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DLPA1000
SLVSDP7A – FEBRUARY 2017 – REVISED MAY 2017
DLPA1000 Power Management and LED Driver IC
1 Features
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1
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– Overcurrent and Undervoltage Protection
49-Ball 0.4-mm Pitch, DSBGA Package
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High-Efficiency RGB LED Driver With Buck-Boost
DC-to-DC Converter and Integrated MOSFETS
Six Low-Impedance ( 100 mV,
otherwise set to 0 (default).
0x05h
SW4
0x02h (9.5x)
Set to 1 if sense voltage is > 200 mV,
otherwise set to 0 (default).
0x06h
SW5
0x02h (9.5x)
Set to 1 if sense voltage is > 200 mV,
otherwise set to 0 (default).
0x07h
SW6
0x02h (9.5x)
Set to 1 if sense voltage is > 200 mV,
otherwise set to 0 (default).
7.3.5 Protection Circuits
DLPA1000 has several protection circuits to protect the IC as well as the system from damage due to excessive
power consumption, die temperature, or over-voltages. These circuits are described below.
7.3.5.1 Thermal Warning (HOT) and Thermal Shutdown (TSD)
DLPA1000 continuously monitors the junction temperature and issues a HOT interrupt if temperature exceeds
the HOT threshold. If the temperature continues to increase above the thermal shutdown threshold, all rails are
disabled and the TSD bit in the INT register is set. Once the temperature drops by 15°C, the output rails are
powered up in sequence and normal operation resumes (DMD_EN bit is not reset by TSD fault).
Thermal shutdown
threshold
Thermal warning
threshold
hysteresis
hysteresis
Temperature
HOT
(internal signal)
TSD
(internal signal)
Available time for controlled
shutdown of System
Figure 8. Definition of the Thermal Shutdown and Hot-Die Temperature Warning
16
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7.3.5.2 Low Battery Warning (BAT_LOW) and Undervoltage Lockout (UVLO)
If the battery voltage drops below the BAT_LOW threshold (typically 3 V) the BAT_LOW interrupt is issued but
normal operation continues. Once the battery drops below the undervoltage threshold (typically 2.3 V) the UVLO
interrupt is issued, all rails are powered down in sequence, the DMD_EN bit is reset, and the part enters
STANDBY mode. The power rails cannot be re-enabled before the input voltage recovers to > 2.4 V. To reenable the rails, the PROJ_ON pin must be toggled.
VINA
hysteresis
BAT_LOW threshold
hysteresis
UVLO threshold
ACTIVE
BAT LOW
(internal signal)
INACTIVE
200 ms
deglitch
UVLO
(internal signal)
ACTIVE
INACTIVE
200 ms
deglitch
Figure 9. Undervoltage Lockout is Asserted When the Input Supply Drops Below the UVLO Threshold
7.3.5.3 DMD Regulator Fault (DMD_FLT)
The DMD regulator is continuously monitored to check if the output rails are in regulation and if the inductor
current increases as expected during a switching cycle. If either one of the output rails drops out of regulation
(e.g. due to a shorted output) or the inductor current does not increase as expected during a switching cycle (due
to a disconnected inductor), the DMD_FLT interrupt bit is set in the INT register, the DMD_EN bit is reset, and
the DMD regulator is shut down. Resetting the DMD_EN bit also causes the LED driver to power down. To
restart the system, the PROJ_ON pin must be toggled.
7.3.5.4 V6V Power-Good (V6V_PGF) Fault
The VLED buck-boost requires the V6V rail for proper operation. The rail is continuously monitored and should
the output drop below the power-good threshold, the V6V_PGF bit is set. The buck-boost is disabled and
attempts to restart automatically.
7.3.5.5 VLED Over-Voltage (VLED_OVP) Fault
If the buck-boost output voltage rises above 6.5 V, the VLED_OVP interrupt is set but the buck-boost regulator is
not turned off. A typical condition to cause this fault is an open LED.
7.3.6 Interrupt Pin (INTZ)
The interrupt pin is used to signal events and fault conditions to the host processor. Whenever a fault or event
occurs in the IC, the corresponding interrupt bit is set in the INT register, and the open-drain output is pulled low.
The INTZ pin is released (returns to HiZ state) and fault bits are cleared when the INT register is read by the
host. However, if a failure persists, the corresponding INT bit remains set and the INTZ pin is pulled low again
after a maximum of 32 µs.
Interrupt events include fault conditions such as power-good faults, over-voltage, over-temperature shut-down,
and under-voltage lock-out.
The MASK register is used to mask events from generating interrupts, i.e. from pulling the INTZ pin low. The
MASK settings affect the INTZ pin only and have no impact on protection and monitor circuits themselves. When
an interrupt is masked, the event causing the interrupt still sets the corresponding bit in the INT register.
However, it does not pull the INTZ pin low.
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Note that persisting fault conditions such as thermal shutdown can cause the INTZ pin to be pulled low for an
extended period of time which can keep the host in a loop trying to resolve the interrupt. If this behavior is not
desired, set the corresponding mask bit after receiving the interrupt and keep polling the INT register to see
when the fault condition has disappeared. After the fault is resolved, unmask the interrupt bit again.
7.3.7 Serial Peripheral Interface (SPI)
DLPA1000 provides a 4-wire SPI port that supports high-speed serial data transfers up to 33.3 MHz. Register
and data buffer write and read operations are supported. The SPI_CSZ input serves as the active low chip select
for the SPI port. The SPI_CSZ input must be forced low in order to write or read registers and data buffers.
When SPI_CSZ is forced high, the data at the SPI_DIN input is ignored, and the SPI_DOUT output is forced to a
high-impedance state. The SPI_DIN input serves as the serial data input for the port; the SPI_DOUT output
serves as the serial data output. The SPI_CLK input serves as the serial data clock for both the input and output
data. Data is latched at the SPI_DIN input on the rising edge of SPI_CLK, while data is clocked out of the
SPI_DOUT output on the falling edge of SPI_CLK. Figure 10 illustrates the SPI port protocol. Byte 0 is referred to
as the command byte, where the most significant bit is the write/not read bit. For the W/nR bit, a 1 indicates a
write operation, while a 0 indicates a read operation. The remaining seven bits of the command byte are the
register address targeted by the write or read operation. The SPI port supports write and read operations for
multiple sequential register addresses through the implementation of an auto-increment mode. As shown in
Figure 10, the auto-increment mode is invoked by simply holding the SPI_CSZ input low for multiple data bytes.
The register address is automatically incremented after each data byte transferred, starting with the address
specified by the command byte. After reaching address 0x7Fh the address pointer jumps back to 0x00h.
Set SPI_CSZ=1 here to write/read one register location
Hold SPI_CSZ=0 to enable auto-increment mode
SPI_CSZ
Header
SPI_DIN
Byte0
Register Data (write)
Byte1
Byte2
Byte3
ByteN
Register Data (read)
SPI_DOUT
Data for A[6:0]
Data for A[6:0]+1
Data for A[6:0]+(N-2)
SPI_CLK
Byte 0
SPI_DIN
W/nR
Byte 1
A6 A5 A4 A3 A2 A1 A0 N7 N6 N5 N4 N3 N2 N1 N0
W/nR
Set high for write, low for read
Register Address
SPI_CLK
Figure 10. SPI Protocol
18
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7.4 Device Functional Modes
Table 4. Modes of Operation
MODE
DESCRIPTION
OFF
This is the lowest-power mode of operation. All power functions are turned off, registers are reset to their default values and
the IC does not respond to SPI commands. RESETZ and PWR_EN pins are pulled low. The IC will enter OFF mode
whenever the PROJ_ON pin is pulled low.
RESET
Logic core and registers are reset to default values, the IC does not respond to SPI commands, RESETZ and PWR_EN pins
are pulled low, but the analog reference system is kept alive. The device enters RESET state when the input voltage drops
below the UVLO threshold.
STANDBY
All power functions are turned off but the IC does respond to the SPI interface. The device enters STANDBY mode when
PROJ_ON pins is high, but DMD_EN bit is set to 0. Also, device enters STANDBY mode when a fault on the DMD regulator
occurs or the temperature increases above thermal shutdown threshold (TSD). (1)
ACTIVE1
The DMD supplies are powered up but LED power (VLED) and the STROBE DECODER are disabled. PROJ_ON pin must
be high, DMD_EN bit must be set to 1, and VLED_EN bit set to 0.
ACTIVE2
DMD supplies, LED power and STROBE DECODER are enabled. PROJ_ON pin must be high and DMD_EN and VLED_EN
bits must both be set to 1.
(1)
DMD_EN power-up default is 1. Once the bit is set to 0, the PROJ_ON pin must be toggled to recover the bit to 1.
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POWER DOWN
Valid power source connected
VRST = OFF &
VBIAS = OFF &
VOFS = OFF &
VLED = OFF &
STROBE DECODER disabled &
SPI interface disabled
PWR_EN is low
RESETZ is low
All registers reset to default values
PROJ_ON = low
ANY STATE
OFF
PROJ_ON = high
VRST = OFF &
VBIAS = OFF &
VOFS = OFF &
VLED = OFF &
STROBE DECODER disabled &
SPI interface disabled
PWR_EN is low
RESETZ is low
All registers reset to default values
PROJ_ON = high &
not UVLO
RESET
STANDBY
DMD_EN = 0(1) ||
FAULT
VRST = OFF &
VBIAS = OFF &
VOFS = OFF &
VLED = OFF &
STROBE DECODER disabled &
SPI interface enabled
PWR_EN is high
RESETZ is high
DMD_EN = 1(1) &
No FAULT
UVLO
VRST = ON &
VBIAS = ON &
VOFS = ON &
VLED = OFF &
STROBE DECODER disabled &
SPI interface enabled
PWR_EN is high
RESETZ is high
ACTIVE1
VLED_EN = 0
VLED_EN = 1
VRST = ON &
VBIAS = ON &
VOFS = ON &
VLED = ON &
STROBE DECODER enabled
SPI interface enabled
PWR_EN is high
RESETZ is high
ACTIVE2
NOTES:
|| = OR, & = AND, () = rising edge, (¯) = falling edge
FAULT = Undervoltage on VRST, VBIAS, VOFS, or DMD regulator current-limit fault (DMD_FLT) ||
Thermal Shut Down (TSD)
DMD_PG and UVLO faults reset the DMD_EN bit and keep the part in STANDBY mode
.
TSD does not reset DMD_EN bit, so part resumes normal operation after the part has cooled off
.
(1) : DMD_EN bit power-up default is 1. The bit can be reset by writing to the ENABLE register but to set
the bit back to1 requires toggling of PROJ_ON
Figure 11. State Diagram
7.5 Programming
7.5.1 Password Protected Registers
Register address 0x11h through 0x27h can be read-accessed the same way as any other register but are
protected against accidental write operations through the PASSWORD register (address 0x10h). To write to a
protected register, first:
• Write data 0xBAh to register address 0x10h, then
• Write data 0xBEh to register address 0x10h.
20
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Programming (continued)
Both writes must be consecutive, i.e. there must be no other read or write operation in between sending the two
bytes. Once the password has been successfully written, register 0x11h through 0x27h are unlocked and can be
write accessed using the regular SPI protocol. They remain unlocked until any byte other than 0xBAh is written to
the PASSWORD register or the part is power cycled.
To check if the registers are unlocked, read back the PASSWORD register. If the data returned is 0x00h, the
registers are locked. If the PASSWORD register returns 0x01h, the registers are unlocked.
7.6 Register Maps
Table 5. Register Address Map
Address
Acronym
Register Name
Section
0x00h
CHIPID
Chip revision register
Go
0x01h
ENABLE
Enable register
Go
0x02h
IREG
Transient-current limit settings
Go
0x03h
SW4MSB
Regulation current MSBs, SW4
Go
0x04h
SW4LSB
Regulation current LSBs, SW4
Go
0x05h
SW5MSB
Regulation current MSBs, SW5
Go
0x06h
SW5LSB
Regulation current LSBs, SW5
Go
0x07h
SW6MSB
Regulation current MSBs, SW6
Go
0x08h
SW6LSB
Regulation current LSBs, SW6
Go
0x09h
RESERVED
Reserved
0x0Ah
AFE
AFE (MUX) control
Go
0x0Bh
BBM
Break before make timing
Go
0x0Ch
INT
Interrupt register
Go
0x0Dh
INT MASK
Interrupt mask register
Go
0x10h
PASSWORD
Password register
Go
0x11h
SYSTEM
System configuration register
Go
0x20h
BYTE0
User EEPROM, Byte0
Go
0x21h
BYTE1
User EEPROM, Byte1
Go
0x22h
BYTE2
User EEPROM, Byte2
Go
0x23h
BYTE3
User EEPROM, Byte3
Go
0x24h
BYTE4
User EEPROM, Byte4
Go
0x25h
BYTE5
User EEPROM, Byte5
Go
0x26h
BYTE6
User EEPROM, Byte6
Go
0x27h
BYTE7
User EEPROM, Byte7
Go
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7.6.1 Chip ID (CHIPID) Register (address = 0x00h) [reset = A6h]
Figure 12. CHIPID Register
7
6
5
4
3
2
1
0
1
DMD_EN
R/W-1h
0
VLED_EN
R/W-1h
CHIPID[7:0]
R-A6h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6. CHIPID Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CHIPID
R
A6h
1010 0000b = DLPA1000 (Rev 1p0)
1010 0010b = DLPA1000 (Rev 1p1)
1010 0110b = DLPA1000 (Rev 1p2)
7.6.2 Enable (ENABLE) Register (address = 0x01h) [reset = 3h]
Figure 13. ENABLE Register
7
6
5
4
3
2
RESERVED
R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7. ENABLE Register Field Descriptions
Bit
Field
Type
Reset
Description
7-2
RESERVED
R
0h
N/A
1h
DMD Regulator enable/status bit
0b = disabled (OFF)
1b = enabled (ON)
NOTE: Power-up default is 1. Once set to 0, the PROJ_ON pin
must be toggled to set the bit back to 1. If bit is set to 0, VLED
buck-boost will automatically be disabled.
1h
VLED Buck-Boost enable bit
0b = disabled (OFF)
1b = enabled (ON)
NOTE: Bit does not reflect current status of VLED buck-boost.
NOTE: If VLED is disabled, RGB Strobe Decoder will automatically
be disabled
1
0
22
DMD_EN
VLED_EN
R/W
R/W
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7.6.3 Switch Transient Current Limit (IREG) Register (address = 0x02h) [reset = 28h]
Figure 14. IREG Register
7
6
5
4
ILIM[2:0]
R/W-5h
RESERVED
R-0h
3
2
SW6LIM_EN
R/W-0h
1
SW5LIM_EN
R/W-0h
0
SW4LIM_EN
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8. IREG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
RESERVED
R
0h
N/A
ILIM[2:0]
R/W
5h
Transient current-limit
000b = 260 mA
001b = 300 mA
010b = 345 mA
011b = 385 mA
100b = 440 mA
101b = 660 mA
110b = 880 mA
111b = 1250 mA
NOTE: Transient current limit should always be set higher than
regulation current
2
SW6LIM_EN
R/W
0h
Transient current-limit enable for SW6
0b = transient current-limit is disabled
1b = transient current-limit is enabled
1
SW5LIM_EN
R/W
0h
Transient current-limit enable for SW5
0b = transient current-limit is disabled
1b = transient current-limit is enabled
0
SW4LIM_EN
R/W
0h
Transient current-limit enable for SW4
0b = transient current-limit is disabled
1b = transient current-limit is enabled
5-3
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7.6.4 SW4 LED DC Regulation Current, MSB (SW4MSB) Register (address = 0x03h) [reset = 0h]
Figure 15. SW4MSB Register
7
6
5
4
3
2
1
RESERVED
R-0h
0
SW4_IDAC[9:8]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9. SW4MSB Register Field Descriptions
Bit
Field
Type
Reset
Description
7-2
RESERVED
R
0h
N/A
1-0
SW4_IDAC[9:8]
R/W
0h
Switch4 DC regulation, most significant byte (MSB)
7.6.5 SW4 LED DC Regulation Current, LSB (SW4LSB) Register (address = 0x04h) [reset = 0h]
Figure 16. SW4LSB Register
7
6
5
4
3
2
1
0
SW4_IDAC[7:0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10. SW4LSB Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
SW4_IDAC[7:0]
R/W
0h
Switch4 DC current limit, least significant byte (MSB)
SW4_IDAC[9:0]
LED
CURRENT (1)
SW4_IDAC[9:0]
LED
CURRENT (1)
SW4_IDAC[9:0]
LED
CURRENT (1)
SW4_IDAC[9:0]
LED
CURRENT (1)
0x000h
0 mA
0x100h
272 mA
0x200h
525 mA
0x300h
777.99 mA
0x001h
19.99 mA
0x101h
272.99 mA
0x201h
525.98 mA
0x301h
778.98 mA
0x002h
20.98 mA
0x102h
273.98 mA
0x202h
526.97 mA
0x302h
779.97 mA
...
...
...
...
...
...
...
...
0x0FEh
270.02 mA
0x1FEh
523.602 mA
0x2FEh
776.02 mA
0x3FEh
1029.01 mA
0x0FFh
271.01 mA
0x1FFh
524.01 mA
0x2FFh
777 mA
0x3FFh
1030 mA
(1)
24
Values shown are for a typical unit at TA = 25°C. Typical step size is 988 µA.
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7.6.6 SW5 LED DC Regulation Current, MSB (SW5MSB) Register (address = 0x05h) [reset = 0h]
Figure 17. SW5MSB Register
7
6
5
4
3
2
1
RESERVED
R-0h
0
SW5_IDAC[9:8]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11. SW5MSB Register Field Descriptions
Bit
Field
Type
Reset
Description
7-2
RESERVED
R
0h
N/A
1-0
SW5_IDAC[9:8]
R/W
0h
Switch5 DC regulation, most significant byte (MSB)
7.6.7 SW5 LED DC Regulation Current, LSB (SW5LSB) Register (address = 0x06h) [reset = 0h]
Figure 18. SW5LSB Register
7
6
5
4
3
2
1
0
SW5_IDAC[7:0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12. SW5LSB Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
SW5_IDAC[7:0]
R/W
0h
Switch5 DC current limit, least significant byte (LSB)
SW5_IDAC[9:0]
LED
CURRENT (1)
SW5_IDAC[9:0]
LED
CURRENT (1)
SW5_IDAC[9:0]
LED
CURRENT (1)
SW5_IDAC[9:0]
LED
CURRENT (1)
0x000h
0 mA
0x100h
272 mA
0x200h
525 mA
0x300h
777.99 mA
0x001h
19.99 mA
0x101h
272.99 mA
0x201h
525.98 mA
0x301h
778.98 mA
0x002h
20.98 mA
0x102h
273.98 mA
0x202h
526.97 mA
0x302h
779.97 mA
...
...
...
...
...
...
...
...
0x0FEh
270.02 mA
0x1FEh
523.602 mA
0x2FEh
776.02 mA
0x3FEh
1029.01 mA
0x0FFh
271.01 mA
0x1FFh
524.01 mA
0x2FFh
777 mA
0x3FFh
1030 mA
(1)
Values shown are for a typical unit at TA = 25°C. Typical step size is 988 µA.
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7.6.8 SW6 LED DC Regulation Current, MSB (SW6MSB) Register (address = 0x07h) [reset = 0h]
Figure 19. SW6MSB Register
7
6
5
4
3
2
1
RESERVED
R-0h
0
SW6_IDAC[9:8]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13. SW6MSB Register Field Descriptions
Bit
Field
Type
Reset
Description
7-2
RESERVED
R
0h
N/A
1-0
SW6_IDAC[9:8]
R/W
0h
Switch6 DC regulation, most significant byte (MSB)
7.6.9 SW6 LED DC Regulation Current, LSB (SW6LSB) Register (address = 0x08h) [reset = 0h]
Figure 20. SW6LSB Register
7
6
5
4
3
2
1
0
SW6_IDAC[7:0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14. SW6LSB Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
SW6_IDAC[7:0]
R/W
0h
Switch6 DC current limit, least significant byte (LSB)
SW6_IDAC[9:0]
LED
CURRENT (1)
SW6_IDAC[9:0]
LED
CURRENT (1)
SW6_IDAC[9:0]
LED
CURRENT (1)
SW6_IDAC[9:0]
LED
CURRENT (1)
0x000h
0 mA
0x100h
272 mA
0x200h
525 mA
0x300h
777.99 mA
0x001h
19.99 mA
0x101h
272.99 mA
0x201h
525.98 mA
0x301h
778.98 mA
0x002h
20.98 mA
0x102h
273.98 mA
0x202h
526.97 mA
0x302h
779.97 mA
...
...
...
...
...
...
...
...
0x0FEh
270.02 mA
0x1FEh
523.602 mA
0x2FEh
776.02 mA
0x3FEh
1029.01 mA
0x0FFh
271.01 mA
0x1FFh
524.01 mA
0x2FFh
777 mA
0x3FFh
1030 mA
(1)
26
Values shown are for a typical unit at TA = 25°C. Typical step size is 988 µA.
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7.6.10 Analog Front End Control (AFE) Register (address = 0x0Ah) [reset = 0h]
Figure 21. AFE Register
7
RESERVED
R-0h
6
AFE_EN
R-0h
5
AFE_CAL_DIS
R/W-0h
4
3
2
1
AFE_SEL[2:0]
R/W-0h
AFE_GAIN[1:0]
R/W-0h
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15. AFE Register Field Descriptions
Bit
Field
Type
Reset
Description
7
RESERVED
R
0h
N/A
6
AFE_EN
R
0h
Enable bit for AFE
0b = AFE is disabled
1b = AFE is enabled
NOTE: Comparator output is in HiZ state when disabled.
0h
Calibration disable bit. Set this bit high to disable the factory
calibration setting. May result in lower offset error if sensed input
voltage level is significantly greater than 40 mV (see Table 3).
0b = Factory calibration setting is enabled
1b = Factory calibration setting is disabled
0h
Gain setting of the programmable gain amplifier
00b = amplifier is off
01b = 1x
10b = 9.5x
11b = 18x
0h
AFE Multiplexer control
000b = SENS2
001b = VLED
010b = VINA
011b = SENS1
100b = RLIM_K
101b = SW4
110b = SW5
111b = SW6
5
AFE_CAL_DIS
4-3
R/W
AFE_GAIN
2-0
R/W
AFE_SEL[2:0]
R/W
7.6.11 Strobe Decode - Break Before Make Timing Control (BBM) Register (address = 0x0Bh) [reset =
0h]
Figure 22. BBM Register
7
6
5
4
3
2
1
0
BBM[7:0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16. BBM Register Field Descriptions
Bit
Field
Type
Reset
Description
Break before make timing. Time between opening one set of switches and closing
the next set. (1)
7-0
(1)
BBM[7:0]
R/W
0h
0x00 = 222 ns
0x01 = 333 ns
0x02 = 444 ns
...
0x3E = 7104 ns
0x3F = 7215 ns
0x40 = 7326 ns
0x41 = 7437 ns
0x42 = 7548 ns
...
0x7E = 14208 ns
0x7F = 14319 ns
0x80 = 14430 ns
0x81 = 14451 ns
0x82 = 14652 ns
...
0xBE = 21312 ns
0xBF = 21423 ns
0xC0 = 21534 s
0xC1 = 21645 ns
0xC2 = 21756 ns
...
0xFE = 28416 ns
0xFF = 28527 ns
It takes 333 ns to 444 ns to turn off the switches from the time a change occurs on LED_SEL[1:0].
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7.6.12 Interrupt (INT) Register (address = 0x0Ch) [reset = X]
Figure 23. INT Register
7
VLED_OVP
R-X
6
V6V_PGF
R-X
5
PROJ_ON
R-X
4
DMD_FLT
R-X
3
UVLO
R-X
2
BAT_LOW
R-X
1
TSD
R-X
0
HOT
R-X
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; X = undefined
Table 17. INT Register Field Descriptions
Bit
Type
Reset
Description
7
VLED_OVP
R
X
VLED BUCK_BOOST over-voltage fault interrupt (normal
operation resumes)
0b = No fault
1b = BUCK-BOOST output is above OVP threshold
6
V6V_PGF
R
X
V6V power-good fault interrupt. (normal operation resumes)
0b = No fault
1b = V6V is not in regulation
5
PROJ_ON
R
X
PROJ_ON interrupt (part enters OFF mode)
0b = PROJ_ON pin is pulled high, normal mode
1b = PROJ_ON pin is pulled low. Alerts the DPP that DMD
regulator is about to shut down.
X
DMD REGULATOR FAULT (part enters STANDBY mode and
DMD_EN bit is cleared)
0b = No fault
1b = The inductor current is not increasing at the correct rate.
Likely to be caused by an open inductor or one of the regulator
outputs has dropped below the power-good threshold. Likely to be
caused by a short.
NOTE: DMD_FLT resets DMD_EN bit to 0.
4
28
Field
DMD_FLT
R
3
UVLO
R
X
Undervoltage lockout threshold (sensed at VINA pin) (part enters
RESET state)
0b = Battery voltage is above the UVLO threshold
1b = Battery voltage has dropped below the UVLO threshold
NOTE: UVLO resets DMD_EN bit to 0. 25ms after UVLO interrupt
part enters RESET state with SPI disabled.
2
BAT_LOW
R
X
Low-Battery warning (sensed at VINA pin) (normal operation
resumes)
0b = Battery voltage is above the low-battery threshold
1b = Battery voltage has dropped below the low-battery threshold
1
TSD
R
X
Thermal Shutdown interrupt (part enters STANDBY mode,
DMD_EN bit is not cleared)
0b = Die temperature is below the thermal shut-down threshold
1b = Die temperature is above thermal shut-down threshold or has
not cooled down enough to recover from TSD
0
HOT
R
X
Thermal warning interrupt (normal operation resumes)
0b = Die temperature is normal operating range
1b = Die temperature is above the HOT threshold or has not
cooled down enough to recover from HOT
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7.6.13 Interrupt Mask (MASK) Register (address = 0x0Dh) [reset = 0h]
Figure 24. MASK Register
7
VLED_OVPM
R/W-0h
6
V6V_PGM
R/W-0h
5
PROJ_ONM
R/W-0h
4
DMD_FLTM
R/W-0h
3
UVLOM
R/W-0h
2
BAT_LOWM
R/W-0h
1
TSDM
R/W-0h
0
HOTM
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18. MASK Register Field Descriptions
Bit
7
6
5
4
Field
VLED_OVPM
V6V_PGM
PROJ_ONM
DMD_FLTM
Type
R/W
R/W
R/W
R/W
Reset
Description
0h
VLED BUCK_BOOST over-voltage fault interrupt mask
0b = interrupt is not masked.
1b = Interrupt is masked. INTZ pin is not pulled low when interrupt
bit is set.
0h
VLED BUCK_BOOST power-good fault interrupt mask
0b = no fault
1b = Interrupt is masked. INTZ pin is not pulled low when interrupt
bit is set.
0h
PROJ_ON interrupt mask
0b = interrupt is not masked.
1b = Interrupt is masked. INTZ pin is not pulled low when interrupt
bit is set.
0h
DMD REGULATOR fault mask
0b = interrupt is not masked.
1b = Interrupt is masked. INTZ pin is not pulled low when interrupt
bit is set.
3
UVLOM
R/W
0h
Undervoltage lockout threshold (sensed at VINA pin) mask
0b = interrupt is not masked.
1b = Interrupt is masked. INTZ pin is not pulled low when interrupt
bit is set.
2
BAT_LOWM
R/W
0h
Low-Battery warning (sensed at VINA pin) mask
0b = interrupt is not masked.
1b = Interrupt is masked. INTZ pin is not pulled low when interrupt
bit is set.
1
TSDM
R/W
0h
Thermal Shutdown interrupt mask
0b = interrupt is not masked.
1b = Interrupt is masked. INTZ pin is not pulled low when interrupt
bit is set.
0
HOTM
R/W
0h
Thermal warning interrupt mask
0b = interrupt is not masked.
1b = Interrupt is masked. INTZ pin is not pulled low when interrupt
bit is set.
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7.6.14 Password (PASSWORD) Register (address = 0x10h) [reset = 0h]
Figure 25. PASSWORD Register
7
6
5
4
3
PASSWORD[7:0]
R/W-0h
2
1
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19. PASSWORD Register Field Descriptions
Bit
Field
7-0
(1)
Type
PASSWORD[7:0]
R/W
Reset
Description (1)
0h
To write-access protected registers write 0xBAh followed by
0xBEh to the register. Both writes need to be consecutive.
To lock protected registers, write 0x00h.
Reading the PASSWORD register returns 0x00h if the protected
registers are locked for write access and 0x01h if they are
unlocked.
Protected registers can be read-accessed without writing to the PASSWORD register.
7.6.15 System Configuration (SYSTEM) Register (address = 0x11h) [reset = 0h]
Figure 26. SYSTEM Register
7
6
5
RESERVED
R-0h
4
3
2
EEPROG
R/W-0h
1
RESERVED
R/W-0h
0
MAP
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20. SYSTEM Register Field Descriptions
30
Bit
Field
Type
Reset
Description
7-3
RESERVED
R
0h
N/A
2
EEPROG
R/W
0h
EEPROM programming bit. When set high, BYTE0 through BYTE7
settings are committed to EEPROM and become new power-up
default values.
To program the EEPROM, set this bit high and back low after 50
ms. Power must not be interrupted during EEPROM programming
to prevent loss of data.
1
RESERVED
R/W
0h
This bit should always be set to 0.
0
MAP
R/W
0h
Switch map selector bit:
0b = Common anode configuration
1b = Cathode-cathode-anode configuration
NOTE: See switch control section for details.
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7.6.16 EEPROM User Register, Byte0 (BYTE0) (address = 0x20h) [reset = 0h]
Figure 27. BYTE0 Register
7
6
5
4
3
2
1
0
BYTE0[7:0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 21. BYTE0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
BYTE0[7:0]
R/W
0h
User programmable EEPROM. See Table 20 for detail on how to
program EEPROM.
7.6.17 EEPROM User Register, Byte1 (BYTE1) (address = 0x21h) [reset = 0h]
Figure 28. BYTE1 Register
7
6
5
4
3
2
1
0
BYTE1[7:0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22. BYTE1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
BYTE1[7:0]
R/W
0h
User programmable EEPROM. See Table 20 for detail on how to
program EEPROM.
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7.6.18 EEPROM User Register, Byte2 (BYTE2) (address = 0x22h) [reset = 0h]
Figure 29. BYTE2 Register
7
6
5
4
3
2
1
0
BYTE2[7:0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23. BYTE2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
BYTE2[7:0]
R/W
0h
User programmable EEPROM. See Table 20 for detail on how to
program EEPROM.
7.6.19 EEPROM User Register, Byte3 (BYTE3) (address = 0x23h) [reset = 0h]
Figure 30. BYTE3 Register
7
6
5
4
3
2
1
0
BYTE3[7:0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 24. BYTE3 Register Field Descriptions
32
Bit
Field
Type
Reset
Description
7-0
BYTE3[7:0]
R/W
0h
User programmable EEPROM. See Table 20 for detail on how to
program EEPROM.
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7.6.20 EEPROM User Register, Byte4 (BYTE4) (address = 0x24h) [reset = 0h]
Figure 31. BYTE4 Register
7
6
5
4
3
2
1
0
BYTE4[7:0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25. BYTE4 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
BYTE4[7:0]
R/W
0h
User programmable EEPROM. See Table 20 for detail on how to
program EEPROM.
7.6.21 EEPROM User Register, Byte5 (BYTE5) (address = 0x25h) [reset = 0h]
Figure 32. BYTE5 Register
7
6
5
4
3
2
1
0
BYTE5[7:0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 26. BYTE5 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
BYTE5[7:0]
R/W
0h
User programmable EEPROM. See Table 20 for detail on how to
program EEPROM.
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7.6.22 EEPROM User Register, Byte6 (BYTE6) (address = 0x26h) [reset = 0h]
Figure 33. BYTE6 Register
7
6
5
4
3
2
1
0
BYTE6[7:0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 27. BYTE6 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
BYTE6[7:0]
R/W
0h
User programmable EEPROM. See Table 20 for detail on how to
program EEPROM.
7.6.23 EEPROM User Register, Byte7 (BYTE7) (address = 0x27h) [reset = 0h]
Figure 34. BYTE7 Register
7
6
5
4
3
2
1
0
BYTE7[7:0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 28. BYTE7 Register Field Descriptions
34
Bit
Field
Type
Reset
Description
7-0
BYTE7[7:0]
R/W
0h
User programmable EEPROM. See Table 20 for detail on how to
program EEPROM.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
A DLPC2607 controller can be used with a DLP2000 DMD to provide a compact, reliable, high-efficiency display
solution for many different video display applications. DMDs are spatial light modulators which reflect incoming
light from an illumination source to one of two directions with the primary direction being into collection optics
within a projection lens. The projection lens sends the light to the destination needed for the application. Each
application is derived primarily from the optical architecture of the system and the format of the pixel data being
input into the DLPC2607.
In display applications using the DLP2000 DMD, the DLPA1000 provides necessary analog functions including
analog power supplies and an RGB LED driver to provide a robust and efficient display solution. Display
applications of interest include pico-projectors embedded in display devices like smart phones, tablets, cameras,
and camcorders. Other applications include wearable (near-eye) displays, battery-powered mobile accessory,
interactive display, low latency gaming displays, and digital signage.
8.2 Typical Application
BAT
Projector Module Electronics
±
+
A common application when using DLPA1000 with DLP2000 DMD and DLPC2607 controller is creating a picoprojector embedded in a handheld product. For example, a pico-projector may be embedded in a smart phone, a
tablet, a camera, or camcorder. The DLPC2607 in the pico-projector embedded module typically receives images
from a host processor within the product as shown in Figure 35. DLPA1000 provides power supply sequencing
and controls the LED currents as required by the application.
L5
2.3 V ± 5.5 V
DC
Supplies
On/Off
Connector
PWR_EN
MIC
SYSPWR
PROJ_ON
LCD
Panel
VDD
L6
RESETZ
FLASH,
SDRAM,
etc.
L2
Flash
INIT_DONE
CLRL
4
GPIO4
Parallel or
BT.656
28
24/16/8
SPI(4)
DLPC2607
DLPA1000
Analog
ASIC
RED
GREEN
BLUE
LED_SEL(2)
BIAS, RST, OFS
3
PWM_IN
RGB
Illumination
Optics
CMP_OUT
DATA
Keypad
L1
INTZ
PROJ_ON
Host
Processor
1.8 V
1V
VLED
PARKZ
RF
I/F
Dual
Reg.
I2C
Thermistor
1.8 V
1V
DDR
VIO
VCORE
CTRL
DATA
nHD/WVGA
WVGA
DDR DMD
GPIO5
DDR
Mobile SDRAM
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Figure 35. Typical Standalone Projector System Block Diagram
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Typical Application (continued)
8.2.1 Design Requirements
A pico-projector is created by using a DLP chipset comprised of a DMD such as the DLP2000, a controller such
as the DLPC2607, and a PMIC/LED driver such as the DLPA1000. The DLPA1000 provides the needed analog
functions for the projector, the DLPC2607 does the digital image processing, and the DMD is the display device
for producing the projected image. In addition to the three critical DLP components, other chips may be needed
for the full system design, such as the battery (SYSPWR), a regulated 1.8-V supply for the controller VIO, and a
regulated 1-V supply for the controller VCORE.
The DLPA1000 provides power to the illumination source for the DMD, typically from red, green, and blue LEDs.
These are often contained in three separate packages, but sometimes more than one color of LED die may be in
the same package to reduce the overall size of the pico-projector. The entire pico-projector can be turned on and
off by using a single signal called PROJ_ON. When PROJ_ON is high, the projector turns on and begins
displaying images. When PROJ_ON is set low, the projector turns off and draws just microamps of current on
SYSPWR. When PROJ_ON is set low, the 1.8-V and 1-V supplies can remain active to be used by other nonprojector sections of the product.
8.2.2 Detailed Design Procedure
The DLPA1000 contains a buck-boost regulator for the LEDs, boost regulators for the DMD rails, and internal
LDOs for logic state control and operation. Each regulator requires a few external components to operate,
referenced by their designators in Figure 36 and Figure 38, and all capacitors should maintain the recommended
values at expected operating temperatures and bias voltages.
36
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Typical Application (continued)
From system power
VINA
TEST
AGND
V2V5
R1
100 k
C2
1 F
C1
2.2 F
AGND1
R2
1k
V6V
From host
C3
100 nF
PWM_IN
C4
1 F
From system power
VINL
To host
VINL
CMP_OUT
From light sensor
SENS1
From temperature sensor
SENS2
C6
1 F
L1
L1
From system power
PGNDL
VINR
C7
10 F
L2
2.2 H
PGNDL
L2
D6
VRST (±10 V)
L2
SWN
REF_VRST
C8
220 nF
VLED
R27
100 k
SWP
VLED
L1
10 H
DLPA1000
VLED
C9
10 F
C10
10 F
PGNDR
SW1
SW2
VBIAS (16 V)
VBIAS
SW3
C11
220 nF
SW4
SW5
VOFS (8.5 V)
VOFS
SW6
C12
220 nF
RLIM
RLIM
RGB LED
Assembly
R34
100 m
VIO
RLIM_K
From host
PROJ_ON
From host
LED_SEL0
From host
LED_SEL1
From host
VSPI
INTZ
R3
100 k
RESETZ
C5
0.1 F
From host
SPI_CSZ
From host
SPI_CLK
From host
SPI_DIN
To host
PWR_EN
SPI_DOUT
DGND
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Figure 36. Schematic
8.2.2.1 VLED Buck-Boost
The VLED buck-boost provides the necessary voltages for the LED array capable of supporting both common
anode and cathode-cathode-anode RGB LEDs. Configurations for both packages are detailed in the RGB Strobe
Decoder section. Alternatively, a design could utilize an optical engine from an OEM that specializes in designing
optics for DLP projectors, which typically integrate the LEDs and DMD into a single module. Current sensing
through the LEDs is accomplished with a high-precision (0.1%) 100-mΩ sense resistor (R34) connecting RLIM to
GND, with a separate trace providing a Kelvin connection to RLIM_K directly from the pad of the sense resistor.
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Typical Application (continued)
The VLED buck-boost utilizes a single 2.2-µH inductor (L2) to generate the voltages for the LED array, bridging
the pins labeled L1 to the pins labeled L2. The buck-boost also requires a 1-µF input bypass capacitor (C6)
connecting VINL to GND, and two 10-µF output filter capacitors (C9 and C10) connecting VLED to GND. Ensure
the inductor can handle the expected operating currents and refer to Calculating Inductor Peak Current to
calculate the expected peak current for a design that can saturate the inductor's core.
8.2.2.1.1 Calculating Inductor Peak Current
To properly configure the DLPA1000 device, a 2.2-µH inductor (L2) must be connected between pins L1 and L2.
The peak current for the inductor in steady state operation can be calculated.
Equation 1 shows how to calculate the peak current I1 in step down mode operation and Equation 2 shows how
to calculate the peak current I2 in boost mode operation. VIN1 is the maximum input voltage VIN2 is the
minimum input voltage, f is the switching frequency (2.25 MHz) and L the inductor value (2.2 µH).
V
(V - V )
I
I1 = OUT + OUT IN 1 OUT
0.8
2 ´ VIN 1 ´ f ´ L
(1)
I2 =
VOUT ´ I OUT VIN 2 (VOUT - VIN 2 )
+
0.8 ´ VIN 2
2 ´ VOUT ´ f ´ L
(2)
The critical current value for selecting the right inductor is the higher value of I1 and I2. It also needs to be taken
into account that load transients and error conditions may cause higher inductor currents. This also needs to be
taken into account when selecting an appropriate inductor. Internally the switching current is limited to 2.2 A.
8.2.2.2 DMD Supplies
The PMIC also utilizes a single inductor (L1) to generate the low-current –10-V, 16-V, and 8.5-V supplies.
Connect the inductor from SWP to SWN, and use a Schottky diode (D6) to generate the –10 V by connecting the
cathode of the diode to the SWN side of the inductor and the anode of the diode to the load (VRST). Place a
220-nF filter cap (C8) from VRST to GND and bridge VRST to the feedback pin (REF_VRST) using a 100-kΩ
resistor (R27). Bypass VINR to GND using a 10-µF capacitor (C7), and ensure VBIAS and VOFS each have
dedicated 220-nF output filter capacitors (C11 and C12).
8.2.2.3 LDOs and Digital Logic
Ensure V2V5 has a 2.2-µF output capacitor (C1), and that V6V has a 100-nF output capacitor (C3). It is critical
that V2V5 externally connects to the TEST pin (R1), otherwise the PMIC will be unable to operate. UVLO for this
device is typically 2.3 V.
8.2.3 Application Curve
Figure 37. Power-Up Sequence: PROJ_ON Asserted
38
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9 Power Supply Recommendations
The DLPA1000 is designed to operate from a 2.3-V to 6-V input voltage supply or battery. To avoid insufficient
supply current due to line drop, ringing due to trace inductance at the VIN terminal, or supply peak current
limitations, additional bulk capacitance may be required. Electrolytic or tantalum type capacitors can dampen
ringing often caused by ceramic input capacitors. The amount of bulk capacitance required should be evaluated
such that the input voltage can remain in specification long enough for a proper fast shutdown to occur for the
VOFS, VRST, and VBIAS supplies. The shutdown begins when the input voltage drops below the programmable
UVLO threshold such as when the external power supply or battery supply is suddenly removed from the system.
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10 Layout
10.1 Layout Guidelines
As for all switching power supplies, the layout is an important step in the design, especially at high peak currents
and high switching frequencies. If the layout is not carefully done, the regulators could show stability problems as
well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground
tracks. Input capacitors, output capacitors, and inductors should be placed as close as possible to the IC.
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SLVSDP7A – FEBRUARY 2017 – REVISED MAY 2017
10.2 Layout Example
Place L2 (VLED)
as close to the IC
as possible. Route
on top level and
avoid vias. Max
current is 2 A.
C6 and C7
should be placed
close to the IC
(supply caps).
Keep traces
separated and
star-connect to
system power.
Place L1 as
close to the IC as
possible. Max
trace current is
200 mA.
Keep trace from
R27 to pin [B6]
shielded from
[A5]-L1 trace as
much as possible
to avoid noise
coupling.
Place C11, and
C12, (VBIAS,
VOFS) close to
the IC. Average
current is
