DLPA200
DLPS015F – APRIL 2010 – REVISED NOVEMBER 2022
DLPA200 DMD Micromirror Driver
1 Features
3 Description
•
The DLPA200 is a DLP® DMD micromirror driver that
generates the micromirror clocking pulses for certain
DMDs in the DLP portfolio. A complete DLP chipset
provides developers easier access to the DMD as well
as high speed micromirror control.
•
•
Generates the micromirror clocking pulses
required by the DLP® Digital Micromirror Device
(DMD)
Generates specialized voltage levels required for
micromirror clocking pulse generation
Designed for use in multiple DLP chipsets
Device Information(1)
2 Applications
PART NUMBER
•
DLPA200
•
•
Display:
– Projectors
– Personal electronics
– Intelligent and adaptive lighting
– Augmented reality and information overlay
Industrial:
– Direct imaging lithography
– Additive manufacturing and 3D printers
– 3D scanners for machine vision and inspection
– Laser marking and repair systems
– Computer-to-plate and industrial printers
Medical:
– Vascular or hyperspectral imaging
– 3D Scanners for ear, teeth, and limb
measurement
– Microscopes
– Ophthalmology
(1)
PACKAGE
HTQFP (80)
BODY SIZE
14.00 mm × 14.00 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
MODE[1:0]
SEL[1:0]
A[3:0]
STROBE
OE
/2
/2
/4
Select, Latch,
Output Logic and
High-Voltage
Output FET
Switches
5-V and
Reference
P12V
/16
OUT(00-15)
V5REG
VBIAS_RAIL
VBIAS_LHI
VBIAS
VBIAS Boost
VBIAS_SWL
VRESET_RAIL
(substrate)
VRESET
Buck-Boost
VRESET_SWL
VRESET
VOFFSET_RAIL
VOFFSET
VOFFSET
Regulator
SCPEN
SCPCK
SCPDI
SCPDO
DEV_ID[1:0]
Serial
Bus
Interface
/2
Power-Up
Initialization
IRQ
Fault Logic
GND
RESET
Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DLPA200
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DLPS015F – APRIL 2010 – REVISED NOVEMBER 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Configurations Table.......................................... 3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 6
7.1 Absolute Maximum Ratings........................................ 6
7.2 ESD Ratings............................................................... 6
7.3 Recommended Operating Conditions.........................6
7.4 Thermal Information....................................................7
7.5 Electrical Characteristics Control Logic...................... 7
7.6 5-V Linear Regulator...................................................8
7.7 Bias Voltage Boost Converter..................................... 8
7.8 Reset Voltage Buck-Boost Converter......................... 9
7.9 VOFFSET/DMDVCC2 Regulator....................................9
7.10 Switching Characteristics........................................10
8 Detailed Description......................................................12
8.1 Overview................................................................... 12
8.2 Functional Block Diagram......................................... 12
8.3 Feature Description...................................................13
9 Application and Implementation.................................. 16
9.1 Application Information............................................. 16
10 Power Supply Recommendations..............................18
10.1 Power Supply Rail Guidelines.................................18
11 Layout........................................................................... 19
11.1 Layout Guidelines................................................... 19
11.2 Thermal Considerations.......................................... 19
12 Device and Documentation Support..........................20
12.1 Device Support....................................................... 20
12.2 Documentation Support.......................................... 20
12.3 Support Resources................................................. 20
12.4 Trademarks............................................................. 20
12.5 Electrostatic Discharge Caution..............................20
12.6 Glossary..................................................................21
13 Mechanical, Packaging, and Orderable
Information.................................................................... 21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (August 2018) to Revision F (November 2022)
Page
• Changed Min/Typ/Max values for switching frequency FSW .............................................................................. 8
Changes from Revision D (May 2015) to Revision E (August 2018)
Page
• Simplified Features section, market update for Applications section..................................................................1
• Added new DLP650LNIR DMD (multiple places)............................................................................................... 3
• Deleted Chipset Configuration Table.................................................................................................................. 3
• Corrected Pin 53 'G' to 'GND' ............................................................................................................................ 3
• Reformatted Absolute Maximum Ratings table ................................................................................................. 6
• Renamed "border mirrors" to "Pond of Mirrors"................................................................................................ 13
• Renamed "serial communication interface" to "Serial Communication Port (SCP)"......................................... 13
• Clarified Pos and Neg as capacitor terminals (multiple) .................................................................................. 16
• Replaced "etch" with "PCB" (multiple).............................................................................................................. 19
• Deleted "or VBB" ............................................................................................................................................. 19
• Removed Discovery D4100 Chipset Datasheet link, Updated datasheet titles ............................................... 20
Changes from Revision C (September 2013) to Revision D (October 2014)
Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................. 1
2
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5 Device Configurations Table
Table 5-1. Device Configurations
DMD
DMD MICROMIRROR DRIVER
DLP9500 DLP 0.95 1080p 2xLVDS Type A DMD
2 ea. DLPA200
DLP7000 DLP 0.7 XGA 2xLVDS Type A DMD
1 ea. DLPA200
DLP650LNIR DLP 0.65 WXGA NIR S450 DMD
1 ea. DLPA200
DLP5500 DLP 0.55 XGA Series 450 DMD
1 ea. DLPA200
DIGITAL CONTROLLER
DLPC410 (+ DLPR410)
DLPC200
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
VBIAS_RAIL
OUT15
VOFFSET_RAIL
OUT14
VRESET_RAIL
VRESET_RAIL
OUT13
VOFFSET_RAIL
OUT12
VBIAS_RAIL
VBIAS_RAIL
OUT11
VOFFSET_RAIL
OUT10
VRESET_RAIL
VRESET_RAIL
OUT09
VOFFSET_RAIL
OUT08
VBIAS_RAIL
6 Pin Configuration and Functions
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
GND
RESET
SCPEN
SCPDI
SCPCK
GND
NC
GND
NC
NC
P12V
VOFFSET
P12V
V5REG
GND
DEV_ID1
DEV_ID0
IRQ
SCPDO
GND
VBIAS_RAIL
OUT00
VOFFSET_RAIL
OUT01
VRESET_RAIL
VRESET_RAIL
OUT02
VOFFSET_RAIL
OUT03
VBIAS_RAIL
VBIAS_RAIL
OUT04
VOFFSET_RAIL
OUT05
VRESET_RAIL
VRESET_RAIL
OUT06
VOFFSET_RAIL
OUT07
VBIAS_RAIL
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
GND
MODE1
MODE0
SEL1
SEL0
OE
GND
VBIAS_SWL
VBIAS
VBIAS_LHI
P12V
VRESET_SWL
VRESET
GND
STROBE
A3
A2
A1
A0
GND
Figure 6-1. PFP Package 80-Pin HTQFP Top View
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Table 6-1. Pin Functions
PIN
NO.
I/O
(INPUT
DEFAULT)(1)
OUT00
22
Output
OUT01
24
Output
OUT02
27
Output
OUT03
29
Output
OUT04
32
Output
OUT05
34
Output
OUT06
37
Output
OUT07
39
Output
OUT08
62
Output
OUT09
64
Output
OUT10
67
Output
OUT11
69
Output
OUT12
72
Output
OUT13
74
Output
OUT14
77
Output
OUT15
79
Output
A0
19
Input (pull down)
A1
18
Input (pull down)
A2
17
Input (pull down)
A3
16
Input (pull down)
MODE0
3
Input (pull down)
MODE1
2
Input (pull down)
SEL0
5
SEL1
4
Input (pull down) Output Voltage Select. Used to switch the voltage applied to the addressed OUTxx
Input (pull down) pin.
STROBE
15
Input (pull down) A rising edge on STROBE latches in the control signals after a tristate delay.
OE
6
Input (pull up)
Asynchronous input controls whether the 16 OUTxx pins are active or are in a in
high-impedance state.
OE = 0 : Enabled. OE = 1 : High Z.
RESET
59
Input (pull up)
Resets the DLPA200 internal logic. Active low. Asynchronous.
SCPEN
58
Input (pull up)
Enables serial bus data transfers. Active low.
SCPDI
57
Input (pull down) Serial bus data input. Clocked in on the falling edge of SCPCK.
SCPCK
56
Input (pull down) Serial bus clock. Provided by chipset controller.
SCPDO
42
Output
Serial bus data output (open drain). Clocked out on the rising edge of SCPCK.
A 1kΩ pull up resistor to the Chip-Set Controller VDD supply is recommended.
IRQ
43
Output
Interrupt request output to the chipset Controller. Active low.
A 1-kΩ pullup resistor to the Chip-Set Controller VDD supply is recommended.
DEV_ID1
45
Input (pull up)
Serial bus device address:
DEV_ID0
44
Input (pull up)
00 = all; 01 = device 1; 10 = device 2; 11 = device 3.
VBIAS
9
Output
VBIAS_LHI
10
Input
Current limiter output for VBIAS supply (also the VBIAS switching inductor input)
VBIAS_SWL
8
Input
Connection point for VBIAS supply switching inductor
VBIAS_RAIL
21, 30, 31,
40, 61, 70,
71, 80
Input
The internally-used VBIAS supply rail. Internally isolated from VBIAS
13
Output
NAME
VRESET
4
DESCRIPTION
16 micromirror clocking waveform outputs (enabled by OE = 0).
Output Address. Used to select which OUTxx pin is active at a given time.
Mode Select. Used to determine the operating mode of the DLPA200.
One of three specialized voltages generated by the DLPA200
One of three specialized voltages which are generated by the DLPA200. The
package thermal pad is tied to this voltage level.
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Table 6-1. Pin Functions (continued)
PIN
NAME
VRESET_SWL
VRESET_RAIL(1)
VOFFSET
NO.
I/O
(INPUT
DEFAULT)(1)
12
Input
Connection point for VRESET supply switching inductor
25, 26, 35,36,
65, 66, 75, 76
Input
The internally-used VRESET supply rail. Internally isolated from VRESET.(1)
DESCRIPTION
49
Output
VOFFSET_RAIL
23, 28, 33,
38, 63, 68,
73, 78
Input
The internally used VOFFSET supply rail. Internally isolated from VOFFSET
GND
1, 7, 14, 20,
41, 46, 53,
55, 60
GND
Common ground
V5REG
47
Output
P12V
11, 48, 50
Input
NC
51, 52, 54
No Connect
(1)
One of three specialized voltages which are generated by the DLPA200
The 5-volt logic supply output
The main power input to the DLPA200
No connect
The exposed thermal pad is internally connected to VRESET_RAIL.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
ELECTRICAL
P12V
Load supply voltage
14
V
VRESET_SWL
Reset supply switching inductor connection
point
(VRESET_SWLVRESET_RAIL )
–1
V
VBIAS_RAIL
Internally-used VBIAS supply rail
(VBIAS_RAILVRESET_RAIL)
60
V
VOFFSET_RAIL
Internally-used VOFFSET supply rail
(VOFFSET_RAILVRESET_RAIL)
40.5
V
VIN
Logic inputs
7
V
VOUT
Open drain logic outputs
7
V
125
°C
0
75
°C
–55
150
°C
ENVIRONMENTAL
TJ(max)
Maximum junction temperature
TA
Operating temperature
Tstg
Storage temperature
(1)
Stresses beyond those listed under Section 7.1 may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under Section 7.3 is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD) (1)
(1)
(2)
(3)
Electrostatic
discharge
Human body model
(HBM)(2)
±2000
Charged device model (CDM)(3)
800
UNIT
V
Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges
in to the device.
JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
at TA = 25°C, P12V = 10.8 V to 13.2 V (unless otherwise noted)(2)
POWER
IP12V1
P12V supply current(1)
MIN
Global shadow at 50 kHz, OUT load = 39 Ω and 390
pF, V5REG = 30 mA, VBIAS = 26 V at 5 mA, VOFFSET =
10V at 30 mA, VRESET = –26 V
TJTSDR
Thermal shutdown temperature
With device temperature rising
Hysteresis
Delta between thermal
shutdown and thermal warning
TJTWR
6
Thermal warning temperature
With device temperature rising
Hysteresis
MAX
200
Outputs disabled and no external loads, VBIAS = 19 V,
VOFFSET = 4.5 V, VRESET = –19 V
IP12V2
(1)
(2)
NOM
UNIT
mA
22
mA
145
160
175
°C
5
10
15
°C
5
10
15
°C
125
140
155
°C
5
10
15
°C
During power up the inrush power supply current can be as high as 1 A for a momentary period of time.
The functional performance of the device specified in this data sheet is achieved when operating the device within the limits defined
by the Recommended Operating Conditions. No level of performance is implied when operating the device above or below the
Recommended Operating Conditions limits.
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7.4 Thermal Information
DLPA200
THERMAL
METRIC(1)
UNIT
PFP (HTQFP)
80 PINS
Thermal resistance,
VBIAS = 26 V, VRESET = -26 V, VOFFSET = 10 V,
Output load = 390 pF and 39R on each output,
Phase by one with global mode,
Channel repetition frequency = 50 kHz,
Additional external loads: IBIAS = 5 mA,
IOFFSET = 30 mA, I5REG = 30 mA
Rc-j
(1)
3
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics Application
Report.
7.5 Electrical Characteristics Control Logic
TA = 25°C, P12V = 10.8 V to 13.2 V (unless otherwise noted)
PARAMETER
VIL
Low-level logic input voltage
VIH
High-level logic input voltage
TEST CONDITIONS
MIN
TYP
MAX
0.8
1.97
UNIT
V
V
IIH
High-level logic input current
VIN = 5 V, input with pulldown. See terminal functions
table.
IIL
Low-level logic input current
VIN = 0 V, input with pullup. See terminal functions
table.
IIH
High-level logic input leakage
current
VIN = 0 V, input with pulldown
–1
1
µA
IIL
Low-level logic input leakage
current
VIN = 5 V, input with pullup
–1
1
µA
VOL
Open drain logic outputs
I = 4 mA
IOL
Logic output leakage current
V = 3.3 V
40
–50
50
–40
µA
µA
0.4
V
1
µA
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7.6 5-V Linear Regulator
TA = 25°C, P12V = 10.8 V to 13.2 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TYP
MAX
4.75
5
5.25
UNIT
V5REG
Output voltage
IIL
Output current: internal logic
4
20
mA
IIE
Output current: external
circuitry
0
30
mA
ICL5
Current limit
VUV5
Undervoltage threshold
VRIP
Output ripple voltage(1)
VOS5
Voltage overshoot at start up
tss
Power up
(1)
Average voltage, IOUT = 4 mA to 50 mA
MIN
80
IOUT = 50 mA
V
mA
V5REG voltage increasing, P12V
= 5.4 V
4.1
V5REG voltage falling, P12V =
5.2 V
3.9
V
200
mVpk-pk
2 %V5REG
Measured between 10 to 90% of V5REG
1
ms
Output ripple voltage relies on suitable external components being selected and good printed circuit board layout practice.
7.7 Bias Voltage Boost Converter
TA = 25°C, P12V = 10.8 V to 13.2 V (unless otherwise noted)
PARAMETER
IRL
Output current: reset outputs
IQL
Output current: quiescent /
drivers
Load = 400 pF, 39 Ω,
repetition frequency = 50 kHz
IDL
Output current: DMD load
ICLFB
Current limit flag
Corresponding current on output at P12V = 10.8 V
ICLB
Current limit
Measured on input
VBIAS
Output voltage
VUVB
VBIAS undervoltage threshold
Bias voltage falling
VUVLHI
VBIAS_LHI undervoltage
threshold
VBIAS_LHI voltage increasing
RDS
Boost switch RDS(on)
TJ = 25°C
VRIP
Output ripple voltage(1)
FSW
Switching frequency
VOSB
Voltage overshoot at start up
tss
Power up
tdis
Discharge current sink
(1)
8
TEST CONDITIONS
Load = 400 pF, 39 Ω,
repetition frequency = 50 kHz
MIN
TYP
0
0
MAX UNIT
18
mA
3
mA
5
mA
30
mA
330
376
460
25.5
26
26.5
50
VBIAS_LHI voltage falling
92
8
V
V
Ω
200
COUT = 3.3 µF, measured between 10 to 90% of
target VBIAS
V
%VBIAS
6.5
2
1.1
mA
1.3
1.5
mVpk-pk
MHz
2
%VBIAS
1
ms
400
mA
Output ripple voltage relies on suitable external components being selected and good printed circuit board layout practice.
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7.8 Reset Voltage Buck-Boost Converter
TA = 25°C, P12V = 10.8 V to 13.2 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IRL
Output current: reset outputs
Load = 400 pF, 39 Ω,
repetition frequency = 50 kHz
IQL
Output current: quiescent / drivers
Load = 400 pF, 39 Ω ,
repetition frequency = 50 kHz
ICLFR
Current limit flag
Corresponding current on output at
P12V = 10.8 V
ICLR
Current limit
Measured on input
VRESET Output voltage
Undervoltage threshold
Reset voltage falling
RDS
Buck-boost switch RDS(on)
TJ = 25°C
VRIP
Output ripple voltage(1)
FSW
Switching frequency
VOSR
Voltage overshoot at start up
tss
Power up
tdis
Discharge current sink
TYP
0
MAX
mA
3
mA
mA
400
800
–26
50
–26.5
mA
V
92 %VRESET
8
1.35
UNIT
18
25
–25.5
VUVR
(1)
MIN
1.5
Ω
200
mVpk-pk
1.65
MHz
2 %VRESET
COUT = 3.3 µF, Measured between 10 to 90% of
target VRESET
1
400
ms
mA
Output ripple voltage relies on suitable external components being selected and good printed circuit board layout practice.
7.9 VOFFSET/DMDVCC2 Regulator
TA = 25°C, P12V = 10.8 V to 13.2 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IRL
Output current: reset
outputs
Load = 400 pF, 39 Ω, repetition frequency = 50 kHz
IQL
Output current: quiescent /
drivers
Load = 400 pF, 39 Ω, repetition frequency = 50 kHz
IDL
Output current: DMDVCC2
ICLO
Current limit
VOFFSET
Output Voltage
VUVO
Undervoltage threshold
VRIP
Output ripple voltage(1)
VOSO
Voltage overshoot at startup
tss
Power up
tdis
Discharge time constant
(1)
MIN
TYP
0
0
MAX
UNIT
12.2
mA
3
mA
30
mA
100
mA
DLP9500, DLP5500, DLP650LNIR
8.25
8.5
8.75
DLP7000
7.25
7.5
7.75
VOFFSET voltage falling
50
V
92 %VOFFSET
100
mVpk-pk
2 %VOFFSET
COUT = 4.7 µF, Measured between 10 to 90% of target
VOFFSET
1
ms
100
μs
Output ripple voltage relies on suitable external components being selected and good printed circuit board layout practice.
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7.10 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
SERIAL COMMUNICATION PORT INTERFACE
A(1)
Setup SCPEN low to SCPCK
Reference to rising edge of SCPCK
B(1)
Byte to byte delay
C(1)
Setup SCPDI to SCPEN high
D(1)
frequency(2)
SCPCK
360
ns
Nominally 1 SCPCK cycle, rising edge to rising edge
1.9
µs
Last byte to slave disable
360
ns
0
SCPCK period
1.9
526
2
kHz
µs
E(1)
SCPCK high or low time
300
ns
F(1)
SCPDI set-up time
Reference to falling edge of SCPCK
300
ns
G(1)
SCPDI hold time
Reference from falling edge of SCPCK
300
H(1)
SCPDO propagation delay
Reference from rising edge of SCPCK
ns
300
SCPEN, SCPCK, SCPDI, RESET
filter (pulse reject)
150
ns
ns
OUTPUT MICROMIRROR CLOCKING PULSES
FPREP
Phased reset repetition frequency
each output pin (non-overlapping)
50
kHz
FGREP
Global reset repetition frequency all
output pins
50
kHz
IRLK
VRESET output leakage current
OE = 1, VRESET_RAIL = -28.5V
-1
-10
µA
IBLK
VBIAS output leakage current
OE = 1, VBIAS_RAIL = 28.5V
1
10
µA
IOLK
VOFFSET output leakage current
OE = 1, VOFFSET_RAIL = 10.25V
1
10
µA
OUTPUT MICROMIRROR CLOCKING PULSE CONTROLS
tSPW
STROBE pulse width
10
ns
tSP
STROBE period
20
ns
tOHZ
Output time to high impedance
OE Pin = High
100
ns
tOEN
Output enable time from high
impedance
OE Pin = Low
100
ns
tSUS
Set-up time
From A[3:0], MODE[1:0], and SEL[1:0] to STROBE edge
8
ns
tHOS
Hold time
From A[3:0], MODE[1:0], and SEL[1:0] to STROBE edge
8
ns
tPBR
From STROBE to VBIAS/VRESET edge 50% point.
80
200
ns
From STROBE to VRESET/VOFFSET edge 50% point.
80
200
ns
tPOB
From STROBE to VOFFSET/VBIAS edge 50% point.
80
200
ns
tDEL
Edge-to-edge propagation delta
Maximum difference between the slowest and fastest
propagation times for any given reset output.
40
ns
tCHCH
Output channel-to-channel
propagation delta
Maximum difference between the slowest and fastest
propagation times for any two outputs for any given edge.
20
ns
tPRO
(1)
(2)
10
Propagation time
See Figure 7-1
There is no minimum speed for the serial port. It can be written to statically for diagnostic purposes.
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SCPEN
D
A
E
B
Clock 1
Byte 1
SCPCK
F
SCPDI
C
E
X
Clock 2
Byte 1
G
F
X
H
Clock 3
Byte 1
Clock 8
Byte 1
Clock 1
Byte 2
G
F
X
X
X
H
Clock 8
Last byte
G
X
H
SCPDO
X = Don’t care
Figure 7-1. Serial Interface Timing
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8 Detailed Description
8.1 Overview
Reliable function and operation of the DLPA200 requires that it be used in conjunction with the other
components of a given DLP chipset. It is typical for the DMD controller to operate the DMD micromirror driver.
For more information on the chipset components, see the appropriate DMD or DMD Controller Data Sheet (Table
12-1).
The DLPA200 consists of three functional blocks: A High-Voltage Power Supply function, a DMD Micromirror
Clock Generation function, and a Serial Communication function.
The High-Voltage Power Supply function generates three specialized voltage levels: VBIAS (19 to 28 V), VRESET
(–19 to –28 V), and VOFFSET (4.5 to 10 V).
The Micromirror Clock Generation function uses the three voltages generated by the High-Voltage Power Supply
function to create the sixteen micromirror clock pluses (output the OUTx pins of the DLPA200).
The Serial Communication function allows the chipset Controller to control the generation of VBIAS, VRESET, and
VOFFSET; control the generation of the micromirror clock pulses; status the general operation of the DLPA200.
8.2 Functional Block Diagram
MODE[1:0]
SEL[1:0]
A[3:0]
STROBE
OE
/2
/2
/4
Select, Latch,
Output Logic and
High-Voltage
Output FET
Switches
/16
5-V and
Reference
P12V
OUT(00-15)
V5REG
VBIAS_RAIL
VBIAS_LHI
VBIAS
VBIAS Boost
VBIAS_SWL
VRESET_RAIL
(substrate)
VRESET
Buck-Boost
VRESET_SWL
VRESET
VOFFSET_RAIL
VOFFSET
VOFFSET
Regulator
SCPEN
SCPCK
SCPDI
SCPDO
DEV_ID[1:0]
Serial
Bus
Interface
/2
Power-Up
Initialization
IRQ
Fault Logic
GND
RESET
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8.3 Feature Description
8.3.1 5-V Linear Regulator
The 5-V linear regulator supplies the 5-V requirement of the DLPA200 internal logic.
Figure 8-1 shows the block diagram of this module. The input decoupling capacitors are shared with other
internal DLPA200 modules. See Section 9.1.1 for recommended component values.
5 V Linear
Regulator
P12V
V5REG
GND
Figure 8-1. 5-Volt Linear Regulator Block Diagram
8.3.2 Bias Voltage Boost Converter
The bias voltage converter is a switching supply that operates at 1.5 MHz. The bias switching device switches
180° out-of-phase with the reset switching device.
The converter supplies the internal bias voltage for the high voltage FET switches and the external VBIAS for
the DMD Pond of Mirrors. The VBIAS voltage level can be different for different generations of DMDs. The VBIAS
voltage level is configured by the DLP Controller chip over the Serial Communication Port (SCP). Four control
bits select the voltage level while a fifth bit is the on/off control. The module provides two status bits to indicate
latched and unlatched status bits for under-voltage (VUV) and current-limit (CL) conditions.
Figure 8-2 shows the block diagram of this module. The input decoupling capacitors are shared with other
internal DLPA200 modules. See Section 9.1.1 for recommended component values.
Inductor
VBIAS_LHI
VBIAS_SWL
P12V
VBIAS
V5REG
BGAP REF
OSC
BIAS
STATUS
Serial Interface
and Control
BIAS
CONTROL
Bias Boost
Converter and
Current Limit
2
4
ENABLE
GND
Figure 8-2. Bias Voltage Boost Converter Block Diagram
8.3.3 Reset Voltage Buck-Boost Converter
The reset voltage buck-boost converter is a switching supply that operates at 1.5 MHz. The reset switching
device switches 180° out-of-phase with the bias switching device.
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The converter supplies the internal reset voltage levels for the high voltage FET switches. The VRESET voltage
level can be different for different generations of DMDs. The VRESET voltage level is configured by the DLP
controller chip over the Serial Communication Port. Four control bits select the voltage level while a fifth bit is the
on/off control. The module provides two status bits to indicate latched and unlatched status bits for under-voltage
(VUV) and current-limit (CL) conditions.
Figure 8-3 shows the block diagram of this module. The input decoupling capacitors are shared with other
internal DLPA200 modules. See Section 9.1.1 for recommended component values.
P12V
SWL
VRESET
V5REG
BGAP REF
OSC
Serial Interface
and Control
RESET
STATUS
Reset Buck-Boost
Converter and
Current Limit
VRESET_SWL
2
RESET
CONTROL
4
Inductor
ENABLE
GND
Figure 8-3. Reset Voltage Buck-Boost Converter Block Diagram
8.3.4 VOFFSET/DMDVCC2 Regulator
The VOFFSET/DMDVCC2 regulator supplies the internal VOFFSET voltage for the high voltage FET switches and
the external DMDVCC2 for the DMD. The VOFFSET voltage level can be different for different generations of
DMDs. The VOFFSET voltage level is configured by the DLP Controller chip over the Serial Communication Port.
Four control bits select the voltage level while a fifth bit is the on/off control. The module provides 2 status bits to
indicate latched and unlatched status bits for under-voltage (VUV) and current-limit (CL) conditions.
Figure 8-4 shows the block diagram of this module. The input decoupling capacitors are shared with other
DLPA200 modules. See Section 9.1.1 for recommended component values.
P12V
VOFFSET
DMDVCC2
V5REG
BGAP REF
VOFFSET Linear
Serial Interface
and Control
OFFSET
STATUS
2
Regulator and
Current Limit
OFFSET
CONTROL
4
ENABLE
GND
Figure 8-4. Offset Voltage Boost Convertor Block Diagram
14
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8.3.5 Serial Communications Port (SCP)
The SCP is a full duplex, synchronous, character-oriented (byte) port that allows exchange of data between the
master ASIC or FPGA, and one or more slave DLPA200s (and/or other DLP devices).
Table 8-1. Serial Communications Port Signal Definitions
SIGNAL
SCPCK
I/O
I
FROM/TO
SCP bus master to slave
TYPE
DESCRIPTION
LVTTL compatible
SCP bus serial transfer clock. The host processor
(master) generates this clock.
SCPEN
I
SCP bus master to slave
LVTTL compatible
SCP bus access enable (low true). When high, slave
will reset to idle state, and SCPDO output will tri-state.
Pulling SCPEN low initiates a read or write access.
SCPEN must remain low for an entire read/write
access, and must be pulled high after the last data
cycle. To abort a read or write cycle, pull SCPEN high
at any point.
SCPDI
I
SCP bus master to slave
LVTTL compatible
SCP bus serial data input. Data bits are valid and
must be clocked in on the falling edge of SCPCK.
SCPDO
O
SCP bus slave to master
IRQ
O
SCP bus slave to master
SCP bus serial data output. Data bits must clocked
LVTTL, open drain w/tri-state out on the rising edge of SCPCK. A 1-kΩ pullup
resistor to the 3.3 volt ASIC supply is required.
LVTTL, open drain
Not part of the SCP bus definition. Asynchronous
interrupt signal from slave to request service from
master. A 1-kΩ pullup resistor to the 3.3-V ASIC
supply is required.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
9.1.1 Component Selection Guidelines
Table 9-1. 5-V Regulator
COMPONENT
VALUE
TYPE OR PART NUMBER
CONNECTION 1
CONNECTION 2
Negative Terminal:
Ground
P12V filter capacitor
10 to 33 µF, 20 VDC,
1Ω max ESR
Tantalum or ceramic
Positive Terminal:
P12V, pin 11
(locate near pin 11)
P12V bypass capacitor
0.1 µF, 50 VDC,
0.1Ω max ESR
Ceramic
P12V, pin 11
(locate near pin 11)
Ground
V5REG filter capacitor
0.1(1) to 1.0 µF, 10 VDC,
2.5Ω max ESR
Tantalum or ceramic
Positive Terminal:
V5REG, pin 47
(locate near pin 47)
Negative Terminal:
Ground
V5REG bypass
capacitor
0.1 µF(1), 16 VDC,
0.1Ω max ESR
Ceramic
V5REG, pin 47
(locate near pin 47)
Ground
(1)
To ensure stability of the linear regulator, use a capacitance with a value not less than 0.1 µF.
Table 9-2. Bias Voltage Boost Converter
COMPONENT
VALUE
TYPE OR PART
NUMBER
CONNECTION 1
CONNECTION 2
LHI filter capacitor
10 µF, 20 VDC,
1-Ω max ESR
Tantalum or ceramic
Positive Terminal:
VBIAS_LHI, pin 10
(locate near pin 10)
Negative Terminal:
Ground
LHI bypass capacitor
0.1 µF, 50 VDC,
0.1-Ω max ESR
Ceramic
VBIAS_LHI, pin 10
(locate near pin 10)
Ground
VBIAS filter capacitor
1 to 10 µF, 35 VDC,
1-Ω max ESR;
(3.3 µF nominal value)
Tantalum or ceramic
Positive Terminal:
VBIAS, pin 9
(locate near pin 9)
Negative Terminal:
Ground
VBIAS bypass capacitor
0.1 µF, 50 VDC,
0.1-Ω max ESR
Ceramic
VBIAS, pin 9
(locate near pin 9)
Ground
VBIAS_RAIL bypass
capacitors (2 required)
0.1 µF, 50 VDC,
0.1Ω max ESR
Ceramic
VBIAS_RAIL, pins 30 and 71
(locate near pins 30 and 71)
Ground
Resistor jumper (optional)
0-Ω normally
(1-Ω for testing(1))
VBIAS, pin 9
VBIAS_RAIL,
pins 21 or 80
Inductor
22 µH, 0.5 A,
160 mΩ ESR
Coil Craft DT1608C-223
(or equivalent)
VBIAS_LHI, pin 10
VBIAS_SWL, pin 8
Schottky diode
0.5 A, 40 V (minimum)
OnSemi MBR0540T1G
or STMicroelectronics
STPS0540Z, STPS0560Z
(or equivalent)
Anode:
VBIAS_SWL, pin 8
Cathode:
VBIAS, pin 9
(1)
16
Allows for VBIAS current measurement.
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Table 9-3. Reset Voltage Boost Converter
COMPONENT
VALUE
TYPE OR PART
NUMBER
CONNECTION 1
CONNECTION 2
VRESET filter capacitor
1 to 10 µF, 35 VDC,
1Ω max ESR;
(3.3 µF nominal value)
Tantalum or ceramic
Negative Terminal:
VRESET, pin 13
(locate near pin 13)
Positive Terminal:
Ground
VRESET bypass capacitor
0.1 µF, 50 VDC,
0.1Ω max ESR
Ceramic
VRESET, pin 13
(locate near pin 13)
Ground
VRESET_RAIL bypass
capacitors (2 required)
0.1 µF, 50 VDC,
0.1Ω max ESR
Ceramic
VRESET_RAIL,
pins 35 and 66
(locate near pins 35 and 66)
Ground
Resistor jumper (optional)
0-Ω normally
(1Ω for testing(1))
VRESET, pin 13
VRESET_RAIL,
pins 25 or 76
Inductor
22 µH, 0.5A,
160 mΩ
Coil Craft DT1608C-223
(or equivalent)
VRESET_SWL, pin 12
Ground
0.5 A (minimum), 60 V
STMicroelectronics
STPS0560Z or Infineon/
International Rectifier
10MQ060N (or equivalent)
Cathode:
VRESET_SWL, pin 12
Anode:
VRESET, pin 13
Schottky diode
(1)
Allows for VRESET current measurement.
Table 9-4. Offset Voltage Regulator
COMPONENT
(1)
(2)
(3)
(4)
VALUE
TYPE OR PART
NUMBER
CONNECTION 1
CONNECTION 2
Tantalum or ceramic
Positive Terminal:
VOFFSET, pin 49
(1st Cap near pin 49)
Positive Terminal:
DMDVCC2 pins
( 2nd Cap at DMD)
Negative Terminal:
Ground at DLPA200
Negative Terminal:
VSS (Ground) at DMD
Ceramic
VOFFSET, pin 49
(locate 1 near pin 49)
DMD DMDVCC2 pins
(locate 4 near DMD pins)
Ground at DLPA200
Ground at DMD
Ceramic
VOFFSET_RAIL,
pins 28 and 73
(locate near pins 28 and
73)
Ground
VOFFSET/VCC2
filter capacitors
(2 required)
1(1) to 4.7(2) µF, 35 VDC,
1Ω max ESR
VOFFSET/VCC2
bypass capacitors
(5 required)
0.1 µF, 50 VDC,
0.1Ω max ESR
VOFFSET_RAIL
bypass capacitor
(2 required)
0.1 µF, 50 VDC,
0.1Ω max ESR
Resistor jumper
(optional)
0-Ω normal
(1Ω for testing(3))
VOFFSET, pin 49
VOFFSET_RAIL,
pins 38 or 63
Resistor jumper
(optional)
0-ohm normal
(1Ω for testing(4))
VOFFSET, pin 49
DMDVCC2 pins
To ensure stability of the linear regulator, the absolute minimum output capacitance must not be less than 1.0 µF.
Recommended value is 3.3 µF each. Different values are acceptable, provided that the sum of the two is 6.8 µF maximum.
Allows for VOFFSET current measurement
Allows for DMDVCC2 current measurement
Table 9-5. Pullup Resistors
COMPONENT
VALUE (kΩ)
TYPE OR PART NUMBER
CONNECTION 1
CONNECTION 2
Resistor
1
SCPDO, pin 42
Chipset controller
3.3-V VDD
Resistor
1
IRQ, pin 43
Chipset Controller
3.3-V VDD
Resistor (optional)
1
OE, pin 6
Chipset Controller
3.3-V VDD
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10 Power Supply Recommendations
10.1 Power Supply Rail Guidelines
Table 9-1 through Table 9-5 provides discrete component selection guidelines.
•
•
•
•
•
•
•
•
•
•
•
Ensure that the P12V filter and bypass capacitors are distributed and connected to pin 11 and pin 48 and pin
50. Place these capacitors as close to their respective pins as possible and if necessary, place on the bottom
layer.
The V5REG filter and bypass capacitors must be placed near and connected to pin 47.
It is best to route the VBIAS_RAIL etch runs in the following order: pin 40, pin 31, pin 30, pin 21, pin 80, pin
71, pin 70, and pin 61. Ensure that the etch runs are short and direct as they must carry 35 ns current spikes
of up to 0.64 A (peak). Locate the bypass capacitors near and connected to pin 30 and pin 71 to provide
bypassing on both sides.
The VBIAS_LHI filter and bypass capacitors must be placed near and connected to pin 10.
The VBIAS filter and bypass capacitors must be placed near and connected to pin 9.
VBIAS pin 9 must also be connected (optionally with a 0-ohm resistor) to VBIAS_RAIL at or between pins 21
and 80.
Route the VRESET_RAIL etch runs in the following order: pin 36, pin 35, pin 26, pin 25, pin 76, pin 75, pin
66, and pin 65. Ensure the etch runs are short and direct as they must carry 35 ns current spikes of up to
0.64 A (peak). Bypass capacitors must be placed near and connected to pins 35 and 66 to provide bypassing
on both sides.
The VRESET filter and bypass capacitors must be located near and connected to pin 13. VRESET pin 13
must also be connected (optionally with a 0-Ω resistor) to VRESET_RAIL at or between pin 25 and pin 76.
Route the VOFFSET_RAIL etch runs in the following order: pin 23, pin 28, pin 33, pin 38, pin 63, pin 68, pin
73, and pin 78. Ensure the etch runs are short and direct as they must carry 35 ns current spikes of up to
0.64 A (peak). Place the bypass capacitors near and connected to pin 28 and pin 73 to provide bypassing on
both sides.
The VOFFSET filter and bypass capacitors must be placed near and connected to pin 49.
VOFFSET pin 49 must also be connected (optionally with a 0-Ω resistor) to VOFFSET_RAIL at or between
pin 38 and pin 63.
Note
Aluminum electrolytic capacitors may not be suitable for the DLPA200 application. At the switching
frequencies used in the DLPA200 (up to 1.5 MHz), aluminum electrolytic capacitors drop significantly
in capacitance and increase in ESR resulting in voltage spikes on the power supply rails, which could
cause the device to shut down or perform in an unreliable manner.
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11 Layout
11.1 Layout Guidelines
CAUTION
Board layout and routing guidelines must be followed explicitly and all external components used
must be in the range of values and of the quality recommended for proper operation of the DLPA200.
CAUTION
Thermal pads must be tied to VRESET_RAIL. Do not connect to ground.
Provide suitable Kelvin connections for the switching regulator feedback pins: VBIAS (pin 9) and VRESET (pin 13).
Make the PCB traces that connect the switching devices: VBIAS_SWL (pin 8) and VRESET_SWL (pin 12) as
short and wide as possible to minimize leakage inductances. Make the PCB traces that connect the switching
converter components (inductors, flywheel diodes and filtering capacitors) as short and wide as possible. Ensure
that the electrical loops that these components form are as small and compact as possible, with the ground
referenced components forming a star connection.
Due to the fast switching transitions appearing on the sixteen reset OUTx pins, it is recommended to keep these
traces as short as possible. Also, to minimize potential cross-talk between outputs, it is advisable to maintain as
much clearance between each of the output traces.
11.1.1 Grounding Guidelines
Ensure that the PWB has an internal ground plane that extends under the DLPA200. All nine ground pins (1, 7,
14, 20, 41, 46, 53, 55, and 60) must be connected to the ground plane using the shortest possible runs and vias.
All filter and bypass capacitors must be placed near the pin being filtered or bypassed for the shortest possible
runs to the part and to the ground plane.
11.2 Thermal Considerations
Thermally bond or solder the DLPA200 package to an external thermal pad on the PWB surface. The
recommended dimensions of the thermal pad are 10 mm × 10 mm centered under the device. The metal bottom
of the package is tied internally to the substrate at the VRESET_RAIL voltage level. Therefore, the thermal pad
on the board must be isolated from any other extraneous circuit or ground and no circuit vias are allowed inside
the pad area. Thermal pads are required on both sides of the PWB. Connect the thermal pads together through
an array of 5 × 5 thermal vias, 0.5 mm in diameter.
Thermal pads and the thermal vias are connected to VRESET_RAIL and must be isolated from ground,
or any other circuit.
Locate an internal P12V plane directly underneath the top layer and have an isolated area under the DLPA200.
This isolated area must be a minimum of 20 cm2 and connect to the thermal pad of the DLPA200 through the
thermal vias. The potential of the isolated area will also be at VRESET_RAIL. The internal ground plane must
extend under the DLPA200 to help carry the heat away. Please refer to the PowerPAD Thermally Enhanced
Package application report (SLMA002) for details on thermally efficient package design considerations.
Be careful to place the DLPA200 device away from local PWB hotspots. Heat generated from adjacent
components may impact the DLPA200 thermal characteristics.
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Device Nomenclature
The device marking consists of the fields shown in Figure 12-1.
Figure 12-1. Device Marking (Device Top View)
DLPA200PFP is functionally equivalent to 2506593-0005N.
12.2 Documentation Support
12.2.1 Related Documentation
Table 12-1. Links to Related Documentation
Document
TI Literature Number
DLP5500 DLP 0.55 XGA Series 450 DMD Data Sheet
DLPS013
DLPC200 DLP Digital Controller Data Sheet
DLPS014
DLP9500 DLP 0.95 1080p 2x LVDS Type A DMD Data Sheet
DLPS025
DLP7000 DLP 0.7 XGA 2x LVDS Type A DMD Data Sheet
DLPS026
DLP650LNIR 0.65 NIR WXGA S450 DMD Data Sheet
DLPS136
DLPC410 DMD Digital Controller Data Sheet
DLPS024
PowerPAD™ Thermally Enhanced Package Application Report
SLMA002
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
DLP® is a registered trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
20
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12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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24-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
Samples
(4/5)
(6)
DLPA200PFP
ACTIVE
HTQFP
PFP
80
5
TBD
Call TI
Call TI
0 to 75
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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