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DLPC2607
DLPS030E – DECEMBER 2013 – REVISED MARCH 2019
DLPC2607 Low-power DLP® Display Controller
1 Features
•
1
•
•
•
•
•
•
1
Supports Reliable Operation of the 0.2-nHD,
0.24-VGA, and 0.3-WVGA DMDs
Multi-Mode, 24-Bit Input Pixel Interfaces:
– Supports Parallel or BT656 Bus Protocol
– Supports Input Sizes from QVGA Through
WVGA
– Supports 1- to 60-Hz Frame Rates
– Supports Pixel Clock up to 33.5 MHz
– Supports Landscape and Portrait Orientations
– Support 8-, 16-, 18-, and 24-Bit Bus Options
– Supports 3 Input Color Bit-Depth Options:
– RGB888, YCrCb888
– RGB666, YCrCb666
– RGB565, 4:2:2 YCrCb
Pixel Data Processing:
– Image Resizing (Scaling)
– Frame Rate Conversion
– Color Coordinate Adjustment
– Automatic Gain Control
– Programmable Degamma
– Spatial-Temporal Multiplexing (Dithering)
– Video Processing Support:
– Color Space Conversion
– 4:2:2 to 4:4:4 Chroma Interpolation
– Field Scaled De-Interlacing
Packaged in a 176-Pin, 0.4-mm Pitch, VFBGA
External Memory Support:
– 166-MHz Mobile DDR SDRAM
– 33.3-MHz Serial Flash
WVGA, VGA, and nHD DMD Display Support
– DMD Bit-Plane Generation and Formatting
– Programmable Bit-Plane Display Sequencer
(Controls the LED Enables and DMD Loading)
– 76.2-MHz Double Data Rate (DDR) DMD I/F
– Pulse-Width Modulation (PWM) for Mirrors:
– Auto DMD Parking at Power-Down
– 24-Bit Bit-Depth on DMD
System Control:
– I2C Control of Device Configuration
– Programmable Splash Screens
– Programmable LED Current Control
– DMD Power and Mirror Driver Control
– DMD Horizontal and Vertical Display Image
•
Flip
– Display Image Rotation
– Flash-Based Configuration Batch Files
– I/F Sleep Still Image Power Savings Mode
Test Support:
– Built-In Test Pattern Generation
– JTAG With Boundary Scan Test Support
2 Applications
•
•
•
•
Embedded Mobile Projection
– Smartphone
– Tablet
– Camera
– Laptop
Mobile Accessories
Wearable (Near-Eye) Displays
Battery-Operated Projectors
3 Description
The DLPC2607 is a low power DLP™ digital
controller for battery powered display applications.
The controller supports reliable operation of 0.3WVGA, 0.24-VGA and 0.2-nHD DMDs. The
DLPC2607 controller provides a convenient, multifunctional interface between system electronics and
the DMD, enabling small form factor and low power
displays.
Device Information(1)
PART NUMBER
DLPC2607
PACKAGE
VFBGA (176)
BODY SIZE (NOM)
7.00 mm × 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DLPC2607
DLPS030E – DECEMBER 2013 – REVISED MARCH 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
Features .................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions ......................... 5
Specifications....................................................... 12
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
Absolute Maximum Ratings .................................... 12
ESD Ratings............................................................ 12
Recommended Operating Conditions..................... 12
Thermal Information ................................................ 13
Typical Current and Power Dissipation................... 13
I/O Characteristics................................................... 14
Internal Pullup and Pulldown Characteristics ........ 14
Parallel I/F Frame Timing Requirements ................ 15
Parallel I/F General Timing Requirements.............. 15
Parallel I/F Maximum Parallel Interface Horizontal
Line Rate.................................................................. 16
6.11 BT.656 I/F General Timing Requirements ............ 17
6.12 100- to 120-Hz Operational Limitations ................ 17
6.13 Flash Interface Timing Requirements .................. 18
6.14 DMD Interface Timing Requirements ................... 18
6.15 mDDR Memory Interface Timing Requirements .. 19
7
7.2 Functional Block Diagram ....................................... 23
7.3 Feature Description................................................. 23
7.4 Programming........................................................... 25
8
Application and Implementation ........................ 27
8.1 Application Information............................................ 27
8.2 Typical Application ................................................. 27
9
Power Supply Recommendations...................... 32
9.1
9.2
9.3
9.4
9.5
System Power Considerations................................ 32
System Power-Up and Power-Down Sequence ..... 32
System Power I/O State Considerations ............... 34
Power-Up Initialization Sequence ........................... 34
Power-Good (PARK) Support ................................ 35
10 Layout................................................................... 36
10.1 Layout Guidelines ................................................. 36
10.2 Layout Example .................................................... 42
11 Device and Documentation Support ................. 43
11.1
11.2
11.3
11.4
11.5
Device Support......................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
43
44
44
44
44
Detailed Description ............................................ 23
12 Mechanical, Packaging, and Orderable
Information ........................................................... 44
7.1 Overview ................................................................. 23
12.1 Package Option Addendum .................................. 45
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (May 2017) to Revision E
Page
•
Changed Changed title from "DLPC2607 DLP PICO Processor 2607 ASIC" to "DLPC2607 Low-power DLP® Display
Controller" .............................................................................................................................................................................. 1
•
Added ZVB Package Bottom View ........................................................................................................................................ 5
•
Changed to "Add external pullup or pulldown resistors as needed to these signals to avoid floating inputs" ...................... 5
•
Changed PAD1000 to DLPA1000 .......................................................................................................................................... 5
•
Changed to "Establish this setting" ....................................................................................................................................... 5
•
Changed "low a minimum" to "low to a minimum" ................................................................................................................ 5
•
Changed "Should be pulled up to" to "Pull up to" .................................................................................................................. 5
•
Changed "Unused inputs should be pulled down" to "Pull unused inputs" ........................................................................... 6
•
Added DMD INTERFACE pin descriptions ........................................................................................................................... 7
•
Added SDRAM INTERFACE pin descriptions ....................................................................................................................... 8
•
Changed "It should be connected" to "Connect". .................................................................................................................. 9
•
Changed globally "Should be left open or unconnected for typical use." to "Leave open or unconnected for typical
use." ..................................................................................................................................................................................... 10
•
Changed globally "An external pullup should not be applied to this pin..." to "Do not apply an external pullup to this
pin..."..................................................................................................................................................................................... 10
•
Swapped all values under IOH and IOL ................................................................................................................................. 14
•
Changed "that should be applied" to "can safely be applied" ............................................................................................. 14
•
Changed "that should be applied" to "can safely be applied" ............................................................................................. 14
•
Changed "OHand OL" to VOH and VOL to clarify meaning .................................................................................................... 14
•
Changed "VCCIO =" to "VCCIO (V)" ................................................................................................................................... 14
2
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DLPS030E – DECEMBER 2013 – REVISED MARCH 2019
Revision History (continued)
•
Changed "MAX Supported" to "Maximum Parallel Interface" .............................................................................................. 16
•
Changed Changed "BT.565" to "BT.656" ............................................................................................................................ 17
•
Added link to ITU-R BT.656 specification ............................................................................................................................ 17
•
Changed "NOTE:" to "The table below" ............................................................................................................................... 17
•
Deleted "Note that" ............................................................................................................................................................... 17
•
Changed fclock min................................................................................................................................................................. 18
•
Changed tp_clkper min and max .............................................................................................................................................. 18
•
Changed "should support" to "supports" ............................................................................................................................. 25
•
Changed "Thus, those pins should be tied" to "Tie these pins" .......................................................................................... 26
•
Changed "1.8-, 2.5-, or 3.3-V" to "1.8 V, 2.5 V, or 3.3 V" .................................................................................................... 26
•
Changed "the ASIC only supports periodic sources" to "the ASIC supports periodic sources only" .................................. 27
•
Changed "multi media" to "multimedia" ............................................................................................................................... 27
•
Changed Device Functional Modes to System Functional Modes and moved to correct position ..................................... 27
•
Added Reference to TSTPT_6 for Crystal nominal frequency ............................................................................................. 28
•
Changed "ASIC, and the PLL_REFCLK_O pins hould be left unconnected" to "ASIC. Leave the PLL_REFCLK_O
pins unconnected" ............................................................................................................................................................... 29
•
Changed "The benefit of an oscillator is that it can be made to provide a spread-spectrum clock that reduces EMI."
to "An oscillator that provides a spread-spectrum clock reduces EMI." ............................................................................... 29
•
Changed "can only accept" to "accepts" ............................................................................................................................. 29
•
Added kHz ........................................................................................................................................................................... 29
•
Changed several items in Table 7 ....................................................................................................................................... 29
•
Changed " the ODM’s own risk" to "the risk of the ODM" ................................................................................................... 29
•
Changed " Layout guidelines should be followed" to "Follow the layout guidelines" .......................................................... 29
•
Changed "To complete DLP system . . . is requiered" to "The DLP system requires" ........................................................ 29
•
Changed "The optical engine that has the LED packages and the DMD mounted to it is typically supplied by an
optical OEM who specializes in designing optics for DLP projectors." to "An optical OEM that specializes in
designing optics for DLP projectors typically supplies the optical engine that has the LED packages and the DMD
mounted to it." ...................................................................................................................................................................... 29
•
Deleted "Note that" .............................................................................................................................................................. 30
•
Changed "this allows these inputs to be driven high" to "This protection allows the device to drive these inputs high" ..... 30
•
Changed .............................................................................................................................................................................. 30
•
Changed "All I/O power should remain" to "Ensure that all I/O power remains" ................................................................. 32
•
Changed "is defined" to "operates as" ................................................................................................................................ 35
•
Changed "should alert" to "alerts" ........................................................................................................................................ 35
•
Changed "Note that the reference clock should continue to run and RESET should remain" to "The reference clock
continues to run. RESET remains" ...................................................................................................................................... 35
•
Changed "At a minimum, VDD_PLL power and VSS_PLL ground pins should be isolated" to "Isolate VDD_PLL
power and VSS_PLL ground pins" ...................................................................................................................................... 36
•
Changed "It is important that the quiet ground and power are treated like analog signals" to "The ground and power
domains are analog signals, and should be treated as such to achieve minimum noise." .................................................. 36
•
Changed "The power and ground traces should be as short as possible" to "Ensure that the power and ground
traces are as short as possible" ........................................................................................................................................... 36
•
Changed "and should not be expected" to "so do not expect them" ................................................................................... 37
•
Changed "they should be" to "ensure they are" .................................................................................................................. 37
•
Changed "should be split" to "Split the" ............................................................................................................................... 37
•
Changed "In addition, the SPICLK trace . . . should be" to "Make the SPICLK trace" ........................................................ 37
•
Changed "should be split" to "Split the" ............................................................................................................................... 37
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DLPC2607
DLPS030E – DECEMBER 2013 – REVISED MARCH 2019
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Revision History (continued)
•
Changed "In addition, the SPIDOUT trace . . . should be" to "Make the SPIDOUT trace" .................................................. 37
•
Changed "The SPIDIN .... should be split" to "Make the SPDIN" ....................................................................................... 37
•
Changed "on their way back" to "on the return" .................................................................................................................. 37
•
Changed "They should then share" to "Make sure they share" .......................................................................................... 37
•
Changed "Variation from these recommendations may also work, but should be confirmed with PCB signal integrity
analysis or lab measurements" to "Make sure to confirm any variation from these recommendations with PCB signal
integrity analysis or lab measurements" .............................................................................................................................. 37
•
Changed PCB Design table to itemized list ........................................................................................................................ 38
•
Changed "should take" to "takes" ........................................................................................................................................ 40
•
Changed "should take" to "takes" ........................................................................................................................................ 40
•
Changed "should" to "must" ................................................................................................................................................ 40
•
Changed "The pair should also be terminated" to "Terminate the pair" .............................................................................. 41
•
Changed "Specifically ... should be terminated" to "Terminate" .......................................................................................... 41
•
Changed "Specifically ... should be terminated" to "Terminate" .......................................................................................... 41
•
Changed "kept" to "maintained to a length of" .................................................................................................................... 41
•
Changed "should" to "does" ................................................................................................................................................ 41
Changes from Revision C (November 2015) to Revision D
Page
•
Removed table 'Compatible SPI Serial Flash Devices' from Serial Flash Interface since listed devices are end of life.
Replaced with new suggested devices as well as Table 4 which lists minimum performance specifications to
determine flash device compatibility..................................................................................................................................... 26
•
Added MSL Peak Temp to Packaging Information ............................................................................................................. 45
Changes from Revision B (January 2014) to Revision C
•
Added ESD Ratings table, Thermal Information table, Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section ..................................... 1
Changes from Revision A (December 2013) to Revision B
•
Page
Page
Removed product preview banner.......................................................................................................................................... 1
Changes from Original (December 2013) to Revision A
Page
•
Corrected columns for IOH and IOL in I/O Characteristics ..................................................................................................... 14
•
Updated B38 I/O Type value for VOH (min) in I/O Characteristics ....................................................................................... 14
•
Added additional table notes to I/O Characteristics ............................................................................................................ 14
•
Added table note to Internal Pullup and Pulldown Characteristics ...................................................................................... 14
•
Corrected device reference to DLPC2607 in the notes for mDDR Memory Interface Timing Requirements ..................... 19
4
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DLPS030E – DECEMBER 2013 – REVISED MARCH 2019
5 Pin Configuration and Functions
ZVB Package
176-Pin NFBGA
Bottom View
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Pin Functions
PIN
I/O
(1)
CLOCK SYSTEM
DESCRIPTION
I1
Async
DLPC2607 power-on reset. Self-configuration starts when a low-to-high
transition is detected on this pin. All ASIC power and clocks must be stable
before this reset is de-asserted (hysteresis buffer). Note that the following
seven signals tri-state while RESET is asserted: DMD_PWR_EN,
LEDDVR_ON, LED_SEL_0,LED_SEL_1, SPICLK, SPIDOUT, SPICSZ0
Add external pullup or pulldown resistors as needed to these signals to avoid
floating inputs.
I4
N/A
Reference clock crystal input. If an external oscillator is used in place of a
crystal, then use this pin as the oscillator Input.
J15
O14
N/A
Reference clock crystal return. If an external oscillator is used in place of a
crystal, then leave this pin unconnected (floating).
SPICLK
A4
O24
N/A
Clock for the external SPI device or devices
SPIDIN
B4
I2
SPICLK
Serial data input from the external SPI device or devices
SPICSZ0
A5
O24
SPICLK
Chip select 0 output for the external SPI flash device. Active low
SPICSZ1
C6
O24
SPICLK
Chip select 1 output for the external SPI DLPA1000 device. Active low
SPIDOUT
C5
O24
SPICLK
Serial data output to the external SPI device or devices. This pin sends
address and control information as well as data when programming
NAME
NO.
POWER
TYPE
DEVICE INITIALIZATION AND REFERENCE CLOCK (1)
RESETZ
J14
PLL_REFCLK_I
K15
VCC18
VCC18 (filter)
PLL_REFCLK_O
FLASH INTERFACE (2)
VCC_ FLSH
MAIN VIDEO DATA AND CONTROL
PARK
B8
VCC_ INTF
I3
Async
DMD park control (active low) is set high to enable typical operation.
Establish this setting prior to releasing RESET, or within 500 µs after
releasing RESET. It should be set low to a minimum of 500 µs before any
power is to be removed from the DLPC2607 (hysteresis buffer).
LED_ENABLE
A11
VCC_ INTF
I3
Async
LED enable (active high input). A logic low on this signal forces
LEDDRV_ON low and LED_SEL(1:0) = b00. These signals are enabled 100
ms after LED_ENABLE transitions from low to high (hysteresis buffer).
DBIC_CSZ
B10
VCC_ INTF
I3
SCL
Unused/reserved: Pull up to VCC_INTF.
SCL
A10
VCC_ INTF
B38
N/A
I2C clock (hysteresis buffer) bidirectional, open-drain signal. An external
pullup is required. No I2C activity is permitted for a minimum of 100 ms after
PARK and RESET are set high.
SDA
C10
VCC_ INTF
B38
SCL
I2C data (hysteresis buffer) bidirectional, open-drain signal. An external
pullup is required.
(1)
(2)
Each device connected to the serial peripheral interface (SPI) bus must be operated off VCC_FLSH
Each device connected to the SPI bus must be operated off VCC_FLSH
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Pin Functions
PIN
NAME
I/O
NO.
POWER
TYPE
(1)
(continued)
CLOCK SYSTEM
DESCRIPTION
GPIO4_INTF
C9
VCC_ INTF
B34
Async
General purpose I/O 4 (hysteresis buffer). Primary usage is to indicate when
auto-initialization is complete (also referred to as INIT-DONE, which is when
GPIO4 transitions high then low following release of RESET) and to flag a
detected error condition in the form of a logic high, pulsed Interrupt flag
subsequent to INIT-DONE.
GPIO5_INTF
B9
VCC_ INTF
B34
Async
General purpose I/O 5 (hysteresis buffer). For applications that use focus
motor control with a sensor, this pin is an input that is connected to the motor
position sensor. For applications that use non-focus motor control with a
sensor, configure this pin with an output at logic 0 and left unconnected.
MAIN VIDEO DATA AND CONTROL
PARALLEL RGB MODE
BT.656 I/F MODE
D13
VCC_ INTF
I3
N/A
PDM_CVS_TE
H15
VCC_ INTF
B34
ASYNC
Parallel data mask
VSYNC_WE
H14
VCC_ INTF
I3
ASYNC
Vsync
(6)
HSYNC_CS
H13
VCC_ INTF
I3
PCLK
Hsync
(6)
DATEN_CMD
G15
VCC_ INTF
I3
PCLK
Data valid
PDATA[0]
G14
VCC_ INTF
I3
PCLK
Data
(7)
Data0
(7)
PDATA[1]
G13
VCC_ INTF
I3
PCLK
Data
(7)
Data1
(7)
Data
(7)
Data2
(7)
Data
(7)
Data3
(7)
Data
(7)
Data4
(7)
Data
(7)
Data5
(7)
Data
(7)
Data6
(7)
Data
(7)
Data7
(7)
Data
(7)
Unused
(5)
Data
(7)
Unused
(5)
Data
(7)
Unused
(5)
Data
(7)
Unused
(5)
Data
(7)
Unused
(5)
Data
(7)
Unused
(5)
Data
(7)
Unused
(5)
Unused
(5)
PDATA[2]
PDATA[3]
PDATA[4]
PDATA[5]
PDATA[6]
PDATA[7]
PDATA[8]
PDATA[9]
PDATA[10]
PDATA[11]
PDATA[12]
PDATA[13]
PDATA[14]
F15
F14
F13
E15
E14
E13
D15
D14
C15
C14
C13
B15
B14
VCC_ INTF
VCC_ INTF
VCC_ INTF
VCC_ INTF
VCC_ INTF
VCC_ INTF
VCC_ INTF
VCC_ INTF
VCC_ INTF
VCC_ INTF
VCC_ INTF
VCC_ INTF
VCC_ INTF
I3
I3
I3
I3
I3
I3
I3
I3
I3
I3
I3
I3
I3
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
Pixel clock
(3)
PCLK (Hysteresis)
Pixel clock
(4)
Unused
(5)
Unused (5)
(6)
Unused
(5)
Unused
(5)
PDATA[15]
A15
VCC_ INTF
I3
PCLK
Data
(7)
PDATA[16]
A14
VCC_ INTF
I3
PCLK
Data
(7)
Unused
(5)
PDATA[17]
B13
VCC_ INTF
I3
PCLK
Data
(7)
Unused
(5)
PDATA[18]
A13
VCC_ INTF
I3
PCLK
Data
(7)
Unused
(5)
PDATA[19]
C12
VCC_ INTF
I3
PCLK
Data
(7)
Unused
(5)
PDATA[20]
B12
VCC_ INTF
I3
PCLK
Data
(7)
Unused
(5)
PDATA[21]
A12
VCC_ INTF
I3
PCLK
Data
(7)
Unused
Unused
Unused
PDATA[22]
C11
VCC_ INTF
I3
PCLK
Data
(7)
PDATA[23]
B11
VCC_ INTF
I3
PCLK
Data
(7)
(3)
(4)
(5)
(6)
(7)
6
(3)
(5)
(5)
(5)
Pixel clock capture edge is software programmable.
Data mask is optional for parallel bus operation. If unused, pull to ground through a resistor.
Pull unused inputs to ground through an external resistor.
VSYNC, HSYNC, and data valid polarity is software programmable.
PDATA(23:0) bus mapping is pixel format and source mode dependent.
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DLPS030E – DECEMBER 2013 – REVISED MARCH 2019
Pin Functions
PIN
NAME
I/O
NO.
POWER
TYPE
(1)
(continued)
CLOCK SYSTEM
DESCRIPTION
DMD_DCLK
DMD Data Pins. DMD Data pins are double data rate (DDR) signals that are
clocked on both edges of DMD_DCLK.
All 15 DMD data signals are use to interface to the WVGA and VGA DMDs;
however, only 12 of the 15 are used to interface to an nHD DMD.
The standard nHD interconnect is to utilize pins DMD_D(11:0). However,
DMD_D(14:3) must be used to interface to the nHD DMD when the I2C
programmable option to reverse the bit-order of the DMD interface pins is
selected (DMD Bus Swap Control, I2C: 0xA7).
DMD INTERFACE
DMD_D0
M15
DMD_D1
N14
DMD_D2
M14
DMD_D3
N15
DMD_D4
P13
DMD_D5
P14
DMD_D6
P15
DMD_D7
R15
DMD_D8
R12
DMD_D9
N11
DMD_D10
P11
DMD_D11
R11
DMD_D12
N10
DMD_D13
P10
DMD_D14
R10
DMD_DCLK
N13
N/A
DMD_LOADB
R13
DMD_DCLK
DMD Data Load Signal (active low). This signal requires an external pullup to
VCC18.
DMD_SCTRL
R14
DMD_DCLK
DMD Data Serial Control Signal
DMD_TRC
P12
DMD_DCLK
DMD Data Toggle Rate Control
DMD_DAD_BUS
L13
DMD_SAC_CLK
DMD DAD Bus Data
DMD_DAD_STRB
K13
DMD_SAC_CLK
DMD DAD Bus Strobe
DMD_DAD_OEZ
M13
Async
DMD_SAC_BUS
L15
DMD_SAC_CLK
DMD SAC Bus Data
DMD_SAC_CLK
L14
N/A
DMD SAC Bus Clock
VCC18
O58
DMD Data Clock (DDR)
DMD Reset Driver Output Enable (active low). To properly park the DMD,
this signal requires a 30-kΩ to 100-kΩ external pullup resistor connected to
VCC18.
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Pin Functions
PIN
NAME
I/O
NO.
POWER
TYPE
(1)
(continued)
CLOCK SYSTEM
DESCRIPTION
SDRAM INTERFACE
MEM0_CLK_P
D1
O74
MEM0_CLK_N
E1
O74
MEM0_A0
P1
MEM0_A1
R3
MEM0_A2
R1
MEM0_A3
R2
MEM0_A4
A1
MEM0_A5
B1
MEM0_A6
A2
MEM0_A7
B2
MEM0_A8
D2
MEM0_A9
A3
MEM0_A10
P2
MEM0_A11
B3
MEM0_A12
D3
MEM0_BA0
M3
MEM0_BA1
P3
N/A
mDDR memory, Differential Memory Clock
mDDR memory, Multiplexed Row, and Column Address
O64
MEM_CLK
mDDR memory, Bank Select
MEM0_RASZ
P4
mDDR memory, Row Address Strobe (active low)
MEM0_CASZ
R4
mDDR memory, Column Address Strobe (active low)
MEM0_WEZ
R5
mDDR memory, Write Enable (active low)
MEM0_CSZ
J3
MEM0_CKE
C1
MEM0_LDQS
J2
B64
N/A
mDDR memory, Lower Byte, R/W Data Strobe
MEM0_LDM
J1
O64
MEM0_LDQS
mDDR memory, Lower Byte, Write Data Mask
MEM0_DQ0
N1
MEM0_DQ1
M2
MEM0_DQ2
M1
MEM0_DQ3
L3
MEM0_DQ4
L2
B64
MEM0_LDQS
mDDR memory, Lower Byte, Bidirectional R/W Data
MEM0_DQ5
K2
mDDR memory, Chip Select (active low)
VCC18
mDDR memory, Clock Enable (active high)
MEM0_DQ6
L1
MEM0_DQ7
K1
MEM0_UDQS
G1
B64
N/A
mDDR memory, Upper Byte, R/W Data Strobe
MEM0_UDM
H1
O64
MEM0_UDQS
mDDR memory, Upper Byte, Write Data Mask
MEM0_DQ8
H2
MEM0_DQ9
G2
MEM0_DQ10
H3
MEM0_DQ11
F3
MEM0_DQ12
F1
B64
MEM0_UDQS
mDDR memory, Upper Byte, Bidirectional R/W Data
MEM0_DQ13
E2
MEM0_DQ14
F2
MEM0_DQ15
E3
8
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Pin Functions
PIN
NAME
I/O
NO.
POWER
TYPE
(1)
(continued)
CLOCK SYSTEM
DESCRIPTION
LED DRIVER INTERFACE
GPIO1_RPWM
N8
O14
Async
General-purpose I/O 1 (output only). If the DLPA1000 is not used, then this
output must be used as the red LED PWM signal used to control the LED
current. (8) If the DLPA1000 is used, then this output can be used as a
general purpose output controlled by the WPC processor.
GPIO2_GPWM
P9
O14
Async
General-purpose I/O 2 (output only). If the DLPA1000 is not used, then this
output must be used as the green LED PWM signal used to control the LED
current. (8) If the DLPA1000 is used, then this output can be used as a
general purpose output controlled by the WPC processor.
GPIO3_BPWM
R8
O14
Async
General-purpose I/O 3 (output only). If the DLPA1000 is not used, then this
output must be used as the blue LED PWM signal used to control the LED
current. (8) If the DLPA1000 is used, then this output can be used as a
general-purpose output controlled by the WPC processor.
LED_SEL_0
R6
O14
Async
LED enable SELECT. Controlled by programmable DMD sequence timing
(hysteresis buffer).
LED_SEL(1:0)
Selected LED
00
None
VCC18
LED_SEL_1
N6
O14
Async
01
Red
10
Green
11
Blue
These outputs should be input directly to the DLPA1000 if used. If the
DLPA1000 is not used, then a decode circuit is required to decode the
selected LED enable.
LEDDRV_ON
DMD_PWR_EN
P7
Async
LED driver enable. Active-high output control to external LED driver logic
(master enable). It is driven high 100 ms after LED_ENABLE is driven high
and driven low immediately when either LED_ENABLE or PARK is driven
low.
Async
DMD power regulator enable (active high). This is an active-high output that
should be used to control DMD VOFFSET, VBIAS, and VRESET voltages.
DMD_PWR_EN is driven high when the PARK input signal is set high.
However, DMD_PWR_EN is held high for 500 µs after the PARK input signal
is set low before it is driven low. TI recommends a weak external pulldown
resistor to keep this signal at a known state during power-up reset.
I1
Async
Successive approximation ADC comparator output (DLPC2607 input).
Assumes a successive approximation ADC is implemented with either a light
sensor or thermocouple or both feeding one input of an external comparator
and the other side of the comparator driven from the CMP_PWM pin of the
ASIC. If this function is not used, pull it down to ground (hysteresis buffer).
O14
Async
Successive approximation comparator pulse-width modulation input.
Supplies a PWM signal to drive the successive approximation ADC
Comparator used in light-to-voltage light sensor applications. If this function
is not used, leave it unconnected.
B14
Async
Power control signal for the WPC light sensor and other analog support
circuits using the DLPC2607 ADC. Alternately, it provides general purpose
I/O to the WPC microprocessor internal to the DLPC2607 device. If not used,
leave it unconnected (hysteresis buffer).
I3
N/A
Manufacturing test enable signal. Connect directly to ground on the PCB for
typical operation. Includes weak internal pulldown.
O14
K14
O14
WHITE POINT CORRECTION LIGHT SENSOR I/F
CMP_OUT
A6
CMP_PWM
B7
GPIO0_CMPPWR
P5
HWTEST_EN
A9
JTAGTDI
P6
JTAGTCK
N5
JTAGTMS
N7
JTAGTDO
R7
JTAGRSTZ
P8
(8)
VCC_ 18
VCC _INTF
JTAGTCK
I1
JTAG, serial data in. Includes weak internal pullup. (When JTAGRSTZ is
held low, this input can be used as ICP/ WPC debug port RXD.)
N/A
JTAG, serial data clock. Includes weak internal pullup.
JTAGTCK
JTAG, test mode select. Includes weak internal pullup.
O14
JTAGTCK
JTAG, serial data out
I1
ASYNC
VCC _18
JTAG, RESET (active low). Includes weak internal pullup. This signal must
be tied to ground, through an external ≤15-kΩ resistor, for typical operation.
The DLPA1000 is not available for initial DLPC2607 design applications. When the DLPA1000 is not used, all LED PWM signals are
forced high when LEDDRV_ON = 0, software LED control is disabled, or the sequence stops.
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Pin Functions
PIN
NAME
I/O
NO.
POWER
TYPE
(1)
(continued)
CLOCK SYSTEM
DESCRIPTION
Async
Test pin 0 – Sampled as an input test mode selection control upon release of
RESET, and then driven as an output. Includes weak internal pulldown. (9)
Normal use: Reserved for test output (ICP/ WPC debug port TXD). Leave
open or unconnected for typical use.
Alternative use: If focus motor control is used, use this pin as the motor
driver chip enable. Do not apply an external pullup to this pin to avoid putting
the DLPC2607 device in a test mode.
Async
Test pin 1 – Sampled as an input test mode selection control upon release of
RESET, and then driven as an output. Includes weak internal pulldown. (9)
Normal use: Reserved for test output. Leave open or unconnected for typical
use.
Alternative use: If focus motor control is used, use this pin as the motor
driver data bit1 (LSB). Do not apply an external pullup to this pin to avoid
putting the DLPC2607 device in a test mode.
Async
Test pin 2 – Sampled as an input test mode selection control upon release of
RESET, and then driven as an output. Includes weak internal pulldown. (9)
Normal use: Reserved for test output. Leave open or unconnected for typical
use.
Alternative use: If focus motor control is used, use this pin as the motor
driver data bit2. Do not apply an external pullup to this pin to avoid putting
the DLPC2607 device in a test mode.
Async
Test Pin 3 – Sampled as an input test mode selection control upon release of
RESET, and then driven as an output. Includes weak internal pulldown. (9)
Normal use: Reserved for test output. Leave open or unconnected for typical
use.
Alternative use: If focus motor control is used, use this pin as the motor
driver motor driver data bit3. Do not apply an external pullup to this pin to
avoid putting the DLPC2607 device in a test mode.
TEST AND DEBUG INTERFACES
TSTPT_0
TSTPT_1
TSTPT_2
TSTPT_3
TSTPT_4
B6
A8
C7
B5
A7
VCC18
VCC18
VCC18
VCC18
VCC18
B18
B18
B18
B18
B18
Async
Test pin 4 – Sampled as an input test mode selection control upon release of
RESET, and then driven as an output. Includes weak internal pulldown. (9)
Normal use: Reserved for test output. Leave open or unconnected for typical
use.
Alternative use: If focus motor control is used, use this pin as the motor
driver data bit4 (MSB). Do not apply an external pullup to this pin to avoid
putting the DLPC2607 device in a test mode.
Without External Pullup
(9)
Enables auto-initialization from flash
TSTPT_5
TSTPT_6
C8
N9
VCC18
VCC18
B18
B18
Async
Async
With External Pullup
(10)
Disables auto-initialization and
facilitates flash programming via
I2C of a blank flash
Test pin 5 – Sampled as an input test mode selection control upon release of
RESET and then driven as an output. Includes weak internal pulldown. (9)
Normal use: Reserved for test output. Leave open or unconnected for typical
use.
Alternative use: Not yet defined. Do not apply an external pullup to this pin to
avoid putting the DLPC2607 device in a test mode.
Test pin 6 and PLL REFCLK frequency selection – Sampled as an input test
mode selection control upon release of RESET and then driven as an output.
Includes a weak internal pulldown. (9)
Normal use: Reserved for test output. Leave open or unconnected for typical
use.
Alternative use: Not yet defined.
This pin is sampled upon de-assertion of RESTZ to determine REFCLK
frequency selection. DLPC2607 I2C address is set corresponding to the
sampled input value as follows:
Without External Pullup
(9)
PLL assumes REFCLK = 16.67 MHz
With External Pullup
(10)
PLL assumes REFCLK = 8.33
MHz
(9)
If operation does not call for an external pullup and there is no external logic that might overcome the weak internal pulldown resistor,
then this I/O can be left open or unconnected for typical operation. If operation does not call for an external pullup, but there is external
logic that might overcome the weak internal pulldown resistor, then TI recommends an external pulldown resistor to ensure a logic low.
(10) External pullup resistor must be 15 kΩ or less.
10
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Pin Functions
PIN
NAME
TSTPT_7
I/O
NO.
R9
POWER
VCC18
TYPE
B18
(1)
(continued)
CLOCK SYSTEM
Async
DESCRIPTION
Test pin 7 and I2C address selection – Sampled as an input test mode
selection control upon release of RESET, and then driven as an output.
Includes weak internal pulldown.
Normal use: Reserved for test output. Leave open or unconnected for typical
use.
Alternative use: Not yet defined.
This pin is sampled upon deassertion of RESET to determine I2C address
selection. DLPC2607 I2C address is set corresponding to the sampled input
value as follows:
Without External Pullup
(9)
2
I C slave Write Address = x36
I2C slave Read Address = x37
With External Pullup
(10)
2
I C slave Write Address = x3A
I2C slave Read Address = x3B
POWER AND GROUND (11)
VDD10
VDD_PLL
VCC18
D5, D9,
F4, F12,
J4, J12,
M6, M8,
M11
H12
C4, D8,
E4, G3,
K3, K12,
L4, M5,
M9,
M12, N4,
N12
VCC_FLSH
D6
VCC_INTF
D11,
E12
GND
D4, D7,
D10,
D12, G4,
G12, H4,
K4, L12,
M4, M7,
M10
RTN_PLL
J13
Reserved
C2, C3,
N2, N3
1-V core logic power supply
1-V power supply for the internal PLL
1.8-V power supply for all I/O other than the host, video interface, and SPI
flash buses
1.8-V, 2.5-V, or 3.3-V power supply for SPI flash bus I/O
1.8-V, 2.5-V, or 3.3-V power supply for all I/Os on the host or video interface
(includes I2C, PDATA, video syncs, PARK, and LED_ENABLE pins)
Common ground
Analog ground return for the PLL (This must be connected to the common
ground GND through a ferrite.)
No connects. Other signals can be routed through the ball on these pins
(versus going around them) to ease routing if desired
(11) 134 total signal I/O pins, 38 total power or ground pins, and 4 total reserved pins
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted) (1)
Voltage (2)
MIN
MAX
VDD10
–0.5
1.32
VDD_PLL
–0.5
1.32
VCC18
–0.5
2.75
VCC_FLSH
–0.5
3.6
–0.5
3.6
VCC_INTF
VI 1.8 V, 2.5 V, 3.3 V
TJ
(3)
Operating junction temperature
TA
Operating ambient temperature
Tstg
Storage temperature
(1)
(2)
(3)
(4)
(5)
(4) (5)
–0.5
3.6
–30
105
UNIT
V
ºC
–30
85
ºC
–40
125
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to GND and are at the device not at the power supply.
Applies to external input and bidirectional buffers.
TI strongly recommends I/O simulations (using IBIS models) for operation near the extremes of the supported ambient operating
temperature range to ensure that the PCB design provides acceptable signal integrity.
The operating ambient temperature range assumes zero forced air flow, a JEDEC JESD51 junction-to-ambient thermal resistance value
at zero forced air flow (RθJA at 0 m/s), a JEDEC JESD51 standard test card and environment, along with minimum and maximum
estimated power dissipation across process, voltage, and temperature. Thermal conditions vary by application, which impacts RθJA.
Thus, maximum operating ambient temperature varies by application.
(a) TA_min = TJ_min – (PD_min × RθJA) = –30°C – (0.0 W × 64.96°C/W) = –30°C
(b) TA_min = TJ_min – (PD_min × RθJA) = 105°C – (0.3 W × 64.96°C/W) = 85°C
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VDD10
1-V supply voltage, core logic
0.95
1
1.05
V
VDD_PLL
Analog voltage for PLL
0.95
1
1.05
V
VCC18
1.8-V supply voltage (for all non-flash and host interface signals)
VCC_FLSH
VCC_INTF
Configuration and control I/O supply voltage
(variable)
Pixel interface supply voltage (variable)
VI
Input voltage
VO
Output voltage
tRAMP
Power supply ramp time
(1)
12
1.71
1.8
1.89
V
1.8-V LVCMOS
1.71
1.8
1.89
V
2.5-V LVCMOS
2.375
2.5
2.625
V
3.3-V LVCMOS
3.135
3.3
3.465
V
1.8-V LVCMOS
1.71
1.8
1.89
V
2.5-V LVCMOS
2.375
2.5
2.625
V
3.3-V LVCMOS
3.135
3.3
3.465
V
+ 0.3
V
–0.3
0
10
VCCIO
(1)
VCCIO (1)
V
µs
VCCIO represents the actual supply voltage applied to the corresponding I/O.
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6.4 Thermal Information
over operating free-air temperature range (unless otherwise noted)
DLPC2607
THERMAL METRIC
(1)
ZVB (NFBGA)
UNIT
176 PINS
RθJC
Junction-to-case thermal resistance
19.52
ºC/W
RθJA
Junction-to-air thermal resistance (with no forced airflow)
64.96
ºC/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
6.5 Typical Current and Power Dissipation
over operating free-air temperature range (unless otherwise noted)
SUPPLY
TYPICAL
VOLTAGE (V)
I/F Sleep Mode Disabled
WVGA APPLICATIONS
nHD APPLICATIONS
TYPICAL CURRENT
(mA)
TYPICAL POWER
(mW)
TYPICAL CURRENT
(mA)
TYPICAL POWER
(mW)
0.1
(1) (2) (3)
VCC_INTF
1.8
0
0.1
0
VCC_FLSH (4)
2.5
0
0
0
0
VCC18
1.8
28.2
50.8
22.7
40.9
VDD_PLL
1
2.8
2.8
2.8
2.8
VDD10
1
39
39.0
37.7
37.7
Total
I/F Sleep Mode Enabled
92.7
VCC_INTF
1.8
0
0.1
0
VCC_FLSH
2.5
0
0
0
0
VCC18 (4)
1.8
27
48.6
22.5
40.4
VDD_PLL
1
2.8
2.8
2.8
2.8
VDD10
1
30.6
30.6
29.3
29.3
Total
(1)
(2)
(3)
(4)
81.5
(1) (2) (3)
82.1
0.1
72.6
I/F sleep is a programmable parameter that can be set to save power in free-run, sequencer mode when displaying still images on the
DMD. When I/F sleep is enabled, any images applied to the input bus to the DLPC2607 device are ignored.
Power for both I/F sleep mode disabled and I/F sleep mode enabled was measured while transferring a full 864 × 480 landscape image
at periodic 30 frames per second. The image was a 12 × 6 color checkerboard.
All measurements were taken on a TI internal reference design board at 25°C ambient.
VCC_FLSH power was 0 at the time of the measurement because flash accesses are limited when the ASIC is being configured.
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6.6 I/O Characteristics
Voltage and current characteristics for each I/O type signal listed previously in the DLPC2607 table are summarized in I/O
Characteristics. All inputs and outputs are LVCMOS. (1)
I/O TYPE
DESCRIPTION
VCCIO
(NOM)
(V)
VIL (2)
(min)
(V)
VIL (MAX)
(V)
VIH (MIN)
(V)
VIH (3)
(MAX)
(V)
IIN (4)
(MAX)
(µA)
I1
Input (STD)
1.8
–0.3
0.5
1.2
3
±10
1.8
–0.3
0.5
1.2
3
±10
2.5
–0.3
0.7
1.7
3.6
±10
3.3
–0.3
0.8
2
3.6
±10
1.8
–0.3
0.5
1.2
3
±10
2.5
–0.3
0.7
1.7
3.6
±10
3.3
–0.3
0.8
2
3.6
±10
–0.3
0.5
1.2
3
±10
I2
I3
Input (FLSH)
Input (INTF)
VOH (5)
(MIN)
(V)
VOL (6)
(MAX)
(V)
IOH (7)
(MIN)
(mA)
IOL (8)
(MIN)
(mA)
ITS (9)
(MAX)
(µA)
I4
Input (REFCLK)
1.8
O14
1× output (STD/
REFCLK)
1.8
1.25
0.4
2.58
2.89
±10
1.8
1.25
0.4
2.58
2.89
±10
O24
1× output (FLSH)
2.5
1.7
0.7
6.2
6.3
±10
3.3
2.4
0.4
5.29
9.38
±10
O58
2× output (DMD)
1.8
1.25
0.4
6.41
5.78
±10
O64 (10)
1× output (MEM)
1.8
1.53
0.19
4
4
±10
(10)
1× output (MEM
DIFF) (11)
1.8
1.53
0.19
4
4
±10
B14
1× bidirectional
(STD) output
1.8
–0.3
0.5
1.2
3
±10
1.25
0.4
2.58
2.89
±10
B18 (12)
2× bidirectional
(STD) output
1.8
–0.3
0.5
1.2
3
±10
1.25
0.4
5.15
5.72
±10
1.8
–0.3
0.5
1.2
3
±10
1.25
0.4
2.58
2.89
±10
2.5
–0.3
0.7
1.7
3.6
±10
1.7
0.7
6.2
6.3
±10
3.3
–0.3
0.8
2
3.6
±10
2.4
0.4
5.29
9.38
±10
1.8
–0.3
0.5
1.2
3
±10
2.4
0.4
5.15
5.72
±10
2.5
–0.3
0.7
1.7
3.6
±10
1.7
0.7
12.4
12.7
±10
3.3
–0.3
0.8
2.0
3.6
±10
1.25
0.4
10.57
18.68
±10
1.8
–0.3
0.57
1.19
2.2
±10
1.53
0.19
4
4
±10
O74
B34
B38
B64
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(10)
1× bidirectional
(INTF) output
2× bidirectional
(INTF) output
1× bidirectional
(MEM) output
Pin PLL_REFCLK_I is a crystal oscillator input pin and is not tested during VIH/VIL testing.
VIL(min) is the absolute minimum voltage that can safely be applied to each corresponding pin.
VOH(max) is the maximum voltage that can safely be applied to each corresponding pin.
Input leakage current with no internal pullup or pulldown. VIN = 0 or VIN = VCCIO where VCCIO = I/O supply voltage
IOH = – rated current
IOL = + rated current
VOH = VOH(max)
VOL = VOL(max)
Tri-state output leakage current. VIN = 0 or VIN = VCCIO where VCCIO = I/O supply voltage
O64, O74, and B64 buffers are tested to only 100 µA for IOH/IOL due to tester limitations.
The O74 mDDR differential clock (CK) output is simply a pair of single-ended drivers driven by a true and complementary signal.
B18 buffers are not tested for IIH.
6.7 Internal Pullup and Pulldown Characteristics
The resistance depends on the supply voltage level applied to the I/O. (1)
Weak pullup resistance
Weak pulldown resistance
(1)
(2)
14
(2)
VCCIO (V)
MIN
MAX
3.3
N/A
N/A
2.5
33
89
1.8
50.3
157.3
3.3
17.8
79.6
2.5
37
109
1.8
51.8
184.1
UNIT
kΩ
kΩ
The description column of identifies whether the corresponding signal includes an internal pullup or pulldown resistor.
Due to tester limitations, only the 1.8-V pullup resistors are measured and no pulldown resistors are measured.
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6.8 Parallel I/F Frame Timing Requirements
MIN
MAX
UNIT
tp_vsw
Pulse duration – VSYNC_WE high
50% reference points
1
lines
tp_vbp
Vertical back porch – Time from the leading edge of VSYNC_WE
to the leading edge HSYNC_CS for the first active line. (1)
50% reference points
2
lines
tp_vfp
Vertical front porch – Time from the leading edge of the
HSYNC_CS following the last active line in a frame to the leading
edge of VSYNC_WE. (1)
50% reference points
1
lines
tp_tvb
Total vertical blanking – Time from the leading edge of HSYNC_CS
following the last active line of one frame to the leading edge of
HSYNC_CS for the first active line in the next frame. This is equal
50% reference points
to the sum of Vertical back porch (tp_vbp) + Vertical front porch
(tp_vfp).
12
lines
tp_hsw
Pulse duration – HSYNC_CS high
50% reference points
4
tp_hbp
Horizontal back porch – Time from rising edge of HSYNC_CS to
rising edge of DATAEN_CMD.
50% reference points
4
PCLKs
tp_hfp
Horizontal front porch – Time from falling edge of DATAEN_CMD
to rising edge of HSYNC_CS.
50% reference points
8
PCLKs
tp_thh
Total horizontal blanking – Sum of horizontal front and back
porches
50% reference points
(1)
(2)
128
PCLKs
(2)
PCLKs
The programmable parameter vertical sync line delay (I2C: 0x23) must be set such that:
6 – Vertical front porch (tp_vfp)’ (min 0) ≤ Vertical sync line delay ≤ Vertical back porch (tp_vbp) – 2 (max 15). The default value for vertical
sync line delay is set to 5; thus, only a vertical back porch less than 7 requires potential action.
Total horizontal blanking is driven by the max line rate for a given source, which is a function of resolution and orientation. See Parallel
I/F Maximum Parallel Interface Horizontal Line Rate for max line rate for each source and display combination. tp_thb = Roundup [(1000
x ƒclock)/ LR] – APPL where ƒclock = Pixel clock rate in MHz, LR = Line rate in kHz, and the number of active pixels per (horizontal) line is
APPL. If tp_thb is calculated to be less than tp_hbp + tp_hfp, then the pixel clock rate is too low, or the line rate is too high, and one or both
must be adjusted.
6.9 Parallel I/F General Timing Requirements
MIN
ƒclock
Clock frequency, PCLK
tp_clkper
Clock period, PCLK
50% reference points
tp_clkjit
Clock jitter, PCLK
tp_wh
tp_wl
MAX
UNIT
1
33.5
MHz
29.85
1000
ns
Max ƒclock
(1)
(1)
Pulse-duration low, PCLK
50% reference points
10
ns
Pulse-duration high, PCLK
50% reference points
10
ns
tp_su
Setup time – HSYNC_CS, DATEN_CMD, PDATA (23:0)
valid before the active edge of PCLK (2)
50% reference points
3
ns
tp_h
Hold time – HSYNC_CS, DATEN_CMD, PDATA (23:0)
valid after the active edge of PCLK (2)
50% reference points
3
ns
tt
Transition time – All signals
20% to 80% reference points
(1)
(2)
0.2
4
ns
Clock jitter (in ns) should be calculated using this formula: Jitter = (1 / ƒclock – 28.35 ns). Setup and hold times must be met during clock
jitter.
See Figure 2.
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6.10 Parallel I/F Maximum Parallel Interface Horizontal Line Rate
DMD
PARALLEL BUS
SOURCE
(2)
17
Not supported
N/A
720 × 288
20
Not supported
N/A
QVGA
320 × 240
(2)
17
240 × 320
(2)
22
QWVGA
427 × 240
(2)
17
240 × 427
(2)
27
42
nHD
640 × 360
(2)
25
360 × 640
(2)
3:2 VGA
640 × 430
(2)
30
430 × 640
(2)
45
4:3 VGA
640 × 480
(2)
34
480 × 640
(2)
45
WVGA-720
720 × 480
(2)
34
480 × 720
(2)
51
WVGA-752
752 × 480
(2)
34
480 × 752
(2)
53
WVGA-800
800 × 480
(2)
34
480 × 800
(2)
56
WVGA-852
852 × 480
(2)
34
480 × 852
(2)
56
WVGA-853
853 × 480
(2)
34
480 × 853
(2)
56
WVGA-854
854 × 480
(2)
34
480 × 854
(2)
56
WVGA-864
864 × 480
(2)
34
480 × 864
(2)
56
720 × 240
(2)
32
Not supported
N/A
720 × 288
(2)
39
Not supported
N/A
32
240 × 320
(2)
42
52
PAL
(1)
(1)
QVGA
16
320 × 240
QWVGA
427 × 240
32
240 × 427
(2)
nHD
640 × 360
48
360 × 640
(2)
79
3:2 VGA
640 × 430
(2)
50
430 × 640
(2)
74
4:3 VGA
640 × 480
(2)
50
480 × 640
(2)
66
WVGA-720
720 × 480
(2)
44
480 × 720
(2)
66
WVGA-752
752 × 480
(2)
42
480 × 752
(2)
66
WVGA-800
800 × 480
(2)
40
480 × 800
(2)
66
WVGA-852
852 × 480
(2)
37
480 × 852
(2)
66
WVGA-853
853 × 480
(2)
37
480 × 853
(2)
66
WVGA-854
854 × 480
(2)
37
480 × 854
(2)
66
864 × 480
(2)
480 × 864
(2)
66
WVGA-864
(1)
(2)
MAX LINE RATE
(kHz)
(2)
NSTC
0.2 nHD Manhattan
RESOLUTION (HxV)
720 × 240
PAL
0.3 WVGA and
0.24 VGA diamond
PORTRAIT FORMAT
MAX LINE RATE
(kHz)
(1)
NSTC
(1)
LANDSCAPE FORMAT
RESOLUTION (H×V)
37
NTSC and PAL are assumed to be interlaced sources
Not supported for 100- to 120-Hz operation
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6.11 BT.656 I/F General Timing Requirements
The DLPC2607 ASIC input interface supports the industry standard BT.656 parallel video interface. See the appropriate ITUR BT.656 specification for detailed interface timing requirements. Map the BT.656 data bits to the DLPC2607 PDATA bus as
shown in Figure 3. (1)
ƒclock
Clock frequency, PCLK
tp_clkper
Clock period, PCLK
50% reference points
(2)
MIN
MAX
UNIT
1
33.5
MHz
29.85
1000
ns
(2)
tp_clkjit
Clock jitter, PCLK
Maximum ƒclock
(2)
tp_wh
Pulse duration low, PCLK
50% reference points
10
ns
tp_wl
Pulse duration high, PCLK
50% reference points
10
ns
tp_su
Setup time – HSYNC, DATEN, PDATA(23:0) valid
before the active edge of PCLK
50% reference points
3
ns
tp_h
Hold time – HSYNC, DATEN, PDATA(23:0) valid
after the active edge of PCLK
50% reference points
3
ns
tt
Transition time – All signals
20% to 80% reference points
(1)
(2)
0.2
4
ns
The BT.656 I/F accepts 8-bit per color, 4:2:2 YCb/Cr data encoded per the industry standard though PDATA(7:0) on the active edge of
PCLK (that is, programmable) as shown in Figure 2.
Clock jitter should be calculated using this formula: Jitter = (1 / ƒclock – 28.35 ns). Setup and hold times must be met during clock jitter.
6.12 100- to 120-Hz Operational Limitations
The table below assumes that a front-end device ahead of the DLPC2607 device converts all 3-D sources to the 3-D format
defined previously and provides any needed left-eye or right-eye selection control directly to the 3-D glasses (that is, the
DLPC2607 device does not control the glasses). The DLPC2607 device includes a double buffer frame memory, which
causes the displayed image to be delayed one frame relative to its input. This requires left or right eye-frame shutter control
to be inverted prior to being sent to the glasses.
SOURCE
nHD
RESOLUTION
(APPL x ALPF)
MIN FRAME
RATE
(Hz)
640 × 360
99
NOM FRAME MAX FRAME
RATE
RATE
(Hz)
(Hz)
100
101
MIN TVB
(tp_tvb)
(LINES)
MAX LINE
RATE
(kHz)
MIN LINE
RATE
(kHz)
MIN CLOCK
RATE
(MHz)
12
48
(1)
(2)
(2)
WQVGA
427 × 240
99
100
101
12
32
(1)
QVGA
320 × 240
99
100
101
12
32
(1)
(2)
48
(1)
(2)
32
(1)
(2)
32
(1)
(2)
nHD
WQVGA
QVGA
(1)
(2)
640 × 360
427 × 240
320 × 240
118.8
118.8
118.8
120
120
120
121.2
121.2
121.2
12
12
12
Use the following equation to determine the minimum line rate for a given application. The application cannot be supported if the
calculated minimum line rate exceeds the maximum line rate defined elsewhere in this table;
Line_Rate_min (kHz) = Frame_Rate_max (Hz) × [ALPF + TVB] /1000
Where: TVB = Total vertical blanking (in lines)
ALPF = Active lines per frame
Frame_Rate_max = Max frame rate including all expected wander
The following equation should be used to determine the minimum pixel clock rate for a given application. The application cannot be
supported if the calculated minimum pixel clock rate exceeds the max pixel clock rate defined in Parallel I/F General Timing
Requirements.
Pixel_Clock_min (MHz) = Line_Rate_max (kHz) × (APPL + 12) / 1000
Where: APPL = Active pixels per line
Line_Rate_max = Max line rate including all expected wander
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6.13 Flash Interface Timing Requirements
The DLPC2607 ASIC flash memory interface consists of a SPI flash serial interface at 33.3 MHz (nominal).
MIN
(3)
(1) (2)
MAX
UNIT
ƒclock
Clock frequency, SPI_CLK
33.3266
33.34
MHz
tp_clkper
Clock period, SPI_CLK
50% reference points
29.994
30.006
ns
tp_wh
Pulse duration low, SPI_CLK
50% reference points
10
ns
tp_wl
Pulse duration high, SPI_CLK
50% reference points
10
ns
tt
Transition time – all signals
20% to 80% reference points
0.2
tp_su
Setup time – SPI_DIN valid before SPI_CLK falling edge
50% reference points
10
ns
tp_h
Hold time – SPI_DIN valid after SPI_CLK falling edge
50% reference points
0
ns
tp_clqv
SP_ICLK clock low to output valid time – SPIDOUT and
SPI_CSZ
50% reference points
tp_clqx
SPI_CLK clock low output hold time – SPI_DOUT and
SPI_CSZ
50% reference points
(1)
(2)
(3)
4
ns
1
ns
–1
ns
Standard SPI protocol is to transmit data on the falling edge of SPI_CLK and capture data on the rising edge. The DLPC2607 device
does transmit data on the falling edge, but it captures data on the falling edge rather than the rising edge. This provides support for SPI
devices with long clock-to-Q timing. The DLPC2607 device hold capture timing is set to facilitate reliable operation with standard
external SPI protocol devices.
With the above output timing, the DLPC2607 device provides the external SPI device 14-ns input set-up and 14-ns input hold relative to
the rising edge of SPI_CLK.
This range includes the 200 ppm of the external oscillator (but no jitter).
6.14 DMD Interface Timing Requirements
The DLPC2607 ASIC DMD interface consists of a 76.19-MHz (nominal) DDR output-only interface with LVCMOS signaling.
(see (1))
(2)
MIN
MAX
UNIT
ƒclock
Clock frequency, DMD_DCLK and DMD_SAC_CLK
76.175
76.206
MHz
tp_clkper
Clock period, DMD_DCLK and DMD_SAC_CLK
50% reference points
13.122
13.128
ns
tp_wh
Pulse duration low, DMD_DCLK and DMD_SAC_CLK
50% reference points
6.2
tp_wl
Pulse duration high, DMD_DCLK and DMD_SAC_CLK
50% reference points
6.2
tt
Transition time – all signals
20% to 80% reference points
0.3
tp_su
Output setup time – DMD_D(14:0),
DMD_SCTRL, DMD_LOADB and DMD_TRC
relative to both rising and falling edges of DMD_DCLK (3)
tp_h
ns
ns
2
ns
50% reference points
1.5
ns
Output hold time – DMD_D(14:0),
DMD_SCTRL,DMD_LOADB and DMD_TRC
signals relative to both rising and falling edges of
DMD_DCLK (3) (4)
50% reference points
1.5
ns
tp_d1_skew
DMD data skew – DMD_D(14:0),
DMD_SCTRL, DMD_LOADB, and DMD_TRC
signals relative to each other (5)
50% reference points
0.2
ns
tp_clk_skew
Clock skew – DMD_DCLK and DMD_SAC_CLK relative to each
50% reference points
other
0.2
ns
tp_d2_skew
DAD/SAC data skew - DMD_SAC_BUS,
DMD_DRC_OEZ (6), DMD_DRC_BUS,
and DMD_DRC_STRB signals relative to DMD_SAC_CLK
0.2
ns
(1)
(2)
(3)
(4)
(5)
(6)
18
(4)
50% reference points
Assumes a 30-Ω series termination for all DMD interface signals (except DAD_DMD_OEZ)
This range includes the 200 ppm of the external oscillator (but no jitter).
Assumes minimum DMD setup time = 1 ns and minimum DMD hold time = 1 ns
Output setup and hold numbers already account for controller clock jitter. Only routing skew and DMD setup/hold must be considered in
system timing analysis.
Assumes DMD data routing skew = 0.1 ns max
DMD_DAD_OEZ requires a 30- to 100-kΩ external pullup resistor connected to VCC18 to achieve proper timing.
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6.15 mDDR Memory Interface Timing Requirements
The DLPC2607 controller mDDR memory interface consists of a 16-bit wide, mDDR interface (that is, LVCMOS signaling)
operated at 133.33 MHz (nominal). (see (1) (2) (3))
MIN
tCYCLE
Cycle-time reference
(4)
MAX
UNIT
7500
ps
tCH
CK high pulse width
2700
ps
tCL
CK low pulse width (4)
2700
ps
tDQSH
DQS high pulse width (4)
2700
ps
tDQSL
DQS low pulse width (4)
2700
ps
tWAC
CK to address and control outputs active
tQAC
CK to DQS output active
tDAC
DQS to DQ and DM output active
tDQSRS
(1)
(2)
(3)
(4)
(5)
Input (read) DQS and DQ skew
–2870
–1225
(5)
2870
ps
200
ps
1225
ps
1000
ps
This includes the 200 ppm of the external oscillator (but no jitter).
Output setup and hold numbers already account for controller clock jitter. Only routing skew and memory setup/hold must be considered
in system timing analysis.
Assumes a 30-Ω series termination on all signal lines.
CK and DQS pulse duration specifications for the DLPC2607 assume it is interfacing to a 166-MHz mDDR device. Even though these
memories are only operated at 133.33 MHz, according to memory vendors, the rated tCK specification (that is 6 ns) can be applied to
determine minimum CK and DQS pulse duration requirements to the memory.
Note that DQS must be within the tDQSRS read data-skew window, but need not be centered.
1 Frame
t p_vsw
VSYNC_WE
(This diagram assumes the VSYNC
active edge is the Rising edge)
tp_vbp
tp_vfp
HSYNC_CS
DATAEN_CMD
1 Line
tp_hsw
HSYNC_CS
(This diagram assumes the HSYNC
active edge is the Rising edge)
tp_hbp
tp_hfp
DATAEN_CMD
PDATA(23/15:0)
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
P0
x
x
x
xx
xx
xx
P1
P2
x
x
x
xx
xx
xx
P3
P
n-2
x
x
x
xx
xxxxxxxxxxxx
xx
xx xxxxxxxxxxxx
xxxxxxxxxxxx
P
n-1
Pn
PCLK
Figure 1. Parallel I/F Frame Timing
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tp_clkper
tp_wh
tp_wl
PCLK
tp_h
tp_su
Figure 2. Parallel and BT.656 I/F General Timing
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
PDATA (7:0 ) of the Input Pixel data bus
0
Bus Assignment Mapping
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
Y
7
Y
6
Y
5
Y
4
Y
3
Y
2
Y
1
Y
0
Data bit mapping on the pins of the ASIC
Figure 3. DLPC2607 PDATA Bus – BT.656 I/F Mode Bit Mapping (YCrCb 4:2:2 Source)
t clkper
SPI_CLK
(ASIC Output)
SPI_DIN
(ASIC Inputs)
twh
t wl
xx
xx
xx
xx
xx
xx
xx
xxxxxxxxxxx
xxx
xx
xxxxxxxxxxx
xxx
xx
xxxxxxxxxxx
xxx
t
p_clqv
SPI_DOUT, SPI_CS(1:0)
(ASIC Outputs)
t p_clqx
xx
xx
xx
xx
xx
xx
tp_su
t p_h
xx
xxxxxxxxxxx
xx
xx
xxxxxxxxxxx
xx
xxxxxxxxxxxxx
xx
xx
xx
xx
xx
xx
xx
Figure 4. Flash I/F Timing
20
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tp_d1_skew
DMD_D(14:0)
DMD_SCTRL
DMD_TRC
DMD_LOADB
tp_su
tp_h
DMD_DCLK
tp_wh
tp_wl
tclk_skew
DMD_SAC_CLK
tp_d2_skew
DMD_SAC_BUS
DMD_DAD_OEZ
DMD_DAD_BUS
DMD_DAD_STRB
Figure 5. DMD I/F Timing
tCYCLE
MEM0_CK_P
MEM0_CK_N
tCH
MEM0_ADDRS(12:0)
MEM0_BA(1:0)
MEM0_RASZ
MEM0_CASZ
MEM0_WEZ
MEM0_CSZ
MEM0_CKE
tWAC
tCL
tWAC
Figure 6. mDRR Memory Address and Control Timing
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tCYCLE
MEM0_CK_P
MEM0_CK_N
tCH
tCL
tQAC
(tDQSCK)
tCYCLE
tDQSH
tDQSL
MEM0_xDQS
tDAC
MEM0_xDQ(7:0)
MEM0_xDQ(15:8)
tDAC
MEM0_xDM
Figure 7. mDRR Memory Write Dtat Timing
tCYCLE
MEM0_xDQS
tDQSH
tDQSL
MEM0_xDQ(first)
tDQSRS
MEM0_xDQ(last)
MEM0xDQ(7:0)
Data Valid Window
Figure 8. mDDR Memory Read Data Timing
22
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7 Detailed Description
7.1 Overview
The DLPC2607 is the display controller for the 0.3-WVGA, 0.24-VGA and 0.2-nHD DMDs. Both the controller
and the DMD must be used in conjunction with each other for reliable operation of the DMD. The DLPC2607
display controller provides interfaces and data/image processing functions that are optimized for small form factor
and low power display applications. Applications include pico projectors, smart projectors, screen less display,
interactive display, wearable displays and many more. In typical systems a separate applications processor is
used to provide various multimedia functionality (such as video decoder, HDMI receiver, VGA, SD card, or USB
I/F chip).
7.2 Functional Block Diagram
DLPC2607
Pixel
Data
I/F
24
Front End
Processing
PLL
Vector Graphics
Processing
Clocks
& Resets
Configuration
Control
I2C
Crystal
or
Osc
Display
Control
16
DDR
Mobile
DDR
DRAM
DMD
Formatting
DDR
SPI
Serial
Flash
Frame
Memory
Controller
LED
Driver
0.3 WVGA
0.2 nHD, or
0.24 VGA
DMD
Host
Controller
7.3 Feature Description
7.3.1 Parallel Bus Interface
The parallel bus interface complies with standard graphics interface protocol, which includes a vertical sync
signal (VSYNC_WE), horizontal sync signal (HSYNC_CS), optional data valid signal (DATAEN_CMD), a 24-bit
data bus (PDATA), and a pixel clock (PCLK). The user can program the polarity of both syncs and the active
edge of the clock. Figure 1 shows the relationship of these signals. The data valid signal (DATAEN_CMD) is
optional in that the DLPC2607 device provides auto-framing parameters that can be programmed to define the
data valid window based on pixel and line counting relative to the horizontal and vertical syncs.
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Feature Description (continued)
In addition to these standard signals, an optional side-band signal (PDM_CVS_TE) is available, which allows the
user to stop the periodic frame updates without losing the displayed image. When PDM_CVS_TE is active, it acts
as a data mask and does not allow the source image to be propagated to the display. A programmable PDM
polarity parameter determines if it is active high or active low. This parameter defaults to make PDM_CVS_TE
active high. Therefore, if this function is not desired, tie it to a logic low on the PCB. PDM_CVS_TE is restricted
to change only during vertical blanking. Note that VSYNC_WE must remain active at all times (in Lock-to-VSYNC
mode) or the display sequencer stops and causes the LEDs to be shut off.
The parallel bus interface supports six data transfer formats:
• 16-bit RGB565
• 18-bit RGB666
• 18-bit 4:4:4 YCrCb666
• 24-bit RGB888
• 24-bit 4:4:4 YCrCb888
• 16-bit 4:2:2 YCrCb (standard sampling assumed to be Y0Cb0, Y1Cr0, Y2Cb2, Y3Cr2, Y4Cb4, Y5Cr4, …)
Figure 9 shows the required PDATA(23:0) bus mapping for these six data transfer formats.
Parallel Bus Mode ± 4:4:4 RGB and YCrCb Sources
PDATA(15:0) ± 565 Mapping to 888
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
PDATA(15:0) of the Input Pixel data bus
0
Bus Assignment Mapping
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B4
B3
B2
B1
RGB Data bit mapping on the ASIC
B0
4:4:4 YCrCb Data bit mapping on the ASIC
PDATA(17:0) ± 666 Mapping to 888
PDATA(17:0) of the Input Pixel data bus
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
RGB Data bit mapping on the ASIC
Cr
5
Cr
4
Cr
3
Cr
2
Cr
1
Cr
0
Y
5
Y
4
Y
3
Y
2
Y
1
Y
0
Cb
5
Cb
4
Cb
3
Cb
2
Cb
1
Cb
0
4:4:4 YCrCb Data bit mapping on the ASIC
Bus Assignment Mapping
PDATA(23:0) ± 888 Mapping
PDATA(23:0) of the Input Pixel data bus
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R7
R6
R5
R4
R3
R2
R1
R0
G7
G6
G5
G4
G3
G2
G1
G0
B7
B6
B5
B4
B3
B2
B1
B0
RGB Data bit mapping on the ASIC
Cr
7
Cr
6
Cr
5
Cr
4
Cr
3
Cr
2
Cr
1
Cr
0
Y
7
Y
6
Y
5
Y
4
Y
3
Y
2
Y
1
Y
0
Cb
7
Cb
6
Cb
5
Cb
4
Cb
3
Cb
2
Cb
1
Cb
0
4:4:4 YCrCb Data bit mapping on the ASIC
9
8
7
6
5
4
3
2
1
0
Bus Assignment Mapping
Parallel Bus Mode - 16-bit YCrCb 4:2:2 Source
PDATA(23:0) ± Cr/CbY880 Mapping
23
22
21
20
19
18
17
16
15
Cr/
Cb
7
Cr/
Cb
6
Cr/
Cb
5
Cr/
Cb
4
Cr/
Cb
3
Cr/
Cb
2
Cr/
Cb
1
Cr/
Cb
0
14
13
12
11
10
PDATA(23:0) of the Input Pixel data bus
Bus Assignment Mapping
Y
7
Y
6
Y
5
Y
4
Y
3
Y
2
Y
1
Y
0
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
Data bit mapping on the pins of the ASIC
Figure 9. PDATA Bus – Parallel I/F Mode Bit Mapping
7.3.2 100- to 120-Hz 3-D Display Operation
The DLPC2607 device supports 100- to 120-Hz 3-D display operation, but is limited to a narrow set of
configurations. 3-D operation is limited to:
• 0.2-nHD DMDs only
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Feature Description (continued)
•
•
•
•
•
•
•
nHD, WQVGA and QVGA source resolutions
Parallel bus interface only (all pixel formats are supported)
Landscape source and display orientation only
Non-interlaced video-graphics only
100-Hz ±1% or 120-Hz ±1% source frame rates
Unpacked, full resolution, frame sequential, 3-D format (that is each 100- or 120-Hz source frame contains a
single, full resolution, eye frame separated by VSYNCs, where an eye frame contains image data for a single
left or right eye; not both)
Minimum line rates that satisfy the high frame rates
To support 3-D operation, run the DLPC2607 device in Lock-to-VSYNC mode with 1× frame rate multiplication
(that is, no frame rate multiplication). Each DMD frame is displayed at the source frame rate in the order it is
received.
Because of the high frame rate of the source, the source line rate must be much higher than typical, but still
cannot exceed the rates defined in Parallel I/F Maximum Parallel Interface Horizontal Line Rate. The minimum
line rate is limited by the maximum frame rate and minimum total vertical blanking (TVB). 100- to 120-Hz
Operational Limitations provides a summary of the line rate range assuming the minimum TVB.
7.4 Programming
7.4.1 Serial Flash Interface
The DLPC2607 device uses an external SPI serial flash memory device for configuration support. The minimum
required size depends on the desired minimum number of sequences, CMT tables, and splash options while the
maximum supported is 16 Mb. Table 1 provides the list of the configuration options.
Table 1. Serial Flash Support Features by Density (1)
TARGET
FLASH
DENSITY (Mb)
(1)
(2)
(3)
QUANTITY OF FEATURES THAT CAN BE SUPPORTED
OPTICAL TEST
SPLASH
SCREENS
STANDARD
SPLASH
SCREENS
SERIES
DATA
SECTOR
4 Mb
0
1
1
1
8 Mb
0
3
1
1
16 Mb
1
4
1
1
UNIT DATA ODM DATA
SECTOR
SECTOR
DLP DISPLAY
SEQUENCES
(2)
CMT TABLES PER
SEQUENCE (3)
1
16
7
1
16
7
1
16
7
All rows in this table have passed DVT at TI.
Assumes individual DLP display sequences are limited to 5 KB each
An equal number of CMT tables are required for each sequence (CMT tables define the DeGamma Curve). The DLPC2607 device uses
a single SPI, employing SPI mode 0 protocol, operating at a frequency of 33.3 MHz. It supports two independent SPI chip selects.
However, the primary flash must be connected to SPI chip select 0 (SPICS0) because the auto-initialization routine is always executed
from the device connected to this chip select. The auto-initialization routine executed from flash consists of the following:
(a) The DLPC2607 device first uploads the size and location of the auto-initialization routine from address range 0x0000 through 0x0007
of the serial flash memory connected to SPICS0.
(b) The DLPC2607 device then uploads the actual auto-initialization routine to its ICP program memory from the serial flash memory
connected to SPICS0.
(c) The DLPC2607 device then executes an auto-init routine, which includes uploading default control parameter values, uploading
mailbox memory contents, turning on the sequence and LEDs, and then enabling the display.
(d) Upon completion of the auto-initialization routine, the DLPC2607 signals INIT DONE with GPIO4_INTF.
The DLPC2607 device supports any flash device that is compatible with these modes of operation. However, the
DLPC2607 device does not support the Normal (slow) Read Opcode, and thus cannot automatically adapt
protocol and clock rate based on the flash’s electronic signature ID. The flash instead uses a fixed SPI clock and
assumes certain attributes of the flash have been ensured by PCB design. The DLPC2607 device also assumes
the flash supports address auto-incrementing for all read operations. Table 2 and Table 3 list the specific
instruction OpCode and timing compatibility requirements for a DLPC2607 device compatible flash.
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Table 2. SPI Flash Instruction OpCode and Timing Compatibility Requirements
SPI FLASH COMMAND
OPCODE (hex)
ADDRESS BYTES
DUMMY BYTES
MIN CLOCK RATE
Fast READ (single output)
0x0B
3
1
33.3 MHz
All others
Can vary
Can vary
Can vary
33.3 MHz
Table 3. SPI Flash Key Timing Parameter Compatibility Requirements
MIN
Minimum chip select high time
Minimum output hold time
MAX
UNIT
300
ns
0
ns
Maximum output valid time
9
ns
Minimum data in setup time
5
ns
Minimum data in hold time
5
ns
The DLPC2607 device does not have any specific page, block, or sector size requirements, except that
programming with the I2C interface requires the use of page mode programming. However, if the user would like
to use a portion of the serial flash for storing external data (such as calibration data) with the I2C interface, then
the minimum sector size must be considered as it drives minimum erase size. Note that use of serial flash for
storing external data may impact the number of features that can be supported.
NOTE
The DLPC2607 device does not drive the HOLD (active low hold) or WP (active low write
protect) pins on the flash device. Tie these pins to a logic high on the PCB with an
external pullup.
The DLPC2607 device supports 1.8 V, 2.5 V, or 3.3 V serial flash devices. Some suggested devices would
include the W25Q16DWSSIG or MX25U4035. If a different flash device is used, Table 4 lists the minimum
performance specifications necessary.
Table 4. Specifications of Compatible SPI Serial Flash Devices
SPI Flash Timing Parameter
MIN
MAX
Minimum Chip Select High Time
Minimum Output Hold Time
300ns
0ns
Maximum Output Valid Time
9ns
Minimum Data in Setup Time
5ns
Minimum Data in Hold Time
Minimum Clock Rate
5ns
33.3MHz
7.4.2 Serial Flash Programming
The flash can be programmed through the DLPC2607 device over I2C (for directions, see the DLPC2607
Software Programmer's Guide, DLPU013) or by driving the SPI pins of the flash directly while the DLPC2607
device I/O are tri-stated. SPICLK, SPIDOUT, and SPICZ0 I/O can be tri-stated by holding RESET in a logic-low
state while power is applied. Note that SPICSZ1 is not tri-stated by this same action.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DLPC2607 controller supports reliable operation of .3-WVGA, .24-VGA and .2-nHD DMDs and must be
always used with the DMD to provide a reliable display solution for various data and video display applications.
The DMDs are spatial light modulators which reflect incoming light from an illumination source to one of two
directions, with the primary direction being into a projection or collection optic. Each application is derived
primarily from the optical architecture of the system and the format of the data coming into the DLPC2607.
Applications of interest include accessory projectors, projectors embedded in display devices like notebooks,
laptops, tablets, and set top box. Other applications include wearable (near-eye or head mounted) displays,
interactive display and low latency gaming display.
8.2 Typical Application
Figure 10 shows a typical accessory projector application. For this application, the DLPC2607 device is
controlled by a separate control processor (typically a MSP430) and the image data is received from a TVP5151
video decoder device. For this application, the ASIC supports periodic sources only. A common application when
using DLPC2607 controller is for creating an accessory Pico projector for a smartphone, tablets or any other
display source. The DLPC2607 in the accessory Pico projector typically receives images from a host processor
or a multimedia processor.
Figure 10. Typical Standalone Projector System Block Diagram
8.2.1 System Functional Modes
The application system has two functional modes (ON/OFF) controlled by a single pin PROJ_ON:
• When pin PROJ_ON is set high, the projector automatically powers up and an image is projected from the
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Typical Application (continued)
•
DMD.
When pin PROJ_ON is set low, the projector automatically powers down to save power.
8.2.2 Design Requirements
8.2.2.1 Reference Clock
The device requires an external reference clock to feed its internal PLL. This reference may be supplied by a
crystal or oscillator. For flexibility, the DLPC2607 device accepts either of two reference clock frequencies (see
Table 5), but both must have a maximum frequency variation of 200 ppm (including aging, temperature, and trim
component variation). When a crystal is used, the configuration requires several discrete components, as shown
in Figure 11.
PLL_REFCLK_O
PLL_REFCLK_I
CL = Crystal load capacitance (Farads)
CL1 = 2 x (CL - Cstray_pll_refclk_i)
R FB
CL2 = 2 x (CL - Cstray_pll_refclk_o)
RS
Where:
Cstray_pll_refclk_i = Sum of package and PCB
Crystal
stray capacitance at the crystal pin associated
with the ASIC pin pll_refclk_i.
Cstray_pll_refclk_o = Sum of package and PCB
stray capacitance at the crystal pin associated
with the ASIC pin pll_refclk_o.
C L1
C L2
Figure 11. Recommended Crystal Oscillator Configuration
Table 5. Crystal Port Characteristics
NOM
UNIT
PLL_REFCLK_I TO GND capacitance
PARAMETER
4.5
pF
PLL_REFCLK_O TO GND capacitance
4.5
pF
Table 6. Recommended Crystal Configuration
PARAMETER
RECOMMENDED
Crystal circuit configuration
Parallel resonant
Crystal type
Fundamental (first harmonic)
Crystal nominal frequency (See TSTPT_6 in the Pin Functions
table)
16.667 or 8.333
Crystal frequency tolerance (including accuracy, temperature, aging,
±200
and trim sensitivity)
UNIT
MHz
PPM
Crystal drive level
100 max
µW
Crystal equivalent series resistance (ESR)
80 max
Ω
Crystal load
12
pF
RS drive resistor (nominal)
100
RFB feedback resistor (nominal)
1
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MΩ
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Table 6. Recommended Crystal Configuration (continued)
PARAMETER
RECOMMENDED
UNIT
CL1 external crystal load capacitor
See Figure 11
pF
CL2 external crystal load capacitor
See Figure 11
pF
PCB layout
TI recommends a ground isolation ring around the crystal
If an external oscillator is used, then the oscillator output must drive the PLL_REFCLK_I pin on the DLPC2607
ASIC. Leave the PLL_REFCLK_O pins unconnected. An oscillator that provides a spread-spectrum clock
reduces EMI.
NOTE
The DLPC2607 device accepts between 0% to –2% spreading (that is, down spreading
only) with a modulation frequency between 20 kHz and 65 kHz and a triangular waveform.
Similar to the crystal option, the oscillator input frequency is limited to 16.667 or 8.333 MHz. To configure the
DLPC2607 device to accept the 8.333-MHz reference clock option, an external pullup resistor to VCC18 must be
applied to the TSTPT (6) pin. To configure the DLPC2607 device to accept the 16.667-MHz reference clock
option, leave the TSTPT (6) pin unconnected.
It is assumed that the external crystal or oscillator stabilizes within 50 ms after stable power is applied.
8.2.2.2 mDDR DRAM Compatibility
The following are the basic SDRAM compatibility requirements for the DLPC2607 SDRAM:
• SDRAM memory type: mDDR
• Size: 128 Mb minimum
• Organization: N × 16-bits wide × 4 banks
• Speed grade tCK: 6-ns max
• CAS latency (CL), tRCD, tRP parameters (clocks): 3, 3, 3
• Burst length options to include: Burst of 4
• Refresh period (full device): ≥64 ms
The following mDDR DRAM devices are recommended for use with the DLPC2607 device:
Table 7. Compatible mDDR DRAM Device Options (1)
SIZE (Mb)
ORGANIZATION
SPEED GRADE tCK
(4)
(ns)
CL, tRCD, tRP (Clocks)
(5)
128
8 M × 16
6
(3)
EDD25163HBH-6ELS-F
256
16 M × 16
6
(3)
256
16 M × 16
6
(3)
DVT (3)
VENDOR
No
Elpida
EDK1216CFBJ-60-F
Yes
Elpida
(1)
(2)
(3)
(4)
(5)
(6)
(2)
PART NUMBER
K4X56163PL-FGC6
(6)
No
Samsung
Yes
Samsung
K4X56163PN-FGC6
256
16 M × 16
6
(3)
Yes
Micron
MT46H16M16LFBF-6IT:H
256
16 M × 16
6
(3)
Yes
Hynix
H5MS2562JFR-J3M
256
16 M × 16
6
(3)
The DLPC2607 device does not use partial array self-refresh or temperature-compensated self-refresh options.
These part numbers reflect Pb-free package.
All these SDRAM devices appear compatible with the DLPC2607 device, but only those marked with 'yes' in the DVT column have been
validated on a TI internal reference design board. Those marked with 'no' can be used at the risk of the ODM.
A 6-ns speed grade corresponds to a 166-MHz mDDR device.
These devices are EOL and no replacement with the same footprint. Do not use these in new designs.
The manufacturer has issued an upcoming end of life notice on this device.
8.2.3 Detailed Design Procedure
For connecting together the DLPC2607 controller and the DMD, see the reference design schematic. Follow the
layout guidelines to achieve a reliable projector. The DLP system requires an optical module or light engine. An
optical OEM that specializes in designing optics for DLP projectors typically supplies the optical engine that has
the LED packages and the DMD mounted to it.
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8.2.3.1 Hot-Plug Usage
The DLPC2607 device provides fail-safe I/O on all host interface signals (signals powered by VCC_INTF). This
protection allows the device to drive these inputs high even when no I/O power is applied.
Under this condition, the DLPC2607 device does not load the input signal, nor draw excessive current that could
degrade ASIC reliability. For example, the I2C bus from the host to other components would not be affected by
powering off VCC_INTF to the DLPC2607 device. Note that TI recommends weak pullups or pulldowns on
signals feeding back to the host to avoid floating inputs.
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8.2.3.2
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Maximum Signal Transition Time
Unless otherwise noted, the maximum recommended 20% to 80% rise and fall time to avoid input buffer
oscillation is 10 ns. This applies to all DLPC2607 device input signals.
NOTE
The PARK input signal includes an additional small digital filter that ignores any inputbuffer transitions caused by a slower rise and fall time for up to 150 ns.
8.2.3.3
Configuration Control
The primary configuration control mechanism for the DLPC2607 device is the I2C interface. See the DLPC2607
Software Programmer's Guide, DLPU004, for details on how to configure and control the DLPC2607.
8.2.3.4 White Point Correction Light Sensor
With the addition of a light-to-voltage light sensor (such as a phototransistor) and a voltage comparator circuit,
the DLPC2607 device supports automatic white point correction and power control.
8.2.4 Application Curve
As the LED currents that are driven time-sequentially through the red, green, and blue LEDs are increased, the
brightness of the projector increases. This increase is somewhat non-linear, and the curve for typical white
screen lumens changes with LED currents is shown in Figure 12. For the LED currents shown, it is assumed that
the same current amplitude is applied to the red, green, and blue LEDs.
1.0
0.9
0.8
Luminance
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0
500
1000
1500
2000
Current (mA)
2500
3000
D001
Figure 12. Luminance vs Current
As with prior DLP electronics solutions, image data is 100% digital from the DLPC2607 device input port to the
image projected on to the display screen. The image stays in digital form and is never converted into an analog
signal. The DLPC2607 device processes the digital input image and converts the data into bit-plane format as
needed by the DMD. The DMD then reflects light to the screen using binary pulse-width modulation (PWM) for
each pixel mirror. The viewer’s eyes integrate this light to form brilliant, crisp images.
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9 Power Supply Recommendations
9.1 System Power Considerations
Table 8 provides a summary of the required power delivery requirements for DLPC2607 for various VCC_FLSH
and VCC_INTF power options.
Table 8. Configuration Based Power Supply Requirements
ASIC POWER RAIL
VCC_INTF
VCC_FLSH
VDD_PLL
(2)
(3)
(4)
NOMINAL VOLTAGE
(V)
TOTAL SUPPLY
MARGIN (1)
Video interface I/O
1.8, 2.5, or 3.3
±5%
Flash I/O
1.8, 2.5, or 3.3
±5%
USAGE
Internal PLL
VCC18
mDDR and DMD I/O
VDD10
ASIC core
(1)
(2)
(3)
(4)
1
±5%
1.8
±5%
1
±5%
Total supply margin = DC offset budget + AC noise budget
VCC_INTF is independent of all other supplies.
VCC_FLSH is independent of all other supplies.
When possible, TI recommends to use a tighter supply tolerance (±3%) for the power to the PLL in
order to improve system noise immunity.
9.2 System Power-Up and Power-Down Sequence
Although the DLPC2607 device requires an array of power supply voltages, (that is, VDD, VDD_PLL, VCC_18,
VCC_FLSH, and VCC_INTF), there are no restrictions regarding the relative order of power supply sequencing
to avoid damaging the DLPC2607 device. This is true for both power-up and power-down scenarios. Similarly
there is no minimum time between powering-up or powering-down the different supplies feeding the DLPC2607
device.
NOTE
Often, there are power sequencing requirements for devices that share the supplies with
the DLPC2607 device.
From a functional standpoint, there is one specific power-sequencing recommendation to ensure proper
operation. In particular, apply all ASIC power and allow it to reach the minimum specified voltage levels before
RESET is deasserted to ensure proper power-up initialization is performed. Ensure that all I/O power remains
applied as long as 1-V core power is applied and RESET is de-asserted.
NOTE
When VDD10 core power is applied but I/O power is not applied, additional leakage
current may be drawn.
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System Power-Up and Power-Down Sequence (continued)
Point at which ALL supplies
reach 95% of the their
specified nominal value.
VDD10 (1.0 V)
VCC_PLL (1.0 V)
VCC_INTF (1.8 to 3.3 V)
VCC_FLSH (1.8 to 3.3 V)
VCC18
PARKZ must be set high within
500 µs after RESETZ is released to
support Auto-initialization
The TI internal reference design board requires
VCC18 to remain active for a minimum of
100 ms after DMD_PWR_EN is de-asserted to
satisfy DMD power sequence requirements.
(1.8 V)
500 µs
max
PARKZ
DMD_PWR_EN
(ASIC output signal)
500 ±5 µs
PLL_REFCLK
RESETZ
I2C
(SCL,SDA)
GPIO4_INTF
(INIT_BUSY)
Per DMD
Power
Sequencing
Requirement
PLL_REFCLK may be
active before power is
applied
Tstable
100 ms min
GPIO4_INTF will be
driven high shortly
after reset is release
to indicate
Initialization Busy
0 µs
500 µs
Min
PARKZ must be set
low a min of 500 µs
before any power is
removed, before
PLL_REFCLK is
stopped and before
RESETZ is asserted
to allow time for the
DMD mirrors to be
Parked.
500 µs
Min
The min requirement to set RESETZ = 1 is anytime after
PLL_REFCLK becomes stable. For external oscillator
application this is oscillator dependent & for crystal
applications it is Crystal dependent.
I2C access CAN start immediately after GPIO4_INTF (INIT_BUSY flag)
goes low (this should occur within 100ms from the release of RESETZ
if the Motor Control function is not utilized. If Motor Control is
utilized it may take several seconds.)
Figure 13. Power-Up and Power-Down Timing
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9.3 System Power I/O State Considerations
Note that:
• If VCC18 I/O power is applied when VDD10 core power is not applied, then all mDDR (non-fail-safe) and nonmDDR (fail-safe) output signals associated with the VCC18 supply are in a high-impedance state.
• If VCC_INTF or VCC_FLSH I/O power is applied when VDD10 core power is not applied, then all output
signals associated with these inactive I/O supplies are in a high-impedance state.
• If VDD10 core power is applied but VCC_INTF or VCC_FLSH I/O power is not applied, then all output signals
associated with these inactive I/O supplies are in a high-impedance state.
• If VDD10 core power is applied but VCC18 I/O power is not applied, then all mDDR (non-fail-safe) and nonmDDR (fail-safe) output signals associated with the VCC18 I/O supply are in a high-impedance state.
However, if driven high externally, only the non-mDDR (fail-safe) output signals remain in a high-impedance
state, and the mDDR (non fail-safe) signals are shorted to ground through clamping diodes.
9.4 Power-Up Initialization Sequence
It is assumed that an external power monitor holds the DLPC2607 device in system reset during power-up. It
must do this by driving RESET to a logic low state. It should continue to assert system reset until all ASIC
voltages have reached minimum specified voltage levels, PARK is asserted high, and input clocks are stable.
During this time, most ASIC outputs are driven to an inactive state and all bidirectional signals are configured as
inputs to avoid contention. ASIC outputs that are not driven to an inactive state are tri-stated, which includes
DMD_PWR_EN, LEDDVR_ON, LED_SEL_0, LED_SEL_1, SPICLK, SPIDOUT, and SPICSZ0. After power is
stable and the PLL_REFCLK clock input to the DLPC2607 device is stable, then RESET should be deactivated
(set to a logic high). The DLPC2607 device then performs a power-up initialization routine that first locks its PLL,
followed by loading self configuration data from the external flash. Upon release of RESET, all DLPC2607 device
I/Os become active. Immediately following the release of RESET, the GPIO4_INTF signal is driven high to
indicate that the auto-initialization routine is in progress. Upon completion of the auto-initialization routine, the
DLPC2607 device drives GPIO4_INTF low to signal INITIALIZATION DONE (also known as INIT DONE).
NOTE
The host processor can start sending standard I2C commands after GPIO4 (INIT_DONE)
goes low, or a 100-ms timer expires in the host processor, whichever is earlier,
irrespective of whether the motor is enabled or not. However, before sending any
compound I2C commands at power-up, the host processor must wait until GPIO4
(INIT_DONE) goes low, irrespective of whether the motor control function is enabled or
not. Due to motor movement, the worst-case time to wait for GPIO4 to go low is when the
motor control function is enabled and system dependent; it may take several seconds.
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Power-Up Initialization Sequence (continued)
An active high pulse on GPIO4_INTF following the initialization
period will indicate an error condition has been detected. The
source of the error is reported in the system status.
RESETZ
100ms max
(INIT_BUSY)
(ERR IRQ)
GPIO4_INTF
0ms min
5ms max
GPIO4_INTF will be driven high within 5 ms
after reset is release to indicate AutoInitialization is Busy
3us min
I2C access to DLPC2607 should not start until GPIO4_INTF
(INIT_BUSY flag) goes low (this should occur within 100 ms
from the release of RESETZ if the Motor Control function is
not utilized. However, If Motor Control is utilized this may
take several seconds.)
I2C traffic
(SCL,SDA,CSZ)
Figure 14. Initialization Timeline
9.5 Power-Good (PARK) Support
The PARK signal operates as an early warning signal that alerts the controller 500 µs before DC supply voltages
have dropped below specifications. This allows the controller time to park the DMD, ensuring the integrity of
future operation. The reference clock continues to run. RESET remains deactivated for at least 500 µs after
PARK has been deactivated (set to a logic low) to allow the park operation to complete.
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10 Layout
10.1 Layout Guidelines
10.1.1 Internal ASIC PLL Power
TI recommends the following guidelines to achieve desired ASIC performance relative to the internal PLL. The
DLPC2607 device contains one internal PLL, which has a dedicated analog supply (VDD_PLL and VSS_PLL).
Isolate VDD_PLL power and VSS_PLL ground pins using an RC-filter consisting of two 50-Ω series ferrites and
two shunt capacitors (to widen the spectrum of noise absorption). TI recommends one 0.1-µF capacitor and that
the other is a 0.01-µF capacitor. Place all four components as close to the ASIC as possible; it is especially
important to keep the leads of the high-frequency capacitors as short as possible. Note that the user should
connect both capacitors across VDD_PLL and VSS_PLL on the ASIC side of the ferrites.
The PCB layout is critical to PLL performance. The ground and power domains are analog signals, and should
be treated as such to achieve minimum noise. Therefore, VDD_PLL must be a single trace from the DLPC2607
device to both capacitors, and then through the series ferrites to the power source. Ensure that the power and
ground traces are as short as possible, parallel to each other, and as close as possible to each other.
Signal VIA
PCB Pad
VIA to Common Analog
Digital Board Power Plane
ASIC Pad
11
VIA to Common Analog
Digital Board Ground Plane
12
13
14
15
A
Local
Decoupling
for the PLL
Digital Supply
G
1.0V
PWR
VDD_
PLL
Signal
Signal
Signal
H
VDD
VSS_
PLL
Signal
PLL _
REF
CLK_O
J
Signal
Signal
Signal
GND
0.1uF
0.01uF
FB
FB
PLL_
REF
CLK_I
K
Crystal Circuit
Figure 15. PLL Filter Layout
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Layout Guidelines (continued)
10.1.2 General Handling Guidelines for Unused CMOS-Type Pins
To avoid potentially damaging current caused by floating CMOS input-only pins, TI recommends to tie unused
ASIC input pins through a pullup resistor to their associated power supply or a pulldown to ground. For ASIC
inputs with internal pullup or pulldown resistors, it is unnecessary to add an external pullup or pulldown unless
specifically recommended.
NOTE
Internal pullup and pulldown resistors are weak so do not expect them to drive the
external line. The DLPC2607 device implements very few internal resistors and these are
noted in the pin list.
Never tie unused output-only pins directly to power or ground. These pins can be left open.
When possible, TI recommends that unused bidirectional I/O pins be configured to their output state such that
the pin can be left open. If this control is not available and the pins may become an input, then ensure they are
pulled-up (or pulled-down) using an appropriate, dedicated resistor.
10.1.3 SPI Signal Routing
The DLPC2607 device is designed to support two SPI slave devices, specifically, a serial flash and the
PMD1000. Given this requires routing associated SPI signals to two locations while attempting to operate at 33.3
MHz, ensure that reflections do not compromise signal integrity. TI recommends the following:
• Split the SPICLK PCB signal trace from the DLPC2607 source to each slave device into separate routes as
close to the DLPC2607 device as possible. Make the SPICLK trace length to each device equal in total
length.
• Split the SPIDOUT PCB signal trace from the DLPC2607 source to each slave device into separate routes as
close to the DLPC2607 device as possible. Make the SPIDOUT trace length to each device equal in total
length (that is, use the same strategy as SPICLK).
• Make the SPIDIN PCB signal trace from each slave device to the point where they intersect on the return to
the DLPC2607 device equal in length and as short as possible. Make sure they share a common trace back
to the DLPC2607 device.
• SPICSZ0 and SPICSZ1 do not require special treatment because they are dedicated signals which drive only
one device.
10.1.4 mDDR Memory and DMD Interface Considerations
High-speed interface waveform quality and timing on the DLPC2607 ASIC (that is, the mDDR memory I/F and
the DMD interface) depend on the total length of the interconnect system, the spacing between traces, the
characteristic impedance, etch losses, and how well matched the lengths are across the interface. Thus,
ensuring positive timing margin requires attention to many factors.
As an example, the DMD interface system timing margin can be calculated as follows:
Setup margin = (DLPC2607 output setup) – (DMD input setup) – (PCB routing mismatch) – (PCB SI degradation)
Hold-time margin = (DLPC2607 output hold) – (DMD input hold) – (PCB routing mismatch) – (PCB SI degradation)
(1)
where
•
PCB SI degradation is signal integrity degradation due to PCB effects. This includes things such as
simultaneously switching output (SSO) noise, crosstalk, and inter-symbol interference (ISI) noise.
(2)
The DLPC2607 device I/O timing parameters, as well as mDDR and DMD I/O timing parameters, can be found in
their corresponding data sheets. Similarly, PCB routing mismatch can be easily budgeted and met by controlled
PCB routing. However, PCB SI degradation is not so straight forward.
In an attempt to minimize the signal integrity analysis that would otherwise be required, the following PCB design
guidelines are provided as a reference of an interconnect system that satisfies both waveform quality and timing
requirements (accounting for both PCB routing mismatch and PCB SI degradation). Make sure to confirm any
variation from these recommendations with PCB signal integrity analysis or lab measurements.
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Layout Guidelines (continued)
10.1.5 PCB Design
• Configuration: Asymmetric dual stripline
• Etch thickness (T): 0.5 oz copper
• Single-ended signal impedance: 50 Ω (±10%)
• Single-ended signal impedance: 100-Ω differential (±10%)
SPACE
• Reference plane 1 is assumed to be a ground plane for proper return path.
• Reference plane 2 is assumed to be the I/O power plane or ground.
• Dielectric FR4, (Er): 4.2 (nominal)
• Signal trace distance to reference plane 1 (H1): 5 mil (nominal)
• Signal trace distance to reference plane 2 (H2): 34.2 mil (nominal)
Reference Plane 1
H1
W
T
W
Trace
S
Trace
H2
Dielectric Er
H2
T
Trace
Trace
H1
Reference Plane 2
Figure 16. PCB Stacking Geometries
38
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Layout Guidelines (continued)
10.1.6 General PCB Routing (Applies to All Corresponding PCB Signals)
Table 9. PCB Line and Spacing Recommendations (1)
(2) (3)
SINGLE-ENDED
SIGNALS
DIFFERENTIAL
PAIRS
UNIT
Escape routing in ball field
3
(0.762)
3
(0.762)
mil
(mm)
PCB etch – Outer layer data or control
7.25
(0.184)
4.5
(0.114)
mil
(mm)
PCB etch - Inner layer data or control
4.5
(0.114)
4.5
(0.114)
mil
(mm)
PCB etch clocks
4.5
(0.114)
4.5
(0.114)
mil
(mm)
PCB etch data or control
N/A
7.75 [1]
(0.305)
mil
(mm)
PCB etch clocks
N/A
7.75 [1]
(0.305)
mil
(mm)
Escape routing in ball field
3
(0.762)
3
(0.762)
mil
(mm)
PCB etch – Outer layer data or control
7.25
(0.184)
4.5
(0.114)
mil
(mm)
PCB etch - Inner layer data or control
4.5
(0.114)
4.5
(0.114)
mil
(mm)
PCB etch clocks
11
(0.279)
11
(0.279)
mil
(mm)
N/A
25
(0.635)
mil
(mm)
PARAMETER
APPLICATION
Line width (W)
Differential signal pair spacing (S)
Minimum line spacing to other signals
(S)
Maximum differential pair P-to-N
length mismatch
(1)
(2)
(3)
Total clock
Spacing may vary to maintain differential impedance requirements.
The DLPC2607 device only includes one differential signal pair – MEM0_CK_P and MEM0_CK_N.
These values are merely recommendations to achieve good signal integrity. The OEM is free to apply their own rules as long as they
maintain good signal integrity.
These PCB design guidelines are purposefully conservative to minimize potential signal integrity issues. Given
this device is targeted for low-cost, handheld application, there is a need to be more aggressive with these best
practices. TI highly recommends to perform a full-board-level signal integrity analysis, if these guidelines cannot
be followed. The DLPC2607 IBIS models are available for such analysis.
10.1.7 Maximum, Pin-to-Pin, PCB Interconnects Etch Lengths
Table 10. Max Pin-to-Pin PCB Interconnect Recommendations (1)
(2)
SIGNAL INTERCONNECT TOPOLOGY
BUS
SINGLE BOARD SIGNAL
ROUTING LENGTH
MULTI-BOARD SIGNAL
ROUTING LENGTH
UNIT
4 max
(101.5 max)
3.5 max
(88.91 max)
inch
(mm)
1.5 max
38.1 max
NA
inch
(mm)
1.5 max
(38.1 max)
NA
inch
(mm)
DMD
DMD_D(14:0), DMD_DCLK, DMD_TRC, DMD_SCTRL,
DMD_LOADB, DMD_OEZ DMD_DAD_STRB,
DMD_DAD_BUS, DMD_SAC_CLK and DMD_SAC_BUS
mDDR
MEM0_DQ(15:8), MEM0_UDM and MEM0_UDQS
mDDR
MEM0_DQ(7:0), MEM0_LDM and MEM0_LDQS
mDDR
(1)
(2)
Max signal routing length includes escape routing.
Multi-board DMD routing length is more restricted due to the impact of the connector.
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Table 10. Max Pin-to-Pin PCB Interconnect Recommendations() () (continued)
SIGNAL INTERCONNECT TOPOLOGY
BUS
MEM0_CK_P, MEM0_CK_N, MEM0_A(12:0),
MEM0_BA(1:0), MEM0_CKE, MEM0_CSZ,
MEM0_RASZ, MEM0_CASZ and MEM0_WEZ
SINGLE BOARD SIGNAL
ROUTING LENGTH
MULTI-BOARD SIGNAL
ROUTING LENGTH
2.5 max
(63.5 max)
N/A
UNIT
inch
(mm)
10.1.8 I/F Specific PCB Routing
Table 11. High-Speed PCB Signal Routing Matching Requirements (1)
(2) (3)
SIGNAL INTERCONNECT TOPOLOGY
IF
DMD
mDDR:
(1)
(2)
(3)
REFERENCE SIGNAL
MAX MISMATCH
UNIT
DMD_D(14:0), DMD_TRC,
DMD_SCTRL, DMD_LOADB,
DMD_OEZ
SINGLE GROUP
DMD_DCLK
±500
(±12.7)
mil
(mm)
DMD_DAD_STRB, DMD_DAD_BUS
DMD_DCLK
±750
(±19.05)
mil
(mm)
DMD_SAC_BUS
DMD_SAC_CLK
±750
(±19.05)
mil
(mm)
DMD_SAC_CLK
DMD_DCLK
±500
(±12.7)
mil
(mm)
MEM0_CLK_P
MEM0_CLK_N
±150
(±3.81)
mil
(mm)
Read/ Write Data Lower Byte:
MEM0_LDM and MEM0_DQ(7:0) 38.1 max
MEM0_LDQS
±300
(±7.62)
mil
(mm)
Read/ Write Data Upper Byte:
MEM0_UDM and MEM0_DQ(15:8)
MEM0_UDQS
±300
(±7.62)
mil
(mm)
Address and control:
MEM0_A(12:0), MEM0_BA(1:0),
MEM0_RASZ , MEM0_CASZ,
MEM0_WEZ, MEM0_CSZ,
MEM0_CKE
MEM0_CLK_P/
MEM0_CLK_N
±1000
(±25.4)
mil
(mm)
Data strobes:
MEM0_LDQS and MEM0_UDQS
MEM0_CLK_P/
MEM0_CLK_N
±300
(±7.62)
mil
(mm)
These values apply to PCB routing only. They do not include any internal package routing mismatch associated with the DLPC2607
device, DMD, or mDDR memory.
DMD data and control lines are DDR, whereas DMD_SAC and DMD_DAD lines are single data rate. Matching the DDR lines is more
critical and takes precedence over matching single data rate lines.
mDDR data, mask, and strobe lines are DDR, whereas address and control are single data rate. Matching the DDR lines is more critical
and takes precedence over matching single data rate lines.
10.1.9 Number of Layer Changes
• Single-ended signals: Minimize the number of layer changes.
• Differential signals: Individual differential pairs can be routed on different layers, but the signals of a given pair
must not change layers.
10.1.10 Stubs
Avoid stubs.
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10.1.11 Termination Requirements:
DMD I/F
Terminate all DMD I/F signals, with the exception of DMD_OEZ (specifically
DMD_D(14:0), DMD_DCLK, DMD_TRC, DMD_SCTRL, DMD_LOADB,
DMD_DAD_STRB, DMD_DAD_BUS, DMD_SAC_CLK, and DMD_SAC_BUS), at the
source with a 10- to 30-Ω series resistor. TI recommends a 30-Ω series resistor for most
applications because this minimizes overshoot, undershoot, and reduces EMI; however,
for systems that must operate below –20°C, it may be necessary to reduce this series
resistance to avoid narrowing the data eye too much under worse-case PVT conditions.
TI recommends IBIS simulations for this worse-case scenario.
mDDR memory I/F
mDDR differential
clock
Terminate each line, specifically MEM0_CK(P:N), at the source with a 30-Ω series
resistor. Terminate the pair with an external 100-Ω differential termination across the two
signals as close to the DRAM as possible. (It may be possible to use a 200-Ω differential
termination at the DRAM to save power while still providing sufficient signal integrity, but
this has not been validated.)
mDDR data, strobe,
and mask
Terminate MEM0_DQ(15:0), MEM0_LDM, MEM0_UDM, MEM0_LDQS, and
MEM0_UDQS with a 30-Ω series resistor located midway between the two devices.
mDDR address and
control
Terminate MEM0_A(12:0), MEM0_BA(1:0), MEM0_CKE, MEM0_CSZ, MEM0_RASZ,
MEM0_CASZ, and MEM0_WEZ at the source with a 30-Ω series resistor.
For applications where the routed distance of the mDDR or DMD signal can be maintained to a length of less
than 0.75 inches, this signal is short enough not be considered a transmission line and does not need a series
terminating resistor.
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10.2 Layout Example
Figure 17. PCB Layout Example
42
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 Device Nomenclature
11.1.2.1 Device Marking
TM
R
DLP
DPP2607
SC
2510465-AB
LLLLLLLL.ZZ
SSSSSYYWWQQ
1
2
3
4
Terminal A1 corner identifier
Marking definitions:
1. DLP device name
SC: Solder ball composition
e1: Indicates lead-free solder balls consisting of SnAgCu
G8: Indicates lead-free solder balls consisting of tin-silver-copper (SnAgCu) with silver content ≤1.5%
and that the mold compound meets TI's definition of green
2. TI part number
AB (1 or 2 alphanumeric) = ‘A’ corresponds to the TI device dash number. ‘B’ is reserved for an unqualified
device marking. All unqualified devices, including prototypes and skew lot samples, are labeled with the letter
'X' in the ‘B’ marking location (following the TI part number). ‘B’ is left blank for qualified devices.
3. LLLLLLLL.ZZ Foundry lot code for semiconductor wafers and lead-free solder ball marking
LLLLLLLL: Manufacturing lot code
ZZ: Lot split number
4. SSSSSYYWWQQ: Package and assembly information
SSSSS: Manufacturing site
YYWW: Date code (YY = Year :: WW = Week)
QQ: Qualification level option – engineering samples are marked in this field with an ES suffix.
For example, KOREA0914ES are engineering samples built in Korea the 14th week of 2009.
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11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
DLP, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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12.1 Package Option Addendum
12.1.1 Packaging Information
Orderable Device
DLPC2607ZVB
(1)
(2)
(3)
(4)
(5)
Status
(1)
ACTIVE
Package
Type
Package
Drawing
Pins
Package
Qty
NFBGA
ZVB
176
260
Eco Plan
TBD
(2)
Lead/Ball Finish
Call TI
MSL Peak Temp
(3)
Level-3-260C-168 HRS
Op Temp
(°C)
Device Marking (4) (5)
-30 to 85
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
space
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest
availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the
requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified
lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used
between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by
weight in homogeneous material)
space
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
space
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device
space
Multiple Device markings will be inside parentheses. Only on Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief
on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third
parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for
release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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