DLPC3439
DLPC3439
DLPS057E – NOVEMBER 2014 – REVISED FEBRUARY
2021
DLPS057E – NOVEMBER 2014 – REVISED FEBRUARY 2021
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DLPC3439 Display Controller
1 Features
3 Description
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The DLPC3439 digital controller, part of the DLP4710
(.47 1080p) chipset, supports reliable operation of the
DLP4710 digital micromirror device (DMD). The
DLPC3439 controller provides a convenient,
multifunctional interface between system electronics
and the DMD, enabling small form factor, low power,
and high resolution full HD displays.
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2 Applications
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DLP Signage
Mobile Projector
Mobile Smart TV
Smart home displays
Pico projectors
The chipsets include established resources to help
the user accelerate the design cycle, which include
production ready optical modules, optical module
manufacturers, and design houses.
Device Information (1)
PART NUMBER
PACKAGE
DLPC3439
(1)
NFBGA (201)
BODY SIZE (NOM)
13.00 × 13.00 mm2
For all available packages, see the orderable addendum at
the end of the data sheet.
SYSPWR
VLED
1.8 V
PROJ_ON
GPIO_8
I2C_0
2
I C
HOST_IRQ
To Flash (A)
•
Visit the getting started with TI DLP®Pico™ display
technology page, and view the programmer's guide to
learn how to get started.
SPI1
RESETZ
PARKZ
DLPA300x
RLIM
VDDLP12
VDD
Parallel
(28)
DLPC3439
SPI (4)
SPI0
VOFFSET,
VRESET
VCC_18
1.8 V
Illumination
optics
VBIAS,
VCC_INTF
VCC_FLSH
CTRL
Sub-LVDS
I2C_1
1.8 V
DMD
I2C_0
VCC_18
To Flash (B)
•
Display controller for DLP4710 (.47 1080p) DMD
– Two DLPC3439 controllers drive the DLP4710
DMD
– Supports input image sizes up to 1080p
– Low-power DMD interface with interface
training
Input frame rates Up to 120 Hz (60 Hz at 1080p
resolution)
Pixel data processing:
– IntelliBright™ suite of image processing
algorithms
• Content adaptive illumination control (CAIC)
• Local area brightness boost (LABB)
– Image resizing (scaling)
– Color coordinate adjustment
– Programmable degamma
– Active power management processing
– Color space conversion
– 4:2:2 to 4:4:4 chroma interpolation
24-Bit, input pixel interface support:
– Parallel Interface Protocol
– Pixel clock up to 155 MHz
– Multiple input pixel data format options
External flash support
Auto DMD parking at power down
Embedded frame memory (eDRAM)
System features:
– I2C control of device configuration
– Programmable splash screens
– Programmable LED current control
– One frame latency
Pair with DLPA3000 or DLPA3005 PMIC (power
management integrated circuit) and LED driver
VCC_INTF
VCC_FLSH
CTRL
Sub-LVDS
SPI0
SPI (4)
DLPC3439
RESETZ
PARKZ
PROJ_ON
GPIO_8
VDDLP12
VDD
Typical, Simplified System
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
Copyright
2021 Texas Instruments
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intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 3
5 Pin Configuration and Functions...................................6
6 Specifications................................................................ 14
6.1 Absolute Maximum Ratings...................................... 14
6.2 ESD Ratings............................................................. 14
6.3 Recommended Operating Conditions.......................15
6.4 Thermal Information..................................................15
6.5 Power Electrical Characteristics............................... 16
6.6 Pin Electrical Characteristics.................................... 17
6.7 Internal Pullup and Pulldown Electrical
Characteristics.............................................................19
6.8 DMD Sub-LVDS Interface Electrical
Characteristics.............................................................20
6.9 DMD Low-Speed Interface Electrical
Characteristics.............................................................21
6.10 System Oscillator Timing Requirements................. 23
6.11 Power Supply and Reset Timing Requirements......24
6.12 Parallel Interface Frame Timing Requirements.......25
6.13 Parallel Interface General Timing Requirements.... 26
6.14 Flash Interface Timing Requirements..................... 27
6.15 Other Timing Requirements.................................... 28
6.16 DMD Sub-LVDS Interface Switching
Characteristics.............................................................28
6.17 DMD Parking Switching Characteristics................. 28
6.18 Chipset Component Usage Specification............... 28
7 Detailed Description......................................................29
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7.1 Overview................................................................... 29
7.2 Functional Block Diagram......................................... 29
7.3 Feature Description...................................................30
7.4 Device Functional Modes..........................................44
7.5 Programming............................................................ 44
8 Application and Implementation.................................. 45
8.1 Application Information............................................. 45
8.2 Typical Application.................................................... 45
9 Power Supply Recommendations................................48
9.1 PLL Design Considerations...................................... 48
9.2 System Power-Up and Power-Down Sequence....... 48
9.3 Power-Up Initialization Sequence............................. 52
9.4 DMD Fast Park Control (PARKZ)..............................52
9.5 Hot Plug I/O Usage................................................... 53
10 Layout...........................................................................54
10.1 Layout Guidelines................................................... 54
10.2 Layout Example...................................................... 62
11 Device and Documentation Support..........................63
11.1 Device Support........................................................63
11.2 Related Documentation...........................................65
11.3 Related Links.......................................................... 65
11.4 Receiving Notification of Documentation Updates.. 65
11.5 Support Resources................................................. 65
11.6 Trademarks............................................................. 65
11.7 Electrostatic Discharge Caution.............................. 65
11.8 Glossary.................................................................. 65
12 Mechanical, Packaging, and Orderable
Information.................................................................... 66
12.1 Package Option Addendum.................................... 67
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DLPC3439
DLPS057E – NOVEMBER 2014 – REVISED FEBRUARY 2021
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (June 2019) to Revision E (February 2021)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• General datasheet formatting and ordering refresh ...........................................................................................1
• Deleted mention of mirror parking time from PARKZ pin description and moved to a specification table.......... 6
• Changed JTAG pin names from Reserved to proper names .............................................................................6
• Deleted support for adjustable DATAEN_CMD polarity ..................................................................................... 6
• Deleted mention of a specific 3D command ...................................................................................................... 6
• Deleted support for adjusting PCLK capture edge in software .......................................................................... 6
• Changed the description of how to use the CMP_OUT pin and corrected how the comparator must use
GPIO_10 (RC_CHARGE) instead of CMP_PWM ............................................................................................. 6
• Deleted support for CMP_PWM......................................................................................................................... 6
• Added note about VCC_INTF power up recommendations if slave devices are on the I2C bus ....................... 6
• Deleted mention of unsupported light sensor on GPIO_13 and GPIO_12 ........................................................ 6
• Deleted reference of the RC_CHARGE circuit being used for the light sensor and added reference of it being
used for the thermistor .......................................................................................................................................6
• Deleted reference of the LS_PWR circuit being used for the light sensor..........................................................6
• Deleted mention of the unsupported LABB output sample and hold sensor control signal................................ 6
• Clarified GPIO_03 - GPIO_01 pins are required to be used as a SPI1 port.......................................................6
• Deleted misleading note about GPIO pins defaulting to inputs ......................................................................... 6
• Added missing I/O definition 10 ......................................................................................................................... 6
• Deleted unneeded VCC_INTF and VCC_FLSH absolute maximum values ................................................... 14
• Added high voltage tolerant note to Absolute Maximum Ratings table ........................................................... 14
• Changed incorrect pin tolerance ......................................................................................................................15
• Changed Power Electrical Characteristics table to reflect updated power measurement values and
techniques ....................................................................................................................................................... 16
• Deleted reference to unsupported IDLE mode ................................................................................................ 16
• Added note that the power numbers vary depending on the utilized software................................................. 16
• Changed and fixed incorrect test conditions for current drive strengths...........................................................17
• Deleted redundant ǀVODǀ specification which is referenced in later sections.................................................... 17
• Added minimum and maximum values for VOH for I/O type 4.......................................................................... 17
• Added minimum and maximum values for VOL for I/O type 4...........................................................................17
• Deleted incorrect reference to 2.5V, 24mA drive ............................................................................................. 17
• Corrected I2C buffer test conditions..................................................................................................................17
• Deleted incorrect steady-state common mode voltage reference ................................................................... 17
• Changed high voltage tolerant I/O note to only refer to the I2C buffer and changed VCC to VCC_INTF......... 17
• Added |VOD| minimum and maximum values, and changed the typical value.................................................. 20
• Added high-level output voltage minimum and maximum values for the sub-LVDS DMD interface, deleted
redundant mention of specification, and changed the typical value. ............................................................... 20
• Added low-level output voltage minimum and maximum values for the sub-LVDS DMD interface, deleted
redundant mention of specification, and changed the typical value. ............................................................... 20
• Corrected the name of the DMD Low-Speed signals from inputs to outputs. ..................................................21
• Deleted VOH(DC) maximum and VOL(DC) minimum values. ............................................................................... 21
• Added note about DMD input specs being met if a proper series termination resistor is used ....................... 21
• Deleted reference of selecting unsupported oscillator frequency .................................................................... 23
• Corrected system oscillator clock period to match clock frequency ................................................................ 23
• Changed pulse duration percent spec from a maximum to a minimum ...........................................................23
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DLPS057E – NOVEMBER 2014 – REVISED FEBRUARY 2021
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Added condition for VDD rise time ...................................................................................................................24
Deleted the incorrect part of the tp_tvb definition............................................................................................... 25
Deleted unneeded total horizontal blanking equation ......................................................................................25
Changed minimum total vertical blanking equation ......................................................................................... 25
Increased maximum PCLK from 150MHz to 155MHz ..................................................................................... 26
Deleted reference to various signal's active edges being configurable ........................................................... 26
Changed the minimum flash SPI_CLK frequency............................................................................................ 27
Corrected flash interface clock period to match clock frequency .....................................................................27
Added Section 6.15 section to more clearly list signal transition time requirements........................................ 28
Changed DMD HS Clock switching rate from maximum to nominal and added accompanying clock
specification ..................................................................................................................................................... 28
Added Section 6.17 section.............................................................................................................................. 28
Added the Section 6.18 section to clarify chipset support requirements.......................................................... 28
Deleted reference to internal software tools and clarified how firmware affects the supported resolution and
frame rates .......................................................................................................................................................30
Clarified note about VSYNC_WE needing to remain active ............................................................................ 31
Deleted support for changing the clock active edge and clarified support of changing the sync active edge.. 31
Changed the DATAEN_CMD signal to not be optional .................................................................................... 31
Added information that the parallel interface isn't ready to accept data until the auto-initialization process is
completed......................................................................................................................................................... 34
Changed how the 500 ms startup time is described ........................................................................................34
Changed SPI flash key timing parameter access frequency minimum and maximum values..........................34
Changed maximum flash size supported from 16Mb to 128Mb ...................................................................... 34
Deleted SPI signal routing section ...................................................................................................................36
Deleted support for a light sensor integrated with the DLPC34xx controller ................................................... 38
Added missing timing definitions ..................................................................................................................... 39
Clarified that the mentioned SDR clock speed is the typical value...................................................................42
Changed how the DMD Sub-LVDS Interface requirements are mentioned .....................................................42
Deleted DMD Interface stack-up image ...........................................................................................................42
Deleted equation concerning DMD interface system timing margin ................................................................ 42
Changed the description of how PROJ_ON affects the power supplies ..........................................................46
Changed which signals are listed as tri-stated at power up and which signals are pulled low ........................ 52
Changed 1-oz copper plane recommendation .................................................................................................54
Deleted reference to unsupported option of variable frequency reference clock..............................................55
Added additional DMD data and DMD clock signal matching requirements ................................................... 58
Changed maximum mismatch from ±0.1" to ±1.0" ...........................................................................................58
Changed incorrect signal matching requirement table note............................................................................. 58
Changed differential signal layer change to a recommendation.......................................................................60
Changed wording requiring no more than two vias on certain DMD signals ................................................... 60
Changed device markings image and definitions ............................................................................................ 63
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DLPC3439
DLPS057E – NOVEMBER 2014 – REVISED FEBRUARY 2021
Changes from Revision C (December 2016) to Revision D (June 2019)
Page
• Changed mirror parking time from "500 μs" to "20 ms" for PARKZ description in Pin Functions table...............6
Changes from Revision B (January 2016) to Revision C (December 2016)
Page
• Updated V(VCC18) maximum from 18 mA to 62 mA in Section 6.5 ................................................................... 16
• Updated V(VCC18) + V(VCC_INTF) + V(VCC_FLSH) maximum from 22.5 mA to 66.5 mA in Section 6.5 ................. 16
• Modified description in Section 7.1 to account for two DLPC3439 controllers................................................. 29
• Included additional DLPC3439 compatible SPI flash device options in Table 7-6 ...........................................34
• Added Section 7.3.7 ........................................................................................................................................ 39
• Updated Section 11.1.2.1 image, changed manufacturing site to generic code...............................................63
• In Section 11.1.2.1 note, updated link for DLPC3439 resolutions on the DMD supported per part number to
refer to Table 7-1 ..............................................................................................................................................63
• Added DLPA3000 to Chipset Documentation table.......................................................................................... 65
• Added MSL Peak Temp to Section 12.1.1 ....................................................................................................... 67
Changes from Revision A (June 2015) to Revision B (January 2016)
Page
• Corrected device markings .............................................................................................................................. 63
• Updated image and table .................................................................................................................................63
Changes from Revision * (February 2014) to Revision A (September 2014)
Page
• Updated Section 11.1.2.1 image and table.......................................................................................................63
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DLPS057E – NOVEMBER 2014 – REVISED FEBRUARY 2021
5 Pin Configuration and Functions
Figure 5-1. ZEZ Package 201-Pin NFBGA Bottom View
1
2
3
4
5
6
7
8
9
10
11
12
A
DMD_LS_C DMD_LS_W DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_CLK_ DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_W
CMP_OUT
P
LK
DATA
DATAH_P DATAG_P
DATAF_P
DATAE_P
DATAD_P
DATAC_P
DATAB_P
DATAA_P
B
DMD_DEN_ DMD_LS_R DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_CLK_ DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_W
N
ARSTZ
DATA
DATAH_N DATAG_N
DATAF_N
DATAE_N
DATAD_N
DATAC_N
DATAB_N
DATAA_N
SPI0_DIN
13
SPI0_CLK
14
15
SPI0_CSZ0 CMP_PWM
SPI0_DOUT LED_SEL_1 LED_SEL_0
C
DD3P
DD3N
VDDLP12
VSS
VDD
VSS
VCC
VSS
VCC
HWTEST_E
N
RESETZ
SPI0_CSZ1
PARKZ
GPIO_00
GPIO_01
D
DD2P
DD2N
VDD
VCC
VDD
VSS
VDD
VSS
VDD
VSS
VCC_FLSH
VDD
VDD
GPIO_02
GPIO_03
E
DCLKP
DCLKN
VDD
VSS
VCC
VSS
GPIO_04
GPIO_05
F
DD1P
DD1N
RREF
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VDD
GPIO_06
GPIO_07
G
DD0P
DD0N
VSS_PLLM
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
GPIO_08
GPIO_09
H
PLL_REFCL
VDD_PLLM VSS_PLLD
K_I
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
GPIO_10
GPIO_11
J
PLL_REFCL
VDD_PLLD
K_O
VSS
VDD
VSS
VSS
VSS
VSS
VSS
VDD
VSS
GPIO_12
GPIO_13
VSS
VSS
VSS
VSS
VSS
VSS
VCC
GPIO_14
GPIO_15
VDD
VDD
GPIO_16
GPIO_17
VSS
JTAGTMS1
GPIO_18
GPIO_19
JTAGTDO1
TSTPT_6
TSTPT_7
K
PDATA_1
PDATA_0
VDD
VSS
L
PDATA_3
PDATA_2
VSS
VDD
M
PDATA_5
PDATA_4
VCC_INTF
VSS
N
PDATA_7
PDATA_6
VCC_INTF
P
VSYNC_WE
DATEN_CM
D
PCLK
PDATA_11
R
PDATA_8
PDATA_9
PDATA_10
PDATA_12
VSS
VDD
VCC_INTF
VSS
VDD
VDD
3DR
VCC_INTF
HOST_IRQ
IIC0_SDA
IIC0_SCL
PDATA_13
PDATA_15
PDATA_17
PDATA_19
PDATA_21
PDATA_23
PDATA_14
PDATA_16
PDATA_18
PDATA_20
PDATA_22
IIC1_SDA
PDM_CVS_
HSYNC_CS
TE
VCC
JTAGTMS2 JTAGTDO2
JTAGTRSTZ
JTAGTCK
JTAGTDI
TSTPT_4
TSTPT_5
IIC1_SCL
TSTPT_0
TSTPT_1
TSTPT_2
TSTPT_3
Note: The lower image view is from the top.
Figure 5-2. 13 mm × 13 mm Package – VF Ball Grid Array
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Table 5-1. Test Pins and General Control
PIN
NAME
HWTEST_EN
NO.
C10
I/O
TYPE(4)
DESCRIPTION
I
6
Manufacturing test enable signal. Connect this signal directly to ground on the
PCB for normal operation.
PARKZ
C13
I
6
DMD fast park control (active low Input with a hysteresis buffer). This signal is
used to quickly park the DMD when loss of power is imminent. The longest
lifetime of the DMD may not be achieved with the fast park operation;
therefore, this signal is intended to only be asserted when a normal park
operation is unable to be completed. The PARKZ signal is typically provided
from the DLPAxxxx interrupt output signal.
JTAGTCK
P12
I
6
TI internal use. Leave this pin unconnected.
JTAGTDI
P13
I
6
TI internal use. Leave this pin unconnected.
JTAGTDO1
N13(1)
O
1
TI internal use. Leave this pin unconnected.
JTAGTDO2
N12(1)
O
1
TI internal use. Leave this pin unconnected.
JTAGTMS1
M13
I
6
TI internal use. Leave this pin unconnected.
JTAGTMS2
N11
I
6
TI internal use. Leave this pin unconnected.
6
TI internal use.
This pin must be tied to ground, through an external resistor for normal
operation. Failure to tie this pin low during normal operation can cause start
up and initialization problems.(2)
6
Power-on reset (active low input with a hysteresis buffer). Self-configuration
starts when a low-to-high transition is detected on RESETZ. All controller
power and clocks must be stable before this reset is de-asserted. No signals
are in their active state while RESETZ is asserted. This pin is typically
connected to the RESET_Z pin of the DLPA300x.
JTAGTRSTZ
RESETZ
P11
C11
I
I
TSTPT_0
R12
I/O
1
TSTPT_1
R13
I/O
1
TSTPT_2
R14
I/O
1
TSTPT_3
R15
I/O
1
TSTPT_4
P14
I/O
1
TSTPT_5
P15
I/O
1
TSTPT_6
N14
I/O
1
TSTPT_7
N15
I/O
1
(1)
(2)
(3)
(4)
Test pins (includes weak internal pulldown). Pins are tri-stated while RESETZ
is asserted low. Sampled as an input test mode selection control
approximately 1.5 µs after de-assertion of RESETZ, and then driven as
outputs.(2) (3)
Normal use: reserved for test output. Leave open for normal use.
Note: An external pullup may put the DLPC34xx in a test mode. See Section
7.3.8 for more information.
If the application design does not require an external pullup, and there is no external logic that can overcome the weak internal
pulldown resistor, then this I/O pin can be left open or unconnected for normal operation. If the application design does not require an
external pullup, but there is external logic that might overcome the weak internal pulldown resistor, then an external pulldown is
recommended to ensure a logic low.
External resistor must have a value of 8 kΩ or less to compensate for pins that provide internal pullup or pulldown resistors.
If the application design does not require an external pullup and there is no external logic that can overcome the weak internal
pulldown, then the TSTPT I/O can be left open (unconnected) for normal operation. If operation does not call for an external pullup, but
there is external logic that might overcome the weak internal pulldown resistor, then an external pulldown resistor is recommended to
ensure a logic low.
See Table 5-10 for type definitions.
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Table 5-2. Parallel Port Input (1) (2)
PIN
NAME
NO.
I/O
Type(4)
DESCRIPTION
PARALLEL RGB MODE
PCLK
P3
I
10
Pixel clock
PDM_CVS_TE
N4
I/O
5
Parallel data mask. Programable polarity with
default of active high. Optional signal.
VSYNC_WE
P1
I
10
Vsync(3)
HSYNC_CS
N5
I
10
Hsync(3)
DATAEN_CMD
P2
I
10
Data valid
PDATA_0
PDATA_1
PDATA_2
PDATA_3
PDATA_4
PDATA_5
PDATA_6
PDATA_7
K2
K1
L2
L1
M2
M1
N2
N1
(TYPICAL RGB 888)
I
10
Blue (bit weight 1)
Blue (bit weight 2)
Blue (bit weight 4)
Blue (bit weight 8)
Blue (bit weight 16)
Blue (bit weight 32)
Blue (bit weight 64)
Blue (bit weight 128)
(TYPICAL RGB 888)
PDATA_8
PDATA_9
PDATA_10
PDATA_11
PDATA_12
PDATA_13
PDATA_14
PDATA_15
R1
R2
R3
P4
R4
P5
R5
P6
PDATA_16
PDATA_17
PDATA_18
PDATA_19
PDATA_20
PDATA_21
PDATA_22
PDATA_23
R6
P7
R7
P8
R8
P9
R9
P10
I
10
Green (bit weight 1)
Green (bit weight 2)
Green (bit weight 4)
Green (bit weight 8)
Green (bit weight 16)
Green (bit weight 32)
Green (bit weight 64)
Green (bit weight 128)
(TYPICAL RGB 888)
3DR
(1)
(2)
(3)
(4)
8
N6
I
I
10
Red (bit weight 1)
Red (bit weight 2)
Red (bit weight 4)
Red (bit weight 8)
Red (bit weight 16)
Red (bit weight 32)
Red (bit weight 64)
Red (bit weight 128)
10
3D reference
• For 3D applications: left or right 3D reference
(left = 1, right = 0). To be provided by the host.
Must transition in the middle of each frame (no
closer than 1 ms to the active edge of VSYNC)
• If a 3D application is not used, pull this input
low through an external resistor.
PDATA(23:0) bus mapping depends on pixel format and source mode. See later sections for details.
Connect unused inputs to ground or pulldown to ground through an external resistor (8 kΩ or less).
VSYNC and HSYNC polarity can be adjusted by software.
See Table 5-10 for type definitions.
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Table 5-3. DSI Input Data and Clock
PIN
NAME
NO.
DCLKN
DCLKP
E2
E1
DD0N
DD0P
DD1N
DD1P
DD2N
DD2P
DD3N
DD3P
G2
G1
F2
F1
D2
D1
C2
C1
RREF
F3
(1)
I/O
Type(1)
DESCRIPTION
Unused; leave unconnected and floating
—
See Table 5-10 for type definitions.
Table 5-4. DMD Reset and Bias Control
PIN
NAME
NO.
I/O
TYPE(1)
DESCRIPTION
DMD_DEN_ARSTZ
B1
O
2
DMD driver enable (active high). DMD reset (active low). When
corresponding I/O power is supplied, the controller drives this signal low
after the DMD is parked and before power is removed from the DMD. If the
1.8-V power to the DLPC34xx is independent of the 1.8-V power to the
DMD, then TI recommends including a weak, external pulldown resistor to
hold the signal low in case DLPC34xx power is inactive while DMD power
is applied.
DMD_LS_CLK
A1
O
3
DMD, low speed (LS) interface clock
DMD_LS_WDATA
A2
O
3
DMD, low speed (LS) serial write data
DMD_LS_RDATA
B2
I
6
DMD, low speed (LS) serial read data
(1)
See Table 5-10 for type definitions.
Table 5-5. DMD Sub-LVDS Interface
PIN
NAME
NO.
I/O
TYPE(1)
DESCRIPTION
DMD_HS_CLK_P
DMD_HS_CLK_N
A7
B7
O
4
DMD high speed (HS) interface clock
DMD_HS_WDATA_H_P
DMD_HS_WDATA_H_N
DMD_HS_WDATA_G_P
DMD_HS_WDATA_G_N
DMD_HS_WDATA_F_P
DMD_HS_WDATA_F_N
DMD_HS_WDATA_E_P
DMD_HS_WDATA_E_N
DMD_HS_WDATA_D_P
DMD_HS_WDATA_D_N
DMD_HS_WDATA_C_P
DMD_HS_WDATA_C_N
DMD_HS_WDATA_B_P
DMD_HS_WDATA_B_N
DMD_HS_WDATA_A_P
DMD_HS_WDATA_A_N
A3
B3
A4
B4
A5
B5
A6
B6
A8
B8
A9
B9
A10
B10
A11
B11
O
4
DMD sub-LVDS high speed (HS) interface write data lanes. The true
numbering and application of the DMD_HS_WDATA pins depend on the
software configuration. See Table 7-9.
(1)
See Table 5-10 for type definitions.
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Table 5-6. Peripheral Interface (1)
PIN
NAME
NO.
I/O
TYPE(3)
DESCRIPTION
CMP_OUT
A12
I
6
Successive approximation ADC (analog-to-digital converter) comparator output
(DLPC34xx Input). To implement, use a successive approximation ADC with a
thermistor feeding one input of the external comparator and the DLPC34xx
controller GPIO_10 (RC_CHARGE) pin driving the other side of the comparator.
It is recommended to use the DLPAxxxx to achieve this function. CMP_OUT
must be pulled-down to ground if this function is not used. (hysteresis buffer)
CMP_PWM
A15
O
1
TI internal use. Leave this pin unconnected.
9
Host interrupt (output)
HOST_IRQ indicates when the DLPC34xx auto-initialization is in progress and
most importantly when it completes.
This pin is tri-stated during reset. An external pullup must be included on this
signal.
HOST_IRQ(2)
N8
O
IIC0_SCL(4)
N10
I/O
7
I2C slave (port 0) SCL (bidirectional, open-drain signal with input hysteresis):
This pin requires an external pullup resistor. The slave I2C I/Os are 3.6-V tolerant
(high-voltage-input tolerant) and are powered by VCC_INTF (which can be 1.8,
2.5, or 3.3 V). External I2C pullups must be connected to a host supply with an
equal or higher supply voltage, up to a maximum of 3.6 V (a lower pullup supply
voltage does not typically satisfy the VIH specification of the slave I2C input
buffers).
IIC1_SCL
R11
I/O
8
TI internal use. TI recommends an external pullup resistor.
IIC0_SDA(4)
N9
I/O
7
I2C slave (port 0) SDA. (bidirectional, open-drain signal with input hysteresis):
This pin requires an external pullup resistor. The slave I2C port is the control port
of controller. The slave I2C I/O pins are 3.6-V tolerant (high-volt-input tolerant)
and are powered by VCC_INTF (which can be 1.8, 2.5, or 3.3 V). External I2C
pullups must be connected to a host supply with an equal or higher supply
voltage, up to a maximum of 3.6 V (a lower pullup supply voltage does not
typically satisfy the VIH specification of the slave I2C input buffers).
IIC1_SDA
R10
I/O
8
TI internal use. TI recommends an external pullup resistor.
LED enable select. Automatically controlled by the DLPC34xx programmable
DMD sequence
LED_SEL_0
B15
O
1
LED_SEL(1:0)
00
01
10
11
Enabled LED
None
Red
Green
Blue
LED_SEL_1
B14
O
1
The controller drives these signals low when RESETZ is asserted and the
corresponding I/O power is supplied. The controller continues to drive these
signals low throughout the auto-initialization process. A weak, external pulldown
resistor is recommended to ensure that the LEDs are disabled when I/O power is
not applied.
SPI0_CLK
A13
O
13
SPI (Serial Peripheral Interface) port 0, clock. This pin is typically connected to
the flash memory clock.
SPI0_CSZ0
A14
O
13
SPI port 0, chip select 0 (active low output). This pin is typically connected to the
flash memory chip select.
TI recommends an external pullup resistor to avoid floating inputs to the external
SPI device during controller reset assertion.
SPI0_CSZ1
C12
O
13
SPI port 0, chip select 1 (active low output). This pin typically remains unused.
TI recommends an external pullup resistor to avoid floating inputs to the external
SPI device during controller reset assertion.
SPI0_DIN
B12
I
12
Synchronous serial port 0, receive data in. This pin is typically connected to the
flash memory data out.
SPI0_DOUT
B13
O
13
Synchronous serial port 0, transmit data out. This pin is typically connected to
the flash memory data in.
(1)
(2)
(3)
10
External pullup resistor must be 8 kΩ or less.
For more information about usage, see Section 7.3.2.
See Table 5-10 for type definitions.
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When VCC_INTF is powered and VDD is not powered, the controller may drive the IIC0_xxx pins low which prevents communication
on this I2C bus. Do not power up the VCC_INTF pin before powering up the VDD pin for any system that has additional slave devices
on this bus.
Table 5-7. GPIO Peripheral Interface (1)
PIN
I/O
TYPE(1)
M15
I/O
1
HBT_ODAT (Output): Required to be connected to the second DLPC3439 controller's HBT_IDAT
(GPIO_17) input pin.
GPIO_18
M14
I/O
1
HBT_OCLK (Output): Required to be connected to the second DLPC3439 controller's HBT_ICLK
(GPIO_16) input pin
GPIO_17
L15
I/O
1
HBT_IDAT (Input): Required to be connected to the second DLPC3439 controller's HBT_ODAT
(GPIO_19) output pin
GPIO_16
L14
I/O
1
HBT_ICLK (Input): Required to be connected to the second DLPC3439 controller's HBT_OCLK
(GPIO_18) outputpin.
GPIO_15
K15
I/O
1
DA_SYNC (BiDir): Required to be connected to the second DLPC3439 controller's DA_SYNC
(GPIO_15) pin.
GPIO_14
K14
I/O
1
SEQ_SYNC (BiDir): Required to be connected to the second DLPC3439 controller's SEQ_SYNC
(GPIO_14) pin with a 7.87k pullup resistor to VCC18.
GPIO_13
J15
I/O
1
General purpose I/O 13 (hysteresis buffer). Optional GPIO. If unused TI recommends this pin be
configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external
pullup or pulldown to avoid a floating GPIO input.
GPIO_12
J14
I/O
1
General purpose I/O 12 (hysteresis buffer). Optional GPIO. If unused TI recommends this pin be
configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external
pullup or pulldown to avoid a floating GPIO input.
1
General purpose I/O 11 (hysteresis buffer). Options:
1. Thermistor power enable (output). Turns on the power to the thermistor when it is used and
enabled.
2. Optional GPIO. If unused TI recommends this pin be configured as a logic zero GPIO output and
left unconnected. Otherwise this pin requires an external pullup or pulldown to avoid a floating
GPIO input.
NAME
NO.
GPIO_19
GPIO_11
H15
I/O
DESCRIPTION(2)
GPIO_10
H14
I/O
1
General Purpose I/O 10 (hysteresis buffer). Options:
1. RC_CHARGE (output): Intended to feed the RC charge circuit of the thermistor interface.
2. Optional GPIO. If unused TI recommends this pin be configured as a logic zero GPIO output and
left unconnected. Otherwise this pin requires an external pullup or pulldown to avoid a floating
GPIO input.
GPIO_09
G15
I/O
1
General purpose I/O 09 (hysteresis buffer). Optional GPIO. If unused TI recommends this pin be
configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external
pullup or pulldown to avoid a floating GPIO input.
GPIO_08
G14
I/O
1
GPIO_07
F15
I/O
1
General purpose I/O 07 (hysteresis buffer). If unused TI recommends this pin be configured as a logic
zero GPIO output and left unconnected. Otherwise this pin requires an external pullup or pulldown to
avoid a floating GPIO input.
GPIO_06
F14
I/O
1
General purpose I/O 06 (hysteresis buffer). Optional GPIO. If unused TI recommends this pin be
configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external
pullup or pulldown to avoid a floating GPIO input.
GPIO_05
E15
I/O
1
General purpose I/O 05 (hysteresis buffer). Optional GPIO. If unused TI recommends this pin be
configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external
pullup or pulldown to avoid a floating GPIO input.
GPIO_04
E14
I/O
1
MST_SLVZ (Input): Master or slave controller identifier signal (Master = 1, Slave = 0).
GPIO_03
D15
I/O
1
General purpose I/O 03 (hysteresis buffer). SPI1_CSZ0 (active low output): SPI1 chip select 0 signal.
This pin is typically connected to the DLPAxxxx SPI_CSZ pin. Requires an external pullup resistor to
deactivate this signal during reset and auto-initialization processes.
GPIO_02
D14
I/O
1
General purpose I/O 02 (hysteresis buffer). SPI1_DOUT (output): SPI1 data output signal. This pin is
typically connected to the DLPAxxxx SPI_DIN pin.
General purpose I/O 08 (hysteresis buffer). Normal mirror parking request (active low): To be driven
by the PROJ_ON output of the host. A logic low on this signal causes the DLPC34xx to PARK the
DMD, but it does not power down the DMD (the DLPAxxxx does that instead). The minimum high
time is 200 ms. The minimum low time is 200 ms.
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Table 5-7. GPIO Peripheral Interface (1) (continued)
PIN
I/O
TYPE(1)
DESCRIPTION(2)
C15
I/O
1
General purpose I/O 01 (hysteresis buffer). SPI1_CLK (output): SPI1 clock signal. This pin is typically
connected to the DLPAxxxx SPI_CLK pin.
C14
I/O
1
General purpose I/O 00 (hysteresis buffer). SPI1_DIN (input): SPI1 data input signal. This pin is
typically connected to the DLPAxxxx SPI_DOUT pin.
NAME
NO.
GPIO_01
GPIO_00
(1)
(2)
GPIO pins must be configured through software for input, output, bidirectional, or open-drain operation. Some GPIO pins have one or
more alternative use modes, which are also software configurable. An external pullup resistor is required for each signal configured as
open-drain.
General purpose I/O for the DLPC3439 controller. These GPIO pins are software configurable.
Table 5-8. Clock and PLL Support
PIN
NAME
NO.
I/O
TYPE(1)
DESCRIPTION
PLL_REFCLK_I
H1
I
11
Reference clock crystal input. If an external oscillator is used instead of a crystal, use
this pin as the oscillator input.
PLL_REFCLK_O
J1
O
5
Reference clock crystal return. If an external oscillator is used instead of a crystal,
leave this pin unconnected (floating with no added capacitive load).
(1)
See Table 5-10 for type definitions.
Table 5-9. Power and Ground
PIN
I/O
TYPE
VDD
C5, D5, D7,
D12, J4,
J12, K3, L4,
L12, M6,
M9, D9,
D13, F13,
H13, L13,
M10, D3, E3
—
PWR
Core 1.1-V power (main 1.1 V)
VDDLP12
C3
—
PWR
Reserved – tie to the VDD rail
VSS
C4, D6, D8,
D10, E4,
E13, F4, G4,
G12, H4,
H12, J3,
J13, K4,
K12, L3, M4,
M5, M8,
M12, G13,
C6, C8, F6,
F7, F8, F9,
F10, G6,
G7, G8, G9,
G10, H6,
H7, H8, H9,
H10, J6, J7,
J8, J9, J10,
K6, K7, K8,
K9, K10
—
GND
Core ground (eDRAM, I/O ground, thermal ground)
VCC18
C7, C9, D4,
E12, F12,
K13, M11
—
PWR
All 1.8-V I/O power:
(1.8-V power supply for all I/O pins except the host or parallel interface
and the SPI flash interface. This includes RESETZ, PARKZ, LED_SEL,
CMP_OUT, GPIO, IIC1, TSTPT, and JTAG pins)
VCC_INTF
M3, M7, N3,
N7
—
PWR
Host or parallel interface I/O power: 1.8 V to 3.3 V (Includes IIC0, PDATA,
video syncs, and HOST_IRQ pins)
NAME
12
NO.
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Table 5-9. Power and Ground (continued)
PIN
NAME
NO.
I/O
TYPE
DESCRIPTION
VCC_FLSH
D11
—
PWR
Flash interface I/O power: 1.8 V to 3.3 V
(Dedicated SPI0 power pin)
VDD_PLLM
H2
—
PWR
MCG PLL (master clock generator phase lock loop) 1.1-V power
VSS_PLLM
G3
—
RTN
MCG PLL return
VDD_PLLD
J2
—
PWR
DCG PLL (DMD clock generator phase lock loop) 1.1-V power
VSS_PLLD
H3
—
RTN
DCG PLL return
Table 5-10. I/O Type Subscript Definition
I/O
SUBSCRIPT
DESCRIPTION
SUPPLY REFERENCE
ESD STRUCTURE
1
1.8-V LVCMOS I/O buffer with 8-mA drive
Vcc18
ESD diode to GND and supply rail
2
1.8-V LVCMOS I/O buffer with 4-mA drive
Vcc18
ESD diode to GND and supply rail
3
1.8-V LVCMOS I/O buffer with 24-mA drive
Vcc18
ESD diode to GND and supply rail
4
1.8-V sub-LVDS output with 4-mA drive
Vcc18
ESD diode to GND and supply rail
5
1.8-V, 2.5-V, 3.3-V LVCMOS with 4-mA drive
Vcc_INTF
ESD diode to GND and supply rail
6
1.8-V LVCMOS input
7
1.8-V, 2.5-V, 3.3-V I2C with 3-mA drive
8
1.8-V I2C with 3-mA drive
9
1.8-V, 2.5-V, 3.3-V LVCMOS with 8-mA drive
10
Reserved
11
Vcc18
ESD diode to GND and supply rail
Vcc_INTF
ESD diode to GND and supply rail
Vcc18
ESD diode to GND and supply rail
Vcc_INTF
ESD diode to GND and supply rail
1.8-V, 2.5-V, 3.3-V LVCMOS input
Vcc_INTF
ESD diode to GND and supply rail
12
1.8-V, 2.5-V, 3.3-V LVCMOS input
Vcc_FLSH
ESD diode to GND and supply rail
13
1.8-V, 2.5-V, 3.3-V LVCMOS with 8-mA drive
Vcc_FLSH
ESD diode to GND and supply rail
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted)(1)
MIN
MAX
UNIT
SUPPLY VOLTAGE(2)
V(VDD)
–0.3
1.21
V
V(VDDLP12)
–0.3
1.32
V
V(VCC18)
–0.3
1.96
V
DMD Sub-LVDS Interface (DMD_HS_CLK_x and DMD_HS_WDATA_x_y)
–0.3
1.96
V
V(VCC_INTF)
–0.3
3.60
V
V(VCC_FLSH)
–0.3
3.60
V
V(VDD_PLLM) (MCG PLL)
–0.3
1.21
V
V(VDD_PLLD) (DCG PLL)
–0.3
1.21
V
VI2C buffer (I/O type 7)
–0.3
See (3)
V
GENERAL
TJ
Operating junction temperature
–30
125
°C
Tstg
Storage temperature
–40
125
°C
(1)
(2)
(3)
Stresses beyond those listed under Section 6.1 may cause permanent damage to the device. These are stress ratings only, which do
not imply functional operation of the device at these or any other conditions beyond those indicated under Section 6.3. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to VSS (GND).
I/O is high voltage tolerant; that is, if VCC_INTF = 1.8 V, the input is 3.3-V tolerant, and if VCC_INTF = 3.3 V, the input is 5-V tolerant.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
14
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins(1)
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins(2)
UNIT
±2000
±500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
V(VDD)
Core power 1.1 V (main 1.1 V)
V(VDDLP12)
Reserved
V(VCC18)
All 1.8-V I/O power:
(1.8-V power supply for all I/O pins except the host or
parallel interface and the SPI flash interface. This includes
RESETZ, PARKZ LED_SEL, CMP_OUT, GPIO, IIC1,
TSTPT, and JTAG pins.)
V(VCC_INTF)
Host or parallel interface I/O power: 1.8 to 3.3 V (includes
See (1)
IIC0, PDATA, video syncs, and HOST_IRQ pins)
V(VCC_FLSH)
See(3)
Flash interface I/O power: 1.8 V to 3.3 V
See (1)
NOM
MAX
UNIT
1.045
1.10
1.155
V
1.045
1.10
1.155
V
1.64
1.80
1.96
V
1.64
1.80
1.96
2.28
2.50
2.72
3.02
3.30
3.58
1.64
1.80
1.96
2.28
2.50
2.72
3.02
3.30
3.58
V
V
V(VDD_PLLM)
MCG PLL 1.1-V power
See (2)
1.025
1.100
1.155
V
V(VDD_PLLD)
DCG PLL 1.1-V power
See (2)
1.025
1.100
1.155
V
–30
85
°C
–30
105
°C
temperature(4)
TA
Operating ambient
TJ
Operating junction temperature
(1)
(2)
(3)
(4)
These supplies have multiple valid ranges.
The minimum voltage is lower than other 1.1-V supply minimum to enable additional filtering. This filtering may result in an IR drop
across the filter.
VDDLP12 must be tied to the VDD rail.
The operating ambient temperature range assumes 0 forced air flow, a JEDEC JESD51 junction-to-ambient thermal resistance value
at 0 forced air flow (RθJA at 0 m/s), a JEDEC JESD51 standard test card and environment, along with minimum and maximum
estimated power dissipation across process, voltage, and temperature. Thermal conditions vary by application, and this affects RθJA.
Thus, maximum operating ambient temperature varies by application.
• Ta_min = Tj_min – (Pd_min × RθJA) = –30°C – (0.0 W × 28.8°C/W) = –30°C
• Ta_max = Tj_max – (Pd_max × RθJA) = +105°C – (0.348 W × 28.8°C/W) = +95.0°C
6.4 Thermal Information
DLPC3439
THERMAL
METRIC(1)
ZEZ (NFBGA)
UNIT
201 PINS
RθJC
RθJA
ψJT
(1)
(2)
(3)
Junction-to-case top thermal resistance
Junction-to-air thermal
resistance
10.1
at 0 m/s of forced airflow(2)
28.8
at 1 m/s of forced airflow(2)
25.3
at 2 m/s of forced airflow(2)
24.4
Temperature variance from junction to package top center temperature, per unit power
dissipation(3)
0.23
°C/W
°C/W
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Thermal coefficients abide by JEDEC Standard 51. RθJA is the thermal resistance of the package as measured using a JEDEC defined
standard test PCB. This JEDEC test PCB is not necessarily representative of the DLPC34xx PCB and thus the reported thermal
resistance may not be accurate in the actual product application. Although the actual thermal resistance may be different, it is the best
information available during the design phase to estimate thermal performance.
Example: (0.5 W) × (0.2 °C/W) ≈ 0.1°C temperature rise.
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6.5 Power Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER(4) (5) (6)
TYP(1)
MAX(2)
Frame rate = 50 Hz
206
338
Frame rate = 60 Hz
222
366
Frame rate = 50 Hz
6
Frame rate = 60 Hz
6
Frame rate = 50 Hz
6
Frame rate = 60 Hz
6
Frame rate = 50 Hz
31
45
45
TEST CONDITIONS
MIN
I(VDD) +
I(VDD_PLLM) +
I(VDD_PLLD)
1.1V rails
I(VDD_PLLM)
MCG PLL 1.1-V current(3)
I(VDD_PLLD)
DCG PLL 1.1-V current(3)
I(VCC18)
All 1.8-V I/O current: (1.8-V power supply
for all I/O other than the host or parallel
interface and the SPI flash interface)
Frame rate = 60 Hz
31
Host or parallel interface I/O current: 1.8 to Frame rate = 50 Hz
3.3 V (includes IIC0, PDATA, video syncs,
Frame rate = 60 Hz
and HOST_IRQ pins)(3)
2
I(VCC_INTF)
I(VCC_FLSH)
Flash interface I/O current:1.8 to 3.3 V(3)
Frame rate = 50 Hz
1
Frame rate = 60 Hz
1
(1)
(2)
(3)
(4)
(5)
(6)
16
2
UNIT
mA
mA
mA
mA
mA
mA
Values assume all pins using 1.1 V are tied together (including VDDLP12), and programmable host and flash I/O are at the minimum
nominal voltage (that is 1.8 V).
Input image is 1920 x 1080 (1080p) 24-bits using VESA reduced blanking v2 timings on the parallel interface at the frame rate shown
with the 0.47-inch 1080p (DLP4710) DMD. The controller has the CAIC and LABB algorithms turned off.
The values do not take into account software updates or customer changes that may affect power performance.
Assumes nominal process, voltage, and temperature (25°C nominal ambient) with nominal input images.
Assumes worst case process, maximum voltage, and high nominal ambient temperature of 65°C with worst case input image.
These power numbers are for a single controller. Two controllers are required in a system and each controller is typically powered by
the same source.
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6.6 Pin Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER(3)
TEST
CONDITIONS(4)
0.7 ×
VCC_INTF
I2C buffer (I/O type 7)
VIH
High-level input
threshold voltage
VIL
VOH
VOL
High-level output
voltage
Low-level output
voltage
TYP
MAX
See
VCC18 = 1.8 V
I/O type 1, 6 for pins noted in (2)
VCC18 = 1.8 V
I/O type 5, 9, 11
VCC_INTF = 1.8 V
I/O type 12, 13
VCC_FLSH = 1.8 V
1.17
3.6
I/O type 5, 9, 11
VCC_INTF = 2.5 V
1.7
3.6
I/O type 12, 13
VCC_FLSH = 2.5 V
1.7
3.6
I/O type 5, 9, 11
VCC_INTF = 3.3 V
2.0
3.6
I/O type 12, 13
VCC_FLSH = 3.3 V
2.0
3.6
–0.5
0.3 ×
VCC_INTF
0.63
1.17
3.6
1.3
3.6
1.17
3.6
I/O type 1, 2, 3, 6, 8 except pins
noted in (2)
VCC18 = 1.8 V
–0.3
I/O type 1, 6 for pins noted in (2)
VCC18 = 1.8 V
–0.3
0.5
I/O type 5, 9, 11
VCC_INTF = 1.8 V
–0.3
0.63
I/O type 12, 13
VCC_FLSH = 1.8 V
–0.3
0.63
I/O type 5, 9, 11
VCC_INTF = 2.5 V
–0.3
0.7
I/O type 12, 13
VCC_FLSH = 2.5 V
–0.3
0.7
I/O type 5, 9, 11
VCC_INTF = 3.3 V
–0.3
0.8
0.8
I/O type 12, 13
VCC_FLSH = 3.3 V
–0.3
I/O type 1, 2, 3, 6, 8
VCC18 = 1.8 V
1.35
I/O type 5, 9, 11
VCC_INTF = 1.8 V
1.35
I/O type 12, 13
VCC_FLSH = 1.8 V
1.35
I/O type 5, 9, 11
VCC_INTF = 2.5 V
1.7
I/O type 12, 13
VCC_FLSH = 2.5 V
1.7
I/O type 5, 9, 11
VCC_INTF = 3.3 V
2.4
I/O type 12, 13
VCC_FLSH = 3.3 V
2.4
I2C buffer (I/O type 7)
VCC_INTF > 2 V
0.4
I2C buffer (I/O type 7)
VCC_INTF < 2 V
0.2 ×
VCC_INTF
I/O type 1, 2, 3, 6, 8
VCC18 = 1.8 V
0.45
I/O Type 5, 9, 11
VCC_INTF = 1.8 V
0.45
I/O Type 12, 13
VCC_FLSH = 1.8 V
0.45
I/O Type 5, 9, 11
VCC_INTF = 2.5 V
0.7
I/O Type 12, 13
VCC_FLSH = 2.5 V
0.7
I/O Type 5, 9, 11
VCC_INTF = 3.3 V
0.4
I/O Type 12, 13
VCC_FLSH = 3.3 V
0.4
Copyright © 2021 Texas Instruments Incorporated
UNIT
(1)
I/O type 1, 2, 3, 6, 8 except pins
noted in (2)
I2C buffer (I/O type 7)
Low-level input
threshold voltage
MIN
V
V
V
V
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6.6 Pin Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER(3)
IOH
High-level output
current(5)
IOL
IOZ
18
High-impedance
leakage current
MIN
TYP
MAX
I/O type 2, 4
VCC18 = 1.8 V
2
I/O type 5
VCC_INTF = 1.8 V
2
I/O type 1
VCC18 = 1.8 V
3.5
I/O type 9
VCC_INTF = 1.8 V
3.5
I/O type 13
VCC_FLSH = 1.8 V
I/O type 3
VCC18 = 1.8 V
I/O type 5
VCC_INTF = 2.5 V
5.4
I/O type 9, 13
VCC_INTF = 2.5V
10.8
I/O type 13
VCC_FLSH = 2.5 V
10.8
I/O type 5
VCC_INTF = 3.3 V
7.8
I/O type 9
VCC_INTF = 3.3 V
15
I/O type 13
VCC_FLSH = 3.3 V
15
I/O type 2, 4
VCC18 = 1.8 V
2.3
I/O type 5
VCC_INTF = 1.8 V
2.3
I/O type 1
VCC18 = 1.8 V
4.6
I/O type 9
VCC_INTF = 1.8 V
4.6
I/O type 13
VCC_FLSH = 1.8 V
4.6
I/O type 3
VCC18 = 1.8 V
I/O type 5
VCC_INTF = 2.5 V
5.2
I/O type 9
VCC_INTF = 2.5 V
10.4
I/O type 13
VCC_FLSH = 2.5 V
10.4
I/O type 5
VCC_INTF = 3.3 V
4.4
I/O type 9
VCC_INTF = 3.3 V
8.9
I/O type 13
VCC_FLSH = 3.3 V
8.9
I2C
VI2C buffer < 0.1 ×
VCC_INTF or
VI2C buffer > 0.9 ×
VCC_INTF
–10
10
I/O type 1, 2, 3, 6, 8,
VCC18 = 1.8 V
–10
10
I/O Type 5, 9, 11
VCC_INTF = 1.8 V
–10
10
I/O Type 12, 13
VCC_FLSH = 1.8 V
–10
10
I/O type 5, 9, 11
VCC_INTF = 2.5 V
–10
10
I/O Type 12, 13
VCC_FLSH = 2.5 V
–10
10
I/O Type 5, 9, 11
VCC_INTF = 3.3 V
–10
10
I/O type 12, 13
VCC_FLSH = 3.3 V
–10
10
I2C
Low-level output
current(6)
TEST
CONDITIONS(4)
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buffer (I/O type 7)
buffer (I/O type 7)
UNIT
3.5
10.6
mA
3
13.9
mA
µA
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6.6 Pin Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER(3)
TEST
CONDITIONS(4)
MIN
TYP
MAX
I2C buffer (I/O type 7)
CI
Input capacitance
(including package)
5
I/O type 1, 2, 3, 6, 8
VCC18 = 1.8 V
2.6
3.5
I/O Type 5, 9, 11
VCC_INTF = 1.8 V
2.6
3.5
I/O Type 12, 13
VCC_FLSH = 1.8 V
2.6
3.5
I/O type 5, 9, 11
VCC_INTF = 2.5 V
2.6
3.5
I/O type 12, 13
VCC_FLSH = 2.5 V
2.6
3.5
I/O type 5, 9, 11
VCC_INTF = 3.3 V
2.6
3.5
I/O type 12, 13
VCC_FLSH = 3.3 V
2.6
3.5
sub-LVDS – DMD high speed (I/O
VCC18 = 1.8 V
type 4)
(1)
(2)
(3)
(4)
(5)
(6)
UNIT
pF
3
I/O is high voltage tolerant; that is, if VCC_INTF = 1.8 V, the input is 3.3-V tolerant, and if VCC_INTF = 3.3 V, the input is 5-V tolerant.
Controller pins CMP_OUT, PARKZ, RESETZ, and GPIO_00 through GPIO_19 have slightly varied VIH and VIL range from other 1.8-V
I/O.
The I/O type refers to the type defined in Table 5-10.
Test conditions that define a value for VCC18, VCC_INTF, or VCC_FLSH show the nominal voltage that the specified I/O's supply
reference is set to.
At a high level output signal, the given I/O will be able to output at least the minimum current specified.
At a low level output signal, the given I/O will be able to sink at least the minimum current specified.
6.7 Internal Pullup and Pulldown Electrical Characteristics
over operating free-air temperature (unless otherwise noted) (2)
INTERNAL PULLUP AND PULLDOWN RESISTOR CHARACTERISTICS
Weak pullup resistance
Weak pulldown resistance
(1)
(2)
TEST
CONDITIONS(1)
MIN
MAX
VCCIO = 3.3 V
29
63
VCCIO = 2.5 V
38
90
kΩ
VCCIO = 1.8 V
56
148
kΩ
VCCIO = 3.3 V
30
72
kΩ
VCCIO = 2.5 V
36
101
kΩ
VCCIO = 1.8 V
52
167
kΩ
UNIT
kΩ
The resistance is dependent on VCCIO, the pin's supply reference (see a given pins supply reference in Table 5-10).
An external 8-kΩ pullup or pulldown (if needed) would work for any voltage condition to correctly pull enough to override any
associated internal pullups or pulldowns.
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6.8 DMD Sub-LVDS Interface Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.8
0.9
1.0
V
75
mV
VCM
Common mode voltage
VCM (Δpp)(1)
VCM change peak-to-peak (during switching)
VCM (Δss)(1)
VCM change steady state
–10
|VOD|(2)
Differential output voltage magnitude
170
VOD (Δ)
VOD change (between logic states)
VOH
Single-ended output voltage high
UNIT
10
mV
250
350
mV
10
mV
0.825
1.025
1.175
–10
V
VOL
Single-ended output voltage low
0.625
0.775
0.975
V
Txterm
Internal differential termination
80
100
120
Ω
Txload
100-Ω differential PCB trace
(50-Ω transmission lines)
0.5
inches
See Figure 6-1
VOD is the differential voltage measured across a 100-Ω termination resistance connected directly between the transmitter differential
pins. VOD = VP - VN, where P and N are the differential output pins. |VOD| is the magnitude of the peak-to-peak voltage swing across
the P and N output pins (see Figure 6-2). VCM cancels out between signals when measured differentially, thus the reason VOD swings
relative to zero.
Common Mode Voltage (V)
(1)
(2)
6
VCM (ûSS)
VCM
VCM (ûP-P)
Figure 6-1. Common Mode Voltage
+VOD
100
Differential Voltage (%)
90
80
|VOD|
70
60
(0 V) 50
40
30
|VOD|
20
10
±VOD
0
tFALL
tRISE
VCM is removed when the signals are viewed differentially
Figure 6-2. Differential Output Signal
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6.9 DMD Low-Speed Interface Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER(3)
TEST CONDITIONS
VOH(DC)
DC output high voltage for DMD_LS_WDATA
and DMD_LS_CLK
VOL(DC)
DC output low voltage for DMD_LS_WDATA
and DMD_LS_CLK
VOH(AC) (1)
AC output high voltage for DMD_LS_WDATA
and DMD_LS_CLK
VOL(AC) (2)
AC output low voltage for DMD_LS_WDATA
and DMD_LS_CLK
MIN
(2)
(3)
UNIT
V
0.3 ×
VCC18
V
0.8 ×
VCC18
VCC18 +
0.5
V
-0.5
0.2 ×
VCC18
V
3.0
VOL(DC) to VOH(AC) for rising edge
and VOH(DC) to VOL(AC) for rising
edge
1.0
DMD_DEN_ARSTZ
VOL(AC) to VOH(AC) for rising edge
0.25
V/ns
DMD_LS_RDATA
(1)
MAX
0.7 ×
VCC18
DMD_LS_WDATA and DMD_LS_CLK
Slew rate
TYP
0.5
VOH(AC) maximum applies to overshoot. When the DMD_LS_WDATA and DMD_LS_CLK lines include a proper 43-Ω series termination
resistor, the DMD operates within the LPSDR input AC specifications.
VOL(AC) minimum applies to undershoot. When the DMD_LS_WDATA and DMD_LS_CLK lines include a proper 43-Ω series
termination resistor, the DMD operates within the LPSDR input AC specifications.
See Figure 6-3 for DMD_LS_CLK, and DMD_LS_WDATA rise and fall times. See Figure 6-4 for DMD_DEN_ARSTZ rise and fall times.
LS_CLK, LS_WDATA
100
90
VCC18 Voltage (%)
VOH(AC) 80
VOH(DC) 70
60
50
40
VOL(DC) 30
VOL(AC) 20
10
0
tRISE
tFALL
Figure 6-3. LS_CLK and LS_WDATA Slew Rate
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DMD_DEN_ARSTZ
100
90
VCC18 Voltage (%)
VOH(AC) 80
70
60
50
40
30
VOL(AC) 20
10
0
tRISE
tFALL
Figure 6-4. DMD_DEN_ARSTZ Slew Rate
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6.10 System Oscillator Timing Requirements
fclk
Clock frequency, MOSC (master oscillator
tc
Cycle time, MOSC (clock period)(1)
(2),
clock)(1)
UNIT
24.000
24.002
MHz
41.667
41.670
ns
50% to 50% reference
points (signal)
40%
50%
40%
50%
10
ns
Pulse duration as percent of tc
tw(L)
Pulse duration as percent of tc (2), MOSC, low
50% to 50% reference
points (signal)
tt
Transition time(2), MOSC
20% to 80% reference
points (rising signal)
80% to 20% reference
points (falling signal)
tjp
Long-term, peak-to-peak, period jitter(2), MOSC
(that is the deviation in period from ideal period due
solely to high frequency jitter)
(2)
MAX
23.998
tw(H)
(1)
NOM
41.663
See Figure 6-5
MOSC, high
MIN
2%
The frequency accuracy for MOSC is ±200 PPM. (This includes impact to accuracy due to aging, temperature, and trim sensitivity.)
The MOSC input does not support spread spectrum clock spreading.
Applies only when driven by an external digital oscillator.
tC
tW(H)
tT
tT
tW(L)
80%
50%
20%
MOSC
Figure 6-5. System Oscillators
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6.11 Power Supply and Reset Timing Requirements
MIN
MAX
tw(L)
Pulse duration, active low, RESETZ
50% to 50% reference points (signal)
tr
Rise time, RESETZ(1)
20% to 80% reference points (signal)
0.5
80% to 20% reference points (signal)
0.5
µs
1
ms
RESETZ(1)
tf
Fall time,
trise
Rise time, VDD (during VDD ramp up at
turn-on)
(1)
1.25
UNIT
0.3 V to 1.045 V (VDD)
µs
µs
For more information on RESETZ, see Section 5.
DC Power Supplies
RESETZ
tr
tf
tw(L)
80%
80%
50%
50%
20%
20%
tw(L)
tw(L)
Time
Figure 6-6. Power-Up and Power-Down RESETZ Timing
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6.12 Parallel Interface Frame Timing Requirements
MIN
MAX
UNIT
tp_vsw
Pulse duration – default VSYNC_WE high
50% reference points
1
lines
tp_vbp
Vertical back porch (VBP) – time from the active edge of
VSYNC_WE to the active edge of HSYNC_CS for the first
active line(1)
50% reference points
2
lines
tp_vfp
Vertical front porch (VFP) – time from the active edge of the
HSYNC_CS following the last active line in a frame to the active 50% reference points
edge of VSYNC_WE(1)
1
lines
tp_tvb
Total vertical blanking – the sum of VBP and VFP (tp_vbp +
tp_vfp)
50% reference points
See (1)
lines
tp_hsw
Pulse duration – default HSYNC_CS high
50% reference points
4
tp_hbp
Horizontal back porch (HBP) – time from the active edge of
HSYNC_CS to the rising edge of DATAEN_CMD
50% reference points
4
PCLKs
tp_hfp
Horizontal front porch (HFP) – time from the falling edge of
DATAEN_CMD to the active edge of HSYNC_CS
50% reference points
8
PCLKs
(1)
128
PCLKs
The minimum total vertical blanking is defined by the following equation: tp_tvb(min) = 6 + [8 × Max(1, Source_ALPF/ DMD_ALPF)] lines
where:
• SOURCE_ALPF = Input source active lines per frame
• DMD_ALPF = Actual DMD used lines per frame supported
1 Frame
tp_vsw
VSYNC_WE
(This diagram assumes the VSYNC
active edge is the rising edge)
tp_vbp
tp_vfp
HSYNC_CS
DATAEN_CMD
1 Line
tp_hsw
HSYNC_CS
tp_hbp
(This diagram assumes the HSYNC
active edge is the rising edge)
tp_hfp
DATAEN_CMD
P0
PDATA(23/15:0)
P1
P2
P3
P
n-2
P
n-1
Pn
PCLK
Figure 6-7. Parallel Interface Frame Timing
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6.13 Parallel Interface General Timing Requirements
ƒclock
PCLK frequency
tp_clkper
PCLK period
50% reference points
MIN
MAX
UNIT
1.0
155.0
MHz
6.45
1000
ns
tp_clkjit
PCLK jitter
Max ƒclock
tp_wh
PCLK pulse duration high
50% reference points
2.43
ns
tp_wl
PCLK pulse duration low
50% reference points
2.43
ns
tp_su
Setup time – HSYNC_CS, DATAEN_CMD,
PDATA(23:0) valid before the active edge of PCLK
50% reference points
0.9
ns
tp_h
Hold time – HSYNC_CS, DATAEN_CMD,
PDATA(23:0) valid after the active edge of PCLK
50% reference points
0.9
ns
tt
Transition time – all signals
20% to 80% reference
points (rising signal)
80% to 20% reference
points (falling signal)
0.2
tsetup, 3DR
This is the setup time with respect to VSYNC(2)
50% reference points
1.0
ms
thold, 3DR
This is the hold time with respect VSYNC(3)
50% reference points
1.0
ms
(1)
(2)
(3)
see
(1)
2.0
ns
Calculate clock jitter (in ns) using this formula: Jitter = [1 / ƒclock – 5.76 ns]. Setup and hold times must be met even with clock jitter.
In other words, the 3DR signal must change at least 1.0 ms before VSYNC changes
In other words, the 3DR signal must not change for at least 1.0 ms after VSYNC changes
tp_clkper
tp_wh
tp_wl
PCLK
tp_su
tp_h
Figure 6-8. Parallel Interface Pixel Timing
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6.14 Flash Interface Timing Requirements
The DLPC34xx flash memory interface consists of a SPI flash serial interface. The DLPC34xx can support 1- to 128-Mb flash
memories.(2) (3) (4)
fclock
See (1)
SPI_CLK frequency
MIN
MAX
UNIT
1.4
36.0
MHz
704
tp_clkper
SPI_CLK period
50% reference points
27.8
tp_wh
SPI_CLK pulse duration high
50% reference points
352
ns
tp_wl
SPI_CLK pulse duration low
50% reference points
352
ns
tt
Transition time – all signals
20% to 80% reference
points (rising signal)
80% to 20% reference
points (falling signal)
0.2
tp_su
Setup time – SPI_DIN valid before SPI_CLK falling edge 50% reference points
tp_h
Hold time – SPI_DIN valid after SPI_CLK falling edge
50% reference points
tp_clqv
SPI_CLK clock falling edge to output valid time –
SPI_DOUT and SPI_CSZ
50% reference points
tp_clqx
SPI_CLK clock falling edge output hold time –
SPI_DOUT and SPI_CSZ
50% reference points
(1)
(2)
(3)
(4)
3.0
ns
ns
10.0
ns
0.0
ns
–3.0
1.0
ns
3.0
ns
This range include the ±200 ppm of the external oscillator (but no jitter).
Standard SPI protocol is to transmit data on the falling edge of SPI_CLK and capture data on the rising edge. The DLPC34xx does
transmit data on the falling edge, but it also captures data on the falling edge rather than the rising edge. This provides support for SPI
devices with long clock-to-Q timing. DLPC34xx hold capture timing has been set to facilitate reliable operation with standard external
SPI protocol devices.
With the above output timing, DLPC34xx provides the external SPI device 8.2-ns input set-up and 8.2-ns input hold, relative to the
rising edge of SPI_CLK.
For additional requirements of the external flash device view the Section 7.3.3.1 section.
tCLKPER
SPI_CLK
(Controller output)
tWH
tWL
tP_SU
tP_H
SPI_DIN
(Controller input)
tP_CLQV
SPI_DOUT, SPI_CS(1:0)
(Controller output)
tP_CLQX
Figure 6-9. Flash Interface Timing
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6.15 Other Timing Requirements
MIN
MAX
UNIT
all(1) (2)
20% to 80% reference points
10
ns
tfall, all(1) (2)
80% to 20% reference points
10
ns
PARKZ(2)
20% to 80% reference points
150
ns
tfall, PARKZ(2)
80% to 20% reference points
150
ns
100
kHz
trise,
trise,
tw, GPIO_08 (normal park) pulse
width(3)
200
I2C baud rate
(1)
(2)
(3)
ms
Unless noted elsewhere, the following signal transition times are for all DLPC34xx signals.
This is the recommended signal transition time to avoid input buffer oscillations.
When the controller is turned off by setting PROJ_ON low, PROJ_ON must not be brought high again for at least 200 ms. View Section
9.3 for additional requirements.
6.16 DMD Sub-LVDS Interface Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
tR (1)
Differential output rise time
250
tF (1)
Differential output fall time
250
tswitch
DMD HS Clock switching rate
fclock
DMD HS Clock frequency
DCout
DMD HS Clock output duty cycle
(1)
1064
UNIT
ps
Mbps
532
MHz
45%
50%
55%
MIN
TYP
MAX
Rise and fall times are defined for the differential VOD signal as shown in Figure 6-2.
6.17 DMD Parking Switching Characteristics
See (2)
PARAMETER
tfast park
(1)
(2)
(3)
TEST CONDITIONS
Normal Park time(1)
tpark
Fast park
time(3)
UNIT
20
ms
32
µs
Normal park time is defined as how long it takes the DLPC34xx controller to complete the parking of the DMD after it receives the
normal park request (GPIO_08 goes low).
The oscillator and power supplies must remain active for at least the duration of the park time. The power supplies must additionally be
held on for a time after parking is completed to satisfy DMD requirements. See Section 9.2 and the appropriate DMD or PMIC
datasheet for more information.
Fast park time is defined as how long it takes the DLPC34xx controller to complete the parking of the DMD after it receives the fast
park request (PARKZ goes low).
6.18 Chipset Component Usage Specification
The DLPC3439 is a component of a DLP chipset. Reliable function and operation of the DLP chipset requires
that it be used with all components (DMD, PMIC, and controller) of the applicable DLP chipset.
Table 6-1. DLPC3439 Supported DMDs and PMICs
DLPC3439 DLP Chipset (two DLPC3439 controllers required)
DMD
PMIC
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DLPA3000
DLPA3005
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7 Detailed Description
7.1 Overview
The DLPC3439 is the display controller for the DLP4710 (0.47 1080p) DMD. The DLPC3439 is part of the
chipset comprising two DLPC3439 controllers, the DLP4710 (0.47 1080p) DMD, and the DLPA3000 or
DLPA3005 PMIC/LED driver. All four components of the chipset must be used in conjunction with each other for
reliable operation of the DLP4710 (0.47 1080p) DMD. Each DLPC3439 display controller provides interfaces and
data and image processing functions that are optimized for small form factor and power-constrained display
applications. Applications include pico projectors, wearable displays, and digital signage. The DLPC3439 is not a
front-end processor; therefore, standalone projectors must include a separate front-end chip to interface to the
outside world (for example, video decoder, HDMI receiver, triple ADC, or USB I/F chip).
7.2 Functional Block Diagram
Parallel
Interface
/5
/24
Input
Control
Processing
Test
Pattern
Generator
Video Processing
x
x
x
x
Chroma Interpolation
Brightness Enhancement
Gamma Correction
Image Format Processing
Splash
Screen
eDRAM
(Frame Memory)
x
x
x
x
x
Contrast Adjust
Color Correction
CAIC Processing
Blue Noise STM
Power Saving Operations
DLP® Display Formatting
DMD_HS_CLK(LVDS)
Arm® Cortex®-M3
Processor
128 KB I/D Memory
2
I C_0
SPI_0
DMD_HS_DATA(A)(LVDS)
Real Time
Control System
DMD_HS_DATA(B)(LVDS)
DMD_HS_DATA(C)(LVDS)
DMD Interface
SPI_1
2
I C_1
LED Control
Other options
/20
GPIO
Clocks and Reset
Generation
DMD_HS_DATA(E)(LVDS)
DMD_HS_DATA(F)(LVDS)
DMD_HS_DATA(G)(LVDS)
DMD_HS_DATA(H)(LVDS)
Clock (Crystal)
Reset Control
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DMD_HS_DATA(D)(LVDS)
DMD_LS_CLK
DMD_LS_WDATA
DMD_LS_RDATA
DMD_DEN_ARSTZ
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7.3 Feature Description
7.3.1 Input Source Requirements
7.3.1.1 Supported Resolution and Frame Rates
Table 7-1. Supported Input Source Ranges (1) (2) (3)
INTERFACE
(2)
(3)
(4)
HORIZONTAL
VERTICAL
FRAME RATE
RANGE
(Hz)
2D only
400 to 1920
550 to 1080
47 to 63
24
2D only
400 to 1280
550 to 720
47 to 123
24
3D only
400 to 1280
550 to 720
100 ±2
120 ±2
IMAGE TYPE
24
Parallel
(1)
SOURCE RESOLUTION RANGE(pixels)
Bits per Pixel
(max)(4)
The application must remain within specifications for all source interface parameters such as maximum clock rate and maximum line
rate.
The maximum DMD size for all rows in the table is 1920 × 1080 pixels.
To achieve the ranges stated, the firmware must support the source parameters. Review the firmware release notes or contact TI to
determine the latest available frame rate and input resolution support for a given firmware image.
Bits per pixel does not necessarily equal the number of data pins used on the DLPC34xx controller.
7.3.1.2 3D Display
For 3D sources on the video input interface, images must be frame sequential (L, R, L, ...) when input to the
DLPC34xx controller. Any processing required to unpack 3D images and to convert them to frame sequential
input must be done by external electronics prior to inputting the images to the controller. Each 3D source frame
input must contain a single eye frame of data, separated by a VSYNC, where an eye frame contains image data
for a single left or right eye. The signal 3DR input to the controller indicates whether the input frame is for the left
eye or right eye.
Each DMD frame is displayed at the same rate as the input interface frame rate. Figure 7-1 below shows the
typical timing for a 50-Hz or 60-Hz 3D HDMI source frame, the input interface of the DLPC34xx controller, and
the DMD. In general, video frames sent over the HDMI interface pack both the left and right content into the
same video frame. GPIO_04 is optionally sent to a transmitter on the system PCB for wirelessly transmitting a
synchronization signal to 3D glasses (usually an IR sync signal). The glasses are then in phase with the DMD
images displayed. Alternately, the 3D Glasses Operation section shows how DLP link pulses can be used
instead.
50 Hz or 60 Hz
(HDMI)
L
100 Hz or 120 Hz
(34xx Input)
L
R
L
R
L
R
L
R
L
R
L
R
R
L
R
L
R
L
R
L
R
L
R
L
R
L
R
L
R
L
R
L
R
L
R
3DR (2)
(3D L/R input)
100 Hz or 120 Hz
(on DMD)
GPIO_04 (1)
(3D L/R output)
(1) Left = 1, Right = 0
(2) 3DR must toggle at least 1 ms before VSYNC
Figure 7-1. 3D Display Left and Right Frame Timing
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7.3.1.3 Parallel Interface
The parallel interface complies with standard graphics interface protocol, which includes the signals listed in
Table 7-2.
Table 7-2. Parallel Interface Signals
SIGNAL
DESCRIPTION
VSYNC_WE
vertical sync
HSYNC_CS
horizontal sync
DATAEN_CMD
data valid
PDATA
24-bit data bus
PCLK
pixel clock
PDM_CVS_TE
parallel data mask (optional)
Note
VSYNC_WE must remain active at all times when using parallel RGB mode. When this signal is no
longer active, the display sequencer stops and causes the LEDs to turn off.
The active edge of both sync signals are variable. The Parallel Interface Frame Timing Requirements section
shows the relationship of these signals.
An optional parallel data mask signal (PDM_CVS_TE) allows periodic frame updates to be stopped without
losing the displayed image. When active, PDM_CVS_TE acts as a data mask and does not allow the source
image to be propagated to the display. A programmable PDM polarity parameter determines if it is active high or
active low. PDM_CVS_TE defaults to active high. To disable the data mask function, tie PDM_CVS_TE to a logic
low signal. PDM_CVS_TE must only change during vertical blanking.
The parallel interface supports six data transfer formats. They are as follows:
• 24-bit RGB888 or 24-bit YCbCr888 on a 24 data wire interface
• 18-bit RGB666 or 18-bit YCbCr666 on an 18 data wire interface
• 16-bit RGB565 or 16-bit YCbCr565 on a 16 data wire interface
• 16-bit YCbCr 4:2:2 (standard sampling assumed to be Y0Cb0, Y1Cr0, Y2Cb2, Y3Cr2, Y4Cb4, Y5Cr4, ...)
• 8-bit RGB888 or 8-bit YCbCr888 serial (1 color per clock input; 3 clocks per displayed pixel) on an 8 data wire
interface
• 8-bit YCbCr 4:2:2 serial (1 color per clock input; 2 clocks per displayed pixel) on an 8 data wire interface
Section 7.3.1.3.1 shows the required PDATA(23:0) bus mapping for these six data transfer formats.
7.3.1.3.1 PDATA Bus – Parallel Interface Bit Mapping Modes
23
0
Red / Cr
Green / Y
Blue / Cb
Controller input mapping
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
Controller internal re-mapping
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
Red / Cr
Green / Y
4
3
2
1
0
4
3
2
1
0
Blue / Cb
Figure 7-2. RGB-888 and YCbCr-888 I/O Mapping
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23
0
Input
Input
Input
Controller input mapping
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
Controller internal re-mapping
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
Red / Cr
Green / Y
4
3
2
1
0
4
3
2
1
0
Blue / Cb
Figure 7-3. RGB-666 and YCbCr-666 I/O Mapping
23
0
Input
Input
Controller input mapping
7
6
5
Controller internal re-mapping
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
Red / Cr
Input
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
Green / Y
4
3
2
1
0
4
3
2
1
0
Blue / Cb
Figure 7-4. RGB-565 and YCbCr-565 I/O Mapping
23
0
Cr / Cb
Y
N/A
Controller input mapping
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Controller internal re-mapping
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Cr / Cb
Y
N/A
Figure 7-5. 16-Bit YCbCr-880 I/O Mapping
23
Input 1 single color pixel per clock, contiguous
Red / Cr
Controller input mapping
7
6
5
4
3
0
Green / Y
2
1
0
7
6
5
4
3
Blue / Cb
2
1
0
7
6
5
4
3
2
1
0
1
0
Input order must be RÆGÆB
First Input Clock
Controller internal re-mapping
7
6
5
4
Red / Cr
3
2
Second Input Clock
1
0
7
6
5
4
3
2
1
Third Input Clock
0
7
6
Green / Y
(Output 1 full pixel per clock, non-contiguous)
5
4
3
2
Blue / Cb
Figure 7-6. 8-Bit RGB-888 or YCbCr-888 I/O Mapping
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[Input 1 single Y/Cr-Cb pixel per clock ± Contiguous]
23
Cr / Cb
Controller input mapping
7
6
5
4
3
0
Y
2
1
0
7
6
5
4
Blue / Cb
3
2
1
0
7
6
5
7
6
5
4
3
2
1
0
4
3
2
1
0
Input Order must be Cr/Cb Æ Y
First Input Clock
Controller internal re-mapping
7
6
5
4
Cr/Cb
3
2
Second Input Clock
1
0
7
6
5
4
3
2
1
0
Y
[Output 1 full pixel per clock ± Non-Contiguous]
Blue / Cb
Figure 7-7. 8-Bit Serial YCbCr-422 I/O Mapping
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7.3.2 Device Startup
•
•
•
•
•
•
•
The HOST_IRQ signal is provided to indicated when the system has completed auto-initialization.
While reset is applied, HOST_IRQ is tri-stated (an external pullup resistor pulls the line high).
HOST_IRQ remains tri-stated (pulled high externally) until the boot process completes. While the signal is
pulled high, this indicates that the controller is performing boot-up and auto-initialization.
As soon as possible after the controller boots-up, the controller drives HOST_IRQ to a logic high state to
indicate that the controller is continuing to perform auto-initialization (no real state changes occur on the
external signal).
The software sets HOST_IRQ to a logic low state at the completion of the auto-initialization process. At the
falling edge of the signal, the initialization is complete.
The DLPC34xx controller is ready to receive commands through I2C or accept video over the video interface
only after auto-initialization is complete.
The controller initialization typically completes (HOST_IRQ goes low) within 500 ms of RESETZ being
asserted. However, this time may vary depending on the software version and the contents of the user
configurable auto initialization file.
RESETZ
auto-initialization
HOST_IRQ
(with external pullup)
(INIT_BUSY)
t0
t1
t0: rising edge of RESETZ; auto-initialization begins
t1: falling edge of HOST_IRQ; auto-initialization is complete
Figure 7-8. HOST_IRQ Timing
7.3.3 SPI Flash
7.3.3.1 SPI Flash Interface
The DLPC34xx controller requires an external SPI serial flash memory device to store the firmware. Follow the
below guidelines and requirements in addition to the requirements listed in the Flash Interface Timing
Requirements section.
The controller supports a maximum flash size of 128 Mb (16 MB). See the DLPC34xx Validated SPI Flash
Device Options table for example compatible flash options. The minimum required flash size depends on the
size of the utilized firmware. The firmware size depends upon a variety of factors including the number of
sequences, lookup tables, and splash images.
The DLPC34xx controller uses a single SPI interface that complies to industry standard SPI flash protocol. The
device will begin accessing the flash at a nominal 1.42-MHz frequency before running at a nominal 30-MHz rate.
The flash device must support these rates.
The controller has two independent SPI chip select (CS) control lines. Ensure that the chip select pin of the flash
device is connects to SPI0_CSZ0 as the controller boot routine is executes from the device connected to chip
select zero. The boot routine uploads program code from flash memory to program memory then transfers
control to an auto-initialization routine within program memory.
The DLPC34xx is designed to support any flash device that is compatible with the modes of operation, features,
and performance as defined in the Additional DLPC34xx SPI Flash Requirements table below Table 7-3, Table
7-4, and Table 7-5.
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Table 7-3. Additional DLPC34xx SPI Flash Requirements
FEATURE
DLPC34xx REQUIREMENT
SPI interface width
Single
SPI polarity and phase settings
SPI mode 0
Fast READ addressing
Auto-incrementing
Programming mode
Page mode
Page size
256 B
Sector size
4-KB sector
Block size
Any
Block protection bits
0 = Disabled
Status register bit(0)
Write in progress (WIP), also called flash busy
Status register bit(1)
Write enable latch (WEN)
Status register bits(6:2)
A value of 0 disables programming protection
Status register bit(7)
Status register write protect (SRWP)
Status register bits(15:8)
(that is expansion status byte)
Because the DLPC34xx controller supports only single-byte status register R/W command execution,
it may not be compatible with flash devices that contain an expansion status byte. However, as long
as the expansion status byte is considered optional in the byte 3 position and any write protection
control in this expansion status byte defaults to unprotected, then the flash device is likely compatible
with the DLPC34xx.
The DLPC34xx controller is intended to support flash devices with program protection defaults of either enabled
or disabled. The controller assumes the default is enabled and proceeds to disable any program protection as
part of the boot process.
The DLPC34xx issues these commands during the boot process:
•
•
•
A write enable (WREN) instruction to request write enable, followed by
A read status register (RDSR) instruction (repeated as needed) to poll the write enable latch (WEL) bit
After the write enable latch (WEL) bit is set, a write status register (WRSR) instruction that writes 0 to all 8
bits (this disables all programming protection)
Prior to each program or erase instruction, the DLPC34xx controller issues similar commands:
•
•
•
A write enable (WREN) instruction to request write enable, followed by
A read status register (RDSR) instruction (repeated as needed) to poll the write enable latch (WEL) bit
After the write enable latch (WEL) bit is set, the program or erase instruction
Note that the flash device automatically clears the write enable status after each program and erase instruction.
Table 7-4 and Table 7-5 below list the specific instruction OpCode and timing compatibility requirements. The
DLPC34xx controller does not adapt protocol or clock rate based on the flash type connected.
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Table 7-4. SPI Flash Instruction OpCode and Access Profile Compatibility Requirements
(1)
(2)
SPI FLASH COMMAND
BYTE 1
(OPCODE)
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE 6
Fast READ (1 output)
0x0B
ADDRS(0)
ADDRS(1)
ADDRS(2)
dummy
DATA(0)(1)
Read status
0x05
N/A
N/A
STATUS(0)
STATUS(0)
See
(2)
Write status
0x01
Write enable
0x06
Page program
0x02
ADDRS(0)
ADDRS(1)
ADDRS(2)
Sector erase (4 KB)
0x20
ADDRS(0)
ADDRS(1)
ADDRS(2)
Chip erase
0xC7
DATA(0)(1)
Shows the first data byte only. Data continues.
Access to a second (expansion) write status byte not supported by the DLPC34xx controller.
Table 7-5 below and the Flash Interface Timing Requirements section list the specific timing compatibility
requirements for a DLPC34xx compatible flash device.
Table 7-5. SPI Flash Key Timing Parameter Compatibility Requirements
SPI FLASH TIMING PARAMETER(1) (2)
SYMBOL
ALTERNATE SYMBOL
MIN
MAX
UNIT
FR
fC
≤ 1.4
≥ 30.1
MHz
Chip select high time (also called chip select
deselect time)
tSHSL
tCSH
≤ 200
Output hold time
tCLQX
tHO
≥0
Clock low to output valid time
tCLQV
tV
Data in set-up time
tDVCH
tDSU
≤5
ns
Data in hold time
tCHDX
tDH
≤5
ns
Access frequency (all commands)
(1)
(2)
ns
ns
≤ 11
ns
The timing values apply to the specification of the peripheral flash device, not the DLPC34xx controller. For example, the flash device
minimum access frequency (FR) must be 1.4 MHz or less and the maximum access frequency must be 30.1 MHz or greater.
The DLPC34xx does not drive the HOLD or WP (active low write protect) pins on the flash device, and thus these pins must be tied to
a logic high on the PCB through an external pullup.
In order for the DLPC34xx controller to support 1.8-V, 2.5-V, or 3.3-V serial flash devices, the VCC_FLSH pin
must be supplied with the corresponding voltage. The DLPC34xx Validated SPI Flash Device Options table
contains a list of validated 1.8-V, 2.5-V, or 3.3-V compatible SPI serial flash devices supported by the DLPC34xx
controller.
Table 7-6. DLPC34xx Validated SPI Flash Device Options (1) (2) (3)
DENSITY (Mb)
VENDOR
PART NUMBER
PACKAGE SIZE
4 Mb
Winbond
W25Q40BWUXIG
2 × 3 mm USON
4 Mb
Macronix
MX25U4033EBAI-12G
1.43 × 1.94 mm WLCSP
8 Mb
Macronix
MX25U8033EBAI-12G
1.68 × 1.99 mm WLCSP
16 Mb
Winbond
1.8-V COMPATIBLE DEVICES
2.5- OR 3.3-V COMPATIBLE DEVICES
(1)
(2)
(3)
W25Q16CLZPIG
5 × 6 mm WSON
The flash supply voltage must equal VCC_FLSH supply voltage on the DLPC34xx controller. Make sure to order the device that
supports the correct supply voltage as multiple voltage options are often available.
Numonyx (Micron) serial flash devices typically do not support the 4 KB sector size compatibility requirement for the DLPC34xx
controller.
The flash devices in this table have been formally validated by TI. Other flash options may be compatible with the DLPC34xx controller,
but they have not been formally validated by TI.
7.3.3.2 SPI Flash Programming
The SPI pins of the flash can directly be driven for flash programming while the DLPC34xx controller I/Os are tristated. SPI0_CLK, SPI0_DOUT, and SPI0_CSZ0 I/O can be tri-stated by holding RESETZ in a logic low state
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while power is applied to the controller. The logic state of the SPI0_CSZ1 pin is not affected by this action.
Alternatively, the DLPC34xx controller can program the SPI flash itself when commanded via I2C if a valid
firmware image has already been loaded and the controller is operational.
7.3.4 I2C Interface
Both of the DLPC34xx I2C interface ports support a 100-kHz baud rate. Because I2C interface transactions
operate at the speed of the slowest device on the bus, there is no requirement to match the speed of all devices
in the system.
7.3.5 Content Adaptive Illumination Control (CAIC)
Content Adaptive Illumination control (CAIC) is part of the IntelliBright® suite of advanced image processing
algorithms that adaptively enhances brightness and reduces power. In common real-world image content most
pixels in the images are well below full scale for the for the R (red), G (green), and B (blue) digital channels input
to the DLPC34xx. As a result of this, the average picture level (APL) for the overall image is also well below full
scale, and the dynamic range for the collective set of pixel values is not fully used. CAIC takes advantage of the
headroom between the source image APL and the top of the available dynamic range of the display system.
CAIC evaluates images on a frame-by-frame basis and derives three unique digital gains, one for each of the R,
G, and B color channel. During image processing, CAIC applies each gain to all pixels in the associated color
channel. The calculated gain is applied to all pixels in that channel so that the pixels as a group collectively shift
upward and as close to full scale as possible. To prevent any image quality degradation, the gains are set at the
point where just a few pixels in each color channel are clipped. The Source Pixels for a Color Channel and
Pixels for a Color Channel After CAIC Processing figures below show an example of the application of CAIC for
one color channel.
Single-pixel
Headroom
255
APL Headroom
110
Time
(1) APL = 110
.
Figure 7-9. Source Pixels for a Color Channel
Pixel Intensity
Pixel Intensity
255
Clipped
to 255
166
Time
(1) APL = 166
(2) Channel gain = 166/110 = 1.51
Figure 7-10. Pixels for a Color Channel After CAIC
Processing
Above, Figure 7-10 shows the gain that is applied to a color processing channel inside the DLPC34xx.
Additionally, CAIC adjusts the power for the R, G, and B LED by commanding different LED currents. For each
color channel of an individual frame, CAIC intelligently determines the optimal combination of digital gain and
LED power. The user configurable CAIC settings heavily influence the amount of digital gain that is applied to a
color channel and the LED power for that color.
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LED Power (W)
0.33
0.22
0.18
CAIC Disabled
PTOTAL = 1 W
(1)
CAIC Enabled
PTOTAL = 0.73 W
(1) With CAIC enabled, if red and blue LEDs require less than nominal power for a given input image, the red and blue LED power will
reduce.
Figure 7-11. CAIC Power Reduction Mode (for Constant Brightness)
As CAIC applies a digital gain to each color channel and adjusts the power to each LED, CAIC ensures the
resulting color balance in the final image matches the target color balance for the projector system. Thus, the
effective displayed white point of images is held constant by CAIC from frame to frame.
CAIC can be used to increase the overall image brightness while holding the total power for all LEDs constant,
or CAIC can be used to hold the overall image brightness constant while decreasing LED power. In summary,
CAIC has two primary modes of operation:
•
•
Power reduction mode holds overall image brightness constant while reducing LED power
Enhanced brightness mode holds overall LED power constant while enhancing image brightness
In power reduction mode, since the R, G, and B channels can be gained up by CAIC inside the DLPC34xx, the
LED power can be reduced for any color channel until the brightness of the color on the screen is unchanged.
Thus, CAIC can achieve an overall LED power reduction while maintaining the same overall image brightness as
if CAIC was not used. Figure 7-11 shows an example of LED power reduction by CAIC for an image where the
red and blue LEDs can consume less power.
In enhanced brightness mode the R, G, and B channels can be gained up by CAIC with LED power generally
being held constant. This results in an enhanced brightness with no power savings.
While there are two primary modes of operation described, the DLPC34xx actually operates within the extremes
of pure power reduction mode and enhanced brightness mode. The user can configure which operating mode
the DLPC34xx will more closely follow by adjusting the CAIC gain setting as described in the software
programmer's guide.
In addition to the above functionality, CAIC also can be used as a tool with which FOFO (full-on full-off) contrast
on a projection system can be improved. While operating in power reduction mode, the DLPC34xx reduces LED
power as the intensity of the image content for each color channel decreases. This will result in the LEDs
operating at nominal settings with full-on content (a white screen) and reducing power output until the dimmest
possible content (a black screen) is reached. In this latter case, the LEDs will be operating at minimum power
output capacity and thus producing the minimum possible amount of off-state light. This optimization provided by
CAIC will thereby improve FOFO contrast ratio. The given contrast ratio will further increase as nominal LED
current (full-on state) is increased.
7.3.6 Local Area Brightness Boost (LABB)
Local area brightness boost (LABB), part of the IntelliBright™ suite of advanced image processing algorithms,
adaptively gains up regions of an image that are dim relative to the average picture level. The controller applies
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significant gain to some regions of the image, and applies little or no gain to other regions. The LABB algorithm
evaluates images frame-by-frame and calculates the local area gains to be used for each image. Since many
images have a net overall boost in gain, even if the controller applies no gain to some parts of the image, the
controller boosts the overall perceived brightness of the image.
Figure 7-12 below shows a split screen example of the impact of the LABB algorithm for an image that includes
dark areas.
Figure 7-12. LABB enabled (left side) and LABB disabled (right side)
The LABB algorithm operates most effectively when ambient light conditions are used to help determine the
decision about the strength of gains utilized. For this reason, it may be useful to include an ambient light sensor
in the system design that is used to measure the display screen's reflected ambient light. This sensor can assist
in dynamically controlling the LABB strength. Set the LABB gain higher for bright rooms to help overcome
washed out images. Set the LABB gain lower in dark rooms to prevent overdriven pixel intensities in images.
7.3.7 3D Glasses Operation
When using 3D glasses (with 3D video input and appropriate software support), the controller outputs sync
information to align the left eye and right eye shuttering in the glasses with the displayed DMD image frames. 3D
glasses typically use either Infrared (IR) transmission or DLP Link™ technology to achieve this synchronization.
One glasses type uses an IR transmitter on the system PCB to send an IR sync signal to an IR receiver in the
glasses. In this case DLPC34xx controller output signal GPIO_04 can be used to cause the IR transmitter to
send an IR sync signal to the glasses. The Figure 7-13 figure shows the timing sequence for the GPIO_04
signal.
The second type of glasses relies on sync information that is encoded into the light being output from the
projection lens. This approach uses the DLP Link feature for 3D video. Many 3D glasses from different suppliers
have been built using this method. The advantage of using the DLP Link feature is that it takes advantage of
existing projector hardware to transmit the sync information to the glasses. This method may give an advantage
in cost, size and power savings in the projector.
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When using DLP Link technology, one light pulse per DMD frame is output from the projection lens while the
glasses have both shutters closed. To achieve this, the DLPC34xx tells the DLPAxxxx when to turn on the
illumination source (typically LEDs or lasers) so that an encoded light pulse is output once per DMD frame.
Because the shutters in the glasses are both off when the pulse is sent, the projector illumination source is also
off except when the light is sent to create the pulse. The pulses may use any color; however, due to the
transmission property of the eye-glass LCD shutter lenses and the sensitivity of the white-light sensor used on
the eye-glasses, it is highly recommended that blue is not used for pulses. Red pulses are the recommended
color to use. The Figure 7-13 figure below shows 3D timing information. Figure 7-14 and Table 7-7 show the
timing for the light pulses when using the DLP Link feature.
50 Hz or 60 Hz
(HDMI)
L
100 Hz or 120 Hz
(34xx Input)
L
R
L
R
L
R
L
R
L
R
L
R
R
L
R
L
R
L
R
L
R
L
R
L
R
L
R
L
R
L
R
L
R
L
R
3DR (1)(2)
(3D L/R input)
100 Hz or 120 Hz
(on DMD)
GPIO_04 (1)
(3D L/R output)
0 µs (min)
5 µs (max)
GPIO_04
LED_SEL_0, LED_SEL_1
On DMD
Video
Video
Dark time
t1
t2
(1) Left = 1, Right = 0
(2) 3DR must toggle 1 ms before VSYNC
t1: both shutters turned off
t2: next shutter turned on
Figure 7-13. 3D Display Left and Right Frame and Signal Timing
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video data on subframe n
video data on subframe n+1
3D glasses shutter
E
C
B
D
A
Video
A
Video
t1
t2
The time offset of DLP Link pulses at the end of a subframe alternates between B and B+D where D is the delta offset.
Figure 7-14. 3D DLP Link Pulse Timing
Table 7-7. 3D DLP Link Timing
HDMI Source Frame
Rate (Hz)(1)
DLPC34xx Input Frame
Rate (Hz)
A
(µs)
B
(µs)
C
(µs)
D
(µs)
E
(µs)
49.0
98
20 - 32
(31.8 nominal)
> 500
> 622
128 - 163
(161.6 nominal)
> 2000
50.0
100
20 - 32
(31.2 nominal)
> 500
> 658
128 - 163
(158.4 nominal)
> 2000
51.0
102
20 - 32
(30.6 nominal)
> 500
> 655
128 - 163
(155.3 nominal)
> 2000
59.0
118
20 - 32
(26.4 nominal)
> 500
> 634
128 - 163
(134.2 nominal)
> 2000
60.0
120
20 - 32
(26.0 nominal)
> 500
> 632
128 - 163
(132.0 nominal)
> 2000
61.0
122
20 - 32
(25.6 nominal)
> 500
> 630
128 - 163
(129.8 nominal)
> 2000
(1)
Timing parameter C is always the sum of B+D.
7.3.8 Test Point Support
The DLPC34xx test point output port, TSTPT_(7:0), provides selected system calibration and controller debug
support. These test points are inputs when reset is applied. These test points are outputs when reset is released.
The controller samples the signal state upon the release of system reset and then uses the captured value to
configure the test mode until the next time reset is applied. Because each test point includes an internal
pulldown resistor, external pullups must be used to modify the default test configuration.
The default configuration (b000) corresponds to the TSTPT_(2:0) outputs remaining tri-stated to reduce
switching activity during normal operation. For maximum flexibility, a jumper to external pullup resistors is
recommended for TSTPT_(2:0). The pullup resistors on TSTPT_(2:0) can be used to configure the controller for
a specific mode or option. TI does not recommend adding pullup resistors to TSTPT_(7:3) due to potentially
adverse effects on normal operation. For normal use TSTPT_(7:3) should be left unconnected. The test points
are sampled only during a 0-to-1 transition on the RESETZ input, so changing the configuration after reset is
released does not have any effect until the next time reset asserts and releases. Table 7-8 describes the test
mode selections for one programmable scenario defined by TSTPT_(2:0).
Table 7-8. Test Mode Selection Scenario Defined by TSTPT_(2:0)
TSTPT OUTPUT VALUE(1)
NO SWITCHING ACTIVITY
CLOCK DEBUG OUTPUT
TSTPT_(2:0) = 0b000
TSTPT_(2:0) = 0b010
TSTPT_0
HI-Z
60 MHz
TSTPT_1
HI-Z
30 MHz
TSTPT_2
HI-Z
0.7 to 22.5 MHz
TSTPT_3
HI-Z
HIGH
TSTPT_4
HI-Z
LOW
TSTPT_5
HI-Z
HIGH
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Table 7-8. Test Mode Selection Scenario Defined by TSTPT_(2:0) (continued)
TSTPT OUTPUT VALUE(1)
(1)
NO SWITCHING ACTIVITY
CLOCK DEBUG OUTPUT
TSTPT_(2:0) = 0b000
TSTPT_(2:0) = 0b010
TSTPT_6
HI-Z
HIGH
TSTPT_7
HI-Z
7.5 MHz
These are default output selections. Software can reprogram the selection at any time.
7.3.9 DMD Interface
The DLPC34xx controller DMD interface consists of one high-speed (HS), 1.8-V sub-LVDS, output-only interface
and one low speed (LS), 1.8-V LVCMOS SDR interface with a typical fixed clock speed of 120 MHz.
7.3.9.1 Sub-LVDS (HS) Interface
The DLPC3439 controller to DMD interface consists of a HS 1.8-V sub-LVDS output only interface with a
maximum clock speed of 532-MHz DDR and a LS SDR (1.8-V LVCMOS) interface with a fixed clock speed of
120 MHz.Table 7-9 shows the two options available for the DLP4710 DMD.
Table 7-9. DLPC3439 (Master and Slave) to DLP4710 (.47 1080p) DMD 8-Lane DMD Pin Mapping
DLPC3439 controller 8 LANE DMD ROUTING OPTION #1
MASTER DLPC3439 PINS
SLAVE DLPC3439 PINS
DMD PINS
HS_WDATA_D_P
HS_WDATA_D_N
HS_WDATA_E_P
HS_WDATA_E_N
Input DATA_p_0
Input DATA_n_0
HS_WDATA_C_P
HS_WDATA_C_N
HS_WDATA_F_P
HS_WDATA_F_N
Input DATA_p_1
Input DATA_n_1
HS_WDATA_B_P
HS_WDATA_B_N
HS_WDATA_G_P
HS_WDATA_G_N
Input DATA_p_2
Input DATA_n_2
HS_WDATA_A_P
HS_WDATA_A_N
HS_WDATA_H_P
HS_WDATA_H_N
Input DATA_p_3
Input DATA_n_3
HS_WDATA_H_P
HS_WDATA_H_N
HS_WDATA_A_P
HS_WDATA_A_N
Input DATA_p_4
Input DATA_n_4
HS_WDATA_G_P
HS_WDATA_G_N
HS_WDATA_B_P
HS_WDATA_B_N
Input DATA_p_5
Input DATA_n_5
HS_WDATA_F_P
HS_WDATA_F_N
HS_WDATA_C_P
HS_WDATA_C_N
Input DATA_p_6
Input DATA_n_6
HS_WDATA_E_P
HS_WDATA_E_N
HS_WDATA_D_P
HS_WDATA_D_N
Input DATA_p_7
Input DATA_n_7
DLPC3439 controller 8 LANE DMD ROUTING OPTION #2
42
MASTER DLPC3439 PINS
SLAVE DLPC3439 PINS
DMD PINS
HS_WDATA_E_P
HS_WDATA_E_N
HS_WDATA_D_P
HS_WDATA_D_N
Input DATA_p_0
Input DATA_n_0
HS_WDATA_F_P
HS_WDATA_F_N
HS_WDATA_C_P
HS_WDATA_C_N
Input DATA_p_1
Input DATA_n_1
HS_WDATA_G_P
HS_WDATA_G_N
HS_WDATA_B_P
HS_WDATA_B_N
Input DATA_p_2
Input DATA_n_2
HS_WDATA_H_P
HS_WDATA_H_N
HS_WDATA_A_P
HS_WDATA_A_N
Input DATA_p_3
Input DATA_n_3
HS_WDATA_A_P
HS_WDATA_A_N
HS_WDATA_H_P
HS_WDATA_H_N
Input DATA_p_4
Input DATA_n_4
HS_WDATA_B_P
HS_WDATA_B_N
HS_WDATA_G_P
HS_WDATA_G_N
Input DATA_p_5
Input DATA_n_5
HS_WDATA_C_P
HS_WDATA_C_N
HS_WDATA_F_P
HS_WDATA_F_N
Input DATA_p_6
Input DATA_n_6
HS_WDATA_D_P
HS_WDATA_D_N
HS_WDATA_E_P
HS_WDATA_E_N
Input DATA_p_7
Input DATA_n_7
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High Speed sub-LVDS DDR Interface
High Speed sub-LVDS DDR Interface
DLPC34xx Slave
DMD_HS_WDATA_A_N
S_DMD_HS_WDATA_A_N
DMD_HS_WDATA_A_P
S_DMD_HS_WDATA_A_P
DMD_HS_WDATA_B_N
S_DMD_HS_WDATA_B_N
(Example DMD)
DLP4710
1920 x 1080
display
Sub-LVDS-DMD
DMD_HS_WDATA_B_P
DMD_HS_WDATA_C_N
S_DMD_HS_WDATA_B_P
S_DMD_HS_WDATA_C_N
DMD_HS_WDATA_C_P
S_DMD_HS_WDATA_C_P
DMD_HS_WDATA_D_N
S_DMD_HS_WDATA_D_N
DMD_HS_WDATA_D_P
S_DMD_HS_WDATA_D_P
DMD_HS_CLK_N
S_DMD_HS_CLK_N
DMD_HS_CLK_P
S_DMD_HS_CLK_P
DMD_HS_WDATA_E_N
S_DMD_HS_WDATA_E_N
DMD_HS_WDATA_E_P
S_DMD_HS_WDATA_E_P
DMD_HS_WDATA_F_N
S_DMD_HS_WDATA_F_N
DMD_HS_WDATA_F_P
S_DMD_HS_WDATA_F_P
DMD_HS_WDATA_G_N
S_DMD_HS_WDATA_G_N
DMD_HS_WDATA_G_P
S_DMD_HS_WDATA_G_P
DMD_HS_WDATA_H_N
S_DMD_HS_WDATA_H_N
DMD_HS_WDATA_H_P
S_DMD_HS_WDATA_H_P
DMD_LS_CLK
DMD_LS_WDATA
DMD_DEN_ARSTZ
S_DMD_LS_CLK
S_DMD_LS_WDATA
S_DMD_DEN_ARSTZ
DMD_LS_RDATA
S_DMD_LS_RDATA
Low Speed SDR Interface (120 MHz)
Low Speed SDR Interface (120 MHz)
Figure 7-15. DLP4710 (.47 1080p) DMD Interface
The sub-LVDS high-speed interface waveform quality and timing on the DLPC34xx controller depends on the
total length of the interconnect system, the spacing between traces, the characteristic impedance, etch losses,
and how well matched the lengths are across the interface. Thus, ensuring positive timing margin requires
attention to many factors.
In an attempt to minimize the signal integrity analysis that would otherwise be required, the DMD Control and
Sub-LVDS Signals layout section is provided as a reference of an interconnect system that satisfy both
waveform quality and timing requirements (accounting for both PCB routing mismatch and PCB signal integrity).
Variation from these recommendations may also work, but should be confirmed with PCB signal integrity
analysis or lab measurements.
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7.4 Device Functional Modes
The DLPC34xx controller has two functional modes (ON and OFF) controlled by a single pin, PROJ_ON
(GPIO_08).
•
•
When the PROJ_ON pin is set high, the controller powers up and can be programmed to send data to the
DMD.
When the PROJ_ON pin is set low, the controller powers down and consumes minimal power.
7.5 Programming
The DLPC34xx controller contains an Arm® Cortex®-M3 processor with additional functional blocks to enable
video processing and control. TI provides software as a firmware image. The customer is required to flash this
firmware image onto the SPI flash memory. The DLPC34xx controller loads this firmware during startup and
regular operation. The controller and its accompanying DLP chipset requires this proprietary software to operate.
The available controller functions depend on the firmware version installed. Different firmware is required for
different chipset combinations (such as when using different PMIC devices). See Documentation Support at the
end of this document or contact TI to view or download the latest published software.
Users can modify software behavior through I2C interface commands. For a list of commands, view the software
user's guide accessible through the Documentation Support page.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The DLPC34xx controller is used with the DLP4710 DMD to provide a reliable display solution for many data and
video display applications. The DMDs are spatial light modulators which reflect incoming light from an
illumination source to one of two directions, with the primary direction being into projection or collection optics.
The optical architecture of the system and the format of the image digital data coming into the DLPC34xx are
what primarily determine the application requirements.
Click these links to find more information about typical applications:
DLP Signage, Mobile Projector, Mobile Smart TV, Commercial gaming displays, Smart home displays, Pico
projectors.
8.2 Typical Application
A common application using a DLPC3439 controller with a DLP4710 DMD and a DLPA3000/DLPA3005
PMIC/LED driver is creating an accessory Pico projector for a smartphone, tablet, or any other display source.
The DLPC3439 in the accessory Pico projector typically receives images from a host processor or a multi media
processor.
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Projector Module
Electronics
+ Battery –
DMD/
DLPC
Bucks
Fan(s)
Sensors
1.1 V
1.8 V
2.5 V
AUX
LDOs
3.3 V
SYSPWR
VLED
DC
Supplies
Charger
DLPA3000
RLIM
SPI1
PARKZ
Control (4)
RESETZ
INTZ
Thermistor
CMP_OUT
PROJ_ON
GPIO_8
HOST_IRQ
Triple
ADC
GPIO_10
Parallel (28)
HDMI
Receiver
Front-End
Chip
RC_CHARGE
DLPC3439
eDRAM
3DR
RESETZ
VCC_INTF
1.8V
OSD
Autolock
Scaler
Keystone
Micro-controller
1.1V
VIO
SPI0
VCORE
I2C_1
GPIO_14-19
SPI (4)
Flash
TI Device
LS_RDATA
I2C_0
Sub-LVDS DATA
Image Sync
Oscillator
Non-TI Device
DLP4710
DMD
Sub-LVDS DATA
LS_RDATA
VCC_INTF
Keypad
VCC, VBIAS,
VOFFSET, VRESET
I2C
Flash,
SDRAM
SD Card
Reader,
Video
Decoder
Illumination
optics
1.1 V
VDD
Flash
SPI (4)
DLPC3439
eDRAM
SPI0
Parallel (28)
3DR
VCC_INTF
PARKZ
1.8V
VIO
1.1V
VCORE
INTZ
RESETZ
Figure 8-1. Typical Application Diagram
8.2.1 Design Requirements
A Pico projector is created by using a DLP chipset comprised of a DLP4710 (.47 1080p) DMD, a 2xDLPC3439
controller and a DLPA3000/DLPA3005 PMIC/LED driver. The DLPC3439 does the digital image processing, the
DLPA3000/DLPA3005 provides the needed analog functions for the projector, and the DMD is the display device
for producing the projected image.
In addition to the three DLP chips in the chipset, other chips may be needed. At a minimum a flash part is
needed to store the software and firmware to control the DLPC3439.
The illumination light that is applied to the DMD is typically from red, green, and blue LEDs. These are often
contained in three separate packages, but sometimes more than one color of LED die may be in the same
package to reduce the overall size of the pico-projector.
For connecting the DLPC3439 to the host processing for receiving images, parallel interface is used. I2C should
be connected to the host processor for sending commands to the DLPC3439.
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The only power supply needed external to the DLPC3439-based chipset is an AC adapter or battery to provide
the SYSPWR DC voltage. The DLPA3000 or DLPA3005 PMIC will create all of the DC supplies needed by the
DLPC3439-based chipset as well as those needed by all other electronics in the projector.
The entire pico-projector can be turned on and off by using a single signal called PROJ_ON. When PROJ_ON is
high, the projector turns on and begins displaying images. When PROJ_ON is set low, the projector turns off and
draws just microamps of current on SYSPWR. When PROJ_ON is set low, the 1.8-V supply can continue to be
left at 1.8 V and used by other non-projector sections of the product. If PROJ_ON is low, the DLPA3000/
DLPA3005 will not draw current on the 1.8-V supply.
8.2.2 Detailed Design Procedure
For connecting together the DLP4710 (.47 1080p) DMD, the 2xDLPC3439 controller, and the DLPA3000/
DLPA3005 PMIC/LED driver, see the reference design schematic. When a circuit board layout is created from
this schematic, a very small circuit board is possible. An example small board layout is included in the reference
design data base. Follow the layout guidelines to achieve a reliable projector.
The optical engine that has the LED packages and the DMD mounted to it is typically supplied by an optical
OEM who specializes in designing optics for DLP projectors.
8.2.3 Application Curve
As the LED currents that are driven time-sequentially through the red, green, and blue LEDs are increased, the
brightness of the projector increases. This increase is somewhat non-linear, and the curve for typical white
screen lumens changes with LED currents is shown in Figure 8-2. For the LED currents shown, it is assumed
that the same current amplitude is applied to the red, green, and blue LEDs. The shape of the curve depends on
the LED devices used as well as the LED system-level heat sink implementation.
SPACE
1
0.9
0.8
Luminance
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
100
200
300
400
Current (mA)
500
600
700
D001
Figure 8-2. Typical Luminance vs Current
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9 Power Supply Recommendations
9.1 PLL Design Considerations
It is acceptable for the VDD_PLLD and VDD_PLLM to be derived from the same regulator as the core VDD.
However, to minimize the AC noise component, apply a filter as recommended in the PLL Power Layout section.
9.2 System Power-Up and Power-Down Sequence
9.2.1
Although the DLPC34xx controller requires an array of power supply voltage pins (for example, VDD, VDDLP12,
VDD_PLLM/D, VCC18, VCC_FLSH, and VCC_INTF), if VDDLP12 is tied to the 1.1-V VDD supply (which is
assumed to be the typical configuration), then there are no restrictions regarding the relative order of power
supply sequencing to avoid damaging the DLPC34xx controller (this remains true for both power-up and powerdown scenarios). The controller requires no minimum delay time between powering-up and powering-down the
individual supplies if the VDDLP12 is tied to the 1.1-V VDD supply.
However, if the VDDLP12 pin is not tied to the VDD supply, then the VDDLP12 pin must be powered-on only
after the VDD supply is powered-on. And in a similar sequence, the VDDLP12 pin must be powered-off before
the VDD supply is powered-off. If the VDDLP12 pin is not tied to VDD, then the VDDLP12 pin and VDD supply
pins must be powered-on or powered-off within 100 ms of each other.
Although there is no risk of damaging the DLPC34xx controller when the above power sequencing rules are
followed, these additional power sequencing recommendations must be considered to ensure proper system
operation:
•
•
To ensure that the DLPC34xx controller output signal states behave as expected, all controller I/O supplies
are encouraged to remain applied while VDD core power is applied. If VDD core power is removed while the
I/O supply (VCC_INTF) is applied, then the output signal states associated with the inactive I/O supply go to
a high impedance state.
Because additional power sequencing rules may exist for devices that share the supplies with the DLPC34xx
controller (such as the PMIC and DMD), these devices may force additional system power sequencing
requirements.
Figure 9-1, Figure 9-2, and Figure 9-3 show the DLPC34xx power-up sequence, the normal PARK power-down
sequence, and the fast PARK power-down sequence of a typical DLPC34xx system.
When the VDD core power is applied, but I/O power is not applied, the controller may draw additional leakage
current. This leakage current does not affect the normal DLPC34xx controller operation or reliability.
Note
During a Normal Park it is recommended to maintain SYSPWR within specification for at least 50 ms
after PROJ_ON goes low. This is to allow the DMD to be parked and the power supply rails to safely
power down. After 50 ms, SYSPWR can be turned off. If a DLPA200x is used, it is also recommended
that the 1.8-V supply fed into the DLPA200x load switch be maintained within specification for at least
50 ms after PROJ_ON goes low.
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Signals
from PMIC (DLPA3000)
from other source
Power
Startup
System State
Pre-Initialization
Initialization
Regular Operation
SYSPWR
PROJ_ON (GPIO_8)
VDD (1.1 V)
VDD_PLLM/D (1.1 V)
(a)
VDDLP12 (if not tied to VDD)
VCC18 (1.8 V)
VCC_INTF (e.g. 1.8 V)
VCC_FLSH (e.g. 1.8 V)
PARKZ
(c)
(b)
PLL_REFCLK
(d)
HOST_IRQ
RESETZ
(e)
I2C (activity)
t0
t1
t2
t3
t0:
SYSPWR applied to the PMIC. All other voltage rails are derived from SYSPWR.
t1:
All supplies reach 95% of their specified nominal value. Note HOST_IRQ may go high sooner if it is pulled-up to a different
external supply.
t2:
Point where RESETZ is deasserted (goes high). This indicates the beginning of the controller auto-initialization routine.
t3:
HOST_IRQ goes low to indicate initialization is complete.
(a):
VDDLP12 must be powered on after VDD if it is supplied from a separate source.
(b):
PLL_REFCLK is allowed to be active before power is applied.
(c):
PLL_REFCLK must be stable within 5 ms of all power being applied. For external oscillator applications this is oscillator
dependent, and for crystal applications this is crystal and controller oscillator cell dependent.
(d):
PARKZ must be high before RESETZ releases to support auto-initialization. RESETZ must also be held low for at least 5 ms
after the power supplies are in specification.
(e):
I2C activity cannot start until HOST_IRQ goes low to indicate auto-initialization completes.
Figure 9-1. System Power-Up Waveforms (With DLPA3000)
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Signals
from PMIC (DLPA3000)
from other source
System State
Normal
Park
Regular operation
Power supply shutdown
(b)
SYSPWR
(c)
PROJ_ON (GPIO_8)
VDD (1.1 V)
VDD_PLLM/D (1.1 V)
VDDLP12
(if not tied to VDD)
VCC18 (1.8 V)
VCC_INTF (e.g. 1.8 V)
VCC_FLSH (e.g. 1.8 V)
PARKZ
PLL_REFCLK
HOST_IRQ
RESETZ
(a)
I2C (activity)
t1
t2
t3
t4
t5
t1:
PROJ_ON goes low to begin the power down sequence.
t2:
The controller finishes parking the DMD.
t3:
RESETZ is asserted which causes HOST_IRQ to be pulled high.
t4:
All controller power supplies are turned off.
t5:
SYSPWR is removed now that all other supplies are turned off.
(a):
I2C activity must stop before PROJ_ON is deasserted (goes low).
(b):
The DMD will be parked within 20 ms of PROJ_ON being deasserted (going low). VDD, VDD_PLLM/D, VCC18, VCC_INITF, and
VCC_FLSH power supplies and the PLL_REFCLK must be held within specification for a minimum of 20 ms after PROJ_ON is
deasserted (goes low). However, 20 ms does not satisfy the typical shutdown timing of the entire chipset. It is therefore
recommended to follow note (c).
(c):
It is recommended that SYSPWR not be turned off for 50 ms after PROJ_ON is deasserted (goes low). This time allows the
DMD to be parked, the controller to turn off, and the PMIC supplies to shut down.
Figure 9-2. Normal Park Power-Down Waveforms
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Signals
from PMIC (DLPA3000)
from other source
System State
Fast
Park
(a)
Regular operation
Power supplies collapse
SYSPWR
PROJ_ON (GPIO_8)
VDD (1.1 V)
VDD_PLLM/D (1.1 V)
VDDLP12
(if not tied to VDD)
VCC18 (1.8 V)
(b)
VCC_INTF (e.g. 1.8 V)
VCC_FLSH (e.g. 1.8 V)
PARKZ
PLL_REFCLK
HOST_IRQ
RESETZ
I2C (activity)
t1
t2 t3
t4
t1:
A fault is detected (in this example the PMIC detects a UVLO condition) and PARKZ is asserted (goes low) to tell the controller to
initiate a fast park of the DMD.
t2:
The controller finishes the fast park procedure.
t3:
RESETZ is asserted which puts the controller in a reset state which causes HOST_IRQ to be pulled high.
t4:
Eventually all power supplies that were derived from SYSPWR collapse.
(a):
VDD, VDD_PLLM/D, VCC18, VCC_INITF, and VCC_FLSH power supplies and the PLL_REFCLK must be held within
specification for a minimum of 32 µs after PARKZ is asserted (goes low).
(b):
VCC18 must remain in specification long enough to satisfy DMD power sequencing requirements defined in the DMD datasheet.
Also see the DLPAxxxx datasheets for more information.
Figure 9-3. Fast Park Power-Down Waveforms
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9.3 Power-Up Initialization Sequence
An external power monitor is required to hold the DLPC34xx controller in system reset during the power-up
sequence by driving RESETZ to a logic-low state. It shall continue to drive RESETZ low until all controller
voltages reach the minimum specified voltage levels, PARKZ goes high, and the input clocks are stable. The
external power monitoring is automatically done by the DLPAxxxx PMIC.
No signals output by the DLPC34xx controller will be in their active state while RESETZ is asserted. The
following signals are tri-stated while RESETZ is asserted:
•
•
•
•
•
SPI0_CLK
SPI0_DOUT
SPI0_CSZ0
SPI0_CSZ1
GPIO [19:00]
Add external pullup (or pulldown) resistors to all tri-stated output signals (including bidirectional signals to be
configured as outputs) to avoid floating controller outputs during reset if they are connected to devices on the
PCB that can malfunction. For SPI, at a minimum, include a pullup to any chip selects connected to devices.
Unused bidirectional signals can be configured as outputs in order to avoid floating controller inputs after
RESETZ is set high.
The following signals are forced to a logic low state while RESETZ is asserted and the corresponding I/O power
is applied:
•
•
•
LED_SEL_0
LED_SEL_1
DMD_DEN_ARSTZ
After power is stable and the PLL_REFCLK_I clock input to the DLPC34xx controller is stable, then RESETZ
should be deactivated (set to a logic high). The DLPC34xx controller then performs a power-up initialization
routine that first locks its PLL followed by loading self configuration data from the external flash. Upon release of
RESETZ, all DLPC34xx I/Os will become active. Immediately following the release of RESETZ, the HOST_IRQ
signal will be driven high to indicate that the auto initialization routine is in progress. However, since a pullup
resistor is connected to signal HOST_IRQ, this signal will have already gone high before the controller actively
drives it high. Upon completion of the auto-initialization routine, the DLPC34xx controller will drive HOST_IRQ
low to indicate the initialization done state of the controller has been reached.
To ensure reliable operation, during the power-up initialization sequence, GPIO_08 (PROJ_ON) must not be
deasserted. In other words, once the startup routine has begun (by asserting PROJ_ON), the startup routine
must complete (indicated by HOST_IRQ going low) before the controller can be commanded off (by deasserting
PROJ_ON).
Note
No I2C or DSI (if applicable) activity is permitted until HOST_IRQ goes low.
9.4 DMD Fast Park Control (PARKZ)
PARKZ is an input early warning signal that must alert the controller at least 32 µs before DC supply voltages
drop below specifications. Typically, the PARKZ signal is provided by the DLPAxxxx interrupt output signal.
PARKZ must be deasserted (set high) prior to releasing RESETZ (that is, prior to the low-to-high transition on
the RESETZ input) for normal operation. When PARKZ is asserted (set low) the controller performs a Fast Park
operation on the DMD which assists in maintaining the lifetime of the DMD. The reference clock must continue
running and RESETZ must remain deactivated for at least 32 µs after PARKZ has been asserted (set low) to
allow the park operation to complete.
Fast Park operation is only intended for use when loss of power is imminent and beyond the control of the host
processor (for example, when the external power source has been disconnected or the battery has dropped
below a minimum level). The longest lifetime of the DMD may not be achieved with Fast Park operation. The
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longest lifetime is achieved with a Normal Park operation (initiated through GPIO_08). Hence, PARKZ is typically
only used instead of a Normal Park request if there is not enough time for a Normal Park. A Normal Park
operation takes much longer than 32 µs to park the mirrors. During a Normal Park operation, the DLPAxxxx
keeps on all power supplies, and keeps RESETZ high, until the longer mirror parking has completed.
Additionally, the DLPAxxxx may hold the supplies on for a period of time after the parking has been completed.
View the relevant DLPAxxxx datasheet for more information. The longer mirror parking time ensures the longest
DMD lifetime and reliability. The DMD Parking Switching Characteristics section specifies the park timings.
9.5 Hot Plug I/O Usage
The DLPC34xx controller provides fail-safe I/O on all host interface signals (signals powered by VCC_INTF).
This allows these inputs to externally be driven even when no I/O power is applied. Under this condition, the
controller does not load the input signal nor draw excessive current that could degrade controller reliability. For
example, the I2C bus from the host to other components is not affected by powering off VCC_INTF to the
DLPC34xx controller. The allows additional devices on the I2C bus to be utilized even if the controller is not
powered on. TI recommends weak pullup or pulldown resistors to avoid floating inputs for signals that feed back
to the host.
If the I/O supply (VCC_INTF) powers off, but the core supply (VDD) remains on, then the corresponding input
buffer may experience added leakage current; however, the added leakage current does not damage the
DLPC34xx controller.
However, if VCC_INTF is powered and VDD is not powered, the controller may drives the IIC0_xx pins low which
prevents communication on this I2C bus. Do not power up the VCC_INTF pin before powering up the VDD pin
for any system that has additional secondary devices on this bus.
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10 Layout
10.1 Layout Guidelines
For a summary of the PCB design requirements for the DLPC34xx controller see PCB Design Requirements for
TI DLP Pico TRP Digital Micromirror Devices. Some applications (such as high frame rate video) may require the
use of 1-oz (or greater) copper planes to manage the controller package heat.
10.1.1 PLL Power Layout
Follow these recommended guidelines to achieve acceptable controller performance for the internal PLL. The
DLPC34xx controller contains two internal PLLs which have dedicated analog supplies (VDD_PLLM,
VSS_PLLM, VDD_PLLD, and VSS_PLLD). At a minimum, isolate the VDD_PLLx power and VSS_PLLx ground
pins using a simple passive filter consisting of two series ferrite beads and two shunt capacitors (to widen the
spectrum of noise absorption). It is recommended that one capacitor be 0.1 µF and one be 0.01 µF. Place all
four components as close to the controller as possible. It is especially important to keep the leads of the high
frequency capacitors as short as possible. Connect both capacitors from VDD_PLLM to VSS_PLLM and
VDD_PLLD to VSS_PLLD on the controller side of the ferrite beads.
Select ferrite beads with these characteristics:
•
•
•
DC resistance less than 0.40 Ω
Impedance at 10 MHz equal to or greater than 180 Ω
Impedance at 100 MHz equal to or greater than 600 Ω
The PCB layout is critical to PLL performance. It is vital that the quiet ground and power are treated like analog
signals. Therefore, VDD_PLLM and VDD_PLLD must be a single trace from the DLPC34xx controller to both
capacitors and then through the series ferrites to the power source. Make the power and ground traces as short
as possible, parallel to each other, and as close as possible to each other.
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signal via
via to common analog digital board power plane
PCB pad
Controller pad
via to common analog digital board ground plane
1
2
3
4
F
Signal
Signal
Signal
VSS
G
Signal
Signal
VSS_
PLLM
VSS
5
A
Local
decoupling
for the PLL
digital
supply
GND
FB
VDD_
PLLM
VSS_
PLLD
VSS
0.01 µF
PLL_
REF
CLK_I
0.1 µF
H
1.1-V
Power
FB
Crystal
Circuit
J
PLL_
REF
CLK_O
VDD_
PLLD
VSS
VDD
VDD
Figure 10-1. PLL Filter Layout
10.1.2 Reference Clock Layout
The DLPC34xx controller requires an external reference clock to feed the internal PLL. Use either a crystal or
oscillator to supply this reference. The DLPC34xx reference clock must not exceed a frequency variation of ±200
ppm (including aging, temperature, and trim component variation).
Figure 10-2 shows the required discrete components when using a crystal.
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PLL_REFCLK_I
PLL_REFCLK_O
RFB
RS
Crystal
CL1
CL2
CL = Crystal load capacitance (farads)
CL1 = 2 × (CL – Cstray_pll_refclk_i)
CL2 = 2 × (CL – Cstray_pll_refclk_o)
where:
• Cstray_pll_refclk_i = Sum of package and PCB stray capacitance at the crystal pin associated with the controller pin pll_refclk_i.
• Cstray_pll_refclk_o = Sum of package and PCB stray capacitance at the crystal pin associated with the controller pin pll_refclk_o.
Figure 10-2. Required Discrete Components
10.1.2.1 Recommended Crystal Oscillator Configuration
Table 10-1. Crystal Port Characteristics
PARAMETER
NOM
UNIT
PLL_REFCLK_I TO GND capacitance
1.5
pF
PLL_REFCLK_O TO GND capacitance
1.5
pF
Table 10-2. Recommended Crystal Configuration
PARAMETER (1) (2)
RECOMMENDED
Crystal circuit configuration
Parallel resonant
Crystal type
Fundamental (first harmonic)
Crystal nominal frequency
24
MHz
Crystal frequency tolerance (including accuracy, temperature, aging and trim sensitivity) ±200
Maximum startup time
UNIT
PPM
1.0
ms
Crystal equivalent series resistance (ESR)
120 (max)
Ω
Crystal load
6
pF
RS drive resistor (nominal)
100
RFB feedback resistor (nominal)
1
MΩ
Ω
CL1 external crystal load capacitor
See equation in Figure 1-1 notes
pF
CL2 external crystal load capacitor
See equation in Figure 1-1 notes
pF
PCB layout
A ground isolation ring around the
crystal is recommended
(1)
(2)
Temperature range of –30°C to 85°C.
The crystal bias is determined by the controllers VCC_INTF voltage rail, which is variable (not the VCC18 rail).
If an external oscillator is used, then the oscillator output must drive the PLL_REFCLK_I pin on the DLPC34xx
controller, and the PLL_REFCLK_O pin must be left unconnected.
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Table 10-3. Recommended Crystal Parts
(1) (2)
PART NUMBER
SPEED
(MHz)
TEMPERATURE
AND AGING
(ppm)
MAXIMUM
ESR (Ω)
LOAD
CAPACITANCE
(pF)
PACKAGE
DIMENSIONS
(mm)
KDS
DSX211G-24.000M-8pF-50-50
24
±50
120
8
2.0 × 1.6
Murata
XRCGB24M000F0L11R0
24
±100
120
6
2.0 × 1.6
NDK
NX2016SA 24M
EXS00A-CS05733
24
±145
120
6
2.0 × 1.6
MANUFACTURER
(1)
(2)
The crystal devices in this table have been validated to work with the DLPC34xx controller. Other devices may also be compatible but
have not necessarily been validated by TI.
Operating temperature range: –30°C to 85°C for all crystals.
10.1.3 Unused Pins
To avoid potentially damaging current caused by floating CMOS input-only pins, TI recommends tying unused
controller input pins through a pullup resistor to its associated power supply or a pulldown resistor to ground. For
controller inputs with internal pullup or pulldown resistors, it is unnecessary to add an external pullup or pulldown
unless specifically recommended. Note that internal pullup and pulldown resistors are weak and should not be
expected to drive an external device. The DLPC34xx controller implements very few internal resistors and are
listed in the tables found in the Pin Configuration and Functions section. When external pullup or pulldown
resistors are needed for pins that have weak pullup or pulldown resistors, choose a maximum resistance of 8
kΩ.
Never tie unused output-only pins directly to power or ground. Leave them open.
When possible, TI recommends that unused bidirectional I/O pins are configured to their output state such that
the pin can remain open. If this control is not available and the pins may become an input, then include an
appropriate pullup (or pulldown) resistor.
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10.1.4 DMD Control and Sub-LVDS Signals
Table 10-4. Maximum Pin-to-Pin PCB Interconnect Recommendations
SIGNAL INTERCONNECT TOPOLOGY
DMD BUS SIGNAL(1) (2)
SINGLE-BOARD SIGNAL
ROUTING LENGTH
MULTI-BOARD SIGNAL
ROUTING LENGTH
UNIT
6.0
(152.4)
See (3)
in
(mm)
6.0
(152.4)
See (3)
in
(mm)
DMD_LS_CLK
6.5
(165.1)
See (3)
in
(mm)
DMD_LS_WDATA
6.5
(165.1)
See (3)
in
(mm)
DMD_LS_RDATA
6.5
(165.1)
See (3)
in
(mm)
DMD_DEN_ARSTZ
7.0
(177.8)
See (3)
in
(mm)
DMD_HS_CLK_P
DMD_HS_CLK_N
DMD_HS_WDATA_A_P
DMD_HS_WDATA_A_N
DMD_HS_WDATA_B_P
DMD_HS_WDATA_B_N
DMD_HS_WDATA_C_P
DMD_HS_WDATA_C_N
DMD_HS_WDATA_D_P
DMD_HS_WDATA_D_N
DMD_HS_WDATA_E_P
DMD_HS_WDATA_E_N
DMD_HS_WDATA_F_P
DMD_HS_WDATA_F_N
DMD_HS_WDATA_G_P
DMD_HS_WDATA_G_N
DMD_HS_WDATA_H_P
DMD_HS_WDATA_H_N
(1)
(2)
(3)
58
Maximum signal routing length includes escape routing.
Multi-board DMD routing length is more restricted due to the impact of the connector.
Due to PCB variations, these recommendations cannot be defined. Any board design should SPICE simulate with the controller IBIS
model (found under the Tools & Software tab of the controller web page) to ensure routing lengths do not violate signal requirements.
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Table 10-5. High Speed PCB Signal Routing Matching Requirements
SIGNAL GROUP LENGTH MATCHING(1) (2) (3)
INTERFACE
SIGNAL GROUP
REFERENCE SIGNAL
MAX MISMATCH(4)
UNIT
DMD_HS_CLK_P
DMD_HS_CLK_N
±1.0
(±25.4)
in
(mm)
DMD_HS_WDATA_A_P
DMD_HS_WDATA_A_N
DMD_HS_WDATA_B_P
DMD_HS_WDATA_B_N
DMD_HS_WDATA_C_P
DMD_HS_WDATA_C_N
DMD(5)
DMD_HS_WDATA_D_P
DMD_HS_WDATA_D_N
DMD_HS_WDATA_E_P
DMD_HS_WDATA_E_N
DMD_HS_WDATA_F_P
DMD_HS_WDATA_F_N
DMD_HS_WDATA_G_P
DMD_HS_WDATA_G_N
DMD_HS_WDATA_H_P
DMD_HS_WDATA_H_N
(1)
(2)
(3)
(4)
(5)
DMD
DMD_HS_WDATA_x_P
DMD_HS_WDATA_x_N
±0.025
(±0.635)
in
(mm)
DMD
DMD_HS_CLK_P
DMD_HS_CLK_N
±0.025
(±0.635)
in
(mm)
DMD
DMD_LS_WDATA
DMD_LS_RDATA
DMD_LS_CLK
±0.2
(±5.08)
in
(mm)
DMD
DMD_DEN_ARSTZ
N/A
N/A
in
(mm)
The length matching values apply to PCB routing lengths only. Internal package routing mismatch associated with the DLPC34xx
controller or the DMD require no additional consideration.
Training is applied to DMD HS data lines. This is why the defined matching requirements are slightly relaxed compared to the LS data
lines.
DMD LS signals are single ended.
Mismatch variance for a signal group is always with respect to the reference signal.
DMD HS data lines are differential, thus these specifications are pair-to-pair.
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Table 10-6. Signal Requirements
PARAMETER
Source series termination
Endpoint termination
PCB impedance
Signal type
REFERENCE
REQUIREMENT
DMD_LS_WDATA
Required
DMD_LS_CLK
Required
DMD_DEN_ARSTZ
Acceptable
DMD_LS_RDATA
Required
DMD_HS_WDATA_x_y
Not acceptable
DMD_HS_CLK_y
Not acceptable
DMD_LS_WDATA
Not acceptable
DMD_LS_CLK
Not acceptable
DMD_DEN_ARSTZ
Not acceptable
DMD_LS_RDATA
Not acceptable
DMD_HS_WDATA_x_y
Not acceptable
DMD_HS_CLK_y
Not acceptable
DMD_LS_WDATA
68 Ω ±10%
DMD_LS_CLK
68 Ω ±10%
DMD_DEN_ARSTZ
68 Ω ±10%
DMD_LS_RDATA
68 Ω ±10%
DMD_HS_WDATA_x_y
100 Ω ±10%
DMD_HS_CLK_y
100 Ω ±10%
DMD_LS_WDATA
SDR (single data rate) referenced to DMD_LS_DCLK
DMD_LS_CLK
SDR referenced to DMD_LS_DCLK
DMD_DEN_ARSTZ
SDR
DMD_LS_RDATA
SDR referenced to DMD_LS_DLCK
DMD_HS_WDATA_x_y
sub-LVDS
DMD_HS_CLK_y
sub-LVDS
10.1.5 Layer Changes
•
•
Single-ended signals: Minimize the number of layer changes.
Differential signals: Individual differential pairs can be routed on different layers. Ideally ensure that the
signals of a given pair do not change layers.
10.1.6 Stubs
•
Avoid using stubs.
10.1.7 Terminations
•
•
•
•
DMD_HS differential signals require no external termination resistors.
Make sure the DMD_LS_CLK and DMD_LS_WDATA signal paths include a 43-Ω series termination resistor
located as close as possible to the corresponding controller pins.
Make sure the DMD_LS_RDATA signal path includes a 43-Ω series termination resistor located as close as
possible to the corresponding DMD pin.
The DMD_DEN_ARSTZ pin requires no series resistor.
10.1.8 Routing Vias
•
•
•
60
The number of vias on DMD_HS signals must be minimized and ideally not exceed two.
Any and all vias on DMD_HS signals must be located as close to the controller as possible.
The number of vias on the DMD_LS_CLK and DMD_LS_WDATA signals must be minimized and ideally not
exceed two.
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Any and all vias on the DMD_LS_CLK and DMD_LS_WDATA signals must be located as close to the
controller as possible.
10.1.9 Thermal Considerations
The underlying thermal limitation for the DLPC34xx controller is that the maximum operating junction
temperature (TJ) not be exceeded (this is defined in the Recommended Operating Conditions section).
Some factors that influence TJ are as follows:
•
•
•
•
•
operating ambient temperature
airflow
PCB design (including the component layout density and the amount of copper used)
power dissipation of the DLPC34xx controller
power dissipation of surrounding components
The controller package is designed to primarily extract heat through the power and ground planes of the PCB.
Thus, copper content and airflow over the PCB are important factors.
The recommends maximum operating ambient temperature (TA) is provided primarily as a design target and is
based on maximum DLPC34xx controller power dissipation and RθJA at 0 m/s of forced airflow, where RθJA is the
thermal resistance of the package as measured using a JEDEC defined standard test PCB with two, 1-oz power
planes. This JEDEC test PCB is not necessarily representative of the DLPC34xx controller PCB, so the reported
thermal resistance may not be accurate in the actual product application. Although the actual thermal resistance
may be different, it is the best information available during the design phase to estimate thermal performance. TI
highly recommended that thermal performance be measured and validated after the PCB is designed and the
application is built.
To evaluate the thermal performance, measure the top center case temperature under the worse case product
scenario (maximum power dissipation, maximum voltage, maximum ambient temperature), and validate the
controller does not exceed the maximum recommended case temperature (TC). This specification is based on
the measured φJT for the DLPC34xx controller package and provides a relatively accurate correlation to junction
temperature.
Take care when measuring this case temperature to prevent accidental cooling of the package surface. TI
recommends a small (approximately 40 gauge) thermocouple. Place the bead and thermocouple wire so that
they contact the top of the package. Cover the bead and thermocouple wire with a minimal amount of thermally
conductive epoxy. Route the wires closely along the package and the board surface to avoid cooling the bead
through the wires.
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10.2 Layout Example
Figure 10-3. Board Layout
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 Device Nomenclature
11.1.2.1 Device Markings
DLPC343x
SC
DLPC343xRXXX
XXXXXXXXXX-TT
LLLLLL.ZZZ
AA YYWW
1
2
3
4
5
Pin (terminal) A1 corner identifier
Marking Definitions:
Line 1:
DLP® Device Name: DLPC343x = x indicates a 9 device name ID.
SC: Solder ball composition
e1: Indicates lead-free solder balls consisting of SnAgCu
G8: Indicates lead-free solder balls consisting of tin-silver-copper (SnAgCu) with silver content
less than or equal to 1.5% and that the mold compound meets TI's definition of green.
Line 2:
TI Part Number
DLP® Device Name: DLPC343x = x indicates a 9 device name ID.
R corresponds to the TI device revision letter for example A, B, or C.
XXX corresponds to the device package designator.
Line 3:
XXXXXXXXXX-TT Manufacturer Part Number
Line 4:
LLLLLLLL.ZZZ Foundry lot code for semiconductor wafers and lead-free solder ball marking
LLLLLLLL: Fab lot number
ZZZ: Lot split number
Line 5:
AA YYWW: Package assembly information
AA corresponds to the manufacturing site
YYWW: Date code (YY = Year :: WW = Week)
Note
Engineering prototype samples are marked with an X suffix appended to the TI part number. For
example, 2512737-0001X.
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11.1.2.2 Video Timing Parameter Definitions
See Figure 11-1 for a visual description.
Active Lines Per Frame Defines the number of lines in a frame containing displayable data. ALPF is a
(ALPF)
subset of the TLPF.
Active Pixels Per Line Defines the number of pixel clocks in a line containing displayable data. APPL is a
(APPL)
subset of the TPPL.
Horizontal Back Porch Defines the number of blank pixel clocks after the active edge of horizontal sync but
(HBP) Blanking
before the first active pixel.
Horizontal Front Porch Defines the number of blank pixel clocks after the last active pixel but before
(HFP) Blanking
horizontal sync.
Horizontal Sync (HS or Timing reference point that defines the start of each horizontal interval (line). The
Hsync)
active edge of the HS signal defines the absolute reference point. The active edge
(either rising or falling edge as defined by the source) is the reference from which all
horizontal blanking parameters are measured.
Total Lines Per Frame Total number of active and inactive lines per frame; defines the vertical period (or
(TLPF)
frame time).
Total Pixel
(TPPL)
Vertical
Vsync)
Per
Sync
Line Total number of active and inactive pixel clocks per line; defines the horizontal line
period in pixel clocks.
(VS
or Timing reference point that defines the start of the vertical interval (frame). The
absolute reference point is defined by the active edge of the VS signal. The active
edge (either rising or falling edge as defined by the source) is the reference from
which all vertical blanking parameters are measured.
Vertical
Back
(VBP) Blanking
Porch Defines the number of blank lines after the active edge of vertical sync but before
the first active line.
Vertical Front
(VFP) Blanking
Porch Defines the number of blank lines after the last active line but before the active edge
of vertical sync.
TPPL
Vertical Back Porch (VBP)
APPL
Horizontal
Back
Porch
(HBP)
ALPF
Horizontal
Front
Porch
(HFP)
TLPF
Vertical Front Porch (VFP)
Figure 11-1. Parameter Definitions
64
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11.2 Related Documentation
The following table lists quick access links for associated parts of the DLP chipset.
Table 11-1. Chipset Documentation
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS & SOFTWARE
DLPA3000
Click here
Click here
Click here
Click here
DLPA3005
Click here
Click here
Click here
Click here
DLP4710
Click here
Click here
Click here
Click here
11.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 11-2. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
DLPC3470
Click here
Click here
Click here
Click here
Click here
11.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.5 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.6 Trademarks
IntelliBright™, Pico™, Link™ are trademarks of Texas Instruments.
TI E2E™ is a trademark of Texas Instruments.
DLP® and IntelliBright® are registered trademarks of Texas Instruments.
Arm® and Cortex® are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
All trademarks are the property of their respective owners.
11.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.8 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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DLPC3439
DLPS057E – NOVEMBER 2014 – REVISED FEBRUARY 2021
www.ti.com
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
66
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12.1 Package Option Addendum
12.1.1 Packaging Information
(1)
(2)
(3)
(4)
(5)
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins
Package
Qty
Eco Plan (2)
Lead/Ball Finish
MSL Peak Temp (3)
Op Temp (°C)
DLPC3439CZEZ
ACTIVE
NFBGA
ZEZ
201
160
Call TI
Call TI
Level-3-260C-168 HRS
–30 to 85
Device Marking(4) (5)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
space
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest
availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the
requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified
lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used
between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1%
by weight in homogeneous material)
space
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
space
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device
space
Multiple Device markings will be inside parentheses. Only on Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by
third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable
steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain
information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Copyright © 2021 Texas Instruments Incorporated
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PACKAGE OUTLINE
ZEZ0201A
NFBGA - 1 mm max height
SCALE 1.000
PLASTIC BALL GRID ARRAY
13.1
12.9
A
B
BALL A1 CORNER
13.1
12.9
1 MAX
C
SEATING PLANE
0.31
TYP
0.21
BALL TYP
0.1 C
11.2 TYP
SYMM
(0.9) TYP
R
11.2
TYP
P
N
M
L
K
J
H
G
F
E
D
C
(0.9) TYP
SYMM
201X
B
0.4
0.3
0.15
0.08
C A
C
B
A
0.8 TYP
BALL A1 CORNER
1
2
3 4 5 6 7 8 9 10 11 12 13 14 15
0.8 TYP
4221521/A 03/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
ZEZ0201A
NFBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
(0.8) TYP
201X ( 0.4)
1
2
3
4
5
6
7
8
10
9
12
11
13
14
15
A
(0.8) TYP
B
C
D
E
F
G
SYMM
H
J
K
L
M
N
P
R
SYMM
LAND PATTERN EXAMPLE
SCALE:8X
( 0.4)
METAL
0.05 MAX
METAL UNDER
SOLDER MASK
0.05 MIN
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON-SOLDER MASK
DEFINED
(PREFERRED)
( 0.4)
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NOT TO SCALE
4221521/A 03/2015
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).
www.ti.com
EXAMPLE STENCIL DESIGN
ZEZ0201A
NFBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
( 0.4) TYP
(0.8) TYP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
A
B
(0.8) TYP
C
D
E
F
G
SYMM
H
J
K
L
M
N
P
R
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.15 mm THICK STENCIL
SCALE:8X
4221521/A 03/2015
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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