DP83620
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SNLS339C – JANUARY 2011 – REVISED APRIL 2013
DP83620 Industrial Temperature Single Port 10/100 Mbps Ethernet Physical Layer
Transceiver with Fiber Support (FX)
Check for Samples: DP83620
1 Introduction
1.1
Features
12
• Deterministic, Low Transmit and Receive
Latency
• Selectable Frequency Synchronized Clock
Output
• Dynamic Link Quality Monitoring
• TDR Based Cable Diagnostic and Cable Length
Detection
• 10/100 Mb/s Packet BIST (Built in Self Test)
• Error-Free Operation up to 150 Meters CAT5
Cable
• ESD Protection - 8 kV Human Body Model
• 2.5 V and 3.3 V I/Os and MAC Interface
• Auto-MDIX for 10/100 Mbps
• Auto-Crossover in Forced Modes of Operation
1.2
•
•
•
•
•
•
•
•
•
•
•
•
RMII Rev. 1.2 and MII MAC Interface
RMII Master Mode
Synchronous Ethernet
25 MHz MDC and MDIO Serial Management
Interface
IEEE 802.3u 100BASE-FX Fiber Interface
IEEE 1149.1 JTAG
Programmable LED Support for Link, 10 /100
Mb/s Mode, Duplex, Activity, and Collision
Detect
Optional 100BASE-TX Fast Link Loss Detection
Industrial Temperature Range
48 Pin WQFN Package (7mm) x (7mm)
Applications
Factory Automation
General Embedded Applications
1.3
Description
The DP83620 is a highly reliable, feature rich device suited for industrial applications. The DP83620 offers
low power consumption, including several intelligent power down states. In addition to low power, the
DP83620 is optimized for cable length performance far exceeding IEEE specifications. The DP83620
includes a 25MHz clock out. This allows the application to be designed with a minimum of external parts,
which in turn results in the lowest possible total cost of the solution.
The DP83620 offers innovative diagnostic features unique to Texas Instruments, including dynamic
monitoring of link quality during standard operation for fault prediction. These advanced features allow the
system designer to implement a fault prediction mechanism to detect and warn of deteriorating and
changing link conditions. This single port fast Ethernet transceiver can support both copper and fiber
media. The DP838620 also provides flexibility by supporting both MII and RMII interfaces.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products conform to
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
Copyright © 2011–2013, Texas Instruments Incorporated
DP83620
SNLS339C – JANUARY 2011 – REVISED APRIL 2013
1
.............................................. 1
............................................. 1
1.2
Applications .......................................... 1
1.3
Description ........................................... 1
Device Information ...................................... 4
2.1
System Diagram ..................................... 4
2.2
Block Diagram ....................................... 4
Pin Descriptions ......................................... 5
3.1
Pin Layout ........................................... 6
3.2
PACKAGE PIN ASSIGNMENTS .................... 7
3.3
SERIAL MANAGEMENT INTERFACE .............. 8
3.4
MAC DATA INTERFACE ............................ 8
3.5
CLOCK INTERFACE ................................ 9
3.6
LED INTERFACE .................................... 9
3.7
JTAG INTERFACE ................................. 10
3.8
RESET AND POWER DOWN ...................... 10
3.9
STRAP OPTIONS .................................. 10
3.10 10 Mb/s AND 100 Mb/s PMD INTERFACE ........ 12
3.11 RESERVED PINS .................................. 12
3.12 POWER SUPPLY PINS ............................ 12
Electrical Specifications ............................. 13
4.1
Absolute Maximum Ratings ........................ 13
4.2
Recommended Operating Conditions .............. 13
4.3
AC and DC Specifications .......................... 13
4.4
DC Specifications .................................. 14
4.5
AC Specifications — Power Up Timing ............ 15
4.6
AC Specifications — Reset Timing ................. 16
3
4
Features
4.7
4.25
4.26
4.27
4.28
4.29
4.30
4.31
4.32
4.33
4.34
4.35
4.36
5
......................................................
17
4.8
AC Specifications — 100 Mb/s MII Transmit Timing
......................................................
17
4.9
4.10
AC Specifications — 100 Mb/s MII Receive Timing
AC Specifications — 100BASE-TX and 100BASEFX MII Transmit Packet Latency Timing ...........
AC Specifications — 100BASE-TX and 100BASEFX MII Transmit Packet Deassertion Timing .......
AC Specifications — 100BASE-TX Transmit Timing
(tR/F & Jitter) ........................................
AC Specifications — 100BASE-TX and 100BASEFX MII Receive Packet Latency Timing ............
AC Specifications — 100BASE-TX and 100BASEFX MII Receive Packet Deassertion Timing .......
17
4.15
AC Specifications — 10 Mb/s MII Transmit Timing
20
4.16
4.17
AC Specifications — 10 Mb/s MII Receive Timing .
AC Specifications — 10BASE-T MII Transmit
Timing (Start of Packet) ............................
AC Specifications — 10BASE-T MII Transmit
Timing (End of Packet) .............................
AC Specifications — 10BASE-T MII Receive Timing
(Start of Packet) ....................................
AC Specifications — 10BASE-T MII Receive Timing
(End of Packet) .....................................
20
...
......
22
4.12
4.13
4.14
4.18
4.19
4.20
18
18
19
6
19
20
21
21
22
22
4.21
AC Specifications — 10 Mb/s Heartbeat Timing
4.22
4.23
AC Specifications — 10 Mb/s Jabber Timing
23
AC Specifications — 10BASE-T Normal Link Pulse
Timing .............................................. 23
...........................................
.........................
5.2
AUTO-NEGOTIATION ..............................
5.3
AUTO-MDIX ........................................
5.4
AUTO-CROSSOVER IN FORCED MODE .........
5.5
PHY ADDRESS ....................................
5.6
LED INTERFACE ...................................
5.7
HALF DUPLEX vs. FULL DUPLEX ................
5.8
INTERNAL LOOPBACK ............................
5.9
POWER DOWN/INTERRUPT ......................
5.10 ENERGY DETECT MODE .........................
5.11 LINK DIAGNOSTIC CAPABILITIES ................
5.12 BIST ................................................
MAC Interface ..........................................
6.1
MII INTERFACE ....................................
6.2
REDUCED MII INTERFACE .......................
6.3
SINGLE CLOCK MII MODE ........................
6.4
7
8
9
AC Specifications — Auto-Negotiation Fast Link
Pulse (FLP) Timing .................................
AC Specifications — 100BASE-TX Signal Detect
Timing ..............................................
AC Specifications — 100 Mb/s Internal Loopback
Timing ..............................................
AC Specifications — 10 Mb/s Internal Loopback
Timing ..............................................
AC Specifications — RMII Transmit Timing (Slave
Mode) ...............................................
AC Specifications — Transmit Timing (Master
Mode) ...............................................
AC Specifications — RMII Receive Timing (Slave
Mode) ...............................................
AC Specifications — RMII Receive Timing (Master
Mode) ...............................................
AC Specifications — RX_CLK Timing (RMII Master
Mode) ...............................................
AC Specifications — CLK_OUT Timing (RMII Slave
Mode) ...............................................
AC Specifications — Single Clock MII (SCMII)
Transmit Timing ....................................
AC Specifications — Single Clock MII (SCMII)
Receive Timing .....................................
AC Specifications — 100 Mb/s X1 to TX_CLK
Timing ..............................................
Configuration
5.1
AC Specifications — MII Serial Management Timing
4.11
2
4.24
Introduction
1.1
2
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MEDIA CONFIGURATION
23
24
24
25
25
26
27
28
28
29
29
30
30
31
31
31
34
34
34
35
37
38
38
38
39
43
44
44
45
46
IEEE 802.3u MII SERIAL MANAGEMENT
INTERFACE ........................................ 47
.........................
............................
Architecture .............................................
7.1
100BASE-TX TRANSMITTER ......................
7.2
100BASE-TX RECEIVER ..........................
7.3
100BASE-FX OPERATION .........................
7.4
10BASE-T TRANSCEIVER MODULE ..............
Reset Operation ........................................
8.1
HARDWARE RESET ...............................
8.2
FULL SOFTWARE RESET .........................
8.3
SOFT RESET ......................................
Design Guidelines .....................................
6.5
PHY CONTROL FRAMES
6.6
PHY STATUS FRAMES
Contents
48
49
50
50
53
57
58
61
61
61
61
62
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10
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..........................
.......................
9.3
ESD PROTECTION ................................
9.4
CLOCK IN (X1) RECOMMENDATIONS ...........
Register Block .........................................
10.1 REGISTER DEFINITION ...........................
...............
......................
LINK DIAGNOSTICS REGISTERS - PAGE 2 ......
9.1
TPI NETWORK CIRCUIT
62
10.2
EXTENDED REGISTERS - PAGE 0
80
9.2
FIBER NETWORK CIRCUIT
63
10.3
TEST REGISTERS - PAGE 1
91
63
10.4
10.5
92
PHY STATUS FRAME CONFIGURATION
REGISTER - PAGE 5 .............................. 99
63
66
70
Revision History
...........................................
Contents
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3
DP83620
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2 Device Information
MPU/CPU
MII or RMII
RJ45
DP83620
10/100 Mb/s
PHYTER
10BASE-T
100BASE-TX
or
Fiber
Transceiver
100BASE-FX
Status
LEDs
Clock
2.2
Magnetics
System Diagram
Media Access Control
(MAC)
2.1
Block Diagram
RX_CLK
RXD[3:0]
RX_DV
RX_ER
COL
MDC
MDIO
TX_EN
TXD[3:0]
TX_CLK
SERIAL
MANAGEMENT
CRS/CRS_DV
MII/RMII
MII/RMII INTERFACE
TX_DATA
TX_CLK
RX_CLK
RX_DATA
MANAGEMENT REGISTERS
10BASE -T
&
100BASE-TX
AUTO-NEGOTIATION
REGISTERS
TRANSMIT BLOCK
10BASE -T
&
100BASE-TX
RECEIVE BLOCK
CLOCK
GENERATION
ADC
DAC
ANALOG SIGNAL
PROCESSOR
BOUNDARY
SCAN
JTAG
LED
DRIVERS
AUTO-MDIX
TD+/-
RD+/-
SYSTEM CLOCK
REFERENCE
LEDS
Figure 2-1. DP83620 Functional Block Diagarm
4
Device Information
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3 Pin Descriptions
The DP83620 pins are classified into the following interface categories (each interface is described in the
sections that follow):
• Serial Management Interface
• MAC Data Interface
• Clock Interface
• LED Interface
• JTAG Interface
• Reset and Power Down
• Strap Options
• 10/100 Mb/s PMD Interface
• Power and Ground pins
NOTE
Strapping pin option. Please see Section 3.9 for strap definitions.
All DP83620 signal pins are I/O cells regardless of the particular use. The definitions below define the
functionality of the I/O cells for each pin.
Type: I
Input
Type: O
Output
Type: I/O
Input/Output
Type: OD
Open Drain
Type: PD
Internal Pulldown
Type: PU
Internal Pullup
Type: S
Strapping Pin (All strap pins have weak internal pull-ups or pull-downs. If the default strap
value is to be changed then an external 2.2 kΩ resistor should be used. Please see
Section 3.9 for details.)
Pin Descriptions
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DP83620
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IO_VSS
RXD_0
RXD_1
RXD_2
RXD_3
COL
RX_ER
CRS/CRS_DV
RX_DV
RX_CLK
RESERVED
Pin Layout
IO_VDD
3.1
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48
47
46
45
44
43
42
41
40
39
38
37
TX_CLK
1
36
RESERVED
TX_EN
2
35
IO_CORE_VSS
TXD_0
3
34
X1
TXD_1
4
33
X2
DP83620SQ
TXD_2
5
32
IO_VDD
31
MDC
TDO
9
28
LED_LINK
TMS
10
27
LED_SPEED/FX_SD
TRST#
11
26
LED_ACT
TDI
12
25
RESERVED
13
14
15
16
17
18
19
20
21
22
23
24
CLK_OUT
RESET_N
RESERVED
29
PCF_EN
DAP = GND
CLK_OUT_EN
8
VREF
TCK
ANA33VDD
MDIO
ANAVSS
30
TD+
48-pin LLP Package
TD-
7
CD_VSS
PWRDOWN/INTN
RD+
6
RD-
TXD_3
TOP VIEW
(not to scale)
Figure 3-1. Top View
Package Number RHS0048A
6
Pin Descriptions
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3.2
SNLS339C – JANUARY 2011 – REVISED APRIL 2013
PACKAGE PIN ASSIGNMENTS
RHS0048A Pin #
(1)
Pin Name
RHS0048A Pin #
Pin Name
1
TX_CLK
26
LED_ACT
2
TX_EN
27
LED_SPEED/FX_SD
3
TXD_0
28
LED_LINK
4
TXD_1
29
RESET_N
5
TXD_2
30
MDIO
6
TXD_3
31
MDC
7
PWRDOWN/INTN
32
IO_VDD
8
TCK
33
X2
9
TDO
34
X1
10
TMS
35
IO_CORE_VSS
11
TRST#
36
RESERVED
12
TDI
37
RESERVED
13
RD-
38
RX_CLK
14
RD+
39
RX_DV
15
CD_VSS
40
CRS/CRS_DV
16
TD-
41
RX_ER
17
TD+
42
COL
18
ANAVSS
43
RXD_3
19
ANA33VDD
44
RXD_2
20
VREF
45
RXD_1
21
CLK_OUT_EN
46
RXD_0
22
PCF_EN
47
IO_VSS
23
RESERVED
48
IO_VDD
24
CLK_OUT
25
RESERVED
DAP
NC or GND (1)
Die Attach Pad (DAP) provides thermal dissipation. Connection to GND plane recommended.
Pin Descriptions
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3.3
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SERIAL MANAGEMENT INTERFACE
Signal Name
Pin Name
Type
Pin #
Description
MDC
MDC
I
31
MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO
management data input/output serial interface which may be asynchronous
to transmit and receive clocks. The maximum clock rate is 25 MHz with no
minimum clock rate.
MDIO
MDIO
I/O
30
MANAGEMENT DATA I/O: Bi-directional management instruction/data
signal that may be sourced by the station management entity or the PHY.
This pin requires a 1.5 kΩ pullup resistor. Alternately, an internal pullup may
be enabled by setting bit 3 in the CDCTRL1 register.
3.4
MAC DATA INTERFACE
Signal Name
Type
Pin #
Description
TX_CLK
TX_CLK
O
1
MII TRANSMIT CLOCK: 25 MHz Transmit clock output in 100 Mb/s mode
or 2.5 MHz in 10 Mb/s mode derived from the 25 MHz reference clock. The
MAC should source TX_EN and TXD[3:0] using this clock.
RMII MODE: Unused in RMII Slave mode. The device uses the X1
reference clock input as the 50 MHz reference for both transmit and
receive. For RMII Master mode, the device outputs the internally generated
50 MHz reference clock on this pin.
This pin provides an integrated 50 ohm signal termination, making external
termination resistors unnecessary.
TX_EN
TX_EN
I, PD
2
MII TRANSMIT ENABLE: Active high input indicates the presence of valid
data inputs on TXD[3:0].
RMII TRANSMIT ENABLE: Active high input indicates the presence of valid
data on TXD[1:0].
TXD_0
TXD_1
TXD_2
TXD_3
TXD_0
TXD_1
TXD_2
TXD_3
I
I
I
I, PD
3
4
5
6
MII TRANSMIT DATA: Transmit data MII input pins, TXD[3:0], that accept
data synchronous to the TX_CLK (2.5 MHz in 10 Mb/s mode or 25 MHz in
100 Mb/s mode).
RMII TRANSMIT DATA: Transmit data RMII input pins, TXD[1:0], that
accept data synchronous to the 50 MHz reference clock.
RX_CLK
RX_CLK
O
38
MII RECEIVE CLOCK: Provides the 25 MHz recovered receive clocks for
100 Mb/s mode and 2.5 MHz for 10 Mb/s mode.
RMII MODE: Unused in RMII Slave mode. The device uses the X1
reference clock input as the 50 MHz reference for both transmit and
receive. For RMII Master mode, the device outputs the internally generated
50 MHz reference clock on this pin.
This pin provides an integrated 50 ohm signal termination, making external
termination resistors unnecessary.
RX_DV
RX_DV
O, PD
39
MII RECEIVE DATA VALID: Asserted high to indicate that valid data is
present on the corresponding RXD[3:0].
RMII RECEIVE DATA VALID: This signal provides the RMII Receive Data
Valid indication independent of Carrier Sense.
This pin provides an integrated 50 ohm signal termination, making external
termination resistors unnecessary.
RX_ER
RX_ER
S, O, PU
41
MII RECEIVE ERROR: Asserted high synchronously to RX_CLK to indicate
that an invalid symbol has been detected within a received packet in 100
Mb/s mode.
RMII RECEIVE ERROR: Asserted high synchronously to X1 whenever a
media error is detected, and RX_DV is asserted in 100 Mb/s mode.
This pin is not required to be used by a MAC in RMII mode, since the PHY
is required to corrupt data on a receive error.
This pin provides an integrated 50 ohm signal termination, making external
termination resistors unnecessary.
RXD_0
RXD_1
RXD_2
RXD_3
RXD_0
RXD_1
RXD_2
RXD_3
S, O, PD
46
45
44
43
MII RECEIVE DATA: Nibble wide receive data signals driven synchronously
to the RX_CLK (25 MHz for 100 Mb/s mode, 2.5 MHz for 10 Mb/s mode).
RXD[3:0] signals contain valid data when RX_DV is asserted.
RMII RECEIVE DATA: 2-bits receive data signals, RXD[1:0], driven
synchronously to the 50 MHz reference clock.
These pins provide integrated 50 ohm signal terminations, making external
termination resistors unnecessary.
8
Pin Name
Pin Descriptions
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Type
Pin #
Description
CRS/CRS_DV
Signal Name
CRS/CRS_DV
S, O, PU
40
MII CARRIER SENSE: Asserted high to indicate the receive medium is
non-idle.
RMII CARRIER SENSE/RECEIVE DATA VALID: This signal combines the
RMII Carrier and Receive Data Valid indications. For a detailed description
of this signal, see the RMII Specification.
This pin provides an integrated 50 ohm signal termination, making external
termination resistors unnecessary.
COL
COL
S, O, PU
42
MII COLLISION DETECT: Asserted high to indicate detection of a collision
condition (simultaneous transmit and receive activity) in 10 Mb/s and 100
Mb/s Half Duplex Modes.
While in 10BASE-T Half Duplex mode with heartbeat enabled this pin is
also asserted for a duration of approximately 1µs at the end of transmission
to indicate heartbeat (SQE test).
In Full Duplex Mode, for 10 Mb/s or 100 Mb/s operation, this signal is
always logic 0. There is no heartbeat function during 10 Mb/s full duplex
operation.
RMII COLLISION DETECT: Per the RMII Specification, no COL signal is
required. The MAC will recover CRS from the CRS_DV signal and use that
along with its TX_EN signal to determine collision.
This pin provides an integrated 50 ohm signal termination, making external
termination resistors unnecessary.
3.5
Pin Name
CLOCK INTERFACE
Signal Name
Type
Pin #
Description
X1
X1
I
34
CRYSTAL/OSCILLATOR INPUT: This pin is the primary clock reference
input for the DP83620 and must be connected to a 25 MHz 0.005% (±50
ppm) clock source. The DP83620 supports either an external crystal
resonator connected across pins X1 and X2 or an external CMOS-level
oscillator source connected to pin X1 only.
RMII REFERENCE CLOCK: For RMII Slave Mode, this pin must be
connected to a 50 MHz 0.005% (±50 ppm) CMOS-level oscillator source. In
RMII Master Mode, a 25 MHz reference is required, either from an external
crystal resonator connected across pins X1 and X2 or from an external
CMOS-level oscillator source connected to pin X1 only.
X2
X2
O
33
CRYSTAL OUTPUT: This pin is the primary clock reference output to
connect to an external 25 MHz crystal resonator device. This pin must be
left unconnected if an external CMOS oscillator clock source is used.
CLK_OUT
CLK_OUT
O
24
CLOCK OUTPUT: This pin provides a highly configurable system clock,
which may have one of three sources:
1. 50 MHz RMII reference clock in RMII Master Mode
2. 25 MHz Receive Clock (same as RX_CLK) in 100 Mb mode
3. 25 MHz or 50 MHz pass-through of X1 reference clock
3.6
Pin Name
LED INTERFACE
The DP83620 supports three configurable LED pins. The LEDs support two operational modes which are
selected by the LED mode strap and a third operational mode which is register configurable. The
definitions for the LEDs for each mode are detailed below.
Signal Name
LED_LINK
Pin Name
LED_LINK
Type
Pin #
Description
S, O, PU
28
LINK LED: In Mode 1, this pin indicates the status of the LINK. The LED
will be ON when Link is good.
LINK/ACT LED: In Mode 2 and Mode 3, this pin indicates transmit and
receive activity in addition to the status of the Link. The LED will be ON
when Link is good. It will blink when the transmitter or receiver is active.
LED_SPEED
LED_SPEED/FX_S
D
S, O, PU
27
SPEED LED: The LED is ON when device is in 100 Mb/s and OFF when in
10 Mb/s. Functionality of this LED is independent of mode selected.
LED_ACT
LED_ACT
S, O, PU
26
ACTIVITY LED: In Mode 1, this pin is the Activity LED which is ON when
activity is present on either Transmit or Receive.
COLLISION/DUPLEX LED: In Mode 2, this pin by default indicates
Collision detection. In Mode 3, this LED output indicates Full-Duplex status.
Pin Descriptions
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3.7
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JTAG INTERFACE
Signal Name
Pin Name
Type
Pin #
Description
TCK
TCK
I, PU
8
TEST CLOCK
TDO
TDO
O
9
TEST OUTPUT
TMS
TMS
I, PU
10
TEST MODE SELECT
TRST#
TRST#
I, PU
11
This pin has a weak internal pullup.
This pin has a weak internal pullup.
TEST RESET: Active low test reset.
This pin has a weak internal pullup.
TDI
TDI
I, PU
12
TEST DATA INPUT
This pin has a weak internal pullup.
3.8
RESET AND POWER DOWN
Signal Name
Type
Pin #
Description
RESET_N
RESET_N
I, PU
29
RESET: Active Low input that initializes or re-initializes the DP83620.
Asserting this pin low for at least 1 µs will force a reset process to occur.
All internal registers will re-initialize to their default states as specified for
each bit in the Register Block section. All strap options are re-initialized as
well.
PWRDOWN/INTN
PWRDOWN/INTN
I, PU
7
The
default
function
of
this
pin
is
POWER
DOWN.
POWER DOWN: Asserting this signal low enables the DP83620 Power
Down mode of operation. In this mode, the DP83620 will power down and
consume minimum power. Register access will be available through the
Management Interface to configure and power up the device.
INTERRUPT: This pin may be programmed as an interrupt output instead
of a Powerdown input. In this mode, Interrupts will be asserted low using
this pin. Register access is required for the pin to be used as an interrupt
mechanism. See Interrupt Mechanisms for more details on the interrupt
mechanisms.
3.9
Pin Name
STRAP OPTIONS
The DP83620 uses many of the functional pins as strap options to place the device into specific modes of
operation. The values of these pins are sampled at power up or hard reset. During software resets, the
strap options are internally reloaded from the values sampled at power up or hard reset. The strap option
pin assignments are defined below. The functional pin name is indicated in parentheses.
A 2.2 kΩ resistor should be used for pull-down or pull-up to change the default strap option. If the default
option is required, then there is no need for external pull-up or pull down resistors. Since these pins may
have alternate functions after reset is deasserted, they should not be connected directly to VCC or GND.
Signal Name
PHYAD0
PHYAD1
PHYAD2
PHYAD3
PHYAD4
10
Pin Name
COL
RXD_3
RXD_2
RXD_1
RXD_0
Type
S,
S,
S,
S,
S,
O,
O,
O,
O,
O,
PU
PD
PD
PD
PD
Pin #
Description
42
43
44
45
46
PHY ADDRESS [4:0]: The DP83620 provides five PHY address pins,
the state of which are latched into the PHYCTRL register at system
Hardware-Reset.
The DP83620 supports PHY Address strapping values 0 ()
through 31 ().A PHY Address of 0 puts the part into the MII
Isolate Mode. The MII isolate mode must be selected by strapping
PHY Address 0; changing to Address 0 by register write will not put the
PHY in the MII isolate mode.
PHYAD[0] pin has weak internal pull-up resistor.
PHYAD[4:1] pins have weak internal pull-down resistors.
Pin Descriptions
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Signal Name
AN_EN
AN1
AN0
SNLS339C – JANUARY 2011 – REVISED APRIL 2013
Pin Name
LED_LINK
LED_SPEED/FX_S
D
LED_ACT
Type
Pin #
Description
S, O, PU
S, O, PU
28
27
S, O, PU
26
AUTO-NEGOTIATION ENABLE: When high, this enables AutoNegotiation with the capability set by AN0 and AN1 pins. When low, this
puts the part into Forced Mode with the capability set by AN0 and AN1
pins.
AN0 / AN1: These input pins control the forced or advertised operating
mode of the DP83620 according to the following table. The value on
these pins is set by connecting the input pins to GND (0) or VCC (1)
through 2.2 kΩ resistors. These pins should NEVER be connected
directly to GND or VCC.
The value set at this input is latched into the DP83620 at HardwareReset.
The float/pull-down status of these pins are latched into the Basic Mode
Control Register and the Auto_Negotiation Advertisement Register
during Hardware-Reset.
The default is 111 since these pins have internal pull-ups.
FIBER MODE DUPLEX SELECTION: If Fiber mode is strapped using
the FX_EN_Z pin (FX_EN_Z = 0), the AN0 strap value is used to select
half or full duplex. AN_EN and AN1 are ignored in Fiber mode since it
is 100 Mb only and does not support Auto-Negotiation. In Fiber mode,
AN1 should not be connected to any system components except the
fiber transceiver.
FX_EN_
Z
AN_EN
AN1
AN0
Forced Mode
1
0
0
0
10BASE-T, Half-Duplex
1
0
0
1
10BASE-T, Full-Duplex
1
0
1
0
100BASE-TX, Half-Duplex
1
0
1
1
100BASE-TX, Full-Duplex
0
X
X
0
100BASE-FX, Half-Duplex
100BASE-FX, Full-Duplex
0
X
X
1
FX_EN_
Z
AN_EN
AN1
AN0
1
1
0
0
10BASE-T, Half/Full-Duplex
1
1
0
1
100BASE-TX, Half/Full-Duplex
1
1
1
0
100BASE-TX, Full-Duplex
1
1
1
1
10BASE-T, Half/Full-Duplex,
100BASE-TX, Half/Full-Duplex
Advertised Mode
CLK_OUT_EN
CLK_OUT_EN
S, I, PD
21
CLK_OUT OUTPUT ENABLE: When high, enables clock output on the
CLK_OUT pin at power-up.
FX_EN_Z
RX_ER
S, O, PU
41
FX ENABLE: This strapping option enables 100Base-FX (Fiber) mode.
This mode is disabled by default. An external pull-down will enable
100Base-FX mode.
LED_CFG
CRS/CRS_DV
S, O, PU
40
LED CONFIGURATION: This strapping option determines the mode of
operation of the LED pins. Default is Mode 1. Mode 1 and Mode 2 can
be controlled via the strap option. All modes are configurable via
register access. See Table 5-3 for LED Mode Selection.
MII_MODE
RX_DV
S, O, PD
39
MII MODE SELECT: This strapping option determines the operating
mode of the MAC Data Interface. Default operation is MII Mode with a
value of 0 due to the internal pulldown. Strapping MII_MODE high will
cause the device to be in RMII mode of operation.
MII_MODE
MAC Interface Mode
0
MII Mode
1
RMII Mode
PCF_EN
PCF_EN
S, I, PD
22
PHY CONTROL FRAME ENABLE: When high, allows the DP83620 to
respond to PHY Control Frames.
RMII_MAS
TXD_3
S, I, PD
6
RMII MASTER ENABLE: When MII_MODE is strapped high, this
strapping option enables RMII Master mode, in which the DP83620
uses a 25 MHz crystal connection on X1/X2 and generates the 50 MHz
RMII reference clock. If strapped low when MII_MODE is strapped high,
default RMII operation (RMII Slave) is enabled, in which the DP83620
uses a 50 MHz oscillator input on X1 as the RMII reference clock. This
strap option is ignored if the MII_MODE strap is low.
Pin Descriptions
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3.10 10 Mb/s AND 100 Mb/s PMD INTERFACE
Signal Name
Pin Name
Type
Pin #
Description
TDTD+
TDTD+
I/O
16
17
Differential common driver transmit output (PMD Output Pair). These
differential outputs are automatically configured to either 10BASE-T or
100BASE-TX signaling.
In Auto-MDIX mode of operation, this pair can be used as the Receive Input
pair.
In 100BASE-FX mode, this pair becomes the 100BASE-FX Transmit pair.
These pins require 3.3V bias for operation.
RDRD+
RDRD+
I/O
13
14
Differential receive input (PMD Input Pair). These differential inputs are
automatically configured to accept either 100BASE-TX or 10BASE-T
signaling.
In Auto-MDIX mode of operation, this pair can be used as the Transmit
Output pair.
In 100BASE-FX mode, this pair becomes the 100BASE-FX Receive pair.
These pins require 3.3V bias for operation.
FX_SD
LED_SPEED/FX_S S, I/O, PU
D
27
FIBER MODE SIGNAL DETECT: This pin provides the Signal Detect input
for 100BASE-FX mode.
3.11 RESERVED PINS
Signal Name
RESERVED
Pin Name
RESERVED
Type
Pin #
I/O
23
25
36
37
Description
RESERVED: These pins are reserved and should not be connected to any
external logic or net for most implementations. For JTAG implementations,
these pins should be connected to GND (0) or VCC (1) through 2.2 kΩ
resistors. These pins should NEVER be connected directly to GND or
VCC.
3.12 POWER SUPPLY PINS
Signal Name
Pin Name
Type
Pin #
Ground
18
Analog Ground
ANA33VDD
Supply
19
Analog VDD Supply
CD_VSS
Ground
15
Analog Ground
IO_CORE_VSS
IO_CORE_VSS
Ground
35
Digital Ground
IO_VDD
IO_VDD
Supply
32
48
I/O VDD Supply
IO_VSS
IO_VSS
Ground
47
Digital Ground
VREF
VREF
20
Bias Resistor Connection. A 4.87 kΩ 1% resistor should be connected from
VREF to GND.
DAP
DAP
ANAVSS
ANAVSS
ANA33VDD
CD_VSS
(1)
12
Description
No Connect or Connect to GND (1)
Die Attach Pad (DAP) provides thermal dissipation. Connection to GND plane recommended.
Pin Descriptions
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4 Electrical Specifications
4.1
Absolute Maximum Ratings (1) (2) (3)
Supply Voltage (VCC)
-0.5 V to 4.2 V
DC Input Voltage (VIN)
-0.5V to VCC + 0.5V
DC Output Voltage (VOUT)
-0.5V to VCC + 0.5V
Storage Temperature (TSTG )
-65°C to 150°C
Maximum Case Temperature for TA = 85 °C
95 °C
Maximum Die Temperature (Tj)
ESD Rating
(1)
(2)
(3)
4.2
150 °C
(RZAP = 1.5k, CZAP = 120 pF)
8.0 kV
Absolute maximum ratings are those values beyond which the safety of the device cannot be ensured. They are not meant to imply that
the device should be operated at these limits.
For soldering specifications: see SNOA549.pdf.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
Recommended Operating Conditions
Analog Supply Voltage (VCC)
3.3 Volts ± 0.3V
I/O Supply Voltage (VI/O)
3.3 Volts ± 10%
or
2.5 Volts ± 5%
Industrial Temperature (TI)
-40 to 85 °C
Power Dissipation (PD) with VI/O = 3.3 V
290 mW
Power Dissipation (PD) with VI/O = 2.5 V
260 mW
4.3
AC and DC Specifications
Thermal Characteristics
Max
Units
Theta Junction to Case (Tjc)
5.0
°C / W
Theta Junction to Ambient (Tja) degrees Celsius/Watt - No Airflow @ 1.0 W
27.5
°C / W
Electrical Specifications
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DC Specifications
Symbol
Pin Types
Parameter
VIH
I
I/O
Input High Voltage
VIL
I
I/O
Input Low Voltage
IIH
I
I/O
IIL
Conditions
Min
Typ
Max
2.0
Units
V
VI/O = 3.3 V
0.8
V
VI/O = 2.5 V
0.7
V
Input High Current
VIN = VI/O
10
µA
I
I/O
Input Low Current
VIN = GND
10
µA
VOL
O
I/O
Output Low Voltage
IOL = 4 mA
0.4
V
VOH
O
I/O
Output High Voltage
IOH = -4 mA
VI/O - 0.5
IOZ
O
I/O
TRI-STATE Output Leakage Current
VOUT = VI/O
or GND
-10
VTPTD_100
PMD Output Pair 100M Transmit Voltage
VTPTDsym
PMD Output Pair 100M Transmit Voltage Symmetry
VTPTD_10
VFXTD_100
V
1
1.05
V
±2
%
PMD Output Pair 10M Transmit Voltage
2.2
2.5
2.8
V
PMD Output Pair FX 100M Transmit Voltage
0.3
0.5
0.93
V
I
CMOS Input Capacitance
8
COUT1
O
CMOS Output Capacitance
8
SDTHon
PMD Input Pair
100BASE-TX Signal detect turn-on
threshold
SDTHoff
PMD Input Pair
Signal detect turn-off threshold
200
VTH
PMD Input Pair
10BASE-T Receive Threshold
300
Idd100
Supply
100BASE-TX (Full Duplex)
Idd10
Supply
(1)
14
µA
0.95
CIN1
Idd
10
Supply
10BASE-T (Full Duplex)
Power Down Mode
pF
pF
1000
mV diff
pk-pk
mV diff
pk-pk
585
mV
VCC = 3.3 V,
VI/O = 3.3 V,
IOUT = 0 mA (1)
88
mA
VCC = 3.3 V,
VI/O = 2.5 V,
IOUT = 0 mA (1)
84
mA
VCC = 3.3 V,
VI/O = 3.3 V,
IOUT = 0 mA (1)
105
mA
VCC = 3.3 V,
VI/O = 2.5 V,
IOUT = 0 mA (1)
103
mA
10
mA
CLK_OUT
disabled
For Idd measurements, outputs are not loaded.
Electrical Specifications
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4.5
AC Specifications — Power Up Timing
Parameter
T2.1.1
T2.1.2
T2.1.3
(1)
SNLS339C – JANUARY 2011 – REVISED APRIL 2013
Notes
Min
Post Power Up Stabilization time
prior to MDC preamble for register
accesses (1)
Description
Typ
MDIO is pulled high for 32-bit serial
management initialization.
167
ms
Hardware Configuration Latch-in
Time from power up (1)
Hardware Configuration Pins are
described in the Pin Description
section.
167
ms
Hardware Configuration pins
transition to output drivers
Max
Units
50
ns
In RMII Slave Mode, the minimum Post Power up Stabilization and Hardware Configuration Latch-in times are 84 ms.
Vcc
X1 clock
T2.1.1
Hardware
RESET_N
32 CLOCKS
MDC
T2.1.2
Latch-In of Hardware
Configuration Pins
T2.1.3
Dual Function Pins
Become Enabled As Outputs
INPUT
OUTPUT
Electrical Specifications
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AC Specifications — Reset Timing
Parameter
Description
Notes
Min
Typ
Max
Units
T2.2.1
Post RESET Stabilization time prior to
MDC preamble for register accesses
MDIO is pulled high for 32-bit serial
management initialization
3
µs
T2.2.2
Hardware Configuration Latch-in Time
from the Deassertion of RESET (either
soft or hard) (1)
Hardware Configuration Pins are
described in the Pin Description
section
3
µs
50
ns
T2.2.3
Hardware Configuration pins transition
to output drivers (1)
T2.2.4
X1 Clock must be stable for at min.
of 1 µs during RESET pulse low
time.
RESET pulse width
(1)
1
µs
It is important to choose pull-up and/or pull-down resistors for each of the hardware configuration pins that provide fast RC time
constants in order to latch-in the proper value prior to the pin transitioning to an output driver.
Vcc
X1 clock
T2.2.1
T2.2.4
Hardware
RESET_N
32 CLOCKS
MDC
T2.2.2
Latch-In of Hardware
Configuration Pins
T2.2.3
Dual Function Pins
Become Enabled As Outputs
16
input
Electrical Specifications
output
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4.7
SNLS339C – JANUARY 2011 – REVISED APRIL 2013
AC Specifications — MII Serial Management Timing
Parameter
Description
Notes
Min
T2.3.1
MDC to MDIO (Output) Delay Time
0
T2.3.2
MDIO (Input) to MDC Setup Time
10
T2.3.3
MDIO (Input) to MDC Hold Time
10
T2.3.4
MDC Frequency
Typ
Max
Units
20
ns
ns
ns
2.5
25
MHz
MDC
T2.3.4
T2.3.1
MDIO (output)
MDC
T2.3.2
Valid Data
MDIO (input)
4.8
T2.3.3
AC Specifications — 100 Mb/s MII Transmit Timing
Min
Typ
Max
Units
T2.4.1
Parameter
TX_CLK High/Low Time
Description
100 Mb/s Normal mode
Notes
16
20
24
ns
T2.4.2
TXD[3:0], TX_EN Data Setup to
TX_CLK
100 Mb/s Normal mode
10
ns
T2.4.3
TXD[3:0], TX_EN Data Hold from
TX_CLK
100 Mb/s Normal mode
0
ns
T2.4.1
T2.4.1
TX_CL
K
T2.4.2
TXD[3:0
]
TX_EN
4.9
T2.4.3
Valid Data
AC Specifications — 100 Mb/s MII Receive Timing
Min
Typ
Max
Units
T2.5.1
Parameter
RX_CLK High/Low Time (1)
100 Mb/s Normal mode
16
20
24
ns
T2.5.2
RX_CLK to RXD[3:0], RX_DV, RX_ER
Delay
100 Mb/s Normal mode
10
30
ns
(1)
Description
Notes
RX_CLK may be held low or high for a longer period of time during transition between reference and recovered clocks. Minimum high
and low times will not be violated
T2.5.1
T2.5.1
RX_CLK
T2.5.2
RXD[3:0]
RX_DV
RX_ER
Valid Data
Electrical Specifications
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4.10 AC Specifications — 100BASE-TX and 100BASE-FX MII Transmit Packet Latency
Timing
Parameter
T2.6.1
(1)
(2)
Description
Notes
TX_CLK to PMD Output Pair
Latency (1) (2)
Min
100BASE-TX and 100BASE-FX modes
Typ
Max
Units
5
bits
For Normal mode, latency is determined by measuring the time from the first rising edge of TX_CLK occurring after the assertion of
TX_EN to the first bit of the “J” code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100 Mb/s mode.
Enabling PHY Control Frames will add latency equal to 8 bits times the PCF_BUF_SIZE setting. For example if PCF_BUF_SIZE is set
to 15, then the additional delay will be 15*8 = 120 bits.
TX_CLK
TX_EN
TXD[3:0]
T2.6.1
PMD Output
Pair
IDLE
(J/K)
DATA
4.11 AC Specifications — 100BASE-TX and 100BASE-FX MII Transmit Packet Deassertion
Timing
Parameter
T2.7.1
(1)
Description
Notes
TX_CLK to PMD Output Pair
Deassertion (1)
Min
100BASE-TX and 100BASE-FX modes
Typ
5
Max
Units
bits
Deassertion is determined by measuring the time from the first rising edge of TX_CLK occurring after the deassertion of TX_EN to the
first bit of the “T” code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100 Mb/s mode.
TX_CLK
TX_EN
TXD[3:0]
T2.7.1
PMD Output
Pair
18
IDLE
(J/K)
Electrical Specifications
DATA
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4.12 AC Specifications — 100BASE-TX Transmit Timing (tR/F & Jitter)
Parameter
T2.8.1
Description
100 Mb/s tR and tF Mismatch
T2.8.2
(1)
(2)
Notes
Min
Typ
Max
Units
3
4
5
ns
500
ps
1.4
ns
100 Mb/s PMD Output Pair tR and tF (1)
(2)
100 Mb/s PMD Output Pair Transmit Jitter
Rise and fall times taken at 10% and 90% of the +1 or -1 amplitude
Normal Mismatch is the difference between the maximum and minimum of all rise and fall times
T2.8.1
+1 rise
90%
10%
PMD Output Pair
10%
+1 fall
90%
T2.8.1
-1 rise
-1 fall
T2.8.1
T2.8.2
T2.8.1
PMD Output Pair
eye pattern
T2.8.2
4.13 AC Specifications — 100BASE-TX and 100BASE-FX MII Receive Packet Latency
Timing
Parameter
T2.9.1
T2.9.2
(1)
(2)
(3)
Description
Notes
Carrier Sense ON Delay (1)
Receive Data Latency (2) (3)
Min
Typ
100BASE-TX mode
20
100BASE-FX mode
10
100BASE-TX mode
24
100BASE-FX mode
14
Max
Units
bits
bits
Carrier Sense On Delay is determined by measuring the time from the first bit of the “J” code group to the assertion of Carrier Sense.
1 bit time = 10 ns in 100 Mb/s mode.
Enabling PHY Status Frames will introduce variability in Receive Data Latency due to insertion of PHY Status Frames into the receive
datapath.
PMD Input Pair
IDLE
(J/K)
Data
T2.9.1
CRS/CRS_DV
T2.9.2
RXD[3:0]
RX_DV
RX_ER
Electrical Specifications
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4.14 AC Specifications — 100BASE-TX and 100BASE-FX MII Receive Packet Deassertion
Timing
Parameter
T2.10.1
(1)
(2)
Description
Notes
Carrier Sense OFF Delay (1) (2)
Min
Typ
100BASE-TX mode
24
100BASE-FX mode
14
Max
Units
bits
Carrier Sense Off Delay is determined by measuring the time from the first bit of the “T” code group to the deassertion of Carrier Sense.
1 bit time = 10 ns in 100 Mb/s mode.
PMD Input Pair
DATA
(T/R)
IDLE
T2.10.1
CRS/CRS_DV
4.15 AC Specifications — 10 Mb/s MII Transmit Timing
Parameter
Description (1)
Min
Typ
Max
Units
T2.11.1
TX_CLK High/Low Time
10 Mb/s MII mode
190
200
210
ns
T2.11.2
TXD[3:0], TX_EN Data Setup to
TX_CLK falling edge
10 Mb/s MII mode
25
ns
T2.11.3
TXD[3:0], TX_EN Data Hold from
TX_CLK rising edge
10 Mb/s MII mode
0
ns
(1)
Notes
An attached Mac should drive the transmit signals using the positive edge of TX_CLK. As shown above, the MII signals are sampled on
the falling edge of TX_CLK.
T2.11.1
T2.11.1
TX_CLK
T2.11.2
TXD[3:0]
TX_EN
T2.11.3
Valid Data
4.16 AC Specifications — 10 Mb/s MII Receive Timing
Min
Typ
Max
Units
T2.12.1
Parameter
RX_CLK High/Low Time (1)
160
200
240
ns
T2.12.2
RXD[3:0], RX_DV transition delay from
10 Mb/s MII mode
RX_CLK rising edge
100
ns
T2.12.3
RX_CLK rising edge delay from
RXD[3:0], RX_DV valid data
100
ns
(1)
Description
Notes
10 Mb/s MII mode
RX_CLK may be held low for a longer period of time during transition between reference and recovered clocks. Minimum high and low
times will not be violated.
T2.12.1
T2.12.1
RX_CLK
T2.12.2
RXD[3:0]
RX_DV
20
T2.12.3
Valid Data
Electrical Specifications
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4.17 AC Specifications — 10BASE-T MII Transmit Timing (Start of Packet)
Parameter
T2.13.1
(1)
Description
Notes
Transmit Output Delay from the Falling
Edge of TX_CLK (1)
Min
10 Mb/s MII mode
Typ
Max
Units
3.5
bits
1 bit time = 100 ns in 10 Mb/s.
TX_CLK
TX_EN
TXD[3:0]
PMD Output
Pair
T2.13.1
4.18 AC Specifications — 10BASE-T MII Transmit Timing (End of Packet)
Min
Typ
T2.14.1
Parameter
End of Packet High Time (with '0'
ending bit)
Description
Notes
Max
Units
250
300
ns
T2.14.2
End of Packet High Time (with '1'
ending bit)
250
300
ns
TX_CLK
TX_EN
PMD Output
Pair
T2.14.1
0
0
T2.14.2
PMD Output
Pair
1
1
Electrical Specifications
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4.19 AC Specifications — 10BASE-T MII Receive Timing (Start of Packet)
Parameter
T2.15.1
Description
Min
Typ
Max
Units
630
1000
ns
(1) (2)
T2.15.2
RX_DV Latency
T2.15.3
Receive Data Latency
(1)
(2)
Notes
Carrier Sense Turn On Delay (PMD
Input Pair to CRS)
10
bits
8
bits
Measurement shown from SFD
10BASE-T RX_DV Latency is measured from first bit of preamble on the wire to the assertion of RX_DV
1 bit time = 100 ns in 10 Mb/s mode.
1st SFD bit decoded
1
0
1
0
1
0
1
0
1
0
1
1
PMD
Input Pair
T2.15.1
CRS/CRS_DV
T2.15.2
RX_DV
T2.15.3
0000
RXD[3:0]
Preamble
SFD
Data
4.20 AC Specifications — 10BASE-T MII Receive Timing (End of Packet)
Parameter
T2.16.1
Description
Notes
Min
Typ
Carrier Sense Turn Off Delay
1
0
1
Max
Units
1.0
µs
IDLE
PMD Input
Pair
RX_CLK
T2.16.1
CRS/CRS_DV
4.21 AC Specifications — 10 Mb/s Heartbeat Timing
Parameter
Description
Notes
Min
Typ
Max
Units
T2.17.1
CD Heartbeat Delay
All 10 Mb/s modes
1200
ns
T2.17.2
CD Heartbeat Duration
All 10 Mb/s modes
1000
ns
TX_EN
TX_CLK
T2.17.1
T2.17.2
COL
22
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4.22 AC Specifications — 10 Mb/s Jabber Timing
Parameter
Description
Notes
Min
Typ
Max
Units
T2.18.1
Jabber Activation Time
85
ms
T2.18.2
Jabber Deactivation Time
500
ms
TX_EN
T2.18.1
T2.18.2
PMD Output
Pair
COL
4.23 AC Specifications — 10BASE-T Normal Link Pulse Timing
Parameter
Description
Notes
Min
Typ (1)
Max
Units
T2.19.1
Pulse Width
100
ns
T2.19.2
Pulse Period
16
ms
(1)
These specifications represent transmit timings.
T2.19.2
T2.19.1
Normal Link
Pulse(s)
4.24 AC Specifications — Auto-Negotiation Fast Link Pulse (FLP) Timing
Parameter
Description
Notes
Typ (1)
Min
Max
Units
T2.20.1
Clock, Data Pulse Width
100
ns
T2.20.2
Clock Pulse to Clock Pulse Period
125
µs
T2.20.3
Clock Pulse to Data Pulse Period
62
µs
T2.20.4
Burst Width
2
ms
T2.20.5
FLP Burst to FLP Burst Period
16
ms
(1)
Data = 1
These specifications represent transmit timings.
T.2.20.2
T2.20.3
T2.20.1
T2.20.1
Fast Link
Pulse(s)
clock
pulse
data
pulse
clock
pulse
T2.20.5
T2.20.4
PMD
Output Pair
FLP Burst
FLP Burst
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4.25 AC Specifications — 100BASE-TX Signal Detect Timing
Parameter
T2.21.1
Description
Min
(1)
T2.21.2
SD Internal Turn-off Time
(1)
(2)
Notes
Typ
SD Internal Turn-on Time
Default operation
Fast link-loss indication
enabled (2)
250
1.3
Max
Units
1
ms
300
µs
µs
The signal amplitude on PMD Input Pair must be TP-PMD compliant.
Fast Link-loss detect is enabled by setting the SD_CNFG[8] register bit to a 1.
PMD Input
Pair
T2.21.1
T2.21.2
SD+ internal
4.26 AC Specifications — 100 Mb/s Internal Loopback Timing
Parameter
T2.22.1
(1)
(2)
Description
TX_EN to RX_DV Loopback (1) (2)
Notes
100 Mb/s internal loopback mode
Min
Typ
Max
Units
240
ns
Due to the nature of the descrambler function, all 100BASE-TX Loopback modes will cause an initial “dead-time” of up to 550 µs during
which time no data will be present at the receive MII outputs. The 100BASE-TX timing specified is based on device delays after the
initial 550µs “dead-time”.
Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN.
TX_CLK
TX_EN
TXD[3:0]
CRS/CRS_DV
T2.22.1
RX_CLK
RX_DV
RXD[3:0]
24
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4.27 AC Specifications — 10 Mb/s Internal Loopback Timing
Parameter
T2.23.1
(1)
Description
TX_EN to RX_DV Loopback (1)
Notes
Min
Typ
10 Mb/s internal loopback mode
Max
Units
2
µs
Measurement is made from the first falling edge of TX_CLK after assertion of TX_EN.
TX_CLK
TX_EN
TXD[3:0]
CRS/CRS_DV
T2.23.1
RX_CLK
RX_DV
RXD[3:0]
4.28 AC Specifications — RMII Transmit Timing (Slave Mode)
Parameter
Description
Notes
T2.24.1
X1 Clock Period
T2.24.2
TXD[1:0], TX_EN, Data Setup to X1 rising edge
T2.24.3
TXD[1:0], TX_EN, Data Hold from X1 rising edge
T2.24.4
X1 Clock to PMD Output Pair Latency (100 Mb) (1)
(1)
Min
50 MHz Reference Clock
Typ
Max
Units
20
4
ns
2
100BASE-TX or 100BASE-FX
ns
ns
11
bits
Latency measurement is made from the X1 rising edge to the first bit of symbol.
T2.24.1
X1
T2.24.2
TXD[1:0]
TX_EN
T2.24.3
Valid data
T2.24.4
PMD Output
Pair
Symbol
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4.29 AC Specifications — Transmit Timing (Master Mode)
Parameter
Description
Notes
Min
20
Max
Units
RX_CLK, TX_CLK, CLK_OUT Period
T2.25.2
TXD[1:0], TX_EN Data Setup to RX_CLK,
TX_CLK, CLK_OUT rising edge
4
ns
T2.25.3
TXD[1:0], TX_EN Data Hold from RX_CLK,
TX_CLK, CLK_OUT rising edge
2
ns
T2.25.4
RX_CLK, TX_CLK, CLK_OUT to PMD Output Pair From RX_CLK rising edge to
Latency (1)
first bit of symbol
(1)
50 MHz Reference Clock
Typ
T2.25.1
11
ns
bits
Latency measurement is made from the RX_CLK rising edge to the first bit of symbol.
T2.25.1
RX_CLK
TX_CLK
CLK_OUT
T2.25.2
TXD[1:0]
TX_EN
T2.25.3
Valid data
T2.25.4
PMD Output
Pair
26
Symbol
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4.30 AC Specifications — RMII Receive Timing (Slave Mode)
Parameter
Description
Notes
T2.26.1
X1 Clock Period
T2.26.2
RXD[1:0], CRS_DV, and RX_ER
output delay from X1 rising edge (1)
T2.26.3
T2.26.4
T2.26.5
(1)
(2)
(3)
(4)
(5)
(6)
Min
Typ
50 MHz Reference Clock
CRS ON delay (2) (3)
CRS OFF delay (4)
RXD[1:0] and RX_ER latency (5) (6)
Max
Units
20
2
ns
14
100BASE-TX mode
18.5
100BASE-FX mode
9
100BASE-TX mode
27
100BASE-FX mode
17
100BASE-TX mode
38
100BASE-FX mode
27
ns
bits
bits
bits
CRS_DV is asserted asynchronously in order to minimize latency of control signals through the PHY. CRS_DV may toggle
synchronously at the end of the packet to indicate CRS de-assertion.
Per the RMII Specification, output delays assume a 25 pF load.
CRS ON delay is measured from the first bit of the JK symbol on the PMD Input Pair to initial assertion of CRS_DV.
CRS OFF delay is measured from the first bit of the TR symbol on the PMD Input Pair to initial de-assertion of CRS_DV.
Receive Latency is measured from the first bit of the symbol pair on the PMD Input Pair. Typical values are with the Elasticity Buffer set
to the default value (01).
Enabling PHY Status Frames will introduce variability in Receive Data Latency due to insertion of PHY Status Frames into the receive
datapath.
PMD Input
Pair
IDLE
(J/K)
Data
(TR)
Data
T2.26.4
T2.26.5
X1
T2.26.1
T2.26.3
T2.26.2
CRS/CRS_DV
T2.26.2
RXD[1:0]
RX_ER
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4.31 AC Specifications — RMII Receive Timing (Master Mode)
Parameter
Description
Notes
T2.27.1
RX_CLK, TX_CLK, CLK_OUT
Clock Period
T2.27.2
RXD[1:0], CRS_DV, RX_DV and
RX_ER output delay from
RX_CLK, TX_CLK, CLK_OUT
rising edge (1)
T2.27.3
T2.27.4
T2.27.5
(1)
(2)
(3)
(4)
(5)
CRS ON delay (2) (3)
CRS OFF delay (4)
RXD[1:0] and RX_ER latency (5)
Min
Typ
50 MHz Reference Clock
Max
20
2
ns
14
100BASE-TX mode
18.5
100BASE-FX mode
9
100BASE-TX mode
27
100BASE-FX mode
17
100BASE-TX mode
38
100BASE-FX mode
27
Units
ns
bits
bits
bits
CRS_DV is asserted asynchronously in order to minimize latency of control signals through the PHY. CRS_DV may toggle
synchronously at the end of the packet to indicate CRS de-assertion.
Per the RMII Specification, output delays assume a 25 pF load.
CRS ON delay is measured from the first bit of the JK symbol on the PMD Input Pair to initial assertion of CRS_DV.
CRS OFF delay is measured from the first bit of the TR symbol on the PMD Input Pair to initial de-assertion of CRS_DV.
Receive Latency is measured from the first bit of the symbol pair on the PMD Input Pair. Typical values are with the Elasticity Buffer set
to the default value (01).
PMD Input
Pair
IDLE
(J/K)
Data
(TR)
Data
T2.27.4
T2.27.5
RX_CLK
TX_CLK
CLK_OUT
T2.27.1
T2.27.2
T2.27.2
T2.27.3
T2.27.2
RX_DV
CRS/CRS_DV
T2.27.2
RXD[1:0]
RX_ER
4.32 AC Specifications — RX_CLK Timing (RMII Master Mode)
Parameter
Description
Notes
Min
Typ
Max
Units
T2.28.1
RX_CLK High Time
12
ns
T2.28.2
RX_CLK Low Time
8
ns
T2.28.3
RX_CLK Period (1)
20
ns
(1)
The High Time and Low Time will add up to 20 ns.
T2.28.3
T2.28.1
T2.28.2
RX_CLK
28
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4.33 AC Specifications — CLK_OUT Timing (RMII Slave Mode)
Parameter
Description
T2.29.1
CLK_OUT High/Low Time
T2.29.2
CLK_OUT propagation delay
Notes
Min
Typ
Max
Units
10
ns
Relative to X1
8
ns
Max
Units
X1
T2.29.2
T2.29.1
T2.29.1
CLK_OUT
4.34 AC Specifications — Single Clock MII (SCMII) Transmit Timing
Parameter
Description
Notes
Min
Typ
T2.30.1
X1 Clock Period
25 MHz Reference Clock
T2.30.2
TXD[3:0], TX_EN Data Setup
To X1 rising edge
4
ns
T2.30.3
TXD[3:0], TX_EN Data Hold
From X1 rising edge
2
ns
T2.30.4
X1 Clock to PMD Output Pair
Latency (100 Mb) (1)
100BASE-TX or 100BASE-FX
(1)
40
13
ns
bits
Latency measurement is made from the X1 rising edge to the first bit of symbol.
T2.30.1
X1
T2.30.2
TXD[3:0]
TX_EN
T2.30.3
Valid data
T2.30.4
PMD Output
Pair
Symbol
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4.35 AC Specifications — Single Clock MII (SCMII) Receive Timing
Parameter
Description
Notes
Min
T2.31.1
X1 Clock Period
25 MHz Reference Clock
T2.31.2
RXD[3:0], RX_DV and RX_ER output
delay (1)
From X1 rising edge
T2.31.3
T2.31.4
T2.31.5
(1)
(2)
(3)
(4)
(5)
CRS ON delay (2) (3)
CRS OFF delay (2) (4)
RXD[3:0] and RX_ER latency (5)
Typ
Max
40
2
ns
18
100BASE-TX mode
19
100BASE-FX mode
9
100BASE-TX mode
26
100BASE-FX mode
16
100BASE-TX mode
56
100BASE-FX mode
46
Units
ns
bits
bits
bits
Output delays assume a 25 pF load.
CRS is asserted and de-asserted asynchronously relative to the reference clock.
CRS ON delay is measured from the first bit of the JK symbol on the PMD Input Pair to assertion of CRS_DV.
CRS OFF delay is measured from the first bit of the TR symbol on the PMD Input Pair to de-assertion of CRS_DV.
Receive Latency is measured from the first bit of the symbol pair on the PMD Input Pair. Typical values are with the Elasticity Buffer set
to the default value (01).
PMD Input
Pair
IDLE
(J/K)
Data
(TR)
Data
T2.31.4
T2.31.5
X1
T2.31.1
T2.31.3
CRS/CSR_DV
T2.31.2
T2.31.2
RX_DV
RXD[3:0]
RX_ER
4.36 AC Specifications — 100 Mb/s X1 to TX_CLK Timing
Parameter
T2.32.1
(1)
Description
X1 to TX_CLK delay
(1)
Notes
100 Mb/s Normal mode
Min
0
Typ
Max
Units
5
ns
X1 to TX_CLK timing is provided to support devices that use X1 instead of TX_CLK as the reference for transmit MII data.
X1
T2.32.1
TX_CLK
30
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5 Configuration
This section includes information on the various configuration options available with the DP83620. The
configuration options described below include:
— Media Configuration
— Auto-Negotiation
— PHY Address and LEDs
— Half Duplex vs. Full Duplex
— Isolate mode
— Loopback mode
— BIST
5.1
MEDIA CONFIGURATION
The DP83620 supports both Twister Pair (100BASE-TX and 10BASE-T) and Fiber (100BASE-FX) media.
The port may be configured for Twisted Pair (TP) or Fiber (FX) operation by strap option or by register
access.
At power-up/reset, the state of the RX_ER pin will select the media for the port. The default selection is
twisted pair mode, while an external pull-down will select FX mode of operation. Strapping the port into FX
mode also automatically sets the Far-End Fault Enable, bit 3 of PCSR (16h), the Scramble Bypass, bit 1
of PCSR (16h) and the Descrambler Bypass, bit 0 of PCSR (16h). In addition, the media selection may be
controlled by writing to bit 6, FX_EN, of PCSR (16h).
5.2
AUTO-NEGOTIATION
The Auto-Negotiation function provides a mechanism for exchanging configuration information between
two ends of a link segment and automatically selecting the highest performance mode of operation
supported by both devices. Fast Link Pulse (FLP) Bursts provide the signalling used to communicate
Auto-Negotiation abilities between two devices at each end of a link segment. For further detail regarding
Auto-Negotiation, refer to Clause 28 of the IEEE 802.3u specification. The DP83620 supports four
different Ethernet protocols (10 Mb/s Half Duplex, 10 Mb/s Full Duplex, 100 Mb/s Half Duplex, and 100
Mb/s Full Duplex), so the inclusion of Auto-Negotiation ensures that the highest performance protocol will
be selected based on the advertised ability of the Link Partner. The Auto-Negotiation function within the
DP83620 can be controlled either by internal register access or by the use of the AN_EN, AN1 and AN0
pins.
5.2.1
Auto-Negotiation Pin Control
The state of AN_EN, AN0 and AN1 determines whether the DP83620 is forced into a specific mode or
Auto-Negotiation will advertise a specific ability (or set of abilities) as given in Table 5-1. These pins allow
configuration options to be selected without requiring internal register access.
The state of AN_EN, AN0 and AN1, upon power-up/reset, determines the state of bits [8:5] of the ANAR
register.
The Auto-Negotiation function selected at power-up or reset can be changed at any time by writing to the
Basic Mode Control Register (BMCR) at address 00h.
Configuration
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Table 5-1. Auto-Negotiation Modes
5.2.2
AN_EN
AN1
AN0
0
0
0
10BASE-T, Half-Duplex
Forced Mode
0
0
1
10BASE-T, Full-Duplex
0
1
0
100BASE-TX, Half-Duplex
100BASE-TX, Full-Duplex
0
1
1
AN_EN
AN1
AN0
1
0
0
10BASE-T, Half/Full-Duplex
1
0
1
100BASE-TX, Half/Full-Duplex
1
1
0
100BASE-TX Full-Duplex
1
1
1
Advertised Mode
10BASE-T, Half/Full-Duplex
100BASE-TX, Half/Full-Duplex
Auto-Negotiation Register Control
When Auto-Negotiation is enabled, the DP83620 transmits the abilities programmed into the AutoNegotiation Advertisement register (ANAR) at address 04h via FLP Bursts. Any combination of 10 Mb/s,
100 Mb/s, Half-Duplex, and Full Duplex modes may be selected.
Auto-Negotiation Priority Resolution:
1. 100BASE-TX Full Duplex (Highest Priority)
2. 100BASE-TX Half Duplex
3. 10BASE-T Full Duplex
4. 10BASE-T Half Duplex (Lowest Priority)
The Basic Mode Control Register (BMCR) at address 00h provides control for enabling, disabling, and
restarting the Auto-Negotiation process. When Auto-Negotiation is disabled, the SPEED SELECTION bit
in the BMCR controls switching between 10 Mb/s or 100 Mb/s operation, and the DUPLEX MODE bit
controls switching between full duplex operation and half duplex operation. The SPEED SELECTION and
DUPLEX MODE bits have no effect on the mode of operation when the Auto-Negotiation Enable bit is set.
The Link Speed can be examined through the PHY Status Register (PHYSTS) at address 10h after a Link
is achieved.
The Basic Mode Status Register (BMSR) indicates the set of available abilities for technology types, AutoNegotiation ability, and Extended Register Capability. These bits are permanently set to indicate the full
functionality of the DP83620 (only the 100BASE-T4 bit is not set since the DP83620 does not support that
function).
The BMSR also provides status on:
• Whether or not Auto-Negotiation is complete
• Whether or not the Link Partner is advertising that a remote fault has occurred
• Whether or not valid link has been established
• Support for Management Frame Preamble suppression
The Auto-Negotiation Advertisement Register (ANAR) indicates the Auto-Negotiation abilities to be
advertised by the DP83620. All available abilities are transmitted by default, but any ability can be
suppressed by writing to the ANAR. Updating the ANAR to suppress an ability is one way for a
management agent to change (restrict) the technology that is used.
The Auto-Negotiation Link Partner Ability Register (ANLPAR) at address 05h is used to receive the base
link code word as well as all next page code words during the negotiation. Furthermore, the ANLPAR will
be updated to either 0081h or 0021h for parallel detection to either 100 Mb/s or 10 Mb/s respectively.
32
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The Auto-Negotiation Expansion Register (ANER) indicates additional Auto-Negotiation status. The ANER
provides status on:
• Whether or not a Parallel Detect Fault has occurred
• Whether or not the Link Partner supports the Next Page function
• Whether or not the DP83620 supports the Next Page function
• Whether or not the current page being exchanged by Auto-Negotiation has been received
• Whether or not the Link Partner supports Auto-Negotiation
5.2.3
Auto-Negotiation Parallel Detection
The DP83620 supports the Parallel Detection function as defined in the IEEE 802.3u specification. Parallel
Detection requires both the 10 Mb/s and 100 Mb/s receivers to monitor the receive signal and report link
status to the Auto-Negotiation function. Auto-Negotiation uses this information to configure the correct
technology in the event that the Link Partner does not support Auto-Negotiation but is transmitting link
signals that the 100BASE-TX or 10BASE-T PMAs recognize as valid link signals.
If the DP83620 completes Auto-Negotiation as a result of Parallel Detection, bits 5 and 7 within the
ANLPAR register will be set to reflect the mode of operation present in the Link Partner. Note that bits 4:0
of the ANLPAR will also be set to 00001 based on a successful parallel detection to indicate a valid 802.3
selector field. Software may determine that negotiation completed via Parallel Detection by reading a zero
in the Link Partner Auto-Negotiation Able bit once the Auto-Negotiation Complete bit is set. If configured
for parallel detect mode and any condition other than a single good link occurs then the parallel detect
fault bit will be set.
5.2.4
Auto-Negotiation Restart
Once Auto-Negotiation has completed, it may be restarted at any time by setting bit 9 (Restart AutoNegotiation) of the BMCR to one. If the mode configured by a successful Auto-Negotiation loses a valid
link, then the Auto-Negotiation process will resume and attempt to determine the configuration for the link.
This function ensures that a valid configuration is maintained if the cable becomes disconnected.
A renegotiation request from any entity, such as a management agent, will cause the DP83620 to halt any
transmit data and link pulse activity until the break_link_timer expires (~1500 ms). Consequently, the Link
Partner will go into link fail and normal Auto-Negotiation resumes. The DP83620 will resume AutoNegotiation after the break_link_timer has expired by issuing FLP (Fast Link Pulse) bursts.
5.2.5
Enabling Auto-Negotiation via Software
It is important to note that if the DP83620 has been initialized upon power-up as a non-auto-negotiating
device (forced technology), and it is then required that Auto-Negotiation or re-Auto-Negotiation be initiated
via software, bit 12 (Auto-Negotiation Enable) of the Basic Mode Control Register (BMCR) must first be
cleared and then set for any Auto-Negotiation function to take effect.
5.2.6
Auto-Negotiation Complete Time
Parallel detection and Auto-Negotiation take approximately 2-3 seconds to complete. In addition, AutoNegotiation with next page should take approximately 2-3 seconds to complete, depending on the number
of next pages sent.
Refer to Clause 28 of the IEEE 802.3u standard for a full description of the individual timers related to
Auto-Negotiation.
Configuration
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5.3
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AUTO-MDIX
When enabled, this function utilizes Auto-Negotiation to determine the proper configuration for
transmission and reception of data and subsequently selects the appropriate MDI pair for MDI/MDIX
operation. The function uses a random seed to control switching of the crossover circuitry. This
implementation complies with the corresponding IEEE 802.3 Auto-Negotiation and Crossover
Specifications.
Auto-MDIX is enabled by default and can be configured via PHYCR (19h) register, bits [15:14].
Neither Auto-Negotiation nor Auto-MDIX is required to be enabled in forcing crossover of the MDI pairs.
Forced crossover can be achieved through the FORCE_MDIX bit, bit 14 of PHYCR (19h) register.
5.4
AUTO-CROSSOVER IN FORCED MODE
When enabled, this function operates in a manner similar to Auto-MDIX. If no link activity is seen,
switching of the crossover circuitry is based on a random seed. Valid link activity can be link pulses (AutoNegotiation link pulse or 10M link pulses) or 100M signaling. Once valid link activity is seen, crossover will
stop to allow the receive and link functions will proceed normally.
Auto-crossover in forced mode allows for shorter link times because it does not require potentially lengthy
Auto-Negotiation transactions prior to link establishment. Link establishment via Auto-crossover can be
accomplished in full or half duplex configuration, but both sides of the link must be forced to the same
duplex configuration.
Auto-crossover in forced mode is disabled by default and must be configured via PCSR (16h) register, bit
15.
Forced crossover can be achieved while Auto-crossover is enabled through the FORCE_MDIX bit, bit 14
of PHYCR (19h) register.
NOTE: Auto-MDIX and Auto-crossover in forced mode are mutually exclusive and should not be enabled
concurrently. Prior to enabling Auto-crossover in forced mode, Auto-Negotiation and Auto-MDIX should be
disabled.
5.5
PHY ADDRESS
The five PHY address strapping pins are shared with the RXD[3:0] pins and COL pin as shown below.
Table 5-2. PHY Address Mapping
Pin #
PHYAD Function
RXD Function
42
PHYAD0
COL
43
PHYAD1
RXD_3
44
PHYAD2
RXD_2
45
PHYAD3
RXD_1
46
PHYAD4
RXD_0
The DP83620 can be set to respond to any of 32 possible PHY addresses via strap pins. The information
is latched into the PHYCR register (address 19h, bits [4:0]) at device power-up and hardware reset. Each
DP83620 or port sharing an MDIO bus in a system must have a unique physical address.
The DP83620 supports PHY Address strapping values 0 () through 31 (). Strapping
PHY Address 0 puts the part into Isolate Mode. It should also be noted that selecting PHY Address 0
via an MDIO write to PHYCR will not put the device in Isolate Mode. See MII Isolate Mode for more
information.
For further detail relating to the latch-in timing requirements of the PHY Address pins, as well as the other
hardware configuration pins, refer to the Reset summary in Reset Operation.
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Since the PHYAD[0] pin has weak internal pull-up resistor and PHYAD[4:1] pins have weak internal pulldown resistors, the default setting for the PHY address is 00001 (01h).
PHYAD4 = 0
PHYAD3 = 0
PHYAD2 = 0
COL
RXD_3
RXD_2
RXD_0
RXD_1
Refer to Figure 5-1 for an example of a PHYAD connection to external components. In this example, the
PHYAD strapping results in address 00011 (03h).
PHYAD1 = 1
PHYAD0 = 1
2.2 k:
VCC
Figure 5-1. PHYAD Strapping Example
5.5.1
MII Isolate Mode
It is recommended that the user have a basic understanding of Clause 22 of the 802.3u standard.
The DP83620 can be put into MII Isolate Mode by writing a 1 to bit 10 of the BMCR register. Strapping the
PHY Address to 0 will force the device into Isolate Mode when powered up. It should be noted that
selecting Physical Address 0 via an MDIO write to PHYCR will not put the device in the MII isolate mode.
When in the MII Isolate Mode, the DP83620 does not respond to packet data present at TXD[3:0] and
TX_EN inputs and presents a high impedance on the TX_CLK, RX_CLK, RX_DV, RX_ER, RXD[3:0],
COL, and CRS/CRS_DV outputs. When in Isolate Mode, the DP83620 will continue to respond to all serial
management transactions over the MII.
While in Isolate Mode, the PMD output pair will not transmit packet data but will continue to source
100BASE-TX scrambled idles or 10BASE-T normal link pulses.
The DP83620 can Auto-Negotiate or parallel detect to a specific technology depending on the receive
signal at the PMD input pair. A valid link can be established for the receiver even when the DP83620 is in
Isolate Mode.
5.5.2
Broadcast Mode
The DP83620 is also capable of accepting broadcast messages (register writes to PHY address 0x1F).
Setting the BC_WRITE to 1, bit 11 of the PHY Control Register 2 (PHYCR2) at address 0x1C, will
configure the device to accept broadcast messages independent of the local PHY Address value.
5.6
LED INTERFACE
The DP83620 supports three configurable
LED_SPEED/FX_SD, and LED_ACT.
Light
Emitting
Diode
(LED)
pins:
LED_LINK,
Several functions can be multiplexed onto the three LEDs using three different modes of operation. The
LED operation mode can be selected by writing to the LED_CFG[1:0] register bits in the PHY Control
Register (PHYCR) at address 19h, bits [6:5]. LED_CFG[1] is only controllable through register access and
cannot be set by a strap pin.
See Table 5-3 for LED Mode selection.
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Table 5-3. LED Mode Selection
Mode
1
LED_CFG[1]
don't care
2
0
3
1
LED_CFG[0]
1
0
0
LED_LINK
LED_SPEED
LED_ACT
ON for Good Link
ON in 100 Mb/s
ON for Activity
OFF for No Link
OFF in 10 Mb/s
OFF for No Activity
ON for Good Link
ON in 100 Mb/s
ON for Collision
BLINK for Activity
OFF in 10 Mb/s
OFF for No Collision
ON for Good Link
ON in 100 Mb/s
ON for Full Duplex
BLINK for Activity
OFF in 10 Mb/s
OFF for Half Duplex
The LED_LINK pin in Mode 1 indicates the link status of the port. In 100BASE-TX mode, link is
established as a result of input receive amplitude compliant with the TP-PMD specifications which will
result in internal generation of signal detect. A 10 Mb/s Link is established as a result of the reception of at
least seven consecutive normal Link Pulses or the reception of a valid 10BASE-T packet. This will cause
the assertion of LED_LINK. LED_LINK will deassert in accordance with the Link Loss Timer as specified
in the IEEE 802.3 specification. In 100BASE-TX mode, an optional fast link loss detection may be enabled
by setting the SD_TIME control in the SD_CNFG register. Enabling fast link loss detection will result in the
LED_LINK deassertion within approximately 1.3 µs of loss of signal on the wire.
The LED_LINK pin in Mode 1 will be OFF when no LINK is present.
The LED_LINK pin in Mode 2 and Mode 3 will be ON to indicate Link is good and BLINK to indicate
activity is present on activity. The BLINK frequency is defined in BLINK_FREQ, bits [7:6] of register
LEDCR (18h).
Activity is defined as configured in LEDACT_RX, bit 8 of register LEDCR (18h). If LEDACT_RX is 0,
Activity is signaled for either transmit or receive. If LEDACT_RX is 1, Activity is only signaled for receive.
The LED_SPEED/FX_SD pin indicates 10 or 100 Mb/s data rate of the port. The standard CMOS driver
goes high when operating in 100 Mb/s operation. The functionality of this LED is independent of mode
selected.
The LED_ACT pin in Mode 1 indicates the presence of either transmit or receive activity. The LED will be
ON for Activity and OFF for No Activity. In Mode 2, this pin indicates the Collision status of the port. The
LED will be ON for Collision and OFF for No Collision.
The LED_ACT pin in Mode 3 indicates Duplex status for 10 Mb/s or 100 Mb/s operation. The LED will be
ON for Full Duplex and OFF for Half Duplex.
In 10 Mb/s half duplex mode, the collision LED is based on the COL signal.
Since these LED pins are also used as strap options, the polarity of the LED is dependent on whether the
pin is pulled up or down.
5.6.1
LEDs
Since the Auto-Negotiation (AN) strap options share the LED output pins, the external components
required for strapping and LED usage must be considered in order to avoid contention.
Specifically, when the LED outputs are used to drive LEDs directly, the active state of each output driver is
dependent on the logic level sampled by the corresponding AN input upon power-up/reset. For example, if
a given AN input is resistively pulled low then the corresponding output will be configured as an active
high driver. Conversely, if a given AN input is resistively pulled high, then the corresponding output will be
configured as an active low driver.
Refer to Figure 5-2 for an example of AN connections to external components. In this example, the AN
strapping results in Auto-Negotiation disabled with 100 Full-Duplex forced.
The adaptive nature of the LED outputs helps to simplify potential implementation issues of these dual
purpose pins.
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LED_LINK
LED_SPEED
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AN1 = 1
AN0 = 1
165:
165:
165:
VCC
2.2 k:
AN_EN = 0
GND
Figure 5-2. AN Strapping and LED Loading Example
5.6.2
LED Direct Control
The DP83620 provides another option to directly control any or all LED outputs through the LED Direct
Control Register (LEDCR), address 18h. The register does not provide read access to LEDs.
5.7
HALF DUPLEX vs. FULL DUPLEX
The DP83620 supports both half and full duplex operation at both 10 Mb/s and 100 Mb/s speeds.
Half-duplex relies on the CSMA/CD protocol to handle collisions and network access. In Half-Duplex
mode, Carrier Sense (CRS) responds to both transmit and receive activity in order to maintain compliance
with the IEEE 802.3 specification.
Since the DP83620 is designed to support simultaneous transmit and receive activity it is capable of
supporting full-duplex switched applications with a throughput of up to 200 Mb/s when operating in either
100BASE-TX or 100BASE-FX. Because the CSMA/CD protocol does not apply to full-duplex operation,
the DP83620 disables its own internal collision sensing and reporting functions and modifies the behavior
of CRS such that it indicates only receive activity. This allows a full-duplex capable MAC to operate
properly.
All modes of operation (100BASE-TX, 100BASE-FX, 10BASE-T) can run either half-duplex or full-duplex.
Additionally, other than CRS and collision reporting, all remaining MII signaling remains the same
regardless of the selected duplex mode.
It is important to understand that while Auto-Negotiation with the use of Fast Link Pulse code words can
interpret and configure to full-duplex operation, parallel detection can not recognize the difference between
full and half-duplex from a fixed 10 Mb/s or 100 Mb/s link partner over twisted pair. As specified in the
802.3u specification, if a far-end link partner is configured to a forced full-duplex 100BASE-TX ability, the
parallel detection state machine in the partner would be unable to detect the full-duplex capability of the
far-end link partner. This link segment would negotiate to a half-duplex 100BASE-TX configuration (same
scenario for 10 Mb/s).
Auto-Negotiation is not supported in 100BASE-FX operation. Selection of Half or Full-duplex operation is
controlled by bit 8 of the Basic Mode Control Register (BMCR), address 00h. If 100BASE-FX mode is
strapped using the RX_ER pin, the AN0 strap value is used to set the value of bit 8 of the BMCR (00h)
register. Note that the other Auto-Negotiation strap pins (AN_EN and AN1) are ignored in 100BASE-FX
mode.
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INTERNAL LOOPBACK
The DP83620 includes a Loopback Test mode for facilitating system diagnostics. The Loopback mode is
selected through bit 14 (Loopback) of the Basic Mode Control Register (BMCR). Writing 1 to this bit
enables MII transmit data to be routed to the MII receive outputs. Loopback status may be checked in bit 3
of the PHY Status Register (PHYSTS). While in Loopback mode the data will not be transmitted onto the
media. To ensure that the desired operating mode is maintained, Auto-Negotiation should be disabled
before selecting the Loopback mode.
5.9
POWER DOWN/INTERRUPT
The Power Down and Interrupt functions are multiplexed on pin 7 of the device. By default, this pin
functions as a power down input and the interrupt function is disabled. Setting bit 0 (INT_OE) of MICR
(11h) will configure the pin as an active low interrupt output.
5.9.1
Power Down Control Mode
The PWRDOWN/INTN pin can be asserted low to put the device in a Power Down mode. This is
equivalent to setting bit 11 (POWER DOWN) in the Basic Mode Control Register, BMCR (00h). An
external control signal can be used to drive the pin low, overcoming the weak internal pull-up resistor.
Alternatively, the device can be configured to initialize into a Power Down state by use of an external pulldown resistor on the PWRDOWN/INTN pin. Since the device will still respond to management register
accesses, setting the INT_OE bit in the MICR register will disable the PWRDOWN/INTN input, allowing
the device to exit the Power Down state.
5.9.2
Interrupt Mechanisms
The interrupt function is controlled via register access. All interrupt sources are disabled by default. Setting
bit 1 (INTEN) of MICR (11h) will enable interrupts to be output, dependent on the interrupt mask set in the
lower byte of the MISR (12h). The PWRDOWN/INTN pin is asynchronously asserted low when an
interrupt condition occurs. The source of the interrupt can be determined by reading the upper byte of the
MISR. One or more bits in the MISR will be set, denoting all currently pending interrupts. Reading of the
MISR clears ALL pending interrupts.
Example: To generate an interrupt on a change of link status or on a change of energy detect power state,
the steps would be:
• Write 0003h to MICR to set INTEN and INT_OE
• Write 0060h to MISR to set ED_INT_EN and LINK_INT_EN
• Monitor PWRDOWN/INTN pin
When PWRDOWN/INTN pin asserts low, the user would read the MISR register to see if the ED_INT or
LINK_INT bits are set, i.e. which source caused the interrupt. After reading the MISR, the interrupt bits
should clear and the PWRDOWN/INTN pin will de-assert.
5.10 ENERGY DETECT MODE
When Energy Detect is enabled and there is no activity on the cable, the DP83620 will remain in a low
power mode while monitoring the transmission line. Activity on the line will cause the DP83620 to go
through a normal power up sequence. Regardless of cable activity, the DP83620 will occasionally wake
up the transmitter to put ED pulses on the line, but will otherwise draw as little power as possible. Energy
detect functionality is controlled via register Energy Detect Control (EDCR), address 1Dh.
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5.11 LINK DIAGNOSTIC CAPABILITIES
The DP83620 contains several system diagnostic capabilities for evaluating link quality and detecting
potential cabling faults in twisted pair cabling. Software configuration is available through the Link
Diagnostics Registers - Page 2 which can be selected via Page Select Register (PAGESEL), address 13h.
These capabilities include:
— Linked Cable Status
— Link Quality Monitor
— TDR (Time Domain Reflectometry) Cable Diagnostics
5.11.1 Linked Cable Status
In an active connection with a valid link status, the following diagnostic capabilities are available:
— Polarity reversal
— Cable swap (MDI vs MDIX) detection
— 100 Mb Cable Length Estimation
— Frequency offset relative to link partner
— Cable Signal Quality Estimation
5.11.1.1 Polarity Reversal
The DP83620 detects polarity reversal by detecting negative link pulses. The Polarity indication is
available in bit 12 of the PHYSTS (10h) or bit 4 of the 10BTSCR (1Ah). Inverted polarity indicates the
positive and negative conductors in the receive pair are swapped. Since polarity is corrected by the
receiver, this does not necessarily indicate a functional problem in the cable.
Since the polarity indication is dependent on link pulses from the link partner, polarity indication is only
valid in 10 Mb modes of operation, or in 100 Mb Auto-Negotiated mode. Polarity indication is not available
in 100 Mb forced mode of operation or in a parallel detected 100 Mb mode.
5.11.1.2 Cable Swap Indication
As part of Auto-Negotiation, the DP83620 has the ability (using Auto-MDIX) to automatically detect a cable
with swapped MDI pairs and select the appropriate pairs for transmitting and receiving data. Normal
operation is termed MDI, while crossed operation is MDIX. The MDIX status can be read from bit 14 of the
PHYSTS (10h).
5.11.1.3 100 Mb Cable Length Estimation
The DP83620 provides a method of estimating cable length based on electrical characteristics of the 100
Mb link. This essentially provides an effective cable length rather than a measurement of the physical
cable length. The cable length estimation is only available in 100 Mb mode of operation with a valid link
status. The cable length estimation is available at the Link Diagnostics Registers - Page 2, register 100
Mb Length Detect (LEN100_DET), address 14h.
5.11.1.4 Frequency Offset Relative to Link Partner
As part of the 100 Mb clock recovery process, the DSP implementation provides a frequency control
parameter. This value may be used to indicate the frequency offset of the device relative to the link
partner. This operation is only available in 100 Mb operation with a valid link status. The frequency offset
can be determined using the register 100 Mb Frequency Offset Indication (FREQ100), address 15h, of the
Link Diagnostics Registers - Page 2.
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Two different versions of the Frequency Offset may be monitored through bits [7:0] of register FREQ100
(15h). The first is the long-term Frequency Offset. The second is the current Frequency Control value,
which includes short-term phase adjustments and can provide information on the amount of jitter in the
system.
5.11.1.5 Cable Signal Quality Estimation
The cable signal quality estimator keeps a simple tracking of results of the DSP and can be used to
generate an approximate Signal-to-Noise Ratio for the 100 Mb receiver. This information is available to
software through the Link Diagnostics Registers - Page 2: Variance Control Register (VAR_CTRL),
address 1Ah and Variance Data Register (VAR_DATA), address 1Bh.
The variance computation times (VAR_TIMER) can be chosen from the set of {2, 4, 6, 8} ms. The 32-bit
variance sum can be read by two consecutive reads of the VAR_DATA register. This sum can be used to
compute an SNR estimate by software using the following equation:
SNR = 10log10((37748736 * VAR_TIMER) / Variance)
5.11.2 Link Quality Monitor
The Link Quality Monitor allows a method to generate an alarm when the DSP adaption strays from a
programmable window. This could occur due to changes in the cable which could indicate a potential
problem. Software can program thresholds for the following DSP parameters to be used to interrupt the
system:
— Digital Equalizer C1 Coefficient (DEQ C1)
— Digital Adaptive Gain Control (DAGC)
— Digital Base-Line Wander Control (DBLW)
— Recovered Clock Long-Term Frequency Offset (FREQ)
— Recovered Clock Frequency Control (FC)
— Signal-to-Noise Ratio (SNR) Variance
Software is expected to read initial adapted values and then program the thresholds based on an
expected valid range. This mechanism takes advantage of the fact that the DSP adaptation should remain
in a relatively small range once a valid link has been established.
5.11.2.1 Link Quality Monitor Control and Status
Control of the Link Quality Monitor is done through the Link Quality Monitor Register (LQMR), address
1Dh and the Link Quality Data Register (LQDR), address 1Bh of the Link Diagnostics Registers - Page 2.
The LQMR register includes a global enable to enable the Link Quality Monitor function. In addition, it
provides warning status from both high and low thresholds for each of the monitored parameters except
SNR Variance.. The LQMR2 register provides warning status for the high threshold of SNR Variance
(upper 16 bits); there is no low threshold. Note that individual low or high parameter threshold
comparisons can be disabled by setting to the minimum or maximum values.
To allow the Link Quality Monitor to interrupt the system, the Interrupt must be enabled through the
interrupt control registers, MICR (11h) and MISR (12h).
The Link Quality Monitor may also be used to automatically reset the DSP and restart adaption. Separate
enable bits in LQMR and LQMR2 allow for automatic reset based on each of the parameter values. If
enabled, a violation of one of the thresholds will result in a restart of the DSP adaption. In addition if the
PCSR:SD_OPTION register bit is set to 0, the violation will also result in a drop in Link Status.
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5.11.2.2 Checking Current Parameter Values
Prior to setting Threshold values, it is recommended that software check current adapted values. The
thresholds may then be set relative to the adapted values. The current adapted values can be read using
the LQDR register by setting the SAMPLE_PARAM bit [13] of LQDR, address (1Eh).
For example, to read the DBLW current value:
1. Write 2400h to LQDR (1Eh) to set the SAMPLE_PARAM bit and set the LQ_PARAM_SEL[2:0] to 010.
2. Read LQDR (1Eh). Current DBLW value is returned in the low 8 bits.
5.11.2.3 Threshold Control
The LQDR (1Eh) register also provides a method of programming high and low thresholds for each of the
five parameters that can be monitored. The register implements an indirect read/write mechanism.
Writes are accomplished by writing data, address, and a write strobe to the register. Reads are
accomplished by writing the address to the register, and reading back the value of the selected threshold.
Setting thresholds to the maximum or minimum values will disable the threshold comparison since values
have to exceed the threshold to generate a warning condition.
Warnings are not generated if the parameter is equal to the threshold. By default, all thresholds are
disabled by setting to the minimum or maximum values. Table 5-4 shows the five parameters and range of
values:
Table 5-4. Link Quality Monitor Parameter Ranges
Parameter
Minimum Value
Maximum Value
Min (2-s comp)
-128
+127
0x80
0x7F
DAGC
0
+255
0x00
0xFF
DBLW
-128
+127
0x80
0x7F
Frequency Offset
-128
+127
0x80
0x7F
Frequency Control
-128
+127
0x80
0x7F
0
+2304
0x0000
0x900
DEQ_C1
SNR Variance
Max (2-s comp)
Note that values are signed 2-s complement values except for DAGC and Variance which are always
positive. The maximum SNR Variance is calculated by assuming the worst-case squared error (144) is
accumulated every 8 ns for 8*220 ns (roughly 8 ms or exactly 1,048,576 clock cycles).
For example, to set the DBLW Low threshold to -38:
1. Write 14DAh to LQDR to set the Write_LQ_Thr bit, select the DBLW Low Threshold, and write data of
-38 (0xDA).
2. Write 8000 to LQMR to enable the Link Quality Monitor (if not already enabled).
5.11.3 TDR Cable Diagnostics
The DP83620 implements a Time Domain Reflectometry (TDR) method of cable length measurement and
evaluation which can be used to evaluate a connected twisted pair cable. The TDR implementation
involves sending a pulse out on either the Transmit or Receive conductor pair and observing the results
on either pair. By observing the types and strength of reflections on each pair, software can determine the
following:
— Cable short
— Cable open
— Distance to fault
— Identify which pair has a fault
— Pair skew
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The TDR cable diagnostics works best in certain conditions. For example, an unterminated cable provides
a good reflection for measuring cable length, while a cable with an ideal termination to an unpowered
partner may provide no reflection at all.
5.11.4 TDR Pulse Generator
The TDR implementation can send two types of TDR pulses. The first option is to send 50 ns or 100 ns
link pulses from the 10 Mb Common Driver. The second option is to send pulses from the 100 Mb
Common Driver in 8 ns increments up to 56 ns in width. The 100 Mb pulses will alternate between positive
and negative pulses. The shorter pulses provide better ability to measure short cable lengths, especially
since they will limit overlap between the transmitted pulse and a reflected pulse. The longer pulses may
provide better measurements of long cable lengths.
In addition, if the pulse width is programmed to 0, no pulse will be sent, but the monitor circuit will still be
activated. This allows sampling of background data to provide a baseline for analysis.
5.11.5 TDR Pulse Monitor
The TDR function monitors data from the Analog to Digital Converter (ADC) to detect both peak values
and values above a programmable threshold. It can be programmed to detect maximum or minimum
values. In addition, it records the time, in 8 ns intervals, at which the peak or threshold value first occurs.
The TDR monitor implements a timer that starts when the pulse is transmitted. A window may be enabled
to qualify incoming data to look for response only in a desired range. This is especially useful for
eliminating the transmitted pulse, but also may be used to look for multiple reflections.
5.11.6 TDR Control Interface
The TDR Control Interface is implemented in the Link Diagnostics Registers - Page 2 through TDR
Control (TDR_CTRL), address 16h and TDR Window (TDR_WIN), address 17h. The following basic
controls are:
• TDR Enable: Enable bit 15 of TDR_CTRL (16h) to allow the TDR function. This bypasses normal
operation and gives control of the CD10 and CD100 block to the TDR function.
• TDR Send Pulse: Enable bit 11 of TDR_CTRL (16h) to send the TDR pulse and starts the TDR
Monitor
The following transmit mode controls are available:
• Transmit Mode: Enables use of 10 Mb Link pulses from the 10 Mb Common Driver or data pulses
from the 100 Mb Common Driver by enabling TDR_100 Mb, bit 14 of TDR_CRTL (16h).
• Transmit Pulse Width: Bits [10:8] of TDR_CTRL (16h) allows sending of 0 to 7 clock width pulses.
Actual pulses are dependent on the transmit mode. If the pulse width is set to 0, then no pulse will be
sent.
• Transmit Channel Select: The transmitter can send pulses down either the transmit pair or the
receive pair by enabling bit 13 of TDR_CTRL (16h). Default value is to select the transmit pair.
The following receive mode controls are available:
• Min/Max Mode Control: Bit 7 of TDR_CTRL (16h) controls the TDR Monitor operation. In default
mode, the monitor will detect maximum (positive) values. In Min Mode, the monitor will detect minimum
(negative) values.
• Receive Channel Select: The receiver can monitor either the transmit pair or the receive pair by
enabling bit 12 of TDR_CTRL (16h). Default value is to select the transmit pair.
• Receive Window: The receiver can monitor receive data within a programmable window using the
TDR Window Register (TDR_WIN), address 17h. The window is controlled by two register values: TDR
Start Window, bits [15:8] of TDR_WIN (17h) and TDR Stop Window, bits [7:0] of TDR_WIN (17h). The
TDR Start Window indicates the first clock to start sampling. The TDR Stop Window indicates the last
clock to sample. By default, the full window is enabled, with Start set to 0 and Stop set to 255. The
window range is in 8 ns clock increments, so the maximum window size is 2048 ns.
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5.11.7 TDR Results
The results of a TDR peak and threshold measurement are available in the TDR Peak Measurement
Register (TDR_PEAK), address 18h and TDR Threshold Measurement Register (TDR_THR), address
19h. The threshold measurement may be a more accurate method of measuring the length of longer
cables since it provides a better indication of the start of the received pulse, rather than the peak value.
Software utilizing the TDR function should implement an algorithm to send TDR pulses and evaluate
results. Multiple runs should be used to best qualify any received pulses as multiple reflections could exist.
In addition, when monitoring the transmitting pair, the window feature should be used to disqualify the
transmitted pulse. Multiple runs may also be used to average the values providing more accurate results.
Actual distance measurements are dependent on the velocity of propagation of the cable. The delay value
is typically on the order of 4.6 to 4.9 ns/m.
5.12 BIST
The DP83620 incorporates an internal Built-in Self Test (BIST) circuit to accommodate in-circuit testing or
diagnostics. The BIST circuit can be utilized to test the integrity of the transmit and receive data paths.
BIST testing can be performed with the part in the internal loopback mode or externally looped back using
a loopback cable fixture. BIST testing can also be performed between two directly connected DP83620
devices.
The BIST is implemented with independent transmit and receive paths, with the transmit block generating
a continuous stream of a pseudo random sequence. The user can select a 9 bit or 15 bit pseudo random
sequence from the PSR_15 bit in the PHY Control Register (PHYCR). The received data is compared to
the generated pseudo-random data by the BIST Linear Feedback Shift Register (LFSR) to determine the
BIST pass/fail status.
The pass/fail status of the BIST is stored in the BIST status bit in the PHYCR register. The status bit
defaults to 0 (BIST fail) and will transition on a successful comparison. If an error (mis-compare) occurs,
the status bit is latched and is cleared upon a subsequent write to the Start/Stop bit.
For transmit VOD testing, the Packet BIST Continuous Mode can be used to allow continuous data
transmission by setting the BIST_CONT_MODE, bit 5, of CDCTRL1 (1Bh).
The number of BIST errors can be monitored through the BIST Error Count in the CDCTRL1 (1Bh), bits
[15:8].
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6 MAC Interface
The DP83620 supports several modes of operation using the MII interface pins. The options are defined in
the following sections and include:
— MII Mode
— RMII Mode
— Single Clock MII Mode (SCMII)
In addition, the DP83620 supports the standard 802.3u MII Serial Management Interface.
The modes of operation can be selected by strap options or register control. For RMII Slave mode, it is
recommended to use the strap option since it requires a 50 MHz clock instead of the normal 25 MHz.
In each of these modes, the IEEE 802.3 serial management interface is operational for device
configuration and status. The serial management interface of the MII allows for the configuration and
control of multiple PHY devices, gathering of status, error information, and the determination of the type
and capabilities of the attached PHY(s).
6.1
MII INTERFACE
The DP83620 incorporates the Media Independent Interface (MII) as specified in Clause 22 of the IEEE
802.3u standard. This interface may be used to connect PHY devices to a MAC in 10/100 Mb/s systems.
This section describes the nibble wide MII data interface.
The nibble wide MII data interface consists of a receive bus and a transmit bus each with control signals
to facilitate data transfer between the PHY and the upper layer (MAC).
6.1.1
Nibble-wide MII Data Interface
Clause 22 of the IEEE 802.3u specification defines the Media Independent Interface. This interface
includes a dedicated receive bus and a dedicated transmit bus. These two data buses, along with various
control and status signals, allow for the simultaneous exchange of data between the DP83620 and the
upper layer agent (MAC).
The receive interface consists of a nibble wide data bus RXD[3:0], a receive error signal RX_ER, a receive
data valid flag RX_DV, and a receive clock RX_CLK for synchronous transfer of the data. The receive
clock operates at either 2.5 MHz to support 10 Mb/s operation modes or at 25 MHz to support 100 Mb/s
operational modes.
The transmit interface consists of a nibble wide data bus TXD[3:0], a transmit enable control signal
TX_EN, and a transmit clock TX_CLK which runs at either 2.5 MHz or 25 MHz.
Additionally, the MII includes the carrier sense signal CRS, as well as a collision detect signal COL. The
CRS signal asserts to indicate the reception of data from the network or as a function of transmit data in
Half Duplex mode. The COL signal asserts as an indication of a collision which can occur during halfduplex operation when both a transmit and receive operation occur simultaneously.
6.1.2
Collision Detect
For Half Duplex, a 10BASE-T or 100BASE-TX collision is detected when the receive and transmit
channels are active simultaneously. Collisions are reported by the COL signal on the MII.
If the DP83620 is transmitting in 10 Mb/s mode when a collision is detected, the collision is not reported
until seven bits have been received while in the collision state. This prevents a collision being reported
incorrectly due to noise on the network. The COL signal remains set for the duration of the collision.
If a collision occurs during a receive operation, it is immediately reported by the COL signal.
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When heartbeat is enabled (only applicable to 10 Mb/s operation), approximately 1µs after the
transmission of each packet, a Signal Quality Error (SQE) signal of approximately 10 bit times is
generated (internally) to indicate successful transmission. SQE is reported as a pulse on the COL signal of
the MII.
Collision is not indicated during Full Duplex operation.
6.1.3
Carrier Sense
In 10 Mb/s operation, Carrier Sense (CRS) is asserted due to receive activity once valid data is detected
via the Smart Squelch function. During 100 Mb/s operation CRS is asserted when a valid link (SD) and
two non-contiguous zeros are detected on the line.
For 10 or 100 Mb/s Half Duplex operation, CRS is asserted during either packet transmission or reception.
For 10 or 100 Mb/s Full Duplex operation, CRS is asserted only due to receive activity.
CRS is deasserted following an end of packet.
6.2
REDUCED MII INTERFACE
The DP83620 incorporates the Reduced Media Independent Interface (RMII) as specified in the RMII
specification (rev 1.2) from the RMII Consortium. This interface may be used to connect PHY devices to a
MAC in 10/100 Mb/s systems using a reduced number of pins. In this mode, data is transferred 2-bits at a
time using the 50 MHz RMII_REF clock for both transmit and receive. The following pins are used in RMII
mode:
— TX_EN
— TXD[1:0]
— RX_ER (optional for MAC)
— CRS/CRS_DV
— RXD[1:0]
— X1 (25 MHz in RMII Master mode, 50 MHz in RMII Slave mode)
— RX_CLK, TX_CLK, CLK_OUT (50 MHz RMII reference clock in RMII Master mode only)
In addition, the RMII mode supplies an RX_DV signal which allows for a simpler method of recovering
receive data without having to separate RX_DV from the CRS_DV indication. This is especially useful for
systems which do not require CRS, such as systems that only support full-duplex operation. This signal is
also useful for diagnostic testing where it may be desirable to loop external Receive RMII data directly to
the transmitter.
The RX_ER output may be used by the MAC to detect error conditions. It is asserted for symbol errors
received during a packet, False Carrier events, and also for FIFO underrun or overrun conditions. Since
the PHY is required to corrupt receive data on an error, a MAC is not required to use RX_ER.
Since the reference clock operates at 10 times the data rate for 10 Mb/s operation, transmit data is
sampled every 10 clocks. Likewise, receive data will be generated every 10th clock so that an attached
device can sample the data every 10 clocks.
RMII Slave mode requires a 50 MHz oscillator to be connected to the device X1 pin. A 50 MHz crystal is
not supported. RMII Master mode can use either a 25 MHz oscillator connected to X1 or a 25 MHz crystal
connected to X1 and X2.
To tolerate potential frequency differences between the 50 MHz reference clock and the recovered receive
clock, the receive RMII function includes a programmable elasticity buffer. The elasticity buffer is
programmable to minimize propagation delay based on expected packet size and clock accuracy. This
allows for supporting a range of packet sizes including jumbo frames.
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The elasticity buffer will force Frame Check Sequence errors for packets which overrun or underrun the
FIFO. Underrun and overrun conditions can be reported in the RMII and Bypass Register (RBR). Table 61 indicates how to program the elasticity buffer FIFO (in 4-bit increments) based on expected maximum
packet size and clock accuracy. It assumes both clocks (RMII Reference clock and far-end Transmitter
clock) have the same accuracy.
Packet lengths can be scaled linearly based on accuracy (+/- 25 ppm would allow packets twice as large).
If the threshold setting must support both 10 Mb and 100 Mb operation, the setting should be made to
support both speeds.
Table 6-1. Supported Packet Sizes at +/-50 ppm Frequency Accuracy
Start Threshold RBR[1:0]
6.2.1
Latency Tolerance
Recommended Packet Size at +/- 50 ppm
100 Mb
10 Mb
100 Mb
10 Mb
01 (default)
2 bits
8 bits
2,400 bytes
9,600 bytes
10
6 bits
4 bits
7,200 bytes
4,800 bytes
11
10 bits
8 bits
12,000 bytes
9,600 bytes
00
14 bits
12 bits
16,800 bytes
14,400 bytes
RMII Master Mode
In RMII Master Mode, the DP83620 uses a 25 MHz crystal on X1/X2 and internally generates the 50 MHz
RMII reference clock for use by the RMII logic. The 50 MHz clock is output on RX_CLK, TX_CLK, and
CLK_OUT for use as the reference clock for an attached MAC. RX_CLK operates at 25 MHz during reset.
6.2.2
RMII Slave Mode
In RMII Slave Mode, the DP83620 takes a 50 MHz reference clock input on X1 from an external oscillator
or another DP83620 in RMII Master Mode. The 50 MHz is internally divided down to 25 MHz for use as
the reference clock for non-RMII logic. RX_CLK, TX_CLK, and CLK_OUT should not be used as the RMII
reference clock in this mode but may be used for other system devices.
6.3
SINGLE CLOCK MII MODE
Single Clock MII (SCMII) Mode allows MII operation using a single 25 MHz reference clock. Normal MII
Mode requires three clocks, a reference clock for physical layer functions, a transmit MII clock, and a
receive MII clock. Similar to RMII mode, Single Clock MII mode requires only the reference clock. In
addition to reducing the number of pins required, this mode allows the attached MAC device to use only
the reference clock domain. AC Timing requirements for SCMII operation are similar to the RMII timing
requirements.
For 10 Mb operation, as in RMII mode, data is sampled and driven every 10 clocks since the reference
clock is at 10 times the data rate.
Separate control bits allow enabling the Transmit and Receive Single Clock modes separately, allowing
just transmit or receive to operate in this mode. Control of Single Clock MII mode is through the RBR
register.
Single Clock MII mode incorporates the use of the RMII elasticity buffer, which is required to tolerate
potential frequency differences between the 25 MHz reference clock and the recovered receive clock.
Settings for the elasticity buffer for SCMII mode are detailed in Table 6-2.
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Table 6-2. Supported SCMII Packet Sizes at +/-50 ppm Frequency Accuracy
Start Threshold RBR[1:0]
6.4
6.4.1
Latency Tolerance
Recommended Packet Size at +/- 50 ppm
100 Mb
10 Mb
100 Mb
10 Mb
01 (default)
4 bits
8 bits
4,000 bytes
9,600 bytes
10
4 bits
8 bits
4,000 bytes
9,600 bytes
11
8 bits
8 bits
9,600 bytes
9,600 bytes
00
8 bits
8 bits
9,600 bytes
9,600 bytes
IEEE 802.3u MII SERIAL MANAGEMENT INTERFACE
Serial Management Register Access
The serial management MII specification defines a set of thirty-two 16-bit status and control registers that
are accessible through the management interface pins MDC and MDIO. The DP83620 implements all the
required MII registers as well as several optional registers. These registers are fully described in Register
Block. A description of the serial management access protocol follows.
6.4.2
Serial Management Access Protocol
The serial control interface consists of two pins, Management Data Clock (MDC) and Management Data
Input/Output (MDIO). MDC has a maximum clock rate of 25 MHz and no minimum rate. The MDIO line is
bi-directional and may be shared by up to 32 devices. The MDIO frame format is shown below in Table 63.
Table 6-3. Typical MDIO Frame Format
MII Management Serial Protocol
Read Operation
Write Operation
The MDIO pin requires a pull-up resistor (1.5 kΩ) which, during IDLE and turnaround, will pull MDIO high.
The DP83620 also includes an option to enable an internal pull-up on the MDIO pin, MDIO_PULL_EN bit
in the CDCTRL1 register. In order to initialize the MDIO interface, the station management entity sends a
sequence of 32 contiguous logic ones on MDIO to provide the DP83620 with a sequence that can be used
to establish synchronization. This preamble may be generated either by driving MDIO high for 32
consecutive MDC clock cycles, or by simply allowing the MDIO pull-up resistor to pull the MDIO pin high
during which time 32 MDC clock cycles are provided. In addition 32 MDC clock cycles should be used to
re-sync the device if an invalid Start, Opcode, or turnaround bit is detected.
The DP83620 waits until it has received this preamble sequence before responding to any other
transaction. Once the DP83620 serial management port has been initialized no further preamble
sequencing is required until after a power-on/reset, invalid Start, invalid Opcode, or invalid turnaround (TA)
bit has occurred.
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The Start code is indicated by a pattern. This assures the MDIO line transitions from the default idle
line state.
Turnaround is defined as an idle bit time inserted between the Register Address field and the Data field.
To avoid contention during a read transaction, no device shall actively drive the MDIO signal during the
first bit of Turnaround. The addressed DP83620 drives the MDIO with a zero for the second bit of
turnaround and follows this with the required data. Figure 6-1 shows the timing relationship between MDC
and the MDIO as driven/received by the Station (STA) and the DP83620 (PHY) for a typical register read
access.
For write transactions, the station management entity writes data to the addressed DP83620 thus
eliminating the requirement for MDIO Turnaround. The Turnaround time is filled by the management entity
by inserting . Figure 7-1 shows the timing relationship for a typical MII register write access.
MDC
z
MDIO
(STA)
z
z
z
MDIO
(PHY)
z
0
Idle
1
1
0
0
1
1
0
0
0
Start Opcode PHY Address
(Read) (PHY AD = 0Ch)
0
0
0
0 z 0
Register Address
(00h = BCMR)
0
0
1
1
0
0
TA
0
1
0
0
0
0
0
0
0
z
0
Register Data
Idle
Figure 6-1. Typical MDC/MDIO Read Operation
MDC
MDIO
(STA)
z
z
z
Idle
0
1
0
1
0
1
1
0
0
Start Opcode
PHY Address
(Write) (PHY AD = 0Ch)
0
0
0
0
0
Register Address
(00h = BCMR)
1
0
0
0
0
0
0
TA
0
0
0
0
0
Register Data
0
0
0
0
0
0
z
Idle
Figure 6-2. Typical MDC/MDIO Write Operation
6.4.3
Serial Management Preamble Suppression
The DP83620 supports a Preamble Suppression mode as indicated by a one in bit 6 of the Basic Mode
Status Register (BMSR, address 01h.) If the station management entity (i.e. MAC or other management
controller) determines that all PHYs in the system support Preamble Suppression by returning a one in
this bit, then the station management entity need not generate preamble for each management
transaction.
The DP83620 requires a single initialization sequence of 32 bits of preamble following hardware/software
reset. This requirement is generally met by the mandatory pull-up resistor on MDIO in conjunction with a
continuous MDC, or the management access made to determine whether Preamble Suppression is
supported.
While the DP83620 requires an initial preamble sequence of 32 bits for management initialization, it does
not require a full 32-bit sequence between each subsequent transaction. A minimum of one idle bit
between management transactions is required as specified in the IEEE 802.3u specification.
6.5
PHY CONTROL FRAMES
The DP83620 supports a packet-based control mechanism for use in situations where the Serial
Management Interface is not available or does not provide enough throughput. Application software may
build a packet, called a PHY Control Frame (PCF), to be passed to the PHY through the MAC Transmit
Data interface. The PHY will intercept these packets and use them to assert writes to Management
Registers as if they occurred via the Management Interface. Multiple register writes may be incorporated
in a single frame.
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The PHY Control Frame may also be used to read a register location. The read value will be returned in a
PHY Status Frame if that function is enabled. Only a single read may be outstanding at any time, so only
one read should be included in a single PHY Control Frame.
The PHY Control Frame block performs the following functions:
• Parse incoming transmit packets to detect PHY Control Frames
• Truncate PHY Control Frames to prevent complete frame from reaching the transmit physical medium
• Buffer up to 15 bytes of the Frame to be intercepted by the PHY with no portion reaching physical
medium
• Detect commands in the PHY Control Frame and pass them to the register block
• Check CRC to detect error conditions
• Report CRC and invalid command errors to the system via register status and/or interrupt
PHY Control Frames can be enabled through the PCF_Enable bit in the PHY Control Frames
Configuration Register (PCFCR). PHY Control Frames can also be enabled by using the PCF_EN strap
option.
6.6
PHY STATUS FRAMES
The DP83620 implements a packet-based status mechanism that allows the PHY to generate status
messages indicating packet buffering errors and to return data read using the PHY Control Frame register
access mechanism.
Each PHY Status Frame may include multiple status messages. The PHY will provide buffering of any
incoming packet to allow the status packet to be passed to the MAC. Programmable inter-frame gap and
preamble length allow the PHY to recover lost bandwidth in the case of heavy receive traffic.
In a PHY Status Frame, status messages are not provided in a chronological order. Instead, they are
provided in the following order of priority:
1. PHY Control Frame Read Data
2. Packet Buffer Error
The packet format may be configured to look like a Layer 2 Ethernet frame or a UDP/IPv4 frame.
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7 Architecture
This section describes the operations within each transceiver module, 100BASE-TX and 10BASE-T. Each
operation consists of several functional blocks and is described in the following:
— 100BASE-TX Transmitter
— 100BASE-TX Receiver
— 100BASE-FX Operation
— 10BASE-T Transceiver Module
7.1
100BASE-TX TRANSMITTER
The 100BASE-TX transmitter consists of several functional blocks which convert synchronous 4-bit nibble
data, as provided by the MII, to a scrambled MLT-3 125 Mb/s serial data stream. Because the 100BASETX TP-PMD is integrated, the differential output pins, PMD Output Pair, can be directly routed to the
magnetics.
The block diagram in Figure 7-1 provides an overview of each functional block within the 100BASE-TX
transmit section.
The Transmitter section consists of the following functional blocks:
— Code-Group Encoder and Injection block
— Scrambler block (bypass option)
— NRZ to NRZI Encoder block
— Binary to MLT-3 Converter / Common Driver block
The bypass option for the functional blocks within the 100BASE-TX transmitter provides flexibility for
applications where data conversion is not always required. The DP83620 implements the 100BASE-TX
transmit state machine diagram as specified in the IEEE 802.3u Standard, Clause 24.
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TX_CLK
DIVIDE
BY 5
TXD[3:0]/
TX_EN
4B5B CODEGROUP
ENCODER and
INJECTOR
5B PARALLEL
TO SERIAL
125 MHz CLOCK
SCRAMBLER
MUX
BP_SCR
100BASE-TX
LOOPBACK
MLT[1:0]
NRZ TO NRZI
ENCODER
BINARY
TO MLT-3/
COMMON
DRIVER
PMD OUTPUT PAIR
Figure 7-1. 100BASE-TX Transmit Block Diagram
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Table 7-1. 4B5B Code-Group Encoding/Decoding
Name
PCS 5B Code-Group
MII 4B Nibble Code
0
11110
0000
1
01001
0001
2
10100
0010
3
10101
0011
4
01010
0100
5
01011
0101
6
01110
0110
7
01111
0111
8
10010
1000
9
10011
1001
A
10110
1010
B
10111
1011
C
11010
1100
D
11011
1101
E
11100
1110
F
11101
1111
DATA CODES
IDLE AND CONTROL CODES
H
00100
HALT code-group - Error code
I
11111
Inter-Packet IDLE - 0000 (1)
J
11000
First Start of Packet - 0101 (1)
K
10001
Second Start of Packet - 0101 (1)
T
01101
First End of Packet - 0000 (1)
R
00111
Second End of Packet - 0000 (1)
INVALID CODES
(1)
52
V
00000
V
00001
V
00010
V
00011
V
00101
V
00110
V
01000
V
01100
V
10000
V
11001
Control code-groups I, J, K, T and R in data fields will be mapped as invalid codes, together with RX_ER asserted.
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7.1.1
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Code-Group Encoding and Injection
The code-group encoder converts 4-bit (4B) nibble data generated by the MAC into 5-bit (5B) code-groups
for transmission. This conversion is required to allow control data to be combined with packet data codegroups. Refer to Table 7-1 for 4B to 5B code-group mapping details.
The code-group encoder substitutes the first 8-bits of the MAC preamble with a J/K code-group pair
(11000 10001) upon transmission. The code-group encoder continues to replace subsequent 4B preamble
and data nibbles with corresponding 5B code-groups. At the end of the transmit packet, upon the
deassertion of Transmit Enable signal from the MAC, the code-group encoder injects the T/R code-group
pair (01101 00111) indicating the end of the frame.
After the T/R code-group pair, the code-group encoder continuously injects IDLEs into the transmit data
stream until the next transmit packet is detected (reassertion of Transmit Enable).
7.1.2
Scrambler
The scrambler is required to control the radiated emissions at the media connector and on the twisted pair
cable (for 100BASE-TX applications). By scrambling the data, the total energy launched onto the cable is
randomly distributed over a wide frequency range. Without the scrambler, energy levels at the PMD and
on the cable could peak beyond FCC limitations at frequencies related to repeating 5B sequences (i.e.,
continuous transmission of IDLEs).
The scrambler is configured as a closed loop linear feedback shift register (LFSR) with an 11-bit
polynomial. The output of the closed loop LFSR is X-ORd with the serial NRZ data from the code-group
encoder. The result is a scrambled data stream with sufficient randomization to decrease radiated
emissions at certain frequencies by as much as 20 dB. The DP83620 uses the PHY_ID (pins PHYAD
[4:0]) to set a unique seed value.
7.1.3
NRZ to NRZI Encoder
After the transmit data stream has been serialized and scrambled, the data must be NRZI encoded in
order to comply with the TP-PMD standard for 100BASE-TX transmission over Category-5 Unshielded
twisted pair cable. There is no ability to bypass this block within the DP83620. The NRZI data is sent to
the 100 Mb Driver. In addition, this module creates an encoded MLT value for use in 100 Mb Internal
Loopback.
7.1.4
Binary to MLT-3 Convertor
The Binary to MLT-3 conversion is accomplished by converting the serial binary data stream output from
the NRZI encoder into two binary data streams with alternately phased logic one events. These two binary
streams are then fed to the twisted pair output driver which converts the voltage to current and alternately
drives either side of the transmit transformer primary winding, resulting in a minimal current MLT-3 signal.
The 100BASE-TX MLT-3 signal sourced by the PMD Output Pair common driver is slew rate controlled.
This should be considered when selecting AC coupling magnetics to ensure TP-PMD Standard compliant
transition times (3 ns < Tr < 5 ns).
The 100BASE-TX transmit TP-PMD function within the DP83620 is capable of sourcing only MLT-3
encoded data. Binary output from the PMD Output Pair is not possible in 100 Mb/s mode.
7.2
100BASE-TX RECEIVER
The 100BASE-TX receiver consists of several functional blocks which convert the scrambled MLT-3 125
Mb/s serial data stream to synchronous 4-bit nibble data that is provided to the MII. Because the
100BASE-TX TP-PMD is integrated, the differential input pins, RD±, can be directly routed from the AC
coupling magnetics.
See Figure 7-2 for a block diagram of the 100BASE-TX receive function. This provides an overview of
each functional block within the 100BASE-TX receive section.
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The Receive section consists of the following functional blocks:
— Analog Front End
— Input and BLW Compensation
— Signal Detect
— Digital Adaptive Equalization
— MLT-3 to Binary Decoder
— Clock Recovery Module
— NRZI to NRZ Decoder
— Serial to Parallel
— Descrambler (bypass option)
— Code Group Alignment
— 4B/5B Decoder
— Link Integrity Monitor
— Bad SSD Detection
7.2.1
Analog Front End
In addition to the Digital Equalization and Gain Control, the DP83620 includes Analog Equalization and
Gain Control in the Analog Front End. The Analog Equalization reduces the amount of Digital Equalization
required in the DSP.
7.2.2
Digital Signal Processor
The Digital Signal Processor includes Base Line Wander Compensation and Adaptive Equalization with
Gain Control.
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RD +/-
AFE
ANALOG ANALOG
AGC EQUALIZER
FCO
ADC Data
INPUT BLW
COMPENSATION
ANALOG
ADAPTATION
CONTROL
AUTOMATIC GAIN
CONTROL
CLOCK
RECOVERY
(LOOPFILTER)
DIGITAL
ADAPTIVE
EQUALIZATION
MLT-3 TO BINARY
DECODER
CLOCK
RECOVERY
MODULE
SIGNAL DETECT
NRZI TO NRZ
DECODER
CLOCK
DESCRAMBLER
LINK INTEGRITY
MONITOR
MUX
BP_SCR
CODE GROUP
ALIGNMENT
RX_DATA VALID
SSD DETECT
SERIAL TO
PARALLEL
DIVIDE BY 5
4B/5B DECODER
RX_DV/CRS
RX_CLK
RXD[3:0] / RX_ER
Figure 7-2. 100BASE-TX Receive Block Diagram
7.2.2.1
Base Line Wander Compensation
The DP83620 is completely ANSI TP-PMD compliant and includes Base Line Wander (BLW)
compensation. The BLW compensation block can successfully recover the TP-PMD defined “killer”
pattern.
7.2.2.2
Digital Adaptive Equalization and Gain Control
The DP83620 utilizes an extremely robust equalization scheme referred as ‘Digital Adaptive Equalization.’
The Digital Equalizer removes ISI (inter symbol interference) from the receive data stream by continuously
adapting to provide a filter with the inverse frequency response of the channel. Equalization is combined
with an adaptive gain control stage. This enables the receive 'eye pattern' to be opened sufficiently to
allow very reliable data recovery.
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7.2.3
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Signal Detect
The signal detect function of the DP83620 is incorporated to meet the specifications mandated by the
ANSI FDDI TP-PMD Standard as well as the IEEE 802.3 100BASE-TX Standard for both voltage
thresholds and timing parameters.
Note that the reception of normal 10BASE-T link pulses and fast link pulses per IEEE 802.3u AutoNegotiation by the 100BASE-TX receiver do not cause the DP83620 to assert signal detect.
7.2.4
MLT-3 to Binary Decoder
The DP83620 decodes the MLT-3 information from the Digital Adaptive Equalizer block to binary NRZI
data.
7.2.5
Clock Recovery Module
The Clock Recovery function is implemented as a Phase detector and Loop Filter which accepts data and
error from the receive datapath to detect the phase of the recovered data. This phase information is fed
into the loop filter to determine an 8-bit signed frequency control. The 8-bit signed frequency control is
sent to the FCO in the Analog Front End to derive the receive clock. The extracted and synchronized
clock and data are used as required by the synchronous receive operations as generally depicted in
Figure 7-2.
7.2.6
NRZI to NRZ Decoder
In a typical application, the NRZI to NRZ decoder is required in order to present NRZ formatted data to the
descrambler (or to the code-group alignment block if the descrambler is bypassed).
7.2.7
Serial to Parallel
The 100BASE-TX receiver includes a Serial to Parallel converter which supplies 5-bit wide data symbols
to the PCS Rx state machine.
7.2.8
Descrambler
A serial descrambler is used to de-scramble the received NRZ data. The descrambler has to generate an
identical data scrambling sequence (N) in order to recover the original unscrambled data (UD) from the
scrambled data (SD) as represented in the equations:
Synchronization of the descrambler to the original scrambling sequence (N) is achieved based on the
knowledge that the incoming scrambled data stream consists of scrambled IDLE data. After the
descrambler has recognized 12 consecutive IDLE code-groups, where an unscrambled IDLE code-group
in 5B NRZ is equal to five consecutive ones (11111), it will synchronize to the receive data stream and
generate unscrambled data in the form of unaligned 5B code-groups.
In order to maintain synchronization, the descrambler must continuously monitor the validity of the
unscrambled data that it generates. To ensure this, a line state monitor and a hold timer are used to
constantly monitor the synchronization status. Upon synchronization of the descrambler, the hold timer
starts a 722 µs countdown. Upon detection of sufficient IDLE code-groups (58 bit times) within the 722 µs
period, the hold timer will reset and begin a new countdown. This monitoring operation will continue
indefinitely given a properly operating network connection with good signal integrity. If the line state
monitor does not recognize sufficient unscrambled IDLE code-groups within the 722 µs period, the entire
descrambler will be forced out of the current state of synchronization and reset in order to re-acquire
synchronization. The DP83604T also provides a bit (DESC_TIME, bit 7) in the PCSR register (0x16) that
increases the descrambler timeout from 722 µs to 2 ms to allow reception of packets up to 9kB in size
without losing descrambler lock.
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Code-Group Alignment
The code-group alignment module operates on unaligned 5-bit data from the descrambler (or, if the
descrambler is bypassed, directly from the NRZI/NRZ decoder) and converts it into 5B code-group data (5
bits). Code-group alignment occurs after the J/K code-group pair is detected. Once the J/K code-group
pair (11000 10001) is detected, subsequent data is aligned on a fixed boundary.
7.2.10 4B/5B Decoder
The code-group decoder functions as a look up table that translates incoming 5B code-groups into 4B
nibbles. The code-group decoder first detects the J/K code-group pair preceded by IDLE code-groups and
replaces the J/K with MAC preamble. Specifically, the J/K 10-bit code-group pair is replaced by the nibble
pair (0101 0101). All subsequent 5B code-groups are converted to the corresponding 4B nibbles for the
duration of the entire packet. This conversion ceases upon the detection of the T/R code-group pair
denoting the End of Stream Delimiter (ESD) or with the reception of a minimum of two IDLE code-groups.
7.2.11 100BASE-TX Link Integrity Monitor
The 100BASE-TX link monitor ensures that a valid and stable link is established before enabling both the
Transmit and Receive PCS layer.
Signal detect must be valid for 395 µs to allow the link monitor to enter the 'Link Up' state and enable the
transmit and receive functions.
7.2.12 Bad SSD Detection
A Bad Start of Stream Delimiter (Bad SSD) is any transition from consecutive idle code-groups to non-idle
code-groups which is not prefixed by the code-group pair /J/K.
If this condition is detected, the DP83620 will assert RX_ER and present RXD[3:0] = 1110 to the MII for
the cycles that correspond to received 5B code-groups until at least two IDLE code-groups are detected.
In addition, the False Carrier Sense Counter register (FCSCR) will be incremented by one.
Once at least two IDLE code-groups are detected, RX_ER and CRS become de-asserted.
7.3
100BASE-FX OPERATION
The DP83620 provides IEEE 802.3 compliant 100BASE-FX operation. Configuration of FX mode is via
strap option, or through the register interface.
7.3.1
100BASE-FX Transmit
In 100BASE-FX mode, the device Transmit pins connect to an industry standard Fiber Transceiver with
PECL signaling through a capacitively coupled circuit.
In FX mode, the device bypasses the Scrambler and the MLT3 encoder. This allows for the transmission
of serialized 5B4B encoded NRZI data at 125 MHz.
The only added functionality from 100BASE-TX is the support for Far-End Fault data generation.
7.3.2
100BASE-FX Receive
In 100BASE-FX mode, the device Receive pins connect to an industry standard Fiber Transceiver with
PECL signaling through a capacitively coupled circuit.
In FX mode, the device bypasses the MLT3 Decoder and the Descrambler. This allows for the reception of
serialized 5B4B encoded NRZI data at 125 MHz.
The only added functionality for 100BASE-FX from 100BASE-TX is the support of Far-End Fault detection.
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7.3.3
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Far-End Fault
Since 100BASE-FX does not support Auto-Negotiation, a Far-End Fault facility is included which allows for
detection of link failures.
When no signal is being received as determined by the Signal Detect function, the device sends a FarEnd Fault indication to the far-end peer. The Far-End Fault indication is comprised of 3 or more repeating
cycles, each consisting of 84 one’s followed by 1 zero. The pattern is such that it will not satisfy the
100BASE-X carrier sense mechanism, but is easily detected as the Fault indication. The pattern will be
transparent to devices that do not support Far-End Fault.
The Far-End Fault detection process continuously monitors the receive data stream for the Far-End Fault
indication. When detected, the Link Monitor is forced to deassert Link status. This causes the device to
transmit IDLE’s on its transmit path.
7.4
10BASE-T TRANSCEIVER MODULE
The 10BASE-T Transceiver Module is IEEE 802.3 compliant. It includes the receiver, transmitter, collision,
heartbeat, loopback, jabber, and link integrity functions, as defined in the standard. An external filter is not
required on the 10BASE-T interface since this is integrated inside the DP83620. This section focuses on
the general 10BASE-T system level operation.
7.4.1
Operational Modes
The DP83620 has two basic 10BASE-T operational modes:
— Half Duplex mode
— Full Duplex mode
Half Duplex Mode
In Half Duplex mode the DP83620 functions as a standard IEEE 802.3 10BASE-T transceiver supporting
the CSMA/CD protocol.
Full Duplex Mode
In Full Duplex mode the DP83620 is capable of simultaneously transmitting and receiving without
asserting the collision signal. The DP83620's 10 Mb/s ENDEC is designed to encode and decode
simultaneously.
7.4.2
Smart Squelch
The smart squelch is responsible for determining when valid data is present on the differential receive
inputs. The DP83620 implements an intelligent receive squelch to ensure that impulse noise on the
receive inputs will not be mistaken for a valid signal. Smart squelch operation is independent of the
10BASE-T operational mode.
The squelch circuitry employs a combination of amplitude and timing measurements (as specified in the
IEEE 802.3 10BASE-T standard) to determine the validity of data on the twisted pair inputs (refer to
Figure 7-3).
The signal at the start of a packet is checked by the smart squelch and any pulses not exceeding the
squelch level (either positive or negative, depending upon polarity) will be rejected. Once this first squelch
level is overcome correctly, the opposite squelch level must then be exceeded within 150 ns. Finally the
signal must again exceed the original squelch level within 150 ns to ensure that the input waveform will
not be rejected. This checking procedure results in the loss of typically three preamble bits at the
beginning of each packet.
Only after all these conditions have been satisfied will a control signal be generated to indicate to the
remainder of the circuitry that valid data is present. At this time, the smart squelch circuitry is reset.
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Valid data is considered to be present until the squelch level has not been generated for a time longer
than 150 ns, indicating the End of Packet. Once good data has been detected, the squelch levels are
reduced to minimize the effect of noise causing premature End of Packet detection.
The receive squelch threshold level can be lowered for use in longer cable or STP applications. This is
achieved by configuring the SQUELCH bits (11:9) in the 10BTSCR register (0x1A).
9k bytes) without loss of synchronization.
1 = 2 ms.
0 = 722 µs (per ANSI X3.263: 1995 (TP-PMD) 7.2.3.3e).
6
FX_EN
Strap, RW
FX Fiber Mode Enable:
This bit is set when the FX_EN strap option is selected for the respective port.
Write PHYCR2[9], SOFT_RESET, after enabling or disabling Fiber Mode via register
access to ensure correct configuration.
1 = Enables FX operation.
0 = Disables FX operation.
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Table 10-18. 100 Mb/s PCS Configuration and Status Register (PCSR), address 0x16 (continued)
Bit
Bit Name
Default
5
FORCE_100_OK
0, RW
Description
Force 100 Mb/s Good Link:
OR’ed with MAC_FORCE_LINK_100 signal.
1 = Forces 100 Mb/s Good Link.
0 = Normal 100 Mb/s operation.
4
RESERVED
0, RO
3
FEFI_EN
Strap, RW
RESERVED: Writes ignored, read as 0.
Far End Fault Indication Mode Enable:
This bit is set when the FX_EN strap option is selected for the respective port.
1 = FEFI Mode Enabled.
0 = FEFI Mode Disabled.
2
NRZI_BYPASS
0, RW
NRZI Bypass Enable:
1 = NRZI Bypass Enabled.
0 = NRZI Bypass Disabled.
1
SCRAM
BYPASS
Strap, RW
Scrambler Bypass Enable:
This bit is set when the FX_EN strap option is selected. In the FX mode, the
scrambler is bypassed.
1 = Scrambler Bypass Enabled.
0 = Scrambler Bypass Disabled.
0
DESCRAM
BYPASS
Strap, RW
Descrambler Bypass Enable:
This bit is set when the FX_EN strap option is selected. In the FX mode, the
descrambler is bypassed.
1 = Descrambler Bypass Enabled.
0 = Descrambler Bypass Disabled.
10.2.4 RMII and Bypass Register (RBR)
This register configures the RMII/MII Interface Mode of operation. This register controls selecting MII,
RMII, or Single Clock MII mode for Receive or Transmit. In addition, several additional bits are included to
allow datapath selection for Transmit and Receive in multiport applications.
Table 10-19. RMII and Bypass Register (RBR), address 0x17
Bit
Bit Name
Default
15
RESERVED
0, RW
14
RMII_MASTER
Strap, RW
13
DIS_TX_OPT
0, RW
Description
RESERVED: Must be 0.
RMII Master Mode:
Setting this bit allows the core to use a 25 MHz input reference clock and generate
its own 50 MHz RMII reference clock. The generated RMII reference clock will also
be used by the attached MAC.
1 = RMII Master Mode (25 MHz input reference)
0 = RMII Slave Mode (50 MHz input reference)
Note: Due to clock muxing and divider operation, this bit should normally only be
reconfigured via the strap option.
Disable RMII TX Latency Optimization:
Normally the RMII Transmitter will minimize the transmit latency by realigning the
transmit clock with the reference clock phase at the start of a packet transmission.
Setting this bit will disable phase realignment and ensure that IDLE bits will always
be sent in multiples of the symbol size. This will result in a larger uncertainty in
RMII transmit latency.
12:9
82
RESERVED
0000, RW
RESERVED: Must be 0.
Register Block
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Table 10-19. RMII and Bypass Register (RBR), address 0x17 (continued)
Bit
Bit Name
Default
8
PMD_LOOP
0, RW
Description
PMD Loopback:
0 = Normal Operation.
1 = Remote (PMD) Loopback.
Setting this bit will cause the device to Loopback data received from the Physical
Layer. The loopback is done prior to the MII or RMII interface. Data received at the
internal MII or RMII interface will be applied to the transmitter. This mode should
only be used if RMII mode or Single Clock MII mode is enabled.
7
SCMII_RX
0, RW
Single Clock RX MII Mode:
0 = Standard MII mode.
1 = Single Clock RX MII Mode.
Setting this bit will cause the device to generate receive data (RX_DV, RX_ER,
RXD[3:0]) synchronous to the X1 Reference clock. RX_CLK is not used in this
mode. This mode uses the RMII elasticity buffer to tolerate variations in clock
frequencies. This bit cannot be set if RMII_MODE is set to a 1.
6
SCMII_TX
0, RW
Single Clock TX MII Mode:
0 = Standard MII mode.
1 = Single Clock TX MII Mode.
Setting this bit will cause the device to sample transmit data (TX_EN, TXD[3:0])
synchronous to the X1 Reference clock. TX_CLK is not used in this mode. This bit
cannot be set if RMII_MODE is set to a 1.
5
RMII_MODE
Strap, RW
Reduced MII Mode:
0 = Standard MII Mode.
1 = Reduced MII Mode.
4
RMII_REV1_0
0, RW
Reduced MII Revision 1.0:
This bit modifies how CRS_DV is generated.
0 = (RMII revision 1.2) CRS_DV will toggle at the end of a packet to indicate
deassertion of CRS.
1 = (RMII revision 1.0) CRS_DV will remain asserted until final data is transferred.
CRS_DV will not toggle at the end of a packet.
3
RX_OVF_STS
0, RO
RX FIFO Over Flow Status:
0 = Normal.
1 = Overflow detected.
2
RX_UNF_STS
0, RO
RX FIFO Under Flow Status:
0 = Normal.
1 = Underflow detected.
1:0
ELAST_BUF[1:0]
01, RW
Receive Elasticity Buffer:
This field controls the Receive Elasticity Buffer which allows for frequency variation
tolerance between the 50 MHz RMII clock and the recovered data. See Reduced
MII Interface for more information on Elasticity Buffer settings in RMII mode. See
Section Single Clock MII Mode for more information on Elasticity Buffer settings in
SCMII mode.
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10.2.5 LED Direct Control Register (LEDCR)
This register provides the ability to directly control any or all LED outputs. It does not provide read access
to LEDs. In addition, it provides control for the Activity source and blinking LED frequency.
Table 10-20. LED Direct Control Register (LEDCR), address 0x18
Bit
Bit Name
Default
15:1
2
RESERVED
0000, RO
Description
11
DIS_SPDLED
0, RW
1 = Disable LED_SPEED output
0 = Enable LED_SPEED output
10
DIS_LNKLED
0, RW
1 = Disable LED_LINK output
0 = Enable LED_LINK output
9
DIS_ACTLED
0, RW
1 = Disable LED_ACT output
0 = Enable LED_ACT output
8
LEDACT_RX
0, RW
1 = Activity is only indicated for Receive traffic
7:6
BLINK_FREQ
00, RW
RESERVED: Writes ignored, read as 0.
0 = Activity is indicated for Transmit or Receive traffic
LED Blink Frequency:
These bits control the blink frequency of the LED_LINK output when blinking on
activity is enabled.
0 = 6 Hz
1 = 12 Hz
2 = 24 Hz
3 = 48 Hz
5
DRV_SPDLED
0, RW
1 = Drive value of SPDLED bit onto LED_SPEED output
0 = Normal operation
4
DRV_LNKLED
0, RW
3
DRV_ACTLED
0, RW
1 = Drive value of LNKLED bit onto LED_LINK output
0 = Normal operation
1 = Drive value of ACTLED bit onto LED_ACT output
0 = Normal operation
84
2
SPDLED
0, RW
Value to force on LED_SPEED output
1
LNKLED
0, RW
Value to force on LED_LINK output
0
ACTLED
0, RW
Value to force on LED_ACT output
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10.2.6 PHY Control Register (PHYCR)
This register provides control for PHY functions such as MDIX, BIST, LED configuration, and PHY
address. It also provides Pause Negotiation status.
Table 10-21. PHY Control Register (PHYCR), address 0x19
Bit
Bit Name
Default
15
MDIX_EN
1, RW
Description
Auto-MDIX Enable:
1 = Enable Auto-neg Auto-MDIX capability.
0 = Disable Auto-neg Auto-MDIX capability.
14
FORCE_MDIX
0, RW
Force MDIX:
1 = Force MDI pairs to cross.
(Receive on TD pair, Transmit on RD pair)
0 = Normal operation.
13
PAUSE_RX
0, RO
Pause Receive Negotiated:
Indicates that pause receive should be enabled in the MAC. Based on ANAR[11:10]
and ANLPAR[11:10] settings.
This function shall be enabled according to IEEE 802.3 Annex 28B Table 28B-3,
“Pause Resolution”, only if the Auto-Negotiated Highest Common Denominator is a
full duplex technology.
12
PAUSE_TX
0, RO
Pause Transmit Negotiated:
Indicates that pause transmit should be enabled in the MAC. Based on ANAR[11:10]
and ANLPAR[11:10] settings.
This function shall be enabled according to IEEE 802.3 Annex 28B Table 28B-3,
Pause Resolution, only if the Auto-Negotiated Highest Common Denominator is a
full duplex technology.
11
BIST_FE
0, RW/SC
BIST Force Error:
1 = Force BIST Error.
0 = Normal operation.
This bit forces a single error, and is self clearing.
10
PSR_15
0, RW
BIST Sequence select:
1 = PSR15 selected.
0 = PSR9 selected.
9
BIST_STATUS
0, LL/RO
BIST Test Status:
1 = BIST pass.
0 = BIST fail. Latched, cleared when a BIST failure occurs or BIST is stopped.
For a count number of BIST errors, see the BIST Error Count in the CDCTRL1
Register.
8
BIST_START
0, RW
BIST Start:
Writes:
1 = BIST start. Writing 1 to this bit enables transmission of BIST packets and
enables the receive BIST engine to start looking for packet traffic.
0 = BIST stop. Stop the BIST. Writing 0 to this bit also clears the BIST_STATUS bit.
Reads:
1 = BIST active. This bit reads 1 after the transmit BIST engine has been enabled
and the receive BIST engine has detected packet traffic.
0 = BIST inactive. This bit will read 0 if the BIST is disabled or if the BIST is enabled
but no receive traffic has been detected.
7
BP_STRETCH
0, RW
Bypass LED Stretching:
This will bypass the LED stretching and the LEDs will reflect the internal value.
1 = Bypass LED stretching.
0 = Normal operation.
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Table 10-21. PHY Control Register (PHYCR), address 0x19 (continued)
Bit
Bit Name
Default
6
5
LED_CNFG[1]
LED_CNFG[0]
0, RW
Strap, RW
Description
LED Configuration
LED_CNFG[1]
LED_CNFG[0]
Mode Description
Don't care
1
Mode 1
0
0
Mode 2
1
0
Mode 3
In Mode 1, LEDs are configured as follows:
LED_LINK = ON for Good Link, OFF for No Link
LED_SPEED = ON in 100 Mb/s, OFF in 10 Mb/s
LED_ACT = ON for Activity, OFF for No Activity
In Mode 2, LEDs are configured as follows:
LED_LINK = ON for Good Link, BLINK for Activity
LED_SPEED = ON in 100 Mb/s, OFF in 10 Mb/s
LED_ACT = ON for Collision, OFF for No Collision
In Mode 3, LEDs are configured as follows:
LED_LINK = ON for Good Link, BLINK for Activity
LED_SPEED = ON in 100 Mb/s, OFF in 10 Mb/s
LED_ACT = ON for Full Duplex, OFF for Half Duplex
4:0
PHYADDR[4:0]
Strap, RW
PHY Address: PHY address for port.
Note: The local PHY address cannot be changed via a broadcast write - writing to
PHY address 0x1F register 0x19 will not change the PHYADDR bits.
10.2.7 10Base-T Status/Control Register (10BTSCR)
This register is used for control and status for 10BASE-T device operation.
Table 10-22. 10Base-T Status/Control Register (10BTSCR), address 0x1A
Bit
Bit Name
Default
15
RESERVED
0, RO
Description
14:12
RESERVED
000, RW
RESERVED: Must be zero.
11:9
SQUELCH
100, RW
Squelch Configuration:
Used to set the Squelch 'ON' threshold for the receiver.
Default Squelch 'ON' is 330mV peak.
8
LOOPBACK_10_DIS
0, RW
RESERVED: Writes ignored, read as 0.
10Base-T Loopback Disable:
This bit is OR’ed with bit 14 (Loopback) in the BMCR.
1 = 10BT Loopback is disabled
0 = 10BT Loopback is enabled
7
LP_DIS
0, RW
Normal Link Pulse Disable:
This bit is OR’ed with the MAC_FORCE_LINK_10 signal.
1 = Transmission of NLPs is disabled.
0 = Transmission of NLPs is enabled.
6
FORCE_LINK_10
0, RW
Force 10 Mb Good Link:
This bit is OR’ed with the MAC_FORCE_LINK_10 signal.
1 = Forced Good 10 Mb Link.
0 = Normal Link Status.
5
FORCE_POL COR
0, RW
4
POLARITY
0, RO/LH
Force 10 Mb Polarity Correction:
1 = Force inverted polarity
0 = Normal polarity
10 Mb Polarity Status:
This bit is a duplication of bit 12 in the PHYSTS register. Both bits will be cleared
upon a read of either register.
1 = Inverted Polarity detected.
0 = Correct Polarity detected.
3
86
AUTOPOL_DIS
0, RW
Auto Polarity Detection & Correction Disable:
1 = Polarity Correction disabled
0 = Polarity Correction enabled
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Table 10-22. 10Base-T Status/Control Register (10BTSCR), address 0x1A (continued)
Bit
Bit Name
Default
2
10BT_SCALE - MSB
1, RW
10BT Scale Configuration Most Significant Bit
Used in conjunction with bit 10 of SD_CNFG register to set the silence ’OFF’
threshold for the receiver.
Description
1
HEARTBEAT_DIS
0, RW
Heartbeat Disable:
This bit only has influence in half-duplex 10 Mb mode.
1 = Heartbeat function disabled.
0 = Heartbeat function enabled.
When the device is operating at 100 Mb or configured for full duplex
operation, this bit will be ignored - the heartbeat function is disabled.
0
JABBER_DIS
0, RW
Jabber Disable:
This bit is only applicable in 10BASE-T.
1 = Jabber function disabled.
0 = Jabber function enabled.
10.2.8 CD Test and BIST Extensions Register (CDCTRL1)
This register controls test modes for the 10BASE-T Common Driver. In addition it contains extended
control and status for the packet BIST function.
Table 10-23. CD Test and BIST Extensions Register (CDCTRL1), address 0x1B
Bit
Bit Name
Default
15:8
BIST_ERROR_COUNT
0000 0000, RO
Description
BIST ERROR Counter:
Counts number of errored data nibbles during Packet BIST. This value
will reset when Packet BIST is restarted. The counter sticks when it
reaches its maximum count of FFh.
7
RESERVED
0, RW
RESERVED: Must be 0.
6
MII_CLOCK_EN
0, RW
Enables MII Clocks TX_CLK and RX_CLK independent of MAC interface
mode selected; for example, normally TX_CLK and RX_CLK are
disabled in RMII Slave mode.
1 = Enable TX_CLK and RX_CLK
0 = Default operation
5
BIST_CONT
0, RW
Packet BIST Continuous Mode:
Allows continuous pseudorandom data transmission without any break in
transmission. This can be used for transmit VOD testing. This is used in
conjunction with the BIST controls in the PHYCR Register (19h). For 10
Mb operation, jabber function must be disabled, bit 0 of the 10BTSCR
(1Ah), JABBER_DIS = 1.
4
CDPATTEN_10
0, RW
CD Pattern Enable for 10 Mb:
1 = Enabled.
0 = Disabled.
3
MDIO_PULL_EN
0, RW
Enable Internal MDIO Pullup:
1 = Internal MDIO pullup enabled
0 = Internal MDIO pullup disabled
This bit is only reset on hard reset. This bit should not be set in systems
that share the management interfaces among several ASICs.
2
PATT_GAP_10M
0, RW
Defines gap between data or NLP test sequences:
1 = 15 µs.
0 = 10 µs.
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Table 10-23. CD Test and BIST Extensions Register (CDCTRL1), address 0x1B (continued)
Bit
Bit Name
Default
1:0
CDPATTSEL[1:0]
00, RW
Description
CD Pattern Select[1:0]:
If CDPATTEN_10 = 1:
00 = Data, EOP0 sequence.
01 = Data, EOP1 sequence.
10 = NLPs.
11 = Constant Manchester 1s (10 MHz sine wave) for harmonic distortion
testing.
10.2.9 PHY Control Register 2 (PHYCR2)
This register provides additional general control.
Table 10-24. PHY Control Register 2 (PHYCR2), address 0x1C
Bit
Bit Name
Default
Description
15:14
RESERVED
00, RO
RESERVED: Writes ignored, read as 0.
13
SYNC_ENET EN
0, RW
Synchronous Ethernet Enable:
When this bit is 1 and the device is in 100 Mb/s mode, and the MAC
interface is either MII or RMII Master, enables fully synchronous
communication relative to the recovered receive clock. The transmitter is
synchronized to the receiver.
When this bit is 0 or the device settings do not match the above
conditions, the transmitter is synchronous to the local reference clock.
12
CLK_OUT RXCLK
0, RW
Enable RX_CLK on CLK_OUT:
When this bit is 1 and the device is in 100 Mb/s mode, the 25 MHz
recovered receive clock (RX_CLK) is driven on CLK_OUT in addition to
RX_CLK. When this bit is 0 or the device is in 10 Mb/s mode, CLK_OUT
reflects the Reference clock.
11
BC_WRITE
0, RW
Broadcast Write Enable:
1 = Enables the Serial Management Interface to accept register writes to
PHY Address of 0x1F independent of the local PHY Address value.
0 = Normal operation
10
PHYTER_COMP
0, RW
Phyter Compatibility Mode:
1 = Enables Phyter (DP83848) Compatible pinout. Reorders the RX MII
pins and Autonegotiation straps to match the DP83848. Also enables the
CLK_OUT output.
0 = Normal operation
9
SOFT_RESET
0, RW/SC
Soft Reset:
Resets the entire device minus the registers - all configuration is
preserved.
1 = Reset, self-clearing.
88
8:2
RESERVED
0 0000 00, RO
1
CLK_OUT_DIS
Strap, RW
0
RESERVED
0, RW
RESERVED: Writes ignored, read as 0.
Disable CLK_OUT Output:
Disables the CLK_OUT output pin.
RESERVED: Must be zero.
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10.2.10 Energy Detect Control (EDCR)
This register provides control and status for the Energy Detect function.
Table 10-25. Energy Detect Control (EDCR), address 0x1D
Bit
Bit Name
Default
15
ED_EN
0, RW
Description
Energy Detect Enable:
Allow Energy Detect Mode.
14
ED_AUTO_UP
1, RW
Energy Detect Automatic Power Up:
Automatically begin power up sequence when Energy Detect Data
Threshold value (EDCR[3:0]) is reached. Alternatively, the device could
be powered up manually using the ED_MAN bit (ECDR[12]).
13
ED_AUTO_DOWN
1, RW
Energy Detect Automatic Power Down:
Automatically begin power down sequence when no energy is detected.
Alternatively, the device could be powered down using the ED_MAN bit
(EDCR[12]).
12
ED_MAN
0, RW/SC
Energy Detect Manual Power Up/Down:
Begin power up/down sequence when this bit is asserted. When set, the
Energy Detect algorithm will initiate a change of Energy Detect state
regardless of threshold (error or data) and timer values. In managed
applications, this bit can be set after clearing the Energy Detect interrupt
to control the timing of changing the power state.
11
ED_BURST_DIS
0, RW
Energy Detect Burst Disable:
Disable bursting of energy detect data pulses. By default, Energy Detect
(ED) transmits a burst of 4 ED data pulses each time the CD is powered
up. When bursting is disabled, only a single ED data pulse will be sent
each time the CD is powered up.
10
ED_PWR_STATE
0, RO
Energy Detect Power State:
Indicates current Energy Detect Power state. When set, Energy Detect is
in the powered up state. When cleared, Energy Detect is in the powered
down state. This bit is invalid when Energy Detect is not enabled.
9
ED_ERR_MET
0, RO/COR
Energy Detect Error Threshold Met:
No action is automatically taken upon receipt of error events. This bit is
informational only and would be cleared on a read.
8
ED_DATA_MET
0, RO/COR
Energy Detect Data Threshold Met:
The number of data events that occurred met or surpassed the Energy
Detect Data Threshold. This bit is cleared on a read.
7:4
ED_ERR_COUNT
0001, RW
Energy Detect Error Threshold:
Threshold to determine the number of energy detect error events that
should cause the device to take action. Intended to allow averaging of
noise that may be on the line. Counter will reset after approximately 2
seconds without any energy detect data events.
3:0
ED_DATA_COUNT
0001, RW
Energy Detect Data Threshold:
Threshold to determine the number of energy detect events that should
cause the device to take actions. Intended to allow averaging of noise
that may be on the line. Counter will reset after approximately 2 seconds
without any energy detect data events.
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10.2.11 PHY Control Frames Configuration Register (PCFCR)
This register provides configuration for the PHY Control Frame mechanism for register access.
Table 10-26. PHY Control Frames Configuration Register (PCFCR), address 0x1F
Bit
Bit Name
Default
15
PCF_STS_ERR
0, RO/COR
Description
PHY Control Frame Error Detected:
Indicates an error was detected in a PCF Frame since the last read of
this register. This bit will be cleared on read.
14
PCF_STS_OK
0, RO/COR
PHY Control Frame OK:
Indicates a PCF Frame has completed without error since the last read
of this register. This bit will be cleared on read.
13:9
RESERVED
00 000, RO
8
PCF_DA_SEL
0, RW
Reserved: Writes ignored, read as 0
Select MAC Destination Address for PHY Control Frames:
0 : Use MAC Address [08 00 17 0B 6B 0F]
1 : Use MAC Address [08 00 17 00 00 00]
The device will also recognize packets with the above address with the
Multicast bit set (i.e. 09 00 17 ...).
7:6
PCF_INT_CTL
00, RW
PHY Control Frame Interrupt Control:
Setting either of these bits enables control and status of the PCF
Interrupt through the MISR Register (taking the place of the RHF
Interrupt).
00 = PCF Interrupts Disabled
x1 = Interrupt on PCF Frame OK
1x = Interrupt on PCF Frame Error
5
PCF_BC_DIS
0, RW
PHY Control Frame Broadcast Disable:
By default, the device will accept broadcast PHY Control Frames which
have a PHY Address field of 0x1F. If this bit is set to a 1, the PHY
Control Frame must have a PHY Address field that exactly matches the
device PHY Address.
4:1
PCF_BUF
0 000, RW
PHY Control Frame Buffer Size:
Determines the buffer size for transmit to allow PHY Control Frame
detection. All packets will be delayed as they pass through this buffer. If
set to 0, packets will not be delayed and PHY Control frames will be
truncated after the Destination Address field.
0
PCF_EN
Strap, RW
PHY Control Frame Enable:
Enables Register writes using PHY Control Frames.
90
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10.3 TEST REGISTERS - PAGE 1
Page 1 Test Registers are accessible by setting bits [2:0] = 001 of PAGESEL (13h).
10.3.1 Signal Detect Configuration (SD_CNFG), Page 1
This register contains Signal Detect configuration control as well as some test controls to speed up Autoneg testing.
Table 10-27. Signal Detect Configuration (SD_CNFG), address 0x1E
Bit
Bit Name
Default
15
RESERVED
1, RW
RESERVED: Write as 1, read as 1.
Description
14:1
2
RESERVED
000, RW
RESERVED: Write as 0, read as 0.
11
RESERVED
0, RO
10:9
RESERVED
00, RW
RESERVED: Write ignored, read as 0.
RESERVED: Write as 0, read as 0.
8
SD_TIME
0, RW
Signal Detect Time
Setting this bit to a 1 enables a fast detection of loss of Signal Detect.
This will result in a fast loss of Link indication. Approximate times to
detect signal detect deassertion are:
1 = 1 µs
0 = 250 µs
7:0
RESERVED
0000 0000, RW
RESERVED: Write as 0, read as 0.
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10.4 LINK DIAGNOSTICS REGISTERS - PAGE 2
Page 2 Link Diagnostics Registers are accessible by setting bits [2:0] = 010 of PAGESEL (13h).
10.4.1 100 Mb Length Detect Register (LEN100_DET), Page 2
This register contains linked cable length estimation in 100 Mb operation. The cable length is an
estimation of the effective cable length based on the characteristics of the recovered signal. The cable
length is valid only during 100 Mb operation with a valid Link status indication.
Table 10-28. 100 Mb Length Detect Register (LEN100_DET), address 0x14
Bit
Bit Name
Default
15:8
RESERVED
0000 0000, RO
RESERVED: Writes ignored, read as 0.
Description
7:0
CABLE_LEN
1111 1111, RO
Cable Length Estimate:
Indicates an estimate of effective cable length in meters. A value of FFh
indicates cable length cannot be determined.
10.4.2 100 Mb Frequency Offset Indication Register (FREQ100), Page 2
This register returns an indication of clock frequency offset relative to the link partner. Two values can be
read, the long term Frequency Offset, or a short term Frequency Control value. The Frequency Control
value includes short term phase correction. The variance between the Frequency Control value and the
Frequency Offset can be used as an indication of the amount of jitter in the system.
Table 10-29. 100 Mb Frequency Offset Indication Register (FREQ100), address 0x15
Bit
Bit Name
Default
15
SAMPLE_FREQ
0, WO
Description
Sample Frequency Offset:
If SEL_FC is set to a 0, then setting this bit to a 1 will poll the DSP for
the long-term Frequency Offset value. The value will be available in
the FREQ_OFFSET bits of this register.
If SEL_FC is set to a 1, then setting this bit to a 1 will poll the DSP for
the current Frequency Control value. The value will be available in the
FREQ_OFFSET bits of this register.
This register bit will always read back as 0.
14:9
RESERVED
000 000, RO
8
SEL_FC
0, RW
RESERVED: Writes ignored, read as 0.
Select Frequency Control:
Setting this bit to a 1 will select the current Frequency Control value
instead of the Frequency Offset. This value contains Frequency Offset
plus the short term phase correction and can be used to indicate
amount of jitter in the system. The value will be available in the
FREQ_OFFSET bits of this register.
7:0
FREQ_OFFSET
0000 0000, RO
Frequency Offset:
Frequency offset value loaded from the DSP following assertion of the
SAMPLE_FREQ control bit. The Frequency Offset or Frequency
Control value is a twos-complement signed value in units of
approximately 5.1562 ppm. The range is as follows:
0x7F = +655 ppm
0x00 = 0 ppm
0x80 = -660 ppm
92
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10.4.3 TDR Control Register (TDR_CTRL), Page 2
This register contains control for the Time Domain Reflectometry (TDR) cable diagnostics. The TDR cable
diagnostics sends pulses down the cable and captures reflection data to be used to estimate cable length
and detect certain cabling faults.
Table 10-30. TDR Control Register (TDR_CTRL), address 0x16
Bit
Bit Name
Default
15
TDR_ENABLE
0, RW
Description
TDR Enable:
Enable TDR mode. This forces the powerup state to the correct operating
condition for sending and receiving TDR pulses.
14
TDR_100Mb
0, RW
TDR 100Mb:
Sets the TDR controller to use the 100 Mb Transmitter. This allows for
sending pulse widths in multiples of 8ns. Pulses in 100 Mb mode will
alternate between positive pulses and negative pulses.
Default operation uses the 10 Mb Link Pulse generator. Pulses may
include just the 50 ns pre-emphasis portion of the pulse or the 100 ns full
link pulse (as controlled by setting TDR Width).
13
TX_CHANNEL
0, RW
Transmit Channel Select:
Select transmit channel for sending pulses. The pulse can be sent on the
Transmit or Receive pair.
0 : Transmit channel
1 : Receive channel
12
RX_CHANNEL
0, RW
Receive Channel Select:
Select receive channel for detecting pulses. The pulse can be monitored
on the Transmit or Receive pair.
0 : Transmit channel
1 : Receive channel
11
SEND_TDR
0, RW/SC
Send TDR Pulse:
Setting this bit will send a TDR pulse and enable the monitor circuit to
capture the response. This bit will automatically clear when the capture is
complete.
10:8
TDR_WIDTH
000, RW
TDR Pulse Width:
Pulse width in clocks for the transmitted pulse. In 100 Mb mode, pulses
are in 8 ns increments. In 10 Mb mode, pulses are in 50 ns increments,
but only 50 ns or 100 ns pulses can be sent. Sending a pulse of 0 width
will not transmit a pulse, but allows for baseline testing.
7
TDR_MIN_MODE
0, RW
Min/Max Mode control:
This bit controls direction of the pulse to be detected. Default looks for a
positive peak. Threshold and peak values will be interpreted appropriately
based on this bit.
0 : Max Mode, detect positive peak
1 : Min Mode, detect negative peak
6
RESERVED
0, RW
5:0
RX_THRESHOLD
10 0000, RW
RESERVED: Must be zero.
RX Threshold:
This value provides a threshold for measurement to the start of a peak. If
Min Mode is set to 0, data must be greater than this value to trigger a
capture. If Min Mode is 1, data must be less than this value to trigger a
capture. Data ranges from 0x00 to 0x3F, with 0x20 as the midpoint.
Positive data is greater than 0x20, negative data is less than 0x20.
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10.4.4 TDR Window Register (TDR_WIN), Page 2
This register contains sample window control for the Time Domain Reflectometry (TDR) cable diagnostics.
The two values contained in this register specify the beginning and end times for the window to monitor
the response to the transmitted pulse. Time values are in 8 ns increments. This provides a method to
search for multiple responses and also to screen out the initial outgoing pulse.
Table 10-31. TDR Window Register (TDR_WIN), address 0x17
Bit
Bit Name
Default
15:8
TDR_START
0000 0000, RW
Description
TDR Start Window:
Specifies start time for monitoring TDR response.
7:0
TDR_STOP
0000 0000, RW
TDR Stop Window:
Specifies stop time for monitoring TDR response. The Stop Window
should be set to a value greater than or equal to the Start Window.
10.4.5 TDR Peak Register (TDR_PEAK), Page 2
This register contains the results of the TDR Peak Detection. Results are valid if the TDR_CTRL[11] is
clear following sending the TDR pulse.
Table 10-32. TDR Peak Register (TDR_PEAK), address 0x18
Bit
Bit Name
Default
15:14
RESERVED
00, RO
13:8
TDR_PEAK
00 0000, RO
Description
RESERVED: Writes ignored, read as 0.
TDR Peak Value:
This register contains the peak value measured during the TDR sample
window. If Min Mode control (TDR_CTRL[7]) is 0, this contains the
maximum detected value. If Min Mode control is 1, this contains the
minimum detected value.
7:0
TDR_PEAK_TIME
0000 0000, RO
TDR Peak Time:
Specifies the time for the first occurrence of the peak value.
10.4.6 TDR Threshold Register (TDR_THR), Page 2
This register contains the results of the TDR Threshold Detection. Results are valid if the TDR_CTRL[11]
is clear following sending the TDR pulse.
Table 10-33. TDR Threshold Register (TDR_THR), address 0x19
Bit
Bit Name
Default
15:9
RESERVED
0000 000, RO
Description
8
TDR_THR_MET
0, RO
RESERVED: Writes ignored, read as 0.
TDR Threshold Met:
This bit indicates the TDR threshold was met during the sample window. A
value of 0 indicates the threshold was not met.
7:0
TDR_THR_TIME
0000 0000, RO
TDR Threshold Time:
Specifies the time for the first data that met the TDR threshold. This field is
only valid if the threshold was met.
94
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10.4.7 Variance Control Register (VAR_CTRL), Page 2
The Variance Control and Data Registers provide control and status for the Cable Signal Quality
Estimation function. The Cable Signal Quality Estimation allows a simple method of determining an
approximate Signal-to-Noise Ratio for the 100 Mb receiver. This register contains the programmable
controls and status bits for the variance computation, which can be used to make a simple Signal-to-Noise
Ratio estimation.
Table 10-34. Variance Control Register (VAR_CTRL), address 0x1A
Bit
Bit Name
Default
15
VAR_RDY
0, RO
Description
Variance Data Ready Status:
Indicates new data is available in the Variance data register. This bit will be
automatically cleared after two consecutive reads of VAR_DATA.
14:4
RESERVED
000 0000 0000, RO
3
VAR_FREEZE
0, RW
RESERVED: Writes ignored, read as 0.
Freeze Variance Registers:
Freeze VAR_DATA register.
This bit is ensures that VAR_DATA register is frozen for software reads. This bit is
automatically cleared after two consecutive reads of VAR_DATA.
2:1
VAR_TIMER
00, RW
Variance Computation Timer (in ms):
Selects the Variance computation timer period. After a new value is written,
computation is automatically restarted. New variance register values are loaded
after the timer elapses.
Var_Timer = 0 => 2 ms timer (default)
Var_Timer = 1 => 4 ms timer
Var_Timer = 2 => 6 ms timer
Var_Timer = 3 => 8 ms timer
Time units are actually 217 cycles of an 8 ns clock, or 1.048576 ms.
0
VAR_ENABLE
0, RW
Variance Enable:
Enable Variance computation. Off by default.
10.4.8 Variance Data Register (VAR_DATA), Page 2
This register contains the 32-bit Variance Sum. The contents of the data are valid only when VAR_RDY is
asserted in the VAR_CTRL register. Upon detection of VAR_RDY asserted, software should set the
VAR_FREEZE bit in the VAR_CTRL register to prevent loading of a new value into the VAR_DATA
register. Since the Variance Data value is 32-bits, two reads of this register are required to get the full
value.
Table 10-35. Variance Data Register (VAR_DATA), address 0x1B
Bit
Bit Name
Default
15:0
VAR_DATA
0000 0000 0000
0000, RO
Description
Variance Data:
Two reads are required to return the full 32-bit Variance Sum value. Following
setting the VAR_FREEZE control, the first read of this register will return the low 16
bits of the Variance data. A second read will return the high 16 bits of Variance data.
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10.4.9 Link Quality Monitor Register (LQMR), Page 2
This register contains the controls for the Link Quality Monitor function. The Link Quality Monitor provides
a mechanism for programming a set of thresholds for DSP parameters. If the thresholds are violated, an
interrupt will be asserted if enabled in the MISR. Monitor control and status are available in this register,
while the LQDR register controls read/write access to threshold values and current parameter values.
Reading the LQMR register clears warning bits and re-arms the interrupt generation. In addition, this
register provides a mechanism for allowing automatic reset of the 100 Mb link based on the Link Quality
Monitor status.
Table 10-36. Link Quality Monitor Register (LQMR), address 0x1D
Bit
Bit Name
Default
15
LQM_ENABLE
0, RW
Description
Link Quality Monitor Enable:
Enables the Link Quality Monitor. The enable is qualified by having a valid 100 Mb
link. In addition, the individual thresholds can be disabled by setting to the
maximum or minimum values.
14
RESTART_ON_FC
0, RW
Restart on Frequency Control Warning:
Allow automatic reset of DSP and restart of 100 Mb Adaption on detecting a
Frequency Threshold violation. If the SD_Option bit, PCSR[8], is set to 0, the
threshold violation will also result in a drop in Link status.
13
RESTART_ON
_FREQ
0, RW
Restart on Frequency Offset Warning:
Allow automatic reset of DSP and restart of 100 Mb Adaption on detecting a
Frequency Offset Threshold violation. If the SD_Option bit, PCSR[8], is set to 0, the
threshold violation will also result in a drop in Link status.
12
RESTART_ON
_DBLW
0, RW
Restart on DBLW Warning:
Allow automatic reset of DSP and restart of 100 Mb Adaption on detecting a DBLW
Threshold violation. If the SD_Option bit, PCSR[8], is set to 0, the threshold
violation will also result in a drop in Link status.
11
RESTART_ON
_DAGC
0, RW
Restart on DAGC Warning:
Allow automatic reset of DSP and restart of 100 Mb Adaption on detecting a DAGC
Threshold violation. If the SD_Option bit, PCSR[8], is set to 0, the threshold
violation will also result in a drop in Link status.
10
RESTART_ON_C1
0, RW
Restart on C1 Warning:
Allow automatic reset of DSP and restart of 100 Mb Adaption on detecting a C1
Threshold violation. If the SD_Option bit, PCSR[8], is set to 0, the threshold
violation will also result in a drop in Link status.
9
FC_HI_WARN
0, RO/COR
Frequency Control High Warning:
This bit indicates the Frequency Control High Threshold was exceeded. This
register bit will be cleared on read.
8
FC_LO_WARN
0, RO/COR
Frequency Control Low Warning:
This bit indicates the Frequency Control Low Threshold was exceeded. This
register bit will be cleared on read.
7
FREQ_HI_WARN
0, RO/COR
Frequency Offset High Warning:
This bit indicates the Frequency Offset High Threshold was exceeded. This register
bit will be cleared on read.
6
FREQ_LO_WARN
0, RO/COR
Frequency Offset Low Warning:
This bit indicates the Frequency Offset Low Threshold was exceeded. This register
bit will be cleared on read.
5
DBLW_HI_WARN
0, RO/COR
DBLW High Warning:
This bit indicates the DBLW High Threshold was exceeded. This register bit will be
cleared on read.
4
DBLW_LO_WARN
0, RO/COR
DBLW Low Warning:
This bit indicates the DBLW Low Threshold was exceeded. This register bit will be
cleared on read.
3
DAGC_HI_WARN
0, RO/COR
DAGC High Warning:
This bit indicates the DAGC High Threshold was exceeded. This register bit will be
cleared on read.
96
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Table 10-36. Link Quality Monitor Register (LQMR), address 0x1D (continued)
Bit
Bit Name
Default
2
DAGC_LO_WARN
0, RO/COR
Description
DAGC Low Warning:
This bit indicates the DAGC Low Threshold was exceeded. This register bit will be
cleared on read.
1
C1_HI_WARN
0, RO/COR
C1 High Warning:
This bit indicates the DEQ C1 High Threshold was exceeded. This register bit will
be cleared on read.
0
C1_LO_WARN
0, RO/COR
C1 Low Warning:
This bit indicates the DEQ C1 Low Threshold was exceeded. This register bit will
be cleared on read.
10.4.10 Link Quality Data Register (LQDR), Page 2
This register provides read/write control of thresholds for the 100 Mb Link Quality Monitor function. The
register also provides a mechanism for reading current adapted parameter values. Threshold values may
not be written if the device is powered-down.
Table 10-37. Link Quality Data Register (LQDR), address 0x1E
Bit
Bit Name
Default
15:14
RESERVED
00, RO
RESERVED: Writes ignored, read as 0.
Description
13
SAMPLE_PARAM
0, RW
Sample DSP Parameter:
Setting this bit to a 1 enables reading of current parameter values and initiates
sampling of the parameter value. The parameter to be read is selected by the
LQ_PARAM_SEL bits.
12
WRITE_LQ_THR
0, RW
Write Link Quality Threshold:
Setting this bit will cause a write to the Threshold register selected by
LQ_PARAM_SEL and LQ_THR_SEL. The data written is contained in
LQ_THR_DATA. This bit will always read back as 0.
11:9
LQ_PARAM_SEL
000, RW
Link Quality Parameter Select:
This 3-bit field selects the Link Quality Parameter. This field is used for sampling
current parameter values as well as for reads/writes to Threshold values. The
following encodings are available:
000: DEQ_C1
001: DAGC
010: DBLW
011: Frequency Offset
100: Frequency Control
101: Variance most significant bits 31:16
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Table 10-37. Link Quality Data Register (LQDR), address 0x1E (continued)
Bit
Bit Name
Default
8
LQ_THR_SEL
0, RW
Description
Link Quality Threshold Select:
This bit selects the Link Quality Threshold to be read or written. A 0 selects the
Low threshold, while a 1 selects the high threshold. When combined with the
LQ_PARAM_SEL field, the following encodings are available {LQ_PARAM_SEL,
LQ_THR_SEL}:
000,0: DEQ_C1 Low
000,1: DEQ_C1 High
001,0: DAGC Low
001,1: DAGC High
010,0: DBLW Low
010,1: DBLW High
011,0: Frequency Offset Low
011,1: Frequency Offset High
100,0: Frequency Control Low
100,1: Frequency Control High
101,0: Variance High bits 7:0 (Variance bits 23:16)
101,1: Variance High bits 15:8 (Variance bits 31:24)
7:0
LQ_THR_DATA
1000 0000, RW
Link Quality Threshold Data:
The operation of this field is dependent on the value of the SAMPLE_PARAM bit.
If SAMPLE_PARAM = 0:
On a write, this value contains the data to be written to the selected Link Quality
Threshold register.
On a read, this value contains the current data in the selected Link Quality
Threshold register.
If SAMPLE_PARAM = 1:
On a read, this value contains the sampled parameter value. This value will
remain unchanged until a new read sequence is started.
10.4.11 Link Quality Monitor Register 2 (LQMR2), Page 2
This register contains additional controls for the Link Quality Monitor function. The Link Quality Monitor
provides a mechanism for programming a set of thresholds for DSP parameters. If the thresholds are
violated, an interrupt will be asserted if enabled in the MISR. Monitor control and status are available in
this register, while the LQDR register controls read/write access to threshold values and current parameter
values. Reading of LQMR2 register clears its warning bits but does NOT re-arm the interrupt generation;
LQMR must be read to re-arm interrupt generation. In addition, this register provides a mechanism for
allowing automatic reset of the 100 Mb link based on the Link Quality Monitor variance status.
Table 10-38. Link Quality Monitor Register 2 (LQMR2), address 0x1F
Bit
Bit Name
Default
15:11
RESERVED
0000 0, RO
10
RESTART_ON_VAR
0, RW
9:2
RESERVED
00 0000 00, RO
1
VAR_HI_WARN
0, RO/COR
0
RESERVED
0, RO
98
Description
Reserved: Writes ignored, Read as 0
Restart on Variance Warning:
Allow automatic reset of DSP and restart of 100 Mb Adaption on detecting a
Frequency Offset Threshold violation. If the SD_Option bit, PCSR[8], is set to 0, the
threshold violation will also result in a drop in Link status.
Reserved: Writes ignored, Read as 0
Variance High Warning:
This bit indicates the Variance High Threshold was exceeded. This register bit will
be cleared on read.
Reserved: Writes ignored, Read as 0
Register Block
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10.5 PHY STATUS FRAME CONFIGURATION REGISTER - PAGE 5
The Page 5 PHY Status Frame Configuration Register is accessible by setting bits [2:0] = 101 of
PAGESEL (13h).
10.5.1 PHY Status Frame Configuration Register(PSF_CFG), Page 5
This register provides configuration for the PHY Status Frame function.
Table 10-39. PHY Status Frame Configuration Register(PSF_CFG), address 0x18
Bit
Bit Name
Default
15:13
RESERVED
000, RO
Reserved: Writes ignored, Read as 0
Description
12:11
MAC_SRC_ADD
00, RW
PHY Status Frame Mac Source Address:
Selects source address as follows:
00 : Use Mac Address [08 00 17 0B 6B 0F]
01 : Use Mac Address [08 00 17 00 00 00]
10 : Use Mac Multicast Dest Address
11 : Use Mac Address [00 00 00 00 00 00]
10:8
MIN_PRE
000, RW
PHY Status Frame Minimum Preamble:
Determines the minimum preamble bytes required for sending packets on the MII
interface. It is recommended that this be set to the smallest value the MAC will
tolerate.
7
PSF_ENDIAN
0, RW
PHY Status Frame Endian Control:
For each 16-bit field in a Status Message, the data will normally be presented in
network byte order (Most significant byte first). If this bit is set to a 1, the byte data
fields will be reversed so that the least significant byte is first.
6
PSF_IPV4
0, RW
PHY Status Frame IPv4 Enable:
This bit controls the type of packet used for PHY Status Frames.
0 = Layer2 Ethernet packets
1 = IPv4 packets.
5
PSF_PCF_RD
0, RW
PHY Control Frame Read PHY Status Frame Enable:
Enable PHY Status Frame delivery of PHY Control Frame read data. Data read via
a PHY Control Frame will be returned in a PHY Status Frame.
4
PSF_ERR_EN
0, RW
PSF Error PHY Status Frame Enable:
Enable PHY Status Frame delivery of PHY Status Frame Errors. This bit will not
independently enable PHY Status Frame operation. One of the other enable bits
must be set for PHY Status Frames to be generated.
3:0
RESERVED
0000, RW
Reserved: Must be 0x0.
Register Block
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SNLS339C – JANUARY 2011 – REVISED APRIL 2013
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Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (April 2013) to Revision C
•
100
Changed layout of National Data Sheet to TI format
Page
..........................................................................
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
(4/5)
(6)
DP83620SQ/NOPB
ACTIVE
WQFN
RHS
48
1000
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 85
DP83620SQ
DP83620SQE/NOPB
ACTIVE
WQFN
RHS
48
250
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 85
DP83620SQ
DP83620SQX/NOPB
ACTIVE
WQFN
RHS
48
2500
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 85
DP83620SQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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