DP83815DUJB/NOPB

DP83815 DP83815 10/100 Mb/s Integrated PCI Ethernet Media Access Controller and Physical Layer (MacPhyter) Literature Number: SNLS059E DP83815 10/100 Mb/s Integrated PCI Ethernet Media Access Controller and Physical Layer (MacPhyter™) DP83815 is a single-chip 10/100 Mb/s Ethernet Controller for the PCI bus. It is targeted at low-cost, high volume PC mother boards, adapter cards, and embedded systems. The DP83815 fully implements the V2.2 33 MHz PCI bus interface for host communications with power management support. Packet descriptors and data are transferred via bus-mastering, reducing the burden on the host CPU. The DP83815 can support full duplex 10/100 Mb/s transmission and reception, with minimum interframe gap. Features ol e The DP83815 device is an integration of an enhanced version of the National Semiconductor PCI MAC/BIU (Media Access Controller/Bus Interface Unit) and a 3.3V CMOS physical layer interface. — Virtual LAN (VLAN) and long frame support — Support for IEEE 802.3x Full duplex flow control — Extremely flexible Rx packet filtration including: single address perfect filter with MSb masking, broadcast, 512 entry multicast/unicast hash table, deep packet pattern matching for up to 4 unique patterns — Statistics gathered for support of RFC 1213 (MIB II), RFC 1398 (Ether-like MIB), IEEE 802.3 LME, reducing CPU overhead for management — Internal 2 KB Transmit and 2 KB Receive data FIFOs — Serial EEPROM port with auto-load of configuration data from EEPROM at power-on — Flash/PROM interface for remote boot support — Fully integrated IEEE 802.3/802.3u 3.3V CMOS physical layer — IEEE 802.3 10BASE-T transceiver with integrated filters — IEEE 802.3u 100BASE-TX transceiver — Fully integrated ANSI X3.263 compliant TP-PMD physical sublayer with adaptive equalization and Baseline Wander compensation — IEEE 802.3u Auto-Negotiation - advertised features configurable via EEPROM — Full Duplex support for 10 and 100 Mb/s data rates — Single 25 MHz reference clock — 144-pin LQFP and 160-pin LBGA packages — Low power 3.3V CMOS design with typical consumption of 561 mW operating, 380 mW during WOL mode, 33 mW sleep mode — IEEE 802.3u MII for connecting alternative external Physical Layer Devices te General Description O bs — IEEE 802.3 Compliant, PCI V2.2 MAC/BIU supports traditional data rates of 10 Mb/s Ethernet and 100 Mb/s Fast Ethernet (via internal phy) — Bus master - burst sizes of up to 128 dwords (512 bytes) — BIU compliant with PC 97 and PC 98 Hardware Design Guides, PC 99 Hardware Design Guide draft, ACPI v1.0, PCI Power Management Specification v1.1, OnNow Device Class Power Management Reference Specification - Network Device Class v1.0a — Wake on LAN (WOL) support compliant with PC98, PC99, SecureOn, and OnNow, including directed packets, Magic Packet, VLAN packets, ARP packets, pattern match packets, and Phy status change — Clkrun function for PCI Mobile Design Guide System Diagram PCI Bus 10/100 Twisted Pair DP83815 Isolation BIOS ROM EEPROM (optional) (optional) Magic Packet is a trademark of Advanced Micro Devices, Inc. © 2005 National Semiconductor Corporation www.national.com DP83815 10/100 Mb/s Integrated PCI Ethernet Media Access Controller and Physical Layer (MacPhyter™) September 2005 3.12.2 MII Serial Management . . . . . . . . . . . . . . . . . . . . 29 1.0 Connection Diagram . . . . . . . . . . . . . . . . . . 4 3.12.3 MII Serial Management Access . . . . . . . . . . . . . 30 1.1 144 LQFP Package (VNG) . . . . . . . . . . . . 4 3.12.4 Serial Management Access Protocol . . . . . . . . . 30 1.2 160 pin LBGA Package (UJB) . . . . . . . . . . 5 3.12.5 Nibble-wide MII Data Interface . . . . . . . . . . . . . . 30 2.0 Pin Description . . . . . . . . . . . . . . . . . . . . . . 6 3.12.6 Collision Detection . . . . . . . . . . . . . . . . . . . . . . . 31 3.0 Functional Description . . . . . . . . . . . . . . . 13 3.12.7 Carrier Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.1 MAC/BIU . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.0 Register Set . . . . . . . . . . . . . . . . . . . . . . . . 32 3.1.1 PCI Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 Configuration Registers . . . . . . . . . . . . . . 32 3.1.2 Tx MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1.3 Rx MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Buffer Management . . . . . . . . . . . . . . . . . 15 3.2.1 3.2.2 3.2.3 3.2.4 Interface Definitions . . . . . . . . . . . . . . . . . 16 3.3.1 3.3.2 3.3.3 3.3.4 3.4 Physical Layer . . . . . . . . . . . . . . . . . . . . . 18 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.4.6 3.5 3.6 3.7 3.8 3.9 PCI System Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Boot PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Auto-Negotiation Register Control . . . . . . . . . . . . . 18 Auto-Negotiation Parallel Detection . . . . . . . . . . . . 18 Auto-Negotiation Restart . . . . . . . . . . . . . . . . . . . . 19 Enabling Auto-Negotiation via Software . . . . . . . . 19 Auto-Negotiation Complete Time . . . . . . . . . . . . . . 19 LED Interfaces . . . . . . . . . . . . . . . . . . . . . Half Duplex vs. Full Duplex . . . . . . . . . . . Phy Loopback . . . . . . . . . . . . . . . . . . . . . Status Information . . . . . . . . . . . . . . . . . . 100BASE-TX TRANSMITTER . . . . . . . . . 4.2 19 20 20 20 20 Code-group Encoding and Injection . . . . . . . . . . . 21 Scrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 NRZ to NRZI Encoder . . . . . . . . . . . . . . . . . . . . . . 22 Binary to MLT-3 Convertor / Common Driver . . . . 22 bs 3.9.1 3.9.2 3.9.3 3.9.4 te 3.3 Tx Buffer Manager . . . . . . . . . . . . . . . . . . . . . . . . . 15 Rx Buffer Manager . . . . . . . . . . . . . . . . . . . . . . . . . 15 Packet Recognition . . . . . . . . . . . . . . . . . . . . . . . . 15 MIB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.10 100BASE-TX Receiver . . . . . . . . . . . . . . 23 O 3.10.1 Input and Base Line Wander Compensation . . . . 23 3.10.2 Signal Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.10.3 Digital Adaptive Equalization . . . . . . . . . . . . . . . . 25 3.10.4 Line Quality Monitor . . . . . . . . . . . . . . . . . . . . . . . 26 3.10.5 MLT-3 to NRZI Decoder . . . . . . . . . . . . . . . . . . . . 26 3.10.6 Clock Recovery Module . . . . . . . . . . . . . . . . . . . . 27 3.10.7 NRZI to NRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.10.8 Serial to Parallel . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.10.9 De-scrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.10.10 Code-group Alignment . . . . . . . . . . . . . . . . . . . . 27 3.10.11 4B/5B Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.10.12 100BASE-TX Link Integrity Monitor . . . . . . . . . . 27 3.10.13 Bad SSD Detection . . . . . . . . . . . . . . . . . . . . . . 27 3.11 10BASE-T Transceiver Module . . . . . . . . 28 3.11.1 Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . 28 3.11.2 Smart Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.11.3 Collision Detection . . . . . . . . . . . . . . . . . . . . . . . . 28 3.11.4 Normal Link Pulse Detection/Generation . . . . . . . 28 3.11.5 Jabber Function . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.11.6 Automatic Link Polarity Detection . . . . . . . . . . . . . 29 3.11.7 10BASE-T Internal Loopback . . . . . . . . . . . . . . . . 29 3.11.8 Transmit and Receive Filtering . . . . . . . . . . . . . . . 29 3.11.9 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.11.10 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.11.11 Far End Fault Indication . . . . . . . . . . . . . . . . . . . 29 4.3 32 33 34 35 35 36 36 37 37 38 38 39 Operational Registers . . . . . . . . . . . . . . . 40 4.2.1 Command Register . . . . . . . . . . . . . . . . . . . . . . . . 4.2.2 Configuration and Media Status Register . . . . . . . 4.2.3 EEPROM Access Register . . . . . . . . . . . . . . . . . . 4.2.4 EEPROM Map . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.5 PCI Test Control Register . . . . . . . . . . . . . . . . . . . 4.2.6 Interrupt Status Register . . . . . . . . . . . . . . . . . . . . 4.2.7 Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . 4.2.8 Interrupt Enable Register . . . . . . . . . . . . . . . . . . . 4.2.9 Transmit Descriptor Pointer Register . . . . . . . . . . 4.2.10 Transmit Configuration Register . . . . . . . . . . . . . 4.2.11 Receive Descriptor Pointer Register . . . . . . . . . . 4.2.12 Receive Configuration Register . . . . . . . . . . . . . 4.2.13 CLKRUN Control/Status Register . . . . . . . . . . . . 4.2.14 Wake Command/Status Register . . . . . . . . . . . . 4.2.15 Pause Control/Status Register . . . . . . . . . . . . . . 4.2.16 Receive Filter/Match Control Register . . . . . . . . 4.2.17 Receive Filter/Match Data Register . . . . . . . . . . 4.2.18 Receive Filter Logic . . . . . . . . . . . . . . . . . . . . . . 4.2.19 Boot ROM Address Register . . . . . . . . . . . . . . . . 4.2.20 Boot ROM Data Register . . . . . . . . . . . . . . . . . . 4.2.21 Silicon Revision Register . . . . . . . . . . . . . . . . . . 4.2.22 Management Information Base Control Register 4.2.23 Management Information Base Registers . . . . . . ol e 3.2 4.1.1 Configuration Identification Register . . . . . . . . . . . 4.1.2 Configuration Command and Status Register . . . 4.1.3 Configuration Revision ID Register . . . . . . . . . . . 4.1.4 Configuration Latency Timer Register . . . . . . . . . 4.1.5 Configuration I/O Base Address Register . . . . . . . 4.1.6 Configuration Memory Address Register . . . . . . . 4.1.7 Configuration Subsystem Identification Register . 4.1.8 Boot ROM Configuration Register . . . . . . . . . . . . 4.1.9 Capabilities Pointer Register . . . . . . . . . . . . . . . . 4.1.10 Configuration Interrupt Select Register . . . . . . . . 4.1.11 Power Management Capabilities Register . . . . . 4.1.12 Power Management Control and Status Register 41 42 44 44 45 46 47 49 49 50 51 52 53 55 57 58 59 60 64 64 64 65 66 Internal PHY Registers . . . . . . . . . . . . . . . 67 4.3.1 Basic Mode Control Register . . . . . . . . . . . . . . . . 4.3.2 Basic Mode Status Register . . . . . . . . . . . . . . . . . 4.3.3 PHY Identifier Register #1 . . . . . . . . . . . . . . . . . . 4.3.4 PHY Identifier Register #2 . . . . . . . . . . . . . . . . . . 4.3.5 Auto-Negotiation Advertisement Register . . . . . . 4.3.6 Auto-Negotiation Link Partner Ability Register . . . 4.3.7 Auto-Negotiate Expansion Register . . . . . . . . . . . 4.3.8 Auto-Negotiation Next Page Transmit Register . . 4.3.9 PHY Status Register . . . . . . . . . . . . . . . . . . . . . . . 4.3.10 MII Interrupt Control Register . . . . . . . . . . . . . . . 4.3.11 MII Interrupt Status and Misc. Control Register . 4.3.12 False Carrier Sense Counter Register . . . . . . . . 4.3.13 Receiver Error Counter Register . . . . . . . . . . . . . 4.3.14 100 Mb/s PCS Configuration and Status Register 4.3.15 PHY Control Register . . . . . . . . . . . . . . . . . . . . . 4.3.16 10BASE-T Status/Control Register . . . . . . . . . . . 67 68 69 69 69 70 71 71 72 74 74 75 75 75 76 77 4.4 Recommended Registers Configuration . 78 5.0 Buffer Management . . . . . . . . . . . . . . . . . . 79 3.12 802.3u MII . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . 79 3.12.1 MII Access Configuration . . . . . . . . . . . . . . . . . . . 29 5.1.1 Descriptor Format . . . . . . . . . . . . . . . . . . . . . . . . . 79 2 www.national.com DP83815 Table of Contents 5.2 6.6 Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . 91 6.6.1 Entering Sleep Mode . . . . . . . . . . . . . . . . . . . . . . 91 6.6.2 Exiting Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . 91 Transmit Architecture . . . . . . . . . . . . . . . 83 6.7 Pin Configuration for Power Management 91 7.0 DC and AC Specifications . . . . . . . . . . . . . 92 5.3 Receive Architecture . . . . . . . . . . . . . . . . 86 7.1 DC Specifications . . . . . . . . . . . . . . . . . . . 92 5.3.1 Receive State Machine . . . . . . . . . . . . . . . . . . . . . 86 7.2 AC Specifications . . . . . . . . . . . . . . . . . . . 93 5.3.2 Receive Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . 88 7.2.1 PCI Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . 93 6.0 Power Management and Wake-On-LAN. . 89 7.2.2 X1 Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 93 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . 89 7.2.3 Power On Reset (PCI Active) . . . . . . . . . . . . . . . . 94 6.2 Definitions (for this document only) . . . . . 89 7.2.4 Non Power On Reset . . . . . . . . . . . . . . . . . . . . . . 94 7.2.5 POR PCI Inactive . . . . . . . . . . . . . . . . . . . . . . . . . 95 6.3 Packet Filtering . . . . . . . . . . . . . . . . . . . . 89 7.2.6 PCI Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 6.4 Power Management . . . . . . . . . . . . . . . . 89 5.2.1 Transmit State Machine . . . . . . . . . . . . . . . . . . . . . 83 5.2.2 Transmit Data Flow . . . . . . . . . . . . . . . . . . . . . . . . 85 6.5 7.2.7 EEPROM Auto-Load . . . . . . . . . . . . . . . . . . . . . 7.2.8 Boot PROM/FLASH . . . . . . . . . . . . . . . . . . . . . . 7.2.9 100BASE-TX Transmit . . . . . . . . . . . . . . . . . . . 7.2.10 10BASE-T Transmit End of Packet . . . . . . . . . 7.2.11 10 Mb/s Jabber Timing . . . . . . . . . . . . . . . . . . 7.2.12 10BASE-T Normal Link Pulse . . . . . . . . . . . . . 7.2.13 Auto-Negotiation Fast Link Pulse (FLP) . . . . . . 7.2.14 Media Independent Interface (MII) . . . . . . . . . . D0 State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 D1 State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 D2 State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 D3hot State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 D3cold State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Wake-On-LAN (WOL) Mode . . . . . . . . . . 90 6.5.1 Entering WOL Mode . . . . . . . . . . . . . . . . . . . . . . . 90 6.5.2 Wake Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 te 6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 101 102 103 104 104 105 105 106 List of Figures DP83815 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MAC/BIU Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ethernet Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Physical Layer Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LED Loading Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100BASE-TX Transmit Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Binary to MLT-3 conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 M/bs Receive Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100BASE-TX BLW Event Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EIA/TIA Attenuation vs. Frequency for 0, 50, 100, 130 & 150 meters of CAT V cable . . . . . . . MLT-3 Signal Measured at AII after 0 meters of CAT V cable. . . . . . . . . . . . . . . . . . . . . . . . . . MLT-3 Signal Measured at AII after 50 meters of CAT V cable. . . . . . . . . . . . . . . . . . . . . . . . . MLT-3 Signal Measured at AII after 100 meters of CAT V cable. . . . . . . . . . . . . . . . . . . . . . . . 10BASE-T Twisted Pair Smart Squelch Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical MDC/MDIO Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical MDC/MDIO Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pattern Buffer Memory - 180h words (word = 18bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hash Table Memory - 40h bytes addressed on word boundaries . . . . . . . . . . . . . . . . . . . . . . . Single Descriptor Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiple Descriptor Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . List and Ring Descriptor Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3-1 Table 3-2 Table 4-1 Table 4-2 Table 4-3 Table 5-1 Table 5-2 Table 5-3 Table 5-4 Table 5-5 Table 5-6 Table 6-1 Table 6-2 4B5B Code-Group Encoding/Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Typical MDIO Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Configuration Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Operational Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 MIB Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 DP83815 Descriptor Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 cmdsts Common Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Transmit Status Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 Receive Status Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 Transmit State Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 Receive State Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 Power Management Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 PM Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 O bs ol e Figure 3-1 Figure 3-2 Figure 3-3 Figure 3-4 Figure 3-5 Figure 3-6 Figure 3-7 Figure 3-8 Figure 3-9 Figure 3-10 Figure 3-11 Figure 3-12 Figure 3-13 Figure 3-14 Figure 3-15 Figure 3-16 Figure 4-1 Figure 4-2 Figure 5-1 Figure 5-2 Figure 5-3 Figure 5-4 Figure 5-5 Figure 5-6 Figure 5-7 13 14 16 17 19 21 22 24 25 26 26 26 26 28 30 31 61 63 81 82 82 83 84 86 88 List of Tables 3 www.national.com DP83815 6.5.3 Exiting WOL Mode . . . . . . . . . . . . . . . . . . . . . . . . 91 5.1.2 Single Descriptor Packets . . . . . . . . . . . . . . . . . . . 81 5.1.3 Multiple Descriptor Packets . . . . . . . . . . . . . . . . . . 82 5.1.4 Descriptor Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 DP83815 1.0 Connection Diagram 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 FXVDD FXVSS NC PHYVDD2 PHYVSS2 TXCLK TXEN CRS COL/MA16 VDDIO3 VSSIO3 TXD3/MA15 TXD2/MA14 TXD1/MA13 TXD0/MA12 PHYVDD1 PHYVSS1 VDDIO2 X2 X1 VSSIO2 RXDV/MA11 RXER/MA10 RXOE RXD3/MA9 RXD2/MA8 RXD1/MA7 VDDIO1 VSSIO1 RXD0/MA6 RXCLK MDC MDIO MA5 MA4/EECLK MA3/EEDI 1.1 144 LQFP Package (VNG) 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 MA2/LED100N MA1/LED10N MA0/LEDACTN MD7 MD6 MD5 MD4/EEDO VDDIO5 VSSIO5 MD3 MD2 MD1/CFGDISN MD0 MWRN MRDN MCSN EESEL RESERVED SUBGND3 MACVDD2 MACVSS2 PWRGOOD 3VAUX AD0 AD1 AD2 AD3 PCIVDD5 AD4 AD5 PCIVSS5 AD6 AD7 CBEN0 AD8 AD9 te Pin1 Identification ol e 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 DP83815 AD25 AD24 CBEN3 IDSEL PCIVSS2 AD23 AD22 PCIVDD2 AD21 AD20 AD19 VSSIO4 VDDIO4 AD18 AD17 AD16 CBEN2 PCIVSS3 FRAMEN IRDYN TRDYN PCIVDD3 DEVSELN STOPN PERRN SERRN PAR CBEN1 AD15 AD14 PCIVSS4 AD13 AD12 AD11 PCIVDD4 AD10 O 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 bs SUBGND1 RXAVSS1 RXAVDD1 VREF RESERVED NC NC RXAVSS2 TPRDM TPRDP RXAVDD2 NC SUBGND2 RESERVED TXDVSS TXIOVSS1 TPTDM TPTDP TXIOVSS2 TXDVDD MACVSS1 MACVDD1 PMEN/CLKRUNN PCICLK INTAN RSTN GNTN REQN PCIVSS1 AD31 AD30 AD29 PCIVDD1 AD28 AD27 AD26 Order Number DP83815DVNG See NS Package Number VNG144A 4 www.national.com DP83815 1.0 Connection Diagram (Continued) 14 13 12 11 10 9 8 7 6 5 4 3 1 Pin A1 Identification (Marked on Top) 2 1.2 160 pin LBGA Package (UJB) A B te C D E G H J K L M bs N ol e F O P Top View Order Number DP83815DUJB See NS Package Number UJB160A 5 www.national.com DP83815 2.0 Pin Description PCI Bus Interface CBEN[3-0] LBGA Pin No(s) 66, 67, 68, 70, 71, 72, 73, 74, 78, 79, 81, 82, 83, 86, 87, 88, 101, 102, 104, 105, 106, 108, 109, 110, 112, 113, 115, 116, 118, 119, 120, 121 K3, K2, K4, L3, L2, M1, N3, P3, L4 N5, M5, L5, N6, L6, N7, P7, N10, L10, M11, N11, P12, N12, M13, M14, L12, L14, K13, K14, K11, J13, J14, J12 I/O Address and Data: Multiplexed address and data bus. As a bus master, the DP83815 will drive address during the first bus phase. During subsequent phases, the DP83815 will either read or write data expecting the target to increment its address pointer. As a bus target, the DP83815 will decode each address on the bus and respond if it is the target being addressed. 75, 89, 100, 111 N4, L7, M10, L13 I/O Bus Command/Byte Enable: During the address phase these signals define the “bus command” or the type of bus transaction that will take place. During the data phase these pins indicate which byte lanes contain valid data. CBEN[0] applies to byte 0 (bits 7-0) and CBEN[3] applies to byte 3 (bits 31-24) in the Little Endian Mode. In Big Endian Mode, CBEN[3] applies to byte 0 (bits 31-24) and CBEN[0] applies to byte 3 (bits 7-0). 60 DEVSELN 95 FRAMEN 91 63 O GNTN Description H4 I Clock: This PCI Bus clock provides timing for all bus phases. The rising edge defines the start of each phase. The clock frequency ranges from 0 to 33 MHz. P9 I/O Device Select: As a bus master, the DP83815 samples this signal to insure that the destination address for the data transfer is recognized by a PCI target. As a target, the DP83815 asserts this signal low when it recognizes its address after FRAMEN is asserted. M7 I/O Frame: As a bus master, this signal is asserted low to indicate the beginning and duration of a bus transaction. Data transfer takes place when this signal is asserted. It is de-asserted before the transaction is in its final phase. As a target, the device monitors this signal before decoding the address to check if the current transaction is addressed to it. bs PCICLK Dir te AD[31-0] LQFP Pin No(s) ol e Symbol J2 I Grant: This signal is asserted low to indicate to the DP83815 that it has been granted ownership of the bus by the central arbiter. This input is used when the DP83815 is acting as a bus master. IDSEL 76 M4 I Initialization Device Select: This pin is sampled by the DP83815 to identify when configuration read and write accesses are intended for it. INTAN 61 J1 O Interrupt A: This signal is asserted low when an interrupt condition occurs as defined in the Interrupt Status Register, Interrupt Mask, and Interrupt Enable registers. IRDYN 92 P8 I/O Initiator Ready: As a bus master, this signal will be asserted low when the DP83815 is ready to complete the current data phase transaction. This signal is used in conjunction with the TRYDN signal. Data transaction takes place at the rising edge of PCICLK when both IRDYN and TRDYN are asserted low. As a target, this signal indicates that the master has put the data on the bus. PAR 99 P10 I/O Parity: This signal indicates even parity across AD[31-0] and CBEN[3-0] including the PAR pin. As a master, PAR is asserted during address and write data phases. As a target, PAR is asserted during read data phases. 6 www.national.com DP83815 2.0 Pin Description (Continued) PCI Bus Interface LBGA Pin No(s) Dir Description PERRN 97 N9 I/O Parity Error: The DP83815 as a master or target will assert this signal low to indicate a parity error on any incoming data (except for special cycles). As a bus master, it will monitor this signal on all write operations (except for special cycles). REQN 64 J4 O Request: The DP83815 will assert this signal low to request ownership of the bus from the central arbiter. RSTN 62 J3 I Reset: When this signal is asserted all PCI bus outputs of DP83815 will be tri-stated and the device will be put into a known state. SERRN 98 L9 I/O System Error: This signal is asserted low by DP83815 during address parity errors and system errors if enabled. STOPN 96 M9 I/O Stop: This signal is asserted low by the target device to request the master device to stop the current transaction. TRDYN 93 N8 I/O Target Ready: As a master, this signal indicates that the target is ready for the data during write operation and with the data during read operation. As a target, this signal will be asserted low when the (target) device is ready to complete the current data phase transaction. This signal is used in conjunction with the IRDYN signal. Data transaction takes place at the rising edge of PCICLK when both IRDYN and TRDYN are asserted low. PMEN/ 59 ol e CLKRUNN te LQFP Pin No(s) Symbol H2 I/O Power Management Event/Clock Run Function: This pin is a dual function pin. The function of this pin is determined by the CLKRUN_EN bit 0 of the CLKRUN Control and Status register (CCSR). Default operation of this pin is PMEN. Power Management Event: This signal is asserted low by DP83815 to indicate that a power management event has occurred. For pin connection please refer to Section 6.7. 3VAUX bs Clock Run Function: In this mode, this pin is used to indicate when the PCICLK will be stopped. 122 J11 I PCI Auxiliary Voltage Sense: This pin is used to sense the presence of a 3.3V auxiliary supply in order to define the PME Support available. For pin connection please refer to Section 6.7. This pin has an internal weak pull down. 123 O PWRGOOD H13 I PCI bus power good: Connected to PCI bus 3.3V power (not 3.3Vaux), this pin is used to sense the presence of PCI bus power. This pin has an internal weak pull down. 7 www.national.com DP83815 2.0 Pin Description (Continued) Media Independent Interface (MII) LQFP Pin No(s) LBGA Pin No(s) Dir COL 28 C5 I Collision Detect: The COL signal is asserted high asynchronously by the external PMD upon detection of a collision on the medium. It will remain asserted as long as the collision condition persists. CRS 29 B5 I Carrier Sense: This signal is asserted high asynchronously by the external PMD upon detection of a non-idle medium. MDC 5 A11 O Management Data Clock: Clock signal with a maximum rate of 2.5 MHz used to transfer management data for the external PMD on the MDIO pin. MDIO 4 C11 I/O Management Data I/O: Bidirectional signal used to transfer management information for the external PMD. (See Section 3.12.4 for details on connections when MII is used.) RXCLK 6 D11 I Receive Clock: A continuous clock, sourced by an external PMD device, that is recovered from the incoming data. During 100 Mb/s operation RXCLK is 25 MHz and during 10 Mb/s this is 2.5 MHz. 12, 11, 10, 7 A9, B9, D10, B10 I Receive Data: Sourced from an external PMD, that contains data aligned on nibble boundaries and are driven synchronous to RXCLK. RXD[3] is the most significant bit and RXD[0] is the least significant bit. O BIOS ROM Address: During external BIOS ROM access, these signals become part of the ROM address. I Receive Data Valid: Indicates that the external PMD is presenting recovered and decoded nibbles on the RXD signals, and that RXCLK is synchronous to the recovered data in 100 Mb/s operation. This signal will encompass the frame, starting with the Start-of-Frame delimiter (JK) and excluding any End-of-Frame delimiter (TR). 15 B8 bs RXDV/MA11 te RXD3/MA9, RXD2/MA8, RXD1/MA7, RXD0/MA6 Description ol e Symbol O RXER/MA10 14 D9 I O O BIOS ROM Address: During external BIOS ROM access, this signal becomes part of the ROM address. Receive Error: Asserted high synchronously by the external PMD whenever it detects a media error and RXDV is asserted in 100 Mb/s operation. BIOS ROM Address: During external BIOS ROM access, this signal becomes part of the ROM address. RXOE 13 C9 O Receive Output Enable: Used to disable an external PMD while the BIOS ROM is being accessed. TXCLK 31 A4 I Transmit Clock: A continuous clock that is sourced by the external PMD. During 100 Mb/s operation this is 25 MHz +/- 100 ppm. During 10 Mb/s operation this clock is 2.5 MHz +/- 100 ppm. 25, 24, 23, 22 B6, C6, A6, D7 O Transmit Data: Signals which are driven synchronous to the TXCLK for transmission to the external PMD. TXD[3] is the most significant bit and TXD[0] is the least significant bit. TXD3/MA15, TXD2/MA14, TXD1/MA13, TXD0/MA12 O TXEN 30 D5 O BIOS ROM Address: During external BIOS ROM access, these signals become part of the ROM address. Transmit Enable: This signal is synchronous to TXCLK and provides precise framing for data carried on TXD[3-0] for the external PMD. It is asserted when TXD[3-0] contains valid data to be transmitted. Note: MII is normally tri-stated, unless enabled by CFG:EXT_PHY. See Section 4.2.2. 8 www.national.com DP83815 2.0 Pin Description (Continued) 100BASE-TX/10BASE-T Interface Symbol LQFP Pin No(s) LBGA Pin No(s) Dir Description TPTDP, TPTDM 54, 53 G1, F1 A-O Transmit Data: Differential common output driver. This differential common output is configurable to either 10BASE-T or 100BASE-TX signaling: 10BASE-T: Transmission of Manchester encoded 10BASE-T packet data as well as Link Pulses (including Fast Link Pulses for AutoNegotiation purposes). 100BASE-TX: Transmission of ANSI X3T12 compliant MLT-3 data. TPRDP, TPRDM 46, 45 D1, C1 te The DP83815 will automatically configure this common output driver for the proper signal type as a result of either forced configuration or Auto-Negotiation. A-I Receive Data: Differential common input buffer. This differential common input can be configured to accept either 100BASE-TX or 10BASE-T signaling: 10BASE-T: Reception of Manchester encoded 10BASE-T packet data as well as normal Link Pulses and Fast Link Pulses for AutoNegotiation purposes. ol e 100BASE-TX: Reception of ANSI X3T12 compliant scrambled MLT-3 data. The DP83815 will automatically configure this common input buffer to accept the proper signal type as a result of either forced configuration or Auto-Negotiation. bs BIOS ROM/Flash Interface LQFP Pin No(s) LBGA Pin No(s) Dir 129 G13 O BIOS ROM/Flash Chip Select: During a BIOS ROM/Flash access, this signal is used to select the ROM device. MD7, MD6, MD5, MD4/EEDO, MD3, MD2, MD1/CFGDISN, MD0 141, 140, 139, 138, 135, 134, 133, 132 D13, D12, D14, E11, E14, F11, F13, F12 I/O BIOS ROM/Flash Data Bus: During a BIOS ROM/Flash access these signals are used to transfer data to or from the ROM/Flash device. MA5, MA4/EECLK, MA3/EEDI, MA2/LED100LNK, MA1/LED10LNK, MA0/LEDACT 3, 2, 1, 144, 143, 142 B11, A12, B12, C13, C12, C14 O BIOS ROM/Flash Address: During a BIOS ROM/Flash access, these signals are used to drive the ROM/Flash address. MWRN 131 F14 O BIOS ROM/Flash Write: During a BIOS ROM/Flash access, this signal is used to enable data to be written to the Flash device. MRDN 130 G11 O BIOS ROM/Flash Read: During a BIOS ROM/Flash access, this signal is used to enable data to be read from the Flash device. Symbol O MCSN Description MD[5:0] pins have internal weak pull ups. MD6 and MD7 pins have internal weak pull downs. Note: DP83815 supports NM27LV010 for the BIOS ROM interface device. 9 www.national.com DP83815 2.0 Pin Description (Continued) Clock Interface LBGA Pin No(s) Dir Description X1 17 D8 I Crystal/Oscillator Input: This pin is the primary clock reference input for the DP83815 and must be connected to a 25 MHz 0.005% (50ppm) clock source. The DP83815 device supports either an external crystal resonator connected across pins X1 and X2, or an external CMOS-level oscillator source connected to pin X1 only. X2 18 C7 O Crystal Output: This pin is used in conjunction with the X1 pin to connect to an external 25 MHz crystal resonator device. This pin must be left unconnected if an external CMOS oscillator clock source is utilized. For more information see the definition for pin X1. Symbol LQFP Pin No(s) LBGA Pin No(s) Dir LEDACTN/MA0 142 C14 O TX/RX Activity: This pin is an output indicating transmit/receive activity. This pin is driven low to indicate active transmission or reception, and can be used to drive a low current LED (