Product
Folder
Sample &
Buy
Support &
Community
Tools &
Software
Technical
Documents
DP83816
SNLS164E – SEPTEMBER 2005 – REVISED DECEMBER 2015
DP83816 10/100 Mb/s Integrated PCI Ethernet Media Access Controller and Physical Layer
(MacPhyter-II™)
1 Device Overview
1.1
Features
1
• IEEE 802.3 Compliant, PCI V2.2 Media Access
Controller (MAC) and Bus Interface Unit (BIU)
Supports Traditional Data Rates of 10 Mb/s
Ethernet and 100 Mb/s Fast Ethernet (Through
Internal PHY)
• Bus Master – Burst Sizes of up to 128 Dwords
(512 Bytes)
• BIU Compliant With PC 97 and PC 98 Hardware
Design Guides, PC 99 Hardware Design Guide
Draft, ACPI v1.0, PCI Power Management
Specification v1.1, OnNow Device Class Power
Management Reference Specification – Network
Device Class v1.0a
• Wake on LAN (WoL) Support Compliant With
PC98, PC99, SecureOn, and OnNow, Including
Directed Packets, Magic Packet™ VLAN Packets,
ARP Packets, Pattern Match Packets, and PHY
Status Change
• Clkrun Function for PCI Mobile Design Guide
• Virtual LAN (VLAN) and Long Frame Support
• Support for IEEE 802.3× Full-Duplex Flow Control
• Extremely Flexible Rx Packet Filtration Including:
Single Address Perfect Filter With MSb Masking,
Broadcast, 512 Entry Multicast and Unicast Hash
Table, Deep Packet Pattern Matching for up to
Four Unique Patterns
• Statistics Gathered for Support of RFC 1213
1.2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Applications
PC Motherboards
PCI Network Interface Cards
1.3
•
(MIB II), RFC 1398 (Ether-Like MIB), IEEE 802.3
LME, Reducing CPU Overhead for Management
Internal 2KB Transmit and 2KB Receive Data
FIFOs
Serial EEPROM Port With Auto-Load of
Configuration Data From EEPROM at Power On
Flash or PROM Interface for Remote Boot Support
Fully Integrated IEEE 802.3 3.3-V CMOS Physical
Layer
IEEE 802.3 10BASE-T Transceiver With Integrated
Filters IEEE 802.3u 100BASE-TX Transceiver
Fully integrated ANSI X3.263 Compliant TP-PMD
Physical Sublayer With Adaptive Equalization and
Baseline Wander Compensation
IEEE 802.3u Auto-Negotiation – Advertised
Features Configurable Through EEPROM
Full-Duplex Support for 10- and 100-Mb/s Data
Rates
Single 25-MHz Reference Clock
144-pin LQFP Package
Low-Power 3.3-V CMOS Design With Typical
Consumption of 383 mW Operating, 297 mW
During WoL, and 53 mW During Sleep Mode
IEEE 802.3u MII for Connecting Alternative
External Physical Layer Devices
3.3-V Signaling With 5-V Tolerant I/O
•
Embedded Systems
Description
The DP83816 device is a single-chip 10/100 Mb/s ethernet controller for the PCI bus. It is targeted at lowcost, high-volume PC motherboards, adapter cards, and embedded systems. The DP83816 device fully
implements the V2.2 33-MHz PCI bus interface for host communications with power management support.
Packet descriptors and data are transferred via bus-mastering, reducing the burden on the host CPU. The
DP83816 device can support full-duplex 10/100 Mb/s transmission and reception with minimum interframe
gap.
Device Information (1)
PART NUMBER
DP83816
(1)
PACKAGE
LQFP (144)
BODY SIZE (NOM)
20.00 mm × 20.00 mm
For all available packages, see the orderable addendum at the end of the data sheet.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DP83816
SNLS164E – SEPTEMBER 2005 – REVISED DECEMBER 2015
1.4
www.ti.com
System Diagram
PCI Bus
10/100 Twisted Pair
DP83816
Isolation
BIOS ROM EEPROM
(optional) (optional)
2
Device Overview
Copyright © 2005–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DP83816
DP83816
www.ti.com
SNLS164E – SEPTEMBER 2005 – REVISED DECEMBER 2015
Table of Contents
1
2
3
Device Overview ......................................... 1
5.4
Device Functional Modes
1.1
Features .............................................. 1
5.5
Programming ........................................ 34
1.2
Applications ........................................... 1
5.6
Register Block ....................................... 65
1.3
Description ............................................ 1
1.4
System Diagram ...................................... 2
6.1
Application Information
Revision History ......................................... 3
Pin Configuration and Functions ..................... 4
6.2
Typical Application ................................. 100
3.1
4
7
8
31
Application and Implementation ................... 100
............................
100
Power Supply Recommendations ................. 106
Layout ................................................... 107
Specifications ........................................... 11
8.1
Layout Guidelines .................................. 107
4.1
Absolute Maximum Ratings ......................... 11
8.2
Layout Example .................................... 110
4.2
ESD Ratings
4.3
Recommended Operating Conditions ............... 11
9.1
Documentation Support ............................ 111
4.4
Thermal Information ................................. 11
9.2
Trademarks ........................................ 111
4.5
Electrical Characteristics – DC Specifications ...... 12
9.3
Electrostatic Discharge Caution
9.4
Glossary............................................ 111
........................................
...........................
Detailed Description ...................................
5.1
Overview ............................................
5.2
Functional Block Diagram ...........................
5.3
Feature Description .................................
4.6
5
Pin Attributes ......................................... 6
6
...........................
AC Timing Requirements
11
12
23
23
23
9
Device and Documentation Support
.............
...................
111
111
10 Mechanical Packaging and Orderable
Information ............................................. 111
10.1
Packaging Information ............................. 111
24
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (September 2005) to Revision E
•
•
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section. ......................................... 1
Changed the Thermal Information table values ................................................................................. 11
Revision History
Copyright © 2005–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DP83816
3
DP83816
SNLS164E – SEPTEMBER 2005 – REVISED DECEMBER 2015
www.ti.com
3 Pin Configuration and Functions
The DP83816 pins are classified into the following interface categories (pins of each interface are
described in Section 3.1.
• PCI bus interface
• Media independent interface
• 10/100 Mb/s PMD interface
• BIOS ROM and flash interface
• Clock interface
• LED Interface
• Serial EEPROM interface
• Special connections
• Power supply pins
All DP83816 signal pins are I/O cells regardless of the particular use. The tables in Section 3.1 define the
functionality of the I/O cells for each pin.
4
Pin Configuration and Functions
Copyright © 2005–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DP83816
DP83816
www.ti.com
SNLS164E – SEPTEMBER 2005 – REVISED DECEMBER 2015
AD9
AD4
109
PCIVDD
116
CBEN0
AD3
117
AD8
AD2
118
110
AD1
119
AD7
AD0
120
111
3VAUX
121
AD6
PWRGOOD
122
112
NC
123
113
NC
124
AD5
NC
125
VSS
NU
126
114
EESEL
127
115
MCSN
128
MD2
134
MRDN
MD3
135
129
VSS
136
MWRN
AUXVDD
137
130
MD4/EEDO
138
131
MD5
139
MD1/CFGDISN
MD6
140
MD0
MD7
141
132
MA0/LEDACT
142
133
MA2/LED100LNK
MA1/LED10LNK
144
143
PGE Package
144-Pin LQFP
Top View
83
AD19
AUXVDD
27
82
AD20
COL
28
81
AD21
CRS
29
80
PCIVDD
TXEN
30
79
AD22
TXCLK
31
78
AD23
VSS
32
77
VSS
AUXVDD
33
76
IDSEL
NC
34
75
CBEN3
VSS
35
74
AD24
NC
36
73
AD25
VSS
72
26
AD26
NC
VSS
71
84
AD27
25
70
NC
TXD3/MA15
AD28
85
69
24
68
AD18
TXD2/MA1
AD29
AD17
86
PCIVDD
87
23
67
22
TXD1/MA1
AD30
TXD0/MA12
66
AD16
AD31
88
65
21
VSS
CBEN2
AUXVDD
64
89
REQN
20
63
VSS
VSS
GNTN
90
62
19
RSTN
FRAMEN
C1
61
IRDYN
91
INTAN
92
18
60
17
X2
PCICLK
X1
59
TRDYN
PMEN/CLKRUNN
93
58
16
AUXVDD
PCIVDD
VSS
57
94
VSS
15
56
DEVSELN
RXDV/MA11
AUXVDD
95
55
14
VSS
STOPN
RXER/MA10
54
96
TPTDP
13
53
PERRN
RXOE
TPTDM
97
52
12
VSS
SERRN
RXD3/MA9
51
98
50
11
NU
PAR
RXD2/MA8
VSS
99
49
10
48
CBEN1
RXD1/MA7
REGEN
AD15
100
47
101
9
IAUXVDD
8
46
VSS
AUXVDD
TPRDP
AD14
45
102
TPRDM
7
44
VSS
RXD0/MA6
VSS
103
43
6
NC
AD13
RXCLK
42
AD12
104
NC
105
5
41
4
MDC
NU
MDIO
40
AD11
39
106
VREF
3
IAUXVDD
PCIVDD
MA5
38
107
37
108
2
NC
1
VSS
MA3/EEDI
MA4/EECLK
AD10
NC – No internal connection
NU – Make no external connection
Pin Configuration and Functions
Copyright © 2005–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DP83816
5
DP83816
SNLS164E – SEPTEMBER 2005 – REVISED DECEMBER 2015
3.1
www.ti.com
Pin Attributes
Table 3-1. Pin Functions, PCI Bus Interface
PIN
NAME
NO.
3VAUX
122
TYPE (1)
DESCRIPTION
I, PD
PCI Auxiliary Voltage Sense: This pin is used to sense the presence of a 3.3-V auxiliary supply
to define the PME support available. For pin connection, see Section 6.2.1.4.
I/O
Address and Data: Multiplexed address and data bus. As a bus master, the DP83816 device
drives address during the first bus phase. During subsequent phases, the DP83816 device either
reads or writes data, expecting the target to increment its address pointer. As a bus target, the
DP83816 device decodes each address on the bus and responds if it is the target being
addressed.
Bus Command and Byte Enable: During the address phase, these signals define the bus
command or the type of bus transaction that takes place. During the data phase these pins
indicate which byte lanes contain valid data. CBEN[0] applies to byte 0 (bits 7–0) and CBEN[3]
applies to byte 3 (bits 31–24) in the little-endian mode. In big-endian mode, CBEN[3] applies to
byte 0 (bits 31–24) and CBEN[0] applies to byte 3 (bits 7–0).
AD[31–0]
66, 67, 68,
70. 71, 72,
73, 74, 78,
79, 81, 82,
83, 86, 87,
88,101,
102, 104,
105, 106,
108, 109,
110, 112,
113, 115,
116, 118,
119, 120,
121
CBEN[3–0]
75, 89, 100,
111
I/O
PCICLK
60
I
Clock: This PCI bus clock provides timing for all bus phases. The rising edge defines the start of
each phase. The clock frequency ranges from 0 to 33 MHz.
DEVSELN
95
I/O
Device Select: As a bus master, the DP83816 device samples this signal to ensure that the
destination address for the data transfer is recognized by a PCI target. As a target, the DP83816
device asserts this signal low when it recognizes its address after FRAMEN is asserted.
FRAMEN
91
I/O
Frame: As a bus master, this signal is asserted low to indicate the beginning and duration of a
bus transaction. Data transfer takes place when this signal is asserted. The signal is de-asserted
before the transaction is in its final phase. As a target, the device monitors this signal before
decoding the address to check if the current transaction is addressed.
GNTN
63
I
Grant: This signal is asserted low to indicate to the DP83816 device that it has been granted
ownership of the bus by the central arbiter. This input is used when the DP83816 device is acting
as a bus master.
IDSEL
76
I
Initialization Device Select: This pin is sampled by the DP83816 device to identify when
configuration read and write accesses are intended.
INTAN
61
O, OD
Interrupt A: This signal is asserted low when an interrupt condition occurs as defined in the
interrupt status, interrupt mask, and interrupt enable registers.
IRDYN
92
I/O
Initiator Ready: When the DP83816 device is a bus master, this signal is asserted low when the
DP83816 device is ready to complete the current data-phase transaction. This signal is used in
conjunction with the TRYDN signal. A data transaction takes place at the rising edge of PCICLK
when both IRDYN and TRDYN are asserted low. When the DP83816 device is a target, this
signal indicates that the master has put the data on the bus.
PAR
99
I/O
Parity: This signal indicates even parity across AD[31–0] and CBEN[3–0] including the PAR pin.
As a master, PAR is asserted during address and write-data phases. As a target, PAR is asserted
during read-data phases.
PERRN
97
I/O
Parity Error: The DP83816 device as a master or target asserts this signal low to indicate a
parity error on any incoming data (except for special cycles). As a bus master, the device
monitors this signal on all write operations (except for special cycles).
REQN
64
O
Request: The DP83816 device asserts this signal low to request ownership of the bus from the
central arbiter.
RSTN
62
I
Reset: When this signal is asserted, all PCI bus outputs of the DP83816 device are in te highimpedance state and the device is put into a known state.
SERRN
98
I/O
System Error: This signal, if enabled, is asserted low by the DP83816 device during address
parity errors and system errors.
STOPN
96
I/O
Stop: This signal is asserted low by the target device to request the master device to stop the
current transaction.
(1)
6
I = input, O = output, I/O = input/output, OD = open-drain, PD = pulldown
Pin Configuration and Functions
Copyright © 2005–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DP83816
DP83816
www.ti.com
SNLS164E – SEPTEMBER 2005 – REVISED DECEMBER 2015
Table 3-1. Pin Functions, PCI Bus Interface (continued)
PIN
NAME
NO.
TRDYN
93
TYPE (1)
DESCRIPTION
I/O
Target Ready: When the DP83816 device is a bus master, this signal indicates that the target is
ready for the data during write operation or with the data during read operation. When the
DP83816 device is a target, this signal is asserted low when the (target) device is ready to
complete the current data-phase transaction. This signal is used in conjunction with the IRDYN
signal. Data transaction takes place at the rising edge of PCICLK when both IRDYN and TRDYN
are asserted low.
Power Management Event and Clock Run Function: This pin is a dual-function pin. The
function of this pin is determined by the CLKRUN_EN bit 0 of the CLKRUN Control and Status
register (CCSR). Default operation of this pin is PMEN.
Power Management Event: This signal is asserted low by the DP83816 device to indicate that a
power management event has occurred. For pin connection, see Section 6.2.1.4.
Clock Run Function: In this mode, this pin is used to indicate when the PCICLK will be stopped.
PMEN/
CLKRUNN
59
I/O, OD
PWRGOOD
123
I, PD
PCI Bus Power Good: Connected to PCI bus 3.3-V power, this pin is used to sense the
presence of PCI bus power during the D3 power-management state.
Table 3-2. Pin Functions, Media Independent Interface (1)
PIN
NAME
NO.
TYPE (2)
DESCRIPTION
COL
28
I
Collision Detect: The COL signal is asserted high asynchronously by the external PMD on
detection of a collision on the medium. It remains asserted as long as the collision condition
persists.
CRS
29
I
Carrier Sense: This signal is asserted high asynchronously by the external PMD on detection of
a non-idle medium.
MDC
5
O
Management Data Clock: Clock signal with a maximum rate of 2.5 MHz used to transfer
management data for the external PMD on the MDIO pin.
MDIO
4
I/O
Management Data I/O: Bidirectional signal used to transfer management information for the
external PMD. (See Section 5.4.1.4 for details on connections when MII is used.)
RXCLK
6
I
Receive Clock: A continuous clock, sourced by an external PMD device, that is recovered from
the incoming data. During 100-Mb/s operation RXCLK is 25 MHz, and during 10 Mb/s RXCLK is
2.5 MHz.
RXD3/MA9
RXD2/MA8
RXD1/MA7
RXD0/MA6
12
11
10
7
I/O
I: BIOS ROM Address: During external BIOS ROM access, these signals become part of the
ROM address.
O: Receive Data: Sourced from an external PMD, that contains data aligned on nibble
boundaries and are driven synchronous to RXCLK. RXD3 is the most-significant bit and RXD0 is
the least-significant bit.
RXDV/MA11
15
I/O
I: Receive Data Valid: Indicates that the external PMD is presenting recovered and decoded
nibbles on the RXD signals, and that RXCLK is synchronous to the recovered data in 100-Mb/s
operation. This signal encompasses the frame, starting with the start-of-frame delimiter (JK) and
excluding any end-of-frame delimiter (TR).
O: BIOS ROM Address: During external BIOS ROM access, this signal becomes part of the
ROM address.
RXER/MA10
14
I/O
I: Receive Error: Asserted high synchronously by the external PMD whenever it detects a media
error and RXDV is asserted in 100-Mb/s operation.
O: BIOS ROM Address: During external BIOS ROM access, this signal becomes part of the
ROM address.
RXOE
13
O
Receive Output Enable: Used to disable an external PMD while the BIOS ROM is being
accessed.
TXCLK
31
I
Transmit Clock: A continuous clock that is sourced by the external PMD. During 100-Mb/s
operation this is 25 MHz ±100 ppm. During 10-Mb/s operation this clock is 2.5 MHz ±100 ppm.
TXD3/MA15
TXD2/MA1
TXD1/MA1
TXD0/MA12
25
24
23
22
O
Transmit Data: Signals which are driven synchronously to the TXCLK for transmission to the
external PMD. TXD3 is the most-significant bit and TXD0 is the least-significant bit.
BIOS ROM Address: During external BIOS ROM access, these signals become part of the ROM
address.
TXEN
30
O
Transmit Enable: This signal is synchronous to TXCLK and provides precise framing for data
carried on TXD[3–0] for the external PMD. It is asserted when TXD[3–0] contains valid data to be
transmitted.
(1)
(2)
MII is normally in the high-impedance state, unless enabled by CFG: EXT_PHY. See Section 5.6.3.2.
I = input, O = output, I/O = input/output
Pin Configuration and Functions
Copyright © 2005–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DP83816
7
DP83816
SNLS164E – SEPTEMBER 2005 – REVISED DECEMBER 2015
www.ti.com
Table 3-3. Pin Functions, 10/100-Mb/s PMD Interface
PIN
NAME
NO.
TPTDP
TPTDM
DESCRIPTION
I/O
Transmit Data: Differential common-output driver. This differential common output is configurable
to either 10BASE-T or 100BASE-TX signaling:
10BASE-T: Transmission of Manchester-encoded 10BASE-T packet data as well as link pulses
(including fast link pulses for auto-negotiation purposes).
100BASE-TX: Transmission of ANSI X3T12 compliant MLT-3 data.
The DP83816 device automatically configures this common output driver for the proper signal
type as a result of either forced configuration or auto-negotiation.
I/O
Receive Data: Differential common-input buffer. This differential common input can be configured
to accept either 100BASE-TX or 10BASE-T signaling:
10BASE-T: Reception of Manchester-encoded 10BASE-T packet data as well as normal link
pulses and fast link pulses for auto-negotiation purposes.
100BASE-TX: Reception of ANSI X3T12 compliant scrambled MLT-3 data.
The DP83816 device automatically configures this common input buffer to accept the proper
signal type as a result of either forced configuration or auto-negotiation.
54
53
TPRDP
TPRDM
(1)
TYPE (1)
46
45
I/O = input/output
Table 3-4. Pin Functions, BIOS ROM (1) or Flash Interface
PIN
TYPE (2)
DESCRIPTION
NAME
NO.
MCSN
129
O
MD7, MD6
MD5, MD4/EEDO,
MD3
MD2,
MD1/CFGDISN,
MD0
141, 140,
139, 138,
135,
134,
133,
132
I/O, PD
I/O, PU
BIOS ROM or Flash Data Bus: During a BIOS ROM or flash access, these signals are used
to transfer data to or from the ROM or flash device.
MA5,
MA4/EECLK,
MA3/EEDI,
MA2/LED100LNK,
MA1/LED10LNK,
MA0/LEDACT
3,
2,
1,
144,
143,
142
O
BIOS ROM or Flash Address: During a BIOS ROM or flash access, these signals are used to
drive the ROM or flash address.
MWRN
131
O
BIOS ROM or Flash Write: During a BIOS ROM or flash access, this signal is used to
enable data to be written to the flash device.
MRDN
130
O
BIOS ROM or Flash Read: During a BIOS ROM or flash access, this signal is used to
enable data to be read from the flash device.
(1)
(2)
BIOS ROM or Flash Chip Select: During a BIOS ROM or flash access, this signal is used
to select the ROM device.
The DP83816 device supports the NM27LV010 EPROM for the BIOS ROM interface device.
O = output, I/O = input/output, PD = pulldown, PU = pullup
Table 3-5. Pin Functions, Clock Interface
PIN
NAME
NO.
TYPE (1)
DESCRIPTION
X1
17
I
Crystal or Oscillator Input: This pin is the primary clock reference input for the DP83816 device
and must be connected to a 25-MHz 0.005% (50-ppm) clock source. The DP83816 device
supports either an external crystal resonator connected across pins X1 and X2, or an external
CMOS-level oscillator source connected to pin X1 only.
X2
18
O
Crystal Output: This pin is used in conjunction with the X1 pin to connect to an external 25-MHz
crystal resonator device. This pin must be left unconnected if an external CMOS oscillator clock
source is used. For more information, see the definition for pin X1.
(1)
8
I = input, O = output
Pin Configuration and Functions
Copyright © 2005–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DP83816
DP83816
www.ti.com
SNLS164E – SEPTEMBER 2005 – REVISED DECEMBER 2015
Table 3-6. Pin Functions, LED Interface
PIN
TYPE (1)
DESCRIPTION
142
O
TX/RX Activity: This pin is an output indicating transmit/receive activity. This pin is driven low
to indicate active transmission or reception, and can be used to drive a low-current LED (
工商网监
湘ICP备2023018690号
