DP83822 EVM
User's Guide
Literature Number: SNLU179
August 2016
Contents
1
Introduction ......................................................................................................................... 4
1.1
2
Operation – Quick Setup ................................................................................................ 7
Board Setup Details ............................................................................................................ 10
2.1
Block Diagram........................................................................................................... 10
2.2
Power Supply Options
2.3
Serial Management and MAC Interfaces ............................................................................ 14
2.4
LED Options ............................................................................................................. 15
2.5
Bootstrap Options/Jumpers
2.6
Clock Options ........................................................................................................... 17
2.7
100BASE-FX Configuration (Fiber)................................................................................... 18
.................................................................................................
...........................................................................................
11
16
5
......................................................................................................................... 19
3.1
Hardware Schematic ................................................................................................... 19
3.2
Main Block Schematic.................................................................................................. 20
3.3
Power Block Schematic ................................................................................................ 21
3.4
Analog Front-End Schematic.......................................................................................... 22
3.5
Connector and Bootstrap Schematic ................................................................................. 23
Layout ............................................................................................................................... 24
4.1
Top Overlay ............................................................................................................. 24
4.2
Top Layer ................................................................................................................ 24
4.3
Signal Layer 1 ........................................................................................................... 25
4.4
Signal Layer 2 ........................................................................................................... 25
4.5
Signal Layer 3 ........................................................................................................... 26
4.6
Signal Layer 4 ........................................................................................................... 26
4.7
Bottom Layer ............................................................................................................ 27
4.8
Bottom Overlay.......................................................................................................... 27
4.9
Board Assembly ........................................................................................................ 28
Bill of Materials .................................................................................................................. 29
2
Table of Contents
3
4
Schematic
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User's Guide
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DP83822 EVM
This User’s Guide details the characteristics, operation, and use of the DP83822 10/100 Mbps Industrial
Ethernet PHY. The EVM enables Texas Instruments’ customers to quickly design and market systems
using the DP83822. This document also includes schematic diagrams, a printed-circuit board layout,
board assembly, board marking drawings, and a bill of materials.
Table 1. Terminology
Acronym
Definition
PHY
Physical Layer Transceiver
MAC
Media Access Controller
EEE
Energy Efficient Ethernet
WoL
Wake-on-LAN
SMI
Serial Management Interface
MDIO
Management Data I/O
MDC
Management Data Clock
SFP
Small Form-Factor Pluggable (Fiber Transceiver)
MII
Media Independent Interface
RMII
Reduced Media Independent Interface
RGMII
Reduced Gigabit Media Independent Interface
SFD
Start-of-Frame Detection
CAT5
Category 5 (cable electrical characteristics)
AVD
Analog Supply Rail
VDDIO
Digital Supply Rail
CT
Center Tap Supply Rail
PD
Pull-Down
PU
Pull-Up
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Introduction
1
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Introduction
The DP83822 EVM supports 10/100 Mbps and is compliant to the IEEE 802.3u standard. This reference
design supports MII, RMII and RGMII MAC interfaces.
The DP83822 EVM includes two onboard status LEDs, optional Fiber SFP connector and cage, and
onboard supply through a 5-V micro USB connector. The DP83822 EVM is capable of providing a 125MHz, 50-MHz or 25-MHz reference clock from an onboard 25-MHz crystal. The EVM includes the
CDCE925 programmable 2-PLL VCXO clock synthesizer with 1.8-V to 3.3-V LVCMOS outputs. Serial
management interface, MDIO/MDC, is supported and can be used to access PHY registers for additional
features. There are 4-level straps, which allow for system configurations without the need to directly
access PHY registers. External power supplies can be connected to each specified voltage rail for
additional system evaluation. The DP83822 supports Wake-on-LAN, Energy Efficient Ethernet
(IEEE802.3az), Start-of-Frame Detect IEEE 1588 Time Stamp, and configurable I/O voltages.
Key Features:
• IEEE 802.3u Compliant: 100BASE-FX, 100BASE-TX and 10BASE-Te
• CDCE925 Programmable 2-PLL VCXO Clock Synthesizer with 1.8 V to 3.3 V
• MII, RMII and RGMII MAC interfaces
• SFD IEEE 1588 Time Stamp
• Two status LEDs
– LED LINK/ACTIVITY
– LED SPEED
• Low Power Modes
– Energy Efficient Ethernet (IEEE802.3az)
– Wake-on-LAN
– Active Sleep
– Passive Sleep
– IEEE Power Down
– Deep Power Down
• Variable I/O voltage range: 1.8 V, 2.5 V and 3.3 V
• 100BASE-TX error free data transfer over 150 meters on CAT5 cable
The DP83822 EVM has an RJ45 connector (J12) with discrete magnetics and stuffing resistor array for
configurable bootstraps. Customers are encouraged to use a design similar to the EVM circuit to expedite
their product development.
4
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Introduction
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Figure 1. DP83822 EVM – Top Side
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Introduction
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Figure 2. DP83822 EVM - Bottom Side
6
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Introduction
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1.1
Operation – Quick Setup
1. Select internal supply by populating the following with jumpers (J6):
(a) Place jumper #1 at ‘AVD INT’ position
(b) Place jumper #2 at ‘CT INT’ position
(c) Place jumper #3 at ‘VDDIO INT’ position
Figure 3. On-Board Power Supply Configuration
2. Select VDDIO voltage level (R26):
• 4.22 kΩ - 3.3 V operation (Default)
• 2.56 kΩ - 2.5 V operation
• 1.20 kΩ - 1.8 V operation
3. Select AVD voltage level (R19):
• 4.22 kΩ - 3.3 V operation (Default)
• 1.20 kΩ - 1.8 V operation
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Introduction
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4. Select reference clock frequency (J2):
• 25 MHz – jumper across pins 1 and 2
• 50 MHz – jumper across pins 2 and 3
Figure 4. Reference Clock Selection
5. Place a jumper in the ‘PU’ position for LED LINK/ACT (J10)
Figure 5. LED LINK/ACT Selection
6.
7.
8.
9.
•
8
Turn ON the PHY by connecting a 5-V micro USB power supply to J5
Plug a CAT5, CAT5E or CAT6 cable into the RJ45 connector (J12)
Connect the far-end of the Ethernet cable to a link partner
Connect a MAC interface to J13 and J14
LED Indication
– The AVD LED (D1) and VDDIO LED (D2) will be illuminated if the 5-V supply is connected
– Look for the LINK LED (D4) to light up on the DP83822 EVM after the PHY links with a connected
partner
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Introduction
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Figure 6. MAC IF Connection and LED Indication
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Board Setup Details
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2
Board Setup Details
2.1
Block Diagram
3.3-V / 2.5-V / 1.8-V
External Supplies
MAC
MII / RMII / RGMII
5-V
EVM
5-V Turret /
USB
14 Pin
Header
26 Pin
Header
AVD & CT LDO
1.8-V or 3.3-V
I
MI
II
GM
R
/
R
I/
MI
VDDIO LDO
1.8-V, 2.5-V, 3.3-V
Bootstrap
Resistors /
Jumpers
AVD
GPIOs
VDDIO
DP83822
DUT
MDIO / MDC
CDCE925
LED LINK /
ACT
External
Clock
LED SPEED
Magnetics
Capacitive
Isolation
Fiber
Termination
RJ45
CAT5
Cable
SFP
Figure 7. DP83822 EVM Block Diagram
10
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2.2
Power Supply Options
The DP83822 EVM power is supplied by a single 5-V connection. This option uses onboard LDOs to
provide 3.3-V, 2.5-V or 1.8-V rails. Connect 5-V supply to either the USB micro A/B connector (J5) or V+1
turret and populate jumpers on J6 as specified in Section 1.1 for onboard supplies. When using the V+1
turret, GND1 turret should be used as the ground connection.
Figure 8. Onboard Supply Connection
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The DP83822 EVM also supports external supply connections. External supply option bypasses the
onboard LDOs and allows for direct connections to each supply rail.
To
•
•
•
configure the DP83822 EVM for external supply operation, use the following jumper configuration (J6):
Place jumper #1 at ‘AVD EXT’ position
Place jumper #2 at ‘CT EXT’ position
Place jumper #3 at ‘VDDIO EXT’ position
Figure 9. External Supply Configuration
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There are three supply rail turrets for external supply connection. The three turrets are shown in the image
below. ‘GND1’ should be used as the ground connection for each of the three supply rails.
• ‘External AVD’ – External AVD supply rail
• ‘External CT’ – External Center Tap supply rail
• ‘External VDDIO’ – External VDDIO supply rail
Figure 10. External Turret Connection
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Board Setup Details
2.3
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Serial Management and MAC Interfaces
The DP83822 EVM supports SMI (MDIO/MDC) and MII, RMII and RGMII MAC interfaces. SMI is
accessible though J14. MDIO is located at pin 23 and MDC is located at pin 21. Ground connection
between the DP83822 EVM and SMI controller is required for proper operation. DP83822 supports both
clause 22 and clause 45 in the IEEE 802.3 specification. For further SMI support please refer to the
Ethernet USB2MDIO Application Note for interfacing the MSP430 Launchpad with TI Ethernet
PHYs.
Note: The default PHY_ID is ‘1’. PHY_ID can be changed via bootstrap options found in the datasheet.
MAC interface pins are located on J13 and J14. MII, RMII and RGMII configurations are located in the
datasheet and can be configured by bootstrapping or direct register access through the SMI. Please refer
to the DP83822 datasheet for specific pin requirements for each MAC interface.
Figure 11. DP83822 EVM MAC IF Connections
14
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2.4
LED Options
The DP83822 supports up to three configurable LEDs: Link, Speed and MLED. The DP83822 EVM has
two onboard LEDs that can be controlled by direct register access using the SMI. LED pins can operate
as either current sources (when connected to pull-down) or current sinks (when connected to pull-up).
Figure 12. LED Speed and Link
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2.5
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Bootstrap Options/Jumpers
Some DP83822 configurations can be done through bootstrap options. Options can be selected with
jumpers or resistor population. Please refer to the datasheet for bootstrap options and schematic/layout
sections of this User’s Guide for resistor locations.
Table 2. Bootstrap Resistor Designation and Suggested Bootstrap Resistor Values
Pin Name Pin Number
COL
RX_D0
RX_D1
RX_D2
RX_D3
CRS
RX_ER
RX_DV
16
29
30
31
32
1
27
28
26
Strap
Mode
PU Resistor (kΩ)
PU Resistor
Designation
1
OPEN
2
13
3
6.2
4
OPEN
OPEN
1
OPEN
OPEN
2
10
3
5.76
PD Resistor (kΩ)
1.96
R84
R71
1.96
1.96
2.49
2.49
4
2.49
OPEN
1
OPEN
OPEN
2
10
3
5.76
R75
2.49
2.49
4
2.49
OPEN
1
OPEN
OPEN
2
10
3
5.76
4
2.49
OPEN
1
OPEN
OPEN
2
10
3
5.76
R77
R80
2.49
2.49
2.49
2.49
4
2.49
OPEN
1
OPEN
1.96
2
13
3
6.2
4
OPEN
OPEN
1
OPEN
1.96
2
13
3
6.2
4
OPEN
OPEN
1
OPEN
OPEN
2
10
3
5.76
4
2.49
PD Resistor
Designation
R53
R60
R45
DP83822 EVM
1.96
1.96
1.96
1.96
2.49
2.49
R88
R72
R76
R78
R82
R55
R66
R48
OPEN
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2.6
Clock Options
The DP83822 EVM uses the CDCE925 programmable 2-PLL VCXO clock synthesizer. A 25-MHz crystal
resonator is connected to the CDCE925, which can then be configured to either a 50-MHz or 25-MHz
LVCMOS output in the range of 1.8 V to 3.3 V. The output of the CDCE925 is directly fed into the XI pin of
the DP83822.
In
•
•
•
•
order to operate with a 25-MHz reference clock, the following modifications are required:
Populate R3 with a 0-Ω resistor
Populate R95 and R96 with 1-kΩ resistors
Remove R4
Place a jumper across pin 1 and pin 2 on J2
In
•
•
•
•
order to operate with a 50-MHz reference clock, the following modifications are required:
Populate R3 with a 0-Ω resistor
Populate R95 and R96 with 1-kΩ resistors
Remove R4
Place a jumper across pin 2 and pin 3 on J2
Table 3. CDCE925 Programmed Clock Setting Selection
2.6.1
S2
S1
S0
Reference Clock Setting
0
0
0
25 MHz
0
0
1
50 MHz
External Configuration
Additionally, the DP83822 EVM has an external reference clock option through an SMA (J1).
The external clock must meet the DP83822 data sheet requirements and to be within 50 MHz or 25 MHz
with ±50ppm tolerance.
The following changes are required to route an external clock to the DP83822:
• Populate R4 with a 0-Ω resistor
• Populate an SMA at J1
• Remove R3
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2.7
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100BASE-FX Configuration (Fiber)
The DP83822 EVM supports 100BASE-FX by use of an SFP transceiver. The DP83822 can be configured
for 100BASE-FX operation through either bootstrap or SMI register configuration.
To
•
•
•
•
•
•
•
configure the DP83822 EVM for 100BASE-FX operation, the following changes are required:
Remove T2
Remove R34, R35, R28, R29, R30 and R31
Populate C47, C48, C49, C50, C53, C54, C57, C58, C59 and C66
Populate L3 and L4
Populate J15
Populate H1
Populate R36, R41, R42 and R44
Note: It is important to read the termination requirements for the SFP transceiver used. The DP83822
EVM allows for custom termination on both receive and transmit paths to ensure support for most SFP
transceivers. Please refer to the schematic/layout for more information regarding the termination network.
Figure 13. SFP Cage and Termination Network
Figure 14. SFP Power Network
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Schematic
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3
Schematic
3.1
Hardware Schematic
M1
M3
EARTH
M2
M4
C68
4700pF
GND
C69
4700pF
GND
SFP_EARTH
3V3 VDDIO
AVD
Power
SV601202-001_POWER_BLOCK.SchDoc
LED_0
LED_GPIO
FID1
FID2
AVD
LED_0
LED_GPIO
FID3
VDDIO
AVD
3V3
VDDIO
FX_TD_P
FX_TD_N
TXD_P
TXD_N
TX_CLK
TX_EN
TX_D0
TX_D1
TX_D2
TX_D3
PCB
LOGO
PCB
LOGO
Pb-Free Symbol
FCC disclaimer
TX_CLK
TX_EN
TX_D0
TX_D1
TX_D2
TX_D3
RX_CLK
RX_DV
CRS
RX_ER
COL
RX_D0
RX_D1
RX_D2
RX_D3
RX_CLK
RX_DV
CRS
RX_ER
COL
RX_D0
RX_D1
RX_D2
RX_D3
Connectors
SV601202-001_CONNECTOR.SchDoc
3V3
VDDIO
PCB Number: SV601202
PCB Rev: E1
Texas Instruments
AFE
SV601202-001_AFE.SchDoc
MAIN
SV601202-001_MAIN_BLOCK.SchDoc
3V3
PCB
LOGO
3V3
AVD
VDDIO
RXD_P
RXD_N
MDC
MDIO
LED_0
LED_GPIO
INT_PWDN_N
RESET_N
TXD_P
TXD_N
RXD_P
RXD_N
MDC
MDIO
TXD_P
TXD_N
RXD_P
RXD_N
FX_RD_P
FX_RD_N
3V3
FX_TD_P
FX_TD_N
FX_RD_P
FX_RD_N
FX_RD_P
FX_RD_N
VDDIO
INT_PWDN_N
RESET_N
MDC
MDIO
LED_0
LED_GPIO
FX_TD_P
FX_TD_N
LED_GPIO
INT_PWDN_N
RESET_N
MDC
MDIO
RX_ER
RX_CLK
RX_DV
COL
CRS
RX_D0
RX_D1
RX_D2
RX_D3
TX_CLK
TX_EN
TX_D0
TX_D1
TX_D2
TX_D3
RX_ER
RX_CLK
RX_DV
COL
CRS
RX_D0
RX_D1
RX_D2
RX_D3
TX_CLK
TX_EN
TX_D0
TX_D1
TX_D2
TX_D3
LED_GPIO
INT_PWDN_N
RESET_N
Label Table
Variant
LBL1
PCB Label
Label Text
001
DP83822
002
DP83822F
Size: 0.65" x 0.20 "
ZZ1
Label Assembly Note
This Assembly Note is for PCB labels only
H1
1
2
3
4
5
6
ZZ2
Assembly Note
These assemblies are ESD sensitive, ESD precautions shall be observed.
ZZ3
Assembly Note
These assemblies must be clean and free fro m flux and all contaminants. Use of no clean flux is not acceptable.
ZZ4
Assembly Note
These assemblies must comply with workmanship standards IPC-A-610 Class 2, unless otherwise specified.
MH1
MH2
MH3
MH4
Shield
Shield
Shield
Shield
Shield
Shield DNP
MH1
MH2
MH3
MH4
Shield
Shield
Shield
Shield
Shield
Shield
MH5
MH6
MH7
MH8
7
8
9
10
11
12
MH5
MH6
MH7
MH8
U77-A1118-200T
SFP_EARTH
SFP_EARTH
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Figure 15. Hardware Schematic
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Schematic
3.2
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Main Block Schematic
J1
G
G
4
2
+1V8
GND
Y1
25 MHz
EXT_CLK
1
DNP
+1V8
+1V8
R93
DNP
1.00k
R94
DNP
1.00k
R95
1.00k
R96
1.00k
5
4
3
2
R1
1.00k
J2
C6
2.2µF
120 ohm
TSW-103-07-T-S
C7
2.2µF
0
GND
DNPC4
12pF
3V3A
L2
R92
3
1
3
2
1
VDDIO
C8
0.1µF
DNPC5
12pF
GND
GND
XIN/CLK
XOUT
U1
+1V8
1
GND
2
R2
1.00k
3
4
C9
0.01µF
5
GND
6
3V3A
GND
7
GND
8
C11
0.01µF
VDDIO
U2
S0
S1/SDA
VDD
S2/SCL
VCTR
Y1
GND
GND
VDDOUT
Y2
Y4
Y3
Y5
VDDOUT
16
15
GND
GND
14
13
R3
12
18
11
10
XI
R4
DNP
0
EXT_CLK
GND
3V3A
9
C10
0.01µF
CDCE925PWR
AVD
21
14
TX_EN
TX_CLK
TX_D0
TX_D1
TX_D2
TX_D3
RX_DV
RX_ER
RX_CLK
RX_D0
RX_D1
RX_D2
RX_D3
COL
CRS
TX_EN
TX_CLK
3
2
TX_D0
TX_D1
TX_D2
TX_D3
4
5
6
7
VDDIO
TD_P
TD_M
AVD33
RD_P
RD_M
TX_EN
TX_CLK
RBIAS
TX_D0
TX_D1
TX_D2
TX_D3
LED_0/AN_0/MLED
MDC
MDIO
RX_DV
RX_ER
RX_CLK
26
28
25
RX_D0
RX_D1
RX_D2
RX_D3
30
31
32
1
RX_D0/PHYAD1
RX_D1/PHYAD2
RX_D2/PHYAD3
RX_D3/PHYAD4/CL KOUT
COL
CRS
29
27
COL/PHYAD0/ML ED
CRS/CRS_DV/LED_CFG
TP1
TP2
13
15
RX_DV/MII_MODE
RX_ER/AMDIX_EN
RX_CLK
INT/PWDN
RESET
XI
XO
CLK_O
NC
NC
PAD
12
11
TXD_P
TXD_N
10
9
RXD_P
RXD_N
16
RBIAS
17
LED_0
20
19
MDC
MDIO
8
INT_PWDN_N
18
RESET_N
23
XI
TXD_P
TXD_N
GND
GND
RXD_P
RXD_N
Rs1
VDDIO
R5
2.21k
4.87k
LED_0
GND
MDC
MDIO
INT_PWDN_N
RESET_N
22
24
LED_GPIO
LED_GPIO
33
DP83822RHBR
GND
VDDIO
DNPC12
22µF
C13 DNPC14 DNPC15
10µF
1µF
0.1µF
C16
0.01µF
C17
C18
1000pF 100pF
VDDIO
VDDIO
J4
GND
1
R7
DNP
0
R6
2.21k
R8
DNP
2.21k
RX_D3
INT_PWDN_N
2
3
4
5
AVD
S1
RESET_N
DNPC19
22µF
C20 DNPC21 DNPC22
10µF
1µF
0.1µF
C23
0.01µF
C24
C25
1000pF 100pF
GND
DNPC27
10µF
R10
2.21k
R9
DNPC26 DNP
2.21k
10µF
GND
GND
GND
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Figure 16. Main Block Schematic
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Schematic
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3.3
Power Block Schematic
R11
DNP
1.00M
PWR_CHASSIS
GND
1
VDDIO
1
AVD
C28
2
D2
QTLP630C4TR
Green
11
10
9
GND
2
D1
QTLP630C4TR
Green
4700pF
PWR_CHASSIS
V+1
DNP
2
2
AK
C31
0.01µF
C32
1000pF
T1
C33
100pF
4
C30
10µF
1
VBUS
2
D-
3
D+
4
GND
GND1
OUT
SHDN
ADJ
6
TAB GND
DNP
GND
+1V8
GND2
VDDIO
GND
3V3
J6
J8
VDDIO_EXT
J9
AVD_EXT
VDDIO_EXT
VDDIO_INT
AVD_INT
3V3_EXT
AVD_EXT
AVD_INT
3V3_EXT
4
1
3
5
7
9
11
2
4
6
8
10
12
AVD
5
R14
1.20k
DNPC35
22µF
PWR_CHASSIS
3
1
C34
10µF
IN
GND
J7
6
7
8
TL1963AQKTTRQ1
U3
2
R13
470
ID
5
5V_20V
J5
PWR_CHASSIS
0475890001
3
1
1
DNPC29
22µF
R12
470
V+2
D3
5V_20V
GND
GND
GND
VDDIO
R15
2.40k
R16
AVD:
Adjustable Supply
2.49k
D4
GND
2
TL1963AQKTTRQ1
U4
2
1
C36
10µF
IN
OUT
SHDN
ADJ
LED_0
LED_0
R17
1
470
QTLP630C4TR
Green
5
TAB GND
6
AVD_INT
4
R19
4.22k
DNPC37
22µF
R18
TSW-103-07-G-S
2.49k
D5
3
5V_20V
J10
1
2
3
R20
GND
1
470
GND
QTLP630C4TR
Green
R21
2.40k
GND
2
GND
VDDIO
GND
Adjustable
Supplies:
4.22K for 3.3V
2.56K for 2.5V
1.2K for 1.8V
R22
2.49k
D6
2
VDDIO:
Adjustable Supply
LED_GPIO
TL1963AQKTTRQ1
U5
IN
OUT
4
1
SHDN
ADJ
5
TAB GND
6
C38
10µF
2
LED_GPIO
470
QTLP630C4TR
Green
R24
TSW-103-07-G-S
VDDIO_INT
2.49k
D7
R26
4.22k
DNPC39
22µF
1
R25
1 2
2
1
2
470
QTLP630C4TR
Green
3
5V_20V
R23
1
J11
1
2
3
GND
GND
GND
GND
R27
2.40k
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 17. Power Block Schematic
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21
Schematic
3.4
www.ti.com
Analog Front-End Schematic
Magnetic
T2
RXD_MAG_N
Copper
J12
8
7
6
5
4
3
2
1
12
11
10
9
8
10
7
11
6
12
5
13
4
14
3
15
2
RXD_N
3V3
R28
RXD_CABLE_N
0
R29
RXD_CABLE_P
DNP C40
22
0
R30
TXD_CABLE_N
1-406541-1
RXD_MAG_P
0
0
R33
75
RXD_P
R31
TXD_CABLE_P
R32
75
EARTH
9
µF
TXD_MAG_N
C41
0.01µF
GND
TXD_N
EARTH
TXD_MAG_P
16
1
TXD_P
C42
1µF
350µH
R34
75
ESD
GND
U6
TXD_CABLE_P
TXD_CABLE_N
1
2
RXD_CABLE_N
RXD_CABLE_P
TXD_CABLE_N
TXD_CABLE_P
6
7
9
10
C43
0.1µF
D1+
D1-
D2+
D2-
GND
GND
C45
0.1µF
GND
RXD_CABLE_P
RXD_CABLE_N
4
5
DNP
NC
NC
NC
NC
C44
1µF
R35
75
C46
0.01µF
8
3
EARTH
TPD4E05U06QDQARQ1
3V3
Fiber
EARTH
Termination
3V3
Cap Isolation
U7
RXD_N
RXD_P
1
2
TXD_P
TXD_N
RXD_P
RXD_N
6
7
9
10
D1+
D1-
D2+
D2-
TXD_N
TXD_P
4
5
C47
FX_RD_N
FX_RD_N
R36
DNP
0
RXD_MAG_N
RXD_MAG_N
1
GND
GND
8
3
2
RXD_N
R37
49.9
FX_RD_P
FX_RD_P
R41
DNP
0
RXD_MAG_P
RXD_MAG_P
1
21
DNP
2
RXD_P
TXD_N
0.1µF
GND
R38
49.9
TXD_P
C48
TPD4E05U06QDQARQ1
R39
49.9
TXD_N
R40
49.9
RXD_P
TXD_P
RXD_N
RXD_P
RXD_N
C49
FX_TD_N
FX_TD_N
R42
DNP
0
TXD_MAG_N
R44
DNP
0
TXD_MAG_P
TXD_MAG_N
1
21
DNP
2
TXD_N
0.1µF
GND Coupling
C50
R43
DNP
1.00M
EARTH
21
DNP
0.1µF
DNP
NC
NC
NC
NC
FX_TD_P
FX_TD_P
TXD_MAG_P
1
21
DNP
2
TXD_P
0.1µF
GND
C51
2
12
1
4700pF
EARTH
GND
C52
2
12
DNP
1
4700pF
EARTH
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 18. Analog Front-End Schematic
22
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Schematic
www.ti.com
3.5
Connector and Bootstrap Schematic
VDDIO
MAC IF
R45
DNP
10.0k
J13
INT_PWDN_N
TX_D3
TX_D2
TX_D1
TX_D0
TX_EN
TX_CLK
INT_PWDN_N
TX_D3
TX_D2
TX_D1
TX_D0
TX_EN
TX_CLK
R46
1
3
5
7
9
11
13
R47
0
R49
R50
0
0
0
R51
R52
R54
0
0
0
2
4
6
8
10
12
14
R48
DNP
2.49k
R53
DNP
13.0k
GND
TSW-107-07-G-D
GND
R55
DNP
1.96k
J14
RX_D3
RX_D2
RX_D1
RX_D0
COL
RX_ER
CRS
RX_DV
RX_CLK
LED_GPIO
MDC
MDIO
RESET_N
RX_D3
RX_D2
RX_D1
RX_D0
COL
RX_ER
CRS
RX_DV
RX_CLK
LED_GPIO
MDC
MDIO
RESET_N
R56
R57
R58
R59
R61
R62
0
0
0
R65
0
R69
0
0
1
3
5
7
9
11
13
15
17
19
21
23
25
0
0
0
R63
R64
0
R68
0
R67
R70
0
0
Fiber IF
2
4
6
8
10
12
14
16
18
20
22
24
26
GND
R60
DNP
13.0k
R66
DNP
1.96k
TSW-113-07-G-D
GND
R71
DNP
10.0k
Pull-Up Pins:
R72
DNP
2.49k
COL
LED_0
CRS
RX_ER
GND
VCC_R
J15
20
FX_TD_N
FX_TD_P
10
FX_TD_N
19
9
FX_TD_P
18
8
17
7
VCC_T
16
6
VCC_R
15
L3
DNP
1µH
DNPC53 DNPC54
0.01µF 0.1µF
FX_RD_P
FX_RD_N
DNP
R73
DNP
10k
R74
DNP
0
LOS
Pull-Down Pins:
LED_GPIO
GND
R75
DNP
10.0k
RX_D0
RX_D1
RX_D2
RX_D3
RX_DV
5
14
4
FX_RD_P
13
3
FX_RD_N
12
2
11
1
R76
DNP
2.49k
3V3
GND
R77
DNP
10.0k
GND
1367073-1
L4
3V3
3V3
DNP
GND
1µH
R79
DNP
82
GND
DNPC57 DNPC58 DNPC59
0.01µF 0.1µF
10µF
R78
DNP
2.49k
DNP C55 DNPC56
1µF
0.1µF
GND
FX_TD_N
R80
DNP
10.0k
GND
R81
DNP
130
LVPECL Termination
R82
DNP
2.49k
GND
GND Coupling
3V3
3V3
3V3
GND
R83
DNP
1.00M
R85
DNP
82
4700pF
SFP_EARTH
FX_RD_P
DNP C62 DNPC63
1µF
0.1µF
GND
GND
R87
DNP
82
DNPC64 DNPC65
1µF
0.1µF
R88
DNP
1.96k
GND
GND
FX_TD_P
R89
DNP
130
R90
DNP
130
GND
GND
R91
DNP
130
1
DNP
R86
DNP
82
FX_RD_N
GND
C67
4700pF
SFP_EARTH
DNPC60 DNPC61
1µF
0.1µF
2
GND
C66
1 2
SFP_EARTH
GND
R84
DNP
6.2k
GND
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 19. Connector and Bootstrap Schematic
SNLU179 – August 2016
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23
Layout
www.ti.com
4
Layout
4.1
Top Overlay
Figure 20. Top Overlay
4.2
Top Layer
Figure 21. Top Layer
24
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SNLU179 – August 2016
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Layout
www.ti.com
4.3
Signal Layer 1
Figure 22. Signal Layer 1
4.4
Signal Layer 2
Figure 23. Signal Layer 2
SNLU179 – August 2016
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25
Layout
4.5
www.ti.com
Signal Layer 3
Figure 24. Signal Layer 3
4.6
Signal Layer 4
Figure 25. Signal Layer 4
26
DP83822 EVM
SNLU179 – August 2016
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Layout
www.ti.com
4.7
Bottom Layer
Figure 26. Bottom Layer
4.8
Bottom Overlay
Figure 27. Bottom Overlay
SNLU179 – August 2016
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Copyright © 2016, Texas Instruments Incorporated
27
Layout
4.9
www.ti.com
Board Assembly
Figure 28. Top Board Assembly
Figure 29. Bottom Board Assembly
28
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Bill of Materials
www.ti.com
5
Bill of Materials
Table 4. Bill of Materials
Part Number
Component
Designation
Description
Qty
C0402C120J3GACAUTO
C4, C5
CAP, CERM, 12 pF, 25 V, ±5%, C0G/NP0, AEC-Q200
Grade 1, 0402
2
GRM155R61C225KE11D
C6, C7
CAP, CERM, 2.2 µF, 16 V, ±10%, X5R, 0402
2
GRM155R71C104KA88D
C8, C15, C22,
C43, C45, C54,
C56, C58, C61,
C63, C65
CAP, CERM, 0.1 µF, 16 V, ±10%, X7R, 0402
11
CGA2B3X7R1H103K050BB
C9, C10, C11,
C16, C23, C31,
C53, C57
CAP, CERM, 0.01 µF, 50 V, ±10%, X7R, AEC-Q200 Grade
1, 0402
8
CGA6P1X7R1C226M250AC
C12, C19, C29,
C35, C37, C39,
C40
CAP, CERM, 22 µF, 16 V, ±20%, X7R, AEC-Q200 Grade
1, 1210
7
CGA6P1X7R1E106M250AC
C13, C20, C26,
C27, C30, C34,
C36, C38, C59
CAP, CERM, 10 µF, 25 V, ±20%, X7R, AEC-Q200 Grade
1, 1210
9
C1005X7S1A105K050BC
C14, C21, C42,
C44, C55, C60,
C62, C64
CAP, CERM, 1 µF, 10 V, ±10%, X7S, 0402
8
CGA2B2C0G1H102J050BA
C17, C24, C32
CAP, CERM, 1000 pF, 50 V, ±5%, C0G/NP0, AEC-Q200
Grade 1, 0402
3
CGA2B2C0G1H101J050BA
C18, C25, C33
CAP, CERM, 100 pF, 50 V, ±5%, C0G/NP0, AEC-Q200
Grade 1, 0402
3
1812GC472KAT1A
C28, C51, C52,
C66, C67
CAP, CERM, 4700 pF, 2000 V, ±10%, X7R, 1812
5
CGA4J3C0G2E103J125AA
C41
CAP, CERM, 0.01 µF, 250 V, ±5%, C0G/NP0, AEC-Q200
Grade 1, 0805
1
CGA4J3C0G2E103J125AA
C46
CAP, CERM, 0.01 µF, 250 V, ±5%, C0G/NP0, AEC-Q200
Grade 1, 0805
1
CGA3E2X8R1E104K080AA
C47, C48, C49,
C50
CAP, CERM, 0.1 µF, 25 V, ±10%, X8R, AEC-Q200 Grade
0, 0603
4
08051C472KAT2A
C68, C69
CAP, CERM, 4700 pF, 100 V, ±10%, X7R, 0805
2
QTLP630C4TR
D1, D2, D4, D5,
D6, D7
LED, Green, SMD
6
NRVBA160T3G
D3
Diode, Schottky, 60 V, 1 A, AEC-Q101, SMA
1
Fiducial
FID1, FID2, FID3
Fiducial mark. There is nothing to buy or mount.
3
1502-2
GND1, GND2,
V+1, V+2
Terminal, Turret, TH, Double
4
U77-A1118-200T
H1
SFP Single Cage
1
142-0701-851
J1
Connector, End launch SMA, 50 Ω, SMT
1
TSW-103-07-T-S
J2
Header, 2.54 mm, 3x1, Tin, TH
1
142-0701-851
J4
Connector, End launch SMA, 50 Ω, SMT
1
0475890001
J5
Connector, Receptacle, Micro-USB Type AB, R/A, Bottom
Mount SMT
1
TSW-106-07-G-D
J6
Header, 100mil, 6x2, Gold, TH
1
1502-2
J7
Terminal, Turret, TH, Double
1
1502-2
J8
Terminal, Turret, TH, Double
1
1502-2
J9
Terminal, Turret, TH, Double
1
TSW-103-07-G-S
J10, J11
Header, 100mil, 3x1, Gold, TH
2
1-406541-1
J12
RJ-45, No LED, tab up, R/A, TH
1
TSW-107-07-G-D
J13
Header, 100mil, 7x2, Gold, TH
1
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Bill of Materials
www.ti.com
Table 4. Bill of Materials (continued)
Part Number
Component
Designation
TSW-113-07-G-D
1367073-1
Description
Qty
J14
Header, 100mil, 13x2, Gold, TH
1
J15
Receptacle, 0.8mm, 10x2, Gold, R/A, SMT
1
BLM21BD121SN1D
L2
Ferrite Bead, 120 Ω at 100 MHz, 0.2 A, 0805
1
IFSC0806AZER1R0M01
L3, L4
Inductor, Shielded, Ferrite, 1 µH, 1.6 A, 0.115 Ω, SMD
2
THT-14-423-10
LBL1
Thermal Transfer Printable Labels, 0.650" W x 0.200" H 10,000 per roll
1
CRCW04021K00FKED
R1, R2
RES, 1.00 k, 1%, 0.063 W, 0402
2
CRCW040218R0JNED
R3
RES, 18, 5%, 0.063 W, 0402
1
CRCW04020000Z0ED
R4
RES, 0, 5%, 0.063 W, 0402
1
TNPW06032K21BEEA
R5, R6, R8, R9,
R10
RES, 2.21 k, 0.1%, 0.1 W, AEC-Q200 Grade 0, 0603
5
ERJ-1GE0R00C
R7
RES, 0, 5%, 0.05 W, 0201
1
CRCW12061M00FKEA
R11, R43, R83
RES, 1.00 M, 1%, 0.25 W, 1206
3
CRCW0402470RJNED
R12, R13, R17,
R20, R23, R25
RES, 470, 5%, 0.063 W, 0402
6
RT0603BRD071K2L
R14
RES, 1.20 k, 0.1%, 0.1 W, 0603
1
ERA-3AEB242V
R15, R21, R27
RES, 2.40 k, 0.1%, 0.1 W, AEC-Q200 Grade 0, 0603
3
CRCW04022K49FKED
R16, R18, R22,
R24, R48, R72,
R76, R78, R82
RES, 2.49 k, 1%, 0.063 W, 0402
9
CRCW06034K22FKEA
R19, R26
RES, 4.22 k, 1%, 0.1 W, 0603
2
RES, 0, 5%, 0.05 W, 0201
28
ERJ-1GE0R00C
30
R28,
R31,
R42,
R47,
R51,
R56,
R59,
R63,
R67,
R29,
R36,
R44,
R49,
R52,
R57,
R61,
R64,
R68,
R70
R30,
R41,
R46,
R50,
R54,
R58,
R62,
R65,
R69,
CRCW080575R0JNEA
R32, R33, R34,
R35
RES, 75, 5%, 0.125 W, 0805
4
CRCW040249R9FKED
R37, R38, R39,
R40
RES, 49.9, 1%, 0.063 W, 0402
4
CRCW040210K0FKED
R45, R71, R75,
R77, R80
RES, 10.0 k, 1%, 0.063 W, 0402
5
CRCW040213K0FKED
R53, R60
RES, 13.0 k, 1%, 0.063 W, 0402
2
CRCW04021K96FKED
R55, R66, R88
RES, 1.96 k, 1%, 0.063 W, 0402
3
RC0603JR-0710KL
R73
RES, 10 k, 5%, 0.1 W, 0603
1
RC0402JR-070RL
R74
RES, 0, 5%, 0.063 W, 0402
1
CRCW040282R0JNED
R79, R85, R86,
R87
RES, 82, 5%, 0.063 W, 0402
4
CRCW0402130RJNED
R81, R89, R90,
R91
RES, 130, 5%, 0.063 W, 0402
4
CRCW04026K20JNED
R84
RES, 6.2 k, 5%, 0.063 W, 0402
1
ERJ-1GE0R00C
R92
RES, 0, 5%, 0.05 W, 0201
1
CRCW02011K00FKED
R93, R94, R95,
R96
RES, 1.00 k, 1%, 0.05 W, 0201
4
CRCW04024K87FKED
Rs1
RES, 4.87 k, 1%, 0.063 W, 0402
1
KSR221GLFS
S1
Switch, Normally open, 2.3N force, 200k operations, SMD
1
ACM9070-701-2PL
T1
Common Mode Filter for Power Line
1
HX1188FNLT
T2
Transformer, 350 uH, SMT
1
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Bill of Materials
www.ti.com
Table 4. Bill of Materials (continued)
Part Number
Component
Designation
Description
Qty
CDCE925PWR
U1
PROGRAMMABLE 2-PLL VCXO CLOCK SYNTHESIZER
WITH 1.8-V, 2.5-V and 3.3-V LVCMOS OUTPUTS,
PW0016A
1
DP83822RHBR
U2
10/100 Ethernet PHY, RHB0032B
1
TL1963AQKTTRQ1
U3, U4, U5
Single Output Fast Transient Response LDO, 1.5 A,
Adjustable 1.21 to 20 V Output, 2.1 to 20 V Input, 5-pin
DDPAK (KTT), -40 to 125 degC, Green (RoHS & no Sb/Br)
3
TPD4E05U06QDQARQ1
U6, U7
1, 4, 6 CHANNEL PROTECTION SOLUTION FOR
SUPER-SPEED (UP TO 6 GBPS) INTERFACE,
DQA0010A
2
ABM8AIG-25.000MHZ-12-2Z-T3
Y1
Crystal, 25MHz, 12pF, SMD
1
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non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
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www.ti.com/computers
DLP® Products
www.dlp.com
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www.ti.com/omap
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