DP83843BVJE

DP83843 DP83843 PHYTER /LWHUDWXUH1XPEHU61/6% DP83843BVJE PHYTER General Description Features The DP83843BVJE is a full feature Physical Layer device — IEEE 802.3 ENDEC with AUI/10BASE-T transceivers with integrated PMD sublayers to support both 10BASE-T and built-in filters and 100BASE-X Ethernet protocols. — IEEE 802.3u 100BASE-TX compatible - directly drives standard Category 5 UTP, no need for external This VLSI device is designed for easy implementation of 100BASE-TX transceiver 10/100 Mb/s Ethernet LANs. It interfaces directly to Twisted Pair media through an external transformer or to fiber — Fully Integrated and fully compliant ANSI X3.263 TPmedia via industry standard electrical/optical fiber PMD PMD physical sublayer which includes adaptive equaltransceivers. This device also interfaces directly to the ization and BLW compensation MAC layer through the IEEE 802.3u standard Media Inde— IEEE 802.3u 100BASE-FX compatible - connects directpendent Interface (MII), ensuring interoperability between ly to industry standard Electrical/Optical transceivers products from different vendors. — IEEE 802.3u Auto-Negotiation for automatic speed seThe DP83843 is designed with National Semiconductor's lection advanced CMOS process. Its system architecture is based on the integration of several of National's industry proven — IEEE 802.3u compatible Media Independent Interface (MII) with Serial Management Interface core technologies: — Integrated high performance 100 Mb/s clock recovery — IEEE 802.3 ENDEC with AUI/10BASE-T transceiver circuitry requiring no external filters module to provide the 10 Mb/s functions — Full Duplex support for 10 and 100 Mb/s data rates — Clock Recovery/Generator Modules from National's Fast — MII Serial 10 Mb/s mode Ethernet and FDDI products — Fully configurable node/switch and 100Mb/s repeater — FDDI Stream Cipher scrambler/descrambler for modes TP-PMD — Programmable loopback modes for flexible system diag— 100BASE-X physical coding sub-layer (PCS) and control nostics logic that integrates the core modules into a dual speed Ethernet physical layer controller — Flexible LED support — ANSI X3T12 Compliant TP-PMD Transceiver — Single register access to complete PHY status technology with Baseline Wander (BLW) compensation — MDIO interrupt support — Individualized scrambler seed for 100BASE-TX applications using multiple PHYs — Low power consumption for multi-port applications — Small footprint 80-pin PQFP package 10BASE-T or 100BASE-TX MII 10 AND/OR 100 Mb/s ETHERNET MAC OR 100Mb/s REPEATER CONTROLLER DP83843 10/100 Mb/s ETHERNET PHYSICAL LAYER 25 MHz CLOCK MAGNETICS System Diagram RJ-45 10BASE-T or 100BASE-TX STATUS LEDS 100BASE-FX/ AUI ThunderLAN® is a registered trademark of Texas Instruments. TWISTER™ is a trademark of National Semiconductor Corporation. TRI-STATE® is a registered trademark of National Semiconductor Corporation. © 1999 National Semiconductor Corporation www.national.com DP83843BVJE PHYTER 1RY Block Diagram MII HARDWARE CONFIGURATION PINS RX_CL RXD[3:0] RX_DV RX_ER RX_EN CRS COL MDC MDIO TX_EN TX_ER (REPEATER, SERIAL10, SYMBOL, , AN0, AN1,FXEN PHYAD[4:0]) TXD[3:0] TX_CLK SERIAL MANAGEMENT MII INTERFACE/CONTROL RX_DATA RX_CLK TX_DATA TX_DATA 4B/5B ENCODER SCRAMBLER REGISTERS MII 10 MB/S PHY ADDRESS NRZ TO MANCHESTER ENCODER AUTO NEGOTIATION PARALLEL TO SERIAL LINK PULSE GENERATOR NRZ TO NRZI ENCODER BINARY TO MLT-3 ENCODER RX_CLK TX_CLK TRANSMIT CHANNELS & STATE MACHINES 100 MB/S RX_DATA RECEIVE CHANNELS & STATE MACHINES 100 MB/S 4B/5B DECODER NODE/RPTR CODE GROUP ALIGNMENT PCS CONTROL DESCRAMBLER 10BASE-T SERIAL TO PARALLEL 10 MB/S MANCHESTER TO NRZ DECODER CLOCK RECOVERY 100BASE-X NRZI TO NRZ DECODER TRANSMIT FILTER FAR-END-FAULT STATE MACHINE 10/100 COMMON OUTPUT DRIVER AUTO-NEGOTIATION STATE MACHINE LINK PULSE DETECTOR CLOCK RECOVERY MLT-3 TO BINARY DECODER ADAPTIVE EQ AND BLW COMP. RECEIVE FILTER SMART SQUELCH 10/100 COMMON INPUT BUFFER CLOCK GENERATION LED DRIVERS TPTD+/− FXTD/AUITD+/− TXAR100 TPRD+/− FXRD/AUIRD+/− LEDS SYSTEM CLOCK REFERENCE 2 FXSD/CD+/− www.national.com Table of Contents 1.0 2.0 3.0 4.0 5.0 6.0 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 MII Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 10 Mb/s and 100 Mb/s PMD Interface . . . . . . . . . . 6 1.3 Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.4 Device Configuration Interface . . . . . . . . . . . . . . . 8 1.5 LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.6 PHY Address Interface . . . . . . . . . . . . . . . . . . . . 11 1.7 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.8 Power And Ground Pins . . . . . . . . . . . . . . . . . . . 12 1.9 Special Connect Pins . . . . . . . . . . . . . . . . . . . . . . 12 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1 802.3u MII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2 100BASE-TX TRANSMITTER . . . . . . . . . . . . . . . 15 2.3 100BASE-TX RECEIVER . . . . . . . . . . . . . . . . . . 18 2.4 10BASE-T TRANSCEIVER MODULE . . . . . . . . . 22 2.5 100 BASE-FX . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.6 AUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.1 Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.2 PHY Address and LEDs . . . . . . . . . . . . . . . . . . . 30 3.3 Half Duplex vs. Full Duplex . . . . . . . . . . . . . . . . . 31 3.4 100 Mb/s Symbol Mode . . . . . . . . . . . . . . . . . . . . 32 3.5 100BASE-FX Mode . . . . . . . . . . . . . . . . . . . . . . . 32 3.6 10 Mb/s Serial Mode . . . . . . . . . . . . . . . . . . . . . . 32 3.7 10 Mb/s AUI Mode . . . . . . . . . . . . . . . . . . . . . . . . 32 3.8 Repeater vs. Node . . . . . . . . . . . . . . . . . . . . . . . . 33 3.9 Isolate Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.10 Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Clock Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.1 Clock Generation Module (CGM) . . . . . . . . . . . . 34 4.2 100BASE-X Clock Recovery Module . . . . . . . . . . 36 4.3 10 Mb/s Clock Recovery Module . . . . . . . . . . . . . 36 4.4 Reference Clock Connection Options . . . . . . . . . 36 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.1 Power-up / Reset . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.2 Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.3 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . 37 DP83843 Application . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.1 Typical Node Application . . . . . . . . . . . . . . . . . . . 38 6.2 Power And Ground Filtering . . . . . . . . . . . . . . . . 38 6.3 Power Plane Considerations . . . . . . . . . . . . . . . . 38 7.0 8.0 9.0 10.0 11.0 3 User Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.1 Link LED While in Force 100Mb/s Good Link . . . 42 7.2 False Link Indication When in Forced 10Mb/s . . 42 7.3 10Mb/s Repeater Mode . . . . . . . . . . . . . . . . . . . 42 7.4 Resistor Value Modifications . . . . . . . . . . . . . . . 42 7.5 Magnetics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.6 Next Page Toggle Bit Initialization . . . . . . . . . . . 43 7.7 Base Page to Next Page Initial FLP Burst Spacing 43 7.8 100Mb/s FLP Exchange Followed by Quiet . . . . 43 7.9 Common Mode Capacitor for EMI improvement 44 7.10 BAD_SSD Event Lockup . . . . . . . . . . . . . . . . . . 44 Register Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.1 Register Definitions . . . . . . . . . . . . . . . . . . . . . . 45 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . 63 9.1 DC Electrical Specification . . . . . . . . . . . . . . . . . 64 9.2 CGM Clock Timing . . . . . . . . . . . . . . . . . . . . . . 66 9.3 MII Serial Management AC Timing . . . . . . . . . . 66 9.4 100 Mb/s AC Timing . . . . . . . . . . . . . . . . . . . . . . 67 9.5 10 Mb/s AC Timing . . . . . . . . . . . . . . . . . . . . . . . 74 9.6 Auto-Negotiation Fast Link Pulse (FLP) Timing 80 9.7 100BASE-X Clock Recovery Module (CRM) Timing 80 9.8 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 82 9.9 Loopback Timing . . . . . . . . . . . . . . . . . . . . . . . 83 9.10 Isolation Timing . . . . . . . . . . . . . . . . . . . . . . . . 84 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 10.1 FXTD/AUITD+/- Outputs (sourcing AUI levels) . 85 10.2 FXTD/AUITD+/- Outputs (sourcing PECL) . . . . . 85 10.3 CMOS Outputs (MII and LED) . . . . . . . . . . . . . . 85 10.4 TPTD+/- Outputs (sourcing 10BASE-T) . . . . . . . 85 10.5 TPTD+/- Outputs (sourcing 100BASE-TX) . . . . . 85 10.6 Idd Measurement Conditions . . . . . . . . . . . . . . . 85 Package Dimensions inches (millimeters) unless otherwise noted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 www.national.com LED_TX/PHYAD[1] LED_COL/PHYAD[0] FXTD-/AUITD- FXTD+/AUITD+ AUIFX_GND FXSD-/CD- AUIFX_VDD FXSD+/CD+ FXRD-/AUIRD- CP_AGND FXRD+/AUIRD+ CP_AVDD CPTW_DVSS NC CPTW_DVDD NC ATP_GND NC NC TWREF Connection Diagram BGREF 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 NC 62 39 THIN/REPEATER 63 38 LED_FDPOL/PHYAD[4] TW_AGND 64 37 IO_VSS5 TPRD- 65 36 IO_VDD5 VCM_CAP 66 35 MDC MDIO TX_CLK LED_RX/PHYAD[2] LED_LINK/PHYAD[3] TPRD+ 67 34 TW_AVDD 68 33 SERIAL10 69 32 IO_VSS4 SUB_GND1 70 31 TXD[0] CD_GND0 71 30 TXD[1] CD_VDD0 72 29 TXD[2] TPTD- 73 28 TXD[3] IO_VSS3 DP83843BVJE PHYTER 77 24 TX_ER TXAR100 78 23 RX_EN TR_AVDD 79 22 CRS/SYMBOL TR_AGND 80 21 COL/FXEN RX_DV RX_ER RX_CLK 9 10 11 12 13 14 15 16 17 18 19 20 IO_VSS2 8 IO_VDD2 7 RXD[0] 6 RXD[1] 5 RXD[2] 4 RXD[3] 3 PCS_VSS 2 PCS_VDD 1 X1 SUB_GND2 X2 TX_EN IO_VSS1 25 IO_VDD1 76 AN0 IO_VDD3 CD_VDD1 SPEED10 26 AN1 27 75 NC 74 RESET TPTD+ CD_GND1 Order Number DP83843BVJE NS Package Number VJE80 4 www.national.com 1.0 Pin Descriptions The DP83843 pins are classified into the following interface — DEVICE CONFIGURATION INTERFACE categories. Each interface is described in the sections that — LED INTERFACE follow. — PHY ADDRESS INTERFACE — MII INTERFACE — RESET — 10/100 Mb/s PMD INTERFACE — POWER AND GROUND PINS — CLOCK INTERFACE — SPECIAL CONNECT PINS 1.1 MII Interface Signal Name Type Pin # Description MDC I 35 MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO management data input/output serial interface which may be asynchronous to transmit and receive clocks. The maximum clock rate is 2.5 MHz. There is no minimum clock rate. MDIO I/O, Z 34 MANAGEMENT DATA I/O: Bi-directional management instruction/data signal that may be sourced by the station management entity or the PHY. This pin requires a 1.5 kΩ pullup resistor. CRS I/O, Z 22 CARRIER SENSE: This pin is asserted high to indicate the presence of carrier due to receive or transmit activities in 10BASE-T or 100BASE-X Half Duplex modes. (SYMBOL) In Repeater or Full Duplex mode, this pin is asserted high to indicate the presence of carrier due only to receive activity. In Symbol mode this pin indicates the signal detect status of the TP-PMD (active high). COL I/O, Z 21 (FXEN) COLLISION DETECT: Asserted high to indicate detection of collision condition (assertion of CRS due to simultaneous transmit and receive activity) in 10 Mb/s and 100 Mb/s Half Duplex modes. While in 10BASE-T Half Duplex mode with Heartbeat enabled (bit 7, register 18h), this pin is also asserted for a duration of approximately 1 µs at the end of transmission to indicate heartbeat (SQE test). During Repeater mode the heartbeat function is disabled. In Full Duplex mode, for 10 Mb/s or 100 Mb/s operation, this signal is always logic 0. There is no heartbeat function during 10 Mb/s full duplex operation. TX_CLK O, Z 33 TRANSMIT CLOCK: Transmit clock output from the DP83843: 25 MHz nibble transmit clock derived from Clock Generator Module's (CGM) PLL in 100BASE-TX mode. 2.5 MHz transmit clock in 10BASE-T Nibble mode. 10 MHz transmit clock in 10BASE-T Serial mode. TXD[3] I 28 TXD[2] 29 TXD[1] 30 TXD[0] 31 TX_EN I 25 TRANSMIT DATA: Transmit data MII input pins that accept nibble data during normal nibble-wide MII operation at either 2.5 MHz (10BASE-T mode) or 25 MHz (100BASE-X mode). In 10 Mb/s Serial mode, the TXD[0] pin is used as the serial data input pin, and TXD[3:1] are ignored. TRANSMIT ENABLE: Active high input indicates the presence of valid nibble data on TXD[3:0] for both 100 Mb/s or 10 Mb/s nibble mode. In 10 Mb/s Serial mode, active high indicates the presence of valid 10 Mb/s data on TXD[0]. TX_ER I 24 (TXD[4]) TRANSMIT ERROR: In 100 Mb/s mode, when this signal is high and TX_EN is active the HALT symbol is substituted for the actual data nibble. In 10 Mb/s mode, this input is ignored. In Symbol mode (Symbol=0), TX_ER becomes the TXD [4] pin which is the MSB for the transmit 5-bit data symbol. RX_CLK O, Z 18 RECEIVE CLOCK: Provides the recovered receive clock for different modes of operation: 25 MHz nibble clock in 100 Mb/s mode 2.5 MHz nibble clock in 10 Mb/s nibble mode 10 MHz receive clock in 10 Mb/s serial mode 5 www.national.com 1.0 Pin Descriptions (Continued) Signal Name Type RXD[3] O, Z Pin # 12 RXD[2] 13 RXD[1] 14 RXD[0] 15 Description RECEIVE DATA: Nibble wide receive data (synchronous to RX_CLK, 25 MHz for 100BASE-X mode, 2.5 MHz for 10BASE-T nibble mode). Data is driven on the falling edge of RX_CLK. In 10 Mb/s serial mode, the RXD[0] pin is used as the data output pin which is also clocked out on the falling edge of RX_CLK. During 10 Mb/s serial mode RXD[3:1] pins become don't cares. RX_EN I 23 RECEIVE ENABLE: Active high enable for receive signals RXD[3:0], RX_CLK, RX_DV and RX_ER. A low on this input places these output pins in the TRI-STATE mode. For normal operation in a node or switch application, this pin should be pulled high. For operation in a repeater application, this pin may be connected to a repeater controller. RX_ER O, Z 19 RECEIVE ERROR: Asserted high to indicate that an invalid symbol has been detected within a received packet in 100 Mb/s mode. (RXD[4]) In Symbol mode (Symbol = 0), RX_ER becomes RXD[4] which is the MSB for the receive 5-bit data symbol. RX_DV O, Z 20 RECEIVE DATA VALID: Asserted high to indicate that valid data is present on RXD[3:0] for nibble mode and RXD[0] for serial mode. Data is driven on the falling edge of RX_CLK. This pin is not meaningful during Symbol mode. 1.2 10 Mb/s and 100 Mb/s PMD Interface Signal Name Type Pin # TPTD- O 73 TPTD+ (MLT-3 74 Description TRANSMIT DATA: Differential common output driver. This differential output is configurable to either 10BASE-T or 100BASE-TX signaling: 10BASE-T: Transmission of Manchester encoded 10BASE-T packet data as well as Link Pulses (including Fast Link Pulses for Auto-Negotiation purposes.) or 10BASE-T) 100BASE-TX: Transmission of ANSI X3T12 compliant MLT-3 data. The DP83843 will automatically configure this common output driver for the proper signal type as a result of either forced configuration or Auto-Negotiation. TPRD- I 65 TPRD+ (MLT-3 67 RECEIVE DATA: Differential common input buffer. This differential input can be configured to accept either 100BASE-TX or 10BASE-T signaling: 10BASE-T: Reception of Manchester encoded 10BASE-T packet data as well as normal Link Pulses (including Fast Link Pulses for Auto-Negotiation purposes.) or 10BASE-T) 100BASE-TX: Reception of ANSI X3T12 compliant scrambled MLT-3 data. The DP83843 will automatically configure this common input buffer to accept the proper signal type as a result of either forced configuration or Auto-Negotiation. FXTD-/AUITD- O 44 FXTD+/AUITD+ (PECL 43 or AUI) 100BASE-FX or 10 Mb/s AUI TRANSMIT DATA: This configurable output driver supports either 125 Mb/s PECL, for 100BASE-FX applications, or 10 Mb/s AUI signaling. When configured as a 100BASE-FX transmitter this output sources 100BASE-FX standard compliant binary data for direct connection to an optical transceiver. This differential output is enabled only during 100BASE-FX device configuration (see pin definition for FXEN.) When configured as an AUI driver this output sources AUI compatible Manchester encoded data to support typical 10BASE2 or 10BASE5 products. 6 www.national.com 1.0 Pin Descriptions (Continued) Signal Name Type Pin # FXRD-/AUIRD- I 49 FXRD+/AUIRD+ (PECL 50 or Description 100BASE-FX or 10 Mb/s AUI RECEIVE DATA: This configurable input buffer supports either 125 Mb/s PECL, for 100BASE-FX applications, or 10 Mb/s AUI signaling. When configured as a 100BASE-FX receiver this input accepts 100BASE-FX standard compliant binary data direct from an optical transceiver. This differential input is enabled only during 100BASE-FX device configuration (see the pin definition for FXEN). AUI) When configured as an AUI buffer this input receives AUI compatible Manchester data to support typical 10BASE2 or 10BASE5 products. FXSD-/CD- I 47 FXSD+/CD+ (PECL 48 or SIGNAL DETECT or AUI COLLISION DETECT: This configurable input buffer supports either 125 Mb/s PECL, for 100BASE-FX applications, or 10 Mb/s AUI signaling. When configured as a 100BASE-FX receiver this input accepts indication from the 100BASE-FX PMD transceiver upon detection of a receive signal from the fiber media. This pin is only active during 100BASE-FX operation(see the pin definition for FXEN). AUI) When configured as an AUI buffer this input receives AUI compatible Manchester data to support typical 10BASE2 or 10BASE5 products. THIN I/O, Z 63 THIN AUI MODE: This output allows for control of an external CTI coaxial transceiver connected through the AUI. This pin is controlled by writing to bit 3 of the 10BTSCR register (address 18h). The THIN pin may also be used as a user configurable output control pin. I (current reference) 78 100 Mb/s TRANSMIT AMPLITUDE REFERENCE CONTROL: Reference current allowing adjustment of the TPTD+/− output amplitude during 100BASE-TX operation. (REPEATER) TXAR100 By placing a resistor between this pin and ground or VCC, a reference current is set up which dictates the output amplitude of the 100BASE-TX MLT-3 transmit signal. Connecting a resistor to VCC will increase the transmit amplitude while connecting a resistor to ground will decrease the transmit amplitude. While the value of the resistor should be evaluated on a case by case bases, the DP83843 was designed to produce an amplitude close to the required range of 2V pk-pk differential ± 5% as measured across TD+/− while driving a typical 100Ω differential load without a resistor connected to this pin. Therefore this pin is allowed to float in typical applications. This current reference is only recognized during 100BASE-TX operation and has no effect during100BASE-FX,10BASE-T, or AUI modes of operation. TWREF I 60 TWISTER REFERENCE RESISTOR: External reference current adjustment, via a resistor to TW_AGND, which controls the TP-PMD receiver equalization levels. The value of this resistor is 70k ± 1%. BGREF I (current reference) 61 BANDGAP REFERENCE: External current reference resistor for internal bandgap circuitry. The value of this resistor is 4.87k ± 1%. VCM_CAP I 66 COMMON MODE BYPASS CAPACITOR: External capacitor to improve common mode filtering for the receive signal. It is recommended that a .0033µF in parallel with a .10µF capacitor be used, see Figure 23. 7 www.national.com 1.0 Pin Descriptions (Continued) 1.3 Clock Interface Signal Name Type Pin # Description X1 I 9 CRYSTAL/OSCILLATOR INPUT: This pin is the primary clock reference input for the DP83843 and must be connected to a 25 MHz 0.005% (50 ppm) clock source. The DP83843 device supports either an external crystal resonator connected across pins X1 and X2, or an external CMOS-level oscillator source connected to pin X1 only. For 100 Mb/s repeater applications, X1 should be tied to the common 25 MHz transmit clock reference. Refer to section 4.4 for further detail relating to the clock requirements of the DP83843. Refer to section 4.0 for clock source specifications. X2 O 8 CRYSTAL/OSCILLATOR OUTPUT PIN: This pin is used in conjunction with the X1 pin to connect to an external 25 MHz crystal resonator device. This pin must be left unconnected if an external CMOS oscillator clock source is utilized. For more information see the definition for pin X1. Refer to section 2.8 for further detail. 1.4 Device Configuration Interface Signal Name AN0 Type I Pin # 4 (3-level) AN1 I (3-level) 3 Description AN0: This is a three level input pin (1, M, 0) that works in conjunction with the AN1 pin to control the forced or advertised operating mode of the DP83843 according to the following table. The value on this pin is set by connecting the input pin to GND (0), VCC (1), or leaving it unconnected (M.) The unconnected state, M, refers to the mid-level (VCC/2) set by internal resistors. The value set at this input is latched into the DP83843 at power-up/reset. AN1 0 1 M M AN0 M M 0 1 Forced Mode 10BASE-T, Half-Duplex without Auto-Negotiation 10BASE-T, Full Duplex without Auto-Negotiation 100BASE-X, Half-Duplex without Auto-Negotiation 100BASE-X, Full Duplex without Auto-Negotiation AN1 M AN0 M 0 0 0 1 1 0 1 1 Advertised Mode All capable (i.e. Half-Duplex & Full Duplex for 10BASE-T and 100BASE-TX) advertised via Auto-Negotiation 10BASE-T, Half-Duplex & Full Duplex advertised via AutoNegotiation 100BASE-TX, Half-Duplex & Full Duplex advertised via Auto-Negotiation 10BASE-T & 100BASE-TX, Half-Duplex advertised via AutoNegotiation 10 BASE-T, Half-Duplex advertised via Auto-Negotiation AN1: This is a three-level input pin (i.e., 1, M, 0) that works in conjunction with the AN0 pin to control the forced or advertised operating mode of the DP83843 according to the table given in the AN0 pin description above. The value on this pin is set by connecting the input pin to GND (0), VCC (1), or leaving it unconnected (M.) The value at this input is latched into the DP83843 at power-up, hardware or software reset. 8 www.national.com 1.0 Pin Descriptions (Continued) Signal Name REPEATER Type I/O Pin # 63 (THIN) Description REPEATER/NODE MODE: Selects 100 Mb/s Repeater mode when set high and node mode when set low. When set in Repeater mode the DP83843 only supports 100 Mb/s data rates. In Repeater mode (or Node mode with Full Duplex configured), the Carrier Sense (CRS) output from the DP83843 is asserted due to receive activity only. In Half Duplex Node mode, CRS is asserted due to either receive or transmit activity. During repeater mode the heartbeat function(SQE) is forced off. The Carrier Integrity Monitor (CIM) function is automatically enabled when this pin is set high (repeater mode) and disabled when this pin is set low (node mode) in order to facilitate 802.3u CIM requirements. There is an internal pullup resistor for this pin which is active during the powerup/reset period. If this pin is left floating externally, then the device will configure to 100 Mb/s Repeater mode as a result of power-up/reset. This pin must be externally pulled low (typically 10 kΩ) in order to configure the DP83843 for Node operation. The value of this input is latched into the DP83843 at power-up, hardware or software reset. SYMBOL/ I/O, Z 22 (CRS) SYMBOL MODE: This active low input allows 100 Mb/s transmit and receive data streams to bypass all of the transmit and receive operations when set low. Note that the PCS signals (CRS, RX_DV, RX_ER, and COL) have no meaning during this mode. During Symbol operation, pins RX_ER/RXD[4] and TX_ER/TXD[4] are used as the MSB of the 5 bit RX and TX data symbols. There is an internal pullup resistor for this pin which is active during the powerup/reset period. If this pin is left floating externally, then the device will configure to normal mode as a result of power-up/reset. This pin must be externally pulled low (typically 10 kΩ) in order to configure the DP83843 for Symbol mode operation. In Symbol mode this pin will indicate the signal detect status of the TP-PMD (active high). This mode has no effect on 10Mb/s operation. The value at this input is latched into the DP83843 at power-up, hardware or software reset. SERIAL10 I 69 10BASE-T SERIAL/NIBBLE SELECT: With this active low input selected, transmit and receive data are exchanged serially at a 10 MHz clock rate on the least significant bits of the nibble-wide MII data buses, pins TXD[0] and RXD[0] respectively. This mode is intended for use with the DP83843 connected to a MAC using a 10 Mb/s serial interface. Serial operation is not supported in 100 Mb/s mode, therefore this input is ignored during 100 Mb/s operation. There is an internal pullup resistor for this pin which is active during the powerup/reset period. If this pin is left floating externally, then the device will configure to normal mode as a result of power-up/reset. This pin must be externally pulled low (typically 10 kΩ) in order to configure the DP83843 for Serial MII operation when running at 10 Mb/s. The value at this input is latched into the DP83843 at power-up, hardware or software reset. FXEN/ (COL) I/O, Z 21 FIBER ENABLE: This active low input allows 100 Mb/s transmit and receive data streams to bypass the scrambler and descrambler circuits when selected. All PCS signaling remains active and unaffected during this mode. During this mode, the internal 100 Mb/s transceiver is disabled, and NRZI data is transmitted and received via the FXTD/AUITD+/− and FXRD/AUIRD+/− pins. There is an internal pullup resistor for this pin which is active during the powerup/reset period. If this pin is left floating externally, then the device will configure to normal mode as a result of power-up/reset. This pin must be externally pulled low (typically 10 kΩ) in order to configure the DP83843 for 100BASE-FX operation. The value at this input is latched into the DP83843 at power-up, hardware or software reset. 9 www.national.com 1.0 Pin Descriptions (Continued) 1.5 LED Interface These outputs can be used to drive LEDs directly, or can be used to provide status information to a network management device. Refer to section 2.2 for a description of how to generate LED indication of 100 Mb/s mode. The active state of each LED output driver is dependent on the logic level sampled by the corresponding PHY address input upon power-up/reset. For example, if a given PHYAD Signal Name LED_COL Type I/O input is resistively pulled low then the corresponding LED output will be configured as an active high driver. Conversely, if a given PHYAD input is resistively pulled high then the corresponding LED output will be configured as an active low driver (refer to section 5.0.1 for further details). Note that these outputs are standard CMOS voltage drivers and not open-drain. Pin # 42 (PHYAD[0]) Description COLLISION LED: Indicates the presence of collision activity for 10 Mb/s and 100 Mb/s Half Duplex operation. This LED has no meaning for 10 Mb/s or 100 Mb/s Full Duplex operation and will remain deasserted. During 10 Mb/s half duplex mode this pin will be asserted after data transmission due to the heartbeat function. The DP83843 incorporates a “monostable” function on the LED_COL output. This ensures that even collisions generate adequate LED ON time (approximately 50 ms) for visibility. LED_TX I/O 41 (PHYAD[1]) TRANSMIT LED: Indicates the presence of transmit activity for 10 Mb/s and 100 Mb/s operation. If bit 7 (LED_Trans_MODE) of the PHYCTRL register (address 19h) is set high, then the LED_TX pin function is changed to indicate the status of the Disconnect function as defined by the state of bit 4 (CIM_STATUS) in the 100 Mb/s PCS configuration & status register (address 16h). See register definition for complete description of alternative operation. The DP83843 incorporates a “monostable” function on the LED_TX output. This ensures that even minimum size packets generate adequate LED ON time (approximately 50 ms) for visibility. LED_RX I/O 40 (PHYAD[2]) RECEIVE LED: Indicates the presence of any receive activity for 10 Mb/s and 100 Mb/s operation. See register definitions(PHYCTRL register and PCSR register) for complete descriptions of alternative operation. The DP83843 incorporates a “monostable” function on the LED_RX output. This ensures that even minimum size packets generate adequate LED active time (approximately 50 ms) for visibility. LED_LINK I/O 39 (PHYAD[3]) LINK LED: Indicates good link status for 10 Mb/s and 100 Mb/s operation. In 100BASE-T mode, link is established as a result of input receive amplitude compliant with TP-PMD specifications which will result in internal generation of Signal Detect as well as an internal signal from the Clock Recovery Module (cypher & sync). LED_LINK will assert after these internal signals have remained asserted for a minimum of 500µs. Once Link is established, then cipher & sync are no longer sampled and the Link will remain valid as long as Signal Detect is valid. LED_LINK will deassert immediately following the deassertion of the internal Signal Detect. 10 Mb/s link is established as a result of the reception of at least seven consecutive normal Link Pulses or the reception of a valid 10BASE-T packet which will cause the assertion of LED_LINK. LED_LINK will deassert in accordance with the Link Loss Timer as specified in IEEE 802.3. In 100BASE-FX mode, link is established as a result of the assertion of the Signal detect input to the DP83843. LED_LINK will assert after Signal Detect has remained asserted for a minimum of 500µS. LED_LINK will deassert immediately following the deassertion of signal detect. The link function is disabled during AUI operation and LED_LINK is asserted. LED_FDPOL I/O 38 (PHYAD[4]) FULL DUPLEX LED: Indicates Full Duplex mode status for 10 Mb/s or 100 Mb/s operation. This pin can be configured to indicate Polarity status for 10 Mb/s operation. If bit 6 (LED_DUP_MODE) in the PHYCTRL Register (address 19h) is deasserted, the LED_FDPOL pin function is changed to indicate Polarity status for 10 Mb/s operation. The DP83843 automatically compensates for 10BASE-T polarity inversion. 10BASE-T polarity inversion is indicated by the assertion of LED_FDPOL. SPEED10 O 5 SPEED 10 Mb/s: Indicates 10 Mb/s operation when high. Indicates 100 Mb/s operation when low. This pin can be used to drive peripheral circuitry such as an LED indicator. 10 www.national.com 1.0 Pin Descriptions (Continued) 1.6 PHY Address Interface The DP83843 PHYAD[4:0] inputs provide up to 32 unique PHY address options. An address selection of all zeros Signal Name Type PHYAD[0] (00000) will result in a PHY isolation condition as a result of power-on/reset, as specified in IEEE 802.3u. Pin # I/O 42 (LED_COL) Description PHY ADDRESS [0]: PHY address sensing pin for multiple PHY applications. PHY address sensing is achieved by strapping a pull-up/pull-down resistor (typically 10 kΩ) to this pin as required. The pull-up/pull-down status of this pin is latched into the PHYCTRL register (address 19h, bit 0) during power up/reset. PHYAD[1] I/O 41 (LED_TX) PHY ADDRESS [1]: PHY address sensing pin for multiple PHY applications. PHY address sensing is achieved by strapping a pull-up/pull-down resistor (typically 10 kΩ) to this pin as required. The pull-up/pull-down status of this pin is latched into the PHYCTRL register (address 19h, bit 1) during power up/reset. PHYAD[2] I/O 40 (LED_RX) PHY ADDRESS [2]: PHY address sensing pin for multiple PHY applications. PHY address sensing is achieved by strapping a pull-up/pull-down resistor (typically 10 kΩ) to this pin as required. The pull-up/pull-down status of this pin is latched into the PHYCTRL register (address 19h, bit 2) during power up/reset. PHYAD[3] I/O 39 (LED_LINK) PHY ADDRESS [3]: PHY address sensing pin for multiple PHY applications. PHY address sensing is achieved by strapping a pull-up/pull-down resistor (typically 10 kΩ) to this pin as required. The pull-up/pull-down status of this pin is latched into the PHYCTRL register (address 19h, bit 3) during power up/reset. PHYAD[4] I/O 38 (LED_FDPOL) PHY ADDRESS [4]: PHY address sensing pin for multiple PHY applications. PHY address sensing is achieved by strapping a pull-up/pull-down resistor (typically 10 kΩ) to this pin as required. The pull-up/pull-down status of this pin is latched into the PHYCTRL register (address 19h, bit 4) during power up/reset. 1.7 Reset Signal Name RESET Type I Pin # 1 Description RESET: Active high input that initializes or reinitializes the DP83843. Asserting this pin will force a reset process to occur which will result in all internal registers reinitializing to their default states as specified for each bit in section 7.0, and all strapping options are reinitialized. Refer to section 5.0 for further detail regarding reset. 11 www.national.com 1.0 Pin Descriptions (Continued) 1.8 Power And Ground Pins supply pairs. This grouping allows for optimizing the layout and filtering of the power and ground supplies to this The power (VCC) and ground (GND) pins of the DP83843 device. are grouped in pairs into three categories--TTL/CMOS Input pairs, Transmit/Receive supply pairs, and Internal Signal Name Pin # Description TTL/CMOS INPUT/OUTPUT SUPPLY PAIRS IO_VDD1 6 IO_VSS1 7 TTL Input/Output Supply #1 IO_VDD2 16 IO_VSS2 17 IO_VDD3 26 IO_VSS3 27 IO_VSS4 32 TTL Input/Output Supply #4 IO_VDD5 36 TTL Input/ Output Supply #5 IO_VSS5 37 PCS_VDD 10 PCS_VSS 11 TTL Input/Output Supply #2 TTL Input /Output Supply #3 Physical Coding Sublayer Supply TRANSMIT/RECEIVE SUPPLY PAIRS AUIFX_VDD 46 AUIFX_GND 45 TR_AVDD 79 TR_AGND 80 TW_AVDD 68 TW_AGND 64 CD_VDD0 72 CD_GND0 71 CD_VDD1 76 CD_GND1 75 AUI Power Supply 10 Mb/s Supply 100 Mb/s Power Supply Common Driver Supply Common Driver Supply INTERNAL SUPPLY PAIRS CP_AVDD 52 CRM/CGM Supply CP_AGND 51 CPTW_DVDD 54 CPTW_DVSS 53 ATP_GND 57 100BASE-T PMD Supply SUB_GND1, 70 100BASE-T PMD Supply SUB_GND2 77 CRM/CGM Supply 1.9 Special Connect Pins Signal Name NC Type Pin # 2,55,56, 58,59, 62 Description NO CONNECT: These pins are reserved for future use. Leave them unconnected (floating). 12 www.national.com 2.0 Functional Description 2.1 802.3u MII The DP83843 incorporates the Media Independent Interface (MII) as specified in clause 22 of the IEEE 802.3u standard. This interface may be used to connect PHY devices to a 10/100 Mb/s MAC or a 100 Mb/s repeater controller. This section describes both the serial MII management interface as well as the nibble wide MII data interface. The management interface of the MII allows the configuration and control of multiple PHY devices, the gathering of status and error information, and the determination of the type and abilities of the attached PHY(s). The nibble wide MII data interface consists of a receive bus and a transmit bus each with control signals to facilitate data transfer between the PHY and the upper layer (MAC or repeater). and no minimum rate. The MDIO line is bi-directional and may be shared by up to 32 devices. The MDIO frame format is shown in Table 1. The MDIO pin requires a pull-up resistor (1.5 kΩ) which, during IDLE and turnaround, will pull MDIO high. In order to initialize the MDIO interface, the Station Management Entity (SME) sends a sequence of 32 contiguous logic ones on MDIO to provide the DP83843 with a sequence that can be used to establish synchronization. This preamble may be generated either by driving MDIO high for 32 consecutive MDC clock cycles, or by simply allowing the MDIO pull-up resistor to pull the MDIO pin high during which time 32 MDC clock cycles are provided. In addition 32 MDC clock cycles should be used if an invalid start, op code, or turnaround bit is detected. The DP83843 waits until it has received this preamble The DP83843 supports the TI ThunderLAN® MII interrupt sequence before responding to any other transaction. function. For further information please contact your local Once the DP83843 serial management port has initialized National sales representative. no further preamble sequencing is required until after a power-on/reset has occurred. 2.1.1 Serial Management Register Access The serial MII specification defines a set of thirty-two 16-bit status and control registers that are accessible through the serial management data interface pins MDC and MDIO. The DP83843 implements all the required MII registers as well as several optional registers. These registers are fully described in Section 7. A description of the serial management access protocol follows. The Start code is indicated by a pattern. This assures the MDIO line transitions from the default idle line state. Turnaround is an idle bit time inserted between the Register Address field and the Data field. To avoid contention, no device actively drives the MDIO signal during the first bit of Turnaround during a read transaction. The addressed DP83843 drives the MDIO with a zero for the second bit of turnaround and follows this with the required data. Figure 2 2.1.2 Serial Management Access Protocol shows the timing relationship between MDC and the MDIO The serial control interface consists of two pins, Manage- as driven/received by the Station Management Entity and ment Data Clock (MDC) and Management Data Input/Out- the DP83843 (PHY) for a typical register read access. put (MDIO). MDC has a maximum clock rate of 2.5 MHz Table 1. Typical MDIO Frame Format MII Management Serial Protocol Read Operation Write Operation MDC MDIO Z Z (SME) 0 1 0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Z Idle Start Opcode (Write) PHY Address (PHYAD = 0Ch) Register Address (00h = BMCR) Register Data TA Z Idle Figure 1. Typical MDC/MDIO Write Operation MDC MDIO Z Z (SME) Z MDIO Z (PHY) Z Idle 0 1 1 0 0 1 1 0 0 0 0 0 0 0Z 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 Start Opcode (Read) PHY Address (PHYAD = 0Ch) Register Address (00h = BMCR) TA Register Data Z Idle Figure 2. Typical MDC/MDIO Read Operation 13 www.national.com 2.0 Functional Description (Continued) For write transactions, the Station Management Entity writes data to an addressed DP83843 eliminating the requirement for MDIO Turnaround. The Turnaround time is filled by the management entity inserting for these two bits. Figure 1 shows the timing relationship for a typical MII register write access. 2.1.3 Preamble Suppression The DP83843 supports a Preamble Suppression mode as indicated by a one in bit 6 of the Basic Mode Status Register (BMSR, address 01h). If the Station Management Entity (i.e. MAC or other management controller) determines that all PHYs in the system support Preamble Suppression by returning a one in this bit, then the Station Management Entity need not generate preamble for each management transaction. The DP83843 requires a single initialization sequence of 32 bits of preamble following power-up/hardware reset. This requirement is generally met by the mandatory pull-up resistor on MDIO in conjunction with a continuous MDC, or the management access made to determine whether Preamble Suppression is supported. While the DP83843 requires an initial preamble sequence of 32 bits for management initialization, it does not require a full 32 bit sequence between each subsequent transaction. A minimum of one idle bit between management transactions is required as specified in IEEE 802.3u. 2.1.4 PHY Address Sensing The DP83843 can be set to respond to any of the possible 32 PHY addresses. Each DP83843 connected to a common serial MII must have a unique address. It should be noted that while an address selection of all zeros will result in PHY Isolate mode, this will not effect serial management access. occur during half-duplex operation when both a transmit and receive operation occur simultaneously. 2.1.6 Collision Detect For Half Duplex, a 10BASE-T or 100BASE-X collision is detected when the receive and transmit channels are active simultaneously. Collisions are reported by the COL signal on the MII. If the DP83843 is transmitting in 10 Mb/s mode when a collision is detected, the collision is not reported until seven bits have been received while in the collision state. This prevents a collision being reported incorrectly due to noise on the network. The COL signal remains set for the duration of the collision. If a collision occurs during a receive operation, it is immediately reported by the COL signal. When heartbeat is enabled (only applicable to 10 Mb/s operation), approximately 1 µs after the transmission of each packet, a Signal Quality Error (SQE) signal of approximately 10 bit times is generated (internally) to indicate successful transmission. SQE is reported as a pulse on the COL signal of the MII. 2.1.7 Carrier Sense Carrier Sense (CRS) may be asserted due to receive activity, once valid data is detected via the Smart Squelch function during 10 Mb/s operation. For 10 Mb/s Half Duplex operation, CRS is asserted during either packet transmission or reception. For 10 Mb/s Full Duplex operation, CRS is asserted only due to receive activity. CRS is deasserted following an end of packet. In Repeater mode (pin 63/bit 9, register address 19h), CRS The DP83843 provides five PHY address pins, the state of is only asserted due to receive activity. which are latched into the PHYCTRL register (address 2.1.8 MII Isolate Mode 19h) at system power-up/reset. These pins are described A 100BASE-X PHY connected to the mechanical MII interin Section 2.8. For further detail relating to the latch-in timface specified in IEEE 802.3u is required to have a default ing requirements of the PHY address pins, as well as the value of one in bit 10 of the Basic Mode Control Register other hardware configuration pins, refer to Section 3.10. (BMCR, address 00h). The DP83843 will set this bit to one 2.1.5 Nibble-wide MII Data Interface if the PHY Address is set to 00000 upon power-up/hardClause 22 of the IEEE 802.3u specification defines the ware reset. Otherwise, the DP83843 will set this bit to zero Media Independent Interface. This interface includes a upon power-up/hardware reset. dedicated receive bus and a dedicated transmit bus. These two data buses, along with various control and indicate signals, allow for the simultaneous exchange of data between the DP83843 and the upper layer agent (MAC or repeater). With bit 10 in the BMCR set to one, the DP83843 does not respond to packet data present at TXD[3:0], TX_EN, and TX_ER inputs and presents a high impedance on the TX_CLK, RX_CLK, RX_DV, RX_ER, RXD[3:0], COL, and The receive interface consists of a nibble wide data bus CRS outputs. The DP83843 will continue to respond to all RXD[3:0], a receive error signal RX_ER, a receive data serial management transactions over the MII. valid flag RX_DV, and a receive clock RX_CLK for synchro- While in Isolate mode, the TPTD+/− and FXTD/AUITD+/− nous transfer of the data. The receive clock can operate at outputs are dependent on the current state of Auto-Negotieither 2.5 MHz to support 10 Mb/s operation modes or at ation. The DP83843 can Auto-Negotiate or parallel detect 25 MHz to support 100 Mb/s operational modes. to a specific technology depending on the receive signal at The transmit interface consists of a nibble wide data bus the TPRD+/− inputs. A valid link can be established for TXD[3:0], a transmit error flag TX_ER, a transmit enable either TPRD or FXRD/AUI even when the DP83843 is in control signal TX_EN, and a transmit clock TX_CLK which Isolate mode. runs at either 2.5 MHz or 25 MHz. It is recommended that the user have a basic understandAdditionally, the MII includes the carrier sense signal CRS, ing of clause 22 of the 802.3u standard. as well as a collision detect signal COL. The CRS signal asserts to indicate the reception of data from the network or as a function of transmit data in Half Duplex mode. The COL signal asserts as an indication of a collision which can 14 www.national.com 2.0 Functional Description (Continued) 2.2 100BASE-TX TRANSMITTER The 100BASE-TX transmitter consists of several functional blocks which convert synchronous 4-bit nibble data, as provided by the MII, to a scrambled MLT-3 125 Mb/s serial data stream. Because the 100BASE-TX TP-PMD is integrated, the differential output pins, TPTD+/−, can be directly routed to the AC coupling magnetics. The block diagram in Figure 3 provides an overview of each functional block within the 100BASE-TX transmit section. — Code-group Encoder and Injection block (bypass option) — Scrambler block (bypass option) — NRZ to NRZI encoder block — Binary to MLT-3 converter / Common Driver The bypass option for the functional blocks within the 100BASE-X transmitter provides flexibility for applications such as 100 Mb/s repeaters where data conversion is not always required. The DP83843 implements the 100BASEX transmit state machine diagram as specified in the IEEE 802.3u Standard, Clause 24. The Transmitter section consists of the following functional blocks: TX_CLK TXD[3:0] / TX_ER 25MHZ CODE-GROUP ENCODER & INJECTOR BP_4B5B MUX SCRAMBLER BP_SCR BP_TX MUX MUX PARALLEL TO SERIAL NRZ TO NRZI ENCODER 100BASE-X LOOPBACK BINARY TO MLT-3 / COMMON DRIVER TPTD +/− Figure 1. 100BASE-TX Transmit Block Diagram – Code-group Encoding and Injection 15 www.national.com 2.0 Functional Description (Continued) The code-group encoder converts 4 bit (4B) nibble data generated by the MAC into 5 bit (5B) code-groups for transmission. This conversion is required to allow control data to be combined with packet data code-groups. Refer to Table 2 for 4B to 5B code-group mapping details. 2.2.1 Scrambler The scrambler is required to control the radiated emissions at the media connector and on the twisted pair cable (for 100BASE-TX applications). By scrambling the data, the total energy launched onto the cable is randomly distribThe code-group encoder substitutes the first 8 bits of the uted over a wide frequency range. Without the scrambler, MAC preamble with a J/K code-group pair (11000 10001) energy levels at the PMD and on the cable could peak upon transmit. The code-group encoder continues to beyond FCC limitations at frequencies related to repeating replace subsequent 4B preamble and data nibbles with 5B sequences (i.e., continuous transmission of IDLEs). corresponding 5B code-groups. At the end of the transmit The scrambler is configured as a closed loop linear feedpacket, upon the deassertion of Transmit Enable signal back shift register (LFSR) with an 11-bit polynomial. The from the MAC or Repeater, the code-group encoder injects output of the closed loop LFSR is combined with the NRZ the T/R code-group pair (01101 00111) indicating the end 5B data from the code-group encoder via an X-OR logic of frame. function. The result is a scrambled data stream with suffiAfter the T/R code-group pair, the code-group encoder continuously injects IDLEs into the transmit data stream until the next transmit packet is detected (reassertion of Transmit Enable). cient randomization to decrease radiated emissions at certain frequencies by as much as 20 dB. The DP83843 uses the PHYID as determined by the PHYAD [4:0] pins to set a unique seed value for the scrambler so that the total energy The DP83843 also incorporates a special injection function produced by a multi-PHY application (i.e. repeater) distribwhich allows for fixed transmission of special repeating pat- utes the energy out of phase across the spectrum and terns for testing purposes. These special patterns are not helps to reduce overall electro-magnetic radiation. delimited with Start of Stream Delimiter (SSD) or End of The scrambler is automatically bypassed when the Stream Delimiter (ESD) code-groups and should not be DP83843 is placed in FXEN mode via hardware or, alternaenabled during normal network connectivity. tively, controlled by bit 12 of LBR (address 17h) via softThese patterns, selectable via bits [8:7] of PCRS (address ware. 16h), include: 2.2.2 NRZ to NRZI Encoder 8=0, 7=0: Normal operation (injection disabled) After the transmit data stream has been scrambled and serialized, the data must be NRZI encoded in order to com8=0, 7=1: Transmit repeating FEFI pattern ply with the TP-PMD standard for 100BASE-TX transmis8=1, 7=0: Transmit repeating 1.28 µs period squarewave sion over Category-5 unshielded twisted pair cable. There is no ability to bypass this block within the DP83843. 8=1, 7=1: Transmit repeating 160 ns period squarewave Note that these patterns will be routed through the transmit scrambler and become scrambled (and therefore potentially less useful) unless the scrambler is bypassed via bit 12 of LBR (address 17h). It should be noted that if the scrambler is bypassed by forcing the FXEN pin (and subsequently resetting the device) the TPTD+/− outputs will become disabled and the test pattern data will be routed to the FXTD/AUITD+/− outputs. Additionally, the test patterns will not be generated if the DP83843 is in symbol mode. 2.2.3 Binary to MLT-3 Convertor / Common Driver The Binary to MLT-3 conversion is accomplished by converting the serial binary datastream output from the NRZI encoder into two binary data streams with alternately phased logic one events. These two binary streams are then fed to the twisted pair output driver which converts these streams to current sources and alternately drives either side of the transmit transformer primary winding resulting in a minimal current (20 mA max) MLT-3 signal. Refer to Figure 4 . binary_in binary_plus Q D Q binary_minus differential MLT-3 CP binary_plus binary_in COMMON DRIVER MLT-3 binary_minus Figure 1. Binary to MLT-3 conversion 16 www.national.com 2.0 Functional Description (Continued) Table 2. 4B5B Code-Group Encoding/Decoding Name PCS 5B Code-group MII 4B Nibble Code 0 11110 0000 1 01001 0001 2 10100 0010 3 10101 0011 4 01010 0100 5 01011 0101 6 01110 0110 7 01111 0111 8 10010 1000 9 10011 1001 A 10110 1010 DATA CODES B 10111 1011 C 11010 1100 D 11011 1101 E 11100 1110 F 11101 1111 IDLE AND CONTROL CODES H 00100 Halt code-group - Error code I 11111 Inter-Packet Idle - 0000 (Note 1) J 11000 First Start of Packet - 0101 (Note 1) K 10001 Second Start of Packet - 0101 (Note 1) T 01101 First End of Packet - 0000 (Note 1) R 00111 Second End of Packet - 0000 (Note 1) V 00000 0110 or 0101 (Note 2) V 00001 0110 or 0101 (Note 2) V 00010 0110 or 0101 (Note 2) V 00011 0110 or 0101 (Note 2) V 00101 0110 or 0101 (Note 2) V 00110 0110 or 0101 (Note 2) V 01000 0110 or 0101 (Note 2) V 01100 0110 or 0101 (Note 2) V 10000 0110 or 0101 (Note 2) V 11001 0110 or 0101 (Note 2) INVALID CODES Note 1: Control code-groups I, J, K, T and R in data fields will be mapped as invalid codes, together with RX_ER asserted. Note 2: Normally, invalid codes (V) are mapped to 6h on RXD[3:0] with RX_ER asserted. If the CODE_ERR bit in the PCS (bit 3, register address 16h) is set, the invalid codes are mapped to 5h on RXD[3:0] with RX_ER asserted. Refer to Section 4.14 for further detail. 17 www.national.com 2.0 Functional Description (Continued) The 100BASE-TX MLT-3 signal sourced by the TPTD+/− common driver output pins is slow rate controlled. This should be considered when selecting AC coupling magnetics to ensure TP-PMD compliant transition times (3 ns < Tr < 5ns). The 100BASE-TX transmit TP-PMD function within the DP83843 is capable of sourcing only MLT-3 encoded data. Binary output from the TPTD+/− outputs is not possible in 100 Mb/s mode. 2.2.4 TX_ER Assertion of the TX_ER input while the TX_EN input is also asserted will cause the DP83843 to substitute HALT codegroups for the 5B data present at TXD[3:0]. However, the SSD (/J/K/) and ESD (/T/R/) will not be substituted with Halt code-groups. As a result, the assertion of TX_ER while TX_EN is asserted will result in a frame properly encapsulated with the /J/K/ and /T/R/ delimiters which contains HALT code-groups in place of the data code-groups. 2.2.5 TXAR100 such as 100 Mb/s repeaters where data conversion is not always required. 2.3.1 Input and Base Line Wander Compensation Unlike the DP83223V TWISTER™, the DP83843 requires no external attenuation circuitry at its receive inputs, TPRD+/−. The DP83843 accepts TP-PMD compliant waveforms directly, requiring only a 100Ω termination plus a simple 1:1 transformer. The DP83843 also requires external capacitance to VCC at the VCM_CAP pin (refer to Figure 23). This establishes a solid common mode voltage that is needed since the TPRD pins are used in both 10 Mb/s and 100 Mb/s modes. The DP83843 is completely ANSI TP-PMD compliant because it compensates for baseline wander. The BLW compensation block can successfully recover the TP-PMD defined “killer” pattern and pass it to the digital adaptive equalization block. Baseline wander can generally be defined as the change in the average DC content, over time, of an AC coupled digital transmission over a given transmission medium. (i.e. copper wire). The transmit amplitude of the signal presented at the TPTD+/− output pins can be controlled by varying the value of resistance between TXAR100 and system GND. This Baseline wander results from the interaction between the TXAR100 resistor sets up a reference current that deter- low frequency components of a bit stream being transmitted and the frequency response of the AC coupling compomines the final output current at TPTD+/−. For 100Ω Category-5 UTP cable implementations, the nent(s) within the transmission system. If the low frequency TXAR100 resistor may be omitted as the DP83843 was content of the digital bit stream goes below the low fredesigned to source a nominal 2V pk-pk differential transmit quency pole of the AC coupling transformers then the amplitude with this pin left floating. Setting the transmit droop characteristics of the transformers will dominate amplitude to 2V pk-pk differential (MLT-3) as measured resulting in potentially serious baseline wander. across the RJ45-8 transmit pins is critical for complying It is interesting to note that the probability of a baseline wanwith the IEEE/ANSI TP-PMD specification of 2.0V pk-pk der event serious enough to corrupt data is very low. In fact, it is reasonable to virtually bound the occurrence of a basedifferential ± 5%. line wander event serious enough to cause bit errors to a 2.3 100BASE-TX RECEIVER legal but premeditated, artificially constructed bit sequence The 100BASE-TX receiver consists of several functional loaded into the original MAC frame. Several studies have blocks which convert the scrambled MLT-3 125 Mb/s serial been conducted to evaluate the probability of various basedata stream to synchronous 4-bit nibble data that is pro- line wander events for FDDI transmission over copper. Convided to the MII. Because the 100BASE-TX TP-PMD is tact the X3.263 ANSI group for further information. integrated, the differential input pins, TPRD+/−, can be 2.3.2 Signal Detect directly routed to the AC coupling magnetics. The signal detect function of the DP83843 is incorporated See Figure 5 for a block diagram of the 100BASE-TX to meet the specifications mandated by the ANSI FDDI TPreceive function. This provides an overview of each funcPMD Standard as well as the IEEE 802.3 100BASE-TX tional block within the 100BASE-TX receive section. Standard for both voltage thresholds and timing parameThe Receive section consists of the following functional ters. blocks: Note that the reception of Normal 10BASE-T link pulses — Input and BLW Compensation and fast link pulses per IEEE 802.3u Auto-Negotiation by the 100BASE-X receiver do not cause the DP83843 to — Signal Detect assert signal detect. — Digital Adaptive Equalization While signal detect is normally generated and processed — MLT-3 to Binary Decoder entirely within the DP83843, it can be observed directly on — Clock Recovery Module the CRS pin (pin 22) while the DP83843 is configured for — NRZI to NRZ Decoder Symbol mode. Refer to Section 3.4 for further detail regarding Symbol mode operation. — Serial to Parallel 2.3.3 Digital Adaptive Equalization — DESCRAMBLER (bypass option) When transmitting data at high speeds over copper twisted — Code Group Alignment pair cable, frequency dependent attenuation becomes a — 4B/5B Decoder (bypass option) concern. In high speed twisted pair signalling, the fre— Link Integrity Monitor quency content of the transmitted signal can vary greatly — Bad SSD Detection during normal operation based primarily on the randomThe bypass option for the functional blocks within the ness of the scrambled data stream. This variation in signal 100BASE-X receiver provides flexibility for applications 18 www.national.com 2.0 Functional Description (Continued) RX_CLK RXD[3:0] / RX_ER BP_RX MUX BP_4B5B MUX CARRIER INTEGRITY MONITOR SD 4B/5B DECODER LINK INTEGRITY MONITOR CODE GROUP ALIGNMENT RX_DATA VALID SSD DETECT MUX BP_SCR DESCRAMBLER SERIAL TO PARALLEL CLOCK DATA NRZI TO NRZ DECODER CLOCK RECOVERY MODULE MLT-3 TO BINARY DECODER DIGITAL ADAPTIVE EQUALIZATION INPUT &BLW COMPENSATION SIGNAL DETECT TPRD +/− Figure 1. Receive Block Diagram 19 www.national.com 2.0 Functional Description (Continued) attenuation caused by frequency variations must be compensated for to ensure the integrity of the transmission. In order to ensure quality transmission when employing MLT-3 encoding, the compensation must be able to adapt to various cable lengths and cable types depending on the installed environment. The selection of long cable lengths for a given implementation, requires significant compensation which will over-compensate for shorter, less attenuating lengths. Conversely, the selection of short or intermediate cable lengths requiring less compensation will cause serious under-compensation for longer length cables. Therefore, the compensation or equalization must be adaptive to ensure proper conditioning of the received signal independent of the cable length. tenuation (dB) The DP83843 utilizes an extremely robust equalization scheme referred to herein as ‘Digital Adaptive Equalization.’ Existing designs use an adaptive equalization scheme that determines the approximate cable length by monitoring signal attenuation at certain frequencies. This attenuation value was compared to the internal receive input reference voltage. This comparison would indicate that amount of equalization to use. Although this scheme is used successfully on the DP83223V TWISTER, it is sensitive to transformer mismatch, resistor variation and process induced offset. The DP83223V also required an external attenuation network to help match the incoming signal amplitude to the internal reference. 100M 22.00 50M 0M 20.00 18.00 16.00 14.00 12.00 10.00 8.00 6.00 4.00 Figure 1. EIA/TIA Attenuation vs Frequency for 0, 50, 100 meters of CAT-5 cable Digital Adaptive Equalization is based on an advanced digitally controlled signal tracking technique. This method uses peak tracking with digital over-sampling and digitally controlled feedback loops to regenerate the receive signal. This technique does not depend on input amplitude variations to set the equalization factor. As a result it maintains constant jitter performance for any cable length up to 150 meters of CAT-5. Digital Adaptive Equalization allows for very high tolerance to signal amplitude variations. The curves given in Figure 6 illustrate attenuation at certain frequencies for given cable lengths. This is derived from the worst case frequency vs. attenuation figures as specified in the EIA/TIA Bulletin TSB-36. These curves indicate the significant variations in signal attenuation that must be compensated for by the receive adaptive equalization circuit. Figure 7 represents a scrambled IDLE transmitted over zero meters of cable as measured at the AII (Active Input 2ns/div Interface) of the receiver. Figure 8 and Figure 9 represent the signal degradation over 50 and 100 Meters of CAT-5 Figure 2. MLT-3 Signal Measured at AII after 0 meters of cable respectively, also measured at the AII. These plots CAT-5 cable show the extreme degradation of signal integrity and indicate the requirement for a robust adaptive equalizer. 2.3.5 Clock Recovery Module The DP83843 provides the added flexibility of controlling The Clock Recovery Module (CRM) accepts 125 Mb/s the type of receive equalization required for a given imple- NRZI data from the MLT-3 to NRZI decoder. The CRM locks mentation. This is done through TW_EQSEL (bits [13:12] onto the 125 Mb/s data stream and extracts a 125 MHz refof the PHYCTRL register, address 19h). While digital adap- erence clock. The extracted and synchronized clock and tive equalization is the preferred method of cable compen- data are used as required by the synchronous receive sation for 100BASE-TX, the ability to switch the equalizer operations as generally depicted in Figure 5. completely off or to a fixed maximum is provided. This feaThe CRM is implemented using an advanced digital Phase ture is intended as a test mode only and, if enabled, will Locked Loop (PLL) architecture that replaces sensitive inhibit normal performance of the DP83843. analog circuits. Using digital PLL circuitry allows the 2.3.4 MLT-3 to NRZI Decoder DP83843 to be manufactured and specified to tighter tolerThe DP83843 decodes the MLT-3 information from the Dig- ances. ital Adaptive Equalizer block to binary NRZI data. The rela- For further information relating to the 100BASE-X clock tionship of binary to MLT-3 data is shown in Figure 4. recovery module, refer to Section 4.3. 20 www.national.com 2.0 Functional Description (Continued) required function for ultimately providing data to the nibblewide interface of the MII. 2.3.8 Descrambler A 5-bit parallel (code-group wide) descrambler is used to descramble the receive NRZ data. To reverse the data scrambling process, the descrambler has to generate an identical data scrambling sequence (N) in order to recover the original unscrambled data (UD) from the scrambled data (SD) as represented in the equations: SD = ( UD ⊕ N ) UD = ( SD ⊕ N ) Synchronization of the descrambler to the original scrambling sequence (N) is achieved based on the knowledge that the incoming scrambled data stream consists of scrambled IDLE data. After the descrambler has recognized 12 consecutive IDLE code-groups, where an IDLE code-group in 5B NRZ is equal to five consecutive ones (11111), it will synchronize to the receive data stream and generate unscrambled data in the form of unaligned 5B code-groups. 2ns/div In order to maintain synchronization, the descrambler must continuously monitor the validity of the unscrambled data that it generates. To ensure this, a line state monitor and a hold timer are used to constantly monitor the synchronization status. Upon synchronization of the descrambler the hold timer starts a 722 µs countdown. Upon detection of sufficient IDLE code-groups within the 722 µs period, the hold timer will reset and begin a new countdown. This monitoring operation will continue indefinitely given a properly operating network connection with good signal integrity. If the line state monitor does not recognize sufficient unscrambled IDLE code-groups within the 722 µs period, the entire descrambler will be forced out of the current state of synchronization and reset in order to re-acquire synchronization. Figure 1. MLT-3 Signal Measured at AII after 50 meters of CAT-5 cable The value of the time-out for this timer may be modified from 722 sto 2 ms by setting bit 12 of the PCSR (address 16h) to one. The 2 ms option allows applications with Maximum Transmission Units (packet sizes) larger than IEEE 802.3 specifications to maintain descrambler synchronization (i.e. switch or router applications). Additionally, this timer may be disabled entirely by setting bit 11 of the PCSR (address 16h) to one. The disabling of the time-out timer is not recommended as this will eventually result in a lack of synchronization between the transmit scrambler and the receive descrambler which will corrupt data. The descrambler time-out counter may be reset by bit 13 of the PCSR. 2ns/div Figure 2. MLT-3 Signal Measured at AII after 100 meters of CAT-5 cable 2.3.6 NRZI to NRZ In a typical application, the NRZI to NRZ required in order to present NRZ formatted descrambler (or to the code-group alignment descrambler is bypassed, or directly to the receiver is bypassed). 2.3.9 Code-group Alignment decoder is data to the block, if the PCS, if the The code-group alignment module operates on unaligned 5-bit data from the descrambler (or, if the descrambler is bypassed, directly from the NRZI/NRZ decoder) and converts it into 5B code-group data (5 bits). Code-group alignment occurs after the J/K code-group pair is detected. The receive data stream is in NRZI format, therefore, the data Once the J/K code-group pair (11000 10001) is detected, subsequent data is aligned on a fixed boundary. must be decoded to NRZ before further processing. 2.3.10 4B/5B Decoder 2.3.7 Serial to Parallel The 100BASE-X receiver includes a Serial to Parallel converter which supplies 5 bit wide data symbols to the Descrambler. Converting to parallel helps to decrease latency through the device, as well as performing the The code-group decoder functions as a look up table that translates incoming 5B code-groups into 4B nibbles. The code-group decoder first detects the J/K code-group pair preceded by IDLE code-groups and replaces the J/K with 21 www.national.com 2.0 Functional Description (Continued) the MAC preamble. Specifically, the J/K 10-bit code-group pair is replaced by the nibble pair (0101 0101). All subsequent 5B code-groups are converted to the corresponding 4B nibbles for the duration of the entire packet. This conversion ceases upon the detection of the T/R code-group pair denoting the End of Stream Delimiter (ESD) or with the reception of a minimum of two IDLE code-groups. Detection of an unstable link condition will cause bit 4 of the PCS register (address 16h) to be set to one. This bit is cleared to zero upon a read operation once a stable link condition is detected by the CIM. Upon detection of a stable link, the DP83843 will resume normal operations. 2.3.11 100BASE-X Link Integrity Monitor 2.4 10BASE-T TRANSCEIVER MODULE The Disconnect Counter (address 13h) increments each time the CIM determines that the link is unstable. The 100BASE-X Link Integrity Monitor function (LIM) allows the receiver to ensure that reliable data is being received. Without reliable data reception, the LIM will halt both transmit and receive operations until such time that a valid link is detected (i.e. good link). The 10BASE-T Transceiver Module is IEEE 802.3 compliant. It includes the receiver, transmitter, collision, heartbeat, loopback, jabber, and link integrity functions, as defined in the standard. An external filter is not required on the 10BASE-T interface since this is integrated inside the If Auto-Negotiation is not enabled, then a valid link will be DP83843. Due to the complexity and scope of the indicated once SD+/− is asserted continuously for 500 µs. 10BASE-T Transceiver block and various sub-blocks, this If Auto-Negotiation is enabled, then Auto-Negotiation will section focuses on the general system level operation. further qualify a valid link as follows: 2.4.1 Operational Modes — The descrambler must receive a minimum of 12 IDLE code groups for proper link initialization. — The Auto-Negotiation must determine that the 100BASE-X function should be enabled. A valid link for a non-Auto-Negotiating application is indicated by either the Link LED output or by reading bit 2 of the Basic Mode Status Register BMSR (address 01h). For a truly qualified valid link indication as a result of AutoNegotiation, bit 2 of the BMSR register (address 01h) must be read. The DP83843 has 2 basic 10BASE-T operational modes: Half Duplex mode Full Duplex mode Half Duplex Mode In Half Duplex mode the DP83843 functions as a standard IEEE 802.3 10BASE-T transceiver supporting the CSMA/CD protocol. Full Duplex Mode In Full Duplex mode the DP83843 is capable of simultaneously transmitting and receiving without asserting the A Bad Start of Stream Delimiter (Bad SSD) is any transition collision signal. The DP83843's 10 Mb/s ENDEC is from consecutive idle code-groups to non-idle code-groups designed to encode and decode simultaneously. which is not prefixed by the code-group pair /J/K. 2.4.2 Oscillator Module Operation If this condition is detected, the DP83843 will assert A 25 MHz crystal or can-oscillator with the following specifiRX_ER and present RXD[3:0] = 1110 to the MII for the cations is recommended for driving the X1 input. cycles that correspond to received 5B code-groups. In order to exit this state the PHYTER must receive at least 1. CMOS output with a 50ppm frequency tolerance. two IDLE code groups and the PHYTER cannot receive a 2. 35-65% duty cycle (max). single IDLE code group at any time. In addition, the False 3. Two TTL load output drive. Carrier Event Counter (address 14h) will be incremented by one. Once the PHYTER exits this state, RX_ER and Additional output drive may be necessary if the oscillator must also drive other components. When using a clock CRS become de-asserted. oscillator it is still recommended that the designer connect When bit 11 of the LBR register is one (BP_RX), RXD[3:0] the oscillator output to the X1 pin and leave X2 floating. and RX_ER/RXD[4] are not modified. 2.4.3 Smart Squelch 2.3.13 Carrier Integrity Monitor The smart squelch is responsible for determining when The Carrier Integrity Monitor function (CIM) protects the valid data is present on the differential receive inputs repeater from transient conditions that would otherwise (TPRD+/−). The DP83843 implements an intelligent cause spurious transmission due to a faulty link. This func- receive squelch to ensure that impulse noise on the receive tion is required for repeater applications and is not speci- inputs will not be mistaken for a valid signal. Smart squelch fied for node applications. operation is independent of the 10BASE-T operational The REPEATER pin (pin 63) determines the default state of mode. bit 5 of the PCS register (Carrier Integrity Monitor Disable, The squelch circuitry employs a combination of amplitude address 16h) to automatically enable or disable the CIM and timing measurements (as specified in the IEEE 802.3 function as required for IEEE 802.3 compliant applications. 10BASE-T standard) to determine the validity of data on After power-up/reset, software may enable or disable this the twisted pair inputs (refer to Figure 10). function independent of Repeater or Node mode. The signal at the start of packet is checked by the smart If the CIM determines that the link is unstable, the squelch and any pulses not exceeding the squelch level DP83843 will not propagate the received data or control (either positive or negative, depending upon polarity) will signaling to the MII and will ignore data transmitted via the be rejected. Once this first squelch level is overcome corMII. The DP83843 will continue to monitor the receive rectly, the opposite squelch level must then be exceeded stream for valid carrier events. within 150 ns. Finally the signal must exceed the original squelch level within a further 150 ns to ensure that the 2.3.12 Bad SSD Detection 22 www.national.com 2.0 Functional Description (Continued) Twisted Pair Squelch Operation