DP83848MPTBREP

Product Folder Order Now Technical Documents Tools & Software Support & Community DP83848-EP SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 DP83848-EP PHYTER™ Military Temperature Single Port 10/100 Mbps Ethernet Physical Layer Transceiver 1 Device Overview 1.1 • • • • • • • • • • • 1 Low-power 3.3-V, 0.18-µm CMOS technology Low-power consumption < 270-mW typical 3.3-V MAC interface Auto-MDIX for 10/100 Mbps Energy detection mode 25-MHz clock out SNI interface (configurable) RMII rev. 1.2 interface (configurable) MII serial management interface (MDC and MDIO) IEEE 802.3u MII IEEE 802.3u auto-negotiation and parallel detection 1.2 • • • • IEEE 802.3u ENDEC, 10BASE-T transceivers and filters • IEEE 802.3u PCS, 100BASE-TX transceivers and filters • IEEE 1149.1 JTAG • Integrated ANSI X3.263 compliant TP-PMD physical sublayer with adaptive equalization and baseline wander compensation • Error-free operation up to 150 m • Programmable LED support link, 10/100 Mbps mode, activity, and collision detect • Single register access for complete PHY status • 10/100 Mbps packet BIST (built in self test) • Lead-free 48-pin PQFP packages 7 mm × 7 mm Features Applications Avionics and defense Industrial controls and factory automation General embedded applications 1.3 • Supports defense, aerospace, and medical applications – Controlled baseline – One assembly and test site – One fabrication site – Military temperature range (–55°C to 125°C) – Extended product life cycle – Extended product-change notification – Product traceability Description The number of applications requiring Ethernet connectivity continues to increase. Along with this increased market demand is a change in application requirements. The DP83848-EP was designed to allow Ethernet connectivity in the harshest environments. Our device meets IEEE 802.3u standards over a military temperature range of –55°C to 125°C. This device is ideally suited for harsh environments for example avionics, defense and industrial control applications. The DP83848-EP is a highly reliable, feature rich robust device which includes enhanced ESD protection, MII, and RMII for maximum flexibility in MPU selection all in a 48-pin PQFP package. The DP83848-EP features integrated sublayers to support both 10BASE-T and 100BASE-TX Ethernet protocols, which ensures compatibility and interoperability with all other standards based Ethernet solutions. Device Information (1) PART NUMBER DP83848MPHPEP DP83848MPHPREP DP83848MPTBEP DP83848MPTBREP (1) 1 PACKAGE PACKAGE DIMENSIONS (W × L × H) PHP 7.00 mm × 7.00 mm × 1.00 mm PTB 7.00 mm × 7.00 mm × 1.40 mm For more information, see Section 10, Mechanical, Packaging, and Orderable Information. An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DP83848-EP SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 1.4 www.ti.com Functional Block Diagram RX_CLK RXD[3:0] RX_DV RX_ER COL MDC MDIO TX_EN TX_CLK TXD[3:0] Serial Management CRS/CRS_DV MII/RMII/SNI MII/RMII/SNI Interfaces TX_DATA TX_CLK RX_DATA RX_CLK MI Registers 10Base-T and 100Base-TX Auto-Negotiation State Machine Transmit Block 10Base-T and 100Base-TX Receive Block Clock Generation DAC ADC Boundary Scan Auto-MDIX JTAG TD± RD± LED Drivers LEDs REFERENCE CLOCK 10/100 MB/S 25-MHZ Clock Source RJ-45 MII/RMII/SNI DP83848 Magnetics MPU/CPU Media Access Controller Typical System Diagram 10Base-T or 100Base-T Status LEDs Typical Application 2 Device Overview Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP DP83848-EP www.ti.com SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 Table of Contents 1 Device Overview ......................................... 1 5.4 Device Functional Modes 1.1 Features .............................................. 1 5.5 Programming ........................................ 44 1.2 Applications ........................................... 1 5.6 Memory .............................................. 54 1.3 Description ............................................ 1 1.4 6 ........................... 38 Application and Implementation .................... 75 Functional Block Diagram ............................ 2 6.1 Application Information .............................. 75 2 3 Revision History ......................................... 3 Pin Configuration and Functions ..................... 4 6.2 Typical Application 4 Specifications ........................................... 12 8.1 Layout Guidelines ................................... 83 4.1 Absolute Maximum Ratings ......................... 12 8.2 Layout Example ..................................... 86 4.2 ESD Ratings 8.3 Thermal Vias Recommendation 4.3 Recommended Operating Conditions ............... 12 4.4 Thermal Information ................................. 12 9.1 Documentation Support ............................. 88 4.5 DC Specifications ................................... 13 9.2 Community Resources .............................. 88 4.6 Electrical Characteristics ............................ 13 9.3 Trademarks.......................................... 88 4.7 AC Specifications.................................... 14 9.4 Electrostatic Discharge Caution ..................... 88 Detailed Description ................................... 32 9.5 Export Control Notice 9.6 Glossary ............................................. 88 3.1 5 5.1 5.2 5.3 Package Pin Assignments............................ 6 ........................................ ............................................ Functional Block Diagram ........................... Feature Description ................................. Overview 7 8 12 32 32 33 9 .................................. 75 Power Supply Recommendations .................. 82 Layout .................................................... 83 .................... 86 Device and Documentation Support ............... 88 ............................... 88 10 Mechanical, Packaging, and Orderable Information .............................................. 89 2 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (December 2015) to Revision E • • • • • • • • • • • • Page Updated document format to current data sheet standard ...................................................................... 1 Changed Ordering Information table to Device Information table .............................................................. 1 Changed Terminal Descriptions section to Pin Configuration and Functions section ....................................... 4 Added Package Pin Assignments section ......................................................................................... 6 Changed footnote in Absolute Maximum Ratings............................................................................... 12 Changed Thermal Information footnotes ......................................................................................... 12 Changed Design Guidelines to Application Information and updated ........................................................ 75 Deleted ESD note, included in Device and Documentation Support section ................................................ 76 Added Magnetics section .......................................................................................................... 78 Added Detailed Design Procedure section ...................................................................................... 79 Added Power Supply Recommendations section ............................................................................... 82 Added Layout section ............................................................................................................... 83 Revision History Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP 3 DP83848-EP SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 www.ti.com 3 Pin Configuration and Functions The DP83848-EP pins are classified into the following interface categories (each interface is described in the sections that follow): • Serial management interface • MAC data interface • Clock interface • LED interface • Reset • Strap options • 10/100 Mbps PMD interface • Special connect pins • Power and ground pins All DP83848-EP signal pins are I/O cells regardless of the particular use. The definitions below define the functionality of the I/O cells for each pin. NOTE Strapping pin option. See Table 3-8 for strap definitions. Type: I Input Type: O Output Type: I/O Input/Output Type: OD Open Drain Type: PD,PU Internal Pulldown/Pullup Type: S 4 Strapping Pin (All strap pins have weak internal pullups or pulldowns. If the default strap value is to be changed then an external 2.2-kΩ resistor should be used. See Table 3-8 for details.) Pin Configuration and Functions Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP DP83848-EP PFBIN2 DGND IOGND X1 X2 IOVDD33 MDC MDIO RESET_N LED_LINK/AN0 LED_SPEED/AN1 LED_ACT/COL/AN_EN 25MHz_OUT 35 34 33 32 31 30 29 28 27 26 25 SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 36 www.ti.com 37 24 RBIAS RX_CLK 38 23 PFBOUT RX_DV/MII_MODE 39 22 AVDD33 CRS/CRS_DV/LED_CFG 40 21 RESERVED RX_ER/MDIX_EN 41 20 RESERVED COL/PHYAD0 42 RXD_0/PHYAD1 43 Thermal Pad 19 AGND 18 PFBIN1 6 7 8 9 10 11 12 TCK TDO TMS TRST TDI RD – PWR_DOWN/INT 13 TXD_3/SNI_MODE 48 5 IOVDD33 4 RD + TXD_1 AGND 14 TXD_2 15 47 3 46 IOGND 2 TD – RXD_3/PHYAD4 TXD_0 TD + 16 TX_EN 17 45 1 44 RXD_2/PHYAD3 TX_CLK RXD_1/PHYAD2 Figure 3-1. PHP or PTB Package (Top View) Pin Configuration and Functions Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP 5 DP83848-EP SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 3.1 www.ti.com Package Pin Assignments Table 3-1. Package Pin Assignments PIN NUMBER 6 PIN NAME 1 TX_CLK 2 TX_EN 3 TXD_0 4 TXD_1 5 TXD_2 6 SNI_MODE(TXD_3) 7 PWR_DOWN(INT) 8 TCK 9 TDO 10 TMS 11 TRST 12 TDI 13 RD– 14 RD+ 15 AGND 16 TD– 17 TD+ 18 PFBIN1 19 AGND 20 RESERVED 21 RESERVED 22 AVDD33 23 PFBOUT 24 RBIAS 25 25MHz_OUT 26 AN_EN(LED_ACT/COL) 27 AN_1(LED_SPEED) 28 AN_0(LED_LINK) 29 RESET_N 30 MDIO 31 MDC 32 IOVDD33 33 X2 34 X1 35 IOGND 36 DGND 37 PFBIN2 38 RX_CLK 39 RX_DV(MII_MODE) 40 CRS/CRS_DV(LED_CFG) 41 MDIX_EN(RX_ER) 42 PHYAD0(COL) 43 PHYAD1(RXD_0) 44 PHYAD2(RXD_1) 45 PHYAD3(RXD_2) Pin Configuration and Functions Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP DP83848-EP www.ti.com SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 Table 3-1. Package Pin Assignments (continued) PIN NUMBER PIN NAME 46 PHYAD4(RXD_3) 47 IOGND 48 IOVDD33 49 DAP (Die Attach Pad/Thermal Pad) Table 3-2. Serial Management Interface TERMINAL NAME NO. I/O DESCRIPTION MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO management data input/output serial interface which may be asynchronous to transmit and receive clocks. The maximum clock rate is 25 MHz with no minimum clock rate. MDC 31 I MDIO 30 I/O MANAGEMENT DATA I/O: Bi-directional management instruction/ data signal that may be sourced by the station management entity or the PHY. This pin requires a 1.5-kΩ pullup resistor. Table 3-3. MAC Data Interface TERMINAL NAME NO. I/O DESCRIPTION MII TRANSMIT CLOCK: 25-MHz transmit clock output in 100-Mbps mode or 2.5 MHz in 10-Mbps mode derived from the 25-MHz reference clock. TX_CLK 1 O Unused in RMII mode. The device uses the X1 reference clock input as the 50-MHz reference for both transmit and receive. SNI TRANSMIT CLOCK: 10-MHz transmit clock output in 10-Mb SNI mode. The MAC should source TX_EN and TXD_0 using this clock. MII TRANSMIT ENABLE: Active high input indicates the presence of valid data inputs on TXD[3:0]. TX_EN 2 I, PD RMII TRANSMIT ENABLE: Active high input indicates the presence of valid data on TXD[1:0]. SNI TRANSMIT ENABLE: Active high input indicates the presence of valid data on TXD_0. TXD_0 3 TXD_1 4 TXD_2 5 TXD_3 6 I MII TRANSMIT DATA: Transmit data MII input pins, TXD[3:0], that accept data synchronous to the TX_CLK (2.5 MHz in 10-Mbps mode or 25 MHz in 100-Mbps mode). RMII TRANSMIT DATA: Transmit data RMII input pins, TXD[1:0], that accept data synchronous to the 50-MHz reference clock. S, I, PD SNI TRANSMIT DATA: Transmit data SNI input pin, TXD_0, that accept data synchronous to the TX_CLK (10 MHz in 10-Mbps SNI mode). MII RECEIVE CLOCK: Provides the 25-MHz recovered receive clocks for 100-Mbps mode and 2.5 MHz for 10Mbps mode. RX_CLK 38 O Unused in RMII mode. The device uses the X1 reference clock input as the 50-MHz reference for both transmit and receive. SNI RECEIVE CLOCK: Provides the 10-MHz recovered receive clocks for 10-Mbps SNI mode. MII RECEIVE DATA VALID: Asserted high to indicate that valid data is present on the corresponding RXD[3:0]. MII mode by default with internal pulldown. RX_DV 39 S, O, PD RMII Synchronous Receive Data Valid: This signal provides the RMII Receive Data Valid indication independent of Carrier Sense. This pin is not used in SNI mode. MII RECEIVE ERROR: Asserted high synchronously to RX_CLK to indicate that an invalid symbol has been detected within a received packet in 100-Mbps mode. RX_ER 41 S, O, PU RMII RECEIVE ERROR: Assert high synchronously to X1 whenever it detects a media error and RXDV is asserted in 100-Mbps mode. This pin is not required to be used by a MAC, in either MII or RMII mode, since the Phy is required to corrupt data on a receive error. This pin is not used in SNI mode. S, O, PD MII RECEIVE DATA: Nibble-wide receive data signals driven synchronously to the RX_CLK (25 MHz for 100Mbps mode, 2.5 MHz for 10-Mbps mode). RXD[3:0] signals contain valid data when RX_DV is asserted. RXD_0 43 RXD_1 44 RMII RECEIVE DATA: 2-bits receive data signals, RXD[1:0], driven synchronously to the X1 clock, 50 MHz. RXD_2 45 RXD_3 46 SNI RECEIVE DATA: Receive data signal, RXD_0, driven synchronously to the RX_CLK. RXD_0 contains valid data when CRS is asserted. RXD[3:1] are not used in this mode. Pin Configuration and Functions Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP 7 DP83848-EP SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 www.ti.com Table 3-3. MAC Data Interface (continued) TERMINAL NAME NO. I/O DESCRIPTION MII CARRIER SENSE: Asserted high to indicate the receive medium is non-idle. CRS/CRS_DV 40 S, O, PU RMII CARRIER SENSE/RECEIVE DATA VALID: This signal combines the RMII Carrier and Receive Data Valid indications. For a detailed description of this signal, see the RMII Specification. SNI CARRIER SENSE: Asserted high to indicate the receive medium is non-idle. It is used to frame valid receive data on the RXD_0 signal. MII COLLISION DETECT: Asserted high to indicate detection of a collision condition (simultaneous transmit and receive activity) in 10-Mbps and 100-Mbps Half Duplex Modes. While in 10BASE-T Half Duplex mode with heartbeat enabled this pin is also asserted for a duration of approximately 1 µs at the end of transmission to indicate heartbeat (SQE test). COL 42 S, O, PU In Full Duplex Mode, for 10-Mbps or 100-Mbps operation, this signal is always logic 0. There is no heartbeat function during 10-Mbps full duplex operation. RMII COLLISION DETECT: Per the RMII Specification, no COL signal is required. The MAC will recover CRS from the CRS_DV signal and use that along with its TX_EN signal to determine collision. SNI COLLISION DETECT: Asserted high to indicate detection of a collision condition (simultaneous transmit and receive activity) in 10-Mbps SNI mode. Table 3-4. Clock Interface TERMINAL NAME X1 NO. 34 I/O DESCRIPTION I CRYSTAL/OSCILLATOR INPUT: This pin is the primary clock reference input for the DP83848-EP and must be connected to a 25-MHz 0.005% (±50 ppm) clock source. The DP83848-EP supports either an external crystal resonator connected across pins X1 and X2, or an external CMOS-level oscillator source connected to pin X1 only. RMII REFERENCE CLOCK: This pin is the primary clock reference input for the RMII mode and must be connected to a 50-MHz 0.005% (±50 ppm) CMOS-level oscillator source. X2 33 O CRYSTAL OUTPUT: This pin is the primary clock reference output to connect to an external 25-MHz crystal resonator device. This pin must be left unconnected if an external CMOS oscillator clock source is used. 25-MHz CLOCK OUTPUT: In MII mode, this pin provides a 25-MHz clock output to the system. 25MHz_OUT 25 O In RMII mode, this pin provides a 50-MHz clock output to the system. This allows other devices to use the reference clock from the DP83848-EP without requiring additional clock sources. 8 Pin Configuration and Functions Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP DP83848-EP www.ti.com SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 Table 3-5. LED Interface TERMINAL NAME NO. I/O DESCRIPTION LINK LED: In Mode 1, this pin indicates the status of the LINK. The LED will be ON when Link is good. LED_LINK 28 S, O, PU LED_SPEED 27 S, O, PU LED_ACT/COL 26 S, O, PU LINK/ACT LED: In Mode 2 and Mode 3, this pin indicates transmit and receive activity in addition to the status of the Link. The LED will be ON when Link is good. It will blink when the transmitter or receiver is active. SPEED LED: The LED is ON when device is in 100 Mbps and OFF when in 10 Mbps. Functionality of this LED is independent of mode selected. ACTIVITY LED: In Mode 1, this pin is the Activity LED which is ON when activity is present on either Transmit or Receive. COLLISION/DUPLEX LED: In Mode 2, this pin by default indicates Collision detection. For Mode 3, this LED output may be programmed to indicate Full-duplex status instead of Collision. Table 3-6. JTAG Interface TERMINAL NAME NO. I/O DESCRIPTION TCK 8 I, PU TEST CLOCK: This pin has a weak internal pullup. TDI 12 I, PU TEST DATA INPUT: This pin has a weak internal pullup. TDO 9 O TMS 10 I, PU TEST MODE SELECT: This pin has a weak internal pullup. TRST 11 I, PU TEST RESET: Active low asynchronous test reset. This pin has a weak internal pullup. TEST OUTPUT Table 3-7. Reset and Power Down TERMINAL NAME RESET_N NO. 29 I/O DESCRIPTION I, PU RESET: Active Low input that initializes or re-initializes the DP83848-EP. Asserting this pin low for at least 1 µs will force a reset process to occur. All internal registers will re-initialize to their default states as specified for each bit in Section 5.6. All strap options are re-initialized as well. The default function of this pin is POWER DOWN. POWER DOWN: The pin is an active low input in this mode and should be asserted low to put the device in a Power Down mode. PWR_DOWN/INT 7 I, OD, PU INTERRUPT: The pin is an open drain output in this mode and will be asserted low when an interrupt condition occurs. Although the pin has a weak internal pullup, some applications may require an external pullup resister. Register access is required for the pin to be used as an interrupt mechanism. See Section 6.2.1.4.2 for more details on the interrupt mechanisms. Pin Configuration and Functions Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP 9 DP83848-EP SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 www.ti.com Table 3-8. Strap Options (1) (2) TERMINAL NAME NO. I/O DESCRIPTION PHYAD0 (COL) 42 S, O, PU PHY ADDRESS [4:0]: The DP83848-EP provides five PHY address pins, the state of which are latched into the PHYCTRL register at system Hardware-Reset. PHYAD1 (RXD_0) 43 S, O, PD The DP83848-EP supports PHY Address strapping values 0 () through 31 (). A PHY Address of 0 puts the part into the MII Isolate Mode. The MII isolate mode must be selected by strapping Phy Address 0; changing to Address 0 by register write will not put the Phy in the MII isolate mode. Please refer to Section 5.4.4.1 for additional information. PHYAD2 (RXD_1) 44 PHYAD3 (RXD_2) 45 PHYAD4 (RXD_3) 46 AN_EN (LED_ACT/COL) 26 AN_1 (LED_SPEED) 27 AN0 / AN1: These input pins control the forced or advertised operating mode of the DP83848-EP according to the following table. The value on these pins is set by connecting the input pins to GND (0) or VCC (1) through 2.2-kΩ resistors. These pins should NEVER be connected directly to GND or VCC. AN_0 (LED_LINK) 28 The value set at this input is latched into the DP83848-EP at Hardware-Reset. PHYAD0: This pin has weak internal pullup resistor. PHYAD[4:1]: These pins have weak internal pulldown resistors. S, O, PU Auto-Negotiation Enable: When high, this enables Auto-Negotiation with the capability set by ANO and AN1 pins. When low, this puts the part into Forced Mode with the capability set by AN0 and AN1 pins. The float/pulldown status of these pins are latched into the Basic Mode Control Register and the Auto_Negotiation Advertisement Register during Hardware-Reset. The default is 111 since these pins have internal pullups. MII_MODE (RX_DV) 39 SNI_MODE (TXD_3) 6 LED_CFG (CRS) 40 S, O, PD AN_EN AN1 AN0 0 0 0 10BASE-T, Half-Duplex Forced Mode 0 0 1 10BASE-T, Full-Duplex 0 1 0 100BASE-TX, Half-Duplex 0 1 1 100BASE-TX, Full-Duplex AN_EN AN1 AN0 1 0 0 10BASE-T, Half/Full-Duplex 1 0 1 100BASE-TX, Half/Full-Duplex 1 1 0 1 1 1 Advertised Mode 10BASE-T Half-Duplex 100BASE-TX, Half-Duplex 10BASE-T, Half/Full-Duplex 100BASE-TX, Half/Full-Duplex MII MODE SELECT: This strapping option pair determines the operating mode of the MAC Data Interface. Default operation (No pullups) will enable normal MII Mode of operation. Strapping MII_MODE high will cause the device to be in RMII or SNI mode of operation, determined by the status of the SNI_MODE strap. Since the pins include internal pulldowns, the default values are 0. The following table details the configurations: S, O, PU MII_MODE SNI_MODE 0 X MII Mode MAC Interface Mode 1 0 RMII Mode 1 1 10-Mb SNI Mode LED CONFIGURATION: This strapping option determines the mode of operation of the LED pins. Default is Mode 1. Mode 1 and Mode 2 can be controlled via the strap option. All modes are configurable via register access. See Table 5-2 for LED Mode Selection. MDIX_EN (RX_ER) (1) (2) 10 41 S, O, PU MDIX ENABLE: Default is to enable MDIX. This strapping option disables Auto-MDIX. An external pulldown will disable Auto- MDIX mode. The DP83848-EP uses many of the functional pins as strap options. The values of these pins are sampled during reset and used to strap the device into specific modes of operation. The functional pin name is indicated in parentheses. A 2.2-kΩ resistor should be used for pulldown or pullup to change the default strap option. If the default option is required, then there is no need for external pullup or pulldown resistors. Since these pins may have alternate functions after reset is deasserted, they should not be connected directly to VCC or GND. Pin Configuration and Functions Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP DP83848-EP www.ti.com SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 Table 3-9. 10-Mbps and 100-Mbps PMD Interface TERMINAL NAME I/O NO. DESCRIPTION Differential common driver transmit output (PMD Output Pair). These differential outputs are automatically configured to either 10BASE-T or 100BASE-TX signaling. TD–, TD+ 16, 17 I/O In Auto-MDIX mode of operation, this pair can be used as the Receive Input pair. These pins require 3.3-V bias for operation. Differential receive input (PMD Input Pair). These differential inputs are automatically configured to accept either 100BASE-TX or 10BASE-T signaling. RD–, RD+ 13, 14 I/O In Auto-MDIX mode of operation, this pair can be used as the Transmit Output pair. These pins require 3.3-V bias for operation. Table 3-10. Special Connections TERMINAL NAME I/O NO. DESCRIPTION RBIAS 24 I Bias Resistor Connection. A 4.87-kΩ 1% resistor should be connected from RBIAS to GND. PFBOUT 23 O Power Feedback Output. Parallel caps, 10 µF (Tantalum preferred) and 0.1 µF, should be placed close to the PFBOUT. Connect this pin to PFBIN1 (pin 18) and PFBIN2 (pin 37). See Section 6.2.1.3 for proper placement pin. PFBIN1 18 I Power Feedback Input. These pins are fed with power from PFBOUT pin. A small capacitor of 0.1 µF should be connected close to each pin. PFBIN2 37 RESERVED Note: Do not supply power to these pins other than from PFBOUT. 20, 21 I/O RESERVED: These pins must be pulled-up through 2.2-kΩ resistors to AVDD33 supply. Table 3-11. Power Supply Pins TERMINAL NAME DESCRIPTION NO. IOVDD33 32, 48 I/O 3.3-V supply IOGND 35, 47 I/O ground DGND 36 Digital ground AVDD33 22 Analog 3.3-V supply AGND GNDPAD 15, 19 DAP Analog ground Thermal pad Pin Configuration and Functions Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP 11 DP83848-EP SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 www.ti.com 4 Specifications Absolute Maximum Ratings (1) 4.1 over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage –0.5 4.2 V VIN DC input voltage –0.5 VCC + 0.5 V VOUT DC output voltage –0.5 VCC + 0.5 V TSTG Storage temperature –65 150 °C TJ Operating junction temperature –55 150 °C 260 °C TL (1) Lead temperature (soldering, 10 seconds) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 4.2 ESD Ratings RZAP = 1.5 kΩ, CZAP = 100 pF VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±4000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 4.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN VCC Supply voltage TA Operating free-air temperature (1) PD (1) NOM MAX UNIT 3 3.6 V –55 125 °C Power dissipation 267 mW Provided that Thermal Pad is soldered down. 4.4 Thermal Information DP83848-EP THERMAL METRIC (1) PHP PTB UNITS 48 PINS θJA Junction-to-ambient thermal resistance 35.74 49.0 °C/W θJCtop Junction-to-case (top) thermal resistance 21.8 62.9 °C/W θJB Junction-to-board thermal resistance 19.5 30.4 °C/W ψJT Junction-to-top characterization parameter 1.2 7.3 °C/W ψJB Junction-to-board characterization parameter 19.4 30.3 °C/W θJCbot Junction-to-case (bottom) thermal resistance 3.2 9.5 °C/W (1) 12 For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Specifications Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP DP83848-EP www.ti.com SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 4.5 DC Specifications 4.6 Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER VIH Input high voltage VIL Input low voltage IIH Input high current IIL Input low current VOL VOH TEST CONDITIONS MIN Nominal VCC TYP MAX UNIT 2 V 0.8 V VIN = VCC 10 µA VIN = GND 10 µA Output low voltage IOL = 4 mA 0.4 V Output high voltage IOH = –4 mA IOZ Tri-state leakage VOUT = VCC VOUT = GND VTPTD_100 100M transmit voltage 0.89 VTPTDsym 100M transmit voltage symmetry –2% VTPTD_10 10M transmit voltage 2.17 CIN1 CMOS input capacitance 5 COUT1 CMOS output capacitance 5 SDTHon 100BASE-TX signal detect turnon threshold SDTHoff 100BASE-TX signal detect turnoff threshold VTH1 10BASE-T receive threshold Idd100 100BASE-TX (full duplex) 81 mA Idd10 10BASE-T (full duplex) 92 mA Idd Power down mode 14 mA VCC – 0.5 V 1 ±10 µA 1.15 V 2% 2.5 2.8 V pF pF 1000 200 mV diff pk-pk mV diff pk-pk 585 mV Estimated Life (Hours) 1000000.00 100000.00 10000.00 1000.00 80 90 100 110 120 130 140 150 160 Continuous T J (°C) (1) (2) (3) See data sheet for absolute maximum and minimum recommended operating conditions. Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect life). Enhanced plastic product disclaimer applies. Figure 4-1. DP83848-EP Operating Life Derating Chart Specifications Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP 13 DP83848-EP SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 4.7 4.7.1 www.ti.com AC Specifications Power Up Timing PARAMETER DESCRIPTION NOTES T2.1.1 Post power up stabilization time prior to MDC preamble for register accesses T2.1.2 Hardware configuration latch-in time from power up T2.1.3 Hardware configuration pins transition to output drivers MIN MDIO is pulled high for 32-bit serial management initialization. X1 clock must be stable for a min. of 167 ms at power up. Hardware configuration pins are described in Section 3 and Table 3-8. X1 clock must be stable for a min. of 167 ms at power up. TYP MAX UNIT 167 ms 167 ms 50 ns VCC X1 clock T2.1.1 Hardware RESET_N 32 clocks MDC T2.1.2 Latch-in of hardware configuration pins T2.1.3 Dual function pins become enabled as outputs Input Output Figure 4-2. Power Up Timing 14 Specifications Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP DP83848-EP www.ti.com 4.7.2 SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 Reset Timing PARAMETER NOTES (1) DESCRIPTION MIN TYP MAX UNIT T2.2.1 Post RESET stabilization time prior to MDC preamble for register accesses MDIO is pulled high for 32-bit serial management initialization. 3 µs T2.2.2 Hardware configuration latch-in time from the deassertion of RESET (either soft or hard) Hardware configuration pins are described in Section 3 and Table 3-8. 3 µs T2.2.3 Hardware configuration pins transition to output drivers 50 ns T2.2.4 RESET pulse width (1) X1 clock must be stable for at min. of 1 µs during RESET pulse low time. 1 µs It is important to choose pullup and/or pulldown resistors for each of the hardware configuration pins that provide fast RC time constants in order to latch-in the proper value prior to the pin transitioning to an output driver. VCC X1 clock T2.2.1 T2.2.4 Hardware RESET_N 32 clocks MDC T2.2.2 Latch-in of hardware configuration pins T2.2.3 Dual function pins become enabled as outputs Input Output Figure 4-3. Reset Timing Specifications Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP 15 DP83848-EP SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 4.7.3 www.ti.com MII Serial Management Timing PARAMETER DESCRIPTION NOTES MIN TYP MAX 30 UNIT T2.3.1 MDC to MDIO (output) delay time 0 T2.3.2 MDIO (input) to MDC setup time 10 ns ns T2.3.3 MDIO (input) to MDC hold time 10 ns T2.3.4 MDC frequency 2.5 25 MHz UNIT MDC T2.3.1 T2.3.4 MDIO (output) MDC T2.3.2 MDIO (input) T2.3.3 Valid data Figure 4-4. MII Serial Management Timing 4.7.4 100-Mbps MII Transmit Timing MIN TYP MAX T2.4.1 PARAMETER TX_CLK high/low time DESCRIPTION 100-Mbps Normal mode NOTES 16 20 24 T2.4.2 TXD[3:0], TX_EN data setup to TX_CLK 100-Mbps Normal mode 9.70 ns T2.4.3 TXD[3:0], TX_EN data hold from TX_CLK 100-Mbps Normal mode 0 ns T2.4.1 ns T2.4.1 TX_CLK T2.4.2 TXD[3:0] TX_EN T2.4.3 Valid data Figure 4-5. 100-Mbps MII Transmit Timing 16 Specifications Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP DP83848-EP www.ti.com 4.7.5 SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 100-Mbps MII Receive Timing MIN TYP MAX T2.5.1 PARAMETER RX_CLK high/low time DESCRIPTION 100-Mbps Normal mode NOTES 16 20 24 ns T2.5.2 RX_CLK to RXD[3:0], RX_DV, RX_ER delay 100-Mbps Normal mode 10 30 ns T2.5.1 UNIT T2.5.1 RX_CLK T2.5.2 RXD[3:0] RX_DV RX_ER Valid data Figure 4-6. 100-Mbps MII Receive Timing 4.7.6 100BASE-TX Transmit Packet Latency Timing PARAMETER T2.6.1 (1) NOTES (1) DESCRIPTION MIN TX_CLK to PMD output pair latency 100-Mbps Normal mode TYP MAX 6 UNIT bits For Normal mode, latency is determined by measuring the time from the first rising edge of TX_CLK occurring after the assertion of TX_EN to the first bit of the “J” code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100-Mbps mode. TX_CLK TX_EN TXD T2.6.1 PMD output pair IDLE (J/K) DATA Figure 4-7. 100BASE-TX Transmit Packet Latency Timing Specifications Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP 17 DP83848-EP SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 4.7.7 100BASE-TX Transmit Packet Deassertion Timing PARAMETER NOTES (1) DESCRIPTION TX_CLK to PMD output pair deassertion T2.7.1 (1) www.ti.com MIN 100-Mbps Normal mode TYP 6 MAX UNIT bits For Normal mode, latency is determined by measuring the time from the first rising edge of TX_CLK occurring after the assertion of TX_EN to the first bit of the “J” code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100-Mbps mode. TX_CLK TX_EN TXD T2.7.1 PMD output pair DATA (T/R) IDLE Figure 4-8. 100BASE-TX Transmit Packet Deassertion Timing 18 Specifications Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP DP83848-EP www.ti.com 4.7.8 SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 100BASE-TX Transmit Timing (tR/F and Jitter) PARAMETER (2) MIN TYP MAX 2.6 4 5.5 ns 100-Mbps tR and tF mismatch 500 ps 100-Mbps PMD output pair transmit jitter 1.4 ns 100-Mbps PMD output pair tR and tF T2.8.1 T2.8.2 (3) (1) (2) (3) NOTES (1) DESCRIPTION UNIT Normal Mismatch is the difference between the maximum and minimum of all rise and fall times. Rise and fall times taken at 10% and 90% of the ±1 amplitude. Specified from –40°C to 125°C. T2.8.1 +1 rise 90% 10% PMD output pair 10% +1 fall 90% T2.8.1 –1 rise –1 fall T2.8.1 T2.8.1 T2.8.2 PMD output pair eye pattern T2.8.2 Figure 4-9. 100BASE-TX Transmit Timing (tR/F and Jitter) Specifications Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP 19 DP83848-EP SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 4.7.9 www.ti.com 100BASE-TX Receive Packet Latency Timing DESCRIPTION (1) PARAMETER NOTES (2) (3) MIN TYP MAX UNIT T2.9.1 Carrier sense ON delay 100-Mbps Normal mode 20 bits T2.9.2 Receive data latency 100-Mbps Normal mode 24 bits (1) (2) (3) Carrier Sense On Delay is determined by measuring the time from the first bit of the “J” code group to the assertion of Carrier Sense. 1 bit time = 10 ns in 100-Mbps mode. PMD Input Pair voltage amplitude is greater than the Signal Detect Turn-On Threshold Value. PMD input pair IDLE (J/K) DATA T2.9.1 CRS T2.9.2 RXD[3:0] RX_DV RX_ER Figure 4-10. 100BASE-TX Receive Packet Latency Timing 4.7.10 100BASE-TX Receive Packet Deassertion Timing PARAMETER T2.10.1 (1) (2) NOTES (1) DESCRIPTION Carrier sense OFF delay (2) MIN 100-Mbps Normal mode TYP 24 MAX UNIT bits Carrier Sense Off Delay is determined by measuring the time from the first bit of the “T” code group to the deassertion of Carrier Sense. 1 bit time = 10 ns in 100-Mbps mode. PMD input pair DATA (T/R) IDLE T2.10.1 CRS Figure 4-11. 100BASE-TX Receive Packet Deassertion Timing 20 Specifications Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP DP83848-EP www.ti.com SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 4.7.11 10-Mbps MII Transmit Timing PARAMETER NOTES (1) MIN TYP MAX UNIT T2.11.1 TX_CLK high/low time 10-Mbps MII mode 190 200 210 ns T2.11.2 TXD[3:0], TX_EN data setup to TX_CLK fall 10-Mbps MII mode 24.70 ns T2.11.3 TXD[3:0], TX_EN data hold from TX_CLK rise 10-Mbps MII mode 0 ns (1) DESCRIPTION An attached Mac should drive the transmit signals using the positive edge of TX_CLK. As shown above, the MII signals are sampled on the falling edge of TX_CLK. T2.11.1 T2.11.1 TX_CLK T211.3 T2.11.2 TXD[3:0] TX_EN Valid data Figure 4-12. 10-Mbps MII Transmit Timing 4.7.12 10-Mbps MII Receive Timing PARAMETER NOTES (1) DESCRIPTION MIN TYP MAX UNIT 200 240 ns T2.12.1 RX_CLK high/low time 160 T2.12.2 RX_CLK to RXD[3:0], RX_DV delay 10-Mbps MII mode 100 ns T2.12.3 RX_CLK rising edge delay from RXD[3:0], RX_DV valid 100 ns (1) 10-Mbps MII mode RX_CLK may be held low for a longer period of time during transition between reference and recovered clocks. Minimum high and low times will not be violated. T2.12.1 T2.12.1 RX_CLK T2.12.3 T2.12.2 RXD[3:0] RX_DV Valid data Figure 4-13. 10-Mbps MII Receive Timing Specifications Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP 21 DP83848-EP SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 www.ti.com 4.7.13 10-Mbps Serial Mode Transmit Timing MIN TYP MAX T2.13.1 PARAMETER TX_CLK high time DESCRIPTION 10-Mbps Serial mode NOTES 20 25 30 ns T2.13.2 TX_CLK low time 10-Mbps Serial mode 70 75 80 ns T2.13.3 TXD_0, TX_EN data setup to TX_CLK rise 10-Mbps Serial mode 24.70 ns T2.13.4 TXD_0, TX_EN data hold from TX_CLK rise 10-Mbps Serial mode 0 ns T2.13.1 UNIT T2.13.2 TX_CLK T2.13.3 TXD[0] TX_EN T2.13.4 Valid data Figure 4-14. 10-Mbps Serial Mode Transmit Timing 4.7.14 10-Mbps Serial Mode Receive Timing PARAMETER NOTES (1) DESCRIPTION T2.14.1 RX_CLK high/low time T2.14.2 RX_CLK fall to RXD_0, RX_DV delay (1) 10-Mbps Serial mode MIN TYP MAX 35 50 65 ns 10 ns –10 UNIT RX_CLK may be held high for a longer period of time during transition between reference and recovered clocks. Minimum high and low times will not be violated. T2.14.1 T2.14.1 RX_CLK T2.14.2 RXD[0] RX_DV Valid data Figure 4-15. 10-Mbps Serial Mode Receive Timing 22 Specifications Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP DP83848-EP www.ti.com SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 4.7.15 10BASE-T Transmit Timing (Start of Packet) PARAMETER DESCRIPTION NOTES MIN TYP MAX UNIT T2.15.1 Transmit output delay from the falling edge of TX_CLK 10-Mbps MII mode 3.5 bits T2.15.2 Transmit output delay from the rising edge of TX_CLK 10-Mbps Serial mode 3.5 bits TX_CLK TX_EN TXD T2.15.2 PMD output pair T2.15.1 Figure 4-16. 10BASE-T Transmit Timing (Start of Packet) 4.7.16 10BASE-T Transmit Timing (End of Packet) PARAMETER MIN TYP T2.16.1 End of packet high time (with ‘0’ ending bit) DESCRIPTION NOTES MAX UNIT 250 300 ns T2.16.2 End of packet high time (with ‘1’ ending bit) 250 300 ns TX_CLK TX_EN 0 T2.16.1 0 PWD output pair T2.16.2 1 1 PMD output pair Figure 4-17. 10BASE-T Transmit Timing (End of Packet) Specifications Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP 23 DP83848-EP SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 www.ti.com 4.7.17 10BASE-T Receive Timing (Start of Packet) PARAMETER NOTES (1) DESCRIPTION T2.17.1 Carrier sense turn on delay (PMD input pair to CRS) T2.17.2 RX_DV latency T2.17.3 Receive data latency (1) (2) (2) MIN Measurement shown from SFD TYP MAX UNIT 630 1000 ns 10 bits 8 bits 10BASE-T RX_DV Latency is measured from first bit of preamble on the wire to the assertion of RX_DV. 1 bit time = 100 ns in 10-Mbps mode. First SFD bit decoded 1 0 1 0 1 0 101011 TPRD± T2.17.1 CRS RX_CLK T2.17.2 RX_DV T2.17.3 RXD[3:0] Preamble 0000 Data SFD Figure 4-18. 10BASE-T Receive Timing (Start of Packet) 4.7.18 10BASE-T Receive Timing (End of Packet) PARAMETER T2.18.1 DESCRIPTION NOTES MIN Carrier sense turn off delay TYP MAX 1 1 0 1 UNIT µs IDLE PMD input pair RX_CLK T2.18.1 CRS Figure 4-19. 10BASE-T Receive Timing (End of Packet) 24 Specifications Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP DP83848-EP www.ti.com SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 4.7.19 10-Mbps Heartbeat Timing PARAMETER DESCRIPTION NOTES MIN TYP MAX UNIT T2.19.1 CD heartbeat delay All 10-Mbps modes 1200 ns T2.19.2 CD heartbeat duration All 10-Mbps modes 1000 ns TX_EN TX_CLK T2.19.1 T2.19.2 COL Figure 4-20. 10-Mbps Heartbeat Timing 4.7.20 10-Mbps Jabber Timing PARAMETER DESCRIPTION T2.20.1 Jabber activation time T2.20.2 Jabber deactivation time NOTES MIN TYP MAX UNIT 85 ms 500 ms TXE T2.20.1 T2.20.2 PMD output pair COL Figure 4-21. 10-Mbps Jabber Timing 4.7.21 10BASE-T Normal Link Pulse Timing PARAMETER NOTES (1) DESCRIPTION MIN TYP MAX UNIT T2.21.1 Pulse width 100 ns T2.21.2 Pulse period 16 ms (1) These specifications represent transmit timings. T2.21.2 T2.21.1 Normal link pulses Figure 4-22. 10BASE-T Normal Link Pulse Timing Specifications Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP 25 DP83848-EP SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 www.ti.com 4.7.22 Auto-Negotiation Fast Link Pulse (FLP) Timing PARAMETER DESCRIPTION NOTES MIN TYP MAX UNIT T2.22.1 Clock, data pulse width 100 ns T2.22.2 Clock pulse to clock pulse period 125 µs T2.22.3 Clock pulse to data pulse period 62 µs T2.22.4 Burst width 2 ms T2.22.5 FLP burst to FLP burst period 16 ms Data = 1 T2.22.2 T2.22.3 T2.22.1 T2.22.1 Fast link pulses data pulse clock pulse clock pulse T2.22.5 T2.22.4 FLP burst FLP burst Figure 4-23. Auto-Negotiation Fast Link Pulse (FLP) Timing 4.7.23 100BASE-TX Signal Detect Timing PARAMETER DESCRIPTION NOTES (1) MIN TYP MAX UNIT T2.23.1 SD internal turn-on time 1 ms T2.23.2 SD internal turn-off time 350 µs (1) The signal amplitude on PMD Input Pair must be TP-PMD compliant. PMD Input Pair T2.23.1 T2.23.2 SD+ internal Figure 4-24. 100BASE-TX Signal Detect Timing 26 Specifications Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP DP83848-EP www.ti.com SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 4.7.24 100-Mbps Internal Loopback Timing PARAMETER T2.24.1 (1) (2) NOTES (1) DESCRIPTION TX_EN to RX_DV loopback (2) MIN 100-Mbps internal loopback mode TYP MAX UNIT 240 ns Due to the nature of the descrambler function, all 100BASE-TX Loopback modes will cause an initial dead time of up to 550 µs, during which no data will be present at the receive MII outputs. The 100BASE-TX timing specified is based on device delays after the initial 550-µs dead time. Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN. TX_CLK TX_EN TXD[3:0] CRS T2.24.1 RX_CLK RX_DV RXD[3:0] Figure 4-25. 100-Mbps Internal Loopback Timing Specifications Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP 27 DP83848-EP SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 www.ti.com 4.7.25 10-Mbps Internal Loopback Timing PARAMETER T2.25.1 (1) NOTES (1) DESCRIPTION TX_EN to RX_DV loopback MIN 10-Mbps internal loopback mode TYP MAX 2 UNIT µs Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN. TX_CLK TX_EN TXD[3:0] CRS T2.25.1 RX_CLK RX_DV RXD[3:0] Figure 4-26. 10-Mbps Internal Loopback Timing 28 Specifications Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP DP83848-EP www.ti.com SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 4.7.26 RMII Transmit Timing PARAMETER DESCRIPTION NOTES MIN 50-MHz reference clock TYP MAX 20 UNIT T2.26.1 X1 clock period T2.26.2 TXD[1:0], TX_EN, data setup to X1 rising 3.70 ns T2.26.3 TXD[1:0], TX_EN, data hold from X1 rising 1.70 ns T2.26.4 X1 clock to PMD output pair latency From X1 rising edge to first bit of symbol ns 17 bits T2.26.1 X1 T2.26.2 TXD[1:0] TX_EN T2.26.3 Valid data T2.26.4 Symbol PMD output pair Figure 4-27. RMII Transmit Timing Specifications Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP 29 DP83848-EP SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 www.ti.com 4.7.27 RMII Receive Timing PARAMETER NOTES (1) DESCRIPTION (2) (3) MIN T2.27.1 X1 clock period T2.27.2 RXD[1:0], CRS_DV, RX_DV and RX_ER output delay from X1 rising T2.27.3 CRS ON delay From JK symbol on PMD receive pair to initial assertion of CRS_DV T2.27.4 CRS OFF delay T2.27.5 RXD[1:0] and RX_ER latency (1) (2) (3) TYP 50-MHz reference clock MAX 20 2 UNIT ns 14 ns 18.5 bits From TR symbol on PMD receive pair to initial deassertion of CRS_DV 27 bits From symbol on receive pair. Elasticity buffer set to default value (01). 38 bits Per the RMII Specification, output delays assume a 25-pF load. CRS_DV is asserted asynchronously in order to minimize latency of control signals through the why. CRS_DV may toggle synchronously at the end of the packet to indicate CRS deassertion. RX_DV is synchronous to X1. While not part of the RMII specification, this signal is provided to simplify recovery of receive data. PMD Input Pair IDLE (J/K) (TR) Data Data T2.27.4 T2.27.5 X1 T2.27.1 T2.27.2 T2.27.2 T2.27.2 T2.27.3 RX_DV CRS_DV T2.27.2 RXD[1:0] RX_ER Figure 4-28. RMII Receive Timing 30 Specifications Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP DP83848-EP www.ti.com SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 4.7.28 Isolation Timing PARAMETER MAX UNIT T2.28.1 From software clear of bit 10 in the BMCR register to the transition from Isolate to Normal Mode DESCRIPTION NOTES MIN TYP 100 µs T2.28.2 From deassertion of S/W or H/W reset to transition from Isolate to Normal mode 500 µs Clear bit 10 of BMCR (return to normal operation from Isolate mode) T2.28.1 Hardware or Software Reset (with PHYAD ¹ 00000) T2.28.2 MODE ISOLATE NORMAL Figure 4-29. Isolation Timing 4.7.29 25MHz_OUT Timing PARAMETER NOTES (1) DESCRIPTION T2.29.1 25MHz_OUT high/low time T2.29.2 25MHz_OUT propagation delay (1) MIN TYP MII mode 20 RMII mode 10 Relative to X1 MAX UNIT ns 8 ns 25MHz_OUT characteristics are dependent upon the X1 input characteristics. X1 T2.29.2 T2.29.1 T2.29.1 25 MHz_OUT Figure 4-30. 25MHz_OUT Timing Specifications Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP 31 DP83848-EP SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 www.ti.com 5 Detailed Description 5.1 Overview The device is 10/100 Mbps Ethernet transceiver with an extended temperature range of –55°C to 125°C. The ability to perform over extreme temperatures makes this device ideal for demanding environments like automotive, transportation and industrial applications. The DP83848-EP operates on a 3.3-V supply voltage with a typical 270-mW typical power consumption making this device suitable for low power applications. The device has Auto MDIX capability to select MDI or MDIX automatically. The device supports AutoNegotiation for selecting the highest performance mode of operation. This functionality can be turned off if a particular mode is to be forced. The device supports MII, RMII, and SNI interfaces thus being more flexible and increasing the number of compatible MPU. Interface options can be selected using strap options or register control. The device operates with 25-MHz clock when in MII mode and requires a 50-MHz clock when in RMII mode. 5.2 Functional Block Diagram RX_CLK RXD[3:0] RX_DV RX_ER CRS/CRS_DV COL MDC MDIO Serial Management TX_EN TX_CLK TXD[3:0] MII/RMII/SNI MII/RMII/SNI Interfaces TX_DATA TX_CLK MI Registers 10Base-T and 100Base-TX Transmit Block RX_DATA RX_CLK Auto-Negotiation State Machine 10Base-T and 100Base-TX Receive Block Clock Generation DAC 32 ADC Boundary Scan Auto-MDIX JTAG TD± RD± LED Drivers REFERENCE CLOCK Detailed Description LEDs Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP DP83848-EP www.ti.com 5.3 SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 Feature Description 5.3.1 Auto-Negotiation The Auto-Negotiation function provides a mechanism for exchanging configuration information between two ends of a link segment and automatically selecting the highest performance mode of operation supported by both devices. Fast Link Pulse (FLP) Bursts provide the signalling used to communicate Auto-Negotiation abilities between two devices at each end of a link segment. For further detail regarding Auto-Negotiation, refer to Clause 28 of the IEEE 802.3u specification. The DP83848-EP supports four different Ethernet protocols (10-Mbps Half Duplex, 10-Mbps Full Duplex, 100-Mbps Half Duplex, and 100Mbps Full Duplex), so the inclusion of Auto-Negotiation ensures that the highest performance protocol will be selected based on the advertised ability of the Link Partner. The Auto-Negotiation function within the DP83848-EP can be controlled either by internal register access or by the use of the AN0 pin. 5.3.1.1 Auto-Negotiation Pin Control The state of AN_EN, AN0 and AN1 determines whether the DP83848-EP is forced into a specific mode or auto-negotiation will advertise a specific ability (or set of abilities) as given in Table 5-1. These pins allow configuration options to be selected without requiring internal register access. The state of AN_EN, AN0 and AN1, upon power-up/reset, determines the state of bits [8:5] of the ANAR register. The auto-negotiation function selected at power-up or reset can be changed at any time by writing to the basic mode control register (BMCR) at address 0x00h. Table 5-1. Auto-Negotiation Modes AN_EN AN1 AN0 Forced Mode 0 0 0 10BASE-T, Half Duplex 0 0 1 10BASE-T, Full Duplex 0 1 0 100BASE-TX, Half Duplex 100BASE-TX, Full Duplex 0 1 1 AN_EN AN1 AN0 1 0 0 10BASE-T, Half or Full Duplex 1 0 1 100BASE-TX, Half or Full Duplex 1 1 0 10BASE-T Half Duplex 100BASE-TX, Half Duplex 1 1 1 10BASE-T, Half/Full Duplex 100BASE-TX, Half/Full Duplex+ 5.3.1.2 Advertised Mode Auto-Negotiation Register Control When Auto-Negotiation is enabled, the DP83848-EP transmits the abilities programmed into the AutoNegotiation Advertisement register (ANAR) at address 04h via FLP Bursts. Any combination of 10 Mbps, 100 Mbps, Half-Duplex, and Full Duplex modes may be selected. Auto-Negotiation Priority Resolution: 1. 100BASE-TX Full Duplex (Highest Priority) 2. 100BASE-TX Half Duplex 3. 10BASE-T Full Duplex 4. 10BASE-T Half Duplex (Lowest Priority) Detailed Description Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP 33 DP83848-EP SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 www.ti.com The Basic Mode Control Register (BMCR) at address 00h provides control for enabling, disabling, and restarting the Auto-Negotiation process. When Auto-Negotiation is disabled, the Speed Selection bit in the BMCR controls switching between 10-Mbps or 100-Mbps operation, and the Duplex Mode bit controls switching between full duplex operation and half duplex operation. The Speed Selection and Duplex Mode bits have no effect on the mode of operation when the Auto-Negotiation Enable bit is set. The Link Speed can be examined through the PHY Status Register (PHYSTS) at address 10h after a Link is achieved. The Basic Mode Status Register (BMSR) indicates the set of available abilities for technology types, AutoNegotiation ability, and Extended Register Capability. These bits are permanently set to indicate the full functionality of the DP83848-EP (only the 100BASE-T4 bit is not set because the DP83848-EP does not support that function). The BMSR also provides status on: • Whether or not Auto-Negotiation is complete • Whether or not the Link Partner is advertising that a remote fault has occurred • Whether or not valid link has been established • Support for Management Frame Preamble suppression The Auto-Negotiation Advertisement Register (ANAR) indicates the Auto-Negotiation abilities to be advertised by the DP83848-EP. All available abilities are transmitted by default, but any ability can be suppressed by writing to the ANAR. Updating the ANAR to suppress an ability is one way for a management agent to change (restrict) the technology that is used. The Auto-Negotiation Link Partner Ability Register (ANLPAR) at address 0x05h is used to receive the base link code word as well as all next page code words during the negotiation. Furthermore, the ANLPAR will be updated to either 0081h or 0021h for parallel detection to either 100 Mbps or 10 Mbps, respectively. The Auto-Negotiation Expansion Register (ANER) indicates additional Auto-Negotiation status. The ANER provides status on: • Whether or not a Parallel Detect Fault has occurred • Whether or not the Link Partner supports the Next Page function • Whether or not the DP83848-EP supports the Next Page function • Whether or not the current page being exchanged by Auto-Negotiation has been received • Whether or not the Link Partner supports Auto-Negotiation 5.3.1.3 Auto-Negotiation Parallel Detection The DP83848-EP supports the Parallel Detection function as defined in the IEEE 802.3u specification. Parallel Detection requires both the 10 Mbps and 100 Mbps receivers to monitor the receive signal and report link status to the Auto-Negotiation function. Auto-Negotiation uses this information to configure the correct technology in the event that the Link Partner does not support Auto-Negotiation but is transmitting link signals that the 100BASE-TX or 10BASE-T PMAs recognize as valid link signals. If the DP83848-EP completes Auto-Negotiation as a result of Parallel Detection, bits 5 and 7 within the ANLPAR register will be set to reflect the mode of operation present in the Link Partner. Note that bits 4:0 of the ANLPAR will also be set to 00001 based on a successful parallel detection to indicate a valid 802.3 selector field. Software may determine that negotiation completed via Parallel Detection by reading a zero in the Link Partner Auto-Negotiation Able bit once the Auto-Negotiation Complete bit is set. If configured for parallel detect mode and any condition other than a single good link occurs then the parallel detect fault bit will be set. 34 Detailed Description Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP DP83848-EP www.ti.com 5.3.1.4 SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 Auto-Negotiation Restart Once Auto-Negotiation has completed, it may be restarted at any time by setting bit 9 (Restart AutoNegotiation) of the BMCR to one. If the mode configured by a successful Auto-Negotiation loses a valid link, then the Auto-Negotiation process will resume and attempt to determine the configuration for the link. This function ensures that a valid configuration is maintained if the cable becomes disconnected. A renegotiation request from any entity, such as a management agent, will cause the DP83848-EP to halt any transmit data and link pulse activity until the break_link_timer expires (~1500 ms). Consequently, the Link Partner will go into link fail and normal Auto-Negotiation resumes. The DP83848-EP will resume Auto-Negotiation after the break_link_timer has expired by issuing FLP (Fast Link Pulse) bursts. 5.3.1.5 Enabling Auto-Negotiation via Software It is important to note that if the DP83848-EP has been initialized upon power-up as a non-autonegotiating device (forced technology), and it is then required that Auto-Negotiation or re-Auto-Negotiation be initiated via software, bit 12 (Auto-Negotiation Enable) of the Basic Mode Control Register (BMCR) must first be cleared and then set for any Auto-Negotiation function to take effect. 5.3.1.6 Auto-Negotiation Complete Time Parallel detection and Auto-Negotiation take approximately 2-3 seconds to complete. In addition, AutoNegotiation with next page should take approximately 2-3 seconds to complete, depending on the number of next pages sent. Refer to Clause 28 of the IEEE 802.3u standard for a full description of the individual timers related to Auto-Negotiation. 5.3.2 Auto-MDIX When enabled, this function uses Auto-Negotiation to determine the proper configuration for transmission and reception of data and subsequently selects the appropriate MDI pair for MDI/MDIX operation. The function uses a random seed to control switching of the crossover circuitry. This implementation complies with the corresponding IEEE 802.3 Auto-Negotiation and Crossover Specifications. Auto-MDIX is enabled by default and can be configured via strap or via PHYCR (19h) register, bits [15:14]. Neither Auto-Negotiation nor Auto-MDIX is required to be enabled in forcing crossover of the MDI pairs. Forced crossover can be achieved through the FORCE_MDIX bit, bit 14 of PHYCR (19h) register. Note: Auto-MDIX will not work in a forced mode of operation. 5.3.3 LED Interface The DP83848-EP supports three configurable light emitting diode (LED) pins. The device supports three LED configurations: Link, Speed, Activity and Collision. Functions are multiplexed among the LEDs. The PHYCR for the LEDs can also be selected through address 19h, bits [6:5]. Table 5-2. LED Mode Select MODE LED_CGF[1] (BIT 6) LED_CFG[0] (BIT 5) or (PIN 40) 1 don't care 1 ON for Good Link OFF for No Link ON in 100 Mbps OFF in 10 Mbps ON for Activity OFF for No Activity 2 0 0 ON for Good Link BLINK for Activity ON in 100 Mbps OFF in 10 Mbps ON for Collision OFF for No Collision 3 1 0 ON for Good Link BLINK for Activity ON in 100 Mbps OFF in 10 Mbps ON for Full Duplex OFF for Half Duplex LED_LINK LED_SPEED LED_ACT/COL Detailed Description Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP 35 DP83848-EP SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 www.ti.com The LED_LINK pin in Mode 1 indicates the link status of the port. In 100BASE-T mode, link is established as a result of input receive amplitude compliant with the TPPMD specifications which will result in internal generation of signal detect. A 10 Mbps Link is established as a result of the reception of at least seven consecutive normal link pulses or the reception of a valid 10BASE-T packet. This will cause the assertion of LED_LINK. LED_LINK will deassert in accordance with the Link Loss Timer as specified in the IEEE 802.3 specification. The LED_LINK pin in Mode 1 will be OFF when no LINK is present. The LED_LINK pin in Mode 2 and Mode 3 will be ON to indicate Link is good and BLINK to indicate activity is present on either transmit or receive activity. The LED_SPEED pin indicates 10 or 100 Mbps data rate of the port. The standard CMOS driver goes high when operating in 100 Mbps operation. The functionality of this LED is independent of mode selected. The LED_ACT/COL pin in Mode 1 indicates the presence of either transmit or receive activity. The LED will be ON for Activity and OFF for No Activity. In Mode 2, this pin indicates the Collision status of the port. The LED will be ON for Collision and OFF for No Collision. The LED_ACT/COL pin in Mode 3 indicates the presence of duplex status for 10-Mbps or 100-Mbps operation. The LED will be ON for full duplex and OFF for half duplex. In 10 Mbps half duplex mode, the collision LED is based on the COL signal. Since these LED pins are also used as strap options, the polarity of the LED is dependent on whether the pin is pulled up or down. 5.3.3.1 LEDs Since the auto-negotiation (AN) strap options share the LED output pins, the external components required for strapping and LED usage must be considered in order to avoid contention. Specifically, when the LED outputs are used to drive LEDs directly, the active state of each output driver is dependent on the logic level sampled by the corresponding AN input upon power-up/reset. For example, if a given AN input is resistively pulled low then the corresponding output will be configured as an active high driver. Conversely, if a given AN input is resistively pulled high, then the corresponding output will be configured as an active low driver. Refer to Figure 5-1 for an example of AN connections to external components. In this example, the AN strapping results in auto-negotiation with 10/100 half or full duplex advertised. The adaptive nature of the LED outputs helps to simplify potential implementation issues of these dual purpose pins. 36 Detailed Description Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP DP83848-EP SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 AN1 = 1 110 Ω AN0 = 1 2.2 kΩ 110 Ω 2.2 kΩ 110 Ω 2.2 kΩ AN_EN = 1 LED_LINK LED_SPEED LED_ACT/COL www.ti.com VCC Figure 5-1. AN Strapping and LED Loading Example 5.3.3.2 LED Direct Control The DP83848-EP provides another option to directly control any or all LED outputs through the LED direct control register (LEDCR), address 18h. The register does not provide read access to LEDs. 5.3.4 Internal Loopback The DP83848-EP includes a Loopback Test mode for facilitating system diagnostics. The Loopback mode is selected through bit 14 (Loopback) of the Basic Mode Control Register (BMCR). Writing 1 to this bit enables MII transmit data to be routed to the MII receive outputs. Loopback status may be checked in bit 3 of the PHY Status Register (PHYSTS). While in Loopback mode the data will not be transmitted onto the media. To ensure that the desired operating mode is maintained, Auto-Negotiation should be disabled before selecting the Loopback mode. 5.3.5 BIST The DP83848-EP incorporates an internal Built-in Self Test (BIST) circuit to accommodate in-circuit testing or diagnostics. The BIST circuit can be used to test the integrity of the transmit and receive data paths. BIST testing can be performed with the part in the internal loopback mode or externally looped back using a loopback cable fixture. The BIST is implemented with independent transmit and receive paths, with the transmit block generating a continuous stream of a pseudo random sequence. The user can select a 9 bit or 15 bit pseudo random sequence from the PSR_15 bit in the PHY Control Register (PHYCR). The received data is compared to the generated pseudo-random data by the BIST Linear Feedback Shift Register (LFSR) to determine the BIST pass/fail status. The pass/fail status of the BIST is stored in the BIST status bit in the PHYCR register. The status bit defaults to 0 (BIST fail) and will transition on a successful comparison. If an error (mis-compare) occurs, the status bit is latched and is cleared upon a subsequent write to the Start/Stop bit. For transmit VOD testing, the Packet BIST Continuous Mode can be used to allow continuous data transmission, setting BIST_CONT_MODE, bit 5, of CDCTRL1 (0x1Bh). The number of BIST errors can be monitored through the BIST Error Count in the CDCTRL1 (0x1Bh), bits [15:8]. Detailed Description Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP 37 DP83848-EP SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 5.3.6 www.ti.com Energy Detect Mode When Energy Detect is enabled and there is no activity on the cable, the DP83848-EP will remain in a low power mode while monitoring the transmission line. Activity on the line will cause the DP83848-EP to go through a normal power up sequence. Regardless of cable activity, the DP83848-EP will occasionally wake up the transmitter to put ED pulses on the line, but will otherwise draw as little power as possible. Energy detect functionality is controlled via register Energy Detect Control (EDCR), address 0x1Dh. 5.4 Device Functional Modes The DP83848-EP supports several modes of operation using the MII interface pins. The options are defined in the following sections and include: • MII mode • RMII mode • 10-Mb serial network interface (SNI) The modes of operation can be selected by strap options or register control. For RMII mode, it is required to use the strap option, since it requires a 50-MHz clock instead of the normal 25 MHz. In each of these modes, the IEEE 802.3 serial management interface is operational for device configuration and status. The serial management interface of the MII allows for the configuration and control of multiple PHY devices, gathering of status, error information, and the determination of the type and capabilities of the attached PHY(s). 5.4.1 MII Interface The DP83848-EP incorporates the Media Independent Interface (MII) as specified in Clause 22 of the IEEE 802.3u standard. This interface may be used to connect PHY devices to a MAC in 10/100-Mbps systems. This section describes the nibble-wide MII data interface. The nibble-wide MII data interface consists of a receive bus and a transmit bus each with control signals to facilitate data transfer between the PHY and the upper layer (MAC). 5.4.1.1 Nibble-wide MII Data Interface Clause 22 of the IEEE 802.3u specification defines the Media Independent Interface. This interface includes a dedicated receive bus and a dedicated transmit bus. These two data buses, along with various control and status signals, allow for the simultaneous exchange of data between the DP83848-EP and the upper layer agent (MAC). The receive interface consists of a nibble-wide data bus RXD[3:0], a receive error signal RX_ER, a receive data valid flag RX_DV, and a receive clock RX_CLK for synchronous transfer of the data. The receive clock operates at either 2.5 MHz to support 10-Mbps operation modes or at 25 MHz to support 100-Mbps operational modes. The transmit interface consists of a nibble-wide data bus TXD[3:0], a transmit enable control signal TX_EN, and a transmit clock TX_CLK which runs at either 2.5 MHz or 25 MHz. Additionally, the MII includes the carrier sense signal CRS, as well as a collision detect signal COL. The CRS signal asserts to indicate the reception of data from the network or as a function of transmit data in Half Duplex mode. The COL signal asserts as an indication of a collision which can occur during halfduplex operation when both a transmit and receive operation occur simultaneously. 5.4.1.2 Collision Detect For Half Duplex, a 10BASE-T or 100BASE-TX collision is detected when the receive and transmit channels are active simultaneously. Collisions are reported by the COL signal on the MII. 38 Detailed Description Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP DP83848-EP www.ti.com SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 If the DP83848-EP is transmitting in 10 Mbps mode when a collision is detected, the collision is not reported until seven bits have been received while in the collision state. This prevents a collision being reported incorrectly due to noise on the network. The COL signal remains set for the duration of the collision. If a collision occurs during a receive operation, it is immediately reported by the COL signal. When heartbeat is enabled (only applicable to 10 Mbps operation), approximately 1 µs after the transmission of each packet, a Signal Quality Error (SQE) signal of approximately 10 bit times is generated (internally) to indicate successful transmission. SQE is reported as a pulse on the COL signal of the MII. 5.4.1.3 Carrier Sense Carrier Sense (CRS) is asserted due to receive activity, once valid data is detected via the squelch function during 10 Mbps operation. During 100 Mbps operation CRS is asserted when a valid link (SD) and two non-contiguous zeros are detected on the line. For 10 or 100 Mbps Half Duplex operation, CRS is asserted during either packet transmission or reception. For 10 or 100 Mbps Full Duplex operation, CRS is asserted only due to receive activity. CRS is deasserted following an end of packet. 5.4.2 Reduced MII Interface The DP83848-EP incorporates the Reduced Media Independent Interface (RMII) as specified in the RMII specification (rev1.2) from the RMII Consortium. This interface may be used to connect PHY devices to a MAC in 10/100 Mbps systems using a reduced number of pins. In this mode, data is transferred 2-bits at a time using the 50-MHz RMII_REF clock for both transmit and receive. The following pins are used in RMII mode: • TX_EN • TXD[1:0] • RX_ER (optional for MAC) • CRS_DV • RXD[1:0] • X1 (RMII Reference clock is 50 MHz) In addition, the RMII mode supplies an RX_DV signal which allows for a simpler method of recovering receive data without having to separate RX_DV from the CRS_DV indication. This is especially useful for diagnostic testing where it may be desirable to externally loop Receive MII data directly to the transmitter. Because the reference clock operates at 10 times the data rate for 10 Mbps operation, transmit data is sampled every 10 clocks. Likewise, receive data will be generated every 10th clock so that an attached device can sample the data every 10 clocks. RMII mode requires a 50-MHz oscillator be connected to the device X1 pin. A 50-MHz crystal is not supported. To tolerate potential frequency differences between the 50-MHz reference clock and the recovered receive clock, the receive RMII function includes a programmable elasticity buffer. The elasticity buffer is programmable to minimize propagation delay based on expected packet size and clock accuracy. This allows for supporting a range of packet sizes including jumbo frames. The elasticity buffer will force Frame Check Sequence errors for packets which overrun or underrun the FIFO. Underrun and Overrun conditions can be reported in the RMII and Bypass Register (RBR). Table 53 indicates how to program the elasticity buffer fifo (in 4-bit increments) based on expected max packet size and clock accuracy. It assumes both clocks (RMII Reference clock and far-end Transmitter clock) have the same accuracy. Detailed Description Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP 39 DP83848-EP SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 www.ti.com Table 5-3. Supported Packet Sizes at ±50 ppm ±100 ppm for Each Clock Start Threshold RBR[1:0] Latency Tolerance Recommended Packet Size at ±50 ppm Recommended Packet Size at ±100 ppm 1 (4-bits) 2 bits 2,400 bytes 1,200 bytes 2 (8-bits) 6 bits 7,200 bytes 3,600 bytes 3 (12-bits) 10 bits 12,000 bytes 6,000 bytes 0 (16-bits) 14 bits 16,800 bytes 8,400 bytes 5.4.2.1 10 Mb Serial Network Interface (SNI) The DP83848-EP incorporates a 10-Mb serial network interface (SNI) which allows a simple serial data interface for 10-Mb only devices. This is also referred to as a 7-wire interface. While there is no defined standard for this interface, it is based on early 10-Mb physical layer devices. Data is clocked serially at 10 MHz using separate transmit and receive paths. The following pins are used in SNI mode: • TX_CLK • TX_EN • TXD[0] • RX_CLK • RXD[0] • CRS • COL 5.4.3 802.3u MII Serial Management Interface 5.4.3.1 Serial Management Register Access The serial management MII specification defines a set of thirty-two 16-bit status and control registers that are accessible through the management interface pins MDC and MDIO. The DP83848-EP implements all the required MII registers as well as several optional registers. These registers are fully described in Section 5.6. 5.4.3.2 Serial Management Access Protocol The serial control interface consists of two pins, Management Data Clock (MDC) and Management Data Input/Output (MDIO). MDC has a maximum clock rate of 25 MHz and no minimum rate. The MDIO line is bi-directional and may be shared by up to 32 devices. The MDIO frame format is shown below in Table 54. Table 5-4. Typical MDIO Frame Format MII Management Serial Protocol Read Operation Write Operation The MDIO pin requires a pullup resistor (1.5 kΩ) which, during IDLE and turnaround, will pull MDIO high. In order to initialize the MDIO interface, the station management entity sends a sequence of 32 contiguous logic ones on MDIO to provide the DP83848-EP with a sequence that can be used to establish synchronization. This preamble may be generated either by driving MDIO high for 32 consecutive MDC clock cycles, or by simply allowing the MDIO pullup resistor to pull the MDIO pin high during which time 32 MDC clock cycles are provided. In addition 32 MDC clock cycles should be used to re-sync the device if an invalid start, opcode, or turnaround bit is detected. The DP83848-EP waits until it has received this preamble sequence before responding to any other transaction. Once the DP83848-EP serial management port has been initialized no further preamble sequencing is required until after a power-on/reset, invalid Start, invalid Opcode, or invalid turnaround bit has occurred. 40 Detailed Description Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP DP83848-EP www.ti.com SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 The Start code is indicated by a pattern. This assures the MDIO line transitions from the default idle line state. Turnaround is defined as an idle bit time inserted between the Register Address field and the Data field. To avoid contention during a read transaction, no device shall actively drive the MDIO signal during the first bit of Turnaround. The addressed DP83848-EP drives the MDIO with a zero for the second bit of turnaround and follows this with the required data. Figure 5-2 shows the timing relationship between MDC and the MDIO as driven/received by the Station (STA) and the DP83848-EP (PHY) for a typical register read access. For write transactions, the station management entity writes data to the addressed DP83848-EP thus eliminating the requirement for MDIO Turnaround. The Turnaround time is filled by the management entity by inserting . Figure 5-3 shows the timing relationship for a typical MII register write access. MDC z MDIO z (STA) z MDIO z (PHY) z Idle 0 1 Start 1 0 0 Opcode (Read) 1 1 0 0 0 0 0 0 z 0 0 Register Address (00h = BMCR) PHY Address (PHYAD = 0Ch) 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 Idle Register Data TA 0 z Figure 5-2. Typical MDC/MDIO Read Operation MDC z MDIO z (STA) z 0 Idle Start 1 0 1 Opcode (Write) 0 1 1 0 0 0 PHY Address (PHYAD = 0Ch) 0 0 0 0 Register Address (00h = BMCR) 1 0 0 0 0 TA 0 0 0 0 0 0 0 0 0 0 0 0 Register Data 0 z Idle Figure 5-3. Typical MDC/MDIO Write Operation 5.4.3.3 Serial Management Preamble Suppression The DP83848-EP supports a Preamble Suppression mode as indicated by a one in bit 6 of the Basic Mode Status Register (BMSR, address 01h.) If the station management entity (i.e. MAC or other management controller) determines that all PHYs in the system support Preamble Suppression by returning a one in this bit, then the station management entity need not generate preamble for each management transaction. The DP83848-EP requires a single initialization sequence of 32 bits of preamble following hardware/software reset. This requirement is generally met by the mandatory pullup resistor on MDIO in conjunction with a continuous MDC, or the management access made to determine whether Preamble Suppression is supported. While the DP83848-EP requires an initial preamble sequence of 32 bits for management initialization, it does not require a full 32-bit sequence between each subsequent transaction. A minimum of one idle bit between management transactions is required as specified in the IEEE 802.3u specification. Detailed Description Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP 41 DP83848-EP SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 5.4.4 www.ti.com PHY Address The 5 PHY address inputs pins are shared with the RXD[3:0] pins and COL pin are shown below. Table 5-5. PHY Address Mapping Pin No. PHYAD Function 42 PHYAD0 RXD Function COL 43 PHYAD1 RXD_0 44 PHYAD2 RXD_1 45 PHYAD3 RXD_2 46 PHYAD4 RXD_3 The DP83848-EP can be set to respond to any of 32 possible PHY addresses via strap pins. The information is latched into the PHYCR register (address 19h, bits [4:0]) at device power-up and hardware reset. The PHY Address pins are shared with the RXD and COL pins. Each DP83848-EP or port sharing an MDIO bus in a system must have a unique physical address. The DP83848-EP supports PHY Address strapping values 0 () through 31 (). Strapping PHY Address 0 puts the part into Isolate Mode. It should also be noted that selecting PHY Address 0 via an MDIO write to PHYCR will not put the device in Isolate Mode. See Section 5.4.4.1 for more information. For further detail relating to the latch-in timing requirements of the PHY Address pins, as well as the other hardware configuration pins, refer to the Reset summary in Section 5.4.6. Because the PHYAD[0] pin has weak internal pullup resistor and PHYAD[4:1] pins have weak internal pulldown resistors, the default setting for the PHY address is 00001 (0x01h). Refer to Figure 5-4 for an example of a PHYAD connection to external components. In this example, the PHYAD strapping results in address 000101 (0x03h). Figure 5-4. PHYAD Strapping Example 5.4.4.1 MII Isolate Mode The DP83848-EP can be put into MII Isolate mode by writing to bit 10 of the BMCR register or by strapping in Physical Address 0. It should be noted that selecting Physical Address 0 via an MDIO write to PHYCR will not put the device in the MII isolate mode. When in the MII isolate mode, the DP83848-EP does not respond to packet data present at TXD[3:0], TX_EN inputs and presents a high impedance on the TX_CLK, RX_CLK, RX_DV, RX_ER, RXD[3:0], COL, and CRS outputs. When in Isolate mode, the DP83848-EP will continue to respond to all management transactions. While in Isolate mode, the PMD output pair will not transmit packet data but will continue to source 100BASE-TX scrambled idles or 10BASE-T normal link pulses. 42 Detailed Description Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP DP83848-EP www.ti.com SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 The DP83848-EP can Auto-Negotiate or parallel detect to a specific technology depending on the receive signal at the PMD input pair. A valid link can be established for the receiver even when the DP83848-EP is in Isolate mode. 5.4.5 Half Duplex vs Full Duplex The DP83848-EP supports both half and full duplex operation at both 10 Mbps and 100 Mbps speeds. Half-duplex relies on the CSMA/CD protocol to handle collisions and network access. In Half-Duplex mode, CRS responds to both transmit and receive activity in order to maintain compliance with the IEEE 802.3 specification. Because the DP83848-EP is designed to support simultaneous transmit and receive activity, it is capable of supporting full-duplex switched applications with a throughput of up to 200 Mbps per port when operating in 100BASE-TX. CSMA/CD protocol does not apply to full-duplex operation so DP83848-EP disables its own internal collision sensing and reporting functions and modifies the behavior of Carrier Sense (CRS) such that it indicates only receive activity. This allows a full-duplex capable MAC to operate properly. All modes of operation (100BASE-TX and 10BASE-T) can run either half-duplex or full-duplex. Additionally, other than CRS and Collision reporting, all remaining MII signaling remains the same regardless of the selected duplex mode. It is important to understand that while Auto-Negotiation with the use of Fast Link Pulse code words can interpret and configure to full-duplex operation, parallel detection can not recognize the difference between full and half-duplex from a fixed 10-Mbps or 100-Mbps link partner over twisted pair. As specified in the 802.3u specification, if a far-end link partner is configured to a forced full duplex 100BASE-TX ability, the parallel detection state machine in the partner would be unable to detect the full duplex capability of the far-end link partner. This link segment would negotiate to a half duplex 100BASE-TX configuration (same scenario for 10 Mbps). 5.4.6 Reset Operation The DP83848-EP includes an internal power-on reset (POR) function and does not need to be explicitly reset for normal operation after power up. If required during normal operation, the device can be reset by a hardware or software reset. 5.4.6.1 Hardware Reset A hardware reset is accomplished by applying a low pulse (TTL level), with a duration of at least 1 µs, to the RESET_N pin. This will reset the device such that all registers will be reinitialized to default values and the hardware configuration values will be re-latched into the device (similar to the power-up/reset operation). 5.4.6.2 Software Reset A software reset is accomplished by setting the reset bit (bit 15) of the Basic Mode Control Register (BMCR). The period from the point in time when the reset bit is set to the point in time when software reset has concluded is approximately 1 µs. A software reset will reset the device such that all the registers will be re-initialized to default values and the hardware configuration values will be re-latched into the device. Software driver code must wait 3 µs following a software reset before allowing further serial MII operations with the DP83848-EP Detailed Description Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP 43 DP83848-EP SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 5.5 www.ti.com Programming 5.5.1 Architecture This section describes the operations within each transceiver module, 100BASE-TX and 10BASE-T. Each operation consists of several functional blocks and described in the following: • 100BASE-TX Transmitter • 100BASE-TX Receiver • 10BASE-T Transceiver Module 5.5.1.1 100BASE-TX Transmitter The 100BASE-TX transmitter consists of several functional blocks which convert synchronous 4-bit nibble data, as provided by the MII, to a scrambled MLT-3 125-Mbps serial data stream. Because the 100BASETX TP-PMD is integrated, the differential output pins, PMD Output Pair, can be directly routed to the magnetics. The block diagram in Figure 5-5 provides an overview of each functional block within the 100BASE-TX transmit section. The Transmitter section consists of the following functional blocks: • Code-group Encoder and Injection block • Scrambler block (bypass option) • NRZ to NRZI encoder block • Binary to MLT-3 converter / Common Driver The bypass option for the functional blocks within the 100BASE-TX transmitter provides flexibility for applications where data conversion is not always required. The DP83848-EP implements the 100BASETX transmit state machine diagram as specified in the IEEE 802.3u Standard, Clause 24. Figure 5-5. 100BASE-TX Transmit Block Diagram 44 Detailed Description Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP DP83848-EP www.ti.com SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 Table 5-6. 4B5B Code-Group Encoding/Decoding DATA CODES 0 11110 0000 1 01001 0001 2 10100 0010 3 10101 0011 4 01010 0100 5 01011 0101 6 01110 0110 7 01111 0111 8 10010 1000 9 10011 1001 A 10110 1010 B 10111 1011 C 11010 1100 D 11011 1101 E 11100 1110 F 11101 1111 H 00100 HALT code-group - Error code I 11111 Inter-Packet IDLE - 0000 (1) J 11000 First Start of Packet - 0101 (1) K 10001 Second Start of Packet - 0101 (1) T 01101 First End of Packet - 0000 (1) R 00111 Second End of Packet - 0000 (1) IDLE AND CONTROL CODES INVALID CODES (1) V 00000 V 00001 V 00010 V 00011 V 00101 V 00110 V 01000 V 01100 Control code-groups I, J, K, T, and R in data fields will be mapped as invalid codes, together with RX_ER asserted. 5.5.1.1.1 Code-Group Encoding and Injection The code-group encoder converts 4-bit (4B) nibble data generated by the MAC into 5-bit (5B) code-groups for transmission. This conversion is required to allow control data to be combined with packet data codegroups. See Table 5-6 for 4B to 5B code-group mapping details. The code-group encoder substitutes the first 8-bits of the MAC preamble with a J/K code-group pair (11000 10001) upon transmission. The code-group encoder continues to replace subsequent 4B preamble and data nibbles with corresponding 5B code-groups. At the end of the transmit packet, upon the deassertion of Transmit Enable signal from the MAC, the code-group encoder injects the T/R code-group pair (01101 00111) indicating the end of the frame. After the T/R code-group pair, the code-group encoder continuously injects IDLEs into the transmit data stream until the next transmit packet is detected (reassertion of Transmit Enable). Detailed Description Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP 45 DP83848-EP SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 www.ti.com 5.5.1.1.2 Scrambler The scrambler is required to control the radiated emissions at the media connector and on the twisted-pair cable (for 100BASE-TX applications). By scrambling the data, the total energy launched onto the cable is randomly distributed over a wide frequency range. Without the scrambler, energy levels at the PMD and on the cable could peak beyond FCC limitations at frequencies related to repeating 5B sequences (that is, continuous transmission of IDLEs). The scrambler is configured as a closed loop linear feedback shift register (LFSR) with an 11-bit polynomial. The output of the closed loop LFSR is X-ORd with the serial NRZ data from the code-group encoder. The result is a scrambled data stream with sufficient randomization to decrease radiated emissions at certain frequencies by as much as 20 dB. The DP83848-EP uses the PHY_ID (pins PHYAD [4:1]) to set a unique seed value. 5.5.1.1.3 NRZ to NRZI Encoder After the transmit data stream has been serialized and scrambled, the data must be NRZI encoded in order to comply with the TP-PMD standard for 100BASE-TX transmission over Category-5 Unshielded twisted-pair cable. 5.5.1.1.4 Binary to MLT-3 Convertor The Binary to MLT-3 conversion is accomplished by converting the serial binary data stream output from the NRZI encoder into two binary data streams with alternately phased logic one events. These two binary streams are then fed to the twisted-pair output driver which converts the voltage to current and alternately drives either side of the transmit transformer primary winding, resulting in a MLT-3 signal. The 100BASE-TX MLT-3 signal sourced by the PMD Output Pair common driver is slew rate controlled. This should be considered when selecting AC coupling magnetics to ensure TP-PMD Standard compliant transition times (3 ns < Tr < 5 ns). The 100BASE-TX transmit TP-PMD function within the DP83848-EP is capable of sourcing only MLT-3 encoded data. Binary output from the PMD Output Pair is not possible in 100 Mbps mode. 5.5.1.2 100BASE-TX Receiver The 100BASE-TX receiver consists of several functional blocks which convert the scrambled MLT-3 125 Mbps serial data stream to synchronous 4-bit nibble data that is provided to the MII. Because the 100BASE-TX TP-PMD is integrated, the differential input pins, RD±, can be directly routed from the AC coupling magnetics. See Figure 5-6 for a block diagram of the 100BASE-TX receive function. This provides an overview of each functional block within the 100BASE-TX receive section. The Receive section consists of the following functional blocks: • Analog Front End • Digital Signal Processor • Signal Detect • MLT-3 to Binary Decoder • NRZI to NRZ Decoder • Serial to Parallel • Descrambler • Code Group Alignment • 4B/5B Decoder • Link Integrity Monitor • Bad SSD Detection 46 Detailed Description Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP DP83848-EP www.ti.com SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 5.5.1.2.1 Analog Front End In addition to the Digital Equalization and Gain Control, the DP83848-EP includes Analog Equalization and Gain Control in the Analog Front End. The Analog Equalization reduces the amount of Digital Equalization required in the DSP. 5.5.1.2.2 Digital Signal Processor The Digital Signal Processor includes Adaptive Equalization with Gain Control and Base Line Wander Compensation. Figure 5-6. 100BASE-TX Receive Block Diagram 5.5.1.2.2.1 Digital Adaptive Equalization and Gain Control When transmitting data at high speeds over copper twisted-pair cable, frequency dependent attenuation becomes a concern. In high-speed twisted-pair signalling, the frequency content of the transmitted signal can vary greatly during normal operation based primarily on the randomness of the scrambled data stream. This variation in signal attenuation caused by frequency variations must be compensated to ensure the integrity of the transmission. To ensure quality transmission when employing MLT-3 encoding, the compensation must be able to adapt to various cable lengths and cable types depending on the installed environment. The selection of long cable lengths for a given implementation, requires significant compensation which will over-compensate for shorter, less attenuating lengths. Conversely, the selection of short or intermediate cable lengths requiring less compensation will cause serious under-compensation for longer length cables. The compensation or equalization must be adaptive to ensure proper conditioning of the received signal independent of the cable length. Detailed Description Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP 47 DP83848-EP SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 www.ti.com The DP83848-EP uses an extremely robust equalization scheme referred as ‘Digital Adaptive Equalization.’ The Digital Equalizer removes ISI (inter symbol interference) from the receive data stream by continuously adapting to provide a filter with the inverse frequency response of the channel. Equalization is combined with an adaptive gain control stage. This enables the receive 'eye pattern' to be opened sufficiently to allow very reliable data recovery. The curves given in Figure 5-8 illustrate attenuation at certain frequencies for given cable lengths. This is derived from the worst case frequency vs attenuation figures as specified in the EIA/TIA Bulletin TSB-36. These curves indicate the significant variations in signal attenuation that must be compensated for by the receive adaptive equalization circuit. Attenuation versus Frequency 35 150m 30 130m Attenuation (dB) 25 100m 20 15 50m 10 5 0m 0 0 20 40 60 80 Frequency (MHz) 100 120 Figure 5-7. EIA/TIA Attenuation vs Frequency for 0, 50, 100, 130, and 150 M of CAT 5 Cable 5.5.1.2.2.2 Base Line Wander Compensation Figure 5-8. 100BASE-TX BLW Event 48 Detailed Description Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP DP83848-EP www.ti.com SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 The DP83848-EP is completely ANSI TP-PMD compliant and includes Base Line Wander (BLW) compensation. The BLW compensation block can successfully recover the TP-PMD defined “killer” pattern. BLW can generally be defined as the change in the average DC content, relatively short period over time, of an AC coupled digital transmission over a given transmission medium. (that is, copper wire). BLW results from the interaction between the low frequency components of a transmitted bit stream and the frequency response of the AC coupling component(s) within the transmission system. If the low frequency content of the digital bit stream goes below the low frequency pole of the AC coupling transformers then the droop characteristics of the transformers will dominate resulting in potentially serious BLW. The digital oscilloscope plot provided in Figure 5-9 illustrates the severity of the BLW event that can theoretically be generated during 100BASE-TX packet transmission. This event consists of approximately 800 mV of DC offset for a period of 120 ms. Left uncompensated, events such as this can cause packet loss. 5.5.1.2.3 Signal Detect The signal detect function of the DP83848-EP is incorporated to meet the specifications mandated by the ANSI FDDI TP-PMD Standard as well as the IEEE 802.3 100BASE-TX Standard for both voltage thresholds and timing parameters. Note that the reception of normal 10BASE-T link pulses and fast link pulses per IEEE 802.3u AutoNegotiation by the 100BASE-TX receiver do not cause the DP83848-EP to assert signal detect. 5.5.1.2.4 MLT-3 to NRZI Decoder The DP83848-EP decodes the MLT-3 information from the Digital Adaptive Equalizer block to binary NRZI data. 5.5.1.2.5 NRZI to NRZ In a typical application, the NRZI to NRZ decoder is required in order to present NRZ formatted data to the descrambler. 5.5.1.2.6 Serial to Parallel The 100BASE-TX receiver includes a Serial to Parallel converter which supplies 5-bit wide data symbols to the PCS Rx state machine. 5.5.1.2.7 Descrambler A serial descrambler is used to de-scramble the received NRZ data. The descrambler has to generate an identical data scrambling sequence (N) in order to recover the original unscrambled data (UD) from the scrambled data (SD) as represented in the equations: (1) Synchronization of the descrambler to the original scrambling sequence (N) is achieved based on the knowledge that the incoming scrambled data stream consists of scrambled IDLE data. After the descrambler has recognized 12 consecutive IDLE code-groups, where an unscrambled IDLE code-group in 5B NRZ is equal to five consecutive ones (11111), it will synchronize to the receive data stream and generate unscrambled data in the form of unaligned 5B code-groups. Detailed Description Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP 49 DP83848-EP SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 www.ti.com In order to maintain synchronization, the descrambler must continuously monitor the validity of the unscrambled data that it generates. To ensure this, a line state monitor and a hold timer are used to constantly monitor the synchronization status. Upon synchronization of the descrambler the hold timer starts a 722-µs countdown. Upon detection of sufficient IDLE code-groups (58 bit times) within the 722-µs period, the hold timer will reset and begin a new countdown. This monitoring operation will continue indefinitely given a properly operating network connection with good signal integrity. If the line state monitor does not recognize sufficient unscrambled IDLE code-groups within the 722-µs period, the entire descrambler will be forced out of the current state of synchronization and reset in order to re-acquire synchronization. 5.5.1.2.8 Code-group Alignment The code-group alignment module operates on unaligned 5-bit data from the descrambler (or, if the descrambler is bypassed, directly from the NRZI/NRZ decoder) and converts it into 5B code-group data (5 bits). Code-group alignment occurs after the J/K code-group pair is detected. Once the J/K code-group pair (11000 10001) is detected, subsequent data is aligned on a fixed boundary. 5.5.1.2.9 4B/5B Decoder The code-group decoder functions as a look up table that translates incoming 5B code-groups into 4B nibbles. The code-group decoder first detects the J/K code-group pair preceded by IDLE code-groups and replaces the J/K with MAC preamble. Specifically, the J/K 10-bit code-group pair is replaced by the nibble pair (0101 0101). All subsequent 5B code-groups are converted to the corresponding 4B nibbles for the duration of the entire packet. This conversion ceases upon the detection of the T/R code-group pair denoting the End of Stream Delimiter (ESD) or with the reception of a minimum of two IDLE code-groups. 5.5.1.2.10 100BASE-TX Link Integrity Monitor The 100 Base TX Link monitor ensures that a valid and stable link is established before enabling both the Transmit and Receive PCS layer. Signal detect must be valid for 395 µs to allow the link monitor to enter the 'Link Up' state, and enable the transmit and receive functions. 5.5.1.2.11 Bad SSD Detection A Bad Start of Stream Delimiter (Bad SSD) is any transition from consecutive idle code-groups to non-idle code-groups which is not prefixed by the code-group pair /J/K. If this condition is detected, the DP83848-EP will assert RX_ER and present RXD[3:0] = 1110 to the MII for the cycles that correspond to received 5B code-groups until at least two IDLE code groups are detected. In addition, the False Carrier Sense Counter register (FCSCR) will be incremented by one. Once at least two IDLE code groups are detected, RX_ER and CRS become de-asserted. 5.5.1.3 10BASE-T Transceiver Module The 10BASE-T Transceiver Module is IEEE 802.3 compliant. It includes the receiver, transmitter, collision, heartbeat, loopback, jabber, and link integrity functions, as defined in the standard. An external filter is not required on the 10BASE-T interface because this is integrated inside the DP83848-EP. This section focuses on the general 10BASE-T system level operation. 5.5.1.3.1 Operational Modes The DP83848-EP has two basic 10BASE-T operational modes: • Half Duplex mode • Full Duplex mode 50 Detailed Description Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP DP83848-EP www.ti.com SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 5.5.1.3.1.1 Half Duplex Mode In Half Duplex mode the DP83848-EP functions as a standard IEEE 802.3 10BASE-T transceiver supporting the CSMA/CD protocol. 5.5.1.3.1.2 Full Duplex Mode In Full Duplex mode the DP83848-EP can simultaneously transmit and receive without asserting the collision signal. The 10-Mbps ENDEC is designed to encode and decode simultaneously. 5.5.1.3.2 Smart Squelch The smart squelch is responsible for determining when valid data is present on the differential receive inputs. The DP83848-EP implements an intelligent receive squelch to ensure that impulse noise on the receive inputs will not be mistaken for a valid signal. Smart squelch operation is independent of the 10BASE-T operational mode. The squelch circuitry employs a combination of amplitude and timing measurements (as specified in the IEEE 802.3 10BSE-T standard) to determine the validity of data on the twisted-pair inputs (see Figure 59). The signal at the start of a packet is checked by the smart squelch and any pulses not exceeding the squelch level (either positive or negative, depending upon polarity) will be rejected. Once this first squelch level is overcome correctly, the opposite squelch level must then be exceeded within 150 ns. Finally the signal must again exceed the original squelch level within 150 ns to ensure that the input waveform will not be rejected. This checking procedure results in the loss of typically three preamble bits at the beginning of each packet. Only after all these conditions have been satisfied will a control signal be generated to indicate to the remainder of the circuitry that valid data is present. At this time, the smart squelch circuitry is reset. Valid data is considered to be present until the squelch level has not been generated for a time longer than 150 ns, indicating the End of Packet. Once good data has been detected, the squelch levels are reduced to minimize the effect of noise causing premature End of Packet detection. Figure 5-9. 10BASE-T Twisted-Pair Smart Squelch Operation 5.5.1.3.3 Collision Detection and SQE When in Half Duplex, a 10BASE-T collision is detected when the receive and transmit channels are active simultaneously. Collisions are reported by the COL signal on the MII. Collisions are also reported when a jabber condition is detected. The COL signal remains set for the duration of the collision. If the PHY is receiving when a collision is detected it is reported immediately (through the COL pin). Detailed Description Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP 51 DP83848-EP SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 www.ti.com When heartbeat is enabled, approximately 1 µs after the transmission of each packet, a Signal Quality Error (SQE) signal of approximately 10-bit times is generated to indicate successful transmission. SQE is reported as a pulse on the COL signal of the MII. The SQE test is inhibited when the PHY is set in full duplex mode. SQE can also be inhibited by setting the HEARTBEAT_DIS bit in the 10BTSCR register. 52 Detailed Description Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP DP83848-EP www.ti.com SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 5.5.1.3.4 Carrier Sense Carrier Sense (CRS) may be asserted due to receive activity once valid data is detected via the squelch function. For 10-Mbps Half Duplex operation, CRS is asserted during either packet transmission or reception. For 10-Mbps Full Duplex operation, CRS is asserted only during receive activity. CRS is deasserted following an end of packet. 5.5.1.3.5 Normal Link Pulse Detection and Generation The link pulse generator produces pulses as defined in the IEEE 802.3 10BASE-T standard. Each link pulse is nominally 100 ns in duration and transmitted every 16 ms in the absence of transmit data. Link pulses are used to check the integrity of the connection with the remote end. If valid link pulses are not received, the link detector disables the 10BASE-T twisted-pair transmitter, receiver and collision detection functions. When the link integrity function is disabled (FORCE_LINK_10 of the 10BTSCR register), a good link is forced and the 10BASE-T transceiver will operate regardless of the presence of link pulses. 5.5.1.3.6 Jabber Function The jabber function monitors the output of DP83848-EP and disables the transmitter if it tries to transmit a packet of longer than legal size. A jabber timer monitors the transmitter and disables the transmission if the transmitter is active for approximately 85 ms. Once disabled by the Jabber function, the transmitter stays disabled for the entire time that the ENDEC module's internal transmit enable is asserted. This signal has to be de-asserted for approximately 500 ms (the “unjab” time) before the Jabber function re-enables the transmit outputs. The Jabber function is only relevant in 10BASE-T mode. 5.5.1.3.7 Automatic Link Polarity Detection and Correction The DP83848-EP's 10BASE-T transceiver module incorporates an automatic link polarity detection circuit. When three consecutive inverted link pulses are received, bad polarity is reported. A polarity reversal can be caused by a wiring error at either end of the cable, usually at the Main Distribution Frame (MDF) or patch panel in the wiring closet. The bad polarity condition is latched in the 10BTSCR register. The DP83848-EP's 10BASE-T transceiver module corrects for this error internally and will continue to decode received data correctly. This eliminates the need to correct the wiring error immediately. 5.5.1.3.8 Transmit and Receive Filtering External 10BASE-T filters are not required when using the DP83848-EP, as the required signal conditioning is integrated into the device. Only isolation transformers and impedance matching resistors are required for the 10BASE-T transmit and receive interface. The internal transmit filtering ensures that all the harmonics in the transmit signal are attenuated by at least 30 dB. 5.5.1.3.9 Transmitter The encoder begins operation when the Transmit Enable input (TX_EN) goes high and converts NRZ data to pre-emphasized Manchester data for the transceiver. For the duration of TX_EN, the serialized Transmit Data (TXD) is encoded for the transmit-driver pair (PMD Output Pair). TXD must be valid on the rising edge of Transmit Clock (TX_CLK). Transmission ends when TX_EN deasserts. The last transition is always positive; it occurs at the center of the bit cell if the last bit is a one, or at the end of the bit cell if the last bit is a zero. Detailed Description Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP 53 DP83848-EP SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 www.ti.com 5.5.1.3.10 Receiver The decoder detects the end of a frame when no additional mid-bit transitions are detected. Within one and a half bit times after the last bit, carrier sense is de-asserted. Receive clock stays active for five more bit times after CRS goes low, to ensure the receive timings of the controller. 5.6 Memory Table 5-7. Register Map OFFSET ACCESS TAG 0 RW BMCR Basic Mode Control Register 1 RO BMSR Basic Mode Status Register 02h 2 RO PHYIDR1 PHY Identifier Register #1 03h 3 RO PHYIDR2 PHY Identifier Register #2 04h 4 RW ANAR 05h 5 RW ANLPAR Auto-Negotiation Link Partner Ability Register (Base Page) 05h 5 RW ANLPARNP Auto-Negotiation Link Partner Ability Register (Next Page) 06h 6 RW ANER 07h 7 RW ANNPTR 08h-Fh 8-15 RW RESERVED HEX DECIMAL 00h 01h DESCRIPTION Auto-Negotiation Advertisement Register Auto-Negotiation Expansion Register Auto-Negotiation Next Page TX RESERVED EXTENDED REGISTERS 54 10h 16 RO PHYSTS 11h 17 RW MICR PHY Status Register MII Interrupt Control Register 12h 18 RO MISR MII Interrupt Status Register 13h 19 RW RESERVED 14h 20 RO FCSCR 15h 21 RO RECR Receive Error Counter Register 16h 22 RW PCSR PCS Sub-Layer Configuration and Status Register 17h 23 RW RBR 18h 24 RW LEDCR LED Direct Control Register 19h 25 RW PHYCR PHY Control Register 1Ah 26 RW 10BTSCR 10Base-T Status/Control Register 1Bh 27 RW CDCTRL1 CD Test Control Register and BIST Extensions Register 1Ch 28 RW RESERVED 1Dh 29 RW EDCR 1Eh-1Fh 30-31 RW RESERVED RESERVED False Carrier Sense Counter Register RMII and Bypass Register RESERVED Energy Detect Control Register RESERVED Detailed Description Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP DP83848-EP www.ti.com SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 Table 5-8. Register Table REGISTER NAME ADDRESS TAG BIT 15 BIT 14 Basic Mode Control Register 00h BMCR Reset Loopback Basic Mode Status Register 01h BMSR 100Base -T4 PHY Identifier Register 1 02h PHYIDR 1 OUI MSB PHY Identifier Register 2 03h PHYIDR 2 OUI LSB AutoNegotiation Advertisement Register 04h ANAR Next Page Ind Reserved AutoNegotiation Link Partner Ability Register (Base Page) 05h ANLPAR Next Page Ind AutoNegotiation Link Partner Ability Register Next Page 05h ANNext LPARNP Page Ind AutoNegotiation Expansion Register 06h ANER Reserved AutoNegotiation Next Page TX Register 07h ANNPTR Reserved 08-0fh Reserved BIT 13 BIT 12 AutoSpeed Neg Selection Enable BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT0 Power Down Isolate Restart AutoNeg Duplex Mode Collision Test Reserved Reserved Reserved Reserved Reserved Reserved Reserved 10BaseT HDX Reserved Reserved Reserved Reserved MF Preamble Suppress AutoNeg Complete Remote Fault AutoNeg Ability Link Status Jabber Detect Extended Capability OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI LSB OUI LSB OUI LSB VNDR_ MDL VNDR_ MDL VNDR_ MDL VNDR_ MDL VNDR_ MDL VNDR_ MDL MDL_ REV MDL_ REV MDL_ REV MDL_ REV Remote Fault Reserved ASM_ DIR PAUSE T4 TX_FD TX 10_FD 10 Protocol Protocol Protocol Protocol Protocol Selection Selection Selection Selection Selection ACK Remote Fault Reserved ASM_ DIR PAUSE T4 TX_FD TX 10_FD 10 Protocol Protocol Protocol Protocol Protocol Selection Selection Selection Selection Selection ACK Message Page ACK2 Toggle Code Code Code Code Code Code Code Code Code Code Code Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PDF LP_NP_ ABLE NP_ ABLE PAGE_ RX LP_AN_ ABLE Next Page Ind Reserved Message ACK2 Page TOG_TX CODE CODE CODE CODE CODE CODE CODE CODE CODE CODE CODE Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 100Base 100Base 10Base-TX FDX -TX HDX T FDX OUI MSB OUI MSB OUI LSB OUI LSB Reserved Reserved Detailed Description Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP 55 DP83848-EP SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 www.ti.com Table 5-8. Register Table (continued) REGISTER NAME ADDRESS TAG BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT0 EXTENDED REGISTERS PHY Status Register 10h PHYSTS Reserved MDI-X mode Rx Err Latch Polarity Status False Carrier Sense Signal Detect Descram Page Lock Receive MII Inter- Remote rupt Fault Jabber Detect AutoNeg Complete Loopback Status Duplex Status Speed Status Link Status MII Interrupt Control Register 11h MICR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved TINT INTEN INT_OE MII Interrupt Status and Misc. Control Register 12h MISR Reserved ED_INT LINK_ INT SPD_ INT DUP_ INT ANC_ INT FHF_ INT RHF_ INT Reserved UNMSK _ ED UNMSK _ LINK UNMSK _ JAB UNMSK _ RF UNMSK _ ANC UNMSK _ FHF UNMSK _ RHF Reserved 13h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved False Carrier Sense Counter Register 14h FCSCR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved FCSCNT FCSCNT FCSCNT FCSCNT FCSCNT FCSCNT FCSCNT FCSCNT Receive Error Counter Register 15h RECR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RXERCNT RXERCNT RXERCNT RXERCNT RXERCNT RXERCNT PCS SubLayer Configuration and Status Register 16h PCSR Reserved Reserved Reserved BYP_4B 5B Reserved TQ_EN SD_FOR SD_ CE_PMA OPTION DESC_ TIME Reserved FORCE_ Re100_OK served Reserved DE SCRAM NRZI_ SCRAM _ BYPASS _ BYPASS BYPASS RMII and Bypass Register 17h RBR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RMII_ MODE RMII_ REV1_0 RX_OVF RX_UNF RX_RD_ _STS _STS PTR[1] RX_RD_ PTR[0] LED Direct Control Register 18h LEDCR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved DRV_SP DRV_LN DLED KLED DRV_AC SPDLED LNKLED TLED ACTLED PHY Control Register 19h PHYCR MDIX_E N FORCE_ PAUSE_ MDIX RX PAUSE_ TX BIST_fe PSR_15 BIST_ STATUS BIST_ START BP_ STRETCH LED_ CNFG[1] LED_ CNFG[0] PHY ADDR PHY ADDR PHY ADDR PHY ADDR PHY ADDR 10Base-T Status/ Control Register 1Ah 10BT_S ERIAL 10BT_S ERIAL REJECT ERROR 100 RANGE BASE T ERROR RANGE SQUELCH SQUELCH SQUELCH LOOPBA CK_10_ LP_DIS DIS FORC_ LINK_10 Reserved POLARI- ReTY served Reserved HEART_ DIS JABBER _DIS CD Test Control and BIST Extensions Register 1Bh CDCTRL 1 BIST_ BIST_ BIST_ BIST_ BIST_ BIST_ BIST_ BIST_ ReERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR served _COUNT _COUNT _COUNT _COUNT _COUNT _COUNT _COUNT _COUNT Reserved BIST_ CONT_ MODE CDPattE N_10 Reserved 10Meg_ Patt_ Gap CDPattSel CDPattSel Reserved 1Ch Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 56 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Detailed Description Reserved RXERCNT RXERCNT Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP DP83848-EP www.ti.com SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 Table 5-8. Register Table (continued) REGISTER NAME ADDRESS TAG BIT 15 BIT 14 BIT 13 Energy Detect Control Register 1Dh EDCR ED_EN ED_ AUTO_ UP ED_ AUTO_ DOWN ED_ MAN ED_ BURST_ DIS ED_ PWR_ STATE Reserved 1Eh-1Fh Reserved Reserved Reserved Reserved Reserved Reserved Reserved BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 3 BIT 2 BIT 1 BIT0 ED_ ED_ERR DATA_ _MET MET ED_ ED_ERR ED_ERR ED_ERR ED_ERR DATA_ _COUNT _COUNT _COUNT _COUNT COUNT ED_ DATA_ COUNT ED_ DATA_ COUNT ED_ DATA_ COUNT Reserved Reserved Reserved Reserved Reserved Reserved BIT 7 BIT 6 Reserved BIT 5 Reserved BIT 4 Reserved Reserved Detailed Description Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP 57 DP83848-EP SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 5.6.1 www.ti.com Register Definition In • • • • • • • • • 5.6.1.1 the register definitions under the ‘Default’ heading, the following definitions hold true: RW = Read Write access SC = Register sets on event occurrence and Self-Clears when event ends RW/SC = Read Write access/Self-Clearing bit RO = Read Only access COR = Clear on Read RO/COR = Read Only, Clear on Read RO/P = Read Only, Permanently set to a default value LL = Latched Low and held until read, based upon the occurrence of the corresponding event LH = Latched High and held until read, based upon the occurrence of the corresponding event Basic Mode Control Register (BMCR) Table 5-9. Basic Mode Control Register (BMCR), Address 0x00 BIT BIT NAME DEFAULT DESCRIPTION Reset: 1 = Initiate software Reset/Reset in Process. 15 Reset 0, RW/SC 0 = Normal operation. This bit, which is self-clearing, returns a value of one until the reset process is complete. The configuration is re-strapped. Loopback: 1 = Loopback enabled. 0 = Normal operation. 14 Loopback 0, RW The loopback function enables MII transmit data to be routed to the MII receive data path. Setting this bit may cause the descrambler to lose synchronization and produce a 500-µs dead time before any valid data will appear at the MII receive outputs. Speed Select: 13 Speed Selection Strap, RW When auto-negotiation is disabled writing to this bit allows the port speed to be selected. 1 = 100 Mbps. 0 = 10 Mbps. Auto-Negotiation Enable: Strap controls initial value at reset. 12 Auto-Negotiation Enable Strap, RW 1 = Auto-Negotiation Enabled - bits 8 and 13 of this register are ignored when this bit is set. 0 = Auto-Negotiation Disabled - bits 8 and 13 determine the port speed and duplex mode. Power Down: 1 = Power down. 11 Power Down 0, RW 0 = Normal operation. Setting this bit powers down the PHY. Only the register block is enabled during a power down condition. This bit is OR’d with the input from the PWR_DOWN/INT pin. When the active low PWR_DOWN/INT pin is asserted, this bit will be set. Isolate: 10 Isolate 0, RW 1 = Isolates the Port from the MII with the exception of the serial management. 0 = Normal operation. 58 Detailed Description Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP DP83848-EP www.ti.com SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 Table 5-9. Basic Mode Control Register (BMCR), Address 0x00 (continued) BIT BIT NAME DEFAULT DESCRIPTION Restart Auto-Negotiation: 9 Restart Auto-Negotiation 0, RW/SC 1 = Restart Auto-Negotiation. Re-initiates the Auto-Negotiation process. If Auto-Negotiation is disabled (bit 12 = 0), this bit is ignored. This bit is self-clearing and will return a value of 1 until Auto-Negotiation is initiated, whereupon it will self-clear. Operation of the Auto-Negotiation process is not affected by the management entity clearing this bit. 0 = Normal operation. Duplex Mode: 8 Duplex Mode Strap, RW When auto-negotiation is disabled writing to this bit allows the port Duplex capability to be selected. 1 = Full Duplex operation. 0 = Half Duplex operation. Collision Test: 1 = Collision test enabled. 7 Collision Test 0, RW 0 = Normal operation. When set, this bit will cause the COL signal to be asserted in response to the assertion of TX_EN within 512-bit times. The COL signal will be de-asserted within 4-bit times in response to the de-assertion of TX_EN. 6:00 5.6.1.2 RESERVED 0, RO RESERVED: Write ignored, read as 0. Basic Mode Status Register (BMSR) Table 5-10. Basic Mode Status Register (BMSR), Address 0x01 BIT BIT NAME DEFAULT 15 100BASE-T4 0, RO/P 14 100BASE-T Full Duplex 1, RO/P 13 100BASE-T Half Duplex 1, RO/P 12 10BASE-T Full Duplex 1, RO/P 11 10BASE-T Half Duplex 1, RO/P 10:07 RESERVED 0, RO DESCRIPTION 100BASE-T4 Capable: 0 = Device not able to perform 100BASE-T4 mode 100BASE-TX Full Duplex Capable: 1 = Device able to perform 100BASE-TX in full duplex mode 100BASE-TX Half Duplex Capable: 1 = Device able to perform 100BASE-TX in half duplex mode 10BASE-T Full Duplex Capable: 1 = Device able to perform 10BASE-T in full duplex mode 10BASE-T Half Duplex Capable: 1 = Device able to perform 10BASE-T in half duplex mode RESERVED: Write as 0, read as 0 Preamble suppression Capable: 6 MF Preamble Suppression 1, RO/P 1 = Device able to perform management transaction with preamble suppressed, 32-bits of preamble needed only once after reset, invalid opcode or invalid turnaround. 0 = Normal management operation Auto-Negotiation Complete: 5 Auto-Negotiation Com- plete 0, RO 1 = Auto-Negotiation process complete 0 = Auto-Negotiation process not complete Remote Fault: 4 Remote Fault 0, RO/LH 1 = Remote Fault condition detected (cleared on read or by reset). Fault criteria: Far End Fault Indication or notification from Link Partner of Remote Fault. 0 = No remote fault condition detected Auto Negotiation Ability: 3 Auto-Negotiation Ability 1, RO/P 1 = Device is able to perform Auto-Negotiation 0 = Device is not able to perform Auto-Negotiation Detailed Description Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP 59 DP83848-EP SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 www.ti.com Table 5-10. Basic Mode Status Register (BMSR), Address 0x01 (continued) BIT BIT NAME DEFAULT DESCRIPTION Link Status: 1 = Valid link established (for either 10 or 100 Mbps operation) 2 Link Status 0, RO/LL 0 = Link not established The criteria for link validity is implementation specific. The occurrence of a link failure condition will causes the Link Status bit to clear. Once cleared, this bit may only be set by establishing a good link condition and a read via the management interface. Jabber Detect: This bit only has meaning in 10 Mbps mode 1 = Jabber condition detected 1 Jabber Detect 0, RO/LH 0 = No Jabber This bit is implemented with a latching function, such that the occurrence of a jabber condition causes it to set until it is cleared by a read to this register by the management interface or by a reset. Extended Capability: 0 Extended Capability 1, RO/P 1 = Extended register capabilities 0 = Basic register set capabilities only 5.6.1.3 PHY Identifier Register #1 (PHYIDR1) The PHY Identifier Registers #1 and #2 together form a unique identifier for the DP83848-EP. The Identifier consists of a concatenation of the Organizationally Unique Identifier (OUI), the vendor's model number and the model revision number. A PHY may return a value of zero in each of the 32 bits of the PHY Identifier if desired. The PHY Identifier is intended to support network management. National's IEEE assigned OUI is 080017h. Table 5-11. PHY Identifier Register #1 (PHYIDR1), Address 0x02 BIT 15:0 5.6.1.4 BIT NAME OUI_MSB DEFAULT DESCRIPTION , RO/P OUI Most Significant Bits: Bits 3 to 18 of the OUI (080017h) are stored in bits 15 to 0 of this register. The most significant two bits of the OUI are ignored (the IEEE standard refers to these as bits 1 and 2). PHY Identifier Register #2 (PHYIDR2) Table 5-12. PHY Identifier Register #2 (PHYIDR2), Address 0x03 BIT BIT NAME DEFAULT DESCRIPTION OUI Least Significant Bits: 15:10 OUI_LSB , RO/P 9:4 VNDR_MDL , RO/P Bits 19 to 24 of the OUI (080017h) are mapped from bits 15 to 10 of this register respectively. Vendor Model Number: The six bits of vendor model number are mapped from bits 9 to 4 (most significant bit to bit 9). Model Revision Number: 3:0 60 MDL_REV , RO/P Four bits of the vendor model revision number are mapped from bits 3 to 0 (most significant bit to bit 3). This field will be incremented for all major device changes. Detailed Description Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP DP83848-EP www.ti.com 5.6.1.5 SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 Auto-Negotiation Advertisement Register (ANAR) This register contains the advertised abilities of this device as they will be transmitted to its link partner during Auto-Negotiation. Table 5-13. Negotiation Advertisement Register (ANAR), Address 0x04 BIT BIT NAME DEFAULT DESCRIPTION Next Page Indication: 15 NP 0, RW 0 = Next Page Transfer not desired 1 = Next Page Transfer desired 14 RESERVED 0, RO/P 13 RF 0, RW 12 RESERVED 0, RW RESERVED by IEEE: Writes ignored, Read as 0 Remote Fault: 1 = Advertises that this device has detected a Remote Fault 0 = No Remote Fault detected RESERVED for Future IEEE use: Write as 0, Read as 0 Asymmetric PAUSE Support for Full Duplex Links: The ASM_DIR bit indicates that asymmetric PAUSE is supported. 11 ASM_DIR 0, RW Encoding and resolution of PAUSE bits is defined in IEEE 802.3 Annex 28B, Tables 28B-2 and 28B-3, respectively. Pause resolution status is reported in PHYCR[13:12]. 1 = Advertise that the DTE (MAC) has implemented both the optional MAC control sublayer and the pause function as specified in clause 31 and annex 31B of 802.3u. 0 = No MAC based full duplex flow control PAUSE Support for Full Duplex Links: The PAUSE bit indicates that the device is capable of providing the symmetric PAUSE functions as defined in Annex 31B. 10 PAUSE 0, RW Encoding and resolution of PAUSE bits is defined in IEEE 802.3 Annex 28B, Tables 28B-2 and 28B-3, respectively. Pause resolution status is reported in PHYCR[13:12]. 1 = Advertise that the DTE (MAC) has implemented both the optional MAC control sublayer and the pause function as specified in clause 31 and annex 31B of 802.3u. 0= No MAC based full duplex flow control 100BASE-T4 Support: 9 T4 0, RO/P 1 = 100BASE-T4 is supported by the local device 0 = 100BASE-T4 not supported 100BASE-TX Full Duplex Support: 8 TX_FD Strap, RW 1 = 100BASE-TX Full Duplex is supported by the local device 0 = 100BASE-TX Full Duplex not supported 100BASE-TX Support: 7 TX Strap, RW 1 = 100BASE-TX is supported by the local device 0 = 100BASE-TX not supported 10BASE-T Full Duplex Support: 6 10_FD Strap, RW 1 = 10BASE-T Full Duplex is supported by the local device 0 = 10BASE-T Full Duplex not supported 10BASE-T Support: 5 10 Strap, RW 1 = 10BASE-T is supported by the local device 0 = 10BASE-T not supported Protocol Selection Bits: 4:0 Selector , RW These bits contain the binary encoded protocol selector supported by this port. indicates that this device supports IEEE 802.3u. Detailed Description Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP 61 DP83848-EP SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 5.6.1.6 www.ti.com Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page) This register contains the advertised abilities of the link partner as received during auto-negotiation. The content changes after the successful auto-negotiation if next-pages are supported. Table 5-14. Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page), Address 0x05 BIT BIT NAME DEFAULT DESCRIPTION Next Page Indication: 15 NP 0, RO 0 = Link Partner does not desire Next Page Transfer 1 = Link Partner desires Next Page Transfer Acknowledge: 1 = Link Partner acknowledges reception of the ability data word 14 ACK 0, RO 0 = Not acknowledged The Auto-Negotiation state machine will automatically control the this bit based on the incoming FLP bursts. Remote Fault: 13 RF 0, RO 12 RESERVED 0, RO 1 = Remote Fault indicated by Link Partner 0 = No Remote Fault indicated by Link Partner RESERVED for Future IEEE use: Write as 0, read as 0 ASYMMETRIC PAUSE: 11 ASM_DIR 0, RO 1 = Asymmetric pause is supported by the Link Partner 0 = Asymmetric pause is not supported by the Link Partner PAUSE: 10 PAUSE 0, RO 1 = Pause function is supported by the Link Partner 0 = Pause function is not supported by the Link Partner 100BASE-T4 Support: 9 T4 0, RO 1 = 100BASE-T4 is supported by the Link Partner 0 = 100BASE-T4 not supported by the Link Partner 100BASE-TX Full Duplex Support: 8 TX_FD 0, RO 1 = 100BASE-TX Full Duplex is supported by the Link Partner 0 = 100BASE-TX Full Duplex not supported by the Link Partner 100BASE-TX Support: 7 TX 0, RO 1 = 100BASE-TX is supported by the Link Partner 0 = 100BASE-TX not supported by the Link Partner 10BASE-T Full Duplex Support: 6 10_FD 0, RO 1 = 10BASE-T Full Duplex is supported by the Link Partner 0 = 10BASE-T Full Duplex not supported by the Link Partner 10BASE-T Support: 5 10 0, RO 1 = 10BASE-T is supported by the Link Partner 0 = 10BASE-T not supported by the Link Partner 4:0 5.6.1.7 Selector , RO Protocol Selection Bits: Link Partner’s binary encoded protocol selector Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page) Table 5-15. Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page), Address 0x05 BIT BIT NAME DEFAULT 15 NP 0, RO DESCRIPTION Next Page Indication: 1 = Link Partner desires Next Page Transfer 0 = Link Partner does not desire Next Page Transfer 62 Detailed Description Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP DP83848-EP www.ti.com SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 Table 5-15. Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page), Address 0x05 (continued) BIT BIT NAME DEFAULT DESCRIPTION Acknowledge: 1 = Link Partner acknowledges reception of the ability data word 14 ACK 0, RO 0 = Not acknowledged The Auto-Negotiation state machine will automatically control the this bit based on the incoming FLP bursts. Software should not attempt to write to this bit. Message Page: 13 MP 0, RO 1 = Message Page 0 = Unformatted Page Acknowledge 2: 12 ACK2 0, RO 1 = Link Partner does have the ability to comply to next page message 0 = Link Partner does not have the ability to comply to next page message Toggle: 11 Toggle 0, RO 1 = Previous value of the transmitted Link Code word equalled 0 0 = Previous value of the transmitted Link Code word equalled 1 Code: 10:0 5.6.1.8 CODE , RO This field represents the code field of the next page transmission. If the MP bit is set (bit 13 of this register), then the code shall be interpreted as a “Message Page,” as defined in annex 28C of Clause 28. Otherwise, the code shall be interpreted as an “Unformatted Page,” and the interpretation is application specific. Auto-Negotiate Expansion Register (ANER) This register contains additional local device and link partner status information. Table 5-16. Auto-Negotiate Expansion Register (ANER), Address 0x06 BIT BIT NAME DEFAULT 15:5 RESERVED 0, RO 4 PDF 0, RO DESCRIPTION RESERVED: Writes ignored, Read as 0 Parallel Detection Fault: 1 = A fault has been detected via the Parallel Detection function 0 = A fault has not been detected Link Partner Next Page Able: 3 LP_NP_ABLE 0, RO 1 = Link Partner does support Next Page 0 = Link Partner does not support Next Page 2 NP_ABLE 1, RO/P Next Page Able: 1 = Indicates local device is able to send additional “Next Pages” Link Code Word Page Received: 1 PAGE_RX 0, RO/COR 1 = Link Code Word has been received, cleared on a read 0 = Link Code Word has not been received Link Partner Auto-Negotiation Able: 0 LP_AN_ABLE 0, RO 1 = indicates that the Link Partner supports Auto-Negotiation 0 = indicates that the Link Partner does not support Auto-Negotiation Detailed Description Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP 63 DP83848-EP SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 5.6.1.9 www.ti.com Auto-Negotiation Next Page Transmit Register (ANNPTR) This register contains the next page information sent by this device to its link partner during autonegotiation. Table 5-17. Auto-Negotiation Next Page Transmit Register (ANNPTR), Address 0x07 BIT BIT NAME DEFAULT DESCRIPTION Next Page Indication: 15 NP 0, RW 0 = No other Next Page Transfer desired 1 = Another Next Page desired 14 RESERVED 0, RO 13 MP 1, RW RESERVED: Writes ignored, read as 0 Message Page: 1 = Message Page 0 = Unformatted Page Acknowledge2: 1 = Will comply with message 12 ACK2 0, RW 0 = Cannot comply with message Acknowledge2 is used by the next page function to indicate that Local Device has the ability to comply with the message received. Toggle: 1 = Value of toggle bit in previously transmitted Link Code Word was 0 11 10:0 TOG_TX CODE 0, RO , RW 0 = Value of toggle bit in previously transmitted Link Code Word was 1 Toggle is used by the Arbitration function within Auto-Negotiation to ensure synchronization with the Link Partner during Next Page exchange. This bit shall always take the opposite value of the Toggle bit in the previously exchanged Link Code Word. This field represents the code field of the next page transmission. If the MP bit is set (bit 13 of this register), then the code shall be interpreted as a "Message Page”, as defined in annex 28C of IEEE 802.3u. Otherwise, the code shall be interpreted as an "Unformatted Page”, and the interpretation is application specific. The default value of the CODE represents a Null Page as defined in Annex 28C of IEEE 802.3u. 64 Detailed Description Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP DP83848-EP www.ti.com 5.6.2 SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 Extended Registers 5.6.2.1 PHY Status Register (PHYSTS) This register provides a single location within the register set for quick access to commonly accessed information. Table 5-18. PHY Status Register (PHYSTS), Address 0x10 BIT BIT NAME DEFAULT 15 RESERVED 0, RO DESCRIPTION RESERVED: Write ignored, read as 0 MDI-X mode as reported by the Auto-Negotiation logic: 14 MDI-X Mode 0, RO This bit will be affected by the settings of the MDIX_EN and FORCE_MDIX bits in the PHYCR register. When MDIX is enabled, but not forced, this bit will update dynamically as the Auto-MDIX algorithm swaps between MDI and MDI-X configurations. 1 = MDI pairs swapped (Receive on TPTD pair, Transmit on TPRD pair) 0 = MDI pairs normal (Receive on TRD pair, Transmit on TPTD pair) Receive Error Latch: This bit will be cleared upon a read of the RECR register. 13 Receive Error Latch 0, RO/LH 1 = Receive error event has occurred since last read of RXERCNT (address 0x15, Page 0) 0 = No receive error event has occurred Polarity Status: 12 Polarity Status 0, RO This bit is a duplication of bit 4 in the 10BTSCR register. This bit will be cleared upon a read of the 10BTSCR register, but not upon a read of the PHYSTS register. 1 = Inverted Polarity detected 0 = Correct Polarity detected False Carrier Sense Latch: This bit will be cleared upon a read of the FCSR register. 11 False Carrier Sense Latch 0, RO/LH 10 Signal Detect 0, RO/LL 100Base-TX unconditional Signal Detect from PMD 9 Descrambler Lock 0, RO/LL 100Base-TX Descrambler Lock from PMD 1 = False Carrier event has occurred since last read of FCSCR (address 0x14) 0 = No False Carrier event has occurred Link Code Word Page Received: 8 Page Received 0, RO This is a duplicate of the Page Received bit in the ANER register, but this bit will not be cleared upon a read of the PHYSTS register. 1 = A new Link Code Word Page has been received. Cleared on read of the ANER (address 0x06, bit 1) 0 = Link Code Word Page has not been received MII Interrupt Pending: 7 MII Interrupt 0, RO 1 = Indicates that an internal interrupt is pending. Interrupt source can be determined by reading the MISR Register (0x12h). Reading the MISR will clear the Interrupt. 0= No interrupt pending Remote Fault: 6 Remote Fault 0, RO 1 = Remote Fault condition detected (cleared on read of BMSR (address 01h) register or by reset). Fault criteria: notification from Link Partner of Remote Fault via Auto-Negotiation. 0 = No remote fault condition detected Detailed Description Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP 65 DP83848-EP SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 www.ti.com Table 5-18. PHY Status Register (PHYSTS), Address 0x10 (continued) BIT BIT NAME DEFAULT DESCRIPTION Jabber Detect: This bit only has meaning in 10 Mbps mode 5 Jabber Detect 0, RO This bit is a duplicate of the Jabber Detect bit in the BMSR register, except that it is not cleared upon a read of the PHYSTS register. 1 = Jabber condition detected 0 = No Jabber Auto-Negotiation Complete: 4 Auto-Neg Complete 0, RO 1 = Auto-Negotiation complete 0 = Auto-Negotiation not complete Loopback: 3 Loopback Status 0, RO 1 = Loopback enabled 0 = Normal operation Duplex: This bit indicates duplex status and is determined from AutoNegotiation or Forced Modes. 2 Duplex Status 0, RO 1 = Full duplex mode 0 = Half duplex mode Note: This bit is only valid if Auto-Negotiation is enabled and complete and there is a valid link or if Auto-Negotiation is disabled and there is a valid link. Speed10: This bit indicates the status of the speed and is determined from AutoNegotiation or Forced Modes. 1 Speed Status 0, RO 1 = 10 Mbps mode 0 = 100 Mbps mode Note: This bit is only valid if Auto-Negotiation is enabled and complete and there is a valid link or if Auto-Negotiation is disabled and there is a valid link. Link Status: 0 Link Status 0, RO This bit is a duplicate of the Link Status bit in the BMSR register, except that it will not be cleared upon a read of the PHYSTS register. 1 = Valid link established (for either 10 or 100 Mbps operation) 0 = Link not established 5.6.2.2 MII Interrupt Control Register (MICR) This register implements the MII interrupt PHY specific control register. Sources for interrupt generation include: energy detect state change, link state change, speed status change, duplex status change, autonegotiation complete or any of the counters becoming half-full. The individual interrupt events must be enabled by setting bits in the MII interrupt status and event control register (MISR). Table 5-19. MII Interrupt Control Register (MICR), Address 0x11 BIT BIT NAME DEFAULT 15:3 RESERVED 0, RO DESCRIPTION Reserved: Write ignored, Read as 0 Test Interrupt: 2 TINT 0, RW Forces the PHY to generate an interrupt to facilitate interrupt testing. Interrupts will continue to be generated as long as this bit remains set. 1 = Generate an interrupt 0 = Do not generate interrupt 66 Detailed Description Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP DP83848-EP www.ti.com SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 Table 5-19. MII Interrupt Control Register (MICR), Address 0x11 (continued) BIT BIT NAME DEFAULT DESCRIPTION Interrupt Enable: 1 INTEN 0, RW Enable interrupt dependent on the event enables in the MISR register. 1 = Enable event based interrupts 0 = Disable event based interrupts Interrupt Output Enable: 0 INT_OE 0, RW Enable interrupt events to signal via the PWR_DOWN/INT pin by configuring the PWR_DOWN/INT pin as an output. 1 = PWR_DOWN/INT is an Interrupt Output 0 = PWR_DOWN/INT is a Power Down Input 5.6.2.3 MII Interrupt Status and Miscellaneous Control Register (MISR) This register contains event status and enables for the interrupt function. If an event has occurred since the last read of this register, the corresponding status bit will be set. If the corresponding enable bit in the register is set, an interrupt will be generated if the event occurs. The MICR register controls must also be set to allow interrupts. The status indications in this register will be set even if the interrupt is not enabled. Table 5-20. MII Interrupt Status and Miscellaneous Control Register (MISR), Address 0x12 BIT BIT NAME DEFAULT 15 RESERVED 0, RO DESCRIPTION RESERVED: Writes ignored, Read as 0 Energy Detect interrupt: 14 ED_INT 0, RO/COR 1 = Energy detect interrupt is pending and is cleared by the current read 0 = No energy detect interrupt pending Change of Link Status interrupt: 13 LINK_INT 0, RO/COR 1 = Change of link status interrupt is pending and is cleared by the current read 0 = No change of link status interrupt pending Change of speed status interrupt: 12 SPD_INT 0, RO/COR 1 = Speed status change interrupt is pending and is cleared by the current read 0 = No speed status change interrupt pending Change of duplex status interrupt: 11 DUP_INT 0, RO/COR 1 = Duplex status change interrupt is pending and is cleared by the current read 0 = No duplex status change interrupt pending Auto-Negotiation Complete interrupt: 10 ANC_INT 0, RO/COR 1 = Auto-negotiation complete interrupt is pending and is cleared by the current read 0 = No Auto-negotiation complete interrupt pending False Carrier Counter half-full interrupt: 9 FHF_INT 0, RO/COR 1 = False carrier counter half-full interrupt is pending and is cleared by the current read 0 = No false carrier counter half-full interrupt pending Receive Error Counter half-full interrupt: 1 = Receive error counter half-full interrupt is pending and is cleared by the current read 8 RHF_INT 0, RO/COR 7 RESERVED 0, RO RESERVED: Writes ignored, Read as 0 6 ED_INT_EN 0, RW Enable Interrupt on energy detect event 5 LINK_INT_EN 0, RW Enable Interrupt on change of link status 0 = No receive error carrier counter half-full interrupt pending Detailed Description Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP 67 DP83848-EP SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 www.ti.com Table 5-20. MII Interrupt Status and Miscellaneous Control Register (MISR), Address 0x12 (continued) BIT BIT NAME DEFAULT 4 SPD_INT_EN 0, RW Enable Interrupt on change of speed status 3 DUP_INT_EN 0, RW Enable Interrupt on change of duplex status 2 ANC_INT_EN 0, RW Enable Interrupt on Auto-negotiation complete event 1 FHF_INT_EN 0, RW Enable Interrupt on False Carrier Counter Register half-full event 0 RHF_INT_EN 0, RW Enable Interrupt on Receive Error Counter Register half-full event 5.6.2.4 DESCRIPTION False Carrier Sense Counter Register (FCSCR) This counter provides information required to implement the “False Carriers” attribute within the MAU managed object class of Clause 30 of the IEEE 802.3u specification. Table 5-21. False Carrier Sense Counter Register (FCSCR), Address 0x14 BIT BIT NAME DEFAULT 15:8 RESERVED 0, RO 7:0 FCSCNT[7:0] 0, RO/COR DESCRIPTION RESERVED: Writes ignored, Read as 0 False Carrier Event Counter: 5.6.2.5 This 8-bit counter increments on every false carrier event. This counter sticks when it reaches its max count (FFh). Receiver Error Counter Register (RECR) This counter provides information required to implement the “Symbol Error During Carrier” attribute within the PHY managed object class of Clause 30 of the IEEE 802.3u specification. Table 5-22. Receiver Error Counter Register (RECR), Address 0x15 BIT BIT NAME DEFAULT 15:8 RESERVED 0, RO DESCRIPTION RESERVED: Writes ignored, Read as 0 RX_ER Counter: 7:0 5.6.2.6 RXERCNT[7:0] 0, RO/COR When a valid carrier is present and there is at least one occurrence of an invalid data symbol, this 8-bit counter increments for each receive error detected. This event can increment only once per valid carrier event. If a collision is present, the attribute will not increment. The counter sticks when it reaches its max count. 100 Mbps PCS Configuration and Status Register (PCSR) This register contains event status and enables for the interrupt function. If an event has occurred since the last read of this register, the corresponding status bit will be set. If the corresponding enable bit in the register is set, an interrupt will be generated if the event occurs. The MICR register controls must also be set to allow interrupts. The status indications in this register will be set even if the interrupt is not enabled. Table 5-23. 100 Mbps PCS Configuration and Status Register (PCSR), Address 0x16 BIT BIT NAME DEFAULT DESCRIPTION 15:13 RESERVED , RO 12 RESERVED 0 RESERVED: Must be zero 11 RESERVED 0 RESERVED: Must be zero 10 TQ_EN 0, RW RESERVED: Writes ignored, Read as 0 100Mbs True Quiet Mode Enable: 1 = Transmit True Quiet Mode 0 = Normal Transmit Mode Signal Detect Force PMA: 9 SD FORCE PMA 0, RW 1 = Forces Signal Detection in PMA 0 = Normal SD operation 68 Detailed Description Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP DP83848-EP www.ti.com SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 Table 5-23. 100 Mbps PCS Configuration and Status Register (PCSR), Address 0x16 (continued) BIT BIT NAME DEFAULT DESCRIPTION Signal Detect Option: 8 SD_OPTION 1, RW 1 = Enhanced signal detect algorithm 0 = Reduced signal detect algorithm Descrambler Timeout: 7 DESC_TIME 0, RW Increase the descrambler timeout. When set this should allow the device to receive larger packets (>9k bytes) without loss of synchronization. 1 = 2 ms 0 = 722 µs (per ANSI X3.263: 1995 (TP-PMD) 7.2.3.3e) 6 RESERVED 0 RESERVED: Must be zero Force 100Mbps Good Link: 5 FORCE_100_OK 0, RW 1 = Forces 100Mbps Good Link 4 RESERVED 0 RESERVED: Must be zero 3 RESERVED 0 RESERVED: Must be zero 2 NRZI_BYPASS 0, RW 0 = Normal 100Mbps operation NRZI Bypass Enable: 1 = NRZI Bypass Enabled 0 = NRZI Bypass Disabled 1 RESERVED 0 RESERVED: Must be zero 0 RESERVED 0 RESERVED: Must be zero 5.6.2.7 RMII and Bypass Register (RBR) This register configures the RMII Mode of operation. When RMII mode is disabled, the RMII functionality is bypassed. Table 5-24. RMII and Bypass Register (RBR), Addresses 0x17 BIT BIT NAME DEFAULT 15:6 RESERVED 0, RO 5 RMII_MODE Strap, RW DESCRIPTION Reserved: Writes ignored, Read as 0 Reduced MII Mode: 0 = Standard MII Mode 1 = Reduced MII Mode Reduce MII Revision 1.0: 4 RMII_REV1_0 0, RW 0 = (RMII revision 1.2) CRS_DV will toggle at the end of a packet to indicate deassertion of CRS. 1 = (RMII revision 1.0) CRS_DV will remain asserted until final data is transferred. CRS_DV will not toggle at the end of a packet. RX FIFO Over Flow Status: 3 RX_OVF_STS 0, RO 0 = Normal 1 = Overflow detected RX FIFO Under Flow Status: 2 RX_UNF_STS 0, RO 0 = Normal 1 = Underflow detected Detailed Description Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP 69 DP83848-EP SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 www.ti.com Table 5-24. RMII and Bypass Register (RBR), Addresses 0x17 (continued) BIT BIT NAME DEFAULT DESCRIPTION Receive Elasticity Buffer: 1:0 ELAST_BUF[1:0] 01, RW This field controls the Receive Elasticity Buffer which allows for frequency variation tolerance between the 50MHz RMII clock and the recovered data. The following values indicate the tolerance in bits for a single packet. The minimum setting allows for standard Ethernet frame sizes at ±50ppm accuracy for both RMII and Receive clocks. For greater frequency tolerance the packet lengths may be scaled (i.e. for ±100ppm, the packet lengths need to be divided by 2). 00 = 14 bit tolerance (up to 16800 byte packets) 01 = 2 bit tolerance (up to 2400 byte packets) 10 = 6 bit tolerance (up to 7200 byte packets) 11 = 10 bit tolerance (up to 12000 byte packets) 5.6.2.8 LED Direct Control Register (LEDCR) This register provides the ability to directly control any or all LED outputs. It does not provide read access to LEDs. Table 5-25. LED Direct Control Register (LEDCR), Address 0x18 BIT BIT NAME DEFAULT 15:6 RESERVED 0, RO 5 DRV_SPDLED 0, RW 4 DRV_LNKLED 0, RW 3 DRV_ACTLED 0, RW 2 SPDLED 0, RW Value to force on LED_SPD output 1 LNKLED 0, RW Value to force on LED_LNK output 0 ACTLED 0, RW Value to force on LED_ACT/COL output 5.6.2.9 DESCRIPTION Reserved: Writes ignored, Read as 0 1 = Drive value of SPDLED bit onto LED_SPD output 0 = Normal operation 1 = Drive value of LNKLED bit onto LED_LNK output 0 = Normal operation 1 = Drive value of ACTLED bit onto LED_ACT/COL output 0 = Normal operation PHY Control Register (PHYCR) Table 5-26. PHY Control Register (PHYCR), Address 0x19 BIT BIT NAME DEFAULT DESCRIPTION Auto-MDIX Enable: 1 = Enable Auto-neg Auto-MDIX capability 15 MDIX_EN Strap, RW 0 = Disable Auto-neg Auto-MDIX capability The Auto-MDIX algorithm requires that the Auto-Negotiation Enable bit in the BMCR register to be set. If Auto-Negotiation is not enabled, AutoMDIX should be disabled as well. Force MDIX: 14 FORCE_MDIX 0, RW 1 = Force MDI pairs to cross (Receive on TPTD pair, Transmit on TPRD pair) 0 = Normal operation Pause Receive Negotiated: 13 PAUSE_RX 0, RO Indicates that pause receive should be enabled in the MAC. Based on ANAR[11:10] and ANLPAR[11:10] settings. This function shall be enabled according to IEEE 802.3 Annex 28B Table 28B-3, “Pause Resolution”, only if the Auto-Negotiated Highest Common Denominator is a full duplex technology. 70 Detailed Description Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP DP83848-EP www.ti.com SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 Table 5-26. PHY Control Register (PHYCR), Address 0x19 (continued) BIT BIT NAME DEFAULT DESCRIPTION Pause Transmit Negotiated: 12 PAUSE_TX 0, RO Indicates that pause transmit should be enabled in the MAC. Based on ANAR[11:10] and ANLPAR[11:10] settings. This function shall be enabled according to IEEE 802.3 Annex 28B Table 28B-3, “Pause Resolution”, only if the Auto-Negotiated Highest Common Denominator is a full duplex technology. BIST Force Error: 11 BIST_FE 0, RW/SC 1 = Force BIST Error 0 = Normal operation This bit forces a single error, and is self clearing BIST Sequence select: 10 PSR_15 0, RW 1 = PSR15 selected 0 = PSR9 selected BIST Test Status: 1 = BIST pass 9 BIST_STATUS 0, LL/RO 0 = BIST fail. Latched, cleared when BIST is stopped For a count number of BIST errors, see the BIST Error Count in the CDCTRL1 register. BIST Start: 8 BIST_START 0, RW 1 = BIST start 0 = BIST stop Bypass LED Stretching: 7 BP_STRETCH 0, RW This will bypass the LED stretching and the LEDs will reflect the internal value. 1 = Bypass LED stretching 0 = Normal operation 6 LED_CNFG[1] 0, RW 5 LED_CNFG[0] Strap, RW LEDs Configuration: LED_CNFG [1] LED_ CNFG[0] Mode Description Don’t care 1 Mode 1 0 0 Mode 2 1 0 Mode 3 In Mode 1, LEDs are configured as follows: LED_LINK = ON for Good Link, OFF for No Link LED_SPEED = ON in 100 Mbps, OFF in 10 Mbps LED_ACT/COL = ON for Activity, OFF for No Activity In Mode 2, LEDs are configured as follows: LED_LINK = ON for good Link, BLINK for Activity LED_SPEED = ON in 100 Mbps, OFF in 10 Mbps LED_ACT/COL = ON for Collision, OFF for No Collision Full Duplex, OFF for Half Duplex In Mode 3, LEDs are configured as follows: LED_LINK = ON for Good Link, BLINK for Activity LED_SPEED = ON in 100 Mbps, OFF in 10 Mbps LED_ACT/COL = ON for Full Duplex, OFF for Half Duplex 4:0 PHYADDR[4:0] Strap, RW PHY Address: PHY address for port Detailed Description Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP 71 DP83848-EP SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 www.ti.com 5.6.2.10 10Base-T Status/Control Register (10BTSCR) Table 5-27. 10Base-T Status/Control Register (10BTSCR), Address 0x1A BIT BIT NAME DEFAULT DESCRIPTION 10Base-T Serial Mode (SNI): 1 = Enables 10Base-T Serial Mode 15 10BT_SERIAL Strap, RW 0 = Normal Operation Places 10 Mbps transmit and receive functions in Serial Network Interface (SNI) Mode of operation. Has no effect on 100 Mbps operation. 14:12 RESERVED 0, RW RESERVED: Must be zero Squelch Configuration: 11:9 SQUELCH 100, RW Used to set the Squelch ‘ON’ threshold for the receiver Default Squelch ON is 330mV peak 8 LOOPBACK_10_D IS 0, RW In half-duplex mode, default 10BASE-T operation loops Transmit data to the Receive data in addition to transmitting the data on the physical medium. This is for consistency with earlier 10BASE2 and 10BASE5 implementations which used a shared medium. Setting this bit disables the loopback function. This bit does not affect loopback due to setting BMCR[14]. Normal Link Pulse Disable: 7 LP_DIS 0, RW 1 = Transmission of NLPs is disabled 0 = Transmission of NLPs is enabled Force 10Mb Good Link: 6 FORCE_LINK_10 0, RW 1 = Forced Good 10Mb Link 0 = Normal Link Status 5 RESERVED 0, RW RESERVED: Must be zero 10Mb Polarity Status: 4 POLARITY RO/LH This bit is a duplication of bit 12 in the PHYSTS register. Both bits will be cleared upon a read of 10BTSCR register, but not upon a read of the PHYSTS register. 1 = Inverted Polarity detected 0 = Correct Polarity detected 3 RESERVED 0, RW RESERVED: Must be zero 2 RESERVED 1, RW RESERVED: Must be zero Heartbeat Disable: This bit only has influence in half-duplex 10Mb mode. 1 HEARTBEAT_DIS 0, RW 1 = Heartbeat function disabled 0 = Heartbeat function enabled When the device is operating at 100Mb or configured for full duplex operation, this bit will be ignored - the heartbeat function is disabled. Jabber Disable: 0 JABBER_DIS 0, RW Applicable only in 10BASE-T. 1 = Jabber function disabled 0 = Jabber function enabled 72 Detailed Description Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP DP83848-EP www.ti.com SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 5.6.2.11 CD Test and BIST Extensions Register (CDCTRL1) Table 5-28. CD Test and BIST Extensions Register (CDCTRL1), Address 0x1B BIT BIT NAME DEFAULT DESCRIPTION BIST ERROR Counter: 15:8 BIST_ERROR_CO UNT 0, RO Counts number of errored data nibbles during Packet BIST. This value will reset when Packet BIST is restarted. The counter sticks when it reaches its max count. 7:6 RESERVED 0, RW RESERVED: Must be zero Packet BIST Continuous Mode: 5 BIST_CONT_MOD E 0, RW Allows continuous pseudo random data transmission without any break in transmission. This can be used for transmit VOD testing. This is used in conjunction with the BIST controls in the PHYCR Register (0x19h). For 10Mb operation, jabber function must be disabled, bit 0 of the 10BTSCR (0x1Ah), JABBER_DIS = 1. CD Pattern Enable for 10Mb: 4 CDPATTEN_10 0, RW 3 RESERVED 0, RW 2 10MEG_PATT_GA P 0, RW 1 = Enabled 0 = Disabled RESERVED: Must be zero Defines gap between data or NLP test sequences: 1 = 15 µs 0 = 10 µs CD Pattern Select[1:0]: If CDPATTEN_10 = 1: 00 = Data, EOP0 sequence 1:0 CDPATTSEL[1:0] 00, RW 01 = Data, EOP1 sequence 10 = NLPs 11 = Constant Manchester 1s (10MHz sine wave) for harmonic distortion testing 5.6.2.12 Energy Detect Control (EDCR) Table 5-29. Energy Detect Control (EDCR), Address 0x1D BIT BIT NAME DEFAULT DESCRIPTION Energy Detect Enable: Allow Energy Detect Mode. 15 ED_EN 0, RW When Energy Detect is enabled and Auto-Negotiation is disabled via the BMCR register, Auto-MDIX should be disabled via the PHYCR register. Energy Detect Automatic Power Up: 14 ED_AUTO_UP 1, RW Automatically begin power up sequence when Energy Detect Data Threshold value (EDCR[3:0]) is reached. Alternatively, device could be powered up manually using the ED_MAN bit (ECDR[12]). Energy Detect Automatic Power Down: 13 ED_AUTO_DOWN 1, RW Automatically begin power down sequence when no energy is detected. Alternatively, device could be powered down using the ED_MAN bit (EDCR[12]). Energy Detect Manual Power Up/Down: 12 ED_MAN 0, RW/SC Begin power up/down sequence when this bit is asserted. When set, the Energy Detect algorithm will initiate a change of Energy Detect state regardless of threshold (error or data) and timer values. In managed applications, this bit can be set after clearing the Energy Detect interrupt to control the timing of changing the power state. Detailed Description Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP 73 DP83848-EP SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 www.ti.com Table 5-29. Energy Detect Control (EDCR), Address 0x1D (continued) BIT BIT NAME DEFAULT DESCRIPTION Energy Detect Bust Disable: 11 ED_BURST_DIS 0, RW Disable bursting of energy detect data pulses. By default, Energy Detect (ED) transmits a burst of 4 ED data pulses each time the CD is powered up. When bursting is disabled, only a single ED data pulse will be send each time the CD is powered up. Energy Detect Power State: 10 ED_PWR_STATE 0, RO 9 ED_ERR_MET 0, RO/COR 8 ED_DATA_MET 0, RO/COR Indicates current Energy Detect Power state. When set, Energy Detect is in the powered up state. When cleared, Energy Detect is in the powered down state. This bit is invalid when Energy Detect is not enabled. Energy Detect Error Threshold Met: No action is automatically taken upon receipt of error events. This bit is informational only and would be cleared on a read. Energy Detect Data Threshold Met: The number of data events that occurred met or surpassed the Energy Detect Data Threshold. This bit is cleared on a read. Energy Detect Error Threshold: 7:4 ED_ERR_COUNT 0001, RW Threshold to determine the number of energy detect error events that should cause the device to take action. Intended to allow averaging of noise that may be on the line. Counter will reset after approximately 2 seconds without any energy detect data events. Energy Detect Data Threshold: 3:0 74 ED_DATA_COUNT 0001, RW Threshold to determine the number of energy detect events that should cause the device to take actions. Intended to allow averaging of noise that may be on the line. Counter will reset after approximately 2 seconds without any energy detect data events. Detailed Description Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP DP83848-EP www.ti.com SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 6 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 6.1 Application Information The device is a physical layer Ethernet transceiver. Typical operating voltage is 3.3 V with typical power consumption less than 270 mW. When using the device for Ethernet application, it is necessary to meet certain requirements for normal operation of device. Following typical application and design requirements can be used for selecting appropriate component values for DP83848-EP. MII/RMII/SNI DP83848 10/100 MB/S 25-MHZ Clock Source RJ-45 MPU/CPU Magnetics Typical Application Media Access Controller 6.2 10Base-T or 100Base-T Status LEDs Typical Application Figure 6-1. Typical Application 6.2.1 Design Requirements The design requirements for DP83848-EP are: • Vin = 3.3 V • Vout = Vcc – 0.5 V • Clock input = 25 MHz for MII and 50 MHz for RMII 6.2.1.1 TPI Network Circuit Figure 6-2 shows the recommended circuit for a 10/100 Mbps twisted pair interface. It is important that the user realize that variations with PCB and component characteristics requires that the application be tested to ensure that the circuit meets the requirements of the intended application. Application and Implementation Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP 75 DP83848-EP SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 www.ti.com Vdd RD– Common mode chokes may be required. Vdd 49.9Ω 0.1µF 1:1 49.9Ω RD+ RD- 0.1μF* RD+ TD- TD– 49.9Ω RJ45 1:1 0.1µF T1 NOTE: Center tap is pulled to VDD. 49.9Ω *Place capacitors close to the transformer center taps. TD+ Place resistors and capacitors close to the device. TD+ 0.1μF* Vdd All values are typical and are +/- 1% Figure 6-2. 10/100 Mbps Twisted Pair Interface 6.2.1.2 Clock IN (X1) Requirements The DP83848-EP supports an external CMOS level oscillator source or a crystal resonator device. Oscillator If an external clock source is used, X1 should be tied to the clock source and X2 should be left floating. Specifications for CMOS oscillators: 25 MHz in MII Mode and 50 MHz in RMII Mode are listed in Table 6-1 and Table 6-2. Crystal A 25-MHz, parallel, 20-pF load crystal resonator should be used if a crystal source is desired. Figure 6-4 shows a typical connection for a crystal resonator circuit. The load capacitor values will vary with the crystal vendors; check with the vendor for the recommended loads. The oscillator circuit is designed to drive a parallel resonance AT cut crystal with a minimum drive level of 100 mW and a maximum of 500 µW. If a crystal is specified for a lower drive level, a current limiting resistor should be placed in series between X2 and the crystal. As a starting point for evaluating an oscillator circuit, if the requirements for the crystal are not known, CL1 and CL2 should be set at 33 pF, and R1 should be set at 0 Ω. Specification for 25-MHz crystal are listed in Table 6-3. 76 Application and Implementation Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP DP83848-EP www.ti.com SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 Figure 6-3. Crystal Oscillator Circuit Table 6-1. 25-MHz Oscillator Specification PARAMETER MIN TYP Frequency 25 UNIT CONDITION MHz Frequency Tolerance ±50 ppm Operational Temperature Frequency Stability ±50 ppm 1 year aging Rise / Fall Time 6 nsec 20% - 80% Jitter 800 (1) psec Short term Jitter 800 (1) psec Symmetry (1) MAX 40% 60% Long term Duty Cycle This limit is provided as a guideline for component selection and not specified by production testing. Refer to SNLA091, PHYTER 100 Base-TX Reference Clock Jitter Tolerance, for details on jitter performance. Table 6-2. 50-MHz Oscillator Specification PARAMETER MIN TYP Frequency 50 UNIT CONDITION MHz Frequency Tolerance ±50 ppm Operational Temperature Frequency Stability ±50 ppm Operational Temperature Rise / Fall Time 6 nsec 20% - 80% Jitter 800 (1) psec Short term Jitter 800 (1) psec Symmetry (1) MAX 40% 60% Long term Duty Cycle This limit is provided as a guideline for component selection and not specified by production testing. Refer to SNLA091, PHYTER 100 Base-TX Reference Clock Jitter Tolerance, for details on jitter performance. Table 6-3. 25-MHz Crystal Specification PARAMETER MIN Frequency TYP MAX 25 UNIT CONDITION MHz Frequency Tolerance ±50 ppm Operational Temperature Frequency Stability ±50 ppm 1 year aging 40 pF Load Capacitance 6.2.1.3 25 Power Feedback Circuit To ensure correct operation for the DP83848-EP, parallel caps with values of 10 µF and 0.1 µF should be placed close to pin 23 (PFBOUT) of the device. Pin 18 (PFBIN1), pin 37 (PFBIN2), pin 23 (PFBIN3) and pin 54 (PFBIN4) must be connected to pin 31 (PFBOUT), each pin requires a small capacitor (0.1 µF). See Figure 6-4 below for proper connections. Application and Implementation Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP 77 DP83848-EP SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 www.ti.com Pin 19 (PFBOUT) 10 PF Pin 16 (PFBIN1) + - 0.1 PF 0.1 PF Pin 30 (PFBIN2) 0.1 PF Figure 6-4. Power Feedback Connection 6.2.1.4 Power Down and Interrupt The power down and interrupt functions are multiplexed on pin 7 of the device. By default, this pin functions as a power down input and the interrupt function is disabled. Setting bit 0 (INT_OE) of MICR (0x11h) will configure the pin as an active low interrupt output. 6.2.1.4.1 Power Down Control Mode The PWR_DOWN/INT pin can be asserted low to put the device in a power down mode. This is equivalent to setting bit 11 (power down) in the basic mode control register, BMCR (0x00h). An external control signal can be used to drive the pin low, overcoming the weak internal pullup resistor. Alternatively, the device can be configured to initialize into a power down state by use of an external pulldown resistor on the PWR_DOWN/INT pin. Since the device will still respond to management register accesses, setting the INT_OE bit in the MICR register will disable the PWR_DOWN/INT input, allowing the device to exit the power down state. 6.2.1.4.2 Interrupt Mechanisms The interrupt function is controlled via register access. All interrupt sources are disabled by default. Setting bit 1 (INTEN) of MICR (0x11h) will enable interrupts to be output, dependent on the interrupt mask set in the lower byte of the MISR (0x12h). The PWR_DOWN/INT pin is asynchronously asserted low when an interrupt condition occurs. The source of the interrupt can be determined by reading the upper byte of the MISR. One or more bits in the MISR will be set, denoting all currently pending interrupts. Reading of the MISR clears ALL pending interrupts. Example: To generate an interrupt on a change of link status or on a change of energy detect power state, the steps would be: • Write 0003h to MICR to set INTEN and INT_OE • Write 0060h to MISR to set ED_INT_EN and LINK_INT_EN • Monitor PWR_DOWN/INT pin When PWR_DOWN/INT pin asserts low, user would read the MISR register to see if the ED_INT or LINK_INT bits are set, i.e. which source caused the interrupt. After reading the MISR, the interrupt bits should clear and the PWR_DOWN/INT pin will deassert. 6.2.1.5 Magnetics The magnetics have a large impact on the PHY performance as well. While several components are listed below, others may be compatible following the requirements listed in Table 6-4. It is recommended that the magnetics include both an isolation transformer and an integrated common mode choke to reduce EMI. When doing the layout, do not run signals under the magnetics. This could cause unwanted noise crosstalk. Likewise void the planes under discrete magnetics, this will help prevent common mode noise coupling. To save board space and reduce component count, an RJ-45 with integrated magnetics may be used. 78 Application and Implementation Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP DP83848-EP www.ti.com SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 Table 6-4. Magnetics Requirements PARAMETER TYP UNIT Turn Ratio 1:1 — ±2% Insertion Loss –1 dB 1 MHz to 100 MHz –16 dB 1 MHz to 30 MHz –12 dB 30 MHz to 60 MHz –10 dB 60 MHz to 80 MHz –30 dB 1 MHz to 50 MHz –20 dB 50 MHz to 150 MHz –35 dB 30 MHz –30 dB 60 MHz 1500 Vrms HPOT Return Loss Differential to Common Rejection Ratio Crosstalk Isolation 6.2.2 CONDITION Detailed Design Procedure 6.2.2.1 MAC Interface (MII/RMII) The Media Independent Interface (MII) connects the PHYTER component to the Media Access Controller (MAC). The MAC may in fact be a discrete device, integrated into a microprocessor, CPU or FPGA. On the MII signals, the IEEE specification states the bus should be 68-Ω impedance. For space critical designs, the PHYTER family of products also support Reduced MII (RMII). For additional information on this mode of operation, refer to the AN-1405 DP83848 Single 10/100 Mbps Ethernet Transceiver Reduced Media Independent Interface (RMII) Mode Application Report (SNLA076). 6.2.2.2 Termination Requirement To reduce digital signal energy, 50-Ω series termination resistors are recommended for all MII output signals (including RXCLK, TXCLK, and RX Data signals). 6.2.2.3 Recommended Maximum Trace Length Although RMII and MII are synchronous bus architectures, there are a number of factors limiting signal trace lengths. With a longer trace, the signal becomes more attenuated at the destination and thus more susceptible to noise interference. Longer traces also act as antennas, and if run on the surface layer, can increase EMI radiation. If a long trace is running near and adjacent to a noisy signal, the unwanted signals could be coupled in as crosstalk. TI recommends keeping the signal trace lengths as short as possible. Ideally, keep the traces under 6 inches. Trace length matching, to within 2 inches on the MII or RMII bus is also recommended. Significant differences in the trace lengths can cause data timing issues. As with any high-speed data signal, good design practices dictate that impedance should be maintained and stubs should be avoided throughout the entire data path. 6.2.2.4 Calculating Impedance Equation 2 through Equation 5 can be used to calculate the differential impedance of the board. For microstrip traces, a solid ground plane is needed under the signal traces. The ground plane helps keep the EMI localized and the trace impedance continuous. Because stripline traces are typically sandwiched between the ground/supply planes, they have the advantage of lower EMI radiation and less noise coupling. The trade off of using strip line is lower propagation speed. Microstrip Impedance - Single-Ended: æ ö æ 87 H ö ÷ ln ç 5.98 Zo = ç ÷ ç E + (1.41) ÷ è 0.8W + T ø è r ø (2) Application and Implementation Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP 79 DP83848-EP SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 www.ti.com Figure 6-5. Microstrip Impedance - Single-Ended Stripline Impedance - Single-Ended: æ 60 ö æ 2H + T ö ÷ ln 1.98 Zo = ç ç E ÷ çè + T ÷ø 0.8W è r ø (3) Figure 6-6. Stripline Impedance – Single Ended Microstrip Impedance - Differential: Zdiff = 2Zo Sö æ ç -0.96 ÷ Hø è (1 - 0.48(e ) (4) Figure 6-7. Microstrip Impedance - Differential Stripline Impedance - Differential: Zdiff = 2Zo 80 Sö æ ç -2.9 ÷ Hø è (1 - 0.347(e ) (5) Application and Implementation Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP DP83848-EP www.ti.com SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 Figure 6-8. Stripline Impedance - Differential 6.2.3 Application Curves Figure 6-9. Sample 100-Mbps Waveform (MLT-3) Figure 6-10. Sample 10-Mbps Waveform Application and Implementation Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP 81 DP83848-EP SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 www.ti.com 7 Power Supply Recommendations The device Vdd supply pins should be bypassed with low impedance 0.1-µF surface mount capacitors. To reduce EMI, the capacitors should be places as close as possible to the component Vdd supply pins, preferably between the supply pins and the vias connecting to the power plane. In some systems it may be desirable to add 0-Ω resistors in series with supply pins, as the resistor pads provide flexibility if adding EMI beads becomes necessary to meet system level certification testing requirements. (See Figure 7-1) It is recommended the PCB have at least one solid ground plane and one solid Vdd plane to provide a low impedance power source to the component. This also provides a low impedance return path for nondifferential digital MII and clock signals. A 10-µF capacitor should also be placed near the PHY component for local bulk bypassing between the Vdd and ground planes. Figure 7-1. Vdd Bypass Layout 82 Power Supply Recommendations Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP DP83848-EP www.ti.com SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 8 Layout 8.1 8.1.1 Layout Guidelines PCB Layout Considerations Place the 49.9-Ω,1% resistors, and 0.1-µF decoupling capacitor, near the PHYTER TD± and RD± pins and via directly to the Vdd plane. Stubs should be avoided on all signal traces, especially the differential signal pairs. See Figure 8-1. Within the pairs (for example, TD+ and TD–) the trace lengths should be run parallel to each other and matched in length. Matched lengths minimize delay differences, avoiding an increase in common mode noise and increased EMI. See Figure 8-1. Figure 8-1. Differential Signal Pair – Stubs Ideally there should be no crossover or via on the signal paths. Vias present impedance discontinuities and should be minimized. Route an entire trace pair on a single layer if possible. PCB trace lengths should be kept as short as possible. Signal traces should not be run such that they cross a plane split. See Figure 8-2. A signal crossing a plane split may cause unpredictable return path currents and would likely impact signal quality as well, potentially creating EMI problems. Figure 8-2. Differential Signal Pair-Plane Crossing MDI signal traces should have 50 Ω to ground or 100-Ω differential controlled impedance. Many tools are available online to calculate this. 8.1.2 PCB Layer Stacking To meet signal integrity and performance requirements, at minimum a four layer PCB is recommended for implementing PHYTER components in end user systems. The following layer stack-ups are recommended for four, six, and eight-layer boards, although other options are possible. Layout Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP 83 DP83848-EP SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 www.ti.com Figure 8-3. PCB Stripline Layer Stacking Within a PCB it may be desirable to run traces using different methods, microstrip vs stripline, depending on the location of the signal on the PCB. For example, it may be desirable to change layer stacking where an isolated chassis ground plane is used. Figure 8-4 illustrates alternative PCB stacking options. 84 Layout Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP DP83848-EP www.ti.com SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 Figure 8-4. Alternative PCB Stripline Layer Stacking Layout Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP 85 DP83848-EP SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 8.2 www.ti.com Layout Example Figure 8-5. Layout Example 8.3 Thermal Vias Recommendation The following thermal via guidelines apply to GNDPAD, pin 49: 1. Thermal via size = 0.2 mm 2. Recommend 4 vias 3. Vias have a center to center separation of 2 mm Adherence to this guideline is required to achieve the intended operating temperature range of the device. Figure 8-6 illustrates an example layout. 86 Layout Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP DP83848-EP www.ti.com SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 Figure 8-6. Top View, Thermal Vias for GNDPAD, Pin 49 Layout Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP 87 DP83848-EP SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 www.ti.com 9 Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. 9.1 Documentation Support 9.1.1 Related Documentation • • 9.2 AN-1405 DP83848 Single 10/100 Mb/s Ethernet Transceiver Reduced Media Independent Interface™ (RMII™) Mode, SNLA076 PHYTER 100 Base-TX Reference Clock Jitter Tolerance, SNLA091 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community The TI engineer-to-engineer (E2E) community was created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. TI Embedded Processors Wiki Established to help developers get started with Embedded Processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices. 9.3 Trademarks PHYTER, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 9.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 9.5 Export Control Notice Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled product restricted by other applicable national regulations, received from disclosing party under nondisclosure obligations (if any), or any direct product of such technology, to any destination to which such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S. Department of Commerce and other competent Government authorities to the extent required by those laws. 9.6 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 88 Device and Documentation Support Copyright © 2012–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP DP83848-EP www.ti.com SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 10 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2012–2019, Texas Instruments Incorporated Mechanical, Packaging, and Orderable Information Submit Documentation Feedback Product Folder Links: DP83848-EP 89 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) DP83848MPHPEP ACTIVE HTQFP PHP 48 250 RoHS & Green NIPDAU Level-4-260C-72 HR -55 to 125 DP83848EP DP83848MPHPREP ACTIVE HTQFP PHP 48 1000 RoHS & Green NIPDAU Level-4-260C-72 HR -55 to 125 DP83848EP DP83848MPTBEP ACTIVE HLQFP PTB 48 250 RoHS & Green NIPDAUAG Level-3-260C-168 HR -55 to 125 DP83848 EP DP83848MPTBREP ACTIVE HLQFP PTB 48 1000 RoHS & Green NIPDAUAG Level-3-260C-168 HR -55 to 125 DP83848 EP V62/12615-01XE ACTIVE HTQFP PHP 48 1000 RoHS & Green NIPDAU Level-4-260C-72 HR -55 to 125 DP83848EP V62/12615-01XE-R ACTIVE HTQFP PHP 48 250 RoHS & Green NIPDAU Level-4-260C-72 HR -55 to 125 DP83848EP V62/12615-01YE ACTIVE HLQFP PTB 48 250 RoHS & Green NIPDAUAG Level-3-260C-168 HR -55 to 125 DP83848 EP V62/12615-01YE-R ACTIVE HLQFP PTB 48 1000 RoHS & Green NIPDAUAG Level-3-260C-168 HR -55 to 125 DP83848 EP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of