DP83849IVSX/NOPB

Product Folder Sample & Buy Technical Documents Tools & Software Support & Community Reference Design DP83849I SNOSAX1F – MAY 2008 – REVISED SEPTEMBER 2015 DP83849I PHYTER DUAL Industrial Temperature With Flexible Port Switching Dual Port 10/100 Mb/s Ethernet Physical Layer Transceiver 1 Device Overview 1.1 Features 1 • • • • • • • • • • • • • • Low-power 3.3-V, 0.18-µm CMOS Technology Low power Consumption 2 ms timer (default) Var_Timer = 1 => 4 ms timer Var_Timer = 2 => 6 ms timer Var_Timer = 3 => 8 ms timer Time units are actually 217 cycles of an 8ns clock, or 1.048576ms 0 VAR_ENABLE 5.6.3.8 0, RW Variance Enable: Enable Variance computation. Off by default. Variance Data Register (VAR_DATA), Page 2, address 1Bh This register contains the 32-bit Variance Sum. The contents of the data are valid only when VAR_RDY is asserted in the VAR_CTRL register. Upon detection of VAR_RDY asserted, software must set the VAR_FREEZE bit in the VAR_CTRL register to prevent loading of a new value into the VAR_DATA register. Because the Variance-Data value is 32-bits, two reads of this register are required to get the full value. Table 5-47. Variance Data Register (VAR_DATA), address 1Bh BIT BIT NAME DEFAULT DESCRIPTION 15:0 VAR_DATA 0, RO Variance Data: Two reads are required to return the full 32-bit Variance Sum value. Following setting the VAR_FREEZE control, the first read of this register will return the low 16 bits of the Variance data. A second read will return the high 16 bits of Variance data. 84 Detailed Description Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83849I DP83849I www.ti.com 5.6.3.9 SNOSAX1F – MAY 2008 – REVISED SEPTEMBER 2015 Link Quality Monitor Register (LQMR), Page 2, address 1Dh This register contains the controls for the Link Quality Monitor function. The Link Quality Monitor provides a mechanism for programming a set of thresholds for DSP parameters. If the thresholds are violated, an interrupt will be asserted if enabled in the MISR. Monitor control and status are available in this register, while the LQDR register controls read/write access to threshold values and current parameter values. Reading of LQMR register clears warning bits and re-arms the interrupt generation. In addition, this register provides a mechanims for allowing automatic reset of the 100-Mb link based on the Link Quality Monitor status. Table 5-48. Link Quality Monitor Register (LQMR), address 1Dh BIT BIT NAME DEFAULT DESCRIPTION 15 LQM_ENABLE 0, RW Link Quality Monitor Enable: Enables the Link Quality Monitor. The enable is qualified by having a valid 100Mb link. In addition, the individual thresholds can be dis- abled by setting to the max or min values. 14:10 9 8 7 6 5 4 3 2 1 0 RESERVED 0, RO RESERVED: Writes ignored, read as 0. FC_HI_WARN 0, RO/COR Frequency Control High Warning: 0, RO/COR Frequency Control Low Warning: 0, RO/COR Frequency Offset High Warning: 0, RO/COR Frequency Offset Low Warning: . 0, RO/COR DBLW High Warning: 0, RO/COR DBLW Low Warning: 0, RO/COR DAGC High Warning: 0, RO/COR DAGC Low Warning: 0, RO/COR C1 High Warning: 0, RO/COR C1 Low Warning: FC_LO_WARN FREQ_HI_WARN FREQ_LO_WARN DBLW_HI_WARN DBLW_LO_WARN DAGC_HI_WARN DAGC_LO_WARN C1_HI_WARN C1_LO_WARN This bit indicates the Frequency Control High Threshold was exceeded. This register bit will be cleared on read. This bit indicates the Frequency Control Low Threshold was exceeded. This register bit will be cleared on read. This bit indicates the Frequency Offset High Threshold was exceeded. This register bit will be cleared on read. This bit indicates the Frequency Offset Low Threshold was exceeded. This register bit will be cleared on read This bit indicates the DBLW High Threshold was exceeded. This register bit will be cleared on read. This bit indicates the DBLW Low Threshold was exceeded. This register bit will be cleared on read. This bit indicates the DAGC High Threshold was exceeded. This register bit will be cleared on read. This bit indicates the DAGC Low Threshold was exceeded. This register bit will be cleared on read. This bit indicates the DEQ C1 High Threshold was exceeded. This register bit will be cleared on read. This bit indicates the DEQ C1 Low Threshold was exceeded. This register bit will be cleared on read. Detailed Description Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83849I 85 DP83849I SNOSAX1F – MAY 2008 – REVISED SEPTEMBER 2015 www.ti.com 5.6.3.10 Link Quality Data Register (LQDR), Page 2 This register provides read/write control of thresholds for the 100Mb Link Quality Monitor function. The register also provides a mechanism for reading current adapted parameter values. Threshold values may not be written if the device is powered-down. Table 5-49. Link Quality Data Register (LQDR), address 1Eh BIT 15:14 13 BIT NAME DEFAULT DESCRIPTION RESERVED 0, RO RESERVED: Writes ignored, read as 0. SAMPLE_PARAM 0, RW Sample DSP Parameter: Setting this bit to a 1 enables reading of current parameter values and initiates sampling of the parameter value. The parameter to be read is selected by the LQ_PARAM_SEL bits. 12 WRITE_LQ_THR 0, RW Write Link Quality Threshold: Setting this bit will cause a write to the Threshold register selected by LQ_PARAM_SEL and LQ_THR_SEL. The data written is contained in LQ_THR_DATA. This bit will always read back as 0. 11:9 LQ_PARAM_SEL 0, RW Link Quality Parameter Select: This 3-bit field selects the Link Quality Parameter. This field is used for sampling current parameter values as well as for reads/writes to Threshold values. The following encodings are available: 000: DEQ_C1 001: DAGC 010: DBLW 011: Frequency Offset 100: Frequency Control 8 LQ_THR_SEL 0, RW Link Quality Threshold Select: This bit selects the Link Quality Threshold to be read or written. A 0 selects the Low threshold, while a 1 selects the high threshold. When combined with the LQ_PARAM_SEL field, the following encodings are available {LQ_PARAM_SEL, LQ_THR_SEL}: 000,0: DEQ_C1 Low 000,1: DEQ_C1 High 001,0: DAGC Low 001,1: DAGC High 010,0: DBLW Low 010,1: DBLW High 011,0: Frequency Offset Low 011,1: Frequency Offset High 100,0: Frequency Control Low 100,1: Frequency Control High 7:0 LQ_THR_DATA 0, RW Link Quality Threshold Data: The operation of this field is dependent on the value of the Sample_Param bit. If Sample_Param = 0: On a write, this value contains the data to be written to the selected Link Quality Threshold register. On a read, this value contains the current data in the selected Link Quality Threshold register. If Sample_Param = 1: On a read, this value contains the sampled parameter value. This value will remain unchanged until a new read sequence is started 86 Detailed Description Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83849I DP83849I www.ti.com SNOSAX1F – MAY 2008 – REVISED SEPTEMBER 2015 6 Applications, Implementation, and Layout NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 6.1 Application Information The DP83849I is a dual port physical layer Ethernet transceiver. When using the device for Ethernet application, it is necessary to meet certain requirements for normal operation of the device. The following typical application and design requirements can be used for selecting appropriate component values for DP83849. MAC Magnetics DP83849I Port A MII/RMII/SNI 25 MHz Clock Source RJ-45 MII/RMII/SNI RJ-45 Port B MPU/CPU 6.2.1 Magnetics Typical Application MAC 6.2 10BASE-T or 100BASE-TX 10BASE-T or 100BASE-TX Status LEDs Design Requirements For this design example, use the parameters listed in Table 6-1 as the input parameters. Table 6-1. Design Parameters PARAMETER 6.2.2 EXAMPLE VALUE VIN 3.3 V VOUT VCC – 0.5 V Clock Input 25 MHz for MII and 50 MHz for RMII Detailed Design Procedure 6.2.2.1 TPI Network Circuit Figure 6-1 shows the recommended circuit for a 10/100 Mb/s twisted pair interface. Below is a partial list of recommended transformers. It is important that the user realize that variations with PCB and component characteristics requires that the application be tested to ensure that the circuit meets the requirements of the intended application. • Pulse H1102 • Pulse H2019 • Belfuse S558-5999-U7 • Halo TG110-S050N2RL Applications, Implementation, and Layout Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83849I 87 DP83849I SNOSAX1F – MAY 2008 – REVISED SEPTEMBER 2015 www.ti.com Vdd TPRDM Vdd COMMON MODE CHOKES MAY BE REQUIRED. 49.9Ω 0.1μF 1:1 49.9Ω TDRDP RD- 0.1µF* RD+ TD- TPTDM TD+ 0.1µF* Vdd 49.9Ω RJ45 1:1 0.1μF T1 NOTE: CENTER TAP IS PULLED TO VDD 49.9Ω *PLACE CAPACITORS CLOSE TO THE TRANSFORMER CENTER TAPS TPTDP PLACE RESISTORS AND CAPACITORS CLOSE TO THE DEVICE. All values are typical and are +/- 1% Figure 6-1. 10/100 Mb/s Twisted Pair Interface 6.2.2.2 Clock In (X1) Requirements The DP83849I supports an external CMOS level oscillator source or a crystal resonator device. 6.2.2.2.1 Oscillator If an external clock source is used, X1 must be tied to the clock source and X2 must be left floating. Specifications for CMOS oscillators: 25 MHz in MII Mode and 50 MHz in RMII Mode are listed in Table 6-2 and Table 6-3. 6.2.2.2.2 Crystal A 25 MHz, parallel, 20-pF load crystal resonator must be used if a crystal source is desired. Figure 6-2 shows a typical connection for a crystal resonator circuit. The load capacitor values will vary with the crystal vendors; check with the vendor for the recommended loads. The oscillator circuit is designed to drive a parallel resonance AT cut crystal with a minimum drive level of 100 µW and a maximum of 500 µW. If a crystal is specified for a lower drive level, a current limiting resistor must be placed in series between X2 and the crystal. As a starting point for evaluating an oscillator circuit, if the requirements for the crystal are not known, CL1 and CL2 must be set at 33 pF, and R1 must be set at 0 Ω. Specification for 25-MHz crystal are listed in Table 6-4. 88 Applications, Implementation, and Layout Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83849I DP83849I www.ti.com SNOSAX1F – MAY 2008 – REVISED SEPTEMBER 2015 X2 X1 R1 CL1 CL2 Figure 6-2. Crystal Oscillator Circuit Table 6-2. 25-MHz Oscillator Specification PARAMETER TEST CONDITIONS MIN Frequency TYP MAX UNIT 25 MHz Frequency Tolerance Operational Temperature 50 ppm Frequency Stability 1 year aging 50 ppm Rise / Fall Time 20%–80% 6 nsec Jitter Short term 800 (1) psec Jitter Long term 800 (1) psec Symmetry Duty Cycle (1) 40% 60% This limit is provided as a guideline for component selection and not guaranteed by production testing. Refer to SNLA076, PHYTER 100 Base-TX Reference Clock Jitter Tolerance, for details on jitter performance. Table 6-3. 50-MHz Oscillator Specification PARAMETER TEST CONDITIONS MIN Frequency TYP MAX 50 UNIT MHz Frequency Tolerance Operational Temperature ±50 ppm Frequency Stability Operational Temperature ±50 ppm Rise / Fall Time 20%–80% 6 nsec Jitter Short term 800 (1) psec Jitter Long term 800 (1) psec Symmetry Duty Cycle (1) 40% 60% This limit is provided as a guideline for component selection and not guaranteed by production testing. Refer to SNLA076, PHYTER 100 Base-TX Reference Clock Jitter Tolerance, for details on jitter performance. Table 6-4. 25-MHz Crystal Specification PARAMETER CONDITION MIN Frequency TYP MAX 25 UNIT MHz Frequency Tolerance Operational Temperature ±50 ppm Frequency Stability 1 year aging ±50 ppm 40 pF Load Capacitance 6.2.3 25 Power Feedback Circuit To ensure correct operation for the DP83849I, parallel caps with values of 10 µF and 0.1 µF must be placed close to pin 31 (PFBOUT) of the device. Pin 7 (PFBIN1), pin 28 (PFBIN2), pin 34 (PFBIN3) and pin 54 (PFBIN4) must be connected to pin 31 (PFBOUT), each pin requires a small capacitor (0.1 µF). See Figure 6-3 for proper connections. Applications, Implementation, and Layout Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83849I 89 DP83849I SNOSAX1F – MAY 2008 – REVISED SEPTEMBER 2015 www.ti.com Pin 31 (PFBOUT) 10 μF + .1 μF Pin 7 (PFBIN1) .1 μF Pin 28 (PFBIN2) .1 μF Pin 34 (PFBIN3) Pin 54 (PFBIN4) .1 μF .1 μF Figure 6-3. Power Feedback Connections 6.2.4 Power Down/Interrupt The Power Down and Interrupt functions are multiplexed on pin 18 and pin 44 of the device. By default, this pin functions as a power down input and the interrupt function is disabled. Setting bit 0 (INT_OE) of MICR (11h) will configure the pin as an active low interrupt output. Ports A and B can be powered down individually, using the separate PWRDOWN_INT_A and PWRDOWN_INT_B pins. 6.2.4.1 Power Down Control Mode The PWRDOWN_INT pins can be asserted low to put the device in a Power Down mode. This is equivalent to setting bit 11 (Power Down) in the Basic Mode Control Register, BMCR (00h). An external control signal can be used to drive the pin low, overcoming the weak internal pullup resistor. Alternatively, the device can be configured to initialize into a Power Down state by use of an external pulldown resistor on the PWRDOWN_INT pin. Because the device will still respond to management register accesses, setting the INT_OE bit in the MICR register will disable the PWRDOWN_INT input, allowing the device to exit the Power Down state 6.2.4.2 Interrupt Mechanisms Because each port has a separate interrupt pin, the interrupts can be connected individually or may be combined in a wired-OR fashion. If the interrupts share a single connection, each port status must be checked following an interrupt. The interrupt function is controlled through register access. All interrupt sources are disabled by default. Setting bit 1 (INTEN) of MICR (11h) will enable interrupts to be output, dependent on the interrupt mask set in the lower byte of the MISR (12h). The PWRDOWN_INT pin is asynchronously asserted low when an interrupt condition occurs. The source of the interrupt can be determined by reading the upper byte of the MISR. One or more bits in the MISR will be set, denoting all currently pending interrupts. Reading of the MISR clears ALL pending interrupts. Example: To generate an interrupt on a change of link status or on a change of energy detect power state, the steps would be: • Write 0003h to MICR to set INTEN and INT_OE • Write 0060h to MISR to set ED_INT_EN and LINK_INT_EN • Monitor PWRDOWN_INT pin 90 Applications, Implementation, and Layout Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83849I DP83849I www.ti.com SNOSAX1F – MAY 2008 – REVISED SEPTEMBER 2015 When PWRDOWN_INT pin asserts low, the user would read the MISR register to see if the ED_INT or LINK_INT bits are set; that is, which source caused the interrupt. After reading the MISR, the interrupt bits must clear and the PWRDOWN_INT pin will deassert. 6.2.5 Application Curves Figure 6-4. Sample 100-Mb/s Waveform (MLT-3) Figure 6-5. Sample 10-Mb/s Waveform Applications, Implementation, and Layout Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83849I 91 DP83849I SNOSAX1F – MAY 2008 – REVISED SEPTEMBER 2015 www.ti.com 7 Power Supply Recommendations The device VDD supply pins must be bypassed with low-impedance 0.1-μF surface mount capacitors. To reduce EMI, the capacitors must be places as close as possible to the component VDD supply pins, preferably between the supply pins and the vias connecting to the power plane. In some systems it may be desirable to add 0-Ω resistors in series with supply pins, as the resistor pads provide flexibility if adding EMI beads becomes necessary to meet system level certification testing requirements. (See Figure 7-1) It is recommended the PCB have at least one solid ground plane and one solid VDD plane to provide a low impedance power source to the component. This also provides a low impedance return path for nondifferential digital MII and clock signals. A 10.0-μF capacitor must also be placed near the PHY component for local bulk bypassing between the VDD and ground planes. PHY Component Vdd PCB Via Vdd Pin Optional 0 : or Bead 0.1 PF Ground Pin PCB Via Figure 7-1. VDD Bypass Layout 92 Power Supply Recommendations Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83849I DP83849I www.ti.com SNOSAX1F – MAY 2008 – REVISED SEPTEMBER 2015 8 Layout 8.1 Layout Guidelines Place the 49.9-Ω,1% resistors, and 0.1-μF decoupling capacitor near the PHYTER TD± and RD± pins and through directly to the VDD plane. Stubs must be avoided on all signal traces, especially the differential signal pairs. See Figure 8-1. Within the pairs (for example, TD+ and TD-) the trace lengths must be run parallel to each other and matched in length. Matched lengths minimize delay differences, avoiding an increase in common mode noise and increased EMI. See Figure 8-1. Does Not Maintain Parallelism Avoid Stubs Ground or Power Plane Figure 8-1. Differential Signal Pair - Stubs Ideally, there must be no crossover or through on the signal paths. Vias present impedance discontinuities and must be minimized. Route an entire trace pair on a single layer if possible. PCB trace lengths must be kept as short as possible. Signal traces must not be run such that they cross a plane split. See Figure 8-2. A signal crossing a plane split may cause unpredictable return path currents and would likely impact signal quality as well, potentially creating EMI problems. Layout Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83849I 93 DP83849I SNOSAX1F – MAY 2008 – REVISED SEPTEMBER 2015 www.ti.com Figure 8-2. Differential Signal Pair-Plane Crossing MDI signal traces must have 50 Ω to ground or 100-Ω differential controlled impedance. Many tools are available online to calculate this. 94 Layout Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83849I DP83849I www.ti.com 8.1.1 SNOSAX1F – MAY 2008 – REVISED SEPTEMBER 2015 PCB Layer Stacking To meet signal integrity and performance requirements, at minimum a 4-layer PCB is recommended for implementing PHYTER components in end user systems. The following layer stack-ups are recommended for four, six, and eight-layer boards, although other options are possible. Figure 8-3. PCB Stripline Layer Stacking Layout Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83849I 95 DP83849I SNOSAX1F – MAY 2008 – REVISED SEPTEMBER 2015 www.ti.com Within a PCB it may be desirable to run traces using different methods, microstrip vs. stripline, depending on the location of the signal on the PCB. For example, it may be desirable to change layer stacking where an isolated chassis ground plane is used. Figure 8-4 illustrates alternative PCB stacking options. Figure 8-4. Alternative PCB Stripline Layer Stacking 8.2 Layout Example Plane Coupling Component Transformer (if not Integrated in RJ45) PHY Component Termination Components Note:Power/ Ground Planes Voided under Transformer System Power/Ground Planes RJ45 Connector Plane Coupling Component Chassis Ground Plane Figure 8-5. Layout Example 96 Layout Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83849I DP83849I www.ti.com SNOSAX1F – MAY 2008 – REVISED SEPTEMBER 2015 9 Device and Documentation Support 9.1 9.1.1 Community Resources Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 9.2 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 9.3 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 9.4 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 10 Mechanical Packaging and Orderable Information 10.1 Packaging Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2008–2015, Texas Instruments Incorporated Mechanical Packaging and Orderable Information Submit Documentation Feedback Product Folder Links: DP83849I 97 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking (4/5) (6) DP83849IVS/NOPB ACTIVE TQFP PFC 80 119 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 DP83849IVS DP83849IVSX/NOPB ACTIVE TQFP PFC 80 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 DP83849IVS (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of