DRV103H

DRV103 D RV DRV 103 103 SBVS029A – JUNE 2001 PWM LOW-SIDE DRIVER (1.5A and 3A) for Solenoids, Coils, Valves, Heaters, and Lamps FEATURES DESCRIPTION ● HIGH OUTPUT DRIVE: 1.5A and 3A Versions ● WIDE SUPPLY RANGE: +8V to +32V ● COMPLETE FUNCTION Digitally Controlled Input PWM Output Adjustable Internal Oscillator: 500Hz to 100kHz Adjustable Delay and Duty Cycle ● FULLY PROTECTED Thermal and Current Limit Shutdown with Status OK Indicator Flag ● PACKAGES: SO-8 and PowerPAD™ SO-8 The DRV103 is a low-side DMOS power switch employing a pulse-width modulated (PWM) output. Its rugged design is optimized for driving electromechanical devices such as valves, solenoids, relays, actuators, motors, and positioners. The DRV103 is also ideal for driving thermal devices such as heaters, coolers, and lamps. PWM operation conserves power and reduces heat rise, resulting in higher reliability. In addition, adjustable PWM allows fine control of the power delivered to the load. DC-to-PWM output delay time and oscillator frequency are also externally adjustable. The DRV103 can be set to provide a strong initial closure, automatically switching to a “soft” hold mode for power savings. A resistor, analog voltage, or Digital-to-Analog (D/A) converter can control the duty cycle. An output OK flag indicates when thermal shutdown or over current occurs. Two packages provide a choice of output current: 1.5A (SO-8) or 3A (PowerPAD™ SO-8 with exposed metal heat sink). The DRV103 is specified for –40°C to +85°C. APPLICATIONS ● ELECTROMECHANICAL DRIVER: Solenoids, Valves, Positioners, Actuators, Relays, Power Contactor Coils, Heaters, Lamps ● HYDRAULIC AND PNEUMATICS SYSTEMS ● PART HANDLERS AND SORTERS ● CHEMICAL PROCESSING ● ENVIRONMENTAL MONITORING AND HVAC ● THERMOELECTRIC COOLERS ● DC MOTOR SPEED CONTROLS ● MEDICAL AND SCIENTIFIC ANALYZERS ● FUEL INJECTOR DRIVERS Status OK Flag DRV103 Thermal Shutdown Over Current DMOS Flyback Diode ESD Load OUT PowerPAD is a trademark of Texas Instruments. VREF +VS Oscillator DMOS PWM Input On Delay GND Off Delay Adj Osc Freq Adj CD RFREQ Duty Cycle Adj RPWM Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2001, Texas Instruments Incorporated www.ti.com PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE DRAWING NUMBER SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER(1) TRANSPORT MEDIA DRV103U " SO-8 " 182 " –40°C to +85°C " DRV103U " DRV103U DRV103U/2K5 Rails Tape and Reel DRV103H " PowerPAD™ SO-8 " DDA " –40°C to +85°C " DRV103H " DRV103H DRV103H/2K5 Rails Tape and Reel NOTES: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of “DRV103U/2K5” will get a single 2500-piece Tape and Reel. ABSOLUTE MAXIMUM RATINGS(1) Supply Voltage, VS(2) ......................................................................... +40V Input Voltage .................................................................. –0.2V to +5.5V(3) PWM Adjust Input .......................................................... –0.2V to +5.5V(3) Delay Adjust Input .......................................................... –0.2V to +5.5V(3) Frequency Adjust Input .................................................. –0.2V to +5.5V(3) Status OK Flag and OUT .................................................... –0.2V to VS(4) Operating Temperature Range ...................................... –55°C to +125°C Storage Temperature Range ......................................... –65°C to +150°C Junction Temperature .................................................................... +150°C Lead Temperature (soldering, 10s) ............................................... +300°C NOTES: (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. (2) See Bypassing section for discussion about operating near maximum supply voltage. (3) Higher voltage may be applied if current is limited to 2mA. (4) The Status OK Flag will internally current limit at about 10mA. 2 ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. DRV103 SBVS029A ELECTRICAL CHARACTERISTICS At TC = +25°C, VS = +24V, Load = 100Ω, and 4.99kΩ “OK Flag” pullup to +5V, Delay Adj Capacitor = 100pF to Ground, Freq Adj Resistor = 205kΩ to Ground, Duty Cycle Adj Resistor = 137kΩ to Ground, unless otherwise noted. DRV103U, H PARAMETER OUTPUT Output Current(1) Output Saturation Voltage, Source Current Limit(2), (10) Leakage Current DIGITAL CONTROL INPUT(3) VCTR Low (output disabled) VCTR High (output enabled) ICTR Low (output disabled) ICTR High (output enabled) Propagation Delay DELAY TO PWM(4) Delay Equation(5) Delay Time Minimum Delay Time(7) DUTY CYCLE ADJUST Duty Cycle Range Duty Cycle Accuracy vs Supply Voltage Nonlinearity(8) DYNAMIC RESPONSE Output Voltage Rise Time Output Voltage Fall Time Oscillator Frequency Range Oscillator Frequency OK FLAG Normal Operation Fault(90) Sink Current Over-Current Flag: Set CONDITIONS MIN SO-8 Package (U) PowerPAD™ SO-8 Package (H) IO = 1A IO = 0.1A 3 DMOS Output Off, VO = +32V TEMPERATURE RANGE Specified Range Operating Range Storage Range Thermal Resistance, θJA SO-8 (U) PowerPAD™ SO-8 (H)(10) 1.5 3 +0.4 +0.05 3.5 ±1 0 +2.2 VCTR = 0V VCTR = +5.5V On-to-Off and Off-to-On 0.01 120 1 MAX UNITS +0.6 +0.07 4.2 ±10 A A V V A µA +1.2 +5.5 1 150 V V µA µA µs DC to PWM Mode CD = 0.1µF CD = 0 90 See Note (6) 110 18 50% Duty Cycle, 25kHz 50% Duty Cycle, VS = VO = +8V to +32V 10% to 90% Duty Cycle 10 to 90 ±2 ±2 1 VO = 10% to 90% of VS VO = 90% to 10% of VS External Adjust ROSC = 205kΩ 0.2 0.2 0.5 to 100 25 20kΩ Pull-Up to +5V Sinking 1mA VOKFLAG = 0.4V 20 +4.5 THERMAL SHUTDOWN Junction Temperature Shutdown Reset from Shutdown POWER SUPPLY Specified Operating Voltage Operating Voltage Range Quiescent Current TYP 5.0 +0.22 2 5 140 % % % % FSR 2 2 30 +0.4 +24 IO = 0 0.4 –40 –55 –65 1in2 0.5oz. Copper on PCB 1in2 0.5oz. Copper on PCB 150 68 µs µs kHz kHz V V mA µs °C °C +160 +140 +8 s ms µs +32 0.8 V V mA +85 +125 +150 °C °C °C °C/W °C/W NOTES: (1) Output current is limited by internal current limit and by DRV103 power dissipation. (2) Output current resets to zero when current limit is reached. (3) Logic High enables output (normal operation). (4) Constant DC output to PWM (Pulse-Width Modulated) time. (5) Maximum delay is determined by an external capacitor. Pulling the Delay Adjust Pin LOW corresponds to an infinite (continuous) delay. (6) Delay to PWM ≈ C D • 10 6 (C D in F • 1.1). (7) Connecting the Delay Adjust Pin to +5V reduces delay time to less than 1µs. (8) VIN at pin 3 to percent of duty cycle at pin 6. (9) OK Flag LOW indicates fault from over-temperature or over-current conditions. (10) PowerPAD™ SO-8 (H) package has highest continuous current (2A) because the chip operates at a lower junction temperature when underside metal tab is connected to a heat sink or heat spreader. θJA = 68°C/W measured on DRV103 demo board; θJA = 58°C/W measured on JEDEC standard test board. H package θJC = 16.7°C/W. DRV103 SBVS029A 3 PIN CONFIGURATION SO Top View Duty Cycle Adj 1 8 Input Delay Adj 2 7 Status OK Flag Osc Freq Adj 3 6 +VS GND 4 5 OUT PIN DESCRIPTIONS PIN # NAME DESCRIPTION Pin 1 Duty Cycle Adjust Internally, this pin connects to the input of a comparator and a (2.75 x IREF) current source from VS. The voltage at this node linearly sets the duty cycle. Duty cycle can be programmed with a resistor, analog voltage, or the voltage output of a D/A converter. The active voltage range is from 1.3V to 3.9V to facilitate the use of single-supply control electronics. At 3.56V, output duty cycle is near 90%. At 1.5V, output duty cycle is near 10%. Pin 2 Delay Adjust This pin sets the duration of the initial 100% duty cycle before the output goes into PWM mode. Leaving this pin floating results in a delay of approximately 18µs, which is internally limited by parasitic capacitance. Minimum delay may be reduced to less than 1µs by tying the pin to 5V. This pin connects internally to a 3µA current source from VS and to a 2.6V threshold comparator. When the pin voltage is below 2.6V, the output device is 100% ON. The PWM oscillator is not synchronized to the Input (pin 1), so the duration of the first pulse may be any portion of the programmed duty cycle. Pin 3 Oscillator Frequency Adjust PWM frequency is adjustable. A resistor to ground sets the current IREF and the internal PWM oscillator frequency. A range of 500Hz to 100kHz can be achieved with practical resistor values. Although oscillator frequency operation below 500Hz is possible, resistors higher than 10M will be required. The pin then becomes a very high impedance node and is, therefore, sensitive to noise pickup and PCB leakage currents. Pin 4 GND This pin must be connected to system ground for the DRV103 to function. It carries the 0.4mA quiescent current plus the full load current when the power DMOS transistor is switched on. Pin 5 OUT The output is the drain of a power DMOS transistor with its source connected to ground. Its low on-resistance (0.5Ω typ) assures low power dissipation in the DRV103. Gate drive to the power device is controlled to provide a slew-rate limited rise and fall time. This reduces radiated RFI/EMI noise. A flyback diode is needed with inductive loads to conduct the load current during the off cycle. The external diode should be selected for low forward voltage and low storage time. The internal clamp diode (an ESD protection diode) provides some degree of back-EMF protection but it should not be used as a flyback diode. This is the power supply pin. Operating range is +8V to +32V. +VS must be ≥ the supply voltage to the load. Pin 6 +VS Pin 7 Status OK Flag Normally HIGH (active LOW), a Flag LOW signals either an over-temperature or over-current fault. The over-current flag (Status OK) is LOW only when the output is ON (constant DC output or the “ON” portion of PWM mode). A thermal fault (thermal shutdown) occurs when the die surface reaches approximately 160°C and latches until the die cools to 140°C. This output requires a pullup resistor and it can typically sink 2mA, sufficient to drive a low-current LED. Sink current is internally limited at 10mA typical. Pin 8 Input The input is compatible with standard TTL levels. The device output becomes enabled when the input voltage is driven above the typical switching threshold, 1.7V. Below this level, the output is disabled. Input current is typically 10nA when driven HIGH and 10nA with the input LOW. The input should not be directly connected to the power supply (VS) or damage will occur. LOGIC BLOCK DIAGRAM Status OK Flag DRV103 Thermal Shutdown Over Current 1.3V VREF DMOS +VS Flyback Diode ESD Load OUT Oscillator DMOS PWM Input On Delay 2.75 • IREF IREF GND Off 4 Delay Adj Osc Freq Adj CD RFREQ Duty Cycle Adj RPWM DRV103 SBVS029A TYPICAL CHARACTERISTICS At TC = +25°C and VS = +24V, unless otherwise noted. VOUT & IOUT WAVEFORMS SOLENOID LOAD VOUT & IOUT WAVEFORMS RESISTIVE LOAD PWM Mode +VS PWM Mode +VS Off Off Delay Delay 0 0 On +VS On 2 IAVG 0 0 Pull-In 0 50 1 100 IOUT (A) 0 1 3 RL IOUT (A) 2 IAVG On +VS 3 RL 0 0 50 100 Time (ms) Time (ms) CURRENT LIMIT SHUTDOWN WAVEFORMS QUIESCENT CURRENT vs JUNCTION TEMPERATURE 5.0 FPWM = 25kHz DC = 50% Delay = 150µs Reset Period = 1/FPWM Off OK Status OK Flag 0 OK OK 24 OK OK 0 Reset Period 24 VOUT 0 IO = 3.5A 3.5 VOUT (V) IO = 0A 4.0 VIN (V) Off 5 IQ (mA) On VIN 4.5 40V (Absolute Maximum) 3.0 2.5 2.0 32V 1.5 1.0 8V to 24V 0.5 0 0 50 100 –60 –10 40 90 CURRENT LIMIT vs JUNCTION TEMPERATURE DELAY vs JUNCTION TEMPERATURE 150 3.8 145 CD = 0.1µF 140 3.7 Delay (ms) 135 Current (A) 140 Temperature (°C) Time (µs) 3.6 3.5 +VS = 8V 130 +VS = 24V 125 120 115 110 3.4 105 +VS = 30V +VS = 40V (Absolute Maximum) 100 3.3 –60 –10 40 Temperature (°C) DRV103 SBVS029A 90 140 –60 –10 40 90 140 Temperature (°C) 5 TYPICAL CHARACTERISTICS (Cont.) At TC = +25°C and VS = +24V, unless otherwise noted. OSCILLATOR FREQUENCY vs JUNCTION TEMPERATURE MINIMUM DELAY vs JUNCTION TEMPERATURE 25.5 50 CD = 0pF 25.3 Frequency (kHz) Min Delay (µs) 40 30 20 25.1 24.9 10 24.7 0 –60 –10 40 90 140 –60 90 140 Temperature (°C) DUTY CYCLE vs JUNCTION TEMPERATURE VSAT vs JUNCTION TEMPERATURE 50.8 1.6 50.6 1.4 RPWM = 137kΩ 50.4 1.2 50.2 1.0 VSAT (V) Duty Cycle (%) 40 –10 Temperature (°C) 50.0 IO = 1.5A 0.8 49.8 0.6 49.6 0.4 49.4 0.2 49.2 IO = 3A IO = 0.5A IO = 0.1A 0 –60 –10 40 90 140 –60 –10 Temperature (°C) 40 90 140 Temperature (°C) VFREQ vs JUNCTION TEMPERATURE INPUT CURRENT vs INPUT VOLTAGE 1.287 300 1.286 250 1.285 Input Current (µA) VFREQ (V) 1.284 1.283 1.282 1.281 1.280 1.279 1.278 200 150 100 50 0 1.277 –50 1.276 –60 –10 40 Temperature (°C) 6 90 140 4 4.5 5 5.5 6 Input Voltage (V) DRV103 SBVS029A BASIC OPERATION set a longer delay time. A resistor, analog voltage, or a voltage from a D/A converter can be used to control the duty cycle of the PWM output. The D/A converter must be able to sink a current 2.75 • IREF (IREF = 1.3V/RFREQ). Figure 2 illustrates a typical timing diagram with the Delay Adjust pin connected to a 3.9nF capacitor, the duty cycle set to 75%, and oscillator frequency set to 1kHz. See the “Delay Adjust” and “Duty Cycle Adjust” text for equations and further explanation. Ground (pin 4) must be connected to system ground for the DRV103 to function. This serves as the load current path to ground, as well as the DRV103 signal ground. The load (relay, solenoid, valve, etc.) should be connected between the supply (pin 5) and output (pin 6). For an inductive load, an external “flyback” diode is required, as shown in Figure 1. The diode serves to maintain continuous current flow in the inductive load during OFF periods of PWM operation. For remotely located loads, the external diode is ideally located next to the DRV103. The internal ESD clamp diode between the output and supply is not intended to be used as a “flyback diode.” The Status OK Flag (pin 7) provides fault status for over-current and thermal shutdown conditions. This pin is active LOW with output voltage of typically +0.3V during a fault condition. The DRV103 is a low-side, DMOS power switch employing a Pulse-Width Modulated (PWM) output for driving electromechanical and thermal devices. Its design is optimized for two types of applications: a two-state driver (open/close) for loads such as solenoids and actuators; and a linear driver for valves, positioners, heaters, and lamps. Its low 0.5Ω “ON” resistance, small size, adjustable delay to PWM mode, and adjustable duty cycle make it suitable for a wide range of applications. Figure 1 shows the basic circuit connections to operate the DRV103. A 1µF (22µF when driving high current loads) or larger tantalum bypass capacitor is recommended on the power-supply pin. Input (pin 8) is level-triggered and compatible with standard TTL levels. An input voltage between +2.2V and +5.5V turns the device’s output ON, while a voltage of 0V to +1.2V shuts the DRV103’s output OFF. Input bias current is typically 1pA. Delay Adjust (pin 2) and Duty Cycle Adjust (pin 1) allow external adjustment of the PWM output signal. The Delay Adjust pin can be left floating for minimum delay to PWM mode (typically 18µs) or a capacitor can be used to +VS RLED +8V to +32V 2mA LED OK = LED “on” 7 6 8 Relay +VS Status OK TTL IN 3A Flyback Diode(1) 1µF + OUT DRV103 5 NOTE: (1) Motorola MSRS1100T3 (1A, 100V) Delay Adj Osc Freq Adj 2 Duty Cycle Adj 3 or Microsemi SK34MS (3A, 40V) 1 RFREQ CD Motorola MBRS360T3 (3A, 60V) GND 4 RPWM FIGURE 1. DRV103 Basic Circuit Connections. ON TTL HIGH Input (V) TTL LOW OFF Period = OFF 1 = TON + TOFF FREQ +VS VO (V) 0 Delay Time +VS/RL IO (A) Duty Cycle = TOFF TON TON TON + TOFF 0 0 1 2 3 4 Time (ms) 5 6 7 8 9 FIGURE 2. Typical DRV103 Timing Diagram, with CD = 3.9nF, OscFreq = 1kHz, and 75% Duty Cycle. DRV103 SBVS029A 7 APPLICATIONS INFORMATION The internal Delay Adjust circuitry is composed of a 3µA current source and a 2.6V comparator, as shown in Figure 3. Thus, when the pin voltage is less than 2.6V, the output device is 100% ON (DC output mode). POWER SUPPLY The DRV103 operates from a single +8V to +32V supply with excellent performance. Most behavior remains unchanged throughout the full operating voltage range. Parameters that vary significantly with operating voltage are shown in the Typical Performance Curves. The DRV103 supply voltage should be ≥ the supply voltage on the load. OSCILLATOR FREQUENCY ADJUST The DRV103 PWM output frequency can be easily programmed over a wide range by connecting a resistor (RFREQ) between the Osc Freq Adj pin (pin 3) and ground. A range of 500Hz to 100kHz can be achieved with practical resistor values, as shown in Table II. Refer to “PWM Frequency vs RFREQ” typical performance curve shown in Figure 4 for additional information. Although oscillator frequency operation below 500Hz is possible, resistors higher than 10M will be required. The pin becomes a very high impedance node and is, therefore, sensitive to noise pickup and PCB leakage currents if very high resistor values are used. Refer to Figure 3 for a simplified circuit of the frequency adjust input. ADJUSTABLE DELAY TIME (INITIAL 100% DUTY CYCLE) A unique feature of the DRV103 is its ability to provide an initial constant DC output (100% duty cycle) and then switch to PWM mode output to save power. This function is particularly useful when driving solenoids that have a much higher pull-in current requirement than continuous hold requirement. The duration of this constant DC output (before PWM output begins) can be externally controlled by a capacitor connected from Delay Adjust (pin 2) to ground according to the following equation: Delay Time ≈ CD • OSCILLATOR FREQUENCY (Hz) RFREQ (nearest 1% values) (Ω) 100k 50k 25k 10k 5k 500 47.5k 100k 205k 523k 1.07M 11.3M 106 (time in seconds, CD in Farads • 1.1) Leaving the Delay Adjust pin open results in a constant output time of approximately 18µs. The duration of this initial output can be reduced to less than 1µs by connecting the pin to 5V. Table I provides examples of delay times (constant output before PWM mode) achieved with selected capacitor values. TABLE II. Oscillator Frequency Resistance. PWM FREQUENCY vs RFREQ 1000M 100M CD 1µs 18µs 110µs 1.1ms 11ms 110ms 1.1s 11s Pin 2 Tied to +5V Pin 2 Open 100pF 1nF 10nF 100nF 1µF 10µF RFREQ (Ω) 10M INITIAL CONSTANT OUTPUT DURATION 1M 100k 10k 1k 10 100 1k 10k 100k 1M Frequency (Hz) FIGURE 4. Using a Resistor to Program Oscillator Frequency. RFREQ (kΩ) = 6808417/F(1.0288) TABLE I. Delay Adjust Times. +VS 3µA CD Reset +2.6V Input VFREQ IREF VREF +1.3V RFREQ FIGURE 3. Simplified Delay Adjust and Frequency Adjust Inputs. 8 DRV103 SBVS029A The DRV103’s adjustable PWM output frequency allows it to be optimized for driving virtually any type of load. A 100pF capacitor in parallel with RPWM is recommended when switching a high load current to maintain a clean output switching waveform, as shown in Figure 6. ADJUSTABLE DUTY CYCLE (PWM Mode) The DRV103’s externally adjustable duty cycle provides an accurate means of controlling power delivered to a load. Duty cycle can be set over a range of at least 10% to 90% with an external resistor, analog voltage, or the voltage output of a D/A converter. A low duty cycle results in reduced power dissipation in the load. This keeps the DRV103 and the load cooler, resulting in increased reliability for both devices. RPWM only on Pin 1 With 100pF in Parallel with RPWM Resistor Controlled Duty Cycle Duty cycle is easily programmed by connecting a resistor (RPWM) between the Duty Cycle Adjust pin (pin 1) and ground. High resistor values correspond to high duty cycles. Table III provides resistor values for typical duty cycles. Resistor values for additional duty cycles can be obtained from Figure 5. For reference purposes, the equation for calculating RPWM is included in Figure 5. RPWM (Nearest 1% Values) 5 10 20 30 40 50 60 70 80 90 95 5kHz 25kHz 100kHz 374k 402k 475k 549k 619k 681k 750k 825k 887k 953k 1M 75k 80.6k 95.3k 110k 124k 137k 150k 165k 182k 196k 200k 16.9k 19.1k 22.6k 26.1k 29.4k 33.2k 37.4k 40.2k 44.2k 47.5k 49.9k FIGURE 6. Output Waveform at High Load Current. Voltage Controlled Duty Cycle Duty cycle can also be programmed by an analog voltage, VPWM. With VPWM ≈ 3.56V, duty cycle is about 90%. Decreasing this voltage results in decreased duty cycles. Table IV provides VPWM values for typical duty cycles. The “Duty Cycle vs Voltage” typical performance curve for additional duty cycles is shown in Figure 7. DUTY CYCLE AND DUTY CYCLE ERROR vs VOLTAGE 100 2 90 1.5 80 Duty Cycle (%) TABLE III. Duty Cycle Adjust Resistance. DUTY CYCLE vs RPWM 1M 5kHz 1 70 0.5 60 50 0 40 –0.5 30 –1 20 –1.5 10 –2 RPWM (Ω) 0 1 2 25kHz 4 FIGURE 7. Using a Voltage to Program Duty Cycle. At VS = 24V and F = 25kHz: VPWM = 1.25 + 0.026 • %DC. 100kHz 10k 20 3 VPWM (V) 100k 0 Duty Cycle Error (%) DUTY CYCLE (%) Time (10µs) 40 60 80 100 Duty Cycle (%) FIGURE 5. Using a Resistor to Program Duty Cycle. At 25kHz: RPWM (kΩ) = 67.46 + 1.41 • %DC. DUTY CYLE (%) VPWM (V) 5 10 20 40 60 80 90 95 1.344 1.518 1.763 2.283 2.788 3.311 3.561 3.705 TABLE IV. Duty Cycle Adjust Voltage. DRV103 SBVS029A 9 The Duty Cycle Adjust pin is internally driven by an oscillator frequency dependent current source and connects to the input of a comparator as shown in Figure 8. The DRV103’s PWM adjustment is inherently monotonic. That is, a decreased voltage (or resistor value) always produces an increased duty cycle. +5V 5kΩ Pull-Up TTL or HCT OK 7 Thermal Shutdown Over Current 3.9V OUT PWM OSC 1.3V 4 DRV103 +VS 2.75 • IREF 5 FIGURE 9. Non-Latching Fault Monitoring Circuit. +5V RPWM 74XX76A VS FIGURE 8. Simplified Duty Cycle Adjust Input. OK Q OK Q OK Reset 20kΩ J CLR CLK (1) GND K STATUS FLAG The OK Flag (pin 7) provides a fault indication for overcurrent and thermal shutdown conditions. During a fault condition, the Status OK Flag output is driven LOW (pin voltage typically drops to 0.3V). A pull-up resistor, as shown in Figure 9, is required to interface with standard logic. Figure 9 also gives an example of a non-latching fault monitoring circuit, while Figure 10 provides a latching version. The OK Flag pin can sink up to 10mA, sufficient to drive external logic circuitry, a reed relay, or an LED, as shown in Figure 11, to indicate when a fault has occurred. In addition, the OK Flag pin can be used to turn off other DRV103s in a system for chain fault protection. OK 7 Thermal Shutdown Over Current 5 OUT PWM 4 DRV103 NOTE: (1) Small capacitor (10pF) may be required in noisy environments. FIGURE 10. Latching Fault Monitoring Circuit. Over Current Fault An over-current fault occurs when the PWM peak output current is greater than approximately 3.75A. The OK flag is not latched. Since current during PWM mode is switched on and off, the OK flag output will be modulated with PWM timing (see OK flag waveforms in the Typical Performance Curves). +5V 5kΩ (LED) HLMP-Q156 Avoid adding capacitance to pin 6 (Out) as it may cause momentary current limiting. Over-Temperature Fault A thermal fault occurs when the die reaches approximately 160°C, producing a similar effect as pulling the input low. Internal shutdown circuitry disables the output. The OK Flag is latched in the LOW state (fault condition) until the die has cooled to approximately 140°C. OK Thermal Shutdown Over Current 7 5 OUT PWM DRV103 4 FIGURE 11. LED to Indicate Fault Condition. 10 DRV103 SBVS029A PACKAGE MOUNTING THERMAL RESISTANCE vs CIRCUIT BOARD COPPER AREA 80 Thermal Resistance, θJA (°C/W) Figure 12 provides recommended PCB layouts for both the SO-8 (U) and the PowerPAD™ SO-8 (H) packages. Although the metal pad of the PowerPAD™ SO-8 (H) package is electrically connected to ground (pin 4), no current should flow in this pad. Do NOT use the exposed metal pad as a power ground connection or erratic operation will result. For lowest overall thermal resistance, it is best to solder the PowerPAD™ directly to a circuit board, as illustrated in Figure 13. Increasing the “heat sink” copper area improves heat dissipation. Figure 14 shows typical junction-to-ambient thermal resistance as a function of the PC board copper area. DRV103 (H) Power PAD Surface-Mount Package 1oz. copper 70 60 50 40 30 0 1 2 3 4 5 Copper Area (inches2) FIGURE 14. Heat Sink Thermal Resistance vs Circuit Board Copper Area. 150 (ref) POWER DISSIPATION 95 x 95 DRV103(H) Package C-C 215 (ref) 153 158 273 277 DRV103 power dissipation depends on power supply, signal, and load conditions. Power dissipation (PD) is equal to the product of output current times the voltage across the conducting DMOS transistor times the duty cycle. Using the lowest possible duty cycle necessary to assure the required hold force can minimize power dissipation in both the load and in the DRV103. For low current, the output DMOS transistor onresistance is 0.5Ω, increasing to 0.6Ω at high output current. At very high oscillator frequencies, the energy in the DRV103’s linear rise and fall times can become significant and cause an increase in PD. 60 (ref) 50 nom THERMAL PROTECTION 18 22 FIGURE 12. Recommended PCB Layout. DRV103 Die Pad-to-Board Solder Signal Trace Copper Pad Copper Traces Thermal Vias FIGURE 13. PowerPAD Heat Transfer. DRV103 SBVS029A Application Bulletin SBFA002 at www.ti.com, explains how to calculate or measure power dissipation with unusual signals and loads. Power dissipated in the DRV103 will cause its internal junction temperature to rise. The DRV103 has an on-chip thermal shutdown circuitry that protects the IC from damage. The thermal protection circuitry disables the output when the junction temperature reaches approximately +160°C, allowing the device to cool. When the junction temperature cools to approximately +140°C, the output circuitry is again enabled. Depending on load and signal conditions, the thermal protection circuit may cycle on and off. This limits the dissipation of the driver but may have an undesirable effect on the load. Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heat sink. For reliable operation, junction temperature should be limited to +125°C, maximum. To estimate the margin of safety in a complete design (including heat sink), increase the ambient temperature until the thermal protection is triggered. Use worst-case load and signal conditions. For good reliability, thermal protection should trigger more than 40°C above the maximum expected ambient condition of your application. This produces a junction temperature of 125°C at the maximum expected ambient condition. 11 The internal protection circuitry of the DRV103 was designed to protect against overload conditions. It was not intended to replace proper heat sinking. Continuously running the DRV103 into thermal shutdown will degrade reliability. To maintain junction temperature below 125°C, the heat sink selected must have a θHA less than 26.3°C/W. In other words, the heat sink temperature rise above ambient must be less than 52.6°C (26.3°C/W • 2W). HEAT SINKING Another variable to consider is natural convection versus forced convection air flow. Forced-air cooling by a small fan can lower θCA (θCH + θHA) dramatically. Most applications will not require a heat sink to assure that the maximum operating junction temperature (125°C) is not exceeded. However, junction temperature should be kept as low as possible for increased reliability. Junction temperature can be determined according to the equation: TJ = TA = PD = θJC = θCH = θHA = θJA = TJ = TA + PDθJA (1) where, θJA = θJC + θCH + θHA (2) Junction Temperature (°C) Ambient Temperature (°C) Power Dissipated (W) Junction-to-Case Thermal Resistance (°C/W) Case-to-Heat Sink Thermal Resistance (°C/W) Heat Sink-to-Ambient Thermal Resistance (°C/W) Junction-to-Air Thermal Resistance (°C/W) Using a heat sink significantly increases the maximum allowable power dissipation at a given ambient temperature. The answer to the question of selecting a heat sink lies in determining the power dissipated by the DRV103. For DC output into a purely resistive load, power dissipation is simply the load current times the voltage developed across the conducting output transistor times the duty cycle. Other loads are not as simple. For further insight on calculating power dissipation, refer to Application Bulletin SBFA002 at www.ti.com. Once power dissipation for an application is known, the proper heat sink can be selected. Heat Sink Selection Example A PowerPAD™ SO-8 (H) package is dissipating 2W. The maximum expected ambient temperature is 35°C. Find the proper heat sink to keep the junction temperature below 125°C. Combining Equations 1 and 2 gives: TJ = TA + PD(θJC + θCH + θHA) (3) TJ, TA, and PD are given. θJC is provided in the specification table, 16.7°C/W. θCH depends on heat sink size, area, and material used. A semiconductor’s package type and mounting can also affect θCH. A typical θCH for a soldered-in-place PowerPAD™ SO-8 (H) package is 2°C/W. Now we can solve for θHA: θ HA = θ HA = As mentioned earlier, once a heat sink has been selected, the complete design should be tested under worst-case load and signal conditions to ensure proper thermal protection. RFI/ EMI Any switching system can generate noise and interference by radiation or conduction. The DRV103 is designed with controlled slew rate current switching to reduce these effects. By slowing the rise and fall times of the output to 0.3µs, much lower switching noise is generated. Radiation from the DRV103-to-load wiring (the “antenna” effect) can be minimized by using “twisted pair” cable or by shielding. Good PCB ground planes are recommended for low noise and good heat dissipation. Refer to Bypassing section for notes on placement of the flyback diode. BYPASSING A 1µF tantalum bypass capacitor is adequate for uniform duty cycle control when switching loads of less than 0.5 amps. Larger bypass capacitors are required when switching high current loads. A 22µF tantalum capacitor is recommended for heavy-duty (3A) applications. It may also be desirable to run the DRV103 and the load on separate power supplies at high load currents. Near the absolute maximum supply voltage of 40V, bypassing is especially critical. In the event of a current overload, the DRV103 current limit responds in microseconds, dropping the load current to zero. With inadequate bypass, energy stored in the supply line inductance can lift the supply sufficiently to exceed voltage breakdown with catastrophic results. Place the flyback diode at the DRV103 end when driving long (inductive) cables to a remotely located load. This minimizes RFI / EMI and helps protect the output DMOS transistor from breakdown caused by dI/dt transients. Fast rectifier diodes such as epitaxial silicon or Schottky types are recommended as flyback diodes. TJ – TA – (θ JC + θ CH ) PD 125°C – 35°C – (16.7°C / W + 2°C / W ) 2W (4) θ HA = 26.3°C / W 12 DRV103 SBVS029A APPLICATIONS CIRCUITS +12V 5.6kΩ 22µF "Fault" HLMP-0156 1MΩ 7 DRV103 1.7V CT + 47µF Tantalum 8 Microsemi SK34MS 3A 40V Schottky + 6 Relay +VS OK 5 OUT Input 316kΩ Delay Adj Duty Cycle Adj 2 1 0.22µF TON (s) 47 22 10 4.7 2.2 10 5 2 1 0.5 4 GND Freq Adj CT (µF) 3 137kΩ 205kΩ FIGURE 15. Time Delay Relay Driver. +28V 22µF + Relay 24kΩ 6 +VS DRV103 OUT 8 3.9kΩ 5 Input Delay Adj Duty Cycle Adj 2 1 0.1µF 137kΩ Freq Adj GND 4 3 205kΩ Housing FIGURE 16. Remotely Operated Solenoid Valve or Relay. DRV103 SBVS029A 13 +12V 22µF + 3kΩ 6 +VS DRV103 8 TTLIN IRF4905 OUT 5 Input High = Load ON Low = Load OFF Duty Cycle Adj Delay Adj 2 Freq Adj 1 4 (1) LOAD 12V 70A 3 RPWM CD GND 10MΩ F ~ 500Hz NOTE: (1) Flyback diode required for inductive loads: IXYS DSE160-06A. FIGURE 17. High Power High Side Driver. +8V to +32V 2mA Microsemi SK34MS 3A 40V Schottky HLMP-Q156 7 6 Status OK TTL IN High = ON Low = OFF 8 22µF + “Fault” Linear Valve Actuator +VS OUT 5 DRV103 Delay Adj NC 2 Duty Cycle Adj 1 Freq Adj GND 4 3 205kΩ 1.3V ≅ 5% Duty Cycle 3.7V ≅ 95% Duty Cycle DATA DAC FIGURE 18. Linear Valve Driver. 14 DRV103 SBVS029A PACKAGE OPTION ADDENDUM www.ti.com 13-Aug-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) DRV103H ACTIVE SO PowerPAD DDA 8 75 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 DRV 103H DRV103H/2K5 ACTIVE SO PowerPAD DDA 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 DRV 103H DRV103U ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR DRV 103U DRV103U/2K5 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR DRV 103U DRV103UG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR DRV 103U (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of