DRV1101U/2K5

® DRV DRV1101 110 1 HIGH POWER DIFFERENTIAL LINE DRIVER FEATURES DESCRIPTION ● ● ● ● The DRV1101 is fixed gain differential line driver designed for very low distortion operation when driving DSL line transformers. It is designed for use as the upstream line driver for ADSL G.Lite, and as both upstream and downstream line drivers in CAP systems. Operating on a single 5V supply, the DRV1101 can supply up to 230mA peak output current. The output voltage can swing up to 9.5Vp-p on a single 5V supply. In ADSL G.Lite applications, DRV1101 can supply up to 10dBm average line power with a crest factor of 5.3 for a peak line power delivered of approximately 25dBm. It is packaged in a 8-lead SOIC. HIGH OUTPUT CURRENT: 230mA SINGLE SUPPLY OPERATION: 5V 10MHz BANDWIDTH: 6Vp-p into 15Ω VERY LOW THD AT HIGH POWER: –81dBc at 6Vp-p, 100kHz, 100Ω ● FIXED DIFFERENTIAL GAIN: 3V/V APPLICATIONS ● DSL TWISTED PAIR LINE DRIVER ● COMMUNICATIONS LINE DRIVER ● TWISTED-PAIR CABLE DRIVER +5V DRV1101 Out+ 4Ω In+ G = 3V/V In– 4Ω Out– Patent Pending Protection 100Ω 1:3.3 Transformer GND International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © SBWS009 1998 Burr-Brown Corporation PDS-1462A Printed in U.S.A. July, 1998 SPECIFICATIONS Typical at 25°C, VCM = VDD/2, VDD = +5.0V, unless otherwise specified. DRV1101U PARAMETER CONDITIONS AC PERFORMANCE –3dB Bandwidth Slew Rate Step Response Delay(2) Settling Time to 1%, Step Input Settling Time to 1%, Step Input Settling Time to 0.1%, Step Input Settling Time to 0.1%, Step Input THD, Total Harmonic Distortion f = 10kHz f = 10kHz f = 100kHz f = 100kHz Input Voltage Noise Input Current Noise INPUT Differential Input Resistance Differential Input Capacitance Common-Mode Input Resistance Common-Mode Input Capacitance Input Offset Voltage Input Bias Current Common-Mode Rejection Ratio Power Supply Rejection Ratio Input Common-Mode Voltage Range(4) OUTPUT Differential Output Offset, RTO Differential Output Offset Drift, RTO Differential Output Resistance Peak Current (Continuous) Differential Output Voltage Swing(5) Gain Gain Error POWER SUPPLY Operating Voltage Range Quiescent Current MIN TYP MAX UNITS RL = 15Ω, VO = 1Vp-p RL = 100Ω, VO = 1Vp-p RL = 15Ω, VO = 6Vp-p RL = 100Ω, VO = 6Vp-p RL = 100Ω, VO = 6Vp-p VO = 1Vp-p VO = 1Vp-p, RL = 100Ω VO = 6Vp-p, RL = 100Ω VO = 1Vp-p, RL = 100Ω VO = 6Vp-p, RL = 100Ω 24 42 17 23 100 25 0.12 0.13 0.30 0.32 MHz MHz MHz MHz V/µs ns µs µs µs µs RL = 100Ω, VO = 6Vp-p RL = 15Ω, VO = 6Vp-p RL = 100Ω, VO = 6Vp-p RL = 15Ω, VO = 6Vp-p f = 100kHz f = 100kHz –88 –85 –83 –71 30 0.5 dB dB dB dB nV/√Hz fA/√Hz 109 1 109 6 3 1 46 76 Ω pF Ω pF mV nA dB dB V Input Referred Input Referred –66 55 0.5 –40°C to +85°C RL = 15Ω RL = 1kΩ RL = 100Ω RL = 15Ω Fixed Gain, Differential 200 8.5 4.5 VDD = 5.0V TEMPERATURE RANGE Thermal Resistance, θJA 8-Pin SOIC VDD –0.5 ±10 30 0.16 230 9.8 9.7 7.0 3.1 5.0 25 –40 125 ±30 ±0.25 mV µV/°C Ω mA Vp-p Vp-p Vp-p V/V dB 5.5 38 V mA +85 °C °C/W NOTES: (1) Measurement Bandwidth = 500kHz. (2) Time from 50% point of input step to 50% point of output step. (3) For step input. (4) Output common-mode voltage follows input common-mode voltage; therefore, if input VCM = VDD/2, then output VCM = VDD/2. (5) THD = 1%. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® DRV1101 2 PIN CONFIGURATIONS ABSOLUTE MAXIMUM RATINGS Analog Inputs: Current .............................................. ±100mA, Momentary ±10mA, Continuous Voltage ....................................... GND –0.3V to VDD +0.2V Analog Outputs Short Circuit to Ground (+25°C) ..................... Momentary Analog Outputs Short Circuit to VDD (+25°C) ........................... Momentary VDD to GND .............................................................................. –0.3V to 6V Junction Temperature ................................................................... +150°C Storage Temperature Range .......................................... –40°C to +125°C Lead Temperature (soldering, 3s) ................................................. +260°C Power Dissipation .............................. (See Thermal/Analysis Discussion) Top View GND 1 8 Out– In+ 2 7 VDD (+5V) In– 3 6 VDD (+5V) GND 4 5 Out+ PACKAGE /ORDERING INFORMATION +5V 6 In+ In– 7 2 5 3 8 4 PRODUCT PACKAGE PACKAGE DRAWING NUMBER(1) DRV1101U SO-8 Surface Mount 182 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. Out+ Out– ELECTROSTATIC DISCHARGE SENSITIVITY 1 GND This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ® 3 DRV1101 APPLICATIONS INFORMATION INTERNAL BLOCK DIAGRAM The DRV1101 is a true differential input to differential output fixed gain amplifier. Operating on a single +5V power supply, it provides an internally fixed differential gain of +3V/V and a common-mode gain of +1V/V from the input to output. Fabricated on an advanced CMOS process, it offers very high input impedance along with a low impedance 230mA output drive. Figure 1 shows a simplified internal block diagram. Out+ VDD/2 VP Out– VP VDD/2 Load VP 0V VP Out+ FIGURE 2. DRV1101 Single Ended and Differential Output Waveforms. In+ Buffer Preamp example, the specifications show that on +5V supply the DRV1101 will deliver 6.0Vp-p into 15Ω. The peak load power under this condition is (6.0Vp-p/2)2/15Ω = 600mW. Out– In– POWER SUPPLY The DRV1101 is designed for operation on a single +5V supply. For loads > 200Ω, each output will swing rail to rail. This gives a peak-to-peak differential output swing that is approximately = 2 • VDD. For best distortion performance, the power supply should be decoupled to a good ground plane immediately adjacent to the package with a 0.1µF capacitor. In addition, a larger electrolytic supply decoupling capacitor (6.8µF) should be near the package but can be shared among multiple devices. FIGURE 1. Simplified DRV1101 Internal Block Diagram. The DRV1101 should be operated with the inputs centered at VDD / 2. This will place the output differential voltage centered at VDD / 2 for maximum swing and lowest distortion. Purely differential input signals will produce a purely differential output signal. A single ended input signal, applied to one input of the DRV1101, with the other input at a fixed voltage, will produce both a differential and common-mode output signal. This is an acceptable mode of operation when the DRV1101 is driving an element with good common-mode rejection (such as a transformer). DIGITAL SUBSCRIBER LINE APPLICATIONS The DRV1101 is designed for the high power, low distortion, requirements of a twisted pair driver in digital communications applications. These include ADSL (Asymmetrical Digital Subscriber Lines), and RADSL (Rate adaptive ADSL). Figure 3 shows a typical transformer coupled xDSL line driver configuration. DIFFERENTIAL OUTPUT VOLTAGE AND POWER Applying the balanced differential output voltage of the DRV1101 to a load between the outputs will produce a peakto-peak voltage swing that is twice the swing of each individual output. This is illustrated in Figure 2 where the common-mode voltage is VDD / 2. For a load connected between the outputs, the only voltage that matters is the differential voltage between the two outputs—the commonmode voltage does not produce any load current in this case. The DRV1101 is recommended as the upstream driver (CPE equipment) for ADSL G.Lite systems. These system require an rms line power of 10dBm with a voltage crest factor of 5.3 (crest factor is the ratio of peak to rms voltage). A voltage crest factor of 5.3 is equivalent to a power crest factor of about 15dB. Therefore, the peak power required at the line for G.Lite is 25dBm. Using the basic circuit shown in Figure 3, DRV1101 will provide this power to the line with very low distortion. The peak power that the DRV1101 can deliver into a differential load is VP2/RL. The peak voltage (Vp) equals 1/2 of the peak-to-peak voltage (Vp-p). Squaring 1/2 of the Vp-p and dividing by the load impedance will give the peak power. For ® DRV1101 4 +5V Protection Circuits DRV1101 Out+ 4Ω In+ Line Impedance 4Ω In– 100Ω Out– 1:3.3 Transformer Impedance Matching Resistors GND FIGURE 3. Typical Digital Subscriber Line Application. OUTPUT PROTECTION Figure 3 also shows overvoltage and short circuit protection elements that are commonly included in DSL applications. Overvoltage suppressors include diodes or MOV’s. The outputs of the DRV1101 can be momentarily shorted to ground or to the supply without damage. The outputs are not, however, designed for a continuous short to ground or the supply. To calculate the amplifier requirements for a DSL application: 1. Determine the average power that must be delivered to the line. The amplifier must deliver twice this power to account for the power dissipated in the series impedance matching resistors. Therefore, add 3dB to the line power. This is the average power delivered at the output of the amplifier. For ADSL G.Lite (as of June 1998), the average line power is 10dBm. Adding 3dB results in an average power at the amplifier output of 13dBm. POWER DISSIPATION AND THERMAL ANALYSIS The total internal power dissipation of the DRV1101 is the sum of a fixed overhead power that is independent of the load plus the power dissipated internally to deliver the average load power. The total internal power dissipation determines the internal temperature rise when in operation. For DSL applications with high crest factors, such as ADSL, the average load power delivered is much lower than the peak power required. For practical purposes, this means that internal temperature rise is not an issue for the DRV1101 in high-crest factor DSL applications. With a +5V supply, the DRV1101’s typical fixed overhead current of 22mA (out of total no-load supply current of 29mA) creates a fixed overhead power dissipation of 110mW. The load dependent power dissipation of the DRV1101 when delivering an output voltage Vrms to a load RL is: 2. Next add the power crest factor needed for the line code used. The power crest factor for ADSL is 15dB which means that the peak power (PPEAK) needed at the amplifier output is 28dBm (13dBm +15dB). 28dBm is 631mW. 3. The DRV1101 peak output voltage is calculated by the formula: VPEAK = (PPEAK • RL)1/2 where RL is the load impedance that the DRV1101 must drive. For ADSL Lite, using the circuit shown in Figure 3, VPEAK = (PPEAK • RL)1/2 = (.631W x 17Ω)1/2 = 3.3V. The peak-to-peak voltage out of the DRV1101 is 2 x 3.3V = 6.6V. 4. The transformer turns ratio can be changed to keep the required output voltage and current within the range of the DRV1101. The line impedance (RLINE) is 100Ω for ADSL. The impedance that is reflected to the DRV1101 side of the transformer is RLINE/(turns ratio)2. For best power transfer, the total of the impedance matching resistors should equal the reflected impedance. Thus, for the circuit shown in Figure 3, the reflected impedance is 100Ω/(3.4)2 = 8.6Ω. With two impedance matching resistors of 4Ω each and about 0.5Ω transformer resistance, the total load impedance is about (8.6Ω + 4Ω + 4Ω + 0.5Ω) = 17Ω. P = (VDD – Vrms) • (Vrms/RL) The internal power dissipation will reach a maximum when Vrms is equal to VDD /2. For a sinusoidal output, this corresponds to an output Vp-p = 1.41 • VDD. As an example, compute the power and junction temperature under a worst case condition with VDD = +5V and Vrms = 2.5V into a 20Ω differential load. The total internal power dissipation would be: (110mW) + (5V – 2.5V) • (2.5V/20Ω) = 423mW Fixed Load Related ® 5 DRV1101 INPUT INTERFACE CIRCUITS DRV1101 is designed for operation with a differential input centered at VDD /2. Signals that do not require DC coupling may be connected as shown in Figure 5 through blocking caps to a midpoint reference developed through resistor dividers from the supply voltage. The 1MΩ bias resistors determine four performance requirements. To compute the internal junction temperature, this power is multiplied by the junction to ambient thermal impedance (to get the temperature rise above ambient) then added to the ambient temperature. Using the specified maximum ambient temperature of +85°C, the junction temperature for the DRV1101 in an SO-8 package under these worst case conditions will be: • They bias the inputs at the supply midpoint. TJ = 85°C + 0.423W • 125°C/W = 138°C • They provide a DC bias current path for the input of the DRV1101. The internal junction temperature should, in all cases, be limited to < 150°C. For a maximum ambient temperature of +85°C, this limits the internal temperature rise to less than 65°C. Figure 4 shows the temperature rise from ambient to junction for loads of 15Ω and 100Ω. • They set the AC input impedance of the circuit to approximately 1MΩ. • They set the low cutoff frequency along with CB. The bias resistors maybe set to a lower level if a lower input impedance is desired. INTERNAL TEMPERATURE RISE OF DRV1101 5V 90 80 100kΩ Limit at 85°C Ambient Temperature Rise 70 60 RL = 15Ω 0.01µF 100kΩ 50 40 1MΩ CB 30 V1 20 RL = 100Ω 10 1MΩ 0 0 0.5 1 1.5 2 2.5 3 V2 3.5 CB Load Voltage (rms) FIGURE 4. Junction Temperature Rise From Ambient for the DRV1101U. FIGURE 5. AC-Coupled Differential Input Interface. ® DRV1101 6 RL PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) DRV1101U ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR DRV 1101U (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of