DRV603
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SLOS617C – JANUARY 2009 – REVISED NOVEMBER 2009
DirectPath™, 3-VRMS Line Driver With Adjustable Gain
Check for Samples: DRV603
FEATURES
DESCRIPTION
• DirectPath™
– Eliminates Pop/Clicks
– Eliminates Output DC-Blocking Capacitors
– Provides Flat Frequency Response 20
Hz–20 kHz
• Low Noise and THD
– SNR > 109 dB
– Typical Vn < 7 μVms
– THD+N < 0.002%
• Output Voltage Into 2.5-kΩ Load
– 2 Vrms With 3.3-V Supply Voltage
– 3 Vrms With 5-V Supply Voltage
• Differential Input
• External Undervoltage Mute
The DRV603PW is a 3-VRMS pop-free stereo line
driver designed to allow the removal of the output
dc-blocking capacitors for reduced component count
and cost. The device is ideal for single-supply
electronics where size and cost are critical design
parameters.
1
234
Using the DRV603 in audio products can reduce
component count considerably compared to
traditional methods of generating a 3-Vrms output. The
DRV603 does not require a power supply greater
than 5 V to generate its 8.5-Vpp output, nor does it
require a split-rail power supply. The DRV603
integrates its own charge pump to generate a
negative supply rail that provides a clean, pop-free
ground biased 3-Vrms output.
APPLICATIONS
•
•
•
•
PDP / LCD TV
Blu-ray Disc™, DVD Players
Home Theater in a Box
Set-Top Boxes
DAC
RIGHT
+
+
The DRV603 is available in a 14-pin TSSOP.
If the low noise and trimmed dc-offset and external
undervoltage mute function are not beneficial in the
application, TI recommends the footprint compatible
DRV602.
DRV603
DAC
Designed
using
TI’s
patented
DirectPath™
technology, The DRV603 is capable of driving 3 Vrms
into a 2.5-kΩ load with 5-V supply voltage. The
device has differential inputs and uses external
gain-setting resistors to support a gain range of ±1
V/V to ±10 V/V, and line outputs that have ±8 kV IEC
ESD protection. The DRV603 (occasionally referred
to as the ‘603) has built-in shutdown control for
pop-free on/off control. The DRV603 has an external
and internal undervoltage detector that mutes the
output.
LEFT
-
1
2
3
4
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DirectPath is a trademark of Texas Instruments.
Blu-ray Disc is a trademark of Blu-ray Disc Association.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
DRV603
SLOS617C – JANUARY 2009 – REVISED NOVEMBER 2009
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION (1)
TA
–40°C to 85°C
(1)
PACKAGE
TRANSPORT MEDIA, QUANTITY
DRV603PW
RAIL, 90
Tape and reel, 2000
DRV603PWR
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range
Supply voltage, VDD to GND
VI
Input voltage
RL
Minimum load impedance
VALUE
UNIT
–0.3 to 5.5
V
VSS – 0.3 to VDD + 0.3
V
> 600
Ω
–0.3 to VDD +0.3
V
TJ
EN to GND
Maximum operating junction temperature range
–40 to 150
°C
Tstg
Storage temperature range
–40 to 150
°C
ESD
Electrostatic discharge, IEC ESD
±8
kV
(1)
OUTL, OUTR
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATINGS
(1)
(2)
PACKAGE
RθJC (°C/W)
RθJA (°C/W)
POWER RATING (1)
AT TA ≤ 25°C
POWER RATING (1)
AT TA ≤ 70°C
TSSOP-14 (PW)
35
115 (2)
870 mW
348 mW
Power rating is determined with a junction temperature of 125°C. This is the point where performance starts to degrade and long-term
reliability starts to be reduced. Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C
for best performance and reliability.
These data were taken with the JEDEC high-K test printed circuit board (PCB). For the JEDEC low-K test PCB, the RθJA is 185°C/W.
RECOMMENDED OPERATING CONDITIONS
VDD
Supply voltage
DC supply voltage
VIH
High-level input voltage
EN
VIL
Low-level input voltage
EN
TA
Operating free-air temperature
2
MIN
NOM
MAX
3
3.3
5.5
60
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V
% of VDD
40
0
UNIT
% of VDD
70
°C
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ELECTRICAL CHARACTERISTICS
TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
|VOS|
Output offset voltage
VDD = 3 V to 5 V, input grounded, unity gain
1
PSRR
Power-supply rejection ratio
VDD = 3 V to 5 V
mV
VOH
High-level output voltage
VDD = 3.3 V, RL = 2.5 kΩ
VOL
Low-level output voltage
VDD = 3.3 V, RL = 2.5 kΩ
–3.05
V
|IIH|
High-level input current (EN)
VDD = 5 V, VI = VDD
1
µA
|IIL|
Low-level input current (EN)
VDD = 5 V, VI = 0 V
1
µA
IDD
Supply current
88
dB
3.1
VDD = 3.3 V, no load, EN = VDD
V
11
VDD = 5 V, no load, EN = VDD
12.5
mA
Shutdown mode, VDD = 3 V to 5 V
1
OPERATING CHARACTERISTICS
VDD = 3.3 V , TA = 25°C, RL = 2.5 kΩ, C(PUMP) = C(PVSS) = 1 µF , CIN = 10 µF, RIN = 10 kΩ, Rfb = 20 kΩ (unless otherwise
noted)
PARAMETER
VO
Output voltage (outputs in phase)
TEST CONDITIONS
2.05
THD = 1%, VDD = 5 V, f = 1 kHz
3.01
THD = 1%, VDD = 5 V, f = 1 kHz, RL = 100 kΩ
THD+N
MIN
THD = 1%, VDD = 3.3 V, f = 1 kHz
TYP MAX
UNIT
Vrms
3.1
Total harmonic distortion plus noise
VO = 2 Vrms, f = 1 kHz
0.001%
Crosstalk
VO = 2 Vrms, f = 1 kHz
–100
dB
IO
Maximum output current
VDD = 3.3 V
20
mA
RIN
Input resistor range
Rfb
Feedback resistor range
1
10
47
4.7
20
100
Slew rate
kΩ
kΩ
4.5
Maximum capacitive load
V/μs
220
pF
μVrms
VN
Noise output voltage
BW = 20 Hz to 22 kHz, A-weighted
6
SNR
Signal-to-noise ratio
VO = 3 Vrms, THD+N = 0.1%, BW = 22 kHz,
A-weighted
GBW
Unity-gain bandwidth
AVO
Open-loop voltage gain
150
dB
Vuvp
External undervoltage detection
1.25
V
IHys
External undervoltage detection
hysteresis current
5
μA
fcp
Charge pump frequency
112
dB
8
225
450
MHz
675
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3
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SLOS617C – JANUARY 2009 – REVISED NOVEMBER 2009
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PW PACKAGE
(TOP VIEW)
+INR
1
14
+IN
-INR
2
13
-INL
OUTR
3
12
OUTL
11
UVP
External
Under
Voltage
Detector
SGND
4
EN
5
10
PGND
PVSS
6
9
PVDD
8
CP
CN
Charge Pump
7
PIN FUNCTIONS
PIN
NAME
NO.
I/O (1)
DESCRIPTION
+INR
1
I
Right-channel OPAMP positive input
–INR
2
I
Right-channel OPAMP negative input
OUTR
3
O
Right-channel OPAMP output
SGND
4
P
Signal ground
EN
5
I
Enable input, active-high
PVSS
6
P
Supply voltage
CN
7
I/O
Charge-pump flying capacitor negative terminal
CP
8
I/O
Charge-pump flying capacitor positive terminal
PVDD
9
P
Positive supply
PGND
10
P
Power ground
UVP
11
I
Undervoltage protection input
OUTL
12
O
Left-channel OPAMP output
–INL
13
I
Left-channel OPAMP negative input
+INL
14
I
Left-channel OPAMP positive input
(1)
4
I = input, O = output, P = power
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FUNCTIONAL BLOCK DIAGRAM
+INL
-INL
+INR
Line
Driver
Line
Driver
OUTL
OUTR
UVP
SGND
Click&Pop
Suppression
Short Circuit
Protection
EN
PVSS
-INR
PGND
Bias
Circuitry
CN
PVDD
CP
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TYPICAL CHARACTERISTICS
VDD = 3.3 V , TA = 25°C, RL = 2.5 kΩ, C(PUMP) = C(VSS) = 1 µF , CIN = 10 µF, RIN = 10 kΩ, Rfb = 20 kΩ (unless otherwise noted)
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT VOLTAGE
VDD = 3.3 V, RL = 100 kΩ, f = 1 kHz
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT VOLTAGE
VDD = 5 V, RL = 100 kΩ, f = 1 kHz
10
THD+N - Total Harmonic Distortion+Noise - %
THD+N - Total Harmonic Distortion+Noise - %
10
1
0.1
0.01
0.001
0.0001
100m
200m 300m 500m 800m
2
VO - Output Voltage - V
3
0.1
0.01
0.001
0.0001
100m
4 5
500m 800m
2
VO - Output Voltage - V
Figure 2.
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT VOLTAGE
VDD = 3.3 V, RL = 2.5 kΩ, f = 1 kHz
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT VOLTAGE
VDD = 5 V, RL = 600 Ω, f = 1 kHz
3
4 5
3
4 5
10
THD+N - Total Harmonic Distortion+Noise - %
1
0.1
0.01
0.001
0.0001
100m
200m
500m 800m
2
VO - Output Voltage - V
3
4 5
1
0.1
0.01
0.001
0.0001
100m
Figure 3.
6
200m
Figure 1.
10
THD+N - Total Harmonic Distortion+Noise - %
1
200m
500m 800m
2
VO - Output Voltage - V
Figure 4.
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TYPICAL CHARACTERISTICS (continued)
VDD = 3.3 V , TA = 25°C, RL = 2.5 kΩ, C(PUMP) = C(VSS) = 1 µF , CIN = 10 µF, RIN = 10 kΩ, Rfb = 20 kΩ (unless otherwise noted)
TOTAL HARMONIC DISTORTION+NOISE
vs
FREQUENCY
VDD = 3.3 V, RL = 2.5 kΩ, VO = 2 Vrms
TOTAL HARMONIC DISTORTION+NOISE
vs
FREQUENCY
VDD = 5 V, RL = 100 kΩ, VO = 2 Vrms
10
THD+N - Total Harmonic Distortion+Noise - %
THD+N - Total Harmonic Distortion+Noise - %
10
1
0.1
0.01
0.001
0.0001
20
50
100 200 500 1k 2k
f - Frequency - Hz
5k
10k 20k
1
0.1
0.01
0.001
0.0001
20
50
100 200 500 1k 2k
f - Frequency - Hz
Figure 5.
Figure 6.
PHASE
vs
FREQUENCY
VDD = 5 V, RL = 100 kΩ, VO = 2 Vrms
GAIN
vs
FREQUENCY
VDD = 5 V, RL = 100 kΩ, VO = 2 Vrms
5k
10k 20k
+10
+150
+9
+8
+100
+7
Gain - dBV
Phase - deg
+50
+0
-50
+6
+5
+4
+3
-100
+2
+1
-150
20
50 100
500 1k 2k 5k 10k
f - Frequency - Hz
50k
200k
0
20
50 100
Figure 7.
500 1k 2k 5k 10k
f - Frequency - Hz
50k
200k
Figure 8.
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TYPICAL CHARACTERISTICS (continued)
VDD = 3.3 V , TA = 25°C, RL = 2.5 kΩ, C(PUMP) = C(VSS) = 1 µF , CIN = 10 µF, RIN = 10 kΩ, Rfb = 20 kΩ (unless otherwise noted)
FFT
vs
FREQUENCY
VDD = 5 V, RL = 100 kΩ, VO = 3 Vrms (-60 dB)
QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
+0
14m
No Load,
VI = 0 V
-20
Quiescent Current - A
12m
FFT - dBr
-40
-60
-80
-100
10m
8m
6m
4m
-120
2m
0
-0
-140
0
5k
10k
15k
20k
f - Frequency - Hz
Figure 9.
8
+1
+4
+2
+3
VDD - Supply Voltage - V
+5
Figure 10.
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SLOS617C – JANUARY 2009 – REVISED NOVEMBER 2009
APPLICATION INFORMATION
LINE DRIVER AMPLIFIERS
Single-supply line-driver amplifiers typically require dc-blocking capacitors. The top drawing in Figure 11
illustrates the conventional line-driver amplifier connection to the load and output signal.
DC blocking capacitors are often large in value, and a mute circuit is needed during power up to minimize click
and pop. The output capacitor and mute circuit consume PCB area and increase cost of assembly, and can
reduce the fidelity of the audio output signal.
9-12 V
Conventional Solution
VDD
+
+
OPAMP
Mute Circuit
Co
+
Output
VDD/2
GND
Enable
5V
DirectPath
DRV603 Solution
VDD
Mute Circuit
+
DRV603
Output
GND
VSS
Enable
Figure 11. Conventional and DirectPath Line Driver
The DirectPath™ amplifier architecture operates from a single supply but makes use of an internal charge pump
to provide a negative voltage rail.
Combining the user-provided positive rail and the negative rail generated by the IC, the device operates in what
is effectively a split supply mode.
The output voltages are now centered at zero volts with the capability to swing to the positive rail or negative rail.
Combining this with the built-in click and pop reduction circuit, the DirectPath™ amplifier requires no output dc
blocking capacitors.
The bottom block diagram and waveform of Figure 11 illustrate the ground-referenced line-driver architecture.
This is the architecture of the DRV603.
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CHARGE PUMP FLYING CAPACITOR AND PVSS CAPACITOR
The charge pump flying capacitor serves to transfer charge during the generation of the negative supply voltage.
The PVSS capacitor must be at least equal to the charge pump capacitor in order to allow maximum charge
transfer. Low-ESR capacitors are an ideal selection, and a value of 1 μF is typical. Capacitor values that are
smaller than 1 μF can be used, but the maximum output voltage may be reduced and the device may not
operate to specifications.
DECOUPLING CAPACITORS
The DRV603 is a DirectPath™ line-driver amplifier that requires adequate power supply decoupling to ensure
that the noise and total harmonic distortion (THD) are low. A good low equivalent-series-resistance (ESR)
ceramic capacitor, typically 1 μF, placed as close as possible to the device VDD lead works best. Placing this
decoupling capacitor close to the DRV603 is important for the performance of the amplifier. For filtering
lower-frequency noise signals, a 10-μF or greater capacitor placed near the audio power amplifier would also
help, but it is not required in most applications because of the high PSRR of this device.
GAIN-SETTING RESISTOR RANGES
The gain-setting resistors, RIN and Rfb, must be chosen so that noise, stability, and input capacitor size of the
DRV603 are kept within acceptable limits. Voltage gain is defined as Rfb divided by RIN.
Selecting values that are too low demands a large input ac-coupling capacitor, CIN. Selecting values that are too
high increases the noise of the amplifier. Table 1 lists the recommended resistor values for different gain
settings.
Table 1. Recommended Resistor Values
INPUT RESISTOR
VALUE, RIN
FEEDBACK RESISTOR
VALUE, Rfb
22 kΩ
22 kΩ
1 V/V
–1 V/V
2 V/V
15 kΩ
30 kΩ
1.5 V/V
–1.5 V/V
2.5 V/V
33 kΩ
68 kΩ
2.1 V/V
–2.1 V/V
3.1 V/V
10 kΩ
100 kΩ
10 V/V
–10 V/V
11 V/V
CIN
DIFFERENTIAL INPUT
GAIN
INVERTING INPUT GAIN
CIN
RIN
NONINVERTING INPUT
GAIN
RIN
-IN
-IN
RFB
RFB
-
Differential
Input
Inverting
+
+
+IN
CIN
RFB
RIN
Cx
RIN
RFB
-
Non
Inverting
+
+IN
CIN
Rx
Figure 12. Differential, Inverting and Non-Inverting Gain Configurations
10
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INPUT-BLOCKING CAPACITORS
DC input-blocking capacitors are required to be added in series with the audio signal into the input pins of the
DRV603. These capacitors block the dc portion of the audio source and allow the DRV603 inputs to be properly
biased to provide maximum performance.
These capacitors form a high-pass filter with the input resistor, RIN. The cutoff frequency is calculated using
Equation 1. For this calculation, the capacitance used is the input-blocking capacitor and the resistance is the
input resistor chosen from Table 1. Then the frequency and/or capacitance can be determined when one of the
two values is given.
1
1
fc IN +
or C IN + 2p fc R
2p RIN C IN
IN IN
(1)
USING THE DRV603 AS A SECOND-ORDER FILTER
Several audio DACs used today require an external low-pass filter to remove out-of-band noise. This is possible
with the DRV603, as it can be used like a standard OPAMP. Several filter topologies can be implemented, both
single-ended and differential. In Figure 13 , a multi-feedback (MFB) with differential input and single-ended input
is shown.
An ac-coupling capacitor to remove dc content from the source is shown; it serves to block any dc content from
the source and lowers the dc-gain to 1, helping reducing the output dc-offset to minimum.
The component values can be calculated with the help of the TI FilterPro™ program available on the TI website
at:
http://focus.ti.com/docs/toolsw/folders/print/filterpro.html
Inverting Input
Differential Input
R2
R2
C3
R1
C3
C1
R3
R3
R1
C1
-IN
-IN
DRV603
+
C2
DRV603
+
C2
+IN
C3
R1
R3
C1
R2
Figure 13. Second-Order Active Low-Pass Filter
The resistor values should have a low value for obtaining low noise, but should also have a high enough value to
get a small size ac-coupling capacitor. Using 5.6 kΩ for the resistors, C1 = 220 pF, and C2 = 470 pF, a DNR of
112 dB can be achieved with a 10-μF input ac-coupling capacitor.
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POP-FREE POWER UP
Pop-free power up is ensured by keeping the SD (shutdown pin) low during power-supply ramp up and ramp
down. The SD pin should be kept low until the input ac-coupling capacitors are fully charged before asserting the
SD pin high to achieve pop-less power up. Figure 14 illustrates the preferred sequence.
Supply
Enable
Supply Ramp
Time for ac-coupling
capacitors to charge
Figure 14. Power-Up Sequence
VSUP_MO
EXTERNAL UNDERVOLTAGE DETECTION
External undervoltage detection can be used to
mute/shut down the DRV603 before an input device
can generate a pop.
The shutdown threshold at the UVP pin is 1.25 V.
The user selects a resistor divider to obtain the
shutdown threshold and hysteresis for the specific
application. The thresholds can be determined as
follows:
R11
R13
UVP pin 11
Cy
R12
VUVP = 1.25 V × (R11 + R12) / R12
Hysteresis = 5 μA × R13 × (R11 + R12) / R12
with the condition R13 >> R11//R12.
For example, to obtain VUVP = 5 V and 1-V
hysteresis, R11 = 3 kΩ, R12 = 1 kΩ and R13 = 50
kΩ.
CAPACITIVE LOAD
The DRV603 has the ability to drive a high capacitive load up to 220 pF directly. Higher capacitive loads can be
accepted by adding a series resistor of 47 Ω or larger.
LAYOUT RECOMMENDATIONS
A proposed layout for the DRV603 can be seen in the DRV603EVM User's Guide (SLOU248), and the Gerber
files can be downloaded from http://focus.ti.com/docs/toolsw/folders/print/drv603evm.html. To access this
information, open the DRV603 product folder and look in the Tools and Software folder.
GAIN-SETTING RESISTORS
The gain-setting resistors, RIN and Rfb, must be placed close to the input pins to minimize capacitive loading on
these input pins and to ensure maximum stability of the DRV603. For the recommended PCB layout, see the
DRV603EVM user's guide (SLOU248).
12
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APPLICATION CIRCUIT
LEFT
OUTPUT
R12
5 V Supply
R11
R2
Linear Low Drop
Regulator
10 mF
+
LEFT
INPUT
System Supply
C3
R1
C3
R1
C2
R3
C1
1mF
CP
PVDD
PGND
UVP
OUTL
Short Circuit
Protection
C1
DRV603
Line
Driver
Bias
Circuitry
CN
PVSS
-INR
OUTR
C1
+INR
R2
SGND
Line
Driver
Click and Pop
Suppression
1mF
EN
R2
-INL
+
R3
+INL
-
+
RIGHT
INPUT
C3
R1
C3
R1
C2
R3
R3
C1
R2
RIGHT
OUTPUT
1mF
R1 = 5.6 kΩ, R2 = 5.6 kΩ, R3 = 5.6 kΩ, C1 = 220 pF, C2 = 470 pF
Differential-input, single-ended output, second-order filter
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REVISION HISTORY
NOTE: Page numbers of current version may differ from previous versions.
Changes from Revision A (February 2009) to Revision B
Page
•
Changed Crosstalk spec from –80dB to –100dB ................................................................................................................. 3
•
Added missing voltage value (1.25V) to External Undervoltage Detection threshold equation. ........................................ 12
14
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Changes from Revision B (October 2009) to Revision C
Page
•
Changed maximum operating junction temperature ............................................................................................................. 2
•
In Dissipation Ratings section, changed θJx to RθJx in three places and 185°C to 185°C/W ............................................... 2
•
Corrected reference to Figure 11 .......................................................................................................................................... 9
•
Added cross-reference to Figure 13 ................................................................................................................................... 11
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
DRV603PW
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
DRV603
DRV603PWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
DRV603
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
