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DRV612
SLOS690C – DECEMBER 2010 – REVISED JULY 2016
DRV612 2-Vrms DirectPath™ Line Driver With Programmable-Fixed Gain
1 Features
3 Description
•
The DRV612 is a single-ended, 2-Vrms stereo line
driver designed to reduce component count, board
space, and cost. It is ideal for single-supply
electronics where size and cost are critical design
parameters.
1
•
•
•
•
•
•
•
DirectPath™
– Eliminates Pops and Clicks
– Eliminates Output DC-Blocking Capacitors
– 3-V to 3.6-V Supply Voltage
Low Noise and THD
– SNR > 105 dB at –1× Gain
– Vn < 12 μVms, 20 Hz to 20 kHz at –1× Gain
(Typical)
– THD+N < 0.003% at 10-kΩ Load and –1× Gain
2-Vrms Output Voltage Into 600-Ω Load
Single-Ended Input and Output
Programmable Gain Select Reduces Component
Count
– 13× Gain Values
Active Mute With More Than 80-dB Attenuation
Short-Circuit and Thermal Protection
±8-kV HBM ESD-Protected Outputs
2 Applications
•
•
•
•
The device has fixed-gain single-ended inputs with a
gain-select pin. Using a single resistor on this pin, the
designer can choose from 13 internal programmable
gain settings to match the line driver with the codec
output level. The device also reduces the component
count and board space.
The DRV612 is available in a 14-pin TSSOP and 16pin VQFN. For a footprint-compatible stereo
headphone driver, see the TPA6139A2.
Functional Block Diagram
±
The DRV612 device is designed using TI’s patented
DirectPath technology, which integrates a charge
pump to generate a negative supply rail that provides
a clean, pop-free ground-biased output. The DRV612
is capable of driving 2 Vms into a 600-Ω load.
DirectPath technology also allows the removal of the
costly output dc-blocking capacitors.
Line outputs have ±8-kV HBM ESD protection,
enabling a simple ESD protection circuit. The
DRV612 has built-in active mute control with more
that 80-dB attenuation for pop-free mute on/off
control.
PDP and LCD TVs
DVD Players
Mini and Micro Combo Systems
Soundcards
DAC
The DRV612 does not require a power supply greater
than 3.3 V to generate its 5.6-VPP output, nor does it
require a split-rail power supply.
Device Information(1)
LEFT
PART NUMBER
+
Programmable
SOC
DAC
Gain
-1x to -10x
DRV612
DRV612
±
Line Driver
RIGHT
PACKAGE
BODY SIZE (NOM)
TSSOP (14)
5.00 mm × 4.40 mm
VQFN (16)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
+
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
DRV612
SLOS690C – DECEMBER 2010 – REVISED JULY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
4
4
4
4
5
5
6
7
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Electrical Characteristics, Line Driver .......................
Programmable Gain Settings....................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 8
Detailed Description .............................................. 9
9.1 Overview ................................................................... 9
9.2 Functional Block Diagram ......................................... 9
9.3 Feature Description................................................... 9
9.4 Device Functional Modes........................................ 10
10 Application and Implementation........................ 12
10.1 Application Information.......................................... 12
10.2 Typical Application ................................................ 13
11 Power Supply Recommendations ..................... 16
12 Layout................................................................... 16
12.1 Layout Guidelines ................................................. 16
12.2 Layout Examples................................................... 17
13 Device and Documentation Support ................. 18
13.1
13.2
13.3
13.4
13.5
13.6
13.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
18
18
18
18
18
18
18
14 Mechanical, Packaging, and Orderable
Information ........................................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (April 2011) to Revision C
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
•
Removed Ordering Information table, see POA at the end of the data sheet ...................................................................... 1
Changes from Revision A (February 2011) to Revision B
Page
•
Changed RIN = 10 kΩ, Rfb = 20 kΩ To Gain = -2V/V in the Typical Characteristics condition text ........................................ 7
•
Changed RIN = 10 kΩ, Rfb = 20 kΩ To Gain = -2V/V in the Typical Characteristics condition text ........................................ 8
Changes from Original (December 2010) to Revision A
Page
•
Added the QFN pinout drawing .............................................................................................................................................. 3
•
Added the QFN device to the Pin Functions table ................................................................................................................. 3
•
Changed minimum storage temperature from –40°C to –65°C ............................................................................................. 4
•
Changed the Gain resistor 2% tolerance values in the Programmable Gain Settings table for Gain Steps and Input
Impedance .............................................................................................................................................................................. 6
•
Changed Note 1 of the PROGRAMMABLE GAIN SETTINGS table From: If pin 12, GAIN, is left floating To: If the
GAIN pin is left floating ........................................................................................................................................................... 6
•
Changed From: CPUMP = C(VSS) = 10 µF To: CPUMP = C(VSS) = 1 µF in the Typical Characteristics condition text .................. 7
•
Changed From: CPUMP = C(VSS) = 10 µF To: CPUMP = C(VSS) = 1 µF in the Typical Characteristics condition text .................. 8
•
Changed the Gain_set RESISTOR values in Table 2.......................................................................................................... 14
•
Changed the Gain_set RESISTOR values in Table 3.......................................................................................................... 15
•
Removed references to DRV614 from the FOOTPRINT COMPATIBLE WITH TPA6139A2 section .................................. 16
2
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SLOS690C – DECEMBER 2010 – REVISED JULY 2016
5 Device Comparison Table
GAIN
INPUT OFFSET (±) (uV)
Vmax (V)
Vmin (V)
DRV603
Adjustable
1000
5.5
3
PACKAGE (PIN)
TSSOP (14)
DRV604
Adjustable
500
3.7
3
HTSSOP (28)
DRV612
Adjustable
1000
4
3
TSSOP (14), VQFN (16)
DRV632
Adjustable
1000
4
3
TSSOP (14)
6 Pin Configuration and Functions
PW Package
14-Pin TSSOP
Top View
5
10
VDD
NC
6
9
7
8
CP
NC
1
GND
2
GND
MUTE
12
OUT_R
11
GAIN
3
10
GND
4
9
VDD
ThermalPad
5
CN
OUT_L
-IN_R
VSS
NC
GND
13
11
14
4
VSS
Not to scale
8
GAIN
MUTE
7
OUT_R
12
CP
13
3
NC
2
GND
NC
OUT_L
-IN_L
-IN_R
15
14
6
1
CN
-IN_L
16
RGT Package
16-Pin VQFN
Top View
Not to scale
Pin Functions
PIN
NAME
TSSOP
VQFN
–IN_L
1
16
–IN_R
14
CN
6
CP
TYPE (1)
DESCRIPTION
I
Negative input, left channel
13
I
Negative input, right channel
6
I/O
Charge Pump flying capacitor negative connection
9
8
I/O
Charge Pump flying capacitor positive connection
GAIN
12
11
I
Gain set programming pin; connect a resistor to ground.
See Table 2 for recommended resistor values.
GND
3, 11
2, 3, 10
P
Ground
MUTE, active low
MUTE
4
4
I
7, 8
7, 14, 15
—
No internal connection
OUT_L
2
1
O
Output, left channel
OUT_R
13
12
O
Output, right channel
Thermal Pad
—
Thermal Pad
P
Connect to ground
VDD
10
9
P
Supply voltage, connect to positive supply
VSS
5
5
O
Change Pump negative supply voltage
NC
(1)
I = Input, O = Output, P = Power
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Input, VI
Voltage
Temperature
(1)
MIN
MAX
VSS – 0.3
VDD + 0.3
VDD to GND
–0.3
4
MUTE to GND
–0.3
VDD + 0.3
Maximum operating junction temperature, TJ
–40
150
Storage temperature, Tstg
–65
150
UNIT
V
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
UNIT
DRV612 in the PW Package
Electrostatic
discharge
V(ESD)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
All pins except Pins 2 and
13
±4000
Pins 2 and 13
±8000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
V
±1500
DRV612 in the RGT Package
Electrostatic
discharge
V(ESD)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
All pins except Pins 1 and
12
±4000
Pins 1 and 12
±8000
(2)
±1500
Charged-device model (CDM), per JEDEC specification JESD22-C101
(1)
(2)
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range unless otherwise noted
MIN
VDD
Supply voltage, DC
RL
Load resistance
VIL
NOM
MAX
3.6
UNIT
3
3.3
600
10000
V
Low-level input voltage, MUTE
38%
40%
43%
VDD
VIH
High-level input voltage, MUTE
57%
60%
66%
VDD
TA
Free-air temperature
0
25
85
Ω
°C
7.4 Thermal Information
DRV612
THERMAL METRIC (1)
PW (TSSOP)
RGT (VQFN)
14 PINS
16 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
130
52
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
49
71
°C/W
RθJB
Junction-to-board thermal resistance
63
26
°C/W
ψJT
Junction-to-top characterization parameter
3.6
3
°C/W
ψJB
Junction-to-board characterization parameter
62
26
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
VDD = 3.3 V, RLD = 5 kΩ, TA = 25°C, and charge pump (CCP) = 1 μF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
|VOS|
Output offset voltage
PSRR
Power-supply rejection ratio
VOH
High-level output voltage
VDD = 3.3 V
VOL
Low-level output voltage
VDD = 3.3 V
Vuvp_on
VDD, undervoltage detection
MIN
VDD = 3.3 V, input ac-coupled
70
TYP
MAX
0.5
1
80
UNIT
mV
dB
3.1
V
–3.05
2.8
V
V
Vuvp_hysteresis VDD, undervoltage detection, hysteresis
200
mV
FCP
Charge-pump switching frequency
350
kHz
|IIH|
High-level input current, MUTE
VDD = 3.3 V, VIH = VDD
1
|IIL|
Low-level input current, MUTE
VDD = 3.3 V, VIL = 0 V
1
I(VDD)
Supply current, no load
VDD, MUTE = 3.3 V
Supply current, MUTED
VDD = 3.3 V, MUTE = GND
TSD
Thermal shutdown
Thermal shutdown hysteresis
µA
µA
18
mA
18
mA
150
°C
15
°C
7.6 Electrical Characteristics, Line Driver
VDD = 3.3 V, RLOAD = 10 kΩ, TA = 25°C, charge pump (CCP) = 1 µF, and 1× gain select (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VO
Output voltage, outputs in phase
1% THD+N, f = 1 kHz, 10 -kΩ load
2.2
THD+N
Total harmonic distortion plus noise
f = 1 kHz, 10-kΩ load, VO = 2 Vrms
0.007%
SNR
Signal-to-noise ratio
A-weighted, AES17 filter, 2 Vrms ref
105
dB
DNR
Dynamic range
A-weighted, AES17 filter, 2 Vrms ref
105
dB
Vn
Noise voltage
A-weighted, AES17 filter
Zo
Output impedance when muted
MUTE = GND
Input-to-output attenuation when muted
1 Vrms, 1-kHz input
Slew rate
GBW
Ilimit
Unity-gain bandwidth
Crosstalk, line L-R and R-L
10-kΩ load, VO = 2 Vrms
Current limit
VDD = 3.3 V
Vrms
12
0.07
μV
1
80
dB
4.5
V/μs
8
MHz
–91
dB
25
mA
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7.7 Programmable Gain Settings
VDD = 3.3 V, Rload = 10 kΩ, TA = 25°C, Charge pump: CCP = 1 μF, 1× gain select (unless otherwise noted) (1) (2)
PARAMETER
R_Tol
Gain programming resistor tolerance
ΔAV
Gain matching
TEST CONDITIONS
249k or higher
Input impedance,
gain resistor 2% tolerance
(1)
(2)
6
TYP
MAX
UNIT
2%
Between left and right channels
Gain step tolerance
Gain steps,
gain resistor 2% tolerance
MIN
0.25
dB
0.1
dB
–2
82k5
–1
51k1
–1.5
34k8
–2.3
27k4
–2.5
20k5
–3
15k4
–3.5
11k5
–4
9k09
–5
7k50
–5.6
6k19
–6.4
5k11
–8.3
4k22
–10
249k or higher
37
82k5
55
51k1
44
34k8
33
27k4
31
20k5
28
15k4
24
11k5
22
9k09
18
7k50
17
6k19
15
5k11
12
4k22
10
V/V
kΩ
If the GAIN pin is left floating, an internal pullup sets the gain to –2×.
Gain setting is latched during power up.
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7.8 Typical Characteristics
VDD = 3.3 V, TA = 25°C, RL = 2.5 kΩ, CPUMP = C(VSS) = 1 µF, and Gain = –2 V/V (unless otherwise noted)
10
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
10
5
1
0.5
0.1
0.01
0.005
0.001
40m
100m
200m
500m
1
2
VO - Output Voltage - Vrms
4
Figure 1. THD+N vs Output Voltage 3.3 V, 10 kΩ, 1 kHz
5
1
0.5
0.1
0.01
0.005
0.001
40m
100m
200m
500m
1
2
VO - Output Voltage - Vrms
4
Figure 2. THD+N vs Output Voltage 3.3 V, 600-Ω Load, 1 kHz
+0
5
-10
1
-20
0.5
-30
Attenuation - dBr
THD+N - Total Harmonic Distortion + Noise - %
10
0.1
3.3 V, 5 kW, 2Vrms
-40
-50
-60
-70
0.01
Left to Right
-80
0.005
-90
Right to Left
0.001
20
50 100 200
500 1k 2k
5k
VO - Output Voltage - Vrms
20k
Blue: 10-µF ceramic AC-coupling capacitor.
Red: 10-µF electrolytic AC-coupling capacitor.
Figure 3. THD+N vs Frequency 3.3 V, 10-kΩ Load, 2 Vrms
-100
20
50
100 200
500 1k 2k
f - Frequency - Hz
5k 10k 20k
Blue: L to R
Red: R to L
Figure 4. Channel Separation 3.3 V, 5-kΩ Load, 2 Vrms
+22
+20
+18
+16
Gain - dBr
+14
+12
+10
+8
+6
+4
+2
-0
-2
20
50 100 200 500 1k 2k 5k 10k 20k 50k
f - Frequency - Hz
200k
Figure 5. Gain vs Frequency for the Different Gain Settings
Figure 6. Mute to Play
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Typical Characteristics (continued)
VDD = 3.3 V, TA = 25°C, RL = 2.5 kΩ, CPUMP = C(VSS) = 1 µF, and Gain = –2 V/V (unless otherwise noted)
Figure 7. Play to Mute
8 Parameter Measurement Information
All parameters are measured according to the conditions described in Specifications.
8
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9 Detailed Description
9.1 Overview
The DRV612 is a DirectPath stereo line driver that requires no output DC-blocking capacitors and is capable of
delivering 2 Vrms into a 600-Ω load. The device has built-in pop suppression circuitry to completely eliminate pop
noise during turn-on and turn-off. The amplifier outputs have short-circuit protection.
The DRV612 gain is controlled by an external resistors RGAIN, see Gain-Setting for recommended values.
The DRV612 operates from a single 3-V to 3.6-V supply, as it uses a built-in charge pump to generate a negative
voltage supply for the line driver.
9.2 Functional Block Diagram
Current
Limit
Left
GAIN
Control
De Pop
Current
Limit
Right
Charge Pump
Thermal
Limit
Power
Management
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9.3 Feature Description
9.3.1 Line Driver Amplifiers
Single-supply line driver amplifiers typically require DC-blocking capacitors. The top drawing in Figure 8
illustrates the conventional line driver amplifier connection to the load and output signal.
DC blocking capacitors are often large in value, and a mute circuit is needed during power up to minimize click
and pop. The output capacitor and mute circuit consume PCB area and increase cost of assembly, and can
reduce the fidelity of the audio output signal.
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Feature Description (continued)
9-12V
Conventional solution
VDD
+
Mute Circuit
Co
+
+
OPAMP
VDD/2
Output
±
GND
MUTE
3.3V
DRV612 Solution
DirectPath
VDD
±
DRV612
Output
GND
VSS
MUTE
Copyright © 2016, Texas Instruments Incorporated
Figure 8. Conventional and DirectPath Line Driver
The DirectPath amplifier architecture operates from a single supply but makes use of an internal charge pump to
provide a negative voltage rail.
Combining the user-provided positive rail and the negative rail generated by the IC, the device operates in what
is effectively a split supply mode.
The output voltages are now centered at zero volts with the capability to swing to the positive rail or negative rail.
Combining this with the built-in click- and pop-reduction circuit, the DirectPath amplifier requires no output dcblocking capacitors.
The bottom block diagram and waveform of Figure 8 illustrate the ground-referenced line-driver architecture. This
is the architecture of the DRV612.
9.4 Device Functional Modes
9.4.1 Internal Undervoltage Detection
The DRV612 contains an internal precision band-gap reference voltage and a comparator used to monitor the
supply voltage, VDD. The internal VDD monitor is set at 2.8 V with 200-mV hysteresis.
10
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Device Functional Modes (continued)
1.25 V
Bandgap
AMP Enable
VDD
Comparator
Internal VDD
Figure 9. UVP Internal Comparator
9.4.2 Pop-Free Power Up
Pop-free power up is ensured by keeping the MUTE pin low during power-supply ramp-up and ramp-down. The
pins should be kept low until the input ac-coupling capacitors are fully charged before asserting the MUTE pin
high, this way proper pre-charge of the ac-coupling is performed and pop-less power up is achieved. Figure 10
illustrates the preferred sequence.
Supply
Supply ramp
MUTE
_
Time for ac -coupling
capasitors to charge
Figure 10. Power-Up and Power-Down Sequence
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The DRV612 starts its operation by asserting the MUTE pin to logic 1. The device enters in mute mode when
pulling low MUTE pin. The charge pump generates a negative supply voltage. The charge pump flying capacitor
connected between CP and CN transfers charge to generate the negative supply voltage. The output voltages
are capable of positive and negative voltage swings and are centered close to 0 V, eliminating the need for
output capacitors. Input coupling capacitors block any dc bias from the audio source and ensure maximum
dynamic range.
This typical connection diagram highlights the required external components and system level connections for
proper operation of the device in popular use case. Any design variation can be supported by TI through
schematic and layout reviews. Visit e2e.ti.com for design assistance and join the audio amplifier discussion
forum for additional information.
10.1.1 Capacitive Load
The DRV612 has the ability to drive a high capacitive load up to 220 pF directly. Higher capacitive loads can be
accepted by adding a series resistor of 47 Ω or larger for the line driver output.
12
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10.2 Typical Application
2
IN_LEFT
U11
1
2
1 -IN_L
C11 2.2 µF
2
OUT_LEFT
-IN_R
OUT_L
OUT_R
4
MUTE
1
2
5
6
C13 1 µF
7
GND
GAIN
DRV612PW
3 GND
MUTE
VSS
GND
VDD
CN
CP
NC
NC
2
14
1
IN_RIGHT
C12 2.2 µF
13
OUT_RIGHT
12
1
2
11
R11
10
1
9
49 kŸ
2
C15 1 µF
GND
8
+3.3 V
1
C14 1 µF
-IN_R
VDD
9
GND
2
C25
1 µF
C23
1 µF
2
R21
49 kŸ
GND
GND
1
1
+3.3 V
1
2
5
10
2
MUTE
OUT_RIGHT
1
14
nc
GND
VSS
MUTE
GAIN
DRV612RGT
GND
12
CP
4
IN_RIGHT
2.2 µF
11
8
GND
GND
1
C22
OUT_R
nc
3
OUT_L
CN
2
7
1
OUT_LEFT
nc
16
-I N_L
U21
13
2
15
1
C21 2.2 µF
6
2
IN_LEFT
C24
1 µF
GND
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Figure 11. Single-Ended Input and Output, Gain Set to –1.5×
10.2.1 Design Requirements
Table 1 lists the design parameters for this application example.
Table 1. Typical Application Design Requirements
PARAMETER
VALUE
Input voltage supply
3 V to 3.6 V
Current
130 mA
Load impedance
32 Ω
10.2.2 Detailed Design Procedure
10.2.2.1 Component Selection
10.2.2.1.1 Charge Pump Flying Capacitor and VSS Capacitor
The charge-pump flying capacitor serves to transfer charge during the generation of the negative supply voltage.
The VSS capacitor must be at least equal to the charge pump capacitor in order to allow maximum charge
transfer. Low-ESR capacitors are an ideal selection, and a value of 1 μF is typical.
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10.2.2.1.2 Decoupling Capacitors
The DRV612 is a DirectPath line-driver amplifier that requires adequate power-supply decoupling to ensure that
the noise and total harmonic distortion (THD) are low. A good low equivalent-series-resistance (ESR) ceramic
capacitor, typically 1 μF, placed as close as possible to the device VDD lead works best. Placing this decoupling
capacitor close to the DRV612 is important for the performance of the amplifier. For filtering lower-frequency
noise signals, a 10-μF or greater capacitor placed near the audio power amplifier also helps, but it is not required
in most applications because of the high PSRR of this device.
10.2.2.1.3 Gain-Setting
The gain setting is programmed with the GAIN pin. Gain setting is latched during power on. Table 2 lists the gain
settings.
NOTE
If gain pin is left unconnected (open) default gain of –2× is selected.
Table 2. Gain Settings
Gain_set RESISTOR
GAIN
GAIN (dB)
INPUT RESISTANCE
249 kΩ or higher
–2×
6
37 kΩ
82k5
–1×
0
55 kΩ
51k1
–1.5×
3.5
44 kΩ
34k8
–2.3×
7.2
33 kΩ
27k4
–2.5×
8
31 kΩ
20k5
–3×
9.5
28 kΩ
15k4
–3.5×
10.9
24 kΩ
11k5
–4.0×
12
22 kΩ
9k09
–5×
14
18 kΩ
7k5
–5.6×
15
17 kΩ
6k19
–6.4×
16.1
15 kΩ
5k11
–8.3×
18.4
12 kΩ
4k22
–10×
20
10 kΩ
10.2.2.1.4 Input-Blocking Capacitors
DC input-blocking capacitors are required to be added in series with the audio signal into the input pins of the
DRV612. These capacitors block the dc portion of the audio source and allow the DRV612 inputs to be properly
biased to provide maximum performance. The input blocking capacitors also limit the dc gain to 1, limiting the dcoffset voltage at the output.
These capacitors form a high-pass filter with the input resistor, RIN. The cutoff frequency is calculated using
Equation 1. For this calculation, the capacitance used is the input-blocking capacitor and the resistance is the
input resistor chosen from Table 3. Then the frequency and/or capacitance can be determined when one of the
two values is given.
1
1
fcIN =
or CIN =
2pRIN CIN
2pfcIN RIN
(1)
For a fixed cutoff frequency of 2 Hz, the size of the input capacitance is shown in Table 3 with the capacitors
rounded up to nearest E6 values. For 20-Hz cutoff, simply divide the capacitor values with 10; for example, for
1× gain, 150 nF is needed.
14
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Table 3. Input Capacitor for Different Gain and Cutoff
Gain_set RESISTOR
GAIN (dB)
INPUT RESISTANCE
2-Hz CUTOFF
249 kΩ
–2× (6)
37 kΩ
2.2 µF
82k5
–1× (0)
55 kΩ
1.5 µF
51k1
–1.5× (3.5)
44 kΩ
2.2 µF
34k8
–2.3× (7.2)
33 kΩ
3.3 µF
27k4
–2.5× (8)
31 kΩ
3.3 µF
20k5
–3× (9.5)
28 kΩ
3.3 µF
15k4
–3.5× (10.9)
24 kΩ
3.3 µF
11k5
–4× (12)
22 kΩ
4.7 µF
9k09
–5× (14)
18 kΩ
4.7 µF
7k5
–5.6× (15)
17 kΩ
4.7 µF
6k19
–6.4× (16.1)
15 kΩ
6.8 µF
5k11
–8.3× (18.4)
12 kΩ
6.8 µF
4k22
–10× (20)
10 kΩ
10 µF
10.2.3 Application Curves
The characteristics of this design are shown in Table 4.
Table 4. Table of Graphs
FIGURE
THD+N vs Output Voltage 3.3 V, 10 kΩ, 1 kHz
Figure 1
THD+N vs Output Voltage 3.3 V, 600-Ω Load, 1 kHz
Figure 2
THD+N vs Frequency 3.3 V, 10-kΩ Load, 2 Vrms
Figure 3
Channel Separation 3.3 V, 5-kΩ Load, 2 Vrms
Figure 4
Gain vs Frequency for the Different Gain Settings
Figure 5
Mute to Play
Figure 6
Play to Mute
Figure 7
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11 Power Supply Recommendations
The device is designed to operate form an input voltage supply from 3 V to 3.6 V. Therefore, the output voltage
range of power supply should be within this range and well regulated. TI recommends placing decoupling
capacitors in every voltage source pin. Place these decoupling capacitors as close as possible to the DRV612.
12 Layout
12.1 Layout Guidelines
A proposed layout for the DRV612 can be seen in the DRV612EVM User's Guide, and the Gerber files can be
downloaded from focus.ti.com. To access this information, open the DRV612 product folder and look in the Tools
and Software folder.
Ground traces are recommended to be routed as a star ground to minimize hum interference. The VDD and VSS
decoupling capacitors and the charge-pump capacitors must be connected with short traces.
12.1.1 Footprint Compatible With TPA6139A2
The DRV612 stereo line driver is pin compatible with the headphone amplifier TPA6139A2. Therefore, a single
PCB layout can be used with stuffing options for different board configurations.
1
1
14
DRV612
TPA6139A2
14
Figure 12. DRV612 and TPA6139A2 Pin Compatibility
16
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12.2 Layout Examples
OUT_RIGHT
8
9
10
11
12
14
IN _RIGHT
13
GAIN
Decoupling capacitor
placed as close as
possible to the device
7
6
5
4
MUTE
3
1
IN _LEFT
2
DRV612
Decoupling capacitor
placed as close as
possible to the device
OUT_LEFT
Top Layer Ground Plane
Top Layer Traces
Pad to Top Layer Ground Plane
Via to Power Supply
Via to Bottom Layer Ground Plane
Figure 13. TSSOP Package Layout
OUT_RIGHT
Decoupling capacitor
placed as close as
possible to the device
12
IN_RIGHT
11
10
9
13
8
14
7
15
IN_LEFT
6
DRV612
16
2
3
5
4
Decoupling capacitor
placed as close as
possible to the device
MUTE
1
OUT_LEFT
Top Layer Ground Plane
Top Layer Traces
Pad to Top Layer Ground Plane
Thermal Pad
Via to Bottom Ground Plane
Via to Power Supply
Figure 14. VQFN Package Layout
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13 Device and Documentation Support
13.1 Device Support
13.1.1 Development Support
For development support, see the following:
TPA6139A2
13.2 Documentation Support
13.2.1 Related Documentation
For related documentation see the following:
DRV612EVM User's Guide (SLOU248)
13.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.5 Trademarks
DirectPath, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
18
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
DRV612PW
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
DRV612
DRV612PWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
DRV612
DRV612RGTR
ACTIVE
VQFN
RGT
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
D612
DRV612RGTT
ACTIVE
VQFN
RGT
16
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
D612
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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