DRV8231ADDAR

DRV8231A SLVSFZ8 – NOVEMBER 2021 DRV8231A 3.7-A Brushed DC Motor Driver with Integrated Current Sense and Regulation 1 Features 3 Description • • • The DRV8231A device is an integrated motor driver with N-channel H-bridge, charge pump, current sense feedback, current regulation, and protection circuitry. The charge pump improves efficiency by supporting N-channel MOSFET half bridges and 100% duty cycle driving. • • • • • • • N-channel H-bridge brushed DC motor driver 4.5-V to 33-V operating supply voltage range Pin-to-pin, RDS(on), voltage, and current sense/ regulation variants (external shunt resistor and integrated current mirror) – DRV8870: 6.5-V to 45-V, 565-mΩ, shunt – DRV8251: 4.5-V to 48-V, 450-mΩ, shunt – DRV8251A: 4.5-V to 48-V, 450-mΩ, mirror – DRV8231: 4.5-V to 33-V, 600-mΩ, shunt – DRV8231A: 4.5-V to 33-V, 600-mΩ, mirror High output current capability: 3.7-A Peak PWM control interface Supports 1.8-V, 3.3-V, and 5-V logic inputs Integrated IPROPI current sensing for stall detection and current regulation Low-power sleep mode – VUVLO,rising Overcurrent (OCP) IOUT > IOCP Disabled Operating IOUT < IOCP Thermal Shutdown (TSD) TJ > TTSD Disabled Operating TJ < TTSD – THYS Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8231A 17 DRV8231A www.ti.com SLVSFZ8 – NOVEMBER 2021 8.6 Pin Diagrams 8.6.1 Logic-Level Inputs Figure 8-9 shows the input structure for the logic-level input pins IN1, IN2, PH/IN1, and EN/IN2. 100 k Figure 8-9. Logic-level input 18 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8231A DRV8231A www.ti.com SLVSFZ8 – NOVEMBER 2021 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The DRV8231A device is typically used to drive one brushed DC motor. 9.2 Typical Application 9.2.1 Brush DC Motor Controller RIPROPI 3.3 V OUT2 IPROPI GND IN2 IN1 3.3 V DRV8231A BDC OUT1 VM VREF PPAD 0.1 µF 47 µF + ± 4.5 to 33 V Power Supply Figure 9-1. Typical Connections 9.2.1.1 Design Requirements The table below lists the design parameters. Table 9-1. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 12 V Average motor current IAVG 0.8 A IINRUSH 2.1 A ISTALL 2.1 A Motor inrush (startup) current Motor stall current Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI sense resistance RIPROPI 1.5 kΩ fPWM 50 kHz PWM frequency 9.2.1.2 Detailed Design Procedure 9.2.1.2.1 Motor Voltage The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8231A 19 DRV8231A www.ti.com SLVSFZ8 – NOVEMBER 2021 9.2.1.2.2 Motor Current Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8231A can help to limit these large currents. Figure 9-4 and Figure 9-5 show examples of limiting inrush current. Alternatively, the microcontroller may limit the inrush current by ramping the PWM duty cycle during the startup time. 9.2.1.3 Application Curves Stall Current Inrush Current Inrush Current Motor Stall Occurs Motor Stall Occurs Stall Current Average Running Current Average Running Current Ch 1 (Yellow) = IN1 Signal Ch 3 (Blue) = OUT1 Voltage Ch 2 (Magenta) = IN2 Signal Ch 7 (Red) = Motor Current Figure 9-2. Motor startup at 100% duty cycle Ch 1 (Yellow) = IN1 Signal Ch 4 (Green) = OUT2 Voltage Figure 9-3. Motor startup at 50% duty cycle Current Regula
on Threshold (ITRIP) Inrush Current Inrush Current Motor Stall Occurs Ch 2 (Magenta) = IN2 Signal Ch 7 (Red) = Motor Current Current Regula
on Threshold (ITRIP) Stall Current Stall Current Average Running Current Ch 1 (Yellow) = IN1 Signal Ch 6 (Purple) = IPROPI Signal Motor Stall Occurs Average Running Current Ch 3 (Blue) = OUT1 Voltage Ch 7 (Red) = Motor Current Figure 9-4. Motor startup at 100% duty cycle with current regulation Ch 1 (Yellow) = IN1 Signal Ch 4 (Green) = OUT2 Voltage Ch 6 (Purple) = IPROPI Signal Ch 7 (Red) = Motor Current Figure 9-5. Motor startup at 50% duty cycle with current regulation 9.2.2 Stall Detection Some applications require stall detection to notify the microcontroller of a locked rotor condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. By using the IPROPI analog current sense feedback of the DRV8231A, the system can implement a simple stall detection scheme. The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in Figure 9-6. To implement stall detection, the microcontroller reads the voltage on the IPROPI pin using an ADC and compares it to a stall threshold set in firmware. Alternatively, a comparator peripheral may be used to set this threshold as well. 20 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8231A DRV8231A www.ti.com SLVSFZ8 – NOVEMBER 2021 Motor driver disabled Stall detected Motor Start IN1 IN2 ITRIP threshold Motor current OUTx disabled Inrush current Average running current OUTx disabled Stall Current Stall threshold in
rmware VIPROPI STALL tINRUSH tSTALL Figure 9-6. Motor Current Profile with STALL Signal 9.2.2.1 Design Requirements The table below lists the design parameters. Table 9-2. Design Parameters DESIGN PARAMETER Motor voltage Motor current trip point REFERENCE EXAMPLE VALUE VM 14.4 V ITRIP 900 mA VREF voltage VREF 2V IPROPI resistance RIPROPI 1.5 kΩ Stall current trip point Stall IPROPI voltage trip point Inrush current ignore time Stall detection time ISTALL 500 mA VIPROPI,STALL 1V tINRUSH 65 ms tSTALL 65 ms 9.2.2.2 Detailed Design Procedure 9.2.2.2.1 Stall Detection Timing The microcontroller needs to decide whether or not the IPROPI signal indicates a motor stall. Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition. One way to do this is for the microcontroller to ignore the IPROPI signal above the firmware stall threshold for the duration of the inrush current, tINRUSH, at startup. The tINRUSH timing should be determined experimentally because it depends on motor parameters, supply voltage, and mechanical load response times. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8231A 21 DRV8231A www.ti.com SLVSFZ8 – NOVEMBER 2021 When a stall condition occurs, the motor current will increase from the average running current level because the back EMF is now 0 V. In some cases, it may be desirable to drive at the stall curent for some time in case the motor can clear the blockage on its own. This might be useful for an unintended stall or high-torque condition on the motor. In this case, the system designer can choose a long stall detection time, tSTALL, before the microcontroller decides to take action. In other cases, like end-stop detection, a faster response might be desired to reduce power or minimize strong motor torque on the gears or end-stop. This corresponds to setting a shorter tSTALL time in the microcontroller. Figure 9-6 illustrates the tINRUSH and tSTALL timings and how they relate to the motor current waveform. 9.2.2.2.2 Stall Threshold Selection The stall detection threshold in firmware should be chosen at a current level between the maximum stall current and the average running current of the motor as shown in Figure 9-6. 9.2.2.3 Application Curves Current Regula
on Threshold (ITRIP) Inrush Current Inrush Current Average Running Current Motor Stall Occurs Current Regula
on Threshold (ITRIP) Stall Current Average Running Current Motor Stall Occurs Stall Current MCU Detects Stall Ch 1 (Yellow) = VIPROPI Ch 3 (Blue) = Stall Indication MCU Detects Stall Ch 2 (Magenta) = IN1 Signal Ch 4 (Green) = Motor Current Ch 1 (Yellow) = VIPROPI Ch 3 (Blue) = Stall Indication Ch 2 (Magenta) = IN1 Signal Ch 4 (Green) = Motor Current Figure 9-7. Example Waveform of Stall Detection Figure 9-8. Stall Detected on IPROPI While Current Regulation Limits Inrush and Stall Currents 9.2.3 Relay Driving The PWM interface may also be used to drive single- and dual-coil latching relays, as shown in the figures below. VCC DRV8251A/31A Controller IPROPI 1 IN2 PWM OUT2 8 2 Singlecoil relay GND 7 Thermal IN1 PWM VCC 3 Pad OUT1 6 VM VREF 4 VM 5 0.1 μF CBulk Figure 9-9. Single-Coil Relay Driving 22 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8231A DRV8231A www.ti.com SLVSFZ8 – NOVEMBER 2021 VCC DRV8251A/31A Controller VM IPROPI PWM IN2 PWM IN1 1 8 2 7 OUT2 Dualcoil relay GND Thermal VCC 3 Pad OUT1 6 VM VREF 4 VM 5 0.1 μF CBulk Figure 9-10. Dual-Coil Relay Driving 9.2.3.1 Design Requirements Table 9-3 provides example requirements for a single- or dual-coil relay application. Current regulation may also be configured to ensure the relay current is within the relay specification. This is important if the VM supply voltage is higher than the voltage rating of the relay. Table 9-3. System design requirements DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor supply voltage VM 12 V Microcontroller supply voltage VCC 3.3 V Single coil relay current IRelay 500 mA pulse for 200 ms Dual coil relay current IOUT1, IOUT2 100 mA pulse for 200 ms 9.2.3.2 Detailed Design Procedure 9.2.3.2.1 Control Interface for Single-Coil Relays The PWM interface can be used to drive single-coil relays. To actuate the relay, the driver needs to drive current with either the forward or reverse states in the PWM table. After driving the relay, the outputs can be disabled (IN1=IN2=0) to put the driver to sleep and save energy. Alternatively, the outputs can be put into brake mode briefly after actuation to avoid back EMF effects from the relay or causing current to flow back from the relay into the VM supply node. 9.2.3.2.2 Control Interface for Dual-Coil Relays A dual coil relay only require two low-side drivers if the center tap is connected to VM. The body diodes of the unused FETs act as freewheeling diodes, so additional freewheeling diodes are not needed when driving a dual-coil relay with the DRV8231A. The PWM interface can be used to control the dual-coil relay. The following figures show the schematic and timing diagram for driving dual-coil relays. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8231A 23 DRV8231A www.ti.com SLVSFZ8 – NOVEMBER 2021 VM Sleep mode Drive Coil1 Sleep mode Drive Coil2 Sleep mode IN1 IN2 VM Coil1 Coil2 VM VOUT2 VOUT1 IOUT1 VOUT1 Hi-Z IOUT2 Hi-Z Hi-Z Hi-Z Hi-Z GND Dual-coil relay VM VOUT2 Hi-Z GND IOUT1 Figure 9-11. Schematic of dual-coil relay driven by the OUTx H-bridge IOUT2 Figure 9-12. Timing diagram for driving a dual-coil relay with PWM interface Table 9-4 shows the logic table for the PWM interface. The descriptions in this table reflect how the input and output states drive the dual coil relay. When Coil1 is driven (OUT1 voltage is at GND), The voltage at OUT2 will go to VM. Because the center tap of the relay is also at VM, no current flows through Coil2. The same is true when Coil2 is driven; Coil1 shorts to VM. The body diodes of the high-side FETs act as freewheeling diodes, so extra external diodes are not needed. Figure 9-15 shows oscilloscope traces for this application. Table 9-4. PWM control table for dual-coil relay driving 24 IN1 IN2 OUT1 OUT2 DESCRIPTION 0 0 Hi-Z Hi-Z 0 1 L H Drive Coil1 1 0 H L Drive Coil2 1 1 L L Drive Coil1 and Coil2 (invalid state for a dual-coil latching relay) Outputs disabled (H-Bridge Hi-Z) Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8231A DRV8231A www.ti.com SLVSFZ8 – NOVEMBER 2021 9.2.3.3 Application Curves A. Ch 1 = IN1 Ch 4 = VOUT2 Ch 2 = IN2 Ch 6 = Relay Switch Ch 3 = VOUT1 Ch 7 = Relay Coil Current Figure 9-13. PWM driving for a single-coil latching relay with driving profile FORWARD → COAST → REVERSE → COAST A. A. Ch 1 = IN1 Ch 4 = VOUT2 Ch 2 = IN2 Ch 6 = Relay Switch Ch 3 = VOUT1 Ch 7 = Relay Coil Current Figure 9-14. PWM driving for a single-coil latching relay with driving profile FORWARD → BRAKE → REVERSE → BRAKE Ch 1 = IN1 Ch 4 = VOUT2 Ch 8 = Relay Coil2 Current Ch 2 = IN2 Ch 6 = Relay Switch Ch 3 = VOUT1 Ch 7 = Relay Coil1 Current Figure 9-15. PWM driving for dual-coil relay 9.2.4 Multi-Sourcing with Standard Motor Driver Pinout The DRV8870, DRV8251, and DRV8231 devices come in an industry standard package footprint in the DDA package. When the system needs current sensing, a current-sense amplifier may be used across the RSENSE resistor to provide an amplifed signal back to an microcontroller ADC as shown in Figure 9-16. To reduce the size of the system bill of materials and cost, the IPROPI function in DRV8231A/51A can replace the current sense amplifer. During the board design process, both solutions, IPROPI and industry standard shunt devices, can be accomodated in the same board layout by placing and not placing (DNP) components as shown in Figure 9-17. This allows the system to be flexible for lowest cost with the DRV8231A/51A or for use with second-source devices with the same pinout as DRV8870, DRV8231, and DRV8251. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8231A 25 DRV8231A www.ti.com SLVSFZ8 – NOVEMBER 2021 0 To ADC DNP GND 1 8 0 IN1 2 IN2 3 VREF 4 DRV8870, DRV8231, DRV8251 OUT2 6 ISEN Rsense 0.5
OUT1 5 VM 7 Sense Amp Figure 9-16. Standard Pinout with Current Sense Amplifier DNP To ADC 0 IPROPI Ripropi 1.5 k 1 IN1 2 IN2 3 VREF 4 8 DRV8231A, DRV8251A 7 OUT2 GND 6 OUT1 5 VM 0
Sense Amp DNP Figure 9-17. DRV8231A/51A Device Using IPROPI to Integrate The Current Sense Function into The Motor Driver 9.3 Current Capability and Thermal Performance The output current and power dissipation capabilities of the driver depends heavily on the PCB design and external system conditions. This section provides some guidelines for calculating these values. 9.3.1 Power Dissipation and Output Current Capability Total power dissipation for the device consists of three main components: quiescent supply current dissipation (PVM), the power MOSFET switching losses (PSW), and the power MOSFET RDS(on) (conduction) losses (PRDS). While other factors may contribute additional power losses, they are typically insignificant compared to the three main items. PTOT = PVM + PSW + PRDS PVM can be calculated from the nominal motor supply voltage (VVM) and the IVM active mode current specification. PVM = VVM x IVM (4) PVM = 96 mW = 24 V x 4 mA (5) PSW can be calculated from the nominal motor supply voltage (VVM), average output current (IAVG), switching frequency (fPWM) and the device output rise (tRISE) and fall (tFALL) time specifications. 26 PSW = PSW_RISE + PSW_FALL (6) PSW_RISE = 0.5 x VM x IAVG x tRISE x fPWM (7) PSW_FALL = 0.5 x VM x IAVG x tFALL x fPWM (8) PSW_RISE = 26.4 mW = 0.5 x 24 V x 0.5 A x 220 ns x 20 kHz (9) Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8231A DRV8231A www.ti.com SLVSFZ8 – NOVEMBER 2021 PSW_FALL = 26.4 mW = 0.5 x 24 V x 0.5 A x 220 ns x 20 kHz (10) PSW = 53 mW = 26.4 mW + 26.4 mW (11) PRDS can be calculated from the device RDS(on) and average output current (IAVG). PRDS = IAVG 2 x (RDS(ON)_HS + RDS(ON)_LS) (12) RDS(ON) has a strong correlation with the device temperature. Assuming a device junction temperature of 85 °C, RDS(on) could increase ~1.5x based on the normalized temperature data. The calculation below shows this derating factor. Alternatively, Section 7.6 shows curves that plot how RDS(on) changes with temperature. PRDS = 225 mW = (0.5 A)2 x (300 mΩ x 1.5 + 300 mΩ x 1.5) (13) Based on the example calculations above, the expressions below calculate the total expected power dissipation for the device. PTOT = PVM + PSW + PRDS PTOT = 374 mW = 96 mW + 53 mW + 225 mW (14) The driver's junction temperature can be estimated using PTOT, device ambient temperature (TA), and package thermal resistance (RθJA). The value for RθJA depends heavily on the PCB design and copper heat sinking around the device. Section 9.3.2 describes this dependence in greater detail. TJ = (PTOT x RθJA) + TA (15) TJ = 100 °C = (0.374 W x 40.4 °C/W) + 85°C (16) The device junction temperature should remain below its absolute maximum rating for all system operating conditions. The calculations in this section provide reasonable estimates for junction temperature. However, other methods based on temperature measurements taken during system operation are more realistic and reliable. Additional information on motor driver current ratings and power dissipation can be found in Section 9.3.2 and Section 12.1.1. 9.3.2 Thermal Performance The datasheet-specified junction-to-ambient thermal resistance, RθJA, is primarily useful for comparing various drivers or approximating thermal performance. However, the actual system performance may be better or worse than this value depending on PCB stackup, routing, number of vias, and copper area around the thermal pad. The length of time the driver drives a particular current will also impact power dissipation and thermal performance. This section considers how to design for steady-state and transient thermal conditions. The data in this section was simulated using the following criteria. HSOP (DDA package) Table 9-5. Simulation PCB Stackup Summary for HSOP package Layer 2-layer 4-layer Top Layer HSOP footprint with 1- or 2-oz copper thickness. See Table 9-6 for copper area varied in simulation. Thermally connected with vias (2 vias, 1.2-mm spacing, 0.3-mm diameter, 0.025-mm copper plating) from HSOP thermal pad to bottom layer and internal ground plane (4-layer only). Layer 2, internal ground plane N/A 1-oz copper thickness, 74.2 mm x 74.2 mm copper area, thermally connected to HSOP thermal pad through vias. Layer 3, internal supply plane N/A 1-oz copper thickness, 74.2 mm x 74.2 mm copper area, not connected to other layers. Bottom Layer Ground plane with 1- or 2-oz copper thickness. See 1- or 2-oz copper thickness. Copper area fixed at 4.90 Table 9-6 for copper area varied in simulation. Thermally mm × 6.00 mm in simulation. Thermally connected to connected to HSOP thermal pad through vias. HSOP thermal pad through vias. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8231A 27 DRV8231A www.ti.com SLVSFZ8 – NOVEMBER 2021 Figure 9-18 shows an example of the simulated board for the HSOP package. Table 9-6 shows the dimensions of the board that were varied for each simulation. Figure 9-18. HSOP PCB model top layer Table 9-6. Dimension A for 8-pin HSOP (DDA) package Cu area (cm2) Dimension A (mm) 0.069 Package thermal pad dimensions 2 16.40 4 22.32 8 30.64 16 42.38 WSON (DSG package) Table 9-7. Simulation PCB Stackup Summary for WSON package Layer 2-layer 4-layer Top Layer WSON footprint with 1- or 2-oz copper thickness. See Table 9-8 for copper area varied in simulation. Thermally connected with vias (2 vias, 1.2-mm spacing, 0.3-mm diameter, 0.025-mm copper plating) from WSON thermal pad to bottom layer and internal ground plane (4-layer only). Layer 2, internal ground plane N/A 1-oz copper thickness, 74.2 mm x 74.2 mm copper area, thermally connected to HSOP thermal pad through vias. Layer 3, internal supply plane N/A 1-oz copper thickness, 74.2 mm x 74.2 mm copper area, not connected to other layers. Bottom Layer Ground plane with 1- or 2-oz copper thickness. See 1- or 2-oz copper thickness. Copper area fixed at 2.00 Table 9-8 for copper area varied in simulation. Thermally mm × 2.00 mm in simulation. Thermally connected to connected to WSON thermal pad through vias. WSON thermal pad through vias. Figure 9-19 shows an example of the simulated board for the WSON package. Table 9-8 shows the dimensions of the board that were varied for each simulation. 28 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8231A DRV8231A www.ti.com SLVSFZ8 – NOVEMBER 2021 Figure 9-19. WSON PCB model top layer Table 9-8. Dimension A for 8-pin WSON package Cu area (mm2) Dimension A (mm) 0.015 Package thermal pad dimensions 2 15.11 4 20.98 8 29.27 16 40.99 9.3.2.1 Steady-State Thermal Performance "Steady-state" conditions assume that the motor driver operates with a constant average current over a long period of time. The figures in this section show how RθJA and ΨJB (junction-to-board characterization parameter) change depending on copper area, copper thickness, and number of layers of the PCB. More copper area, more layers, and thicker copper planes decrease RθJA and ΨJB, which indicate better thermal performance from the PCB layout. 50 200 4 layer, 2 oz 4 layer, 1 oz 2 layer, 2 oz 2 layer, 1 oz 180 160 40 JB (C/W) RJA (C/W) 140 120 100 80 35 30 25 60 20 40 15 20 0 2 4 6 8 10 12 Top layer copper area (cm2) 14 Figure 9-20. HSOP, PCB junction-to-ambient thermal resistance vs copper area 16 4 layer, 2 oz 4 layer, 1 oz 2 layer, 2 oz 2 layer, 1 oz 45 10 0 2 4 6 8 10 12 Top layer copper area (cm2) 14 16 Figure 9-21. HSOP, junction-to-board characterization parameter vs copper area Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8231A 29 DRV8231A www.ti.com SLVSFZ8 – NOVEMBER 2021 275 4 layer, 2 oz 4 layer, 1 oz 2 layer, 2 oz 2 layer, 1 oz 250 225 175 JB (C/W) RJA (C/W) 200 150 125 100 75 50 25 0 2 4 6 8 10 12 Top layer copper area (cm2) 14 16 Figure 9-22. WSON, PCB junction-to-ambient thermal resistance vs copper area 80 75 70 65 60 55 50 45 40 35 30 25 20 15 4 layer, 2 oz 4 layer, 1 oz 2 layer, 2 oz 2 layer, 1 oz 0 2 4 6 8 10 12 Top layer copper area (cm2) 14 16 Figure 9-23. WSON, junction-to-board characterization parameter vs copper area 9.3.2.2 Transient Thermal Performance The motor driver may experience different transient driving conditions that cause large currents to flow for a short duration of time. These may include • • • Motor start-up when the rotor is initially stationary. Fault conditions when there is a supply or ground short to one of the motor outputs, and the overcurrent protection triggers. Briefly energizing a motor or solenoid for a limited time, then de-energizing. For these transient cases, the duration of drive time is another factor that impacts thermal performance in addition to copper area and thickness. In transient cases, the thermal impedance parameter ZθJA denotes the junction-to-ambient thermal performance. The figures in this section show the simulated thermal impedances for 1-oz and 2-oz copper layouts for the HSOP and WSON packages. These graphs indicate better thermal performance with short current pulses. For short periods of drive time, the device die size and package dominates the thermal performance. For longer drive pulses, board layout has a more significant impact on thermal performance. Both graphs show the curves for thermal impedance split due to number of layers and copper area as the duration of the drive pulse duration increases. Long pulses can be considered steady-state performance. 200 100 70 ZJA (C/W) 50 40 30 20 10 7 0.069 cm2, 2 layer 2 cm2, 2 layer 4 cm2, 2 layer 8 cm2, 2 layer 0.069 cm2, 4 layer 2 cm2, 4 layer 4 cm2, 4 layer 8 cm2, 4 layer 5 4 3 2 1 0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.3 0.50.7 1 2 3 4 5 678 10 Pulse duration (s) 20 30 50 70 100 200300 500 1000 Figure 9-24. HSOP package junction-to-ambient thermal impedance for 1-oz copper layouts 30 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8231A DRV8231A www.ti.com SLVSFZ8 – NOVEMBER 2021 200 100 70 ZJA (C/W) 50 40 30 20 10 7 0.69 cm2, 2 layer 2 cm2, 2 layer 4 cm2, 2 layer 8 cm2, 2 layer 0.69 cm2, 4 layer 2 cm2, 4 layer 4 cm2, 4 layer 8 cm2, 4 layer 5 4 3 2 1 0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.3 0.50.7 1 2 3 4 5 678 10 Pulse Duration (s) 20 30 50 70 100 200300 500 1000 Figure 9-25. HSOP package junction-to-ambient thermal impedance for 2-oz copper layouts 300 200 100 ZJA (C/W) 70 50 40 30 20 0.015 cm2, 2 layer 2 cm2, 2 layer 4 cm2, 2 layer 8 cm2, 2 layer 0.015 cm2, 4 layer 2 cm2, 4 layer 4 cm2, 4 layer 8 cm2, 4 layer 10 7 5 4 3 2 0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.3 0.50.7 1 2 3 4 5 678 10 Pulse duration (s) 20 30 50 70 100 200300 500 1000 Figure 9-26. WSON package junction-to-ambient thermal impedance for 1-oz copper layouts 300 200 100 ZJA (C/W) 70 50 40 30 20 0.015 cm2, 2 layer 2 cm2, 2 layer 4 cm2, 2 layer 8 cm2, 2 layer 0.015 cm2, 4 layer 2 cm2, 4 layer 4 cm2, 4 layer 8 cm2, 4 layer 10 7 5 4 3 2 0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.3 0.50.7 1 2 3 4 5 678 10 Pulse duration (s) 20 30 50 70 100 200300 500 1000 Figure 9-27. WSON package junction-to-ambient thermal impedance for 2-oz copper layouts Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8231A 31 DRV8231A www.ti.com SLVSFZ8 – NOVEMBER 2021 10 Power Supply Recommendations 10.1 Bulk Capacitance Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: • • • • • • The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Power Supply Parasitic Wire Inductance Motor Drive System VBB + ± + Motor Driver GND Local Bulk Capacitor IC Bypass Capacitor Figure 10-1. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. 32 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8231A DRV8231A www.ti.com SLVSFZ8 – NOVEMBER 2021 11 Layout 11.1 Layout Guidelines Since the DRV8231A integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. • • • • • • • Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. 11.2 Layout Example IPROPI 1 IN2 2 8 OUT2 7 GND 6 OUT1 5 VM Thermal IN1 3 VREF 4 Pad + Figure 11-1. Layout Recommendation for DSG package Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8231A 33 DRV8231A www.ti.com SLVSFZ8 – NOVEMBER 2021 IPROPI 1 IN2 2 8 OUT2 7 GND 6 OUT1 5 VM Thermal IN1 3 VREF 4 Pad + Figure 11-2. Layout Recommendation for DDA Package 34 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8231A DRV8231A www.ti.com SLVSFZ8 – NOVEMBER 2021 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation, see the following: • • • • • Texas Instruments, Calculating Motor Driver Power Dissipation application report Texas Instruments, Current Recirculation and Decay Modes application report Texas Instruments, PowerPAD™ Made Easy application report Texas Instruments, PowerPAD™ Thermally Enhanced Package application report Texas Instruments, Understanding Motor Driver Current Ratings application report 12.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.3 Community Resources 12.4 Trademarks PowerPAD™ are trademarks of Texas Instruments. All trademarks are the property of their respective owners. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8231A 35 PACKAGE OPTION ADDENDUM www.ti.com 8-Apr-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) DRV8231ADDAR ACTIVE SO PowerPAD DDA 8 3000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 150 DRV8231A Samples DRV8231ADSGR ACTIVE DSG 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 150 31A Samples WSON (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of