DRV8243-Q1
SLVSG23C – DECEMBER 2021 – REVISED AUGUST 2022
DRV8243-Q1 Automotive H-Bridge Driver with Integrated Current Sense and
Diagnostics
1 Features
3 Description
•
The DRV824x-Q1 family of devices is a fully
integrated H-bridge driver intended for a wide
range of automotive applications. The device can
be configured as a single full-bridge driver or as
two independent half-bridge drivers. Designed in a
BiCMOS high power process technology node, this
monolithic family of devices in a power package
offer excellent power handling and thermal capability
while providing compact package size, ease of layout,
EMI control, accurate current sense, robustness, and
diagnostic capability. This family provides an identical
pin function with scalable RON (current capability) to
support different loads.
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The devices integrate a N-channel H-bridge, charge
pump regulator, high-side current sensing with
regulation, current proportional output, and protection
circuitry. A low-power sleep mode is provided to
achieve low quiescent current. The devices offer
voltage monitoring and load diagnostics as well
as protection features against over current and
over temperature. Fault conditions are indicated on
nFAULT pin. The devices are available in three
variants - hardwired interface: HW (H) and two SPI
interface variants: SPI(P) and SPI(S), with SPI (P)
for externally supplied logic supply and SPI (S) for
internally generated logic supply. The SPI interface
variants offer more flexibility in device configuration
and fault observability.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (nominal)
DRV8243-Q1
VQFN-HR (14)
3 mm X 4.5 mm
DRV8243-Q1
HVSSOP (28)
3 mm X 7.3 mm
2 Applications
Automotive brushed DC motors, Solenoids
Door modules , mirror modules, and seat modules
Body control module (BCM)
E-Shifter
Gas engine systems
On board charger
(1)
For all available packages, see the orderable addendum at
the end of the data sheet
4.5 - 35 V
nSLEEP
Controller
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IOs
•
AEC-Q100 qualified for automotive applications:
– Temperature grade 1: –40°C to +125°C, TA
Functional Safety-Capable
– Documentation available to aid functional safety
system design
4.5-V to 35-V (40-V abs. max) operating range
VQFN-HR package: RON_LS + RON_HS: 84 mΩ
HVSSOP package: RON_LS + RON_HS: 98 mΩ
IOUT Max = 12 A
PWM frequency operation up to 25 KHz with
automatic dead time assertion
Configurable slew rate and spread spectrum
clocking for low electromagnetic interference (EMI)
Integrated current sense (eliminates shunt resistor)
Proportional load current output on IPROPI pin
Configurable current regulation
Protection and diagnostic features with
configurable fault reaction (latched or retry)
– Load diagnostics in both the off-state and onstate to detect open load and short circuit
– Voltage monitoring on supply (VM)
– Over current protection
– Over temperature protection
– Fault indication on nFAULT pin
Supports 3.3-V, 5-V logic inputs
Low sleep current - 1μA typical at 25°C
3 variants - HW (H), SPI (S) or SPI (P)
Configurable control modes:
– Single full bridge using PWM or PH/EN mode
– Two half-bridges using Independent mode
Device family comparison table
ADC
DRV824X-Q1
Driver Control
nFAULT
SPI (SPI variant)
CONFIG pins
(HW variant)
IPROPI
Full Bridge
Driver
Diagnoscs
Current Sense
Current Regula on
Built-in Protecon
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRV8243-Q1
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SLVSG23C – DECEMBER 2021 – REVISED AUGUST 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison......................................................... 4
6 Pin Configuration and Functions...................................6
6.1 HW Variant..................................................................6
6.2 SPI Variant.................................................................. 8
7 Specifications................................................................ 11
7.1 Absolute Maximum Ratings...................................... 11
7.2 ESD Ratings..............................................................11
7.3 Recommended Operating Conditions.......................12
7.4 Thermal Information..................................................12
7.5 Electrical Characteristics...........................................12
7.6 SPI Timing Requirements......................................... 19
7.7 Switching Waveforms................................................21
7.8 Typical Characteristics.............................................. 27
8 Detailed Description......................................................29
8.1 Overview................................................................... 29
8.2 Functional Block Diagram......................................... 30
8.3 Feature Description...................................................33
8.4 Device Functional States.......................................... 46
8.5 Programming - SPI Variant Only...............................48
8.6 Register Map - SPI Variant Only............................... 53
9 Application and Implementation.................................. 60
9.1 Application Information............................................. 60
9.2 Typical Application.................................................... 61
10 Power Supply Recommendations..............................65
10.1 Bulk Capacitance Sizing......................................... 65
11 Layout........................................................................... 66
11.1 Layout Guidelines................................................... 66
11.2 Layout Example...................................................... 66
12 Device and Documentation Support..........................67
12.1 Documentation Support.......................................... 67
12.2 Receiving Notification of Documentation Updates..67
12.3 Community Resources............................................67
12.4 Trademarks............................................................. 67
13 Mechanical, Packaging, and Orderable
Information.................................................................... 67
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (August 2022) to Revision C (August 2022)
Page
• Added footer to allow Absolute Maximum Rating violation on VM pin during ISO 7637 transients ................. 11
• Improved footer description on short protection............................................................................................... 12
• EC table - HVSSOP package only - Lowered AIPROPI accuracy from 5% to 6%, and AIPROPI matching from 2%
to 5% ................................................................................................................................................................17
• Typical characteristics - Added FET RON plot for leaded package..................................................................27
Changes from Revision A (January 2022) to Revision B (July 2022)
Page
• Device comparison - Removed pre-production information, slew rate and off-state diagnostics feature
exceptions for DRV8245HRXZQ1 and DRV8244SRYJQ1.................................................................................4
• Corrected pin name typo for PH/IN2.................................................................................................................11
• EC table - RLVL3of3 for MODE pin increased to 250 KΩ minimum.................................................................... 14
• EC table - Updated typical RON values............................................................................................................. 14
• Typical characteristics - Corrected FET RON plot, improved AIPROPI plot........................................................ 27
• Block diagram for P-variant - Corrected VDD pin typo..................................................................................... 30
• Feature description for PWM mode - Removed pre-production information.................................................... 34
• Feature description for Register - Pin control - Removed pre-production information......................................36
• Feature description for SR - Removed pre-production information and duplication of SR tables (Refer EC
table instead).................................................................................................................................................... 37
• Feature description for ITRIP regulation - Removed pre-production information, added note on linear ITRIP
levels using external DAC.................................................................................................................................37
• Feature description for DIAG pin (HW variant only) - Corrected behavior for LVL5 setting..............................39
• Feature description update for OLA - Added clarification on fault clearing when drive direction is reversed... 44
• Functional states - Removed pre-production information................................................................................. 46
• SDO frame - Removed pre-production information.......................................................................................... 49
• User registers - Removed pre-production information......................................................................................54
• Typical application - Added recommendations for EMC................................................................................... 61
2
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Changes from Revision * (November 2021) to Revision A (January 2022)
Page
• Updated device status to Mixed Production....................................................................................................... 1
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5 Device Comparison
Table 5-1 summarizes the RON and package differences between devices in the DRV824X-Q1 family.
Table 5-1. Device Comparison
PART NUMBER(1)
(LS + HS) RON
IOUT MAX
PACKAGE
BODY SIZE (nominal)
DRV8243-Q1
84 mΩ
12 A
VQFN-HR (14)
3 mm X 4.5 mm
HW (H), SPI (S)
DRV8243-Q1
98 mΩ
12 A
HVSSOP (28)
3 mm X 7.3 mm
HW (H), SPI (S), SPI (P)
DRV8244-Q1
47 mΩ
21 A
VQFN-HR (16)
3 mm X 6 mm
HW (H), SPI (S)
DRV8244-Q1
60 mΩ
21 A
HVSSOP (28)
3 mm X 7.3 mm
HW (H), SPI (S), SPI (P)
DRV8245-Q1
32 mΩ
32 A
VQFN-HR (16)
3.5 mm X 5.5 mm
HW (H), SPI (S)
DRV8245-Q1
40 mΩ
32 A
HTSSOP (28)
4.4 mm X 9.7 mm
HW (H), SPI (S), SPI (P)
(1)
Variants
This is the product datasheet for the DRV8243-Q1. Please reference other device variant data sheets for additional information.
Table 5-2 summarizes the feature differences between the SPI and HW interface variants in the DRV824XQ1 family. In general, the SPI variant offers more configurability, bridge control options, diagnostic feedback,
redundant driver shutoff, improved Pin FMEA and additional features.
In addition, the SPI variant has two options - SPI (S) variant and SPI (P) variant. The SPI (P) variant supports
an external, low voltage 5 V supply to the device through the VDD pin for the device logic, whereas in the SPI
(S) variant, this supply is internally derived from the VM pin. With this external logic supply, the SPI (P) variant
avoids device brown out (reset of device) during VM under voltage transients.
Table 5-2. SPI Variant vs HW Variant Comparison
FUNCTION
HW (H) Variant
Bridge control
SPI (S) Variant
Pin only
Sleep function
SPI (P) Variant
Individual pin "and/or" register bit with pin status indication (Refer
Register Pin control)
Available through nSLEEP pin
Not available
External logic supply to the device
Not supported
Clear fault command
Reset pulse on nSLEEP
pin
Not supported
Supported through VDD pin
SPI CLR_FAULT command
Slew rate
6 levels
8 levels
Over current protection (OCP)
Fixed at the highest
setting
3 choices for thresholds, 4 choices for filter time
ITRIP regulation
5 levels with disable &
fixed TOFF time
7 levels with disable & indication, with programmable TOFF time
Individual fault reaction configuration
between retry or latched behavior
Not supported, either all
latched or all retry
Supported
Detailed fault logging and device status
feedback
Not supported, nFAULT
pin monitoring necessary
Supported, nFAULT pin monitoring optional
VM over voltage
Fixed
4 threshold choices
On-state (Active) diagnostics
Not supported
Supported for high-side loads
Spread spectrum clocking (SSC)
Not supported
Supported
Additional driver states in PWM mode
Not supported
Supported
Hi-Z for individual half-bridge in
Independent mode
Not supported
Supported (SPI register only)
Table 5-3. Differentiating between devices in the family
4
Device
Package Symbolization
DEVICE_ID Register
DRV8243H-Q1
8243H
Not applicable
DRV8244H-Q1
8244H
Not applicable
DRV8245H-Q1
8245H
Not applicable
DRV8243S-Q1
8243S
0 x 32
DRV8244S-Q1
8244S
0 x 42
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Table 5-3. Differentiating between devices in the family (continued)
Device
Package Symbolization
DEVICE_ID Register
DRV8245S-Q1
8245S
0 x 52
DRV8243P-Q1
8243P
0 x 36
DRV8244P-Q1
8244P
0 x 46
DRV8245P-Q1
8245P
0 x 56
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6 Pin Configuration and Functions
6.1 HW Variant
6.1.1 HVSSOP (28) package
1
28
ITRIP
DIAG
2
27
MODE
PH/IN2
3
26
nFAULT
EN/IN1
4
25
IPROPI
DRVOFF
5
24
nSLEEP
23
VM
22
VM
21
VM
20
OUT2
VM
6
VM
7
VM
8
Thermal Pad
SR
OUT1
9
OUT1
10
19
OUT2
OUT1
11
18
OUT2
GND
12
17
GND
GND
13
16
GND
GND
14
15
GND
Figure not drawn to scale
Figure 6-1. DRV8243H-Q1 HW variant in HVSSOP (28) package
Table 6-1. Pin Functions
PIN
6
TYPE(1)
DESCRIPTION
NO.
NAME
1
SR
I
Device configuration pin for Slew Rate control . For details, refer to Slew Rate in the Device
Configuration section.
2
DIAG
I
Device configuration pin for load type indication and fault reaction configuration. For details,
refer to DIAG in the Device Configuration section.
3
PH/IN2
I
Controller input pin for bridge operation. For details, see the Bridge Control section.
4
EN/IN1
I
Controller input pin for bridge operation. For details, see the Bridge Control section.
5
DRVOFF
I
Controller input pin for bridge Hi-Z. For details, see the Bridge Control section.
6, 7, 8, 21,
22, 23
VM
P
Power supply. This pin is the motor supply voltage. Must combine with the rest of VM pins
(6 total) to support device current capability. Bypass this pin to GND with a 0.1-µF ceramic
capacitor and a bulk capacitor.
9, 10, 11
OUT1
P
Half-bridge output 1. Connect this pin to the motor or load. Must combine with the rest of
OUT1 pins (3 total) to support device current capability.
12, 13, 14,
15, 16, 17
GND
G
Ground pin. Must combine with the rest of GND pins (6 total) to support device current
capability.
18, 19, 20
OUT2
P
Half-bridge output 2. Connect this pin to the motor or load. Must combine with the rest of
OUT2 pins (3 total) to support device current capability.
24
nSLEEP
I
Controller input pin for SLEEP. For details, see the Bridge Control section.
25
IPROPI
I/O
Driver load current analog feedback. For details, refer to IPROPI in the Device Configuration
section.
26
nFAULT
OD
Fault indication to the controller. For details, refer to nFAULT in the Device Configuration
section.
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Table 6-1. Pin Functions (continued)
PIN
(1)
TYPE(1)
DESCRIPTION
NO.
NAME
27
MODE
I
Device configuration pin for MODE. For details, refer to the Device Configuration section.
28
ITRIP
I
Device configuration pin for ITRIP level for high-side current limiting. For details, refer to
ITRIP in the Device Configuration section.
I = input, O = output, I/O = input/output, G = ground, P = power, OD = open-drain output, PP = push-pull output
14 MODE
11
13 ITRIP
DIAG
12
12 SR
SR
13
DIAG
ITRIP
14
11
MODE
6.1.2 VQFN-HR (14) package
nFAULT
1
10
PH/IN2
PH/IN2
10
1
nFAULT
IPROPI
2
9
EN/IN1
EN/IN1
9
2
IPROPI
nSLEEP
3
8
DRVOFF
DRVOFF
8
3
nSLEEP
TOP VIEW
7
5
OUT2
GND
6
GND
GND
VM
VM
4
VM
GND
BOTTOM VIEW
OUT1
OUT1
GND
GND
VM
4
7
5
6
GND
GND
GND
OUT2
GND
GND
GND
Figure not drawn to scale
Figure 6-2. DRV8243H-Q1 HW variant in VQFN-HR (14) package
Table 6-2. Pin Functions
PIN
TYPE (1)
DESCRIPTION
NO.
NAME
1
nFAULT
OD
Fault indication to the controller. For details, refer to nFAULT in the Device Configuration
section.
2
IPROPI
I/O
Driver load current analog feedback. For details, refer to IPROPI in the Device Configuration
section.
3
nSLEEP
I
Controller input pin for SLEEP . For details, see the Bridge Control section.
4
VM
P
Power supply. This pin is the motor supply voltage. Bypass this pin to GND with a 0.1-µF
ceramic capacitor and a bulk capacitor.
5
OUT2
P
Half-bridge output 2. Connect this pin to the motor or load.
6
GND
G
Ground pin
7
OUT1
P
Half-bridge output 1. Connect this pin to the motor or load.
8
DRVOFF
I
Controller input pin for bridge Hi-Z. For details, see the Bridge Control section.
9
EN/IN1
I
Controller input pin for bridge operation. For details, see the Bridge Control section.
10
PH/IN2
I
Controller input pin for bridge operation. For details, see the Bridge Control section.
11
DIAG
I
Device configuration pin for load type indication and fault reaction configuration. For details,
refer to DIAG in the Device Configuration section.
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Table 6-2. Pin Functions (continued)
PIN
(1)
TYPE (1)
DESCRIPTION
NO.
NAME
12
SR
I
Device configuration pin for Slew Rate control . For details, refer to Slew Rate in the Device
Configuration section.
13
ITRIP
I
Device configuration pin for ITRIP level for high-side current limiting. For details, refer to
ITRIP in the Device Configuration section.
14
MODE
I
Device configuration pin for MODE. For details, refer to the Device Configuration section.
I = input, O = output, I/O = input/output, G = ground, P = power, OD = open-drain output, PP = push-pull output
6.2 SPI Variant
6.2.1 HVSSOP (28) package
28
SDI
SCLK
1
28
SDI
nSCS
2
27
SDO
nSCS
2
27
SDO
PH/IN2
3
26
nFAULT
PH/IN2
3
26
nFAULT
EN/IN1
4
25
IPROPI
EN/IN1
4
25
IPROPI
DRVOFF
5
24
nSLEEP
DRVOFF
5
24
VDD
23
VM
VM
6
23
VM
22
VM
VM
7
22
VM
21
VM
VM
8
21
VM
20
OUT2
OUT1
9
20
OUT2
VM
6
VM
7
VM
8
Thermal Pad
1
Thermal Pad
SCLK
OUT1
9
OUT1
10
19
OUT2
OUT1
10
19
OUT2
OUT1
11
18
OUT2
OUT1
11
18
OUT2
GND
12
17
GND
GND
12
17
GND
GND
13
16
GND
GND
13
16
GND
GND
14
15
GND
GND
14
15
GND
Figure not drawn to scale
Figure not drawn to scale
SPI (S) variant
SPI (P) variant
Figure 6-3. DRV8243S-Q1 SPI variant in HVSSOP (28) package
Table 6-3. Pin Functions
PIN
8
TYPE (1)
DESCRIPTION
NO.
NAME
1
SCLK
I
SPI - Serial Clock input.
2
nSCS
I
SPI - Chip Select. An active low on this pin enables the serial interface communication.
3
PH/IN2
I
Controller input pin for bridge operation. For details, see the Bridge Control section.
4
EN/IN1
I
Controller input pin for bridge operation. For details, see the Bridge Control section.
5
DRVOFF
I
Controller input pin for bridge Hi-Z. For details, see the Bridge Control section.
6, 7, 8, 21,
22, 23
VM
P
Power supply. This pin is the motor supply voltage. Must combine with the rest of VM pins
(6 total) to support device current capability. Bypass this pin to GND with a 0.1-µF ceramic
capacitor and a bulk capacitor.
9, 10, 11
OUT1
P
Half-bridge output 1. Connect this pin to the motor or load. Must combine with the rest of
OUT1 pins (3 total) to support device current capability.
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Table 6-3. Pin Functions (continued)
PIN
TYPE (1)
DESCRIPTION
NO.
NAME
12, 13, 14,
15, 16, 17
GND
G
Ground pin. Must combine with the rest of GND pins (6 total) to support device current
capability.
18, 19, 20
OUT2
P
Half-bridge output 2. Connect this pin to the motor or load. Must combine with the rest of
OUT2 pins (3 total) to support device current capability.
nSLEEP
I
SPI (S) variant: Controller input pin for SLEEP. For details, see the Bridge Control section.
Also VIO logic level for SDO.
VDD
P
SPI (P) variant: Logic power supply to the device.
25
IPROPI
I/O
Driver load current analog feedback. For details, refer to IPROPI in the Device Configuration
section.
26
nFAULT
OD
Fault indication to the controller. For details, refer to nFAULT in the Device Configuration
section.
27
SDO
PP
SPI - Serial Data Output. Data is updated at the rising edge of SCLK.
28
SDI
I
SPI - Serial Data Input. Data is captured at the falling edge of SCLK.
24
(1)
I = input, O = output, I/O = input/output, G = ground, P = power, OD = open-drain output, PP = push-pull output
SDI
SDO
13
14
11
SCLK
nSCS
12
12
SCLK
13
nSCS
SDI
14
11
SDO
6.2.2 VQFN-HR (14) package
nFAULT
1
10
PH/IN2
PH/IN2
10
1
nFAULT
IPROPI
2
9
EN/IN1
EN/IN1
9
2
IPROPI
nSLEEP
3
8
DRVOFF
DRVOFF
8
3
nSLEEP
TOP VIEW
7
5
OUT2
GND
6
GND
GND
VM
VM
4
VM
GND
BOTTOM VIEW
OUT1
OUT1
GND
GND
VM
4
7
5
6
GND
GND
GND
OUT2
GND
GND
GND
Figure not drawn to scale
Figure 6-4. DRV8243S-Q1 SPI variant in VQFN-HR (14) package
Table 6-4. Pin Functions
PIN
TYPE (1)
DESCRIPTION
NO.
NAME
1
nFAULT
OD
2
IPROPI
O
Driver load current analog feedback. For details, refer to IPROPI in the Device Configuration
section.
3
nSLEEP
I
Controller input pin for SLEEP. For details, see the Bridge Control section. Also VIO logic
level for SDO.
Fault indication to the controller. For details, refer to nFAULT in the Device Configuration
section.
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Table 6-4. Pin Functions (continued)
PIN
(1)
10
NO.
NAME
4
VM
5
6
TYPE (1)
DESCRIPTION
P
Power supply. This pin is the motor supply voltage. Bypass this pin to GND with a 0.1-µF
ceramic capacitor and a bulk capacitor.
OUT2
P
Half-bridge output 2. Connect this pin to the motor or load.
GND
G
Ground pin
7
OUT1
P
Half-bridge output 1. Connect this pin to the motor or load.
8
DRVOFF
I
Controller input pin for bridge Hi-Z. For details, see the Bridge Control section.
9
EN/IN1
I
Controller input pin for bridge operation. For details, see the Bridge Control section.
10
PH/IN2
I
Controller input pin for bridge operation. For details, see the Bridge Control section.
11
nSCS
I
SPI - Chip Select. An active low on this pin enables the serial interface communication.
12
SCLK
I
SPI - Serial Clock input.
13
SDI
I
SPI - Serial Data Input. Data is captured at the falling edge of SCLK.
14
SDO
PP
SPI - Serial Data Output. Data is updated at the rising edge of SCLK.
I = input, O = output, I/O = input/output, G = ground, P = power, OD = open-drain output, PP = push-pull output
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7 Specifications
7.1 Absolute Maximum Ratings
Over operating temperature range (unless otherwise noted)(1)
Power supply pin voltage
VM
Power supply transient voltage ramp
Output pin voltage
OUT1, OUT2
Driver disable pin voltage
MAX
UNIT
40
V
2
V/µs
-0.9
VVM + 0.9
V
VM
OUT1, OUT2
Output pin current
MIN
–0.3(3)
Internally
limited(2)
A
DRVOFF
–0.3
40
V
Logic I/O voltage
EN/IN1, PH/IN2, nFAULT
–0.3
5.75
V
HW variant - Configuration pins voltage
MODE, ITRIP, SR, DIAG
–0.3
5.75
V
Analog feedback pin voltage
IPROPI
–0.3
5.75
V
Sleep pin voltage (Not applicable for SPI (P)
variant)
nSLEEP
–0.3
40
V
SPI I/O voltage - SPI variant
SDI, SDO, nSCS, SCLK
–0.3
5.75
V
SPI (P) variant - Logic supply
VDD
-0.3
5.75
V
SPI (P) variant - Logic supply transient voltage
ramp
VDD
5
V/µs
Ambient temperature, TA
–40
125
°C
Junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–65
150
°C
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
Limited by the over current and over temperature protection functions of the device
With external component support, short duration violation of this limit can be tolerated during ISO 7637 transient pulse testing
7.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic
discharge
Human body model (HBM), per AEC Q100-002(1)
HBM ESD Classification Level 2
VM, OUT1, OUT2, GND
±4000
All other pins
±2000
Charged device model (CDM), per AEC Q100-011 Corner pins
CDM ESD Classification Level C4B
Other pins
±750
UNIT
V
±500
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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7.3 Recommended Operating Conditions
over operating temperature range (unless otherwise noted)
VVM
Power supply voltage
VVDD
SPI (P) variant - Logic supply voltage
MAX
UNIT
V
VM
4.5
35(1)
VDD
4.5
5.5
V
VLOGIC
Logic pin voltage
EN/IN1, PH/IN2, nSLEEP, DRVOFF,
nFAULT
0
5.5
V
fPWM
PWM frequency
EN/IN1, PH/IN2
0
25
KHz
MODE, ITRIP, SR, DIAG
0
5.5
V
IPROPI
0
5.5
V
SPI (S) variant - SPI pin voltage
SDI, SDO, nSCS, SCLK
0
VnSLEEP +
0.5
V
SPI (P) variant - SPI pin voltage
SDI, SDO, nSCS, SCLK
VCONFIG
HW variant - Configuration pin voltage
VIPROPI
Analog feedback voltage
VSPI_IOS
(1)
MIN
0
VVDD + 0.5
V
TA
Operating ambient temperature
–40
125
°C
TJ
Operating junction temperature
–40
150
°C
The over current protection function does not support short on OUTx to VM or GND above 28 V for short inductance < 1 μH.
7.4 Thermal Information
Refer Transient thermal impedance table for application related use case.
THERMAL METRIC(1)
RθJA
RθJC(top)
(1)
HVSSOP package VQFN-HR package
UNIT
Junction-to-ambient thermal resistance
31.0
48.4
°C/W
Junction-to-case(top) thermal resistance
29.1
22.3
°C/W
RθJB
Junction-to-board thermal resistance
9.3
8.1
°C/W
ΨJT
Junction-to-top characterization parameter
1.4
0.5
°C/W
ΨJB
Junction-to-board characterization parameter
9.3
7.9
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance
1.3
N/A
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
4.5 V (falling) ≤ VVM ≤ 35 V, -40°C ≤ TJ ≤ 150°C (unless otherwise noted)
For SPI (P) variant only: 4.5 V ≤ VVDD ≤ 5.5 V (unless otherwise noted)
7.5.1 Power Supply & Initialization
Refer wake up transient waveforms
PARAMETER
VVM_REV
IVMQ
12
Supply pin voltage during reverse
current
VM current in SLEEP state
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IVM = - 5 A, device in unpowered state
1.4
V
VVM = 13.5 V, VnSLEEP = 0 V or VVDD <
PORVDD_FALL, TA = 25°C
1
µA
VVM = 13.5 V, VnSLEEP = 0 V or VVDD <
PORVDD_FALL, TA = 125°C
µA
5
mA
10
mA
IVMS
VM current in STANDBY state
VVM = 13.5 V
IVDD
VDD current in ACTIVE state
SPI (P) variant
tRESET
RESET pulse filter time
Reset signal on nSLEEP pin for HW (H)
variant
5
20
µs
tSLEEP
SLEEP command filter time
Sleep signal on nSLEEP pin for HW (H)
variant
40
120
µs
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PARAMETER
TEST CONDITIONS
MIN
SLEEP command filter time
Sleep signal on nSLEEP pin for SPI (S)
variant
5
Wake-up command filter time
Wake-up signal on nSLEEP pin for HW
(H) and SPI (S) variants
tCOM
Time for communication to be available
after wake-up or power-up through VM
or VDD supply pin
Wake-up signal on nSLEEP pin or
power cycle - VVM > VMPOR_RISE or
VVDD > VDDPOR_RISE
400
µs
tREADY
Time for driver ready to be driven after
wake-up through nSLEEP pin or powerup through VM or VDD supply pin
Wake-up signal on nSLEEP pin or
power cycle - VVM > VMPOR_RISE or
VVDD > VDDPOR_RISE
1
ms
MAX
UNIT
0.65
V
tSLEEP_SPI
tWAKEUP
TYP
MAX
UNIT
20
µs
10
µs
7.5.2 Logic I/Os
PARAMETER
VIL_nSLEEP
TEST CONDITIONS
Input logic low voltage
VIH_nSLEEP Input logic high voltage
nSLEEP pin
VIHYS_nSLEE
Input hysteresis
nSLEEP pin
VIL
Input logic low voltage
DRVOFF, EN/IN1, PH/IN2 pins
VIH
Input logic high voltage
DRVOFF, EN/IN1, PH/IN2 pins
Input hysteresis
DRVOFF, EN/IN1, PH/IN2 pins
P
VIHYS
MIN
TYP
nSLEEP pin
1.55
V
200
mV
0.7
1.5
V
V
100
mV
Internal pull-down resistance on nSLEEP
Measured at min VIL level
to GND
100
400
KΩ
RPU
Internal pull-up resistance to VDD
(reverse current blocked) on DRVOFF
Measured at min VIH level
200
550
KΩ
RPD
Internal pull-down resistance to GND on
EN/IN1 and PH/IN2
Measured at max VIL level
200
500
KΩ
Sink current to GND on nFAULT pin
when asserted low
VnFAULT = 0.3 V
RPD_nSLEEP
InFAULT_PD
5
mA
7.5.3 SPI I/Os
PARAMETER
TEST CONDITIONS
Internal pull-up resistance to VDD
(reverse current blocked) on nSCS
Measured at min VIH level
Internal pull-down resistance to GND on
SDI, SCLK
Measured at max VIL level
VIL
Input logic low voltage
SDI, SCLK, nSCS pins
VIH
Input logic high voltage
SDI, SCLK, nSCS pins
Input hysteresis
SDI, SCLK, nSCS pins
Output logic low voltage
0.5 mA sink into SDO
RPU_nSCS
RPD_SPI
VIHYS
VOL_SDO
VOH_SDO
Output logic high voltage for SPI (S)
variant
Output logic high voltage for SPI (P)
variant
VOH_SDO_NL
Output logic high voltage at no load on
SDO, valid only for SPI (S) variant
MIN
TYP
MAX
UNIT
200
500
KΩ
150
500
KΩ
0.7
V
1.5
V
100
mV
0.4
V
0.5 mA source from SDO, VnSLEEP = 5
V, VVM > 7 V
4.1
V
0.5 mA source from SDO, VnSLEEP =
3.3 V, VVM > 5 V
2.7
V
0.5 mA source from SDO, VVDD = 5 V
4.5
V
No current from SDO, VnSLEEP = 5 V,
VVM > 7 V
5.5
V
No current from SDO, VnSLEEP = 3.3 V,
VVM > 5 V
3.8
V
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7.5.4 Configuration Pins - HW Variant Only
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
6 level setting for ITRIP, SR and DIAG
RLVL1OF6
Level 1 of 6
Connect to GND
10
Ω
RLVL2OF6
Level 2 of 6
+/- 10% resistor to GND
7.4
8.2
9
KΩ
RLVL3OF6
Level 3 of 6
+/- 10% resistor to GND
19.8
22
24.2
KΩ
RLVL4OF6
Level 4 of 6
+/- 10% resistor to GND
42.3
47
51.7
KΩ
RLVL5OF6
Level 5 of 6
+/- 10% resistor to GND
90
100
110
KΩ
RLVL6OF6
Level 6 of 6
Hi-Z (no connect)
250
RLVL1OF3
Level 1 of 3
Connect to GND
RLVL2OF3
Level 2 of 3
+/- 10% resistor to GND
7.4
RLVL3OF3
Level 3 of 3
Hi-Z (no connect)
250
KΩ
3 level setting for MODE
8.2
10
Ω
9
KΩ
KΩ
7.5.5 Power FET Parameters
Measured at VVM = 13.5 V
PARAMETER
TEST CONDITIONS
High-side FET on resistance, HVSSOP
package
IOUT = 3 A, TJ = 25°C
High-side FET on resistance, VQFN-HR
package
IOUT = 3 A, TJ = 25°C
Low-side FET on resistance, HVSSOP
package
IOUT = 3 A, TJ = 25°C
Low-side FET on resistance, VQFN-HR
package
IOUT = 3 A, TJ = 25°C
RHS_ON
RLS_ON
VSD
RHi-Z
Low-side & High-side FET source-drain
voltage when body diode is forward
biased
OUT resistance to GND in SLEEP or
STANDBY state, VOUTx = VVM = 13.5 V
MIN
TYP
49
IOUT = 3 A, TJ = 150°C
41.7
49
42
0.4
0.9
mΩ
mΩ
93.1
IOUT = 3 A, TJ = 150°C
mΩ
mΩ
79.8
IOUT = 3 A, TJ = 150°C
UNIT
mΩ
93.1
IOUT = 3 A, TJ = 150°C
IOUT = +/- 3 A (both directions)
MAX
mΩ
mΩ
79.8
mΩ
1.5
V
SR = 3'b000 or 3'b001 or 3'b010 or
3'b111 or LVL2 or LVL5
2
5
KΩ
SR = 3'b011 or LVL3
7
14
KΩ
SR = 3'b100 or LVL4
5
10.5
KΩ
SR = 3'b101 or LVL1
4
8.5
KΩ
SR = 3'b110 or LVL6
2.5
6
KΩ
7.5.6 Switching Parameters with High-Side Recirculation
Load = 1.5mH / 4.7 Ohm, VVM = 13.5 V, refer high-side recirculation waveform
14
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PARAMETER
TEST CONDITIONS
MIN
SR = 3'b000 or LVL2
SRLSOFF
tPD_LSOFF
Output voltage rise time, 10% - 90%
Propagation time during output voltage
rise
tDEAD_LSOFF Dead time during output voltage rise
SRLSON
tPD_LSON
Output voltage fall time, 90% - 10%
Propagation time during output voltage
fall
tDEAD_LSON Dead time during output voltage fall
MatchSRLS
Output voltage rise and fall slew rate
matching
TYP
MAX
UNIT
1.6
V/µs
SR = 3'b001 (SPI only)
5
V/µs
SR = 3'b010 (SPI only)
8
V/µs
SR = 3'b011 or LVL3
13.3
V/µs
SR = 3'b100 or LVL4
19
V/µs
SR = 3'b101 or LVL1
24.5
V/µs
SR = 3'b110 or LVL6
36
V/µs
SR = 3'b111 or LVL5
47
V/µs
SR = 3'b000 or LVL2
1
µs
SR = 3'b001 (SPI only)
0.9
µs
SR = 3'b010 (SPI only)
0.8
µs
SR = 3'b011 or LVL3
0.7
µs
SR = 3'b100 & 3'b101 or LVL4 & LVL1
0.6
µs
SR = 3'b110 & 3'b111 or LVL6 & LVL5
0.5
µs
All SRs
0.9
µs
SR = 3'b000 or LVL2
1.6
V/µs
SR = 3'b001 (SPI only)
5
V/µs
SR = 3'b010 (SPI only)
8
V/µs
SR = 3'b011 or LVL3
13.3
V/µs
SR = 3'b100 or LVL4
19
V/µs
SR = 3'b101 or LVL1
24.5
V/µs
SR = 3'b110 or LVL6
36
V/µs
SR = 3'b111 or LVL5
47
V/µs
SR = 3'b000 or LVL2
0.2
µs
SR = 3'b001 (SPI only)
0.2
µs
SR = 3'b010 (SPI only)
0.2
µs
SR = 3'b011 or LVL3
0.4
µs
SR = 3'b100 or 3'b101 or LVL4 or LVL1
0.3
µs
SR = 3'b110 & 3'b111 or LVL6 & LVL5
0.2
µs
SR = 3'b000 or LVL2
1.5
µs
SR = 3'b001 or 3'b010 (SPI only)
0.6
µs
SR = 3'b011 or LVL3
0.7
µs
All other SRs
0.6
µs
All SRs
-20
+20
%
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7.5.7 Switching Parameters with Low-Side Recirculation
Load = 1.5 mH / 4.7 Ohm, VVM = 13.5 V, refer low-side recirculation waveform
PARAMETER
SRHSON
TEST CONDITIONS
Output voltage rise time, 10% - 90%
All SRs
Propagation time during output voltage
rise
tDEAD_HSON Dead time during output voltage rise
SRHSOFF
tPD_HSOFF
Output voltage fall time, 90% - 10%
Propagation time during output voltage
fall
tDEAD_HSOFF Dead time during output voltage fall
tBLANK
16
Current regulation blanking time after
OUT slewing for current sense output to
settle (Valid for only for LS recirculation)
TYP
MAX
UNIT
8
V/µs
3.1
µs
SR = 3'b001 (SPI only)
2
µs
SR = 3'b010 (SPI only)
1.7
µs
SR = 3'b011 or LVL3
1.2
µs
All other SRs
0.9
µs
SR = 3'b000 or LVL2
1.5
µs
SR = 3'b001 (SPI only)
1
µs
SR = 3'b010 (SPI only)
0.8
µs
All other SRs
SR = 3'b000 or LVL2
tPD_HSON
MIN
0.45
µs
SR = 3'b000 or 3'b001 or 3'b010 or
LVL2
43
V/µs
SR = 3'b011 or LVL3
14
V/µs
SR = 3'b100 or LVL4
19
V/µs
SR = 3'b101 or LVL1
24
V/µs
SR = 3'b110 or LVL6
34
V/µs
SR = 3'b111 or LVL5
43
V/µs
All SRs
0.25
µs
All SRs
0.2
µs
All SRs
3.4
µs
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7.5.8 IPROPI & ITRIP Regulation
PARAMETER
AIPROPI
AI_ERR
AI_ERR
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Current scaling factor, HVSSOP
package
3075
A/A
Current scaling factor, VQFN-HR
package
3070
A/A
Current scaling factor error, VQFN-HR
package
Current scaling factor error, HVSSOP
package
0.8 A < IOUT < 4.3 A
-5
+5
%
0.2 A < IOUT ≤ 0.8 A
-20
+20
%
0.1 A < IOUT ≤ 0.2 A
-50
+50
%
0.8 A < IOUT < 4.3 A
-6
+6
%
0.2 A < IOUT ≤ 0.8 A
-20
+20
%
0.1 A < IOUT ≤ 0.2 A
-50
+50
%
AI_ERR_M
Current matching between the two halfbridges, VQFN-HR package
IOUT > 0.8 A
-2
+2
%
AI_ERR_M
Current matching between the two halfbridges, HVSSOP package
IOUT > 0.8 A
-5
+5
%
Offset current on IPROPI at no load
current
IOUT = 0 A
15
µA
Bandwidth of the IPROPI internal sense
circuit
No external capacitor on IPROPI.
400
5.5
V
ITRIP = 3'b001 or LVL2
1.06
1.18
1.3
V
ITRIP = 3'b010 (SPI only)
1.27
1.41
1.55
V
ITRIP = 3'b011 (SPI only)
1.49
1.65
1.82
V
ITRIP = 3'b100 or LVL3
1.78
1.98
2.18
V
ITRIP = 3'b101 or LVL4
2.08
2.31
2.54
V
ITRIP = 3'b110 or LVL5
2.38
2.64
2.9
V
ITRIP = 3'b111 or LVL6
2.67
2.97
3.27
V
TOFF = 2'b00 (SPI only)
16
20
25
µs
TOFF = 2'b01 (SPI). Only choice for
HW
24
30
36
µs
TOFF = 2'b10 (SPI only)
33
40
48
µs
TOFF = 2'b11 (SPI only)
41
50
61
µs
MIN
TYP
MAX
UNIT
OffsetIPROPI
BWIPROPI
VIPROPI_LIM Internal clamping voltage on IPROPI
VITRIP_LVL
tOFF
KHz
4.5
Voltage limit on VIPROPI to trigger TOFF
cycle for ITRIP regulation
ITRIP regulation - off time
7.5.9 Over Current Protection (OCP)
PARAMETER
IOCP_HS
IOCP_LS
tOCP
TEST CONDITIONS
Over current protection threshold on the
high side
Over current protection threshold on the
low side
OCP_SEL = 2'b00 (SPI), Only choice
for HW
12
24
A
OCP_SEL = 2'b10 (SPI only)
9
18
A
OCP_SEL = 2'b01 (SPI only)
6
14
A
OCP_SEL = 2'b00 (SPI), Only choice
for HW
12
24
A
OCP_SEL = 2'b10 (SPI only)
9
18
A
OCP_SEL = 2'b01 (SPI only)
6
14
A
Over current protection deglitch time
TOCP_SEL = 2'b00 (SPI), Only choice
for HW
4.5
6
7.3
µs
Over current protection deglitch time
TOCP_SEL = 2'b01 (SPI only)
2.2
3
4.1
µs
Over current protection deglitch time
TOCP_SEL = 2'b10 (SPI only)
1.1
1.5
2.3
µs
Over current protection deglitch time
TOCP_SEL = 2'b11 (SPI only)
0.15
0.2
0.4
µs
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7.5.10 Over Temperature Protection (TSD)
PARAMETER
TTSD
Thermal shutdown temperature
THYS
Thermal shutdown hysteresis
tTSD
Thermal shutdown deglitch time
TEST CONDITIONS
MIN
TYP
MAX
UNIT
155
170
185
°C
30
°C
10
12
19
µs
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VMOV_SEL = 2'b00 (SPI), Only choice
in HW variant
33.6
37
V
VMOV_SEL = 2'b01 (SPI only)
28
31
V
VMOV_SEL = 2'b10 (SPI only)
18
21
V
7.5.11 Voltage Monitoring
PARAMETER
VVMOV
VM over voltage threshold while rising
VVMOV_HYS VM over voltage hysteresis
0.6
tVMOV
VM over voltage deglitch time
10
VVMUV
VM under voltage threshold while falling
4.2
VVMUV_HYS VM under voltage hysteresis
tVMUV
12
V
19
µs
4.5
V
200
VM under voltage deglitch time
8
12
mV
19
µs
VMPOR_FALL
VM voltage at which device goes into
POR
Applicable for HW & SPI (S) variant
3.6
V
VMPOR_RISE
VM voltage at which device comes out of
Applicable for HW & SPI (S) variant
POR
3.9
V
VDDPOR_FAL VDD voltage at which device goes into
POR
L
Applicable for SPI (P) variant
3.5
V
VDDPOR_RIS VDD voltage at which device comes out
of POR
E
Applicable for SPI (P) variant
3.8
V
MAX
UNIT
7.5.12 Load Monitoring
PARAMETER
TEST CONDITIONS
MIN
TYP
Off-state diagnostics (OLP)
RS_GND
Resistance on OUT to GND that will be
detected as short, All modes
1
KΩ
RS_VM
Resistance on OUT to VM that will be
detected as short , All modes
1
KΩ
ROPEN_FB
Resistance between OUTx that will be
detected as open, PH/EN or PWM mode
ROPEN_LS
Resistance on OUT to GND that will be
detected as open , Independent mode
ROPEN_HS
Resistance on OUT to VM that will be
detected as open, Independent mode
VOLP_REFH
OLP Comparator Reference High
2.65
V
VOLP_REFL
OLP Comparator Reference Low
2
V
1.5
KΩ
Valid for low-side load
2
KΩ
Valid for high-side load, VVM = 13.5 V
10
KΩ
ROLP_PU
Internal pull-up resistance on OUT to
VDD during OLP
VOUTx = VOLP_REFH + 0.1V
1
KΩ
ROLP_PD
Internal pull-down resistance on OUT to
GND during OLP
VOUTx = VOLP_REFL - 0.1V
1
KΩ
SPI variant only - On-state diagnostics (OLA)
IPD_OLA
18
Internal sink current on OUTx to
GND during dead-time in high-side
recirculation
SR = 3'b000 or 3'b001 or 3'b010 or
3'b111 or LVL2 or LVL5
2.5
5
mA
SR = 3'b011 or LVL3
0.8
2
mA
SR = 3'b100 or LVL4
1.2
2.5
mA
SR = 3'b101 or LVL1
1.5
3
mA
SR = 3'b110 or LVL6
2.2
4
mA
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PARAMETER
VOLA_REF
TEST CONDITIONS
MIN
Comparator Reference with respect to
VM used for OLA
TYP
MAX
0.25
UNIT
V
7.5.13 Fault Retry Setting
Refer to retry setting waveform
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
5
6.1
ms
tRETRY
Automatic driver retry time
Fault reaction set to RETRY
4.1
tCLEAR
Fault free operation time to auto-clear
from over current event
Fault reaction set to RETRY
85
200
µs
tCLEAR_TSD
Fault free operation time to auto-clear
from over temperature event
Fault reaction set to RETRY
4.2
6.7
ms
7.5.14 Transient Thermal Impedance & Current Capability
Information based on thermal simulations
Table 7-1. Transient Thermal Impedance (RθJA) and Current Capability - full-bridge
Current [A](2)
RθJA [°C/W](1)
PART NUMBER
PACKA
GE
0.1 sec
1 sec
10 sec
DC
0.1 sec
1 sec
10 sec
DC
10 sec
DC
DRV8243-Q1
VQFNHR
7.3
13
17.5
34.2
7.5
5.6
4.8
3.5
4.4
3.0
DRV8243-Q1
HVSSOP
5.8
10.5
15.3
32.4
7.8
5.8
4.8
3.3
4.4
2.9
(1)
without PWM(3)
with PWM(4)
Based on thermal simulations using 40 mm x 40 mm x 1.6 mm 4 layer PCB – 2 oz Cu on top and bottom layers, 1 oz Cu on internal
planes with 0.3 mm thermal via drill diameter, 0.025 mm Cu plating, 1 minimum mm via pitch.
Estimated transient current capability at 85 °C ambient temperature for junction temperature rise up to 150°C
Only conduction losses (I2R) considered
Switching loss roughly estimated by the following equation:
(2)
(3)
(4)
PSW = VVM x ILoad x fPWM x VVM/SR, where VVM = 13.5 V, fPWM = 20 KHz, SR = 23 V/µs
(1)
7.6 SPI Timing Requirements
MIN
TYP
MAX
UNIT
tSCLK
SCLK minimum period(1)
100
ns
tSCLKH
SCLK minimum high time
50
ns
tSCLKL
SCLK minimum low time
50
ns
tHI_nSCS
nSCS minimum high time
300
ns
tSU_nSCS
nSCS input setup time
25
ns
tH_nSCS
nSCS input hold time
25
ns
tSU_SDI
SDI input data setup time
25
ns
tH_SDI
SDI input data hold time
25
ns
tEN_SDO
SDO enable delay
time(1)
35
ns
tDIS_SDO
SDO disable delay time(1)
100
ns
(1)
SPI (S) variant: SDO delay times are valid only with SDO external load of 5 pF. With a 20 pF load on SDO, there is an additional
delay on SDO, which results in a 25% increase in SCLK minimum time, limiting the SCLK to a maximum of 8 MHz. There is NO such
limitation for the SPI (P) variant.
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tHI_nSCS
tH_nSCS
tSU_nSCS
nSCS
tSCLK
SCLK
tSCLKH
SDI
DON’T
X CARE
tSCLKL
X DON’T CARE
LSB
MSB
tSU_SDI tH_SDI
tDIS_SDO
SDO
HI-Z
Z
LSB
MSB
tEN_SDO
Z HI-Z
Write Command
executed by device
SDI capture point
SDO propogate point
Figure 7-1. SPI Peripheral-Mode Timing Definition
20
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7.7 Switching Waveforms
This section illustrates the switching transients for an inductive load due to external PWM or internal ITRIP
regulation.
7.7.1.1 High-Side Recirculation
LOAD
LOAD
1, 2
3
1
2
3
4
LOAD
LOAD
4, 5, 6
7
5
Isense OK
6
tDEAD_LSOFF
OUT1
LOAD
8, 1
7
8
1
tDEAD_LSON
VM + VD(FET BODY DIODE)
VM
90%
tPD_LSON ~SRHSOFF
~SRHSON
SRLSOFF
90%
Accuracy not
applicable
Accuracy not
applicable
High side recirculaon
SRLSON
Slew rate controlled by Low Side Driver (SRLSON & SRLSOFF)
10%
10%
OUT2
GND
tPD_LSOFF
“fPWM” @ duty cycle “D”
EN/IN1
PH/IN2
E.g. Full bridge in PH/EN mode, OUT1 is held high, while OUT2 is switching
Figure 7-2. Output Switching Transients for a H-Bridge with High-Side Recirculation
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LOAD
LOAD
1, 2
3
1
2
3
4
LOAD
LOAD
4, 5, 6
7
5
6
LOAD
8, 1
7
8
1
Isense NOT OK
tDEAD_LSOFF
tDEAD_LSON
VM + VD(FET BODY DIODE)
VM
90%
90%
tPD_LSON ~SRHSOFF
~SRHSON
Accuracy not
applicable
Accuracy not
applicable
High side recirculaon
SRLSON
Slew rate controlled by Low Side Driver (SRLSON & SRLSOFF)
SRLSOFF
10%
10%
OUT1
GND
tPD_LSOFF
“fPWM” @ duty cycle “1-D”
IN1
E.g. High side load in Independent mode, OUT1 is switching
Figure 7-3. Output Switching Transients for a Half-Bridge with High-Side Recirculation
7.7.1.2 Low-Side Recirculation
LOAD
LOAD
1, 2
3
1
2
3
4
Isense OK
LOAD
LOAD
4, 5, 6
7
5
6
7
LOAD
8, 1
8
1
Isense NOT OK
Isense OK
VM
OUT1
90%
90%
tPD_HSOFF
Low side recirculaon
SRHSOFF
SRHSON
Slew rate controlled by High Side Driver (SRHSON & SRHSOFF)
10%
~SRLSON
Accuracy not applicable
~SRLSOFF
Accuracy not applicable
tBLANK
10%
GND
GND - VD(FET BODY DIODE)
tDEAD_HSOFF
tDEAD_HSON
tPD_HSON
“fPWM” @ duty cycle “D”
IN1
E.g. Low side load in Independent mode, OUT1 is switching
Figure 7-4. Output Switching Transients for a half-bridge with Low-Side Recirculation
22
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7.7.2 Wake-up Transients
7.7.2.1 HW Variant
tRESET
tWAKEUP
tREADY
nSLEEP
tCOM
t4
t5
t3
t2
t1
t0
nFAULT
nSLEEP RESET
pulse ACK
Figure 7-5. Wake-up from SLEEP State to STANDBY State Transition for HW Variant
Hand shake between controller and device during wake-up as follows:
• t0: Controller - nSLEEP asserted high to initiate device wake-up
• t1: Device internal state - Wake-up command registered by device (end of Sleep state)
• t2: Device – nFAULT asserted low to acknowledge wake-up and indicate device ready for communication
• t3: Device internal state - Initialization complete
• t4 (any time after t2): Controller – Issue nSLEEP reset pulse to acknowledge device wake-up
• t5: Device - nFAULT de-asserted as an acknowledgment of nSLEEP reset pulse. Device in STANDBY state
tREADY
VM
VVMUV_HYST
VVMUV
VMPOR_RISE
VMPOR_FALL
Internal
nPOR
tRESET
nSLEEP=
1'b1
tCOM
t4
t5
t3
t2
t1
t0
nFAULT
nSLEEP RESET
pulse ACK
Figure 7-6. Power-up to STANDBY State Transition for HW Variant
Hand shake between controller and device during power-up as follows:
• t0: Device internal state - POR asserted based on under voltage of internal LDO (VM dependent)
• t1: Device internal state – POR de-asserted based on recovery of internal LDO voltage
• t2: Device – nFAULT asserted low to acknowledge wake-up and indicate device ready for communication
• t3: Device internal state - Initialization complete
• t4 (any time after t2): Controller – Issue nSLEEP reset pulse to acknowledge device power-up
• t5: Device - nFAULT de-asserted as an acknowledgment of nSLEEP reset pulse. Device in STANDBY state
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7.7.2.2 SPI Variant
CLR_FLT
cmd
tWAKEUP
tREADY
nSLEEP
tCOM
t4
t5
t3
t0
t1
t2
nFAULT
CLR_FLT
cmd ACK
Figure 7-7. Wake-up from SLEEP State to STANDBY State Transition for SPI (S) Variant
Hand shake between controller and device during a wake-up transient as follows:
• t0: Controller - nSLEEP asserted high to initiate device wake-up
• t1: Device internal state - Wake-up command registered by device (end of Sleep state)
• t2: Device – nFAULT asserted low to acknowledge wake-up and indicate device ready for communication
• t3: Device internal state - Initialization complete
• t4 (Any time after t2): Controller – Issue CLR_FLT command through SPI to acknowledge device wake-up
• t5: Device - nFAULT de-asserted as an acknowledgment of nSLEEP reset pulse. Device in STANDBY state
tREADY
VM
VVMUV_HYST
VMPOR_RISE
VMPOR_FALL
CLR_FLT
cmd
VVMUV
Internal
nPOR
nSLEEP=
1'b1
tCOM
t5
t4
t3
t2
t1
t0
nFAULT
CLR_FLT
cmd ACK
Figure 7-8. Power-up to STANDBY State Transition for SPI (S) Variant
Hand shake between controller and device during power-up as follows:
• t0: Device internal state - POR asserted based on under voltage of internal LDO (VM dependent)
• t1: Device internal state – POR de-asserted based on recovery of internal LDO voltage
• t2: Device – nFAULT asserted low to acknowledge wake-up and indicate device ready for communication
• t3: Device internal state - Initialization complete
• t4 (Any time after t2): Controller – Issue CLR_FLT command through SPI to acknowledge device power-up
• t5: Device - nFAULT de-asserted as an acknowledgment of nSLEEP reset pulse. Device in STANDBY state
24
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tREADY
VDD
CLR_FLT
cmd
VDDPOR_RISE
VDDPOR_FALL
Internal
nPOR
tCOM
t4
t5
t3
t2
t1
t0
nFAULT
CLR_FLT
cmd ACK
Figure 7-9. Power-up to STANDBY State Transition for SPI (P) Variant
Hand shake between controller and device during power-up as follows:
• t0: Device internal state - POR asserted based on under voltage on VDD (external supply)
• t1: Device internal state – POR de-asserted based on recovery of voltage on VDD (external supply)
• t2: Device – nFAULT asserted low to acknowledge wake-up and indicate device ready for communication
• t3: Device internal state - Initialization complete
• t4 (Any time after t2): Controller – Issue CLR_FLT command through SPI to acknowledge device power-up
• t5: Device - nFAULT de-asserted as an acknowledgment of nSLEEP reset pulse. Device in STANDBY state
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7.7.3 Fault Reaction Transients
7.7.3.1 Retry setting
Valid for both SPI and HW variants
tCLEAR
nFAULT
tOCP
tOCP
tRETRY
tOCP
IOCP
tRETRY
I(VM)
ILOAD
t6
t5
t4
t3
t2
t1
IVMQ
External short to ground fault
Figure 7-10. Fault reaction with RETRY setting (shown for OCP occurrence on high-side when OUT is
shorted to ground)
Short occurrence and recovery scenario with RETRY setting:
• t1: An external short occurs.
• t2: OCP (Over Current Protection) fault confirmed after tOCP, output disabled, nFAULT asserted low to
indicate fault.
• t3: Device automatically attempts retry (auto retry) after tRETRY. Each time output is briefly turned on to
confirm short occurrence and then immediately disabled after tOCP. nFAULT remains asserted low through
out. Cycle repeats till driver is disabled by the user or external short is removed, as illustrated further. Note
that, in case of a TSD (Thermal Shut Down) event, automatic retry time depends on the cool off based on
thermal hysteresis.
• t4: The external short is removed.
• t5: Device attempts auto retry. But this time, no fault occurs and device continues to keep the output enabled.
• t6: After a fault free operation for a period of tCLEAR is confirmed, nFAULT is de-asserted.
• SPI variant only – Fault status remains latched till a CLR_FLT command is issued.
Note that, in the event of an output short to ground causing the high-side OCP fault detection, IPROPI pin will
continue to be pulled up to VIPROPI_LIM voltage to indicate this type of short, while the output is disabled. This
is especially useful for the HW (H) variant to differentiate the indication of a short to ground fault from the other
faults.
26
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7.7.3.2 Latch setting
Valid for both SPI and HW variants
CLR_FLT CMD (SPI) /
nSLEEP RESET PULSE (HW)
nFAULT
tOCP
tOCP
IOCP
I(VM)
ILOAD
t6
t5
t4
t3
t2
t1
IVMQ
External short to ground fault
Figure 7-11. Fault reaction with Latch setting (shown for OCP occurrence on high-side when OUT is
shorted to ground)
Short occurrence and recovery scenario with LATCH setting:
• t1: An external short occurs.
• t2: OCP (Over Current Protection) fault confirmed after tOCP, output disabled, nFAULT asserted low to
indicate fault.
• t3: A CLR_FLT command (SPI variant) or nSLEEP RESET Pulse (HW variant) issued by controller. nFAULT
is de-asserted and output is enabled. OCP fault is detected again and output is disabled with nFAULT
asserted low.
• t4: The external short is removed.
• t5: A CLR_FLT command (SPI variant) or nSLEEP RESET Pulse (HW variant) issued by controller. nFAULT
is de-asserted and output is enabled. Normal operation resumes.
• SPI variant only – Fault status remains latched till a CLR_FLT command is issued.
Note that, in the event of an output short to ground causing the high-side OCP fault detection, IPROPI pin will
continue to be pulled up to VIPROPI_LIM voltage to indicate this type of short, while the output is disabled. This
is especially useful for the HW (H) variant to differentiate the indication of a short to ground fault from the other
faults.
7.8 Typical Characteristics
20
80
FET RON [m]
70
LS FET - VQFN-HR
HS FET - VQFN-HR
LS FET - HVSSOP
HS FET - HVSSOP
65
60
55
50
45
40
10
5
0
-5
-10
-15
-20
35
30
-40
OUT1+
OUT2+
OUT1OUT2-
15
AIPROPI 6 sigma Error [%]
75
-20
0
20
40
60
80 100
Temperature [C]
120
140
160
Figure 7-12. RHS_ON & RLS_ON vs Temperature at
VVM = 13.5 V
-25
0.1
0.2
0.3 0.4 0.5 0.7
1
Load Current [A]
2
3
4
5
Figure 7-13. AIPROPI Gain Error vs Load Current at
VVM = 13.5 V
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20.5
LS OCP Threshold [A]
19.5
18.5
17.5
OCP_SEL = 0
OCP_SEL = 2
OCP_SEL = 1
16.5
15.5
14.5
13.5
12.5
11.5
-40
-20
0
20
40
60
80 100
Temperature [C]
120
140
160
Figure 7-14. LS OCP Threshold vs Temperature at
VVM = 13.5 V
Figure 7-15. HS OCP Threshold vs Temperature at
VVM = 13.5 V
4
3.75
Standby current [mA]
3.5
3.25
3
VM
VM
VM
VM
2.75
2.5
5V
13.5V
25V
35V
2.25
2
1.75
1.5
1.25
-40
-20
0
20
40
60
80 100
Temperature [C]
120
140
160
Figure 7-16. Current on VM in STANDBY state vs
Temperature
Figure 7-17. Current on VM in SLEEP state vs
Temperature
100
100
Measured OUT duty cycle [%]
80
70
60
50
=
=
=
=
=
=
=
=
3'b000
3'b001
3'b010
3'b011
3'b100
3'b101
3'b110
3'b111
40
30
20
10
80
70
60
50
=
=
=
=
=
=
=
=
3'b000
3'b001
3'b010
3'b011
3'b100
3'b101
3'b110
3'b111
40
30
20
10
0
0
0
10
20
30
40
50
60
70
80
90
Input Duty Cycle [%] on EN/IN1 pin at 5 KHz PWM
100
Figure 7-18. Measured Duty Cycle vs Input Duty
Cycle at PWM frequency of 5 KHz at VVM = 13.5 V
for HS recirculation
28
SR
SR
SR
SR
SR
SR
SR
SR
90
Measured OUT duty cycle [%]
SR
SR
SR
SR
SR
SR
SR
SR
90
0
10
20
30
40
50
60
70
80
90
Input Duty Cycle [%] on EN/IN1 pin at 20 KHz PWM
100
Figure 7-19. Measured Duty Cycle vs Input Duty
Cycle at PWM frequency of 20 KHz at VVM = 13.5 V
for HS recirculation
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8 Detailed Description
8.1 Overview
The DRV824x-Q1 family of devices are brushed DC motor drivers that operate from 4.5 to 35-V supporting a
wide range of output load currents for various types of motors and loads. The devices integrate an H-bridge
output power stage that can be operated in different control modes set by the MODE function. This allows for
driving a single bidirectional brushed DC motor or two unidirectional brushed DC motors. The devices integrate
a charge pump regulator to support efficient high-side N-channel MOSFETs with 100% duty cycle operation.
The devices operate from a single power supply input (VM) which can be directly connected to a battery or DC
voltage supply. The devices also provide a low power mode to minimize current draw during system inactivity.
The devices are available in two interface variants 1. HW variant - Hardwired interface variant is available for easy device configuration. Due to the limited number
of available pins in the device, this variant offers fewer configuration and fault reporting capability compared
to the SPI variant.
2. SPI variant - A standard 4-wire serial peripheral interface (SPI) with daisy chain capability allows flexible
device configuration and detailed fault reporting to an external controller. The feature differences of the SPI
and HW variants can be found in the device comparison section. The SPI interface is available in two device
variant choices, as stated below:
a. SPI (S) variant - The power supply for the digital block is provided by an internal LDO regulator sourced
from VM supply. The nSLEEP pin is a high impedance input pin.
b. SPI (P) variant - This allows for an external supply input to the digital block of the device through a VDD
pin. The nSLEEP pin is replaced by this VDD supply pin. This prevents device reset (brown out) during a
VM under voltage condition.
The DRV824x family of devices provide a load current sense output using current mirrors on the high-side
power MOSFETs. The IPROPI pin sources a small current that is proportional to the current in the high-side
MOSFETs (current sourced out of the OUTx pin). This current can be converted to a proportional voltage using
an external resistor (RIPROPI). Additionally, the devices also support a fixed off-time PWM chopping scheme for
limiting current to the load. The current regulation level can be configured through the ITRIP function.
A variety of protection features and diagnostic functions are integrated into the device. These include supply
voltage monitors (VMOV & VMUV), , off-state (Passive) diagnostics (OLP), on-state (Active) diagnostics (OLA) SPI variant only, overcurrent protection (OCP) for each power FET and over-temperature shutdown (TSD). Fault
conditions are indicated on the nFAULT pin. The SPI variant has additional communication protection features
such as frame errors and lock features for configuration register bits and driver control bits.
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8.2 Functional Block Diagram
8.2.1 HW Variant
0.1 μF
VM
PSM
Gate Driver
VVCP
VCP
Charge
Pump
ISNS1
HS
VDD
Internal
LDO & Bias
GND
Full Bridge load
(PH/EN or PWM mode)
OUT1
VDD
Supply
Monitors
LS LOAD
VM
Low Side load to GND
(Independent mode)
HS LOAD
High Side load to VM
(Independent mode)
LS
GND
VDD
Oscillator
DRVOFF
FB LOAD
Thermal Shut Down (TSD)
EN/IN1
Digital IOs
PH/IN2
Off-state Diagnostics (OLP)
VM
Gate Driver
VVCP
ISNS2
HS
HS LOAD
nSLEEP
Digital Core
Over Current Protection (OCP)
OUT2
LS LOAD
VDD
MODE
LS
ITRIP
SR
GND
Impedance
Estimator
RnFAULT
nFAULT
DIAG
ISNS1
ISNS2
IPROPI
RIPROPI
Figure 8-1. Functional Block Diagram - HW Variant
8.2.2 SPI Variant
There are two variants for the SPI interface - SPI (S) variant and SPI (P) variant as shown below.
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High Side load to VM
(Independent mode)
VM
PSM
Gate Driver
VVCP
VCP
Charge
Pump
HS
VDD
Internal
LDO & Bias
GND
ISNS1
HS LOAD
0.1 μF
Full Bridge load
(PH/EN or PWM mode)
OUT1
VDD
Supply
Monitors
LS LOAD
VM
Low Side load to GND
(Independent mode)
LS
GND
VDD
DRVOFF
FB LOAD
Oscillator
Thermal Shut Down (TSD)
nSLEEP
EN/IN1
PH/IN2
VM
Gate Driver
VVCP
ISNS2
HS
Digital IOs
OUT2
VDD
LS LOAD
VDD
nSCS
Load Diagnostics (OLP & OLA)
HS LOAD
Digital Core
Over Current Protection (OCP)
LS
GND
SDI
RnFAULT
nFAULT
SCLK
ISNS1
SDO
ISNS2
IPROPI
RIPROPI
Figure 8-2. Functional Block Diagram - SPI (S) Variant
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High Side load to VM
(Independent mode)
VM
PSM
Gate Driver
VVCP
VCP
0.1 μF
Charge
Pump
VDD
Full Bridge load
(PH/EN or PWM mode)
ISNS1
HS
Bias
OUT1
VDD
GND
Supply
Monitors
LS LOAD
0.1 μF
HS LOAD
VM
Low Side load to GND
(Independent mode)
LS
GND
Oscillator
FB LOAD
VDD
Thermal Shut Down (TSD)
Over Current Protection (OCP)
EN/IN1
PH/IN2
Load Diagnostics (OLP & OLA)
VM
Gate Driver
VVCP
ISNS2
HS
OUT2
VDD
VDD
LS LOAD
Digital IOs
nSCS
HS LOAD
Digital Core
DRVOFF
LS
GND
SDI
RnFAULT
nFAULT
SCLK
ISNS1
SDO
ISNS2
IPROPI
RIPROPI
Figure 8-3. Functional Block Diagram - SPI (P) Variant
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8.3 Feature Description
8.3.1 External Components
Section 8.3.1.1 and Section 8.3.1.2 contain the recommended external components for the device.
8.3.1.1 HW Variant
Table 8-1. External Components Table for HW Variant
Component
PIN
Recommendation
CVM1
VM
0.1 µF, low ESR ceramic capacitor to GND rated for VM
CVM2
VM
Local bulk capacitor to GND, 10 µF or higher, rated for VM to handle load transients. Refer the
section on bulk capacitor sizing.
RIPROPI
IPROPI
Typically 500 - 5000 Ω 0.063 W resistor to GND, depending on the controller ADC dynamic range.
Pin can be shorted to GND if ITRIP and IPROPI function is not needed.
CIPROPI
IPROPI
Optional 10 - 100nF, 6.3 V capacitor to GND to slow down the ITRIP regulation loop. Refer Over
Current Protection (OCP) section.
RnFAULT
nFAULT
Typically 1KΩ - 10 KΩ, 0.063 W pull-up resistor to controller supply.
RMODE
MODE
Open or short to GND or 0.063 W 10% resistor to GND depending on setting. Refer MODE table.
RSR
SR
Open or short to GND or 0.063 W 10% resistor to GND depending on setting. Refer SR section.
RITRIP
ITRIP
Open or short to GND or 0.063 W 10% resistor to GND depending on setting. Refer ITRIP table.
RDIAG
DIAG
Open or short to GND or 0.063 W 10% resistor to GND depending on setting. Refer DIAG section.
8.3.1.2 SPI Variant
Table 8-2. External Components Table for SPI Variant
Component
PIN
Recommendation
CVM1
VM
0.1 µF, low ESR ceramic capacitor to GND rated for VM
CVM2
VM
Local bulk capacitor to GND, 10 µF or higher, rated for VM to handle load transients. Refer the
section on bulk capacitor sizing.
RIPROPI
IPROPI
Typically 500 - 5000 Ω 0.063 W resistor to GND, depending on the controller ADC dynamic range.
Pin can be shorted to GND if ITRIP and IPROPI function is not needed.
CIPROPI
IPROPI
Optional 10 - 100nF, 6.3 V capacitor to GND to slow down the ITRIP regulation loop. Refer Over
Current Protection (OCP) section.
RnFAULT
nFAULT
Typically 1KΩ - 10 KΩ, 0.063 W pull-up resistor to controller supply. If nFAULT signaling is not
used, this pin can be short to GND or left open.
CVDD
VDD
0.1 µF, 6.3 V, low ESR ceramic capacitor to GND. This is applicable for the SPI (P) variant only.
8.3.2 Bridge Control
The DRV824x-Q1 family of devices provides three separate modes to support different control schemes with the
EN/IN1 and PH/IN2 pins. The control mode is selected through the MODE setting. MODE is a 3-level setting
based on the MODE pin for the HW variant or S_MODE bits in the CONFIG3 register for the SPI variant as
summarized in Table 8-3:
Table 8-3. Mode table
MODE pin
S_MODE bits
Device Mode
Description
RLVL1OF3
2'b00
PH/EN mode
full-bridge mode where EN/IN1 is the PWM input,
PH/IN2 is the direction input
RLVL2OF3
2'b01
Independent mode
Independent control for 2 half-bridges
RLVL3OF3
2'b10, 2b'11
PWM mode
full-bridge mode where EN/IN1 and PH/IN2 control the
PWM respectively depending on the direction
In the HW variant, MODE pin is latched during device initialization following power-up or wake-up from sleep.
Update during operation is blocked.
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In the SPI variant of the device, the mode setting can be changed anytime the SPI communication is available by
writing to the S_MODE bits. This change is immediately reflected.
The inputs can accept static or pulse-width modulated (PWM) voltage signals for either 100% or PWM drive
modes. The device input pins can be powered before VM is applied. By default, the nSLEEP and DRVOFF
pins have an internal pull-down and pull-up resistor respectively, to ensure the outputs are Hi-Z if no inputs are
present. Both the EN/IN1 and PH/IN2 pins also have internal pull down resistors. The sections below show the
truth table for each control mode.
The device automatically generates the optimal dead-time needed during transitioning between the high-side
and low-side FET on the switching half-bridge. This timing is based on internal FET gate-source voltage
feedback. No external timing is required. This scheme ensures minimum dead time, while guaranteeing no
shoot-through current.
Note
1. The SPI variant also provides additional control through the SPI_IN register bits. Refer to Register - Pin control.
2. For the SPI (P) variant, ignore the nSLEEP column in the control table as there is no nSLEEP pin.
Internally, nSLEEP = 1, always. The control table is valid when VDD > VDDPOR level.
8.3.2.1 PH/EN mode
In this mode, the two half-bridges are configured to operate as a full-bridge. EN/IN1 is the PWM input and
PH/IN2 is the direction input. For load illustration, refer the Load Summary section.
Table 8-4. Control table - PH/EN mode
nSLEEP
DRVOFF
EN/IN1
PH/IN2
OUT1
OUT2
IPROPI
0
X
X
X
Hi-Z
Hi-Z
No current
SLEEP
1
1
0
0
Hi-Z
Hi-Z
No current
STANDBY
1
1
1
0
1
1
0
1
No current
STANDBY
1
1
1
1
1
0
0
X
H
H
ISNS1 or ISNS2(1)
ACTIVE
H
ISNS2
ACTIVE
L(2)
ISNS1
ACTIVE
(1)
(2)
Refer Off-state diagnostics table
1
0
1
0
L(2)
1
0
1
1
H
Device State
Current sourcing out of the device (VM → OUTx → Load)
If internal ITRIP regulation is enabled and ITRIP level is reached, then OUTx is forced "H" for a fixed time
8.3.2.2 PWM mode
In this mode, the two half-bridges are configured to operate as a full-bridge. EN/IN1 provides the PWM input
in one direction, while PH/IN2 provides the PWM in the other direction. For load illustration, refer the Load
Summary section.
Table 8-5. Control table - PWM mode
34
nSLEEP
DRVOFF
EN/IN1
PH/IN2
OUT1
OUT2
IPROPI
0
X
X
X
Hi-Z
Hi-Z
No current
SLEEP
1
1
0
0
Hi-Z
Hi-Z
No current
STANDBY
1
1
1
0
No current
STANDBY
1
1
0
1
No current
STANDBY
1
1
1
1
1
0
0
0
H
Refer Off-state diagnostics table
1
0
0
1
L(2)
1
0
1
0
H
Device State
No current
STANDBY
H
ISNS1 or ISNS2(1)
ACTIVE
H
ISNS2
ACTIVE
L(2)
ISNS1
ACTIVE
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Table 8-5. Control table - PWM mode (continued)
nSLEEP
DRVOFF
EN/IN1
PH/IN2
OUT1
OUT2
IPROPI
Device State
1
0
1
1
Hi-Z
Hi-Z
No current
STANDBY
(1)
(2)
Current sourcing out of device (VM → OUTx → Load)
If internal ITRIP regulation is enabled and ITRIP level is reached, then OUTx is forced "H" for a fixed time
For the SPI variant, by setting the PWM_EXTEND bit in the CONFIG2 register, there are additional Hi-Z states
that are possible, when a forward ([EN/IN1 PH/IN2] = [1 0]) or reverse ([EN/IN1 PH/IN2] = [0 1]) command is
followed by a Hi-Z command ([EN/IN1 PH/IN2] = [1 1]). In this condition of Hi-Z (coasting), only the half-bridge
involved with the PWM is Hi-Z, while the HS FET on the other half-bridge is kept ON. The determination on
which half-bridge to Hi-Z is made based on the previous cycle. This is summarized in Table 8-6.
Table 8-6. PWM EXTEND table (PWM_EXTEND bit = 1'b1)
PREVIOUS STATE
CURRENT STATE
Device State Transition
OUT1
OUT2
OUT1
OUT2
IPROPI
Hi-Z
Hi-Z
Hi-Z
Hi-Z
No current
Remains in STANDBY, no change
H
H
Hi-Z
Hi-Z
No current
ACTIVE to STANDBY
L
H
Hi-Z
H
ISNS2
ACTIVE to STANDBY
H
L
H
Hi-Z
ISNS1
ACTIVE to STANDBY
8.3.2.3 Independent mode
In this mode, the two half-bridges are configured to be used as two independent half-bridges. The Table 8-7
shows the logic table for bridge control. For load illustration, refer the Load Summary section.
Table 8-7. Control table - Independent mode
nSLEEP
DRVOFF
EN/IN1
PH/IN2
OUT1
OUT2
IPROPI
Device State
0
X
X
X
Hi-Z
Hi-Z
No current
SLEEP
1
1
0
0
Hi-Z
Hi-Z
No current
STANDBY
1
1
1
0
No current
STANDBY
1
1
0
1
No current
STANDBY
1
1
1
1
No current
STANDBY
1
0
0
0
L
L
No current
ACTIVE
1
0
0
1
L
H(2)
ISNS2(1)
ACTIVE
L
ISNS1(1)
ACTIVE
H(2)
ISNS1 + ISNS2(1)
ACTIVE
Refer Off-state diagnostics table
1
0
1
0
H(2)
1
0
1
1
H(2)
For the SPI variant, it is possible to have independent Hi-Z control of both half-bridges through equivalent bits,
S_DRVOFF & S_DRVOFF2 in the SPI_IN register, when the SPI_IN register has been unlocked. Table 8-8
shows the logic table for bridge control using the pin & register combined inputs. Refer to - Register - Pin control
for details on the combined inputs shown in Table 8-8.
Table 8-8. Control table - Independent mode for SPI variant, when SPI_IN is unlocked
nSLEEP
DRVOFF1 DRVOFF2 EN_IN1
PH_IN2
combined combined combined combined
OUT1
OUT2
IPROPI
Device State
0
X
X
X
X
Hi-Z
Hi-Z
No current
SLEEP
1
1
1
0
0
Hi-Z
Hi-Z
No current
STANDBY
1
1
1
1
0
No current
STANDBY
1
1
1
0
1
No current
STANDBY
1
1
1
1
1
No current
STANDBY
1
1
0
X
0
Hi-Z
L
No current
ACTIVE
1
1
0
X
1
Hi-Z
H(2)
ISNS2(1)
ACTIVE
1
0
1
0
X
L
Hi-Z
No current
ACTIVE
Refer Off-state diagnostics table
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Table 8-8. Control table - Independent mode for SPI variant, when SPI_IN is unlocked (continued)
nSLEEP
(1)
(2)
DRVOFF1 DRVOFF2 EN_IN1
PH_IN2
combined combined combined combined
OUT1
OUT2
IPROPI
Device State
1
0
1
1
X
H(2)
Hi-Z
ISNS1(1)
ACTIVE
1
0
0
0
0
L
L
No current
ACTIVE
ISNS2(1)
ACTIVE
1
0
0
0
1
L
H(2)
1
0
0
1
0
H(2)
L
ISNS1(1)
ACTIVE
1
0
0
1
1
H(2)
H(2)
ISNS1 +
ISNS2(1)
ACTIVE
Current sourcing out of device (VM → OUTx → Load)
If internal ITRIP regulation is enabled and ITRIP level is reached, then OUTx is forced "L" for a fixed time
In this mode, the device behavior is as listed below:
• Load current can be sensed only for current from VM → OUTx → Load. So current sense is not possible for
high-side loads
• The current on IPROPI pin is the sum of the high-side sense current from both the half-bridges. This limits the
ITRIP current regulation feature as a combined current regulation, rather than as truly independent.
• Slew rate configurability is limited for low-side recirculation (low-side loads)
• Active state open load diagnostics (OLA) is possible only for high-side loads
• For the HW variant, it is NOT possible to have independent Hi-Z control of each half-bridge. Asserting
DRVOFF pin high will Hi-Z both the half-bridges.
8.3.2.4 Register - Pin Control - SPI Variant Only
The SPI variant allows control of the bridge through the specific register bits, S_DRVOFF, S_DRVOFF2,
S_EN_IN1, S_PH_IN2 in the SPI_IN register, provided the SPI_IN register has been unlocked. The user
can unlock this register by writing the right combination to the SPI_IN_LOCK bits in the COMMAND register.
Additionally, the user can configure between an AND / OR logic combination of each of external input pin with
their equivalent register bit in the SPI_IN register. This logical configuration is done through the equivalent
selects bits in the CONFIG4 register:
• DRVOFF_SEL, EN_IN1_SEL and PH_IN2_SEL
The control of the output is similar to the truth tables described in the section before, but with these logically
combined inputs. These combined inputs are listed as follows:
• Combined input = Pin input OR equivalent SPI_IN register bit, if equivalent CONFIG4 select bit = 1'b0
• Combined input = Pin input AND equivalent SPI_IN register bit, if equivalent CONFIG4 select bit = 1'b1
• In Independent mode:
– DRVOFF2 combined = DRVOFF pin OR S_DRVOFF2 bit, if DRVOFF_SEL bit = 1'b0
– DRVOFF2 combined = DRVOFF pin AND S_DRVOFF2 bit, if DRVOFF_SELbit = 1'b1
Note that external nSLEEP pin is still needed for sleep function.
This logical combination offers more configurability to the user as shown in the table below.
Table 8-9. Register - Pin Control Examples
Example
CONFIG4: xxx_SEL
Bit
PIN status
SPI_IN Bit Status
Comment
DRVOFF as
redundant shutoff
DRVOFF_SEL = 1’b0
DRVOFF active
S_DRVOFF active
Either DRVOFF pin = 1 or S_DRVOFF bit = 1
will shutoff the output
Pin only control
DRVOFF_SEL = 1’b1
DRVOFF active
S_DRVOFF = 1'b1
Only DRVOFF pin function is available
Register only control
PH_IN2_SEL bit =
1’b0
PH/IN2 - short to
GND or float
S_PH_IN2 active
PH (direction) will be controlled by the
register bit alone
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8.3.3 Device Configuration
This section describes the various device configurations to enable the user to configure the device to suit their
use case.
8.3.3.1 Slew Rate (SR)
The SR pin (HW variant) or S_SR bits in the CONFIG3 register (SPI variant) determines the voltage slew
rate of the driver output. This enables the user to optimize the PWM switching losses while meeting the EM
conformance requirements. For the HW variant, SR is a 6-level setting, while the SPI variant has 8 settings. For
an inductive load, the slew rate control of the device depends on whether the recirculation path is through the
high-side path to VM or through the low-side path to GND. Depending on the use-case, refer to the switching
parameters table for either high-side recirculation or low-side recirculation in the Electrical Characteristics
section for the slew rate range and values.
Note
The SPI variant also offers an optional spread spectrum clocking (SSC) feature that spreads the
internal oscillator frequency +/- 12% around its mean with a period triangular function of ~1.3 MHz to
reduce emissions at higher frequencies. There is no spread spectrum clocking (SSC) feature in the
HW variant.
In the HW variant, the SR pin is latched during device initialization following power-up or wake-up from sleep.
Update during operation is blocked.
In the SPI variant, the slew rate setting can be changed at any time when SPI communication is available by
writing to the S_SR bits. This change is immediately reflected.
8.3.3.2 IPROPI
The device integrates a current sensing feature with a proportional analog current output on the IPROPI pin that
can be used for load current regulation. This eliminates the need of an external sense resistor or sense circuitry
reducing system size, cost, and complexity.
The device senses the load current by using a shunt-less high-side current mirror topology. This way the device
can only sense an uni-directional high-side current from VM → OUTx → Load through the high-side FET when
it is fully turned ON (linear mode). The IPROPI pin outputs an analog current proportional to this sensed current
scaled by AIPROPI as follows:
IIPROPI = (IHS1 + IHS2) / AIPROPI
The IPROPI pin must be connected to an external resistor (RIPROPI) to ground in order to generate a proportional
voltage VIPROPI. This allows for the load current to be measured as a voltage-drop across the RIPROPI resistor
with an analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current
in the application so that the full range of the controller ADC is utilized.
The current expressed on IPROPI is the sum of the currents flowing out of the OUTx pins from VM. This implies
that:
• In full-bridge operation using PWM or PH/EN mode, the current expressed on IPROPI pin is always from one
of the half-bridges that is sourcing the current from VM to the load.
• In independent mode, the current expressed on IPROPI pin could be from either half-bridges or both of them.
It is not possible to observe only one half-bridge current independently.
8.3.3.3 ITRIP Regulation
The device offers an optional internal load current regulation feature using fixed TOFF time method. This is done
by comparing the voltage on the IPROPI pin against a reference voltage determined by ITRIP setting. TOFF time
is fixed at 30 µsec for HW variant, while it is configurable between or 20 to 50 µsec for the SPI variant using
TOFF_SEL bits in the CONFIG3 register.
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The ITRIP regulation, when enabled, comes into action only when the HS FET is enabled and current sensing is
possible. In this scenario, when the voltage on the IPROPI pin exceeds the reference voltage set by the ITRIP
setting, the internal current regulation loop forces the following action:
• In PH/EN or PWM mode, OUT1 = H, OUT2 = H (high-side recirculation) for the fixed TOFF time
– Cycle skipping: Due to minimum duty cycle limitations (especially at low slew rate settings and high VM),
load current will contiue to increase even with ITRIP regulation. In order to prevent this current walk away,
a cycle skipping scheme is implemented, where, if IOUT sensed is still greater than ITRIP at the end of
TOFF time, then the recirculation time is extended by an additional TOFF period. This recirculation time
addition will continue till IOUT sensed is less than ITRIP at the end of the TOFF period.
• In Independent mode, If OUTx = H, then toggle OUTx = L for the fixed TOFF time, else no action on OUTx
Note
The user inputs always takes precedence over the internal control. That means that if the inputs
change during the TOFF time, the remainder of the TOFF time is ignored and the outputs will follow
the inputs as commanded.
ISNS
IPROPI
VM
High Side Current
Sense
RIPROPI
V(IPROPI)
Impedance Estimator
(HW variant)
DAC
ITRIP_CMP
ITRIP
V(ITRIP)
OUTx
RITRIP
GND
Digital Core
SPI (SPI variant)
Figure 8-4. ITRIP Implementation
Current limit is set by the following equation:
ITRIP regulation level = (VITRIP / RIPROPI) X AIPROPI
(2)
ITRIP regulaon ac ve
ITRIP
IOUT
VOUT1
VOUT2
EN/IN1
tOFF
tOFF
tOFF
PH/IN2
E.g. PH/EN mode
Figure 8-5. Fixed TOFF ITRIP Current Regulation
In Independent mode, since ITRIP regulation is based on summation of the two half-bridge currents on IPROPI
pin, it is not possible to have completely independent current regulation for the two half-bridges simultaneously.
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The ITRIP comparator output (ITRIP_CMP) is ignored during output slewing to avoid false triggering of the
comparator output due to current spikes from the load capacitance. Additionally, in the event of transition from
low-side recirculation, an additional blanking time tBLANK is needed for the sense loop to stabilize before the
ITRIP comparator output is valid.
ITRIP is a 6-level setting for the HW variant. The SPI variant offers two more settings. This is summarized in the
table below:
Table 8-10. ITRIP Table
ITRIP Pin
S_ITRIP Register Bits
VITRIP [V]
RLVL1OF6
3'b000
Regulation Disabled
RLVL2OF6
3'b001
1.18
Not available
3'b010
1.41
Not available
3'b011
1.65
RLVL3OF6
3'b100
1.98
RLVL4OF6
3'b101
2.31
RLVL5OF6
3'b110
2.64
RLVL6OF6
3'b111
2.97
In the HW variant of the device, the ITRIP pin changes are transparent and changes are reflected immediately.
In the SPI variant of the device, the ITRIP setting can be changed at any time when SPI communication is
available by writing to the S_ITRIP bits. This change is immediately reflected in the device behavior.
SPI variant only - If the ITRIP regulation levels are reached, the ITRIP_CMP bit in the STATUS1 register is set.
There is no nFAULT pin indication. This bit can be cleared with a CLR_FLT command.
Note
If the application requires a linear ITRIP control with multiple steps beyond the choices provided by
the device, an external DAC can be used to force the voltage on the bottom side of the IPROPI
resistor, instead of terminating it to GND. With this modification, the ITRIP current can be controlled by
the external DAC setting as follows:
ITRIP regulation level = [(VITRIP - VDAC) / RIPROPI] X AIPROPI
(3)
8.3.3.4 DIAG
The DIAG is a pin (HW variant) or register (SPI variant) setting that is used in both ACTIVE and STANDBY
operation of the device, as follows:
• STANDBY state
– In PH/EN or PWM modes: Enable or disable Off-state diagnostics (OLP).
– Enable or disable Off-state diagnostics (OLP), as well as select the OLP combinations when enabled.
Refer to the tables in the Off-state diagnostics (OLP) section for details on this.
• ACTIVE state
– Mask ITRIP regulation function if the load type is indicated as high-side load.
– SPI variant only - Mask active open load detection (OLA) if the load type is indicated as low-side. load
– HW variant only - Configure fault reaction between retry and latch settings
8.3.3.4.1 HW variant
For the HW variant, the DIAG pin is a 6-level setting. Depending on the mode, its configurations are
summarized in the table below.
Table 8-11. DIAG table for the HW variant, PH/EN or PWM mode
DIAG pin
RLVL1OF6
STANDBY state
ACTIVE state
Off-state diagnostics
Fault reaction
Disabled
Retry
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Table 8-11. DIAG table for the HW variant, PH/EN or PWM mode (continued)
STANDBY state
ACTIVE state
Off-state diagnostics
Fault reaction
RLVL5OF6
Disabled
Latch
All other levels
Enabled(1)
Latch
DIAG pin
Table 8-12. DIAG table for the HW variant, Independent mode
STANDBY state
DIAG pin
(1)
ACTIVE state
Off-state diagnostics
Load Configuration
Fault reaction
IPROPI / ITRIP
RLVL1OF6
Disabled
Low-side load
Retry
Available
RLVL2OF6
Enabled(1)
Low-side load
Latch
Available
RLVL3OF6
Enabled(1)
High-side load
Latch
Disabled
RLVL4OF6
Enabled(1)
High-side load
Retry
Disabled
RLVL5OF6
Disabled
Low-side load
Latch
Available
RLVL6OF6
Enabled(1)
Low-side load
Retry
Available
Refer to the tables in the Off-state diagnostics (OLP) section for combination details
Note
HW variant only - Option to disable off-state diagnostics for a high-side load use case is not
supported. In this case, setting DRVOFF pin high and IN pin low is only way to disable off-state
diagnostics.
In the HW variant, the DIAG pin is latched during device initialization following power-up or wake-up from sleep.
Update during operation is blocked.
8.3.3.4.2 SPI variant
For the SPI variant, S_DIAG is a 2-bit setting in the CONFIG2 register. Depending on the mode, its
configurations are summarized in the table below.
Table 8-13. DIAG table for the SPI variant, PH/EN or PWM mode
STANDBY state
ACTIVE state
Off-state diagnostics
On-state diagnostics
2'b00
Disabled
Available
2'b01, 2'b10, 2'b11
Enabled(1)
Available
S_DIAG bits
Table 8-14. DIAG table for the SPI variant, Independent mode
S_DIAG bits
(1)
STANDBY state
ACTIVE state
Off-state diagnostics
Load Configuration
On-state diagnostics
IPROPI / ITRIP
2'b00
Disabled
Low-side load
Disabled
Available
2'b01
Enabled(1)
Low-side load
Disabled
Available
2'b10
Disabled
High-side load
Available
Disabled
2'b11
Enabled(1)
High-side load
Available
Disabled
Refer to the tables in the Off-state diagnostics (OLP) section for combination details
In the SPI variant of the device, the settings can be changed anytime when SPI communication is available by
writing to the S_DIAG bits. This change is immediately reflected.
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8.3.4 Protection and Diagnostics
The driver is protected against over-current and over-temperature events to ensure device robustness.
Additionally, the device also offers load monitoring (on-state and off-state), over/ under voltage monitoring on
VM pin to signal any unexpected voltage conditions. Fault signaling is done through a low-side open drain
nFAULT pin which gets pulled to GND by InFAULT_PD current on detection of a fault condition. Transition to SLEEP
state automatically de-asserts nFAULT.
Note
In the SPI variant, nFAULT pin logic level is the inverted copy of the FAULT bit in the FAULT
SUMMARY register. Only exception is when off-state diagnostics are enabled and SPI_IN register
is locked (Refer OLP section) .
For the SPI variant, whenever nFAULT is asserted low, the device logs the fault into the FAULT SUMMARY and
STATUS registers. These registers can be cleared only by
• CLR FLT command or
• SLEEP command through the nSLEEP pin
It is possible to get all the useful diagnostic information for periodic software monitoring in a single 16 bit SPI
frame by:
• Reading the STATUS1 register during ACTIVE state
• Reading the STATUS2 register during STANDBY state
All the diagnosable fault events can be uniquely identified by reading the STATUS registers.
8.3.4.1 Over Current Protection (OCP)
•
•
•
•
•
Device state: ACTIVE
Mechanism & thresholds: An analog current limit circuit on each MOSFET limits the peak current out of the
device even in hard short circuit events. If the output current exceeds the overcurrent threshold, IOCP, for
longer than tOCP, then an over current fault is detected.
Action:
– nFAULT pin is asserted low
– Reaction is based on mode selection:
• PH/EN or PWM mode - Both OUTx is Hi-Z
• Independent mode - The affected half-bridge OUTx is Hi-Z
– For a short to GND fault (over current detected on the high-side FET), the IPROPI pin continues to be
pulled up to VIPROPI_LIM even if the FET has been disabled. For the HW variant, this helps differentiate a
short to GND fault during ACTIVE state from other fault types, as the IPROPI pin is pulled high while the
nFAULT pin is asserted low.
Reaction configurable between latch setting and retry setting based on tRETRY and tCLEAR
User can add a capacitor in the range of 10 nF to 100 nF on the IPROPI pin to ensure OCP detection
in case of a load short condition when internal ITRIP regulation is enabled. This is especially true where
there is enough inductance in the short that causes ITRIP regulation to trigger ahead of the OCP detection,
resulting in the device missing the short detection. To ensure that OCP detection wins this race condition, a
small capacitance added on the IPROPI pin slows down the ITRIP regulation loop enough to allow the OCP
detection circuit to work as intended.
The SPI variant offers configurable IOCP levels and tOCP filter times. Refer CONFIG4 register for these settings.
8.3.4.2 Over Temperature Protection (TSD)
•
•
•
Device state: STANDBY, ACTIVE
Mechanism & thresholds: The device has several temperature sensors spread around the die. If any of the
sensors detect an over temperature event, set by TTSD for a time greater than tTSD, then an over temperature
fault is detected.
Action:
– nFAULT pin is asserted low
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•
– Both OUTx is Hi-Z
– IPROPI pin is Hi-Z
Reaction configurable between latch setting and retry setting based on THYS and tCLEAR_TSD
8.3.4.3 Off-State Diagnostics (OLP)
The user can determine the impedance on the OUTx node using off-state diagnostics in the STANDBY state
when the power FETs are off. With this diagnostics, it is possible to detect the following fault conditions passively
in the STANDBY state:
• Output short to VM or GND < 100 Ω
• Open load > 1K Ω for full-bridge load or low-side load
• Open load > 10K Ω for high-side load, VM = 13.5 V
Note
It is NOT possible to detect a load short with this diagnostic. However, the user can deduce this
logically if an over current fault (OCP) occurs during ACTIVE operation, but OLP diagnostics do not
report any fault in the STANDBY state. Occurrence of both OCP in the ACTIVE state and OLP in the
STANDBY state would imply a terminal short (short on OUT node).
•
•
•
•
•
•
42
The user can configure the following combinations
– Internal pull up resistor (ROLP_PU) on OUTx
– Internal pull down resistor (ROLP_PD) on OUTx
– Comparator reference level
– Comparator input selection (OUT1 or OUT2)
This combination is determined by the controller inputs (pins only for the HW variant) or equivalent bits in the
SPI_IN register for the SPI variant if the SPI_IN register has been unlocked.
HW variant - When off-state diagnostics are enabled, comparator output (OLP_CMP) is available on nFAULT
pin.
SPI variant - The off-state diagnostics comparator output (OLP_CMP) is available on OLP_CMP bit in
STATUS2 register. Additionally, if the SPI_IN register has been locked, this comparator output is also
available on the nFAULT pin when off-state diagnostics are enabled.
The user is expected to toggle through all the combinations and record the comparator output after its output
is settled.
Based on the input combinations and comparator output, the user can determine if there is a fault on the
output.
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Internal
5V
VM
ROLP_PU
ROLP_PU
D1
D1
OUT1
OUT2
Filter
ROLP_PD
RHIZ
Filter
D2
ROLP_PD
RHIZ
D2
GND
Output on nFAULT pin / register
OLP_CMP
VOLP_REFH
REF Voltage proporonal
VOLP_REFL
to Internal 5V
PIN / register control
Figure 8-6. Off-State Diagnostics for full-bridge Load (PH/EN or PWM Mode)
The OLP combinations and truth table for a no fault scenario vs. fault scenario for a full-bridge load in PH/EN or
PWM modes is shown in Table 8-15.
Table 8-15. Off-State Diagnostics Table - PH/EN or PWM Mode (full-bridge)
User Inputs
OLP Set-Up
OLP CMP Output
nSLEEP
DRVOFF
EN/IN1
PH/IN2
OUT1
OUT2
CMP REF
Output
selected
Normal
Open
GND
Short
VM Short
1
1
1
0
ROLP_PU
ROLP_PD
VOLP_REFH
OUT1
L
H
L
H
1
1
0
1
ROLP_PU
ROLP_PD
VOLP_REFL
OUT2
H
L
L
H
1
1
1
1
ROLP_PD
ROLP_PU
VOLP_REFL
OUT2
H
H
L
H
The OLP combinations and truth table for a no fault scenario vs. fault scenario for a low-side load in Independent
mode is shown in Table 8-16.
Table 8-16. Off-State Diagnostics Table for Low-Side Load - Independent Mode
User Inputs
DIAG
pin
S_DIAG
nSLEEP DRVOFF
bits
LVL2,
LVL6
2'b01
LVL3,
LVL4
2'b11
LVL2,
LVL6
2'b01
LVL3,
LVL4
2'b11
1
1
1
1
1
1
1
1
OLP Set-Up
EN/IN1
PH/IN2
OUT1
OUT2
1
don't
care
ROLP_PU
Hi-Z
don't
care
ROLP_PD
Hi-Z
1
Hi-Z
ROLP_PU
1
0
0
1
Hi-Z
CMP
REF
VOLP_REF
OLP_CMP Output
Output
selected
Normal
Open
Short
OUT1
L
H
H
OUT1
L
L
H
OUT2
L
H
H
OUT2
L
L
H
H
VOLP_REF
L
ROLP_PD
VOLP_REF
H
VOLP_REF
L
The OLP combinations and truth table for a no fault scenario vs. fault scenario for a high-side load in
Independent mode is shown in Table 8-17.
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Table 8-17. Off-State Diagnostics Table for High-Side Load - Independent Mode
User Inputs
DIAG
pin
S_DIAG
nSLEEP DRVOFF
bits
LVL2,
LVL6
2'b01
LVL3,
LVL4
2'b11
LVL2,
LVL6
2'b01
LVL3,
LVL4
2'b11
1
1
1
1
1
1
1
1
OLP Set-Up
EN/IN1
PH/IN2
OUT1
OUT2
1
don't
care
ROLP_PU
Hi-Z
don't
care
ROLP_PD
Hi-Z
1
Hi-Z
ROLP_PU
1
0
0
1
Hi-Z
CMP
REF
VOLP_REF
OLP_CMP Output
Output
selected
Normal
Open
Short
OUT1
H
H
L
OUT1
H
L
L
OUT2
H
H
L
OUT2
H
L
L
H
VOLP_REF
L
ROLP_PD
VOLP_REF
H
VOLP_REF
L
8.3.4.4 On-State Diagnostics (OLA) - SPI Variant Only
•
•
•
•
Device state: ACTIVE - high-side recirculation
Mechanism and threshold: On-state diagnostics (OLA) can detect an open load detection in the ACTIVE state
during high-side recirculation. This includes high-side load connected directly to VM or through a high-side
FET on the other half-bridge. During a PWM switching transition, the inductive load current re-circulates into
VM through the HS body diode when the LS FET is turned OFF. The device looks for a voltage spike on
OUTx above VM during the brief dead time, before the HS FET is turned ON. To observe the voltage spike,
this load current needs to be higher than the pull down current (IPD_OLA) on the output asserted by the FET
driver. Absence of this voltage spike for "3" consecutive re-circulation switching cycles indicates a loss of load
inductance or increase in load resistance and is detected as an OLA fault.
Action:
– nFAULT pin is asserted low
– Output - normal function maintained
– IPROPI pin - normal function maintained
Reaction configurable between latch setting and retry setting. In retry setting, OLA fault is automatically
cleared with the detection of "3" consecutive voltage spikes during re-circulation switching cycles.
This monitoring is optional and can be disabled.
Note
1. OLA is not supported for low-side loads (low-side recirculation).
2. CLR_FAULT command can clear this fault (recorded in the STATUS1 register) only if the direction
commanded is aligned with direction during which the fault was detected.
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VM
OLA_VREF
OUTx_OLA_CMP
D1
OUTx
IPD_OLA
D2
GND
Figure 8-7. On-State Diagnostics
8.3.4.5 VM Over Voltage Monitor
•
•
•
•
Device state: STANDBY, ACTIVE
Mechanism & thresholds: If the supply voltage on the VM pin exceeds the threshold, set by VVMOV for a time
greater than tVMOV, then an VM over voltage fault is detected.
Action:
– nFAULT pin is asserted low
– Output - normal function maintained
– IPROPI pin - normal function maintained
Reaction configurable between retry and latch setting
In the SPI variant, this monitoring is optional and can be disabled. Also the thresholds are configurable. Refer
CONFIG1 register.
8.3.4.6 VM Under Voltage Monitor
•
•
•
•
•
•
Device state: STANDBY, ACTIVE
Mechanism & thresholds: If the supply voltage on the VM pin drops below the threshold, set by VVMUV for a
time greater than tVMUV, then an VM under voltage fault is detected.
Action:
– nFAULT pin is asserted low
– Both OUTx is Hi-Z
– IPROPI pin is Hi-Z
HW and SPI (S) variant: Reaction fixed to retry setting
Only for SPI (P) variant: Reaction configurable between retry and latch setting
Note that retry time is only dependent on recovery of VM under voltage condition and is independent of
tRETRY / tCLEAR times
8.3.4.7 Power On Reset (POR)
•
•
•
Device state: ALL
Mechanism & thresholds: If logic supply drops below VDDPOR_FALL for a time greater than tPOR, then a power
on reset will occur that will hard reset the device.
Action:
– nFAULT pin is de-asserted
– Both OUTx is Hi-Z
– IPROPI pin is Hi-Z.
– When this supply recovers above the VDDPOR_RISE level, the device will go through a wake-up
initialization and nFAULT pin will be asserted low to notify the user on this reset (Refer Wake-up
transients).
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•
•
•
HW and SPI (S) variant: These thresholds translate to VMPOR_FALL and VMPOR_RISE as the logic supply is
internally derived from the VM supply
Only for SPI (P) variant: These thresholds directly map to the VDD pin voltage (VDDPOR_FALL and
VDDPOR_RISE)
Fault reaction: Always retry, retry time depends on the external supply condition to initiate a device wake-up
8.3.4.8 Event Priority
In the ACTIVE state, in a scenario where two or more events occur simultaneously, the device assigns control of
the driver based on the following priority table.
Table 8-18. Event Priority Table
Event
Priority
User SLEEP command
1
User input: DRVOFF
2
Over temperature detection (TSD)
3
Over current detection (OCP)(1)
4
VM under voltage detection (VMUV)
5
User input: EN/IN1 and/or PH/IN2
6
Internal PWM control from ITRIP regulation
7
VM over voltage detection (VMOV)(2)
8
On-state fault detection (OLA - SPI variant
(1)
(2)
only)(2)
9
If the device is waiting for an OCP event to be confirmed (waiting for tOCP) when any of events with lower priority than OCP occur, then
the device may delay servicing the other events up to a maximum time of tOCP to enable detection of the OCP event.
Priority is "don't care" in this case as this fault event does not cause a change in OUTx
8.4 Device Functional States
The device has three functional states:
• SLEEP
• STANDBY
• ACTIVE
SLEEP
nFAULT = H, No communicaon
1
2
2
INIT2
STANDBY
2
ACTIVE
3
INIT1
nFAULT = H
4
nFAULT = L
Communicaon
enabled
5
nFAULT = H
Communicaon
available
6
7
Protec on Enabled
nFAULT = fault
signaling
Communicaon
available
1. nSLEEP = 1 for t > tWAKE
2. nSLEEP = 0 for t > tSLEEP
3. Power on reset
4. End of tCOM
5. CLR_FLT or HW RESET pulse from from controller & End of tREADY
6. DRVOFF = 0 & [IN1/EN IN2/PH] != [1 1], if PWM mode
7. DRVOFF = 1 or [IN1/EN IN2/PH] = [1 1], if PWM mode
Figure 8-8. Illustrative State Diagram
These states are described in the following section.
46
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8.4.1 SLEEP State
This state occurs when nSLEEP pin is asserted low for a time > tSLEEP or voltage on the VDD pin is <
VDDPOR_FALL.
This is the deep sleep low power (ISLEEP) state of the device where all functions except a wake-up command are
not serviced. The drivers are in Hi-Z. The internal power supply rails (5 V and others) are powered off. nFAULT
pin is de-asserted in this state. The device can enter this state from either the STANDBY or the ACTIVE state,
when the nSLEEP pin is asserted low for time longer than tSLEEP (HW variant) or for tSLEEP_SPI (SPI (S) variant).
8.4.2 STANDBY State
The device is in this state when nSLEEP pin is asserted high or the voltage on the VDD pin is > VDDPOR_RISE
with DRVOFF = 1'b0 for all modes and additionally, in PWM mode when both IN1/EN & IN2/PH are 1'b1. In this
state, the device is powered up (ISTANDBY), with the driver Hi-Z and nFAULT de-asserted. The device is ready
to transition to ACTIVE state or SLEEP state when commanded so. Off-state diagnostics (OLP), if enabled, are
done in this state.
8.4.3 Wake-up to STANDBY State
The device starts transition from SLEEP state to STANDBY state
• if the nSLEEP pin goes high for a duration longer than tWAKE, or
• if VM supply > VMPOR_RISE or VDD supply > VDDPOR_RISE such that internal POR is released to indicate a
power-up.
The device goes through an initialization sequence to load its internal registers and wake-up all the blocks in the
following sequence:
• At a certain time, tCOM from wake-up, the device is capable of communication. This is indicated by asserting
the nFAULT pin low.
• This is followed by the time tREADY, when the device wake-up is complete.
• At this point, once the device receives a nSLEEP reset pulse (HW variant) or a CLR FAULT command
through SPI (SPI variant) as an acknowledgment of the wake-up from the controller, the device enters the
STANDBY state. This is indicated by the de-assertion of the nFAULT pin. The driver is held in Hi-Z till this
point.
• From here on, the device is ready to drive the bridge based on the truth tables for the specific mode
configured.
Refer to the wake-up transients waveforms for the illustration.
8.4.4 ACTIVE State
The device is fully functional in this state with the drivers controlled by other inputs as described in prior sections.
All protection features are fully functional with fault signaling on nFAULT pin. SPI communication is available.The
device can transition into this state only from the STANDBY state.
8.4.5 nSLEEP Reset Pulse (HW Variant Only)
This is a special communication signal from the controller to the device through the nSLEEP pin available only
for the HW variant. This is used to:
• Acknowledge the nFAULT asserted during the SLEEP/ Power up transition to STANDBY state
• Clear a latched fault when the fault reaction is configured to the LATCHED setting, without forcing the device
into SLEEP or affecting any of the other functions (Equivalent to the CLR_FAULT command in the SPI
variant)
This pulse on nSLEEP must be greater than the nSLEEP deglitch time of tRESET time, but shorter than tSLEEP
time, as shown in case # 3, in Table 8-19 below.
Table 8-19. nSLEEP Timing (HW Variant Only)
Case #
Window Start Time
Window End Time
1
0
tRESET min
Command Interpretation
Clear Fault
Sleep
No
No
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Table 8-19. nSLEEP Timing (HW Variant Only) (continued)
Case #
Window Start Time
Window End Time
2
tRESET min
3
Command Interpretation
Clear Fault
Sleep
tRESET max
Indeterminate
No
tRESET max
tSLEEP min
Yes
No
4
tSLEEP min
tSLEEP max
Yes
Indeterminate
5
tSLEEP max
No limit
Yes
Yes
tSLEEP max
tSLEEP min
tRESET max
tRESET min
nSLEEP pulses
Case 1
Case 2
Case 3
Case 4
Case 5
Window 1
Window 2
Window 3
Window 4
Window 5
me
Figure 8-9. nSLEEP Pulse Scenarios
8.5 Programming - SPI Variant Only
8.5.1 SPI Interface
The SPI variant has full-duplex, 4-wire synchronous communication that is used to set device configurations,
operating parameters, and read out diagnostic information from the device. The SPI operates in peripheral mode
and connects to a controller. The serial data input (SDI) word consists of a 16-bit word, with an 8-bit command
(A1), followed by 8-bit data (D1). The serial data output (SDO) word consists of the FAULT_SUMMARY byte
(S1), followed by a report byte (R1). The report byte is either the register data being accessed by read command
or null for a write command. The data sequence between the MCU and the SPI peripheral driver is shown in
Figure 8-10.
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nSCS
A1
D1
S1
R1
SDI
SDO
Figure 8-10. SPI Data - Standard "16-bit" Frame
A valid frame must meet the following conditions:
• SCLK pin should be low when the nSCS pin transitions from high to low and from low to high.
• nSCS pin should be pulled high between words.
• When nSCS pin is pulled high, any signals at the SCLK and SDI pins are ignored and the SDO pin is placed
in the Hi-Z state.
• Data on SDO from the device is propagated on the rising edge of SCLK, while data on SDI is captured by the
device on the subsequent falling edge of SCLK.
• The most significant bit (MSB) is shifted in and out first.
• A full 16 SCLK cycles must occur for a valid transaction for a standard frame, or alternately, for a daisy chain
frame with "n" number of peripheral devices, 16 + (n x 16) SCLK cycles must occur for a valid transaction.
Else, a frame error (SPI_ERR) is reported and the data is ignored if it is a WRITE operation.
8.5.2 Standard Frame
The SDI input data word is 2 bytes long and consists of the following format:
• Command byte (first byte)
– MSB bit indicates frame type (bit B15 = 0 for standard frame).
– Next to MSB bit, W0, indicates read or write operation (bit B14, write = 0, read = 1)
– Followed by 6 address bits, A[5:0] (bits B13 through B8)
• Data byte (second byte)
– Second byte indicates data, D[7:0] (bits B7 through B0). For a read operation, these bits are typically set
to null values, while for a write operation, these bits have the data value for the addressed register.
Table 8-20. SDI - Standard Frame Format
Command Byte
Data Byte
Bit
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Data
0
W0
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
The SDO output data word is 2 bytes long and consists of the following format:
• Status byte (first byte)
– 2 MSB bits are forced high (B15, B14 = 1)
– Following 6 bits are from the FAULT SUMMARY register (B13:B8)
• Report byte (second byte)
– The second byte (B7:B0) is either the data currently in the register being read for a read operation (W0 =
1), or, existing data in the register being written to for a write command (W0 = 0)
Table 8-21. SDO - Standard Frame Format
Status Byte
Bit
B15
B14
B13
B12
B11
Report Byte
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
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Table 8-21. SDO - Standard Frame Format (continued)
Status Byte
Data
1
1
FAULT VMOV VMUV
Report Byte
OCP
TSD
SPI_E
RR
D7
D6
D5
D4
D3
D2
D1
D0
8.5.3 SPI Interface for Multiple Peripherals
Multiple devices can be connected to the controller with and without the daisy chain. For connecting a 'n' number
of devices to a controller without using a daisy chain, 'n' number of I/O resources from controller has to utilized
for nSCS pins as shown in Figure 8-11. Whereas, if the daisy chain configuration is used, then a single nSCS
line can be used for connecting multiple devices. Figure 8-12
DRV8x
DRV8x
SCLK
Master Controller
SCLK
Master Controller
SDI
SDO
CS1
SDO
CS
nSCS
MCLK
SPI
Communication
DRV8x
MI
SPI
Communication
nSCS
MO
DRV8x
MI
SCLK
SCLK
SDI
SDO
SDI
SPI
Communication
SDO
nSCS
SPI
Communication
nSCS
Figure 8-11. SPI Operation Without Daisy Chain
50
SPI
Communication
MCLK
MO
CS2
SDI
SPI
Communication
Figure 8-12. SPI Operation With Daisy Chain
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8.5.3.1 Daisy Chain Frame for Multiple Peripherals
The device can be connected in a daisy chain configuration to save GPIO ports when multiple devices
are communicating to the same MCU. Figure 8-13 shows the topology with waveforms, where, number of
peripherals connected in a daisy chain "n" is set to 3. A maximum of up to 63 devices can be connected in this
manner.
SDI1
SDO1
SDI1
SDI2
SDO3
SDO2
SDO1
M-SDO
M-SDO
SDI2
SDO2
SDI2
SDI3
SDO3
M-SDI
M-nSCS
M-SCLK
M-SDI
nSCS
HDR1
HDR2
A3
A2
A1
D3
D2
D1
S1
HDR1
HDR2
A3
A2
R1
D3
D2
S2
S1
HDR1
HDR2
A3
R2
R1
D3
S3
S2
S1
HDR1
HDR2
R3
R2
R1
SDI1
SDO1
SDI2
SDO2
SDI3
SDO3
All Address
Bytes Reach
Destination
Status
Response Here
All Address
Bytes Reach
Destination
Reads
Execute Here
Writes
Execute Here
Figure 8-13. Daisy Chain SPI Operation
The SDI sent by the controller in this case would be in the following format (see SDI1 in Figure 8-13 ):
• 2 bytes of header (HDR1, HDR2)
• "n" bytes of command byte starting with furthest peripheral in the chain (for this example, this is A3, A2, A1)
• "n" bytes of data byte starting with furthest peripheral in the chain (for this example, this is D3, D2, D1)
• Total of 2 x "n" + 2 bytes
While the data is being transmitted through the chain, the controller receives it in the following format (see SDO3
in Figure 8-13):
• 3 bytes of status byte starting with furthest peripheral in the chain (for this example, this is S3, S2, S1)
• 2 bytes of header that were transmitted before (HDR1, HDR2)
• 3 bytes of report byte starting with furthest peripheral in the chain (for this example, this is R3, R2, R1)
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The Header bytes are special bytes asserted at the beginning of a daisy chain SPI communication. Header
bytes must start with 1 and 0 for the two leading bits.
The first header byte (HDR1) contains information of the total number of peripheral devices in the daisy chain.
N5 through N0 are 6 bits dedicated to show the number of device in the chain as shown in Figure 8-14. Up to
63 devices can be connected in series per daisy chain connection. Number of peripheral = 0 is not permitted and
will result in a SPI_ERR flag.
The second header byte (HDR2) contains a global CLR FAULT command that will clear the fault registers of
all the devices on the rising edge of the chip select (nSCS) signal. The 5 trailing bits of the HDR2 register are
marked as SPARE (don’t care bits). These can be used by the MCU to determine integrity of the daisy chain
connection.
HDR1
1
0
N5
N4
N3
N2
N1
N0
Number of Devices in the Chain (Up to 63 max)
HDR2
1
0
CLR_FLT SPARE
SPARE
SPARE
SPARE
SPARE
Don’t Care
1 = Global CLR_FAULT
0 = Don’t Care
Figure 8-14. Header bytes
In addition, the device recognizes bytes that start with 1 and 1 for the two leading bits as a "pass" byte. These
"pass" bytes are NOT processed by the device, but they are simply transmitted out on SDO in the following byte.
When data passes through a device, it determines the position of itself in the chain by counting the number of
Status bytes it receives following by the first Header byte. For example, in this 3 device configuration, device 2 in
the chain will receive two status bytes before receiving the two header bytes.
From the two status bytes it knows that its position is second in the chain, and from HDR2 byte it knows how
many devices are connected in the chain. That way it only loads the relevant address and data byte in its buffer
and bypasses the other bits. This protocol allows for faster communication without adding latency to the system
for up to 63 devices in the chain.
The command, data, status and report bytes remain the same as described in the standard frame format.
52
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8.6 Register Map - SPI Variant Only
This section describes the user configurable registers in the device.
Note
While the device allows register writes at any time SPI communication is available, it is recommended
to exercise caution while updating registers in the ACTIVE state while the load is being driven. This
is especially important for settings such as S_MODE and S_DIAG which control the critical device
configuration. In order to prevent accidental register writes, the device offers a locking mechanism
through the REG_LOCK bits in the COMMAND register to lock the contents of all configurable
registers. Best practice would be to write all the configurable registers during initialization and then
lock these settings. Run-time register writes for output control are handled by the SPI_IN register,
which offers its own separate locking mechanism through the SPI_IN_LOCK bits.
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8.6.1 User Registers
The following table lists all the registers that can be accessed by the user. All register addresses NOT listed in this table should be considered as
"reserved" locations and access is blocked to this space. Accessing them will cause a SPI_ERR.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type (2)
Addr
Table 8-22. User Registers
DEVICE_ID
DEV_ID[5]
DEV_ID[4]
DEV_ID[3]
DEV_ID[2]
DEV_ID[1]
DEV_ID[0]
REV_ID[1]
REV_ID[0]
R
00h
FAULT_SUMMARY
SPI_ERR(3)
POR
FAULT
VMOV
VMUV
OCP
TSD
OLA (3)
R
01h
Name
(1)
(2)
(3)
(4)
54
STATUS1
OLA1
OLA2
ITRIP_CMP
ACTIVE
OCP_H1
OCP_L1
OCP_H2
OCP_L2
R
02h
STATUS2
DRVOFF_STAT
N/A(4)
N/A(4)
ACTIVE
N/A(4)
N/A(4)
N/A(4)
OLP_CMP
R
03h
COMMAND
CLR_FLT
N/A(4)
N/A(4)
SPI_IN_LOCK[1]
SPI_IN_LOCK[0]
(1)
N/A(4)
REG_LOCK[1]
SPI_IN
N/A(4)
N/A(4)
N/A(4)
N/A(4)
S_DRVOFF (1)
S_DRVOFF2 (1)
S_EN_IN1
S_PH_IN2
R/W 09h
OCP_RETRY
TSD_RETRY
VMOV_RETRY
OLA_RETRY
R/W 0Ah
N/A(4)
S_ITRIP[2]
S_ITRIP[1]
S_ITRIP[0]
R/W 0Bh
CONFIG1
EN_OLA
VMOV_SEL[1]
VMOV_SEL[0]
SSC_DIS(1)
CONFIG2
PWM_EXTEND
S_DIAG[1]
S_DIAG[0]
N/A(4)
CONFIG3
TOFF[1]
CONFIG4
TOCP_SEL[1]
TOFF[0]
(1)
TOCP_SEL[0]
REG_LOCK[0] (1) R/W 08h
N/A(4)
S_SR[2]
S_SR[1]
S_SR[0]
S_MODE[1]
S_MODE[0]
R/W 0Ch
N/A(4)
OCP_SEL[1]
OCP_SEL[0]
DRVOFF_SEL(1)
EN_IN1_SEL
PH_IN2_SEL
R/W 0Dh
Defaulted to 1b on reset, others are defaulted to 0b on reset
R = Read Only, R/W = Read/Write
OLA replaced by SPI_ERR in the first SDO byte response, common to all SPI frames. Refer SDO - Standard frame format.
N/A = Not available (read back of this bit will be 0b)
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8.6.1.1 DEVICE_ID register (Address = 00h)
Return to the User Register table.
Device
DEVICE_ID value
DRV8243S-Q1
32h
DRV8244S-Q1
42h
DRV8245S-Q1
52h
DRV8243P-Q1
36h
DRV8244P-Q1
46h
DRV8245P-Q1
56h
8.6.1.2 FAULT_SUMMARY Register (Address = 01h) [reset = 40h]
Return to the User Register table.
Bit
Field
Type
Reset
Description
7
SPI_ERR
R
0b
6
POR
R
1b
5
FAULT
R
0b
Logic OR of SPI_ERR, POR, VMOV, VMUV, OCP, TSD & OLA
4
VMOV
R
0b
1b indicates that a VM over voltage has been detected. Refer VMOV_SEL to change
thresholds or disable diagnostic, VMOV_RETRY to configure fault reaction.
3
VMUV
R
0b
1b indicates that a VM under voltage has been detected.
2
OCP
R
0b
1b indicates that an over current has been detected in either one or more power FETs. Refer
OCP_SEL, TOCP_SEL to change thresholds & filter times. Refer OCP_RETRY to configure
fault reaction.
1
TSD
R
0b
1b indicates that an over temperature has been detected. Refer TSD_RETRY to configure
fault reaction.
0
OLA
R
0b
1b indicates that an open load condition has been detected in the ACTIVE state. Refer to
EN_OLA to disable diagnostic, OLA_RETRY to configure fault reaction.
1b indicates that a SPI communication fault has occurred in the previous SPI frame.
1b indicates that a power-on-reset has been detected.
8.6.1.3 STATUS1 Register (Address = 02h) [reset = 00h]
Return to the User Register table.
Bit
Field
Type
Reset
7
OLA1
R
0b
1b indicates that an open load condition has been detected in the ACTIVE state on OUT1
Description
6
OLA2
R
0b
1b indicates that an open load condition has been detected in the ACTIVE state on OUT2
5
ITRIP_CMP
R
0b
1b indicates that load current has reached the ITRIP regulation level.
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Bit
Field
Type
Reset
4
ACTIVE
R
0b
1b indicates that the device is in the ACTIVE state
Description
3
OCP_H1
R
0b
1b indicates that an over current has been detected on the high-side FET (short to GND) on
OUT1
2
OCP_L1
R
0b
1b indicates that an over current has been detected on the low-side FET (short to VM) on
OUT1
1
OCP_H2
R
0b
1b indicates that an over current has been detected on the high-side FET (short to GND) on
OUT2
0
OCP_L2
R
0b
1b indicates that an over current has been detected on the low-side FET (short to VM) on
OUT2
8.6.1.4 STATUS2 Register (Address = 03h) [reset = 80h]
Return to the User Register table.
Bit
Field
Type
Reset
Description
7
DRVOFF_STAT
R
1b
This bit shows the status of the DRVOFF pin. 1b implies the pin status is high.
6, 5
N/A
R
0b
Not available
4
ACTIVE
R
0b
1b indicates that the device is in the ACTIVE state (Copy of bit4 in STATUS1)
3, 2, 1
N/A
R
0b
Not available
0
OLP_CMP
R
0b
This bit is the output of the off-state diagnostics (OLP) comparator.
8.6.1.5 COMMAND Register (Address = 08h) [reset = 09h]
Return to the User Register table.
Bit
56
Field
Type
Reset
Description
7
CLR_FLT
R/W
0b
Clear Fault command - Write 1b to clear all faults reported in the fault registers and de-assert
the nFAULT pin
6-5
N/A
R
0b
Not available
4-3
SPI_IN_LOCK
R/W
01b
Write 10b to unlock the SPI_IN register
Write 01b or 00b or 11b to lock the SPI_IN register
SPI_IN register is locked by default.
2
N/A
R
0b
Not available
1-0
REG_LOCK
R/W
01b
Write 10b to lock the CONFIG registers
Write 01b or 00b or 11b to unlock the CONFIG registers
CONFIG registers are unlocked by default.
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8.6.1.6 SPI_IN Register (Address = 09h) [reset = 0Ch]
Return to the User Register table.
Bit
Field
Type
Reset
7-4
N/A
R
0b
Not available
Description
3
S_DRVOFF
R/W
1b
Register bit equivalent of DRVOFF pin when SPI_IN is unlocked. Refer Register Pin control
section. In Independent mode, this bit shuts off half-bridge 1.
2
S_DRVOFF2
R/W
1b
Register bit to shut off half-bridge 2 in Independent mode when SPI_IN is unlocked. Refer
Register Pin control section
1
S_EN_IN1
R/W
0b
Register bit equivalent of EN/IN1 pin when SPI_IN is unlocked. Refer Register Pin control
section
0
S_PH_IN2
R/W
0b
Register bit equivalent of PH/IN2 pin when SPI_IN is unlocked. Refer Register Pin control
section
8.6.1.7 CONFIG1 Register (Address = 0Ah) [reset = 10h]
Return to the User Register table.
Bit
Field
Type
Reset
7
EN_OLA
R/W
0b
Description
Write 1b to enable open load detection in the active state. In Independent mode, OLA is
always disabled for low-side load. Refer DIAG section.
Determines the thresholds for the VM over voltage diagnostics
00b = VM > 35 V
6-5
VMOV_SEL
R/W
0b
01b = VM > 28 V
10b = VM > 18 V
11b = VMOV disabled
4
SSC_DIS
R/W
1b
0b: Enables the spread spectrum clocking feature
3
OCP_RETRY
R/W
0b
Write 1b to configure fault reaction to retry setting on the detection of over current, else the
fault reaction is latched
2
TSD_RETRY
R/W
0b
Write 1b to configure fault reaction to retry setting on the detection of over temperature, else
the fault reaction is latched
Write 1b to configure fault reaction to retry setting on the detection of VMOV, else the fault
reaction is latched.
1
VMOV_RETRY
R/W
0b
Note
For the SPI (P) variant, this bit also controls the fault reaction for a VM under
voltage detection.
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Bit
0
Field
OLA_RETRY
Type
R/W
Reset
0b
Description
Write 1b to configure fault reaction to retry setting on the detection of open load during active,
else the fault reaction is latched.
8.6.1.8 CONFIG2 Register (Address = 0Bh) [reset = 00h]
Return to the User Register table.
Bit
Field
Type
Reset
Description
7
PWM_EXTEND
R/W
0b
Write 1b to access additional Hi-Z (coast) states in the PWM mode - refer PWM EXTEND
table
6-5
S_DIAG
R/W
0b
Load type indication - refer to DIAG table
4-3
N/A
R
0b
Not available
2-0
S_ITRIP
R/W
0b
ITRIP level configuration - refer ITRIP table
8.6.1.9 CONFIG3 Register (Address = 0Ch) [reset = 40h]
Return to the User Register table.
Bit
Field
Type
Reset
Description
TOFF time used for ITRIP current regulation
00b = 20 µsec
7-6
TOFF
R/W
1b
01b = 30 µsec
10b = 40 µsec
11b = 50 µsec
5
N/A
R
0b
Not available
4-2
S_SR
R/W
0b
Slew Rate configuration - refer to Section 8.3.3.1
1-0
S_MODE
R/W
0b
Device mode configuration - refer MODE table
8.6.1.10 CONFIG4 Register (Address = 0Dh) [reset = 04h]
Return to the User Register table.
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Field
Type
Reset
Description
Filter time for over current detection configuration
00b = 6 µsec
7-6
TOCP_SEL
R/W
0b
01b = 3 µsec
10b = 1.5 µsec
11b = Minimum (~0.2 µsec)
5
N/A
R
0b
Not available
Threshold for over current detection configuration
00b = 100% setting
4-3
OCP_SEL
R/W
0b
01b, 11b = 50% setting
10b = 75% setting
DRVOFF pin - register logic combination, when SPI_IN is unlocked
2
DRVOFF_SEL
R/W
1b
0b = OR
1b = AND
EN/IN1 pin - register logic combination, when SPI_IN is unlocked
1
EN_IN1_SEL
R/W
0b
0b = OR
1b = AND
PH/IN2 pin - register logic combination, when SPI_IN is unlocked
0
PH_IN2_SEL
R/W
0b
0b = OR
1b = AND
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The DRV824x-Q1 family of devices can be used in a variety of applications that require either a half-bridge
or H-bridge power stage configuration. Common application examples include brushed DC motors, solenoids,
and actuators. The device can also be utilized to drive many common passive loads such as LEDs, resistive
elements, relays, etc. The application examples below will highlight how to use the device in bidirectional current
control applications requiring an H-bridge driver and dual unidirectional current control applications requiring two
half-bridge drivers.
9.1.1 Load Summary
Table 9-1 summarizes the utility of the device features for different type of inductive loads.
Table 9-1. Load Summary Table
Configuration
LOAD TYPE
Device Feature
Device
Recirculation
Path
Slew Rate
Current sense
ITRIP regulation
Bi-directional motor or
solenoid(1)
DRV824x in PH/EN or PWM
mode
High-side
Full range
Continuous
Useful
2 Uni-directional motors or
low-side solenoids (one side
connected to GND)
DRV824x in Independent
mode (2)
Low-side
Limited(4)
Discontinuous(3),
Individual load
regulation not
possible
2 High-side solenoids (one
side connected to VM)
DRV824x in Independent
mode (2)
High-side
Full range
Not available, need external solution
(1)
(2)
(3)
(4)
Solenoid - clamping or quick demagnetization possible, but clamping level will be VM dependent
Independent Hi-Z only supported in the SPI variant
Not sensed during recirculation and during OUTx voltage slew times including tblank
Rising edge slew rate capped at 8 V/µsec for higher settings
VM
nFAULT
DRVOFF
nSLEEP
IPROPI
DRV824X
PWM or
PH/EN
mode
to Controller ADC
BDC
OUT1
EN/IN1
to Controller I/O
Applicable for
BD
C
Controller I/Os SPI (Opt)
(can be shared)
solenoid
LOAD
OUT2
PH/IN2
GND
Figure 9-1. Illustration Showing a Full-Bridge Topology With DRV824X-Q1 in PWM or PH/EN Mode
60
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VM
nFAULT
Summing current
DRVOFF
DRV824X
nSLEEP
Independent
mode
Applicable for
BD
C
Controller I/Os SPI (Opt)
(can be shared)
to Controller ADC
IPROPI
BDC
OUT1
solenoid
LOAD
EN/IN1
to Controller I/O
OUT2
PH/IN2
LOAD
GND
Figure 9-2. Illustration Showing Half-Bridge Topology to Drive Two Low-side Loads Independently With
DRV824X-Q1 Device in INDEPENDENT Mode
VM
VM
nFAULT
(can be shared)
DRVOFF
nSLEEP
Not useful
DRV824X
Independent
mode
to Controller I/O
OUT1
solenoid
EN/IN1
to Controller I/O
HS Switch for
clamping
(OPT)
IPROPI
Controller I/Os SPI (Opt)
OUT2
PH/IN2
solenoid
GND
Figure 9-3. Illustration Showing a Half-Bridge Topology to Drive Two High-side Loads Independently With
DRV824X-Q1 Device in INDEPENDENT Mode
9.2 Typical Application
The figures below show the typical application schematic for driving a brushed DC motor or any inductive load in
various modes. There are several optional connections shown in these schematics, which are listed as follows:
• nSLEEP pin
– SPI (S) variant - This pin can be tied off high in the application if SLEEP function is not needed.
– SPI (P) variant - N/A
– HW (H) variant - Pin control is mandatory even if SLEEP function is not needed. The controller needs
to issue a reset pulse (typical: 30 μsec bounded between treset max and tsleep min) during wake-up to
acknowledge wake-up or power-up.
• DRVOFF pin
– Both SPI (P) and SPI (S) variants - This pin can be tied off low in the application if shutoff through pin
function is not needed. The equivalent register bit can be used.
• EN/IN1 pin
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•
•
•
•
•
•
•
– Both SPI (P) and SPI (S) variants - This pin can be tied off low or left floating if register only control is
needed.
PH/IN2 pin
– Both SPI (P) and SPI (S) variants - This pin can be tied off low or left floating if register only control is
needed.
OUT1 & OUT2 pins
– Recommend to add PCB footprints for capacitors from OUTx to GND as well as between OUTx close to
the load for EMC purposes.
IPROPI pin
– All variants - Monitoring of this output is optional. Also IPROPI pin can be tied low if ITRIP feature &
IPROPI function is not needed. Recommend to add a PCB footprint for a small capacitor (10 nF to 100 nF)
if needed.
nFAULT pin
– Both SPI (P) and SPI (S) variants - Monitoring of this output is optional. All diagnostic information can be
read from the STATUS registers.
SPI input pins
– Both SPI (S) and SPI (P) variants - Inputs (SDI, nSCS, SCLK) are compatible with 3.3 V / 5 V levels.
SPI SDO pin
– SPI (S) variant - SDO tracks the nSLEEP pin voltage.
– SPI (P) variant - SDO tracks the VDD pin voltage. To interface with a 3.3 V level controller input, a level
shifter or a current limiting series resistor is recommended.
CONFIG pins
– HW (H) variant - Resistor is not needed for short to GND and Hi-Z level selections
• LVL1 and LVL3 for MODE pin
• LVL1 and LVL6 for SR, ITRIP, DIAG pins
9.2.1 HW Variant
VCC
VCC
SSOP HW
24
I/O
nSLEEP
Reverse Supply
Protected Input
24
6,7,8,21,22,23
I/O
CVM2
I/O
VM
5
I/O
SSOP HW
DRVOFF
CVM1
25
IPROPI
26
nFAULT
27
MODE
RMODE
EN/IN1
OUT1
9,10,11
3
PH/IN2
I/O
Oponal (5)
ADC
RIPROPI
I/O
ITRIP
RITRIP
GND
12,13,14,
15,16,17
1
18,19,20
LOAD
IPROPI
VM / GND
26
nFAULT
MODE
2
28
OUT2
25
27
DIAG
RDIAG
VCC
RnFAULT
RMODE
Op onal (7)
I/O
VCC
RnFAULT
18,19,20
LOAD
RIPROPI
OUT2
CONTROLLER
PH/IN2
Op onal (7)
CONTROLLER
ADC
CVM1
4
3
Oponal (5)
6,7,8,21,22,23
CVM2
DRVOFF
I/O
EN/IN1
I/O
VM
5
4
I/O
nSLEEP
Reverse Supply
Protected Input
OUT1
9,10,11
LOAD
2
DIAG
RDIAG
28
ITRIP
RITRIP
GND
12,13,14,
15,16,17
1
SR
SR
RSR
RSR
FB with PH/EN or PWM mode
HS/ LS load in Independent mode
Figure 9-4. Typical Application Schematic - HW Variant in HVSSOP Package
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VCC
VCC
VQFN-HR HW
3
I/O
nSLEEP
VM
8
I/O
DRVOFF
VQFN-HR HW
Reverse Supply
Protected Input
4
CVM1
3
VCC
RnFAULT
OUT2
2
IPROPI
1
)
nFAULT
14
7
MODE
RMODE
OUT1
CONTROLLER
5
LOAD
I/O
EN/IN1
PH/IN2
I/O
Oponal (5)
ADC
RIPROPI
13
OUT2
LOAD
2
IPROPI
VM / GND
1
nFAULT
14
7
MODE
RMODE
11
6
ITRIP
RITRIP
VCC
RnFAULT
I/O
Op onal (7)
RDIAG
5
10
DIAG
Op onal (7)
CONTROLLER
RIPROPI
CVM1
9
PH/IN2
ADC
DRVOFF
I/O
10
Oponal (5)
VM
CVM2
I/O
EN/IN1
I/O
nSLEEP
8
CVM2
9
I/O
Reverse Supply
Protected Input
4
I/O
GND
12
OUT1
LOAD
11
DIAG
RDIAG
13
6
ITRIP
RITRIP
GND
12
SR
SR
RSR
RSR
HS/ LS load in Independent mode
FB with PH/EN or PWM mode
Figure 9-5. Typical Application Schematic - HW Variant in VQFN-HR Package
9.2.2 SPI Variant
VCC
VCC
5
Oponal (3)
4
Oponal (5)
ADC
RIPROPI
I/O
S
P
I
VCC
RnFAULT
Oponal (6)
nSLEEP
6,7,8,21,22,23
Oponal (1)
24
I/O
CVM2
Oponal (2)
5
I/O
Oponal (3)
4
3
I/O
Op onal (4)
ADC
Op
onal (5)
25
VM
DRVOFF
CVM1
I/O
EN/IN1
3
PH/IN2
OUT2
18,19,20
25
IPROPI
26
nFAULT
27
SDO
OUT1
9,10,11
2
nSCS
28
SDI
GND
12,13,14,
15,16,17
1
RIPROPI
I/O
SSOP SPI
nSLEEP
S
P
I
Reverse Supply
Protected Input
6,7,8,21,22,23
VM
CVM2
DRVOFF
CVM1
EN/IN1
PH/IN2
OUT2
18,19,20
LOAD
IPROPI
VM / GND
26
nFAULT
27
SDO
SCLK
FB with PH/EN or PWM mode
VCC
RnFAULT
Op onal (6)
Daisy Chain capable
Op onal (2)
Oponal (4)
I/O
Daisy Chain capable
CONTROLLER
I/O
24
CONTROLLER
I/O
Oponal (1)
LOAD
I/O
SSOP SPI
Reverse Supply
Protected Input
OUT1
9,10,11
LOAD
2
nSCS
28
SDI
12,13,14,
GND 15,16,17
1
SCLK
HS/ LS load in Independent mode
Figure 9-6. Typical Application Schematic - SPI (S) Variant in HVSSOP Package
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VCC
VCC
ADC
5
Op onal (3)
4
Oponal (4)
3
Oponal (5)
25
RIPROPI
I/O
S
P
I
VCC
RnFAULT
Oponal (6)
6,7,8,21,22,23
Logic Supply
VM
DRVOFF
CVM2
CVM1
PH/IN2
OUT2
18,19,20
IPROPI
26
nFAULT
27
SDO
Oponal (3)
4
3
I/O
Oponal (4)
25
ADC
Oponal (5)
OUT1
9,10,11
RIPROPI
I/O
nSCS
28
SDI
GND
CVM2
S
P
I
12,13,14,
15,16,17
1
CVM1
EN/IN1
PH/IN2
OUT2
18,19,20
LOAD
IPROPI
VM / GND
26
nFAULT
27
SDO
2
6,7,8,21,22,23
VM
DRVOFF
VCC
RnFAULT
Op onal (6)
Reverse Supply
Protected Input
SSOP SPI
VDD
5
I/O
EN/IN1
24
Oponal (2)
I/O
CONTROLLER
I/O
Oponal (2)
Daisy Chain capable
CONTROLLER
I/O
VDD
LOAD
I/O
24
Daisy Chain capable
Logic Supply
SSOP SPI
Reverse Supply
Protected Input
OUT1
9,10,11
LOAD
2
nSCS
28
SDI
12,13,14,
GND 15,16,17
1
SCLK
SCLK
HS/ LS load in Independent mode
FB with PH/EN or PWM mode
Figure 9-7. Typical Application Schematic - SPI (P) Variant in HVSSOP Package
VCC
VCC
VQFN-HR SPI
3
Op onal (2)
8
Oponal (3)
9
10
I/O
Oponal (4)
ADC
Oponal (5)
2
RIPROPI
I/O
VCC
RnFAULT
Oponal (6)
DRVOFF
S
P
I
CVM1
CVM2
5
PH/IN2
OUT2
IPROPI
1
nFAULT
14
7
OUT1
11
nSCS
13
6
SDI
Oponal (1)
3
I/O
Oponal (2)
8
I/O
Oponal (3)
9
Op onal (4)
10
Op
onal (5)
2
I/O
EN/IN1
SDO
Daisy Chain capable
CONTROLLER
I/O
VM
GND
12
CONTROLLER
I/O
nSLEEP
VQFN-HR SPI
Reverse Supply
Protected Input
LOAD
I/O
4
I/O
ADC
RIPROPI
I/O
S
P
I
Reverse Supply
Protected Input
4
nSLEEP
VM
CVM2
DRVOFF
CVM1
EN/IN1
5
PH/IN2
OUT2
LOAD
IPROPI
VM / GND
1
nFAULT
14
7
SDO
SCLK
FB with PH/EN or PWM mode
VCC
RnFAULT
Op onal (6)
Daisy Chain capable
Oponal (1)
LOAD
OUT1
11
nSCS
13
6
SDI
GND
12
SCLK
HS/ LS load in Independent mode
Figure 9-8. Typical Application Schematic - SPI (S) Variant in VQFN-HR Package
64
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10 Power Supply Recommendations
The device is designed to operate with an input voltage supply (VM) range from 4.5 V to 40 V. A 0.1-µF ceramic
capacitor rated for VM must be placed as close to the device as possible. Also, an appropriately sized bulk
capacitor must be placed on the VM pin.
10.1 Bulk Capacitance Sizing
Bulk capacitance sizing is an important factor in motor drive system design. It is beneficial to have more bulk
capacitance, while the disadvantages are increased cost and physical size.
The amount of local capacitance needed depends on a variety of factors including:
• The highest current required by the motor system.
• The capacitance of the power supply and the ability of the power supply to source current.
• The amount of parasitic inductance between the power supply and motor system.
• The acceptable voltage ripple.
• The type of motor used (brushed DC, brushless DC, and stepper).
• The motor braking method.
The inductance between the power supply and motor drive system limits the rate that current can change from
the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands
or dumps from the motor with a change in voltage. When sufficient bulk capacitance is used, the motor voltage
remains stable, and high current can be quickly supplied.
The data sheet provides a recommended value, but system-level testing is required to determine the appropriate
sized bulk capacitor.
Parasitic Wire
Inductance
Motor Drive System
Power Supply
VM
+
+
Motor Driver
±
GND
Local
Bulk Capacitor
IC Bypass
Capacitor
Figure 10-1. Example Setup of Motor Drive System With External Power Supply
The voltage rating for bulk capacitors should be higher than the operating voltage to provide a margin for cases
when the motor transfers energy to the supply.
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11 Layout
11.1 Layout Guidelines
Each VM pin must be bypassed to ground using low-ESR ceramic bypass capacitors with recommended values
of 0.1 μF rated for VM. These capacitors should be placed as close to the VM pins as possible with a thick trace
or ground plane connection to the device GND pin.
Additional bulk capacitance is required to bypass the high current path. This bulk capacitance should be placed
such that it minimizes the length of any high current paths. The connecting metal traces should be as wide as
possible, with numerous vias connecting PCB layers. These practices minimize inductance and allow the bulk
capacitor to deliver high current.
For the SPI (P) device variant, VDD pin may be bypassed to ground using low-ESR ceramic 6.3 V bypass
capacitor with recommended values of 0.1 μF.
11.2 Layout Example
The following figure shows a layout example for a 4 cm X 4 cm x 1.6 mm, 4 layer PCB for a leaded package
device. The 4 layers uses 2 oz copper on top/ bottom signal layers and 1 oz copper on internal supply layers,
with 0.3 mm thermal via drill diameter, 0.025 mm Cu plating, 1 mm minimum via pitch. The same layout can be
adopted for the non-leaded VQFN-HR package as well. The Section 7.5.14 for the 4 cm X 4 cm X 1.6 mm is
based on a similar layout.
Note: The layout example shown is for a full bridge topology using DRV824xQ1 device in SSOP package.
Figure 11-1. Layout example: 4cm x 4 cm x 1.6mm, 4 layer PCB
66
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Full Bridge Driver Junction Temperature Estimator (Excel-based worksheet)
• Texas Instruments, Calculating Motor Driver Power Dissipation application report
• Texas Instruments, Current Recirculation and Decay Modes application report
• Texas Instruments, PowerPAD™ Made Easy application report
• Texas Instruments, PowerPAD™ Thermally Enhanced Package application report
• Texas Instruments, Understanding Motor Driver Current Ratings application report
• Texas Instruments, Best Practices for Board Layout of Motor Drivers application report
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
12.4 Trademarks
All trademarks are the property of their respective owners.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and order-able information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
DRV8243HQDGQRQ1
ACTIVE
HVSSOP
DGQ
28
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
8243H
Samples
DRV8243HQRXYRQ1
ACTIVE
VQFN-HR
RXY
14
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
DRV8243H
Samples
DRV8243PQDGQRQ1
ACTIVE
HVSSOP
DGQ
28
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
8243P
Samples
DRV8243SQDGQRQ1
ACTIVE
HVSSOP
DGQ
28
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
8243S
Samples
DRV8243SQRXYRQ1
ACTIVE
VQFN-HR
RXY
14
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
DRV8243S
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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