DRV8300U
SLVSGY3A – JULY 2022 – REVISED OCTOBER 2022
DRV8300U: 100-V Three-Phase BLDC Gate Driver
1 Features
3 Description
•
DRV8300U is 100-V three half-bridge gate drivers,
capable of driving high-side and low-side N-channel
power MOSFETs. The DRV8300UD generates the
correct gate drive voltages using an integrated
bootstrap diode and external capacitor for the highside MOSFETs. GVDD is used to generate gate drive
voltage for the low-side MOSFETs. The Gate Drive
architecture supports peak up to 750-mA source and
1.5-A sink currents.
•
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•
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100-V Three Phase Half-Bridge Gate driver
– Drives N-Channel MOSFETs (NMOS)
– Gate Driver Supply (GVDD): 5-20 V
– MOSFET supply (SHx) support upto 100 V
Integrated Bootstrap Diodes (DRV8300UD
devices)
Supports Inverting and Non-Inverting INLx inputs
Bootstrap gate drive architecture
– 750-mA source current
– 1.5-A sink current
Supports up to 15S battery powered applications
Higher BSTUV (8V typ) and GVDDUV (7.6V typ)
threshold to support standard MOSFETs
Low leakage current on SHx pins ( 1µF
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7.4 Thermal Information
DRV8300U
THERMAL
RθJA
METRIC(1)
PW (TSSOP)
RGE (VQFN)
20 PINS
24 PINS
97.4
49.3
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
38.3
42.5
°C/W
RθJB
Junction-to-board thermal resistance
48.8
26.5
°C/W
ΨJT
Junction-to-top characterization parameter
4.3
2.2
°C/W
ΨJB
Junction-to-board characterization parameter
48.4
26.4
°C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance
N/A
11.5
°C/W
(1)
Junction-to-ambient thermal resistance
UNIT
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
8.7 V ≤ VGVDD ≤ 20 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLIES (GVDD, BSTx)
GVDD standby mode current
INHx = INLX = 0; VBSTx = VGVDD
400
800
1400
µA
GVDD active mode current
INHx = INLX = Switching @20kHz; VBSTx
= VGVDD; NO FETs connected
400
825
1400
µA
ILBSx
Bootstrap pin leakage current
VBSTx = VSHx = 85V; VGVDD = 0V
2
4
7
µA
ILBS_TRAN
Bootstrap pin active mode transient
leakage current
INHx = Switching@20kHz
30
105
220
µA
ILBS_DC
Bootstrap pin active mode leakage
static current
INHx = High
30
85
150
µA
ILSHx
High-side source pin leakage current
INHx = INLX = 0; VBSTx - VSHx = 12V;
VSHx = 0 to 85V
30
55
80
µA
IGVDD
LOGIC-LEVEL INPUTS (INHx, INLx, MODE)
VIL_MODE
Input logic low voltage
Mode pin
0.6
V
VIL
Input logic low voltage
INLx, INHx pins
0.8
V
VIH_MODE
Input logic high voltage
Mode pin
3.7
V
VIH
Input logic high voltage
INLx, INHx pins
2.0
V
VHYS_MODE
Input hysteresis
Mode pin
1600
2000
2400
mV
VHYS
Input hysteresis
INLx, INHx pins
40
100
260
mV
VPIN (Pin Voltage) = 0 V; INLx in noninverting mode
-1
0
1
µA
VPIN (Pin Voltage) = 0 V; INLx in inverting
mode
5
20
30
µA
VPIN (Pin Voltage) = 5 V; INLx in noninverting mode
5
20
30
µA
VPIN (Pin Voltage) = 5 V; INLx in inverting
mode
0
0.5
1.5
µA
-1
0
1
µA
IIL_INLx
IIH_INLx
INLx Input logic low current
INLx Input logic high current
IIL
INHx, MODE Input logic low current
VPIN (Pin Voltage) = 0 V;
IIH
INHx, MODE Input logic high current
VPIN (Pin Voltage) = 5 V;
5
20
30
µA
RPD_INHx
INHx Input pulldown resistance
To GND
120
200
280
kΩ
RPD_INLx
INLx Input pulldown resistance
To GND, INLx in non-inverting mode
120
200
280
kΩ
RPU_INLx
INLx Input pullup resistance
To INT_5V, INLx in inverting mode
120
200
280
kΩ
RPD_MODE
MODE Input pulldown resistance
To GND
120
200
280
kΩ
GATE DRIVERS (GHx, GLx, SHx, SLx)
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8.7 V ≤ VGVDD ≤ 20 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0
0.15
0.35
V
VGHx_LO
I
= -100 mA; VGVDD = 12V; No FETs
High-side gate drive low level voltage GLx
connected
VGHx_HI
High-side gate drive high level
voltage (VBSTx - VGHx)
IGHx = 100 mA; VGVDD = 12V; No FETs
connected
0.3
0.6
1.2
V
VGLx_LO
Low-side gate drive low level voltage
IGLx = -100 mA; VGVDD = 12V; No FETs
connected
0
0.15
0.35
V
VGLx_HI
Low-side gate drive high level voltage IGHx = 100 mA; VGVDD = 12V; No FETs
(VGVDD - VGHx)
connected
0.3
0.6
1.2
V
IDRIVEP_HS
High-side peak source gate current
GHx-SHx = 12V
400
750
1200
mA
IDRIVEN_HS
High-side peak sink gate current
GHx-SHx = 0V
850
1500
2100
mA
IDRIVEP_LS
Low-side peak source gate current
GLx = 12V
400
750
1200
mA
IDRIVEN_LS
Low-side peak sink gate current
GLx = 0V
850
1500
2100
mA
tPD
Input to output propagation delay
INHx, INLx to GHx, GLx; VGVDD = VBSTx
- VSHx > 8V; SHx = 0V, No load on GHx
and GLx
70
125
180
ns
tPD_match
Matching propagation delay per
phase
GHx turning OFF to GLx turning ON, GLx
turning OFF to GHx turning ON; VGVDD =
VBSTx - VSHx > 8V; SHx = 0V, No load on
GHx and GLx
-30
±4
30
ns
tPD_match
GHx/GLx turning ON to GHy/GLy turning
Matching propagation delay phase to ON, GHx/GLx turning OFF to GHy/GLy
phase
turning OFF; VGVDD = VBSTx - VSHx > 8V;
SHx = 0V, No load on GHx and GLx
-30
±4
30
ns
tR_GLx
GLx rise time (10% to 90%)
CLOAD = 1000 pF; VGVDD = VBSTx - VSHx >
8V; SHx = 0V
10
24
50
ns
tR_GHx
GHx rise time (10% to 90%)
CLOAD = 1000 pF; VGVDD = VBSTx - VSHx >
8V; SHx = 0V
10
24
50
ns
tF_GLx
GLx fall time (90% to 10%)
CLOAD = 1000 pF; VGVDD = VBSTx - VSHx >
8V; SHx = 0V
5
12
30
ns
tF_GHx
GHx fall time (90% to 10%)
CLOAD = 1000 pF; VGVDD = VBSTx - VSHx >
8V; SHx = 0V
5
12
30
ns
DT pin floating
150
215
280
ns
DT pin connected to GND
150
215
280
ns
tDEAD
Gate drive dead time
tPW_MIN
40 kΩ between DT pin and GND
150
200
260
ns
400 kΩ between DT pin and GND
1500
2000
2600
ns
40
70
150
ns
IBOOT = 100 µA
0.45
0.7
0.85
V
IBOOT = 100 mA
2
2.3
3.1
V
11
15
25
Ω
Supply rising
8
8.3
8.6
V
Supply falling
7.8
8
8.25
V
Rising to falling threshold
295
330
360
mV
5
10
13
µs
Minimum input pulse width on INHx,
INLx that changes the output on
GHx, GLx
BOOTSTRAP DIODES(DRV8300UD, DRV8300UDI)
VBOOTD
Bootstrap diode forward voltage
RBOOTD
Bootstrap dynamic resistance
(ΔVBOOTD/ΔIBOOT)
IBOOT = 100 mA and 80 mA
PROTECTION CIRCUITS
VGVDDUV
Gate Driver Supply undervoltage
lockout (GVDDUV)
VGVDDUV_HYS Gate Driver Supply UV hysteresis
tGVDDUV
8
Gate Driver Supply undervoltage
deglitch time
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8.7 V ≤ VGVDD ≤ 20 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
Supply rising
7.5
8
8.7
V
Boot Strap undervoltage lockout
(VBSTx - VSHx)
Supply falling
6.9
7.6
8.4
V
VBSTUV_HYS
Bootstrap UV hysteresis
Rising to falling threshold
250
400
850
mV
tBSTUV
Bootstrap undervoltage deglitch time
5.5
10
22
µs
VBSTUV
TEST CONDITIONS
Boot Strap undervoltage lockout
(VBSTx - VSHx)
UNIT
7.6 Timing Diagrams
INHx/INLx
50%
50%
GHx/GLx
tPD
tPD
Figure 7-1. Propagation Delay(tPD)
INHx
INLx
GHx
GLx
tPD_match
tPD_match
Figure 7-2. Propagation Delay Match (tPD_match)
7.7 Typical Characteristics
1150
1150
1100
1100
1050
Active Current (uA)
Active Current (uA)
1050
1000
950
900
850
TJ = -40C
TJ = 25C
TJ = 150C
800
750
4
6
8
10
12
14
GVDD Voltage (V)
16
18
20
Figure 7-3. Supply Current Over GVDD Voltage
1000
VGVDD = 5 V
VGVDD = 12 V
VGVDD = 20 V
950
900
850
800
750
700
-40
-20
0
20
40
60
80 100
Junction Temperature (C)
120
140
160
Figure 7-4. Supply Current Over Temperature
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Figure 7-5. Bootstrap Resistance Over GVDD
Voltage
10
Figure 7-6. Bootstrap Diode Forward Voltage over
GVDD Voltage
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8 Detailed Description
8.1 Overview
The DRV8300U family of devices is a gate driver for three-phase motor drive applications. These devices
decrease system component count, saves PCB space and cost by integrating three independent half-bridge gate
drivers and optional bootstrap diodes.
DRV8300U supports external N-channel high-side and low-side power MOSFETs and can drive 750-mA source,
1.5-A sink peak currents with total combined 30-mA average output current. The DRV8300U family of devices
are available in 0.5-mm pitch QFN and 0.65-mm pitch TSSOP surface-mount packages. The QFN size is 4 × 4
mm (0.5-mm pin pitch) for the 24-pin package, and TSSOP body size is 6.5 × 4.4 mm (0.65-mm pin pitch) for the
20-pin package.
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8.2 Functional Block Diagram
GVDD
CGVDD
PVDD
GVDD
INHA
HS
INT_5V
BSTA
HS
GHA
CBSTA RGHA
SHA
GVDD
INLA/INLA
LS
LS
RGLA
GLA
MODE**
Gate Driver
GVDD
BSTB
PVDD
CBSTB
HS
INHB
INT_5V
Input logic
control
HS
MODE**
SHB
LS
LS
GLB
RGLB
Gate Driver
GVDD
INHC
RGHB
GVDD
INLB/INLB
ShootThrough
Prevention
GHB
HS
INT_5V
PVDD
BSTC
HS
GHC
CBSTC
RGHC
SHC
GVDD
INLC/INLC
LS
LS
GLC
RGLC
MODE**
DT**
Gate Driver
MODE**
GND
PowerPAD
** QFN-24 Package
Figure 8-1. Block Diagram for DRV8300UD
12
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8.3 Feature Description
8.3.1 Three BLDC Gate Drivers
The DRV8300U integrates three half-bridge gate drivers, each capable of driving high-side and low-side Nchannel power MOSFETs. Input on GVDD provides the gate bias voltage for the low-side MOSFETs. The high
voltage is generated using bootstrap capacitor and GVDD supply. The half-bridge gate drivers can be used in
combination to drive a three-phase motor or separately to drive other types of loads.
8.3.1.1 Gate Drive Timings
8.3.1.1.1 Propagation Delay
The propagation delay time (tpd) is measured as the time between an input logic edge to a detected output
change. This time has two parts consisting of the input deglitcher delay and the delay through the analog gate
drivers.
The input deglitcher prevents high-frequency noise on the input pins from affecting the output state of the gate
drivers. The analog gate drivers have a small delay that contributes to the overall propagation delay of the
device.
8.3.1.1.2 Deadtime and Cross-Conduction Prevention
In the DRV8300U, high-side and low-side inputs operate independently, with an exception to prevent cross
conduction when high and low side are turned ON at same time. The DRV8300U turns OFF high-side and
low-side output to prevent shoot through when the both high-side and low-side inputs are at logic HIGH at same
time.
The DRV8300U also provides option to insert additional deadtime to prevent the external high-side and low-side
MOSFET from switching on at the same time. In the devices with DT pin (QFN package), deadtime can be
linearly adjusted between 200 ns to 2000 ns by configuring resistor value between DT and GND. When the DT
pin is left floating, fixed deadtime of 200 nS (typical value) is inserted. The value of resistor can be calculated
using Equation 1.
4&6 (GÀ) =
&A=@PEIA (J5)
5
(1)
In the devices without DT pin (TSSOP package), fixed deadtime of 200 ns (typical value) is inserted to prevent
high and low side gate output turning ON at same time.
INHx/INLx Inputs
INHx
INLx
GHx/GLx outputs
GHx
GLx
DT
DT
Cross
Conduction
Prevention
Figure 8-2. Cross Conduction Prevention and Deadtime Insertion
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8.3.1.2 Mode (Inverting and non inverting INLx)
The DRV8300U has flexibility of accepting different kind of inputs on INLx. In the devices with MODE pin
(QFN package), the DRV8300U provides option of configuring the GLx outputs to be inverted or non-inverted
compared to polarity of signal on INLx pins. When the MODE pin is left floating, the INLx is configured to be in
non-inverting mode and GLx output is in phase with respect to INLx (see Figure 8-3), whereas when the MODE
pin is connected to GVDD, GLx output is out of phase with respect to INLx (see Figure 8-4). In devices without
MODE pin (TSSOP package device), there are different device option available for inverting and non inverting
inputs (see Section 5).
INHx
INLx
GHx
GLx
DT
DT
DT
Figure 8-3. Non-Inverted INLx inputs
INHx
INLx
GHx
GLx
DT
DT
DT
Figure 8-4. Inverted INLx inputs
14
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8.3.2 Pin Diagrams
Figure 8-5 shows the input structure for the logic level pins INHx, INLx. INHx and non-inverted INLx has passive
pull down, so when inputs are floating the output the gate driver will be pulled low. Figure 8-6 shows the input
structure for the inverted INLx pins. The inverted INLx has passive pull up, so when inputs are floating the output
of the low-side gate driver will be pulled low.
INT_5V
INPUT
INPUT
200 k
Logic High
Logic High
INHx
INLx
INLx
Logic Low
Logic Low
200 k
Figure 8-5. INHx and non-inverted INLx Logic-Level
Input Pin Structure
Figure 8-6. Inverted INLx Logic-Level Input Pin
Structure
8.3.3 Gate Driver Protective Circuits
The DRV8300U is protected against BSTx undervoltage and GVDD undervoltage events.
Table 8-1. Fault Action and Response
FAULT
CONDITION
GATE DRIVER
RECOVERY
VBSTx undervoltage
(BSTUV)
VBSTx < VBSTUV
GHx - Hi-Z
Automatic:
VBSTx > VBSTUV and low to high
PWM edge detected on INHx pin
GVDD undervoltage
(GVDDUV)
VGVDD < VGVDDUV
Hi-Z
Automatic:
VGVDD > VGVDDUV
8.3.3.1 VBSTx Undervoltage Lockout (BSTUV)
The DRV8300U has separate voltage comparator to detect undervoltage condition for each phases. If at any
time the voltage on the BSTx pin falls lower than the VBSTUV threshold, high side external MOSFETs of that
particular phase is disabled by disabling (Hi-Z) GHx pin. Normal operation starts again when the BSTUV
condition clears and low to high PWM edge is detected on INHx input of the same phase that BSTUV condition
was detected. BSTUV protection ensures that high-side MOSFETs are not driven when the BSTx pins has lower
value.
8.3.3.2 GVDD Undervoltage Lockout (GVDDUV)
If at any time the voltage on the GVDD pin falls lower than the VGVDDUV threshold voltage, all of the external
MOSFETs are disabled. Normal operation starts again when the GVDDUV condition clears. GVDDUV protection
ensures that external MOSFETs are not driven when the GVDD input is at lower value.
8.4 Device Functional Modes
The DRV8300U is in operating (active) mode, whenever the GVDD and BST pins are higher than the UV
threshold (GVDD > VGVDDUVand VBSTX > VBSTUV). In active mode, the gate driver output GHx and GLX will
follow respective inputs INHx and INLx.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The DRV8300U family of devices is primarily used in applications for three-phase brushless DC motor control.
The design procedures in the Section 9.2 section highlight how to use and configure the DRV8300U.
16
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9.2 Typical Application
GVDD
GVDD
CGVDD
PVDD
GND
External
Supply
GND
BSTA
CBSTA RGHA
GHA
SHA
RGLA
INHA
GLA
INLA
INHB
PWM
MCU
INLB
PVDD
BSTB
INHC
INLC
CBSTB
RGHB
GHB
ADC
SHB
RGLB
DRV8300D
GLB
GVDD
MODE**
PVDD
BSTC
BSTC
CBSTC
RGHC
GHC
GND or Floating
GHC
SHC
SHC
RDT
DT**
RGLC
GLC
** QFN-24 Package
GLC
RSENSE
INC+
RSENSE
R
INB+
RSENSE
INA+
INA-
INB-
INC-
R
R
R
OUT
±
OUT
OUT
Reference
Voltage
± +
VREF
VREF
IN- INx+
IN-IN+
RR
IN-IN+
R
IN+
INx-
R
R
VREF
R
± +
R
+
R R
R
+
Current Sense Amplifier 1x or 3x
±
Figure 9-1. Application Schematic
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9.2.1 Design Requirements
Table 9-1 lists the example design input parameters for system design.
Table 9-1. Design Parameters
EXAMPLE DESIGN PARAMETER
MOSFET
Gate Supply Voltage
Gate Charge
REFERENCE
EXAMPLE VALUE
-
CSD19532Q5B
VGVDD
12 V
QG
48 nC
9.2.2 Bootstrap Capacitor and GVDD Capacitor Selection
The bootstrap capacitor must be sized to maintain the bootstrap voltage above the undervoltage lockout for
normal operation. Equation 2 calculates the maximum allowable voltage drop across the bootstrap capacitor:
¿8$56: = 8)8&& F 8$116& F 8$5678
(2)
=12 V – 0.85 V – 4.5 V = 6.65 V
where
• VGVDD is the supply voltage of the gate drive
• VBOOTD is the forward voltage drop of the bootstrap diode
• VBSTUV is the threshold of the bootstrap undervoltage lockout
In this example the allowed voltage drop across bootstrap capacitor is 6.65 V. It is generally recommended that
ripple voltage on both the bootstrap capacitor and GVDD capacitor should be minimized as much as possible.
Many of commercial, industrial, and automotive applications use ripple value between 0.5 V to 1 V.
The total charge needed per switching cycle can be estimated with Equation 3:
3616 = 3) +
+.$5_64#05
B59
(3)
=48 nC + 220 μA/20 kHz = 50 nC + 11 nC = 59 nC
where
• QG is the total MOSFET gate charge
• ILBS_TRAN is the bootstrap pin leakage current
• fSW is the is the PWM frequency
The minimum bootstrap capacitor an then be estimated as below assuming 1V ΔVBSTx:
%$56_/+0 = 3616W¿8
(4)
$56:
= 59 nC / 1 V = 59 nF
The calculated value of minimum bootstrap capacitor is 59 nF. It should be noted that, this value of capacitance
is needed at full bias voltage. In practice, the value of the bootstrap capacitor must be greater than calculated
value to allow for situations where the power stage may skip pulse due to various transient conditions. It is
recommended to use a 100 nF bootstrap capacitor in this example. It is also recommenced to include enough
margin and place the bootstrap capacitor as close to the BSTx and SHx pins as possible.
%)8&& R 10 × %$56:
(5)
= 10*100 nF= 1 μF
18
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For this example application choose 1 µF CGVDD capacitor. Choose a capacitor with a voltage rating at
least twice the maximum voltage that it will be exposed to because most ceramic capacitors lose significant
capacitance when biased. This value also improves the long term reliability of the system.
9.2.3 Application Curves
GHA
GHA
SHA
SHA
GLA
GLA
Figure 9-2. Gate voltages, SHx rising with 15 ohm
gate resistor and CSD19532Q5B MOSFET
Figure 9-3. Gate voltages, SHx falling with 15 ohm
gate resistor and CSD19532Q5B MOSFET
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10 Power Supply Recommendations
The DRV8300U is designed to operate from an input voltage supply (GVDD) range from 4.8 V to 20 V. A local
bypass capacitor should be placed between the GVDD and GND pins. This capacitor should be located as close
to the device as possible. A low ESR, ceramic surface mount capacitor is recommended. It is recommended
to use two capacitors across GVDD and GND: a low capacitance ceramic surface-mount capacitor for high
frequency filtering placed very close to GVDD and GND pin, and another high capacitance value surfacemount
capacitor for device bias requirements. In a similar manner, the current pulses delivered by the GHx pins are
sourced from the BSTx pins. Therefore, capacitor across the BSTx to SHx is recommended, it should be high
enough capacitance value capacitor to deliver GHx pulses
20
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DRV8300U
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SLVSGY3A – JULY 2022 – REVISED OCTOBER 2022
11 Layout
11.1 Layout Guidelines
•
•
•
•
•
•
•
•
Low ESR/ESL capacitors must be connected close to the device between GVDD and GND and between
BSTx and SHx pins to support high peak currents drawn from GVDD and BSTx pins during the turn-on of the
external MOSFETs.
To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor and a
good quality ceramic capacitor must be connected between the high side MOSFET drain and ground.
In order to avoid large negative transients on the switch node (SHx) pin, the parasitic inductances between
the source of the high-side MOSFET and the source of the low-side MOSFET must be minimized.
In order to avoid unexpected transients, the parasitic inductance of the GHx, SHx, and GLx connections must
be minimized. Minimize the trace length and number of vias wherever possible. Minimum 10 mil and typical
15 mil trace width is recommended.
Resistance between DT and GND must be place as close as possible to device
Place the gate driver as close to the MOSFETs as possible. Confine the high peak currents that charge
and discharge the MOSFET gates to a minimal physical area by reducing trace length. This confinement
decreases the loop inductance and minimize noise issues on the gate terminals of the MOSFETs.
In QFN package device variants, NC pins can be connected to GND to increase ground conenction between
thermal pad and external ground plane.
Refer to sections General Routing Techniques and MOSFET Placement and Power Stage Routing in
Application Report
11.2 Layout Example
DT resistor
close to device
BSTx capacitor close
to device
GVDD capacitor
close to device
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SLVSGY3A – JULY 2022 – REVISED OCTOBER 2022
12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
22
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PACKAGE OPTION ADDENDUM
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2-Nov-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
DRV8300UDIPWR
ACTIVE
TSSOP
PW
20
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
8300UDI
Samples
DRV8300UDPWR
ACTIVE
TSSOP
PW
20
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
8300UD
Samples
DRV8300UDRGER
ACTIVE
VQFN
RGE
24
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
8300UD
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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