TMS570LS31x/21x 16/32-Bit RISC Flash
Microcontroller
Technical Reference Manual
Literature Number: SPNU499C
March 2018
Contents
Preface....................................................................................................................................... 91
1
Introduction ....................................................................................................................... 93
1.1
1.2
1.3
2
2.2
2.3
2.4
2.5
Introduction .................................................................................................................. 99
2.1.1 Architecture Block Diagram ...................................................................................... 99
2.1.2 Definitions of Terms ............................................................................................. 100
2.1.3 Bus Master / Slave Access Privileges ........................................................................ 102
Memory Organization .................................................................................................... 103
2.2.1 Memory-Map Overview ......................................................................................... 103
2.2.2 Memory-Map Table .............................................................................................. 104
2.2.3 Flash Memory .................................................................................................... 108
2.2.4 On-Chip SRAM ................................................................................................... 110
Exceptions ................................................................................................................. 115
2.3.1 Resets ............................................................................................................. 115
2.3.2 Aborts ............................................................................................................. 115
2.3.3 System Software Interrupts ..................................................................................... 117
Clocks ...................................................................................................................... 118
2.4.1 Clock Sources .................................................................................................... 118
2.4.2 Clock Domains ................................................................................................... 119
2.4.3 Low Power Modes ............................................................................................... 121
2.4.4 Clock Test Mode ................................................................................................. 123
2.4.5 Embedded Trace Macrocell (ETM-R4)........................................................................ 124
2.4.6 Safety Considerations for Clocks .............................................................................. 125
System and Peripheral Control Registers ............................................................................. 127
2.5.1 Primary System Control Registers (SYS) .................................................................... 127
2.5.2 Secondary System Control Registers (SYS2) ............................................................... 181
2.5.3 Peripheral Central Resource (PCR) Control Registers .................................................... 189
Power Management Module (PMM) ..................................................................................... 204
3.1
3.2
3.3
2
94
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97
97
Architecture ....................................................................................................................... 98
2.1
3
Designed for Safety Applications .........................................................................................
Family Description..........................................................................................................
Endianism Considerations ................................................................................................
1.3.1 TMS570: Big Endian (BE32) .....................................................................................
Overview ...................................................................................................................
3.1.1 Main Features of the Power Management Module (PMM) .................................................
3.1.2 Block Diagram ....................................................................................................
Power Domains ...........................................................................................................
PMM Operation ...........................................................................................................
3.3.1 Power Switch .....................................................................................................
3.3.2 Power Domain State ............................................................................................
3.3.3 Default Power Domain State ...................................................................................
3.3.4 Disabling a Power Domain Permanently .....................................................................
3.3.5 Changing Power Domain State ................................................................................
3.3.6 Reset Management ..............................................................................................
3.3.7 Diagnostic Power State Controller (PSCON) ................................................................
3.3.8 PSCON Compare Block ........................................................................................
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3.4
4
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230
I/O Multiplexing and Control Module (IOMM) ........................................................................ 231
4.1
4.2
4.3
4.4
4.5
4.6
5
PMM Registers ............................................................................................................
3.4.1 Logic Power Domain Control Register (LOGICPDPWRCTRL0) ..........................................
3.4.2 Memory Power Domain Control Register 0 (MEMPDPWRCTRL0) .......................................
3.4.3 Power Domain Clock Disable Register (PDCLKDISREG) .................................................
3.4.4 Power Domain Clock Disable Set Register (PDCLKDISSETREG) ......................................
3.4.5 Power Domain Clock Disable Clear Register (PDCLKDISCLRREG) .....................................
3.4.6 Logic Power Domain PD2 Power Status Register (LOGICPDPWRSTAT0) .............................
3.4.7 Logic Power Domain PD3 Power Status Register (LOGICPDPWRSTAT1) .............................
3.4.8 Logic Power Domain PD4 Power Status Register (LOGICPDPWRSTAT2) .............................
3.4.9 Logic Power Domain PD5 Power Status Register (LOGICPDPWRSTAT3) .............................
3.4.10 Memory Power Domain RAM_PD1 Power Status Register (MEMPDPWRSTAT0) ...................
3.4.11 Memory Power Domain RAM_PD2 Power Status Register (MEMPDPWRSTAT1) ...................
3.4.12 Memory Power Domain RAM_PD3 Power Status Register (MEMPDPWRSTAT2) ...................
3.4.13 Global Control Register 1 (GLOBALCTRL1) ................................................................
3.4.14 Global Status Register (GLOBALSTAT) .....................................................................
3.4.15 PSCON Diagnostic Compare Key Register (PRCKEYREG) .............................................
3.4.16 LogicPD PSCON Diagnostic Compare Status Register 1 (LPDDCSTAT1).............................
3.4.17 LogicPD PSCON Diagnostic Compare Status Register 2 (LPDDCSTAT2).............................
3.4.18 Memory PD PSCON Diagnostic Compare Status Register 1 (MPDDCSTAT1) ........................
3.4.19 Memory PD PSCON Diagnostic Compare Status Register 2 (MPDDCSTAT2) ........................
3.4.20 Isolation Diagnostic Status Register (ISODIAGSTAT) .....................................................
Overview ..................................................................................................................
Main Features of I/O Multiplexing Module (IOMM) ..................................................................
Control of Multiplexed Functions .......................................................................................
4.3.1 Control of Multiplexed Outputs ................................................................................
4.3.2 Control of Multiplexed Inputs ..................................................................................
4.3.3 Control of Special Multiplexed Options ......................................................................
Safety Features ..........................................................................................................
4.4.1 Locking Mechanism for Memory-Mapped Registers .......................................................
4.4.2 Error Conditions .................................................................................................
IOMM Registers ...........................................................................................................
4.5.1 REVISION_REG: Revision Register .........................................................................
4.5.2 ENDIAN_REG: Device Endianness Register ...............................................................
4.5.3 KICK_REG0: Kicker Register 0 ...............................................................................
4.5.4 KICK_REG1: Kicker Register 1 ...............................................................................
4.5.5 ERR_RAW_STATUS_REG: Error Raw Status / Set Register ............................................
4.5.6 ERR_ENABLED_STATUS_REG: Error Enabled Status / Clear Register ...............................
4.5.7 ERR_ENABLE_REG: Error Signaling Enable Register ....................................................
4.5.8 ERR_ENABLE_CLR_REG: Error Signaling Enable Clear Register ......................................
4.5.9 FAULT_ADDRESS_REG: Fault Address Register ..........................................................
4.5.10 FAULT_STATUS_REG: Fault Status Register ............................................................
4.5.11 FAULT_CLEAR_REG: Fault Clear Register ...............................................................
4.5.12 PINMMRnn: Pin Multiplexing Control Registers ...........................................................
Signal Multiplexing and Control .........................................................................................
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F021 Flash Module Controller (FMC) ................................................................................... 250
5.1
5.2
5.3
Overview ..................................................................................................................
5.1.1 Features ..........................................................................................................
5.1.2 Definition of Terms ..............................................................................................
5.1.3 F021 Flash Tools ................................................................................................
Default Flash Configuration .............................................................................................
SECDED ..................................................................................................................
5.3.1 SECDED Initialization ...........................................................................................
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5.4
5.5
5.6
5.7
4
5.3.2 ECC Encoding....................................................................................................
5.3.3 Syndrome Table: Decode to Bit in Error ......................................................................
5.3.4 Syndrome Table: An Alternate Method .......................................................................
Memory Map ..............................................................................................................
5.4.1 Location of Flash ECC Bits .....................................................................................
5.4.2 OTP Memory .....................................................................................................
Power On, Power Off, and Reset Considerations ...................................................................
5.5.1 Error Checking at Power On ...................................................................................
5.5.2 Flash Integrity when Reset while Programming or Erasing ................................................
5.5.3 Flash Integrity at Power Off ....................................................................................
Emulation and SIL3 Diagnostic Modes ................................................................................
5.6.1 System Emulation ...............................................................................................
5.6.2 Diagnostic Mode .................................................................................................
5.6.3 Diagnostic Mode Summary .....................................................................................
5.6.4 Read Margin ......................................................................................................
Control Registers .........................................................................................................
5.7.1 Flash Option Control Register (FRDCNTL) ..................................................................
5.7.2 Flash Error Detection and Correction Control Register 1 (FEDACCTRL1) .............................
5.7.3 Flash Error Correction and Correction Control Register 2 (FEDACCTRL2) ............................
5.7.4 Flash Correctable Error Count Register (FCOR_ERR_CNT) .............................................
5.7.5 Flash Correctable Error Address Register (FCOR_ERR_ADD) ..........................................
5.7.6 Flash Correctable Error Position Register (FCOR_ERR_POS) ..........................................
5.7.7 Flash Error Detection and Correction Status Register (FEDACSTATUS) ...............................
5.7.8 Flash Uncorrectable Error Address Register (FUNC_ERR_ADD) .......................................
5.7.9 Flash Error Detection and Correction Sector Disable Register (FEDACSDIS) .........................
5.7.10 Primary Address Tag Register (FPRIM_ADD_TAG) ......................................................
5.7.11 Duplicate Address Tag Register (FDUP_ADD_TAG) .....................................................
5.7.12 Flash Bank Protection Register (FBPROT) ................................................................
5.7.13 Flash Bank Sector Enable Register (FBSE) ................................................................
5.7.14 Flash Bank Busy Register (FBBUSY) .......................................................................
5.7.15 Flash Bank Access Control Register (FBAC) ..............................................................
5.7.16 Flash Bank Fallback Power Register (FBFALLBACK) ....................................................
5.7.17 Flash Bank/Pump Ready Register (FBPRDY) .............................................................
5.7.18 Flash Pump Access Control Register 1 (FPAC1) .........................................................
5.7.19 Flash Pump Access Control Register 2 (FPAC2) .........................................................
5.7.20 Flash Module Access Control Register (FMAC) ...........................................................
5.7.21 Flash Module Status Register (FMSTAT) ..................................................................
5.7.22 EEPROM Emulation Data MSW Register (FEMU_DMSW) ...............................................
5.7.23 EEPROM Emulation Data LSW Register (FEMU_DLSW) ................................................
5.7.24 EEPROM Emulation ECC Register (FEMU_ECC) .........................................................
5.7.25 EEPROM Emulation Address Register (FEMU_ADDR) ...................................................
5.7.26 Diagnostic Control Register (FDIAGCTRL) .................................................................
5.7.27 Uncorrected Raw Data High Register (FRAW_DATAH) ..................................................
5.7.28 Uncorrected Raw Data Low Register (FRAW_DATAL) ...................................................
5.7.29 Uncorrected Raw ECC Register (FRAW_ECC) ............................................................
5.7.30 Parity Override Register (FPAR_OVR) ......................................................................
5.7.31 Flash Error Detection and Correction Sector Disable Register (FEDACSDIS2) ......................
5.7.32 FSM Register Write Enable (FSM_WR_ENA) .............................................................
5.7.33 FSM Sector Register (FSM_SECTOR) .....................................................................
5.7.34 EEPROM Emulation Configuration Register (EEPROM_CONFIG) .....................................
5.7.35 EEPROM Emulation Error Detection and Correction Control Register 1 (EE_CTRL1) ..............
5.7.36 EEPROM Emulation Error Correction and Correction Control Register 2 (EE_CTRL2) .............
5.7.37 EEPROM Emulation Correctable Error Count Register (EE_COR_ERR_CNT) .......................
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5.7.38
5.7.39
5.7.40
5.7.41
5.7.42
6
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305
306
307
308
Tightly-Coupled RAM (TCRAM) Module ............................................................................... 309
6.1
6.2
6.3
6.4
6.5
6.6
6.7
7
EEPROM Emulation Correctable Error Address Register (EE_COR_ERR_ADD) ....................
EEPROM Emulation Correctable Error Position Register (EE_COR_ERR_POS) ....................
EEPROM Emulation Error Status Register (EE_STATUS) ..............................................
EEPROM Emulation Uncorrectable Error Address Register (EE_UNC_ERR_ADD) .................
Flash Bank Configuration Register (FCFG_BANK) .......................................................
Overview ...................................................................................................................
6.1.1 B0TCM and B1TCM Connection Diagram ...................................................................
6.1.2 Main Features ....................................................................................................
RAM Memory Map ........................................................................................................
Safety Features ...........................................................................................................
6.3.1 Support for Cortex-R4F CPU's Single-Error-Correction Double-Error-Detection (SECDED) ..........
6.3.2 Support for Cortex-R4F CPU's Address and Control Bus Parity Checking ..............................
6.3.3 Redundant Address Decode ...................................................................................
TCRAM Auto-Initialization ...............................................................................................
Trace Module Support ...................................................................................................
Emulation / Debug Mode Behavior .....................................................................................
Control and Status Registers ............................................................................................
6.7.1 TCRAM Module Control Register (RAMCTRL) ..............................................................
6.7.2 TCRAM Module Single-Bit Error Correction Threshold Register (RAMTHRESHOLD) .................
6.7.3 TCRAM Module Single-Bit Error Occurrences Counter Register (RAMOCCUR) .......................
6.7.4 TCRAM Module Interrupt Control Register (RAMINTCTRL) ...............................................
6.7.5 TCRAM Module Error Status Register (RAMERRSTATUS) ...............................................
6.7.6 TCRAM Module Single-Bit Error Address Register (RAMSERRADDR)..................................
6.7.7 TCRAM Module Uncorrectable Error Address Register (RAMUERRADDR) ............................
6.7.8 TCRAM Module Test Mode Control Register (RAMTEST).................................................
6.7.9 TCRAM Module Test Mode Vector Register (RAMADDRDECVECT) ....................................
6.7.10 TCRAM Module Parity Error Address Register (RAMPERRADDR) .....................................
6.7.11 Auto-Memory Initialization Enable Register (INIT_DOMAIN) .............................................
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323
Programmable Built-In Self-Test (PBIST) Module .................................................................. 324
7.1
7.2
7.3
7.4
7.5
7.6
Overview ..................................................................................................................
7.1.1 Features of PBIST ..............................................................................................
7.1.2 PBIST vs. Application Software-Based Testing..............................................................
7.1.3 PBIST Block Diagram ..........................................................................................
RAM Grouping and Algorithm ..........................................................................................
PBIST Flow ...............................................................................................................
7.3.1 PBIST Sequence ................................................................................................
Memory Test Algorithms on the On-chip ROM ......................................................................
PBIST Control Registers ................................................................................................
7.5.1 RAM Configuration Register (RAMT) .........................................................................
7.5.2 Datalogger Register (DLR) .....................................................................................
7.5.3 PBIST Activate/Clock Enable Register (PACT) ..............................................................
7.5.4 PBIST ID Register ...............................................................................................
7.5.5 Override Register (OVER) ......................................................................................
7.5.6 Fail Status Fail Register (FSRF0) .............................................................................
7.5.7 Fail Status Count Registers (FSRC0 and FSRC1) ..........................................................
7.5.8 Fail Status Address Registers (FSRA0 and FSRA1) .......................................................
7.5.9 Fail Status Data Registers (FSRDL0 and FSRDL1) ........................................................
7.5.10 ROM Mask Register (ROM) ...................................................................................
7.5.11 ROM Algorithm Mask Register (ALGO) .....................................................................
7.5.12 RAM Info Mask Lower Register (RINFOL) ..................................................................
7.5.13 RAM Info Mask Upper Register (RINFOU) ..................................................................
PBIST Configuration Example ..........................................................................................
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7.6.1
7.6.2
8
CPU Self-Test Controller (STC) Module ............................................................................... 346
8.1
8.2
8.3
8.4
8.5
9
9.4
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Main Features .............................................................................................................
Block Diagram .............................................................................................................
Module Operation .........................................................................................................
9.3.1 1oo1D Lock Step Mode .........................................................................................
9.3.2 Self-Test Mode ...................................................................................................
9.3.3 Error Forcing Mode ..............................................................................................
9.3.4 Self-Test Error Forcing Mode ..................................................................................
9.3.5 Operation During CPU Debug Mode ..........................................................................
CCM-R4F Control Registers ............................................................................................
9.4.1 CCM-R4F Status Register (CCMSR) .........................................................................
9.4.2 CCM-R4F Key Register (CCMKEYR) .........................................................................
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366
366
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368
369
........................................................................................................... 370
Introduction ................................................................................................................ 371
10.1.1 Features.......................................................................................................... 371
Quick Start ................................................................................................................. 372
Oscillator ................................................................................................................... 373
10.3.1 Oscillator Implementation ...................................................................................... 374
10.3.2 Oscillator Enable ................................................................................................ 374
10.3.3 Oscillator Disable ............................................................................................... 374
Low-Power Oscillator and Clock Detect (LPOCLKDET) ............................................................. 375
10.4.1 Clock Detect ..................................................................................................... 375
10.4.2 Behavior on Oscillator Failure ................................................................................. 375
10.4.3 Recovery from Oscillator Failure ............................................................................. 376
10.4.4 LPOCLKDET Enable ........................................................................................... 376
10.4.5 LPOCLKDET Disable .......................................................................................... 377
10.4.6 Trimming the HF LPO Oscillator .............................................................................. 377
PLL ......................................................................................................................... 378
Oscillator and PLL
10.1
10.2
10.3
10.4
10.5
6
General Description ......................................................................................................
8.1.1 CPU Self-Test Controller Features ............................................................................
8.1.2 STC Block Diagram .............................................................................................
Application Self-Test Flow ...............................................................................................
8.2.1 STC Module Configuration .....................................................................................
8.2.2 Context Saving ...................................................................................................
8.2.3 Entering CPU Idle Mode ........................................................................................
8.2.4 Self-Test Completion and Error Generation ..................................................................
STC Test Coverage and Duration ......................................................................................
STC Control Registers ...................................................................................................
8.4.1 STC Global Control Register 0 (STCGCR0) .................................................................
8.4.2 STC Global Control Register 1 (STCGCR1) .................................................................
8.4.3 Self-Test Run Timeout Counter Preload Register (STCTPR) .............................................
8.4.4 STC Current ROM Address Register (STC_CADDR) ......................................................
8.4.5 STC Current Interval Count Register (STCCICR) ...........................................................
8.4.6 Self-Test Global Status Register (STCGSTAT)..............................................................
8.4.7 Self-Test Fail Status Register (STCFSTAT) .................................................................
8.4.8 CPU1 Current MISR Register (CPU1_CURMISR[3:0]) .....................................................
8.4.9 CPU2_CURMISR[3:0] (CPU2 Current MISR Register) .....................................................
8.4.10 STCSCSCR (Signature Compare Self-Check Register) ..................................................
STC Configuration Example ............................................................................................
8.5.1 Example 1: Self-Test Run for 24 Interval ....................................................................
CPU Compare Module for Cortex-R4F (CCM-R4F) ................................................................. 362
9.1
9.2
9.3
10
Example 1 : Configuration of PBIST Controller to Run Self-Test on RAM Group 3 .................... 344
Example 2 : Configuration of PBIST Controller to Run Self-Test on ALL RAM Groups ................ 345
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10.6
10.7
10.8
11
Dual-Clock Comparator (DCC) Module
11.1
11.2
11.3
11.4
12
10.5.1 Modulation .......................................................................................................
10.5.2 PLL Output Control .............................................................................................
10.5.3 Behavior on PLL Fail ...........................................................................................
10.5.4 Recovery from a PLL Failure ..................................................................................
10.5.5 PLL Modulation Depth Measurement ........................................................................
10.5.6 PLL Frequency Measurement Circuit ........................................................................
10.5.7 PLL2 ..............................................................................................................
PLL Control Registers ....................................................................................................
10.6.1 PLL Modulation Depth Measurement Control Register (SSWPLL1) .....................................
10.6.2 SSW PLL BIST Control Register 2 (SSWPLL2) ............................................................
10.6.3 SSW PLL BIST Control Register 3 (SSWPLL3) ............................................................
Phase-Locked Loop Theory of Operation .............................................................................
10.7.1 Phase-Frequency Detector ....................................................................................
10.7.2 Charge Pump and Loop Filter.................................................................................
10.7.3 Voltage-Controlled Oscillator ..................................................................................
10.7.4 Frequency Modulation .........................................................................................
Programming Example ...................................................................................................
12.1
12.2
12.3
12.4
................................................................................ 396
Introduction ................................................................................................................
11.1.1 Main Features ...................................................................................................
11.1.2 Block Diagram ...................................................................................................
Module Operation .........................................................................................................
11.2.1 Continuous Monitoring Mode..................................................................................
11.2.2 Single-Shot Measurement Mode .............................................................................
Clock Source Selection for Counter0 and Counter1 .................................................................
DCC Control Registers ...................................................................................................
11.4.1 DCC Global Control Register (DCCGCTRL) ...............................................................
11.4.2 DCC Revision Id Register (DCCREV) ......................................................................
11.4.3 DCC Counter0 Seed Register (DCCCNT0SEED) .........................................................
11.4.4 DCC Valid0 Seed Register (DCCVALID0SEED) ..........................................................
11.4.5 DCC Counter1 Seed Register (DCCCNT1SEED) .........................................................
11.4.6 DCC Status Register (DCCSTAT) ...........................................................................
11.4.7 DCC Counter0 Value Register (DCCCNT0) ................................................................
11.4.8 DCC Valid0 Value Register (DCCVALID0) .................................................................
11.4.9 DCC Counter1 Value Register (DCCCNT1) ................................................................
11.4.10 DCC Counter1 Clock Source Selection Register (DCCCNT1CLKSRC) ..............................
11.4.11 DCC Counter0 Clock Source Selection Register (DCCCNT0CLKSRC) ..............................
Error Signaling Module (ESM)
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........................................................................................... 412
Overview ..................................................................................................................
12.1.1 Features..........................................................................................................
12.1.2 Block Diagram ..................................................................................................
Module Operation ........................................................................................................
12.2.1 Reset Behavior .................................................................................................
12.2.2 ERROR Pin Timing ............................................................................................
12.2.3 Forcing an Error Condition ....................................................................................
Recommended Programming Procedure .............................................................................
Control Registers .........................................................................................................
12.4.1 ESM Enable ERROR Pin Action/Response Register 1 (ESMEEPAPR1) ...............................
12.4.2 ESM Disable ERROR Pin Action/Response Register 1 (ESMDEPAPR1) ..............................
12.4.3 ESM Interrupt Enable Set Register 1 (ESMIESR1) ........................................................
12.4.4 ESM Interrupt Enable Clear Register 1 (ESMIECR1) .....................................................
12.4.5 ESM Interrupt Level Set Register 1 (ESMILSR1) ..........................................................
12.4.6 ESM Interrupt Level Clear Register 1 (ESMILCR1) ........................................................
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12.4.7
12.4.8
12.4.9
12.4.10
12.4.11
12.4.12
12.4.13
12.4.14
12.4.15
12.4.16
12.4.17
12.4.18
12.4.19
12.4.20
12.4.21
12.4.22
12.4.23
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Real-Time Interrupt (RTI) Module ........................................................................................ 434
13.1
13.2
13.3
8
ESM Status Register 1 (ESMSR1) ...........................................................................
ESM Status Register 2 (ESMSR2) ...........................................................................
ESM Status Register 3 (ESMSR3) ...........................................................................
ESM ERROR Pin Status Register (ESMEPSR) ..........................................................
ESM Interrupt Offset High Register (ESMIOFFHR) ......................................................
ESM Interrupt Offset Low Register (ESMIOFFLR) .......................................................
ESM Low-Time Counter Register (ESMLTCR) ...........................................................
ESM Low-Time Counter Preload Register (ESMLTCPR)................................................
ESM Error Key Register (ESMEKR) ........................................................................
ESM Status Shadow Register 2 (ESMSSR2) .............................................................
ESM Influence ERROR Pin Set Register 4 (ESMIEPSR4) .............................................
ESM Influence ERROR Pin Clear Register 4 (ESMIEPCR4) ..........................................
ESM Interrupt Enable Set Register 4 (ESMIESR4) ......................................................
ESM Interrupt Enable Clear Register 4 (ESMIECR4) ...................................................
ESM Interrupt Level Set Register 4 (ESMILSR4) ........................................................
ESM Interrupt Level Clear Register 4 (ESMILCR4) .....................................................
ESM Status Register 4 (ESMSR4) .........................................................................
Overview ...................................................................................................................
13.1.1 Features..........................................................................................................
13.1.2 Industry Standard Compliance Statement ...................................................................
Module Operation .........................................................................................................
13.2.1 Counter Operation ..............................................................................................
13.2.2 Interrupt/DMA Requests .......................................................................................
13.2.3 RTI Clocking .....................................................................................................
13.2.4 Synchronizing Timer Events to Network Time (NTU) ......................................................
13.2.5 Digital Watchdog (DWD) .......................................................................................
13.2.6 Low Power Modes ..............................................................................................
13.2.7 Halting Debug Mode Behaviour...............................................................................
RTI Control Registers ....................................................................................................
13.3.1 RTI Global Control Register (RTIGCTRL) ...................................................................
13.3.2 RTI Timebase Control Register (RTITBCTRL) .............................................................
13.3.3 RTI Capture Control Register (RTICAPCTRL)..............................................................
13.3.4 RTI Compare Control Register (RTICOMPCTRL) .........................................................
13.3.5 RTI Free Running Counter 0 Register (RTIFRC0) .........................................................
13.3.6 RTI Up Counter 0 Register (RTIUC0) ........................................................................
13.3.7 RTI Compare Up Counter 0 Register (RTICPUC0) ........................................................
13.3.8 RTI Capture Free Running Counter 0 Register (RTICAFRC0) ...........................................
13.3.9 RTI Capture Up Counter 0 Register (RTICAUC0)..........................................................
13.3.10 RTI Free Running Counter 1 Register (RTIFRC1)........................................................
13.3.11 RTI Up Counter 1 Register (RTIUC1) ......................................................................
13.3.12 RTI Compare Up Counter 1 Register (RTICPUC1).......................................................
13.3.13 RTI Capture Free Running Counter 1 Register (RTICAFRC1) .........................................
13.3.14 RTI Capture Up Counter 1 Register (RTICAUC1) ........................................................
13.3.15 RTI Compare 0 Register (RTICOMP0) .....................................................................
13.3.16 RTI Update Compare 0 Register (RTIUDCP0) ............................................................
13.3.17 RTI Compare 1 Register (RTICOMP1) .....................................................................
13.3.18 RTI Update Compare 1 Register (RTIUDCP1) ............................................................
13.3.19 RTI Compare 2 Register (RTICOMP2) .....................................................................
13.3.20 RTI Update Compare 2 Register (RTIUDCP2) ............................................................
13.3.21 RTI Compare 3 Register (RTICOMP3) .....................................................................
13.3.22 RTI Update Compare 3 Register (RTIUDCP3) ............................................................
13.3.23 RTI Timebase Low Compare Register (RTITBLCOMP) .................................................
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13.3.25
13.3.26
13.3.27
13.3.28
13.3.29
13.3.30
13.3.31
13.3.32
13.3.33
13.3.34
13.3.35
13.3.36
13.3.37
13.3.38
13.3.39
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RTI Timebase High Compare Register (RTITBHCOMP) ................................................
RTI Set Interrupt Enable Register (RTISETINTENA) ....................................................
RTI Clear Interrupt Enable Register (RTICLEARINTENA) ..............................................
RTI Interrupt Flag Register (RTIINTFLAG) ................................................................
Digital Watchdog Control Register (RTIDWDCTRL) .....................................................
Digital Watchdog Preload Register (RTIDWDPRLD) .....................................................
Watchdog Status Register (RTIWDSTATUS) .............................................................
RTI Watchdog Key Register (RTIWDKEY) ................................................................
RTI Digital Watchdog Down Counter (RTIDWDCNTR) ..................................................
Digital Windowed Watchdog Reaction Control (RTIWWDRXNCTRL) .................................
Digital Windowed Watchdog Window Size Control (RTIWWDSIZECTRL) ............................
RTI Compare Interrupt Clear Enable Register (RTIINTCLRENABLE) .................................
RTI Compare 0 Clear Register (RTICMP0CLR) ..........................................................
RTI Compare 1 Clear Register (RTICMP1CLR) ..........................................................
RTI Compare 2 Clear Register (RTICMP2CLR) ..........................................................
RTI Compare 3 Clear Register (RTICMP3CLR) ..........................................................
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Cyclic Redundancy Check (CRC) Controller Module ............................................................. 476
14.1
14.2
14.3
14.4
Overview ..................................................................................................................
14.1.1 Features .........................................................................................................
14.1.2 Block Diagram ...................................................................................................
Module Operation ........................................................................................................
14.2.1 General Operation .............................................................................................
14.2.2 CRC Modes of Operation ......................................................................................
14.2.3 PSA Signature Register........................................................................................
14.2.4 PSA Sector Signature Register ...............................................................................
14.2.5 CRC Value Register ............................................................................................
14.2.6 Raw Data Register .............................................................................................
14.2.7 Example DMA Controller Setup...............................................................................
14.2.8 Pattern Count Register .........................................................................................
14.2.9 Sector Count Register/Current Sector Register ............................................................
14.2.10 Interrupt .........................................................................................................
14.2.11 CPU Data Trace ...............................................................................................
14.2.12 Power Down Mode ............................................................................................
14.2.13 Emulation ......................................................................................................
14.2.14 Peripheral Bus Interface ......................................................................................
Example ...................................................................................................................
14.3.1 Example: Auto Mode Using Time Based Event Triggering ...............................................
14.3.2 Example: Auto Mode Without Using Time Based Triggering .............................................
14.3.3 Example: Semi-CPU Mode ....................................................................................
14.3.4 Example: Full-CPU Mode ......................................................................................
CRC Control Registers ...................................................................................................
14.4.1 CRC Global Control Register 0 (CRC_CTRL0).............................................................
14.4.2 CRC Global Control Register (CRC_CTRL1) ...............................................................
14.4.3 CRC Global Control Register 2 (CRC_CTRL2).............................................................
14.4.4 CRC Interrupt Enable Set Register (CRC_INTS) ..........................................................
14.4.5 CRC Interrupt Enable Reset Register (CRC_INTR) .......................................................
14.4.6 CRC Interrupt Status Register (CRC_STATUS)............................................................
14.4.7 CRC Interrupt Offset (CRC_INT_OFFSET_REG) ..........................................................
14.4.8 CRC Busy Register (CRC_BUSY) ...........................................................................
14.4.9 CRC Pattern Counter Preload Register 1 (CRC_PCOUNT_REG1) .....................................
14.4.10 CRC Sector Counter Preload Register 1 (CRC_SCOUNT_REG1) ....................................
14.4.11 CRC Current Sector Register 1 (CRC_CURSEC_REG1) ...............................................
14.4.12 CRC Channel 1 Watchdog Timeout Preload Register A (CRC_WDTOPLD1) ........................
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14.4.14
14.4.15
14.4.16
14.4.17
14.4.18
14.4.19
14.4.20
14.4.21
14.4.22
14.4.23
14.4.24
14.4.25
14.4.26
14.4.27
14.4.28
14.4.29
14.4.30
14.4.31
14.4.32
14.4.33
14.4.34
14.4.35
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Vectored Interrupt Manager (VIM) Module ............................................................................ 515
15.1
15.2
15.3
15.4
15.5
15.6
15.7
15.8
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CRC Channel 1 Block Complete Timeout Preload Register B (CRC_BCTOPLD1) ..................
Channel 1 PSA Signature Low Register (PSA_SIGREGL1) ............................................
Channel 1 PSA Signature High Register (PSA_SIGREGH1) ...........................................
Channel 1 CRC Value Low Register (CRC_REGL1).....................................................
Channel 1 CRC Value High Register (CRC_REGH1)....................................................
Channel 1 PSA Sector Signature Low Register (PSA_SECSIGREGL1) ..............................
Channel 1 PSA Sector Signature High Register (PSA_SECSIGREGH1) .............................
Channel 1 Raw Data Low Register (RAW_DATAREGL1)...............................................
Channel 1 Raw Data High Register (RAW_DATAREGH1)..............................................
CRC Pattern Counter Preload Register 2 (CRC_PCOUNT_REG2) ...................................
CRC Sector Counter Preload Register 2 (CRC_SCOUNT_REG2) ....................................
CRC Current Sector Register 2 (CRC_CURSEC_REG2) ...............................................
CRC Channel 2 Watchdog Timeout Preload Register A (CRC_WDTOPLD2) ........................
CRC Channel 2 Block Complete Timeout Preload Register B (CRC_BCTOPLD2) ..................
Channel 2 PSA Signature Low Register (PSA_SIGREGL2) ............................................
Channel 2 PSA Signature High Register (PSA_SIGREGH2) ...........................................
Channel 2 CRC Value Low Register (CRC_REGL2).....................................................
Channel 2 CRC Value High Register (CRC_REGH2)....................................................
Channel 2 PSA Sector Signature Low Register (PSA_SECSIGREGL2) ..............................
Channel 2 PSA Sector Signature High Register (PSA_SECSIGREGH2) .............................
Channel 2 Raw Data Low Register (RAW_DATAREGL2)...............................................
Channel 2 Raw Data High Register (RAW_DATAREGH2)..............................................
Data Bus Selection Register (CRC_TRACE_BUS_SEL) ................................................
Overview ...................................................................................................................
Device Level Interrupt Management ...................................................................................
15.2.1 Interrupt Generation at the Peripheral .......................................................................
15.2.2 Interrupt Handling at the CPU.................................................................................
15.2.3 Software Interrupt Handling Options .........................................................................
Interrupt Handling Inside VIM ...........................................................................................
15.3.1 VIM Interrupt Channel Mapping...............................................................................
15.3.2 VIM Input Channel Management .............................................................................
Interrupt Vector Table (VIM RAM) ......................................................................................
15.4.1 Interrupt Vector Table Operation .............................................................................
15.4.2 Enabling and Controlling the VIM Parity .....................................................................
15.4.3 Interrupt Vector Table Initialization ...........................................................................
15.4.4 Interrupt Vector Table Parity Testing .........................................................................
VIM Wakeup Interrupt ....................................................................................................
Capture Event Sources ..................................................................................................
Examples ..................................................................................................................
15.7.1 Examples - Configure CPU To Receive Interrupts .........................................................
15.7.2 Examples - Register Vector Interrupt and Index Interrupt Handling .....................................
VIM Control Registers ....................................................................................................
15.8.1 Interrupt Vector Table Parity Flag Register (PARFLG) ...................................................
15.8.2 Interrupt Vector Table Parity Control Register (PARCTL) .................................................
15.8.3 Address Parity Error Register (ADDERR) ...................................................................
15.8.4 Fall-Back Address Parity Error Register (FBPARERR)....................................................
15.8.5 VIM Offset Vector Registers...................................................................................
15.8.6 IRQ Index Offset Vector Register (IRQINDEX) .............................................................
15.8.7 FIQ Index Offset Vector Registers (FIQINDEX) ............................................................
15.8.8 FIQ/IRQ Program Control Registers (FIRQPR[0:2]) .......................................................
15.8.9 Pending Interrupt Read Location Registers (INTREQ[0:2]) ...............................................
15.8.10 Interrupt Enable Set Registers (REQENASET[0:2]) ......................................................
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15.8.12
15.8.13
15.8.14
15.8.15
15.8.16
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Direct Memory Access Controller (DMA) Module .................................................................. 545
16.1
16.2
16.3
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Interrupt Enable Clear Registers (REQENACLR[0:2]) ...................................................
Wake-Up Enable Set Registers (WAKEENASET[0:2])...................................................
Wake-Up Enable Clear Registers (WAKEENACLR[0:2]) ................................................
IRQ Interrupt Vector Register (IRQVECREG) .............................................................
FIQ Interrupt Vector Register (FIQVECREG) .............................................................
Capture Event Register (CAPEVT) .........................................................................
VIM Interrupt Control Registers (CHANCTRL[0:23]) .....................................................
Overview ...................................................................................................................
16.1.1 Main Features ...................................................................................................
Module Operation .........................................................................................................
16.2.1 Memory Space ..................................................................................................
16.2.2 DMA Data Access ..............................................................................................
16.2.3 Addressing Modes ..............................................................................................
16.2.4 DMA Channel Control Packets ...............................................................................
16.2.5 Priority Queue ...................................................................................................
16.2.6 Data Packing and Unpacking .................................................................................
16.2.7 DMA Request ...................................................................................................
16.2.8 Auto-Initiation ....................................................................................................
16.2.9 Interrupts .........................................................................................................
16.2.10 Debugging ......................................................................................................
16.2.11 Power Management ..........................................................................................
16.2.12 FIFO Buffer.....................................................................................................
16.2.13 Channel Chaining .............................................................................................
16.2.14 Memory Protection ............................................................................................
16.2.15 Parity Checking ................................................................................................
16.2.16 Parity Testing ..................................................................................................
16.2.17 Initializing RAM with Parity ...................................................................................
Control Registers and Control Packets ................................................................................
16.3.1 Global Configuration Registers ...............................................................................
16.3.2 Channel Configuration .........................................................................................
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External Memory Interface (EMIF) ....................................................................................... 619
17.1
17.2
Introduction ................................................................................................................
17.1.1 Purpose of the Peripheral .....................................................................................
17.1.2 Features..........................................................................................................
17.1.3 Functional Block Diagram .....................................................................................
EMIF Module Architecture ...............................................................................................
17.2.1 EMIF Clock Control .............................................................................................
17.2.2 EMIF Requests..................................................................................................
17.2.3 EMIF Signal Descriptions ......................................................................................
17.2.4 EMIF Signal Multiplexing Control .............................................................................
17.2.5 SDRAM Controller and Interface .............................................................................
17.2.6 Asynchronous Controller and Interface ......................................................................
17.2.7 Data Bus Parking ...............................................................................................
17.2.8 Reset and Initialization Considerations ......................................................................
17.2.9 Interrupt Support ................................................................................................
17.2.10 DMA Event Support ...........................................................................................
17.2.11 EMIF Signal Multiplexing .....................................................................................
17.2.12 Memory Map ...................................................................................................
17.2.13 Priority and Arbitration ........................................................................................
17.2.14 System Considerations .......................................................................................
17.2.15 Power Management ..........................................................................................
17.2.16 Emulation Considerations ....................................................................................
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17.3
17.4
18
EMIF Registers ............................................................................................................
17.3.1 Module ID Register (MIDR) ...................................................................................
17.3.2 Asynchronous Wait Cycle Configuration Register (AWCC) ...............................................
17.3.3 SDRAM Configuration Register (SDCR) ....................................................................
17.3.4 SDRAM Refresh Control Register (SDRCR) ................................................................
17.3.5 Asynchronous n Configuration Registers (CE2CFG-CE5CFG) ..........................................
17.3.6 SDRAM Timing Register (SDTIMR) ..........................................................................
17.3.7 SDRAM Self Refresh Exit Timing Register (SDSRETR) ..................................................
17.3.8 EMIF Interrupt Raw Register (INTRAW).....................................................................
17.3.9 EMIF Interrupt Masked Register (INTMSK) .................................................................
17.3.10 EMIF Interrupt Mask Set Register (INTMSKSET) ........................................................
17.3.11 EMIF Interrupt Mask Clear Register (INTMSKCLR) ......................................................
17.3.12 Page Mode Control Register (PMCR) ......................................................................
Example Configuration ...................................................................................................
17.4.1 Hardware Interface .............................................................................................
17.4.2 Software Configuration .........................................................................................
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Parameter Overlay Module (POM) ....................................................................................... 675
18.1
18.2
18.3
Introduction ................................................................................................................
18.1.1 Main Features ...................................................................................................
18.1.2 Parameter Overlay Module (POM) Considerations ........................................................
18.1.3 Block Diagram ...................................................................................................
Module Operation .........................................................................................................
18.2.1 Decode Regions ................................................................................................
18.2.2 Bus Errors on Accesses via POM ............................................................................
POM Control Registers ..................................................................................................
18.3.1 POM Global Control Register (POMGLBCTRL) ............................................................
18.3.2 POM Revision ID (POMREV) .................................................................................
18.3.3 POM Clock Gate Control Register (POMCLKCTRL) ......................................................
18.3.4 POM Status Register (POMFLG) .............................................................................
18.3.5 POM Program Region Start Address Register x (POMPROGSTARTx) ................................
18.3.6 POM Overlay Region Start Address Register x (POMOVLSTARTx) ....................................
18.3.7 POM Region Size Register x (POMREGSIZEx) ............................................................
18.3.8 POM Integration Control Register (POMITCTRL) ..........................................................
18.3.9 POM Claim Set Register (POMCLAIMSET) ................................................................
18.3.10 POM Claim Clear Register (POMCLAIMCLR) ............................................................
18.3.11 POM Lock Access Register (POMLOCKACCESS) ......................................................
18.3.12 POM Lock Status Register (POMLOCKSTATUS) ........................................................
18.3.13 POM Authentication Status Register (POMAUTHSTATUS) .............................................
18.3.14 POM Device ID Register (POMDEVID) ....................................................................
18.3.15 POM Device Type Register (POMDEVTYPE) ............................................................
18.3.16 POM Peripheral ID 4 Register (POMPERIPHERALID4) .................................................
18.3.17 POM Peripheral ID 5 Register (POMPERIPHERALID5) .................................................
18.3.18 POM Peripheral ID 6 Register (POMPERIPHERALID6) .................................................
18.3.19 POM Peripheral ID 7 Register (POMPERIPHERALID7) .................................................
18.3.20 POM Peripheral ID 0 Register (POMPERIPHERALID0) .................................................
18.3.21 POM Peripheral ID 1 Register (POMPERIPHERALID1) .................................................
18.3.22 POM Peripheral ID 2 Register (POMPERIPHERALID2) .................................................
18.3.23 POM Peripheral ID 3 Register (POMPERIPHERALID3) .................................................
18.3.24 POM Component ID 0 Register (POMCOMPONENTID0) ...............................................
18.3.25 POM Component ID 1 Register (POMCOMPONENTID1) ...............................................
18.3.26 POM Component ID 2 Register (POMCOMPONENTID2) ...............................................
18.3.27 POM Component ID 3 Register (POMCOMPONENTID3) ...............................................
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Analog To Digital Converter (ADC) Module .......................................................................... 695
12
Contents
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Overview ...................................................................................................................
Introduction ................................................................................................................
19.2.1 Input Multiplexor ................................................................................................
19.2.2 Self-Test and Calibration Cell .................................................................................
19.2.3 Analog-to-Digital Converter Core .............................................................................
19.2.4 Sequencer .......................................................................................................
19.2.5 Conversion Groups .............................................................................................
19.3 Basic Features and Usage of the ADC ................................................................................
19.3.1 How to Select Between 12-bit and 10-bit Resolution ......................................................
19.3.2 How to Set Up the ADCLK Speed ............................................................................
19.3.3 How to Set Up the Input Channel Acquisition Time ........................................................
19.3.4 How to Select an Input Channel for Conversion............................................................
19.3.5 How to Select Between Single Conversion Sequence or Continuous Conversions ...................
19.3.6 How to Start a Conversion ....................................................................................
19.3.7 How to Know When the Group Conversion is Completed ................................................
19.3.8 How Results are Stored in the Results’ Memory ...........................................................
19.3.9 How to Read the Results from the Results’ Memory ......................................................
19.3.10 How to Stop a Conversion ...................................................................................
19.3.11 Example Sequence for Basic Configuration of ADC Module ............................................
19.4 Advanced Conversion Group Configuration Options.................................................................
19.4.1 Group Trigger Options .........................................................................................
19.4.2 Single or Continuous Conversion Modes ....................................................................
19.4.3 Conversion Group Freeze Capability ........................................................................
19.4.4 Conversion Group Memory Overrun Option ................................................................
19.4.5 Response on Writing Non-Zero Value to Conversion Group’s Channel Select Register .............
19.4.6 Conversion Result Size on Reading: 8-bit, 10-bit or 12-bit ...............................................
19.4.7 Option to Read Group Channel ID Along with Conversion Result .......................................
19.5 ADC Module Basic Interrupts ...........................................................................................
19.5.1 Group Conversion End Interrupt ..............................................................................
19.5.2 Group Memory Threshold Interrupt ..........................................................................
19.5.3 Group Memory Overrun Interrupt .............................................................................
19.6 ADC Module DMA Requests ............................................................................................
19.6.1 DMA Request for Each Conversion Result Written to the Results’ Memory ............................
19.6.2 DMA Request for a Fixed Number of Conversion Results ................................................
19.7 ADC Magnitude Threshold Interrupts ..................................................................................
19.7.1 Magnitude Threshold Interrupt Configuration ...............................................................
19.7.2 Magnitude Threshold Interrupt Comparison Mask Configuration ........................................
19.7.3 Magnitude Threshold Interrupt Enable / Disable Control ..................................................
19.7.4 Magnitude Threshold Interrupt Flags.........................................................................
19.7.5 Magnitude Threshold Interrupt Offset Register .............................................................
19.8 ADC Special Modes ......................................................................................................
19.8.1 ADC Error Calibration Mode ..................................................................................
19.8.2 ADC Self-Test Mode ...........................................................................................
19.8.3 ADC Power-Down Mode .......................................................................................
19.8.4 ADC Sample Capacitor Discharge Mode ....................................................................
19.9 ADC Results’ RAM Special Features ..................................................................................
19.9.1 ADC Results’ RAM Auto-Initialization ........................................................................
19.9.2 ADC Results’ RAM Test Mode ................................................................................
19.9.3 ADC Results’ RAM Parity......................................................................................
19.10 ADEVT Pin General Purpose I/O Functionality .......................................................................
19.10.1 GPIO Functionality ............................................................................................
19.10.2 Summary .......................................................................................................
19.11 ADC Control Registers...................................................................................................
19.1
19.2
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19.11.1
19.11.2
19.11.3
19.11.4
19.11.5
19.11.6
19.11.7
19.11.8
19.11.9
19.11.10
19.11.11
19.11.12
19.11.13
19.11.14
19.11.15
19.11.16
19.11.17
19.11.18
19.11.19
19.11.20
19.11.21
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19.11.25
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19.11.27
19.11.28
19.11.29
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19.11.31
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19.11.33
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19.11.35
19.11.36
19.11.37
19.11.38
19.11.39
19.11.40
19.11.41
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19.11.43
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19.11.46
19.11.47
19.11.48
19.11.49
19.11.50
19.11.51
19.11.52
19.11.53
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ADC Reset Control Register (ADRSTCR) .................................................................
ADC Operating Mode Control Register (ADOPMODECR) ..............................................
ADC Clock Control Register (ADCLOCKCR)..............................................................
ADC Calibration Mode Control Register (ADCALCR) ....................................................
ADC Event Group Operating Mode Control Register (ADEVMODECR) ..............................
ADC Group1 Operating Mode Control Register (ADG1MODECR) .....................................
ADC Group2 Operating Mode Control Register (ADG2MODECR) .....................................
ADC Event Group Trigger Source Select Register (ADEVSRC) .......................................
ADC Group1 Trigger Source Select Register (ADG1SRC) ..............................................
ADC Group2 Trigger Source Select Register (ADG2SRC) ............................................
ADC Event Interrupt Enable Control Register (ADEVINTENA)........................................
ADC Group1 Interrupt Enable Control Register (ADG1INTENA) .....................................
ADC Group2 Interrupt Enable Control Register (ADG2INTENA) .....................................
ADC Event Group Interrupt Flag Register (ADEVINTFLG) ............................................
ADC Group1 Interrupt Flag Register (ADG1INTFLG) ..................................................
ADC Group2 Interrupt Flag Register (ADG2INTFLG) ..................................................
ADC Event Group Threshold Interrupt Control Register (ADEVTHRINTCR) ........................
ADC Group1 Threshold Interrupt Control Register (ADG1THRINTCR) ..............................
ADC Group2 Threshold Interrupt Control Register (ADG2THRINTCR) ..............................
ADC Event Group DMA Control Register (ADEVDMACR) ............................................
ADC Group1 DMA Control Register (ADG1DMACR) ...................................................
ADC Group2 DMA Control Register (ADG2DMACR) ...................................................
ADC Results Memory Configuration Register (ADBNDCR) ...........................................
ADC Results Memory Size Configuration Register (ADBNDEND) ....................................
ADC Event Group Sampling Time Configuration Register (ADEVSAMP) ...........................
ADC Group1 Sampling Time Configuration Register (ADG1SAMP)..................................
ADC Group2 Sampling Time Configuration Register (ADG2SAMP)..................................
ADC Event Group Status Register (ADEVSR) ..........................................................
ADC Group1 Status Register (ADG1SR) .................................................................
ADC Group2 Status Register (ADG2SR) .................................................................
ADC Event Group Channel Select Register (ADEVSEL) ..............................................
ADC Group1 Channel Select Register (ADG1SEL) .....................................................
ADC Group2 Channel Select Register (ADG2SEL) .....................................................
ADC Calibration and Error Offset Correction Register (ADCALR) ....................................
ADC State Machine Status Register (ADSMSTATE) ...................................................
ADC Channel Last Conversion Value Register (ADLASTCONV) .....................................
ADC Event Group Results' FIFO Register (ADEVBUFFER) ...........................................
ADC Group1 Results FIFO Register (ADG1BUFFER) .................................................
ADC Group2 Results FIFO Register (ADG2BUFFER) .................................................
ADC Event Group Results Emulation FIFO Register (ADEVEMUBUFFER) ........................
ADC Group1 Results Emulation FIFO Register (ADG1EMUBUFFER)...............................
ADC Group2 Results Emulation FIFO Register (ADG2EMUBUFFER)...............................
ADC ADEVT Pin Direction Control Register (ADEVTDIR) .............................................
ADC ADEVT Pin Output Value Control Register (ADEVTOUT) .......................................
ADC ADEVT Pin Input Value Register (ADEVTIN) .....................................................
ADC ADEVT Pin Set Register (ADEVTSET) ............................................................
ADC ADEVT Pin Clear Register (ADEVTCLR) ..........................................................
ADC ADEVT Pin Open Drain Enable Register (ADEVTPDR) .........................................
ADC ADEVT Pin Pull Control Disable Register (ADEVTPDIS) ........................................
ADC ADEVT Pin Pull Control Select Register (ADEVTPSEL).........................................
ADC Event Group Sample Cap Discharge Control Register (ADEVSAMPDISEN) .................
ADC Group1 Sample Cap Discharge Control Register (ADG1SAMPDISEN) .......................
ADC Group2 Sample Cap Discharge Control Register (ADG2SAMPDISEN) .......................
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ADC
ADC
ADC
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ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
Magnitude Compare Interrupt x Control Registers (ADMAGINTxCR) .........................
Magnitude Compare Interrupt x Mask Register (ADMAGxMASK)..............................
Magnitude Compare Interrupt Enable Set Register (ADMAGINTENASET) ...................
Magnitude Compare Interrupt Enable Clear Register (ADMAGINTENACLR) ................
Magnitude Compare Interrupt Flag Register (ADMAGINTFLG) ................................
Magnitude Compare Interrupt Offset Register (ADMAGINTOFF) ..............................
Event Group FIFO Reset Control Register (ADEVFIFORESETCR) ...........................
Group1 FIFO Reset Control Register (ADG1FIFORESETCR)..................................
Group2 FIFO Reset Control Register (ADG2FIFORESETCR)..................................
Event Group RAM Write Address Register (ADEVRAMWRADDR) ............................
Group1 RAM Write Address Register (ADG1RAMWRADDR) ..................................
Group2 RAM Write Address Register (ADG2RAMWRADDR) ..................................
Parity Control Register (ADPARCR) ................................................................
Parity Error Address Register (ADPARADDR) ....................................................
Power-Up Delay Control Register (ADPWRUPDLYCTRL) ......................................
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High-End Timer (N2HET) Module ........................................................................................ 791
20.1
20.2
20.3
20.4
Overview ...................................................................................................................
20.1.1 Features..........................................................................................................
20.1.2 Major Advantages ..............................................................................................
20.1.3 Block Diagram ...................................................................................................
20.1.4 Timer Module Structure and Execution ......................................................................
20.1.5 Performance .....................................................................................................
20.1.6 N2HET Compared to NHET ...................................................................................
20.1.7 NHET and N2HET Compared to HET .......................................................................
20.1.8 Instructions Features ...........................................................................................
20.1.9 Program Usage .................................................................................................
N2HET Functional Description ..........................................................................................
20.2.1 Specialized Timer Micromachine .............................................................................
20.2.2 N2HET RAM Organization ....................................................................................
20.2.3 Time Base .......................................................................................................
20.2.4 Host Interface ...................................................................................................
20.2.5 I/O Control .......................................................................................................
20.2.6 Suppression Filters .............................................................................................
20.2.7 Interrupts and Exceptions .....................................................................................
20.2.8 Hardware Priority Scheme .....................................................................................
20.2.9 N2HET Requests to DMA and HTU ..........................................................................
Angle Functions ...........................................................................................................
20.3.1 Software Angle Generator .....................................................................................
20.3.2 Hardware Angle Generator (HWAG) .........................................................................
N2HET Control Registers ................................................................................................
20.4.1 Global Configuration Register (HETGCR) ...................................................................
20.4.2 Prescale Factor Register (HETPFR) .........................................................................
20.4.3 N2HET Current Address Register (HETADDR) ............................................................
20.4.4 Offset Index Priority Level 1 Register (HETOFF1) .........................................................
20.4.5 Offset Index Priority Level 2 Register (HETOFF2) .........................................................
20.4.6 Interrupt Enable Set Register (HETINTENAS)..............................................................
20.4.7 Interrupt Enable Clear Register (HETINTENAC) ...........................................................
20.4.8 Exception Control Register 1 (HETEXC1) ...................................................................
20.4.9 Exception Control Register 2 (HETEXC2) ...................................................................
20.4.10 Interrupt Priority Register (HETPRY) .......................................................................
20.4.11 Interrupt Flag Register (HETFLG) ..........................................................................
20.4.12 AND Share Control Register (HETAND) ..................................................................
20.4.13 HR Share Control Register (HETHRSH) ...................................................................
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20.6
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High-End Timer Transfer Unit (HTU) Module ........................................................................ 969
21.1
21.2
16
20.4.14 XOR Share Control Register (HETXOR) ...................................................................
20.4.15 Request Enable Set Register (HETREQENS) ............................................................
20.4.16 Request Enable Clear Register (HETREQENC) ..........................................................
20.4.17 Request Destination Select Register (HETREQDS)......................................................
20.4.18 NHET Direction Register (HETDIR) ........................................................................
20.4.19 N2HET Data Input Register (HETDIN) .....................................................................
20.4.20 N2HET Data Output Register (HETDOUT) ................................................................
20.4.21 NHET Data Set Register (HETDSET) ......................................................................
20.4.22 N2HET Data Clear Register (HETDCLR) ..................................................................
20.4.23 N2HET Open Drain Register (HETPDR) ...................................................................
20.4.24 N2HET Pull Disable Register (HETPULDIS) ..............................................................
20.4.25 N2HET Pull Select Register (HETPSL) ....................................................................
20.4.26 Parity Control Register (HETPCR) ..........................................................................
20.4.27 Parity Address Register (HETPAR) .........................................................................
20.4.28 Parity Pin Register (HETPPR) ...............................................................................
20.4.29 Suppression Filter Preload Register (HETSFPRLD) .....................................................
20.4.30 Suppression Filter Enable Register (HETSFENA) ........................................................
20.4.31 Loop Back Pair Select Register (HETLBPSEL) ...........................................................
20.4.32 Loop Back Pair Direction Register (HETLBPDIR) ........................................................
20.4.33 N2HET Pin Disable Register (HETPINDIS) ...............................................................
HWAG Registers ..........................................................................................................
20.5.1 HWAG Pin Select Register (HWAPINSEL) .................................................................
20.5.2 HWAG Global Control Register 0 (HWAGCR0) ............................................................
20.5.3 HWAG Global Control Register 1 (HWAGCR1) ............................................................
20.5.4 HWAG Global Control Register 2 (HWAGCR2) ............................................................
20.5.5 HWAG Interrupt Enable Set Register (HWAENASET) ....................................................
20.5.6 HWAG Interrupt Enable Clear Register (HWAENACLR) ..................................................
20.5.7 HWAG Interrupt Level Set Register (HWALVLSET) .......................................................
20.5.8 HWAG Interrupt Level Clear Register (HWALVLCLR) ....................................................
20.5.9 HWAG Interrupt Flag Register (HWAFLG) ..................................................................
20.5.10 HWAG Interrupt Offset Register 0 (HWAOFF0) ..........................................................
20.5.11 HWAG Interrupt Offset Register 1 (HWAOFF1) ..........................................................
20.5.12 HWAG Angle Value Register (HWAACNT) ................................................................
20.5.13 HWAG Previous Tooth Period Value Register (HWAPCNT1) ..........................................
20.5.14 HWAG Current Tooth Period Value Register (HWAPCNT) .............................................
20.5.15 HWAG Step Width Register (HWASTWD).................................................................
20.5.16 HWAG Teeth Number Register (HWATHNB) .............................................................
20.5.17 HWAG Current Teeth Number Register (HWATHVL) ....................................................
20.5.18 HWAG Filter Register (HWAFIL) ............................................................................
20.5.19 HWAG Filter Register 2 (HWAFIL2) ........................................................................
20.5.20 HWAG Angle Increment Register (HWAANGI) ...........................................................
Instruction Set .............................................................................................................
20.6.1 Instruction Summary ...........................................................................................
20.6.2 Abbreviations, Encoding Formats and Bits .................................................................
20.6.3 Instruction Description .........................................................................................
Overview ...................................................................................................................
21.1.1 Features..........................................................................................................
Module Operation .........................................................................................................
21.2.1 Data Transfers between Main RAM and N2HET RAM ....................................................
21.2.2 Arbitration of HTU Elements and Frames ...................................................................
21.2.3 Conditions for Frame Transfer Interruption..................................................................
21.2.4 HTU Overload and Request Lost Detection .................................................................
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21.3
21.4
21.5
21.6
22
21.2.5 Memory Protection ............................................................................................. 981
21.2.6 Control Packet RAM Parity Checking ........................................................................ 981
Use Cases ................................................................................................................. 983
21.3.1 Example: Single Element Transfer with One Trigger Request ........................................... 983
21.3.2 Example: Multiple Element Transfer with One Trigger Request.......................................... 983
21.3.3 Example: 64-Bit-Transfer of Control Field and Data Fields ............................................... 985
HTU Control Registers ................................................................................................... 986
21.4.1 Global Control Register (HTU GC) ........................................................................... 987
21.4.2 Control Packet Enable Register (HTU CPENA) ............................................................ 988
21.4.3 Control Packet (CP) Busy Register 0 (HTU BUSY0) ...................................................... 989
21.4.4 Control Packet (CP) Busy Register 1 (HTU BUSY1) ...................................................... 990
21.4.5 Control Packet (CP) Busy Register 2 (HTU BUSY2) ...................................................... 990
21.4.6 Control Packet (CP) Busy Register 3 (HTU BUSY3) ...................................................... 991
21.4.7 Active Control Packet and Error Register (HTU ACPE) ................................................... 991
21.4.8 Request Lost and Bus Error Control Register (HTU RLBECTRL) ....................................... 993
21.4.9 Buffer Full Interrupt Enable Set Register (HTU BFINTS).................................................. 994
21.4.10 Buffer Full Interrupt Enable Clear Register (HTU BFINTC) ............................................. 994
21.4.11 Interrupt Mapping Register (HTU INTMAP) ............................................................... 995
21.4.12 Interrupt Offset Register 0 (HTU INTOFF0) ............................................................... 996
21.4.13 Interrupt Offset Register 1 (HTU INTOFF1) ............................................................... 997
21.4.14 Buffer Initialization Mode Register (HTU BIM) ............................................................ 998
21.4.15 Request Lost Flag Register (HTU RLOSTFL) ........................................................... 1000
21.4.16 Buffer Full Interrupt Flag Register (HTU BFINTFL) ..................................................... 1000
21.4.17 BER Interrupt Flag Register (HTU BERINTFL) .......................................................... 1001
21.4.18 Memory Protection 1 Start Address Register (HTU MP1S) ............................................ 1002
21.4.19 Memory Protection 1 End Address Register (HTU MP1E) ............................................. 1002
21.4.20 Debug Control Register (HTU DCTRL) ................................................................... 1003
21.4.21 Watch Point Register (HTU WPR) ........................................................................ 1004
21.4.22 Watch Mask Register (HTU WMR) ........................................................................ 1004
21.4.23 Module Identification Register (HTU ID) .................................................................. 1005
21.4.24 Parity Control Register (HTU PCR) ....................................................................... 1006
21.4.25 Parity Address Register (HTU PAR) ...................................................................... 1007
21.4.26 Memory Protection Control and Status Register (HTU MPCS) ........................................ 1008
21.4.27 Memory Protection Start Address Register 0 (HTU MP0S) ............................................ 1011
21.4.28 Memory Protection End Address Register (HTU MP0E) ............................................... 1011
Double Control Packet Configuration Memory ...................................................................... 1012
21.5.1 Initial Full Address A Register (HTU IFADDRA) .......................................................... 1013
21.5.2 Initial Full Address B Register (HTU IFADDRB) .......................................................... 1013
21.5.3 Initial N2HET Address and Control Register (HTU IHADDRCT) ....................................... 1014
21.5.4 Initial Transfer Count Register (HTU ITCOUNT) .......................................................... 1015
21.5.5 Current Full Address A Register (HTU CFADDRA) ...................................................... 1016
21.5.6 Current Full Address B Register (HTU CFADDRB) ...................................................... 1017
21.5.7 Current Frame Count Register (HTU CFCOUNT) ........................................................ 1018
Examples ................................................................................................................. 1019
21.6.1 Application Examples for Setting the Transfer Modes of CP A and B of a DCP ..................... 1019
21.6.2 Software Example Sequence Assuming Circular Mode for Both CP A and B ........................ 1019
21.6.3 Example of an Interrupt Dispatch Flow for a Request Lost Interrupt ................................... 1020
General-Purpose Input/Output (GIO) Module ...................................................................... 1021
22.1
22.2
22.3
Overview..................................................................................................................
Quick Start Guide .......................................................................................................
Functional Description of GIO Module................................................................................
22.3.1 I/O Functions...................................................................................................
22.3.2 Interrupt Function .............................................................................................
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22.5
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FlexRay Module .............................................................................................................. 1048
23.1
23.2
23.3
23.4
23.5
23.6
23.7
23.8
23.9
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22.3.3 GIO Block Diagram ...........................................................................................
Device Modes of Operation ............................................................................................
22.4.1 Emulation Mode ...............................................................................................
22.4.2 Power-Down Mode (Low-Power Mode) ....................................................................
GIO Control Registers ..................................................................................................
22.5.1 GIO Global Control Register (GIOGCR0) ..................................................................
22.5.2 GIO Interrupt Detect Register (GIOINTDET) ..............................................................
22.5.3 GIO Interrupt Polarity Register (GIOPOL) .................................................................
22.5.4 GIO Interrupt Enable Registers (GIOENASET and GIOENACLR) .....................................
22.5.5 GIO Interrupt Priority Registers (GIOLVLSET and GIOLVLCLR) .......................................
22.5.6 GIO Interrupt Flag Register (GIOFLG) .....................................................................
22.5.7 GIO Offset Register 1 (GIOOFF1) ..........................................................................
22.5.8 GIO Offset B Register (GIOOFF2) ..........................................................................
22.5.9 GIO Emulation A Register (GIOEMU1) ....................................................................
22.5.10 GIO Emulation B Register (GIOEMU2) ...................................................................
22.5.11 GIO Data Direction Registers (GIODIR[A-B]) ............................................................
22.5.12 GIO Data Input Registers (GIODIN[A-B]).................................................................
22.5.13 GIO Data Output Registers (GIODOUT[A-B]) ...........................................................
22.5.14 GIO Data Set Registers (GIODSET[A-B]) ................................................................
22.5.15 GIO Data Clear Registers (GIODCLR[A-B]) .............................................................
22.5.16 GIO Open Drain Registers (GIOPDR[A-B]) ..............................................................
22.5.17 GIO Pull Disable Registers (GIOPULDIS[A-B]) ..........................................................
22.5.18 GIO Pull Select Registers (GIOPSL[A-B]) ................................................................
I/O Control Summary ...................................................................................................
Overview..................................................................................................................
23.1.1 Feature List ....................................................................................................
FlexRay Module Block Diagram .......................................................................................
FlexRay Module Block Mapping .......................................................................................
Transfer Unit Block Diagram ...........................................................................................
Transfer Unit Functional Description..................................................................................
23.5.1 Transfer Control ...............................................................................................
23.5.2 Transfer Configuration RAM .................................................................................
23.5.3 Memory Protection Mechanism .............................................................................
Communication Cycle ..................................................................................................
23.6.1 Static Segment ................................................................................................
23.6.2 Dynamic Segment .............................................................................................
23.6.3 Symbol Window ...............................................................................................
23.6.4 Network Idle Time (NIT) ......................................................................................
23.6.5 Configuration of NIT Start and Offset Correction Start ...................................................
Communication Modes .................................................................................................
23.7.1 Time-Triggered Distributed (TT-D) ..........................................................................
Clock Synchronization ..................................................................................................
23.8.1 Global Time ....................................................................................................
23.8.2 Local Time .....................................................................................................
23.8.3 Synchronization Process .....................................................................................
23.8.4 Sync Frame Transmission ...................................................................................
23.8.5 External Clock Synchronization .............................................................................
Error Handling ...........................................................................................................
23.9.1 Clock Correction Failed Counter ............................................................................
23.9.2 Passive to Active Counter ....................................................................................
23.9.3 HALT Command...............................................................................................
23.9.4 FREEZE Command ...........................................................................................
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23.10 Communication Controller States .....................................................................................
23.10.1 Communication Controller State Diagram ................................................................
23.10.2 DEFAULT_CONFIG State ..................................................................................
23.10.3 CONFIG State ................................................................................................
23.10.4 MONITOR_MODE ...........................................................................................
23.10.5 READY State .................................................................................................
23.10.6 WAKEUP State ..............................................................................................
23.10.7 STARTUP State .............................................................................................
23.10.8 NORMAL_ACTIVE State ...................................................................................
23.10.9 NORMAL_PASSIVE State .................................................................................
23.10.10 HALT State ..................................................................................................
23.11 Network Management ..................................................................................................
23.12 Filtering and Masking ...................................................................................................
23.12.1 Slot Counter Filtering ........................................................................................
23.12.2 Cycle Counter Filtering ......................................................................................
23.12.3 Channel ID Filtering .........................................................................................
23.12.4 FIFO Filtering .................................................................................................
23.13 Transmit Process .......................................................................................................
23.13.1 Static Segment ...............................................................................................
23.13.2 Dynamic Segment ...........................................................................................
23.13.3 Transmit Buffers .............................................................................................
23.13.4 Frame Transmission.........................................................................................
23.13.5 Null Frame Transmission ...................................................................................
23.14 Receive Process ........................................................................................................
23.14.1 Dedicated Receive Buffers .................................................................................
23.14.2 Frame Reception ............................................................................................
23.14.3 Null Frame Reception .......................................................................................
23.15 FIFO Function ...........................................................................................................
23.15.1 Description ....................................................................................................
23.15.2 Configuration of the FIFO...................................................................................
23.15.3 Access to the FIFO ..........................................................................................
23.16 Message Handling ......................................................................................................
23.16.1 Reconfiguration of Message Buffers ......................................................................
23.16.2 Host Access to Message RAM.............................................................................
23.16.3 FlexRay Protocol Controller Access to Message RAM .................................................
23.17 Module RAMs ...........................................................................................................
23.17.1 Message RAM ...............................................................................................
23.17.2 Parity Check ..................................................................................................
23.18 Interrupts .................................................................................................................
23.18.1 Transfer Unit Interrupts .....................................................................................
23.18.2 Communication Controller Interrupts ......................................................................
23.19 FlexRay Module Registers .............................................................................................
23.19.1 Transfer Unit Registers .....................................................................................
23.19.2 Communication Controller Registers ......................................................................
23.20 Minimum Peripheral Clock Frequency ..............................................................................
23.21 Assignment of FlexRay Configuration Parameters ................................................................
23.22 Emulation/Debug Support .............................................................................................
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Controller Area Network (DCAN) Module............................................................................ 1245
24.1
24.2
Overview..................................................................................................................
24.1.1 Features ........................................................................................................
24.1.2 Functional Description ........................................................................................
CAN Blocks ..............................................................................................................
24.2.1 CAN Core ......................................................................................................
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24.2.2 Message RAM .................................................................................................
24.2.3 Message Handler .............................................................................................
24.2.4 Message RAM Interface ......................................................................................
24.2.5 Register and Message Object Access .....................................................................
24.2.6 Dual Clock Source ............................................................................................
24.3 CAN Bit Timing ..........................................................................................................
24.3.1 Bit Time and Bit Rate .........................................................................................
24.3.2 DCAN Bit Timing Registers ..................................................................................
24.4 CAN Module Configuration.............................................................................................
24.4.1 DCAN RAM Initialization through Hardware ...............................................................
24.4.2 CAN Module Initialization ....................................................................................
24.5 Message RAM ...........................................................................................................
24.5.1 Structure of Message Objects ...............................................................................
24.5.2 Addressing Message Objects in RAM ......................................................................
24.5.3 Message RAM Representation in Debug/Suspend Mode ...............................................
24.5.4 Message RAM Representation in Direct Access Mode ..................................................
24.6 Message Interface Register Sets .....................................................................................
24.6.1 Message Interface Register Sets 1 and 2 .................................................................
24.6.2 Using Message Interface Register Sets 1 and 2 ..........................................................
24.6.3 Message Interface Register 3 ...............................................................................
24.7 Message Object Configurations .......................................................................................
24.7.1 Configuration of a Transmit Object for Data Frames .....................................................
24.7.2 Configuration of a Transmit Object for Remote Frames .................................................
24.7.3 Configuration of a Single Receive Object for Data Frames .............................................
24.7.4 Configuration of a Single Receive Object for Remote Frames ..........................................
24.7.5 Configuration of a FIFO Buffer ..............................................................................
24.7.6 Reconfiguration of Message Objects for the Reception of Frames.....................................
24.7.7 Reconfiguration of Message Objects for the Transmission of Frames .................................
24.8 Message Handling ......................................................................................................
24.8.1 Message Handler Overview .................................................................................
24.8.2 Receive/Transmit Priority.....................................................................................
24.8.3 Transmission of Messages in Event Driven CAN Communication .....................................
24.8.4 Updating a Transmit Object ..................................................................................
24.8.5 Changing a Transmit Object .................................................................................
24.8.6 Acceptance Filtering of Received Messages ..............................................................
24.8.7 Reception of Data Frames ...................................................................................
24.8.8 Reception of Remote Frames ...............................................................................
24.8.9 Reading Received Messages ...............................................................................
24.8.10 Requesting New Data for a Receive Object .............................................................
24.8.11 Storing Received Messages in FIFO Buffers ............................................................
24.8.12 Reading from a FIFO Buffer ...............................................................................
24.9 CAN Message Transfer ................................................................................................
24.9.1 Automatic Retransmission ...................................................................................
24.9.2 Auto-Bus-On ...................................................................................................
24.10 Interrupt Functionality ..................................................................................................
24.10.1 Message Object Interrupts .................................................................................
24.10.2 Status Change Interrupts ...................................................................................
24.10.3 Error Interrupts ...............................................................................................
24.11 Global Power-Down Mode .............................................................................................
24.11.1 Entering Global Power-Down Mode .......................................................................
24.11.2 Wakeup From Global Power-Down Mode ................................................................
24.12 Local Power-Down Mode ..............................................................................................
24.12.1 Entering Local Power-Down Mode ........................................................................
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24.12.2 Wakeup From Local Power-Down Mode .................................................................
24.13 GIO Support .............................................................................................................
24.14 Test Modes ..............................................................................................................
24.14.1 Silent Mode ...................................................................................................
24.14.2 Loop Back Mode .............................................................................................
24.14.3 External Loop Back Mode ..................................................................................
24.14.4 Loop Back Combined with Silent Mode...................................................................
24.14.5 Software Control of CAN_TX Pin ..........................................................................
24.15 Parity Check Mechanism ..............................................................................................
24.15.1 Behavior on Parity Error ....................................................................................
24.15.2 Parity Testing .................................................................................................
24.16 Debug/Suspend Mode..................................................................................................
24.17 DCAN Control Registers ...............................................................................................
24.17.1 CAN Control Register (DCAN CTL) .......................................................................
24.17.2 Error and Status Register (DCAN ES) ....................................................................
24.17.3 Error Counter Register (DCAN ERRC) ...................................................................
24.17.4 Bit Timing Register (DCAN BTR) ..........................................................................
24.17.5 Interrupt Register (DCAN INT) .............................................................................
24.17.6 Test Register (DCAN TEST) ...............................................................................
24.17.7 Parity Error Code Register (DCAN PERR) ...............................................................
24.17.8 Core Release Register (DCAN REL) .....................................................................
24.17.9 Auto-Bus-On Time Register (DCAN ABOTR)............................................................
24.17.10 Transmission Request X Register (DCAN TXRQ X) ..................................................
24.17.11 Transmission Request Registers (DCAN TXRQ12 to DCAN TXRQ78) ............................
24.17.12 New Data X Register (DCAN NWDAT X) ...............................................................
24.17.13 New Data Registers (DCAN NWDAT12 to DCAN NWDAT78) ......................................
24.17.14 Interrupt Pending X Register (DCAN INTPND X) ......................................................
24.17.15 Interrupt Pending Registers (DCAN INTPND12 to DCAN INTPND78) .............................
24.17.16 Message Valid X Register (DCAN MSGVAL X)........................................................
24.17.17 Message Valid Registers (DCAN MSGVAL12 to DCAN MSGVAL78) ..............................
24.17.18 Interrupt Multiplexer Registers (DCAN INTMUX12 to DCAN INTMUX78)..........................
24.17.19 IF1/IF2 Command Registers (DCAN IF1CMD, DCAN IF2CMD).....................................
24.17.20 IF1/IF2 Mask Registers (DCAN IF1MSK, DCAN IF2MSK) ...........................................
24.17.21 IF1/IF2 Arbitration Registers (DCAN IF1ARB, DCAN IF2ARB) ......................................
24.17.22 IF1/IF2 Message Control Registers (DCAN IF1MCTL, DCAN IF2MCTL) ..........................
24.17.23 IF1/IF2 Data A and Data B Registers (DCAN IF1DATA/DATB, DCAN IF2DATA/DATB) ........
24.17.24 IF3 Observation Register (DCAN IF3OBS) .............................................................
24.17.25 IF3 Mask Register (DCAN IF3MSK) .....................................................................
24.17.26 IF3 Arbitration Register (DCAN IF3ARB) ...............................................................
24.17.27 IF3 Message Control Register (DCAN IF3MCTL) .....................................................
24.17.28 IF3 Data A and Data B Registers (DCAN IF3DATA/DATB) ..........................................
24.17.29 IF3 Update Enable Registers (DCAN IF3UPD12 to IF3UPD78) .....................................
24.17.30 CAN TX IO Control Register (DCAN TIOC) ............................................................
24.17.31 CAN RX IO Control Register (DCAN RIOC) ............................................................
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Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin Option (MibSPIP) . 1318
25.1
25.2
Overview..................................................................................................................
25.1.1 Word Format Options .........................................................................................
25.1.2 Multi-buffering (Mib) Support ................................................................................
25.1.3 Transmission Lock (Multi-Buffer Mode Master Only) .....................................................
Operating Modes ........................................................................................................
25.2.1 Pin Configurations .............................................................................................
25.2.2 Data Handling..................................................................................................
25.2.3 Operation with SPICS ........................................................................................
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25.3
25.4
25.5
25.6
25.7
25.8
25.9
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25.2.4 Operation with SPIENA.......................................................................................
25.2.5 Five-Pin Operation (Hardware Handshaking) .............................................................
25.2.6 Data Formats ..................................................................................................
25.2.7 Clocking Modes ...............................................................................................
25.2.8 Data Transfer Example .......................................................................................
25.2.9 Decoded and Encoded Chip Select (Master Only) .......................................................
25.2.10 Variable Chip Select Setup and Hold Timing (Master Only) ...........................................
25.2.11 Hold Chip-Select Active .....................................................................................
25.2.12 Detection of Slave Desynchronization (Master Only) ...................................................
25.2.13 ENA Signal Time-Out (Master Only) ......................................................................
25.2.14 Data-Length Error............................................................................................
25.2.15 Parallel Mode (Multiple SIMO/SOMI Support, not available on all devices) .........................
25.2.16 Continuous Self-Test (Master/Slave) ......................................................................
25.2.17 Half Duplex Mode ............................................................................................
Test Features ............................................................................................................
25.3.1 Internal Loop-Back Test Mode (Master Only) .............................................................
25.3.2 Input/Output Loopback Test Mode ..........................................................................
General-Purpose I/O ....................................................................................................
Low-Power Mode ........................................................................................................
Interrupts .................................................................................................................
25.6.1 Interrupts in Multi-Buffer Mode ..............................................................................
DMA Interface ...........................................................................................................
25.7.1 DMA in Multi-Buffer Mode ....................................................................................
Module Configuration ...................................................................................................
25.8.1 Compatibility (SPI) Mode Configuration ....................................................................
25.8.2 MibSPI Mode Configuration..................................................................................
Control Registers ........................................................................................................
25.9.1 SPI Global Control Register 0 (SPIGCR0) .................................................................
25.9.2 SPI Global Control Register 1 (SPIGCR1) .................................................................
25.9.3 SPI Interrupt Register (SPIINT0) ............................................................................
25.9.4 SPI Interrupt Level Register (SPILVL) ......................................................................
25.9.5 SPI Flag Register (SPIFLG) .................................................................................
25.9.6 SPI Pin Control Register 0 (SPIPC0) .......................................................................
25.9.7 SPI Pin Control Register 1 (SPIPC1) .......................................................................
25.9.8 SPI Pin Control Register 2 (SPIPC2) .......................................................................
25.9.9 SPI Pin Control Register 3 (SPIPC3) .......................................................................
25.9.10 SPI Pin Control Register 4 (SPIPC4) .....................................................................
25.9.11 SPI Pin Control Register 5 (SPIPC5) .....................................................................
25.9.12 SPI Pin Control Register 6 (SPIPC6) .....................................................................
25.9.13 SPI Pin Control Register 7 (SPIPC7) .....................................................................
25.9.14 SPI Pin Control Register 8 (SPIPC8) .....................................................................
25.9.15 SPI Transmit Data Register 0 (SPIDAT0) ................................................................
25.9.16 SPI Transmit Data Register 1 (SPIDAT1) ................................................................
25.9.17 SPI Receive Buffer Register (SPIBUF) ...................................................................
25.9.18 SPI Emulation Register (SPIEMU) ........................................................................
25.9.19 SPI Delay Register (SPIDELAY) ..........................................................................
25.9.20 SPI Default Chip Select Register (SPIDEF) ..............................................................
25.9.21 SPI Data Format Registers (SPIFMT) ....................................................................
25.9.22 Interrupt Vector 0 (INTVECT0).............................................................................
25.9.23 Interrupt Vector 1 (INTVECT1).............................................................................
25.9.24 SPI Pin Control Register 9 (SPIPC9) .....................................................................
25.9.25 Parallel/Modulo Mode Control Register (SPIPMCTRL) .................................................
25.9.26 Multi-buffer Mode Enable Register (MIBSPIE)...........................................................
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25.9.27 TG Interrupt Enable Set Register (TGITENST) ..........................................................
25.9.28 TG Interrupt Enable Clear Register (TGITENCR) .......................................................
25.9.29 Transfer Group Interrupt Level Set Register (TGITLVST)..............................................
25.9.30 Transfer Group Interrupt Level Clear Register (TGITLVCR) ...........................................
25.9.31 Transfer Group Interrupt Flag Register (TGINTFLG) ...................................................
25.9.32 Tick Count Register (TICKCNT) ...........................................................................
25.9.33 Last TG End Pointer (LTGPEND) .........................................................................
25.9.34 TGx Control Registers (TGxCTRL) ........................................................................
25.9.35 DMA Channel Control Register (DMAxCTRL) ...........................................................
25.9.36 DMAxCOUNT Register (ICOUNT) ........................................................................
25.9.37 DMA Large Count (DMACNTLEN) ........................................................................
25.9.38 Multi-buffer RAM Uncorrectable Parity Error Control Register (UERRCTRL) .......................
25.9.39 Multi-buffer RAM Uncorrectable Parity Error Status Register (UERRSTAT) ........................
25.9.40 RXRAM Uncorrectable Parity Error Address Register (UERRADDR1) ..............................
25.9.41 TXRAM Uncorrectable Parity Error Address Register (UERRADDR0) ...............................
25.9.42 RXRAM Overrun Buffer Address Register (RXOVRN_BUF_ADDR) .................................
25.9.43 I/O-Loopback Test Control Register (IOLPBKTSTCR) .................................................
25.9.44 SPI Extended Prescale Register 1 (EXTENDED_PRESCALE1 for SPIFMT0 and SPIFMT1) ....
25.9.45 SPI Extended Prescale Register 2 (EXTENDED_PRESCALE2 for SPIFMT2 and SPIFMT3) ....
25.10 Multi-Buffer RAM ........................................................................................................
25.10.1 Multi-Buffer RAM Auto Initialization .......................................................................
25.10.2 Multi-Buffer RAM Register Summary .....................................................................
25.10.3 Multi-Buffer RAM Transmit Data Register (TXRAM) ....................................................
25.10.4 Multi-Buffer RAM Receive Buffer Register (RXRAM) ...................................................
25.11 Parity Memory ...........................................................................................................
25.11.1 Example of Parity Memory Organization .................................................................
25.12 MibSPI Pin Timing Parameters .......................................................................................
25.12.1 Master Mode Timings for SPI/MibSPI.....................................................................
25.12.2 Slave Mode Timings for SPI/MibSPI ......................................................................
25.12.3 Master Mode Timing Parameter Details ..................................................................
25.12.4 Slave Mode Timing Parameter Details....................................................................
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Serial Communication Interface (SCI)/ Local Interconnect Network (LIN) Module .................... 1429
26.1
26.2
26.3
26.4
26.5
Introduction and Features ..............................................................................................
26.1.1 SCI Features ...................................................................................................
26.1.2 LIN Features ...................................................................................................
26.1.3 Block Diagram .................................................................................................
SCI Communication Formats ..........................................................................................
26.2.1 SCI Frame Formats ...........................................................................................
26.2.2 SCI Timing Mode ..............................................................................................
26.2.3 SCI Baud Rate.................................................................................................
26.2.4 SCI Multiprocessor Communication Modes ...............................................................
26.2.5 SCI Multi-Buffered Mode .....................................................................................
SCI Interrupts ............................................................................................................
26.3.1 Transmit Interrupt .............................................................................................
26.3.2 Receive Interrupt ..............................................................................................
26.3.3 WakeUp Interrupt .............................................................................................
26.3.4 Error Interrupts ................................................................................................
SCI DMA Interface ......................................................................................................
26.4.1 Receive DMA Requests ......................................................................................
26.4.2 Transmit DMA Requests .....................................................................................
SCI Configurations ......................................................................................................
26.5.1 Receiving Data ................................................................................................
26.5.2 Transmitting Data .............................................................................................
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26.6
26.7
26.8
26.9
26.10
26.11
26.12
26.13
24
SCI Low-Power Mode ..................................................................................................
26.6.1 Sleep Mode for Multiprocessor Communication ..........................................................
LIN Communication Formats ..........................................................................................
26.7.1 LIN Standards .................................................................................................
26.7.2 Message Frame ...............................................................................................
26.7.3 Synchronizer ...................................................................................................
26.7.4 Baud Rate ......................................................................................................
26.7.5 Header Generation ............................................................................................
26.7.6 Extended Frames Handling ..................................................................................
26.7.7 Timeout Control ...............................................................................................
26.7.8 TXRX Error Detector (TED) ..................................................................................
26.7.9 Message Filtering and Validation ...........................................................................
26.7.10 Receive Buffers ..............................................................................................
26.7.11 Transmit Buffers.............................................................................................
LIN Interrupts ............................................................................................................
LIN DMA Interface ......................................................................................................
26.9.1 LIN Receive DMA Requests .................................................................................
26.9.2 LIN Transmit DMA Requests ................................................................................
LIN Configurations ......................................................................................................
26.10.1 Receiving Data ...............................................................................................
26.10.2 Transmitting Data ............................................................................................
Low-Power Mode .......................................................................................................
26.11.1 Entering Sleep Mode ........................................................................................
26.11.2 Wakeup .......................................................................................................
26.11.3 Wakeup Timeouts ...........................................................................................
Emulation Mode .........................................................................................................
SCI/LIN Control Registers .............................................................................................
26.13.1 SCI Global Control Register 0 (SCIGCR0) ...............................................................
26.13.2 SCI Global Control Register 1 (SCIGCR1) ...............................................................
26.13.3 SCI Global Control Register 2 (SCIGCR2) ...............................................................
26.13.4 SCI Set Interrupt Register (SCISETINT) .................................................................
26.13.5 SCI Clear Interrupt Register (SCICLEARINT) ...........................................................
26.13.6 SCI Set Interrupt Level Register (SCISETINTLVL) .....................................................
26.13.7 SCI Clear Interrupt Level Register (SCICLEARINTLVL) ...............................................
26.13.8 SCI Flags Register (SCIFLR) ..............................................................................
26.13.9 SCI Interrupt Vector Offset 0 (SCIINTVECT0) ...........................................................
26.13.10 SCI Interrupt Vector Offset 1 (SCIINTVECT1) .........................................................
26.13.11 SCI Format Control Register (SCIFORMAT) ...........................................................
26.13.12 Baud Rate Selection Register (BRS) ....................................................................
26.13.13 SCI Data Buffers (SCIED, SCIRD, SCITD) .............................................................
26.13.14 SCI Pin I/O Control Register 0 (SCIPIO0) .............................................................
26.13.15 SCI Pin I/O Control Register 1 (SCIPIO1) .............................................................
26.13.16 SCI Pin I/O Control Register 2 (SCIPIO2) .............................................................
26.13.17 SCI Pin I/O Control Register 3 (SCIPIO3) .............................................................
26.13.18 SCI Pin I/O Control Register 4 (SCIPIO4) .............................................................
26.13.19 SCI Pin I/O Control Register 5 (SCIPIO5) .............................................................
26.13.20 SCI Pin I/O Control Register 6 (SCIPIO6) .............................................................
26.13.21 SCI Pin I/O Control Register 7 (SCIPIO7) .............................................................
26.13.22 SCI Pin I/O Control Register 8 (SCIPIO8) .............................................................
26.13.23 LIN Compare Register (LINCOMPARE) ................................................................
26.13.24 LIN Receive Buffer 0 Register (LINRD0)................................................................
26.13.25 LIN Receive Buffer 1 Register (LINRD1)................................................................
26.13.26 LIN Mask Register (LINMASK) ...........................................................................
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26.13.27 LIN Identification Register (LINID) .......................................................................
26.13.28 LIN Transmit Buffer 0 Register (LINTD0) ...............................................................
26.13.29 LIN Transmit Buffer 1 Register (LINTD1) ...............................................................
26.13.30 Maximum Baud Rate Selection Register (MBRS) .....................................................
26.13.31 Input/Output Error Enable (IODFTCTRL) Register ....................................................
26.14 GPIO Functionality ......................................................................................................
26.14.1 GPIO Functionality ..........................................................................................
26.14.2 Under Reset ..................................................................................................
26.14.3 Out of Reset ..................................................................................................
26.14.4 Open-Drain Feature Enabled on a Pin ....................................................................
26.14.5 Summary ......................................................................................................
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Serial Communication Interface (SCI) Module ..................................................................... 1525
27.1
27.2
27.3
27.4
27.5
27.6
27.7
Introduction ...............................................................................................................
27.1.1 SCI Features ...................................................................................................
27.1.2 Block Diagram .................................................................................................
SCI Communication Formats ..........................................................................................
27.2.1 SCI Frame Formats ...........................................................................................
27.2.2 SCI Timing Mode ..............................................................................................
27.2.3 SCI Baud Rate.................................................................................................
27.2.4 SCI Multiprocessor Communication Modes ...............................................................
SCI Interrupts ............................................................................................................
27.3.1 Transmit Interrupt .............................................................................................
27.3.2 Receive Interrupt ..............................................................................................
27.3.3 WakeUp Interrupt .............................................................................................
27.3.4 Error Interrupts ................................................................................................
SCI DMA Interface ......................................................................................................
27.4.1 Receive DMA Requests ......................................................................................
27.4.2 Transmit DMA Requests .....................................................................................
SCI Configurations ......................................................................................................
27.5.1 Receiving Data ................................................................................................
27.5.2 Transmitting Data .............................................................................................
SCI Low-Power Mode ..................................................................................................
27.6.1 Sleep Mode for Multiprocessor Communication ..........................................................
SCI Control Registers ..................................................................................................
27.7.1 SCI Global Control Register 0 (SCIGCR0) ................................................................
27.7.2 SCI Global Control Register 1 (SCIGCR1) ................................................................
27.7.3 SCI Set Interrupt Register (SCISETINT) ..................................................................
27.7.4 SCI Clear Interrupt Register (SCICLEARINT) ............................................................
27.7.5 SCI Set Interrupt Level Register (SCISETINTLVL) ......................................................
27.7.6 SCI Clear Interrupt Level Register (SCICLEARINTLVL) ................................................
27.7.7 SCI Flags Register (SCIFLR) ...............................................................................
27.7.8 SCI Interrupt Vector Offset 0 (SCIINTVECT0) ...........................................................
27.7.9 SCI Interrupt Vector Offset 1 (SCIINTVECT1) ...........................................................
27.7.10 SCI Format Control Register (SCIFORMAT) ............................................................
27.7.11 Baud Rate Selection Register (BRS) .....................................................................
27.7.12 SCI Data Buffers (SCIED, SCIRD, SCITD) ..............................................................
27.7.13 SCI Pin I/O Control Register 0 (SCIPIO0) ...............................................................
27.7.14 SCI Pin I/O Control Register 1 (SCIPIO1) ...............................................................
27.7.15 SCI Pin I/O Control Register 2 (SCIPIO2) ...............................................................
27.7.16 SCI Pin I/O Control Register 3 (SCIPIO3) ...............................................................
27.7.17 SCI Pin I/O Control Register 4 (SCIPIO4) ...............................................................
27.7.18 SCI Pin I/O Control Register 5 (SCIPIO5) ...............................................................
27.7.19 SCI Pin I/O Control Register 6 (SCIPIO6) ...............................................................
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27.8
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Inter-Integrated Circuit (I2C) Module .................................................................................. 1572
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28.2
28.3
28.4
28.5
28.6
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27.7.20 SCI Pin I/O Control Register 7 (SCIPIO7) ...............................................................
27.7.21 SCI Pin I/O Control Register 8 (SCIPIO8) ...............................................................
27.7.22 Input/Output Error Enable (IODFTCTRL) Register .....................................................
GPIO Functionality ......................................................................................................
27.8.1 GPIO Functionality ............................................................................................
27.8.2 Under Reset ...................................................................................................
27.8.3 Out of Reset ...................................................................................................
27.8.4 Open-Drain Feature Enabled on a Pin .....................................................................
27.8.5 Summary .......................................................................................................
Overview..................................................................................................................
28.1.1 Introduction to the I2C Module ..............................................................................
28.1.2 Functional Overview ..........................................................................................
28.1.3 Clock Generation ..............................................................................................
I2C Module Operation ..................................................................................................
28.2.1 Input and Output Voltage Levels ............................................................................
28.2.2 I2C Module Reset Conditions ...............................................................................
28.2.3 I2C Module Data Validity ....................................................................................
28.2.4 I2C Module Start and Stop Conditions .....................................................................
28.2.5 Serial Data Formats...........................................................................................
28.2.6 NACK Bit Generation .........................................................................................
I2C Operation Modes ...................................................................................................
28.3.1 Master Transmitter Mode ....................................................................................
28.3.2 Master Receiver Mode .......................................................................................
28.3.3 Slave Transmitter Mode ......................................................................................
28.3.4 Slave Receiver Mode ........................................................................................
28.3.5 Low Power Mode ..............................................................................................
28.3.6 Free Run Mode ................................................................................................
28.3.7 Ignore NACK Mode ..........................................................................................
I2C Module Integrity.....................................................................................................
28.4.1 Arbitration ......................................................................................................
28.4.2 I2C Clock Generation and Synchronization ...............................................................
28.4.3 Prescaler .......................................................................................................
28.4.4 Noise Filter .....................................................................................................
Operational Information.................................................................................................
28.5.1 I2C Module Interrupts .........................................................................................
28.5.2 DMA Controller Events .......................................................................................
28.5.3 I2C Enable/Disable............................................................................................
28.5.4 General Purpose I/O ..........................................................................................
28.5.5 Pull Up/Pull Down Function ..................................................................................
28.5.6 Open Drain Function ..........................................................................................
I2C Control Registers ...................................................................................................
28.6.1 I2C Own Address Manager (I2COAR) .....................................................................
28.6.2 I2C Interrupt Mask Register (I2CIMR) ......................................................................
28.6.3 I2C Status Register (I2CSTR) ...............................................................................
28.6.4 I2C Clock Divider Low Register (I2CCKL) .................................................................
28.6.5 I2C Clock Control High Register (I2CCKH) ................................................................
28.6.6 I2C Data Count Register (I2CCNT) .........................................................................
28.6.7 I2C Data Receive Register (I2CDRR) ......................................................................
28.6.8 I2C Slave Address Register (I2CSAR) .....................................................................
28.6.9 I2C Data Transmit Register (I2CDXR) .....................................................................
28.6.10 I2C Mode Register (I2CMDR) ..............................................................................
28.6.11 I2C Interrupt Vector Register (I2CIVR) ...................................................................
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28.7
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28.6.12 I2C Extended Mode Register (I2CEMDR) ................................................................
28.6.13 I2C Prescale Register (I2CPSC) ..........................................................................
28.6.14 I2C Peripheral ID Register 1 (I2CPID1) ..................................................................
28.6.15 I2C Peripheral ID Register 2 (I2CPID2) ..................................................................
28.6.16 I2C DMA Control Register (I2CDMACR) .................................................................
28.6.17 I2C Pin Function Register (I2CPFNC) ....................................................................
28.6.18 I2C Pin Direction Register (I2CPDIR) .....................................................................
28.6.19 I2C Data Input Register (I2CDIN) .........................................................................
28.6.20 I2C Data Output Register (I2CDOUT) ....................................................................
28.6.21 I2C Data Set Register (I2CDSET) .........................................................................
28.6.22 I2C Data Clear Register (I2CDCLR) ......................................................................
28.6.23 I2C Pin Open Drain Register (I2CPDR) ..................................................................
28.6.24 I2C Pull Disable Register (I2CPDIS) ......................................................................
28.6.25 I2C Pull Select Register (I2CPSEL) .......................................................................
28.6.26 I2C Pins Slew Rate Select Register (I2CSRS) ..........................................................
Sample Waveforms .....................................................................................................
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EMAC/MDIO Module ........................................................................................................ 1610
29.1
29.2
29.3
Introduction ...............................................................................................................
29.1.1 Purpose of the Peripheral ....................................................................................
29.1.2 Features ........................................................................................................
29.1.3 Functional Block Diagram ....................................................................................
29.1.4 Industry Standard(s) Compliance Statement ..............................................................
Architecture ..............................................................................................................
29.2.1 Clock Control ..................................................................................................
29.2.2 Memory Map ...................................................................................................
29.2.3 Signal Descriptions............................................................................................
29.2.4 MII / RMII Signal Multiplexing Control ......................................................................
29.2.5 Ethernet Protocol Overview ..................................................................................
29.2.6 Programming Interface .......................................................................................
29.2.7 EMAC Control Module ........................................................................................
29.2.8 MDIO Module ..................................................................................................
29.2.9 EMAC Module .................................................................................................
29.2.10 MAC Interface ................................................................................................
29.2.11 Packet Receive Operation ..................................................................................
29.2.12 Packet Transmit Operation .................................................................................
29.2.13 Receive and Transmit Latency.............................................................................
29.2.14 Transfer Node Priority .......................................................................................
29.2.15 Reset Considerations .......................................................................................
29.2.16 Initialization ...................................................................................................
29.2.17 Interrupt Support .............................................................................................
29.2.18 Power Management .........................................................................................
29.2.19 Emulation Considerations ..................................................................................
EMAC Control Module Registers ......................................................................................
29.3.1 EMAC Control Module Revision ID Register (REVID) ...................................................
29.3.2 EMAC Control Module Software Reset Register (SOFTRESET) .......................................
29.3.3 EMAC Control Module Interrupt Control Register (INTCONTROL) ....................................
29.3.4 EMAC Control Module Receive Threshold Interrupt Enable Registers (C0RXTHRESHEN) .......
29.3.5 EMAC Control Module Receive Interrupt Enable Registers (C0RXEN) ...............................
29.3.6 EMAC Control Module Transmit Interrupt Enable Registers (C0TXEN) ...............................
29.3.7 EMAC Control Module Miscellaneous Interrupt Enable Registers (C0MISCEN) .....................
29.3.8 EMAC Control Module Receive Threshold Interrupt Status Registers (C0RXTHRESHSTAT) .....
29.3.9 EMAC Control Module Receive Interrupt Status Registers (C0RXSTAT) .............................
29.3.10 EMAC Control Module Transmit Interrupt Status Registers (C0TXSTAT) ...........................
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29.4
29.5
28
29.3.11 EMAC Control Module Miscellaneous Interrupt Status Registers (C0MISCSTAT) .................
29.3.12 EMAC Control Module Receive Interrupts Per Millisecond Registers (C0RXIMAX) ................
29.3.13 EMAC Control Module Transmit Interrupts Per Millisecond Registers (C0TXIMAX) ...............
MDIO Registers..........................................................................................................
29.4.1 MDIO Revision ID Register (REVID) .......................................................................
29.4.2 MDIO Control Register (CONTROL) .......................................................................
29.4.3 PHY Acknowledge Status Register (ALIVE) ...............................................................
29.4.4 PHY Link Status Register (LINK) ...........................................................................
29.4.5 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) ...........................
29.4.6 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) .........................
29.4.7 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW)..................
29.4.8 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) ................
29.4.9 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) ..............
29.4.10 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) .......
29.4.11 MDIO User Access Register 0 (USERACCESS0) ......................................................
29.4.12 MDIO User PHY Select Register 0 (USERPHYSEL0)..................................................
29.4.13 MDIO User Access Register 1 (USERACCESS1) ......................................................
29.4.14 MDIO User PHY Select Register 1 (USERPHYSEL1)..................................................
EMAC Module Registers ...............................................................................................
29.5.1 Transmit Revision ID Register (TXREVID) ................................................................
29.5.2 Transmit Control Register (TXCONTROL) .................................................................
29.5.3 Transmit Teardown Register (TXTEARDOWN) ...........................................................
29.5.4 Receive Revision ID Register (RXREVID) .................................................................
29.5.5 Receive Control Register (RXCONTROL) .................................................................
29.5.6 Receive Teardown Register (RXTEARDOWN) ...........................................................
29.5.7 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) ...................................
29.5.8 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) .................................
29.5.9 Transmit Interrupt Mask Set Register (TXINTMASKSET) ...............................................
29.5.10 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) .......................................
29.5.11 MAC Input Vector Register (MACINVECTOR) ..........................................................
29.5.12 MAC End Of Interrupt Vector Register (MACEOIVECTOR) ...........................................
29.5.13 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) ..................................
29.5.14 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) ................................
29.5.15 Receive Interrupt Mask Set Register (RXINTMASKSET) ..............................................
29.5.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) ........................................
29.5.17 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) ...................................
29.5.18 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) ..................................
29.5.19 MAC Interrupt Mask Set Register (MACINTMASKSET)................................................
29.5.20 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) .........................................
29.5.21 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) .........
29.5.22 Receive Unicast Enable Set Register (RXUNICASTSET) .............................................
29.5.23 Receive Unicast Clear Register (RXUNICASTCLEAR) ................................................
29.5.24 Receive Maximum Length Register (RXMAXLEN)......................................................
29.5.25 Receive Buffer Offset Register (RXBUFFEROFFSET) .................................................
29.5.26 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH).................
29.5.27 Receive Channel Flow Control Threshold Registers (RX0FLOWTHRESH-RX7FLOWTHRESH)
29.5.28 Receive Channel Free Buffer Count Registers (RX0FREEBUFFER-RX7FREEBUFFER) ........
29.5.29 MAC Control Register (MACCONTROL) .................................................................
29.5.30 MAC Status Register (MACSTATUS) .....................................................................
29.5.31 Emulation Control Register (EMCONTROL) .............................................................
29.5.32 FIFO Control Register (FIFOCONTROL) .................................................................
29.5.33 MAC Configuration Register (MACCONFIG) ............................................................
29.5.34 Soft Reset Register (SOFTRESET) .......................................................................
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29.5.35
29.5.36
29.5.37
29.5.38
29.5.39
29.5.40
29.5.41
29.5.42
29.5.43
29.5.44
29.5.45
29.5.46
29.5.47
29.5.48
29.5.49
29.5.50
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Data Modification Module (DMM)....................................................................................... 1733
30.1
30.2
30.3
31
MAC Source Address Low Bytes Register (MACSRCADDRLO) .....................................
MAC Source Address High Bytes Register (MACSRCADDRHI) ......................................
MAC Hash Address Register 1 (MACHASH1) ...........................................................
MAC Hash Address Register 2 (MACHASH2) ...........................................................
Back Off Test Register (BOFFTEST) .....................................................................
Transmit Pacing Algorithm Test Register (TPACETEST) ..............................................
Receive Pause Timer Register (RXPAUSE) .............................................................
Transmit Pause Timer Register (TXPAUSE) ............................................................
MAC Address Low Bytes Register (MACADDRLO) ....................................................
MAC Address High Bytes Register (MACADDRHI) .....................................................
MAC Index Register (MACINDEX) ........................................................................
Transmit Channel DMA Head Descriptor Pointer Registers (TX0HDP-TX7HDP) ..................
Receive Channel DMA Head Descriptor Pointer Registers (RX0HDP-RX7HDP) ..................
Transmit Channel Completion Pointer Registers (TX0CP-TX7CP) ...................................
Receive Channel Completion Pointer Registers (RX0CP-RX7CP) ...................................
Network Statistics Registers ...............................................................................
Overview..................................................................................................................
30.1.1 Features ........................................................................................................
30.1.2 Block Diagram .................................................................................................
Module Operation .......................................................................................................
30.2.1 Data Format ....................................................................................................
30.2.2 Data Port .......................................................................................................
30.2.3 Error Handling .................................................................................................
30.2.4 Interrupts .......................................................................................................
Control Registers ........................................................................................................
30.3.1 DMM Global Control Register (DMMGLBCTRL) ..........................................................
30.3.2 DMM Interrupt Set Register (DMMINTSET) ...............................................................
30.3.3 DMM Interrupt Clear Register (DMMINTCLR) ............................................................
30.3.4 DMM Interrupt Level Register (DMMINTLVL) .............................................................
30.3.5 DMM Interrupt Flag Register (DMMINTFLG) ..............................................................
30.3.6 DMM Interrupt Offset 1 Register (DMMOFF1) ............................................................
30.3.7 DMM Interrupt Offset 2 Register (DMMOFF2) ............................................................
30.3.8 DMM Direct Data Mode Destination Register (DMMDDMDEST) .......................................
30.3.9 DMM Direct Data Mode Blocksize Register (DMMDDMBL) .............................................
30.3.10 DMM Direct Data Mode Pointer Register (DMMDDMPT) ..............................................
30.3.11 DMM Direct Data Mode Interrupt Pointer Register (DMMINTPT) .....................................
30.3.12 DMM Destination x Region 1 (DMMDESTxREG1) ......................................................
30.3.13 DMM Destination x Blocksize 1 (DMMDESTxBL1) .....................................................
30.3.14 DMM Destination x Region 2 (DMMDESTxREG2) ......................................................
30.3.15 DMM Destination x Blocksize 2 (DMMDESTxBL2) .....................................................
30.3.16 DMM Pin Control 0 (DMMPC0) ............................................................................
30.3.17 DMM Pin Control 1 (DMMPC1) ............................................................................
30.3.18 DMM Pin Control 2 (DMMPC2) ............................................................................
30.3.19 DMM Pin Control 3 (DMMPC3) ............................................................................
30.3.20 DMM Pin Control 4 (DMMPC4) ............................................................................
30.3.21 DMM Pin Control 5 (DMMPC5) ............................................................................
30.3.22 DMM Pin Control 6 (DMMPC6) ............................................................................
30.3.23 DMM Pin Control 7 (DMMPC7) ............................................................................
30.3.24 DMM Pin Control 8 (DMMPC8) ............................................................................
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RAM Trace Port (RTP)...................................................................................................... 1779
31.1
Overview.................................................................................................................. 1780
31.1.1 Features ........................................................................................................ 1780
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31.2
31.3
31.4
32
31.1.2 Block Diagram .................................................................................................
Module Operation .......................................................................................................
31.2.1 Trace Mode ....................................................................................................
31.2.2 Direct Data Mode (DDM) .....................................................................................
31.2.3 Trace Regions .................................................................................................
31.2.4 Overflow/Empty Handling ....................................................................................
31.2.5 Signal Description .............................................................................................
31.2.6 Data Rate ......................................................................................................
GIO Function .............................................................................................................
Control Registers ........................................................................................................
31.4.1 RTP Global Control Register (RTPGLBCTRL) ............................................................
31.4.2 RTP Trace Enable Register (RTPTRENA) ................................................................
31.4.3 RTP Global Status Register (RTPGSR)....................................................................
31.4.4 RTP RAM 1 Trace Region [1:2] Register (RTPRAM1REG[1:2]) ........................................
31.4.5 RTP RAM 2 Trace Region [1:2] Register (RTPRAM2REG[1:2]) ........................................
31.4.6 RTP Peripheral Trace Region [1:2] Registers (RTPPERREG[1:2]) ....................................
31.4.7 RTP Direct Data Mode Write Register (RTPDDMW) .....................................................
31.4.8 RTP Pin Control 0 Register (RTPPC0) .....................................................................
31.4.9 RTP Pin Control 1 Register (RTPPC1) .....................................................................
31.4.10 RTP Pin Control 2 Register (RTPPC2) ...................................................................
31.4.11 RTP Pin Control 3 Register (RTPPC3) ...................................................................
31.4.12 RTP Pin Control 4 Register (RTPPC4) ...................................................................
31.4.13 RTP Pin Control 5 Register (RTPPC5) ...................................................................
31.4.14 RTP Pin Control 6 Register (RTPPC6) ...................................................................
31.4.15 RTP Pin Control 7 Register (RTPPC7) ...................................................................
31.4.16 RTP Pin Control 8 Register (RTPPC8) ...................................................................
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1807
eFuse Controller ............................................................................................................. 1808
32.1
32.2
32.3
32.4
Overview..................................................................................................................
Introduction ...............................................................................................................
eFuse Controller Testing ...............................................................................................
32.3.1 eFuse Controller Connections to ESM .....................................................................
32.3.2 Checking for eFuse Errors After Power Up ................................................................
eFuse Controller Registers.............................................................................................
32.4.1 EFC Boundary Control Register (EFCBOUND) ...........................................................
32.4.2 EFC Pins Register (EFCPINS) ..............................................................................
32.4.3 EFC Error Status Register (EFCERRSTAT)...............................................................
32.4.4 EFC Self Test Cycles Register (EFCSTCY) ...............................................................
32.4.5 EFC Self Test Signature Register (EFCSTSIG) ..........................................................
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Revision History ...................................................................................................................... 1817
30
Contents
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List of Figures
1-1.
Block Diagram .............................................................................................................. 96
1-2.
Example: SPIDELAY – 0xFFF7F448 .................................................................................... 97
2-1.
Architectural Block Diagram
2-2.
Memory-Map
2-3.
2-4.
2-5.
2-6.
2-7.
2-8.
2-9.
2-10.
2-11.
2-12.
2-13.
2-14.
2-15.
2-16.
2-17.
2-18.
2-19.
2-20.
2-21.
2-22.
2-23.
2-24.
2-25.
2-26.
2-27.
2-28.
2-29.
2-30.
2-31.
2-32.
2-33.
2-34.
2-35.
2-36.
2-37.
2-38.
2-39.
2-40.
2-41.
2-42.
2-43.
2-44.
2-45.
.............................................................................................. 99
.............................................................................................................. 103
Hardware Memory Initialization Protocol .............................................................................. 113
Clock Test Register (CLKTEST) [offset = FFFF FFF8Ch] .......................................................... 123
EXTCTL_Out_Port Register [offset = 404h] ........................................................................... 124
SYS Pin Control Register 1 (SYSPC1) [offset = 00h] ................................................................ 129
SYS Pin Control Register 2 (SYSPC2) [offset = 04h] ................................................................ 129
SYS Pin Control Register 3 (SYSPC3) [offset = 08h] ................................................................ 130
SYS Pin Control Register 4 (SYSPC4) [offset = 0Ch] ............................................................... 130
SYS Pin Control Register 5 (SYSPC5) [offset = 10h] ................................................................ 131
SYS Pin Control Register 6 (SYSPC6) [offset = 14h] ................................................................ 131
SYS Pin Control Register 7 (SYSPC7) [offset = 18h] ................................................................ 132
SYS Pin Control Register 8 (SYSPC8) [offset = 1Ch] ............................................................... 132
SYS Pin Control Register 9 (SYSPC9) [offset = 20h] ................................................................ 133
Clock Source Disable Register (CSDIS) [offset = 30h] .............................................................. 134
Clock Source Disable Set Register (CSDISSET) [offset = 34h] .................................................... 135
Clock Source Disable Clear Register (CSDISCLR) [offset = 38h] ................................................. 136
Clock Domain Disable Register (CDDIS) [offset = 3Ch] ............................................................. 137
Clock Domain Disable Set Register (CDDISSET) [offset = 40h] ................................................... 139
Clock Domain Disable Clear Register (CDDISCLR) [offset = 44h]................................................. 140
GCLK, HCLK, VCLK, and VCLK2 Source Register (GHVSRC) [offset = 48h] ................................... 143
Peripheral Asynchronous Clock Source Register (VCLKASRC) [offset = 4Ch] .................................. 144
RTI Clock Source Register (RCLKSRC) [offset = 50h] .............................................................. 145
Clock Source Valid Status Register (CSVSTAT) [offset = 54h] .................................................... 146
Memory Self-Test Global Control Register (MSTGCR) [offset = 58h] ............................................. 147
Memory Hardware Initialization Global Control Register (MINITGCR) [offset = 5Ch] ........................... 148
MBIST Controller/Memory Initialization Enable Register (MSINENA) [offset = 60h]............................. 149
MSTC Global Status Register (MSTCGSTAT) [offset = 68h] ....................................................... 150
Memory Hardware Initialization Status Register (MINISTAT) [offset = 6Ch]...................................... 151
PLL Control Register 1 (PLLCTL1) [offset = 70h] .................................................................... 151
PLL Control Register 2 (PLLCTL2) [offset = 74h] .................................................................... 153
SYS Pin Control Register 10 (SYSPC10) [offset = 78h] ............................................................. 154
Die Identification Register, Lower Word (DIEIDL) [offset = 7Ch] ................................................... 155
Die Identification Register, Upper Word (DIEIDH) [offset = 80h] ................................................... 155
LPO/Clock Monitor Control Register (LPOMONCTL) [offset = 88h] ............................................... 156
Clock Test Register (CLKTEST) [offset = 8Ch] ....................................................................... 159
DFT Control Register (DFTCTRLREG) [offset = 90h] ............................................................... 161
DFT Control Register 2 (DFTCTRLREG2) [offset = 94h] ........................................................... 162
General Purpose Register (GPREG1) [offset = A0h] ............................................................... 163
Imprecise Fault Status Register (IMPFASTS) [offset = A8h] ....................................................... 165
Imprecise Fault Write Address Register (IMPFTADD) [offset = ACh] ............................................. 166
System Software Interrupt Request 1 Register (SSIR1) [offset = B0h] ............................................ 167
System Software Interrupt Request 2 Register (SSIR2) [offset = B4h] ............................................ 167
System Software Interrupt Request 3 Register (SSIR3) [offset = B8h] ............................................ 168
System Software Interrupt Request 4 Register (SSIR4) [offset = BCh] ........................................... 168
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2-46.
RAM Control Register (RAMGCR) [offset = C0h] .................................................................... 169
2-47.
Bus Matrix Module Control Register 1 (BMMCR) [offset = C4h] ................................................... 170
2-48.
CPU Reset Control Register (CPURSTCR) [offset = CCh]
2-49.
Clock Control Register (CLKCNTL) [offset = D0h] ................................................................... 172
2-50.
ECP Control Register (ECPCNTL) [offset = D4h] .................................................................... 173
2-51.
DEV Parity Control Register 1 (DEVCR1) [offset = DCh] ........................................................... 174
2-52.
System Exception Control Register (SYSECR) [offset = E0h] ...................................................... 174
2-53.
System Exception Status Register (SYSESR) [offset = E4h]
175
2-54.
System Test Abort Status Register (SYSTASR) [offset = E8h]
176
2-55.
2-56.
2-57.
2-58.
2-59.
2-60.
2-61.
2-62.
2-63.
2-64.
2-65.
2-66.
2-67.
2-68.
2-69.
2-70.
2-71.
2-72.
2-73.
2-74.
2-75.
2-76.
2-77.
2-78.
2-79.
2-80.
2-81.
2-82.
2-83.
2-84.
2-85.
2-86.
2-87.
2-88.
2-89.
2-90.
2-91.
2-92.
3-1.
3-2.
32
........................................................
......................................................
....................................................
Global Status Register (GLBSTAT) [offset = ECh] ...................................................................
Device Identification Register (DEVID) [offset = F0h] ................................................................
Software Interrupt Vector Register (SSIVEC) [offset = F4h] ........................................................
System Software Interrupt Flag Register (SSIF) [offset = F8h] .....................................................
PLL Control Register 3 (PLLCTL3) [offset = 00] ......................................................................
CPU Logic BIST Clock Prescaler (STCLKDIV) [offset = 08h] ......................................................
Clock 2 Control Register (CLK2CNTRL) [offset = 3Ch] .............................................................
Peripheral Asynchronous Clock Configuration 1 Register (VCLKACON1) [offset = 40h] .......................
Clock Slip Register (CLKSLIP) [offset = 70h] ........................................................................
EFUSE Controller Control Register (EFC_CTLREG) [offset = ECh] ..............................................
Die Identification Register, Lower Word (DIEIDL_REG0) [offset = F0h] ..........................................
Die Identification Register, Upper Word (DIEIDH_REG1) [offset = F4h] ..........................................
Die Identification Register, Lower Word (DIEIDL_REG2) [offset = F8h] ..........................................
Die Identification Register, Upper Word (DIEIDH_REG3) [offset = FCh] .........................................
Peripheral Memory Protection Set Register 0 (PMPROTSET0) [offset = 00] ....................................
Peripheral Memory Protection Set Register 1 (PMPROTSET1) [offset = 04h] ...................................
Peripheral Memory Protection Clear Register 0 (PMPROTCLR0) [offset = 10h] ................................
Peripheral Memory Protection Clear Register 1 (PMPROTCLR1) [offset = 14h] ................................
Peripheral Protection Set Register 0 (PPROTSET0) [offset = 20h] ................................................
Peripheral Protection Set Register 1 (PPROTSET1) [offset = 24h] ................................................
Peripheral Protection Set Register 2 (PPROTSET2) [offset = 28h] ................................................
Peripheral Protection Set Register 3 (PPROTSET3) [offset = 2Ch] ...............................................
Peripheral Protection Clear Register 0 (PPROTCLR0) [offset = 40h] .............................................
Peripheral Protection Clear Register 1 (PPROTCLR1) [offset = 44h] .............................................
Peripheral Protection Clear Register 2 (PPROTCLR2) [offset = 48h] .............................................
Peripheral Protection Clear Register 3 (PPROTCLR3) [offset = 4Ch] .............................................
Peripheral Memory Power-Down Set Register 0 (PCSPWRDWNSET0) [offset = 60h] .........................
Peripheral Memory Power-Down Set Register 1 (PCSPWRDWNSET1) [offset = 64h] .........................
Peripheral Memory Power-Down Clear Register 0 (PCSPWRDWNCLR0) [offset = 70h] ......................
Peripheral Memory Power-Down Clear Register 1 (PCSPWRDWNCLR1) [offset = 74h] ......................
Peripheral Power-Down Set Register 0 (PSPWRDWNSET0) [offset = 80h] .....................................
Peripheral Power-Down Set Register 1 (PSPWRDWNSET1) [offset = 84h] .....................................
Peripheral Power-Down Set Register 2 (PSPWRDWNSET2) [offset = 88h] .....................................
Peripheral Power-Down Set Register 3 (PSPWRDWNSET3) [offset = 8Ch] .....................................
Peripheral Power-Down Clear Register 0 (PSPWRDWNCLR0) [offset = A0h]...................................
Peripheral Power-Down Clear Register 1 (PSPWRDWNCLR1) [offset = A4h]...................................
Peripheral Power-Down Clear Register 2 (PSPWRDWNCLR2) [offset = A8h]...................................
Peripheral Power-Down Clear Register 3 (PSPWRDWNCLR) [offset = ACh] ....................................
PMM Block Diagram......................................................................................................
Core Power Domains.....................................................................................................
List of Figures
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178
179
180
182
183
183
184
185
186
186
187
187
188
190
190
191
191
192
193
193
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3-3.
Logic Power Domain Control Register (LOGICPDPWRCTRL0) [offset = 00h] ................................... 212
3-4.
Memory Power Domain Control Register 0 (MEMPDPWRCTRL0) [offset = 10h]
213
3-5.
Power Domain Clock Disable Register (PDCLKDISREG) [offset = 20h]
214
3-6.
3-7.
3-8.
3-9.
3-10.
3-11.
3-12.
3-13.
3-14.
3-15.
3-16.
3-17.
3-18.
3-19.
3-20.
3-21.
3-22.
4-1.
4-2.
4-3.
4-4.
4-5.
4-6.
4-7.
4-8.
4-9.
4-10.
4-11.
4-12.
4-13.
4-14.
4-15.
5-1.
5-2.
5-3.
5-4.
5-5.
5-6.
5-7.
5-8.
5-9.
5-10.
5-11.
5-12.
5-13.
5-14.
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Power Domain Clock Disable Set Register (PDCLKDISSETREG) [offset = 24h] ................................
Power Domain Clock Disable Clear Register (PDCLKDISCLRREG) [offset = 28h] ............................
Logic Power Domain PD2 Power Status Register (LOGICPDPWRSTAT0) [offset = 40h] .....................
Logic Power Domain PD3 Power Status Register (LOGICPDPWRSTAT1) [offset = 44h] .....................
Logic Power Domain PD4 Power Status Register (LOGICPDPWRSTAT2) [offset = 48h] .....................
Logic Power Domain PD5 Power Status Register (LOGICPDPWRSTAT3) [offset = 4Ch] .....................
Memory Power Domain RAM_PD1 Power Status Register (MEMPDPWRSTAT0) [offset = 80h] .............
Memory Power Domain RAM_PD2 Power Status Register (MEMPDPWRSTAT1) [offset = 84h] .............
Memory Power Domain RAM_PD3 Power Status Register (MEMPDPWRSTAT2) [offset = 88h] .............
Global Control Register 1 (GLOBALCTRL1) [offset = A0h] .........................................................
Global Status Register (GLOBALSTAT) [offset = A8h] ..............................................................
PSCON Diagnostic Compare Key Register (PRCKEYREG) [offset = ACh] ......................................
LogicPD PSCON Diagnostic Compare Status Register 1 (LPDDCSTAT1) [offset = B0h] ......................
LogicPD PSCON Diagnostic Compare Status Register 2 (LPDDCSTAT2) [offset = B4h] ......................
Memory PD PSCON Diagnostic Compare Status Register 1 (MPDDCSTAT1) [offset = B8h] ................
Memory PD PSCON Diagnostic Compare Status Register 2 (MPDDCSTAT2) [offset = BCh] ................
Isolation Diagnostic Status Register (ISODIAGSTAT) [offset = C0h] .............................................
PINMMR10 Control Register, Address = FFFF EB38h .............................................................
Output Multiplexing Example ...........................................................................................
Input Multiplexing Example .............................................................................................
REVISION_REG: Revision Register (Address = FFFFEA00h) .....................................................
ENDIAN_REG: Device Endianness Register (Address = FFFFEA20h) ..........................................
KICK_REG0: Kicker Register 0 (Address = FFFFEA38h) ..........................................................
KICK_REG1: Kicker Register 1 (Address = FFFFEA3Ch) ..........................................................
ERR_RAW_STATUS_REG: Error Raw Status / Set Register (Address = FFFFEAE0h) .......................
ERR_ENABLED_STATUS_REG: Error Enabled Status / Clear Register (Address = FFFFEAE4h) .........
ERR_ENABLE_REG: Error Signaling Enable Register (Address = FFFFEAE8h) ..............................
ERR_ENABLE_CLR_REG: Error Signaling Enable Clear Register (Address = FFFFEAECh) ...............
FAULT_ADDRESS_REG: Fault Address Register (Address = FFFFEAF4h) ....................................
FAULT_STATUS_REG: Fault Status Register (Address = FFFFEAF8h) .........................................
FAULT_CLEAR_REG: Fault Clear Register (Address = FFFFEAFCh ) ..........................................
PINMMRnn: Pin Multiplexing Control Registers (Address = FFFFEB10h-FFFFEB88h) ........................
ECC Organization for Program Flash (144-Bits Wide) ..............................................................
TI OTP Bank 0 Sector Information .....................................................................................
TI OTP Bank 0 Package and Memory Size Information (F008 015Ch) ...........................................
TI OTP Bank 0 LPO Trim and Max HCLK Information (F008 01B4h) .............................................
TI OTP Bank 0 Symbolization Information (F008 01E0h-F008 01FFh) ...........................................
TI OTP Bank 0 Deliberate ECC Error Information (F008 03F0h-F008 03FFh) ...................................
Flash Option Control Register (FRDCNTL) [offset = 00h] ..........................................................
Flash Error Detection and Correction Control Register 1 (FEDACCTRL1) [offset = 08h].......................
Flash Error Correction and Correction Control Register 2 (FEDACCTRL2) [offset = 0Ch] .....................
Flash Correctable Error Count Register (FCOR_ERR_CNT) [offset = 10h] ......................................
Flash Correctable Error Address Register (FCOR_ERR_ADD) [offset = 14h] ...................................
Flash Correctable Error Position Register (FCOR_ERR_POS) [offset = 18h] ....................................
Flash Error Detection and Correction Status Register (FEDACSTATUS) [offset = 1Ch] .......................
Flash Uncorrectable Error Address Register (FUNC_ERR_ADD) [offset = 20h] .................................
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Copyright © 2018, Texas Instruments Incorporated
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5-15.
Flash Error Detection and Correction Sector Disable Register (FEDACSDIS) [offset = 24h] .................. 279
5-16.
Primary Address Tag Register (FPRIM_ADD_TAG) [offset = 28h] ................................................ 280
5-17.
Duplicate Address Tag Register (FDUP_ADD_TAG) [offset = 2Ch] ............................................... 280
5-18.
Flash Bank Protection Register (FBPROT) [offset = 30h] ........................................................... 281
5-19.
Flash Bank Sector Enable Register (FBSE) [offset = 34h] .......................................................... 281
5-20.
Flash Bank Busy Register (FBBUSY) [offset = 38h] ................................................................. 282
5-21.
Flash Bank Access Control Register (FBAC) [offset = 3Ch] ........................................................ 283
5-22.
Flash Bank Fallback Power Register (FBFALLBACK) [offset = 40h] .............................................. 284
5-23.
Flash Bank/Pump Ready Register (FBPRDY) [offset = 44h] ....................................................... 285
5-24.
Flash Pump Access Control Register 1 (FPAC1) [offset = 48h] .................................................... 286
5-25.
Flash Pump Access Control Register 2 (FPAC2) [offset = 4Ch] ................................................... 287
5-26.
Flash Module Access Control Register (FMAC) [offset = 50h] ..................................................... 287
5-27.
Flash Module Status Register (FMSTAT) [offset = 54h] ............................................................. 288
5-28.
EEPROM Emulation Data MSW Register (FEMU_DMSW) [offset = 58h] ........................................ 290
5-29.
EEPROM Emulation Data LSW Register (FEMU_DLSW) [offset = 5Ch] ......................................... 290
5-30.
EEPROM Emulation ECC Register (FEMU_ECC) [offset = 60h]
5-31.
5-32.
5-33.
5-34.
5-35.
5-36.
5-37.
5-38.
5-39.
5-40.
5-41.
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5-45.
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5-47.
5-48.
6-1.
6-2.
6-3.
6-4.
6-5.
6-6.
6-7.
6-8.
6-9.
6-10.
6-11.
6-12.
6-13.
7-1.
7-2.
34
..................................................
EEPROM Emulation Address Register (FEMU_ADDR) [offset = 68h] ............................................
Diagnostic Control Register (FDIAGCTRL) [offset = 6Ch] ..........................................................
Uncorrected Raw Data High Register (FRAW_DATAH) [offset = 70h] ............................................
Uncorrected Raw Data Low Register (FRAW_DATAL) [offset = 74h] .............................................
Uncorrected Raw ECC Register (FRAW_ECC) [offset = 78h] ......................................................
Parity Override Register (FPAR_OVR) [offset = 7Ch] ...............................................................
Flash Error Detection and Correction Sector Disable Register (FEDACSDIS2) [offset = C0h] ................
FSM Register Write Enable (FSM_WR_ENA) [offset = 288h] ......................................................
FSM Sector Register (FSM_SECTOR) [offset = 2A4h] ..............................................................
EEPROM Emulation Configuration Register (EEPROM_CONFIG) [offset = 2B8h] .............................
EEPROM Emulation Error Detection and Correction Control Register 1 (EE_CTRL1) [offset = 308h] .......
EEPROM Emulation Error Correction and Correction Control Register 2 (EE_CTRL2) [offset = 30Ch] ......
EEPROM Emulation Error Correctable Error Count Register (EE_COR_ERR_CNT) [offset = 310h].........
EEPROM Emulation Correctable Error Address Register (EE_COR_ERR_ADD) [offset = 314h] ............
EEPROM Emulation Correctable Error Position Register (EE_COR_ERR_POS) [offset = 318h] .............
EEPROM Emulation Error Status Register (EE_STATUS) [offset = 31Ch] .......................................
EEPROM Emulation Uncorrectable Error Address Register (EE_UNC_ERR_ADD) [offset = 320h] ..........
Flash Bank Configuration Register (FCFG_BANK) [offset = 400h] ................................................
TCRAM Module Connections ...........................................................................................
RAM Memory Map ........................................................................................................
TCRAM Module Control Register (RAMCTRL) [offset = 00h] ......................................................
TCRAM Module Single-Bit Error Correction Threshold Register (RAMTHRESHOLD) [offset = 04h] .........
TCRAM Module Single-Bit Error Occurrences Counter Register (RAMOCCUR) [offset = 08h] ...............
TCRAM Module Interrupt Control Register (RAMINTCTRL) [offset = 0Ch] .......................................
TCRAM Module Error Status Register (RAMERRSTATUS) [offset = 10h] .......................................
TCRAM Module Single-Bit Error Address Register (RAMSERRADDR) [offset = 14h] ..........................
TCRAM Module Uncorrectable Error Address Register (RAMUERRADDR) [offset = 1Ch] ....................
TCRAM Module Test Mode Control Register (RAMTEST) [offset = 30h] .........................................
TCRAM Module Test Mode Vector Register (RAMADDRDECVECT) [offset = 38h] ............................
TCRAM Module Parity Error Address Register (RAMPERRADDR) [offset = 3Ch] ..............................
Auto-Memory Initialization Enable Register (INIT_DOMAIN) [offset = 40h].......................................
PBIST Block Diagram ...................................................................................................
PBIST Memory Self-Test Flow Diagram ..............................................................................
List of Figures
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SPNU499C – March 2018
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7-3.
RAM Configuration Register (RAMT) [offset = 0160h] ............................................................... 332
7-4.
Datalogger Register (DLR) [offset = 0164h] ........................................................................... 333
7-5.
PBIST Activate/ROM Clock Enable Register (PACT) [offset = 0180h] ............................................ 334
7-6.
PBIST ID Register [offset = 184h] ...................................................................................... 335
7-7.
Override Register (OVER) [offset = 0188h] ........................................................................... 336
7-8.
Fail Status Fail Register 0 (FSRF0) [offset = 0190h]
7-9.
7-10.
7-11.
7-12.
7-13.
7-14.
7-15.
7-16.
7-17.
7-18.
8-1.
8-2.
8-3.
8-4.
8-5.
8-6.
8-7.
8-8.
8-9.
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8-14.
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8-18.
9-1.
9-2.
9-3.
10-1.
10-2.
10-3.
10-4.
10-5.
10-6.
10-7.
10-8.
10-9.
10-10.
10-11.
10-12.
................................................................
Fail Status Count 0 Register (FSRC0) [offset = 0198h] .............................................................
Fail Status Count Register 1 (FSRC1) [offset = 019Ch] .............................................................
Fail Status Address 0 Register (FSRA0) [offset = 01A0h] ..........................................................
Fail Status Address 1 Register (FSRA1) [offset = 01A4h] ..........................................................
Fail Status Data Register 0 (FSRDL0) [offset = 01A8h] .............................................................
Fail Status Data Register 1 (FSRDL1) [offset = 01B0h] .............................................................
ROM Mask Register (ROM) [offset = 01C0h] .........................................................................
ROM Algorithm Mask Register (ALGO) [offset = 01C4h]............................................................
RAM Info Mask Lower Register (RINFOL) [offset = 01C8h] ........................................................
RAM Info Mask Upper Register (RINFOU) [offset = 01CCh] .......................................................
STC Block Diagram ......................................................................................................
Application Self-Test Flow Chart........................................................................................
STC Global Control Register 0 (STCGCR0) [offset = 00] ...........................................................
STC Global Control Register 1 (STCGCR1) [offset = 04h] .........................................................
Self-Test Run Timeout Counter Preload Register (STCTPR) [offset = 08h] ......................................
STC Current ROM Address Register (STC_CADDR) [offset = 0Ch] ..............................................
STC Current Interval Count Register (STCCICR) [offset = 10h] ...................................................
Self-Test Global Status Register (STCGSTAT) [offset = 14h] ......................................................
Self-Test Fail Status Register (STCFSTAT) [offset = 18h] ..........................................................
CPU1 Current MISR Register (CPU1_CURMISR3) [offset = 1Ch] ................................................
CPU1 Current MISR Register (CPU1_CURMISR2) [offset = 20h] .................................................
CPU1 Current MISR Register (CPU1_CURMISR1) [offset = 24h] .................................................
CPU1 Current MISR Register (CPU1_CURMISR0) [offset = 28h] .................................................
CPU2 Current MISR Register (CPU2_CURMISR3) [offset = 2Ch] ................................................
CPU2 Current MISR Register (CPU2_CURMISR2) [offset = 30h] .................................................
CPU2 Current MISR Register (CPU2_CURMISR1) [offset = 34h] .................................................
CPU2 Current MISR Register (CPU2_CURMISR0) [offset = 38h] .................................................
Signature Compare Self-Check Register (STCSCSCR) [offset = 3Ch] ...........................................
Block Diagram .............................................................................................................
CCM-R4F Status Register (CCMSR) (Address = FFFF F600h)....................................................
CCM-R4F Key Register (CCMKEYR) (Address = FFFF F604h) ...................................................
Clock Path From Oscillator Through PLL To Device.................................................................
Clock Generation Path ...................................................................................................
Oscillator Implementation ................................................................................................
Operation of the FM-PLL Module .......................................................................................
PLL Slip Detection and Reset/Bypass Block Diagram ...............................................................
SSW PLL BIST Control Register 1 (SSWPLL1) [offset = FF24h] ..................................................
SSW PLL BIST Control Register 2 (SSWPLL2) [offset = FF28h] ..................................................
SSW PLL BIST Control Register 3 (SSWPLL3) [offset = FF2Ch] ..................................................
Basic PLL Circuit ..........................................................................................................
PFD Timing ................................................................................................................
PLL Modulation Block Diagram .........................................................................................
Frequency vs. Time ......................................................................................................
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List of Figures
Copyright © 2018, Texas Instruments Incorporated
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11-1.
DCC Operation ............................................................................................................ 397
11-2.
Counter Relationship ..................................................................................................... 399
11-3.
Clock1 Slower Than Clock0 - Results in an Error and Stops Counting ........................................... 399
11-4.
Clock1 Faster Than Clock0 - Results in an Error and Stops Counting ............................................ 400
11-5.
Clock1 Not Present - Results in an Error and Stops Counting ..................................................... 400
11-6.
Clock0 Not Present - Results in an Error and Stops Counting ..................................................... 401
11-7.
DCC Global Control Register (DCCGCTRL) [offset = 00]
404
11-8.
DCC Revision Id Register (DCCREV) [offset = 4h]
405
11-9.
11-10.
11-11.
11-12.
11-13.
11-14.
11-15.
11-16.
11-17.
12-1.
12-2.
12-3.
12-4.
12-5.
12-6.
12-7.
12-8.
12-9.
12-10.
12-11.
12-12.
12-13.
12-14.
12-15.
12-16.
12-17.
12-18.
12-19.
12-20.
12-21.
12-22.
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12-32.
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.................................................................
DCC Counter0 Seed Register (DCCCNT0SEED) [offset = 8h] ....................................................
DCC Valid0 Seed Register (DCCVALID0SEED) [offset = Ch] .....................................................
DCC Counter1 Seed Register (DCCCNT1SEED) [offset = 10h] ..................................................
DCC Status Register (DCCSTAT) [offset = 14h] ....................................................................
DCC Counter0 Value Register (DCCCNT0) [offset = 18h] .........................................................
DCC Valid0 Value Register (DCCVALID0) [offset = 1Ch] ..........................................................
DCC Counter1 Value Register (DCCCNT1) [offset = 20h] .........................................................
DCC Counter1 Clock Source Selection Register (DCCCNT1CLKSRC) [offset = 24h] .........................
DCC Counter0 Clock Source Selection Register (DCCCNT0CLKSRC) [offset = 28h] .........................
Block Diagram .............................................................................................................
Interrupt Response Handling ...........................................................................................
ERROR Pin Response Handling .......................................................................................
ERROR Pin Timing - Example 1 ........................................................................................
ERROR Pin Timing - Example 2 .......................................................................................
ERROR Pin Timing - Example 3 .......................................................................................
ERROR Pin Timing - Example 4 .......................................................................................
ERROR Pin Timing - Example 5 .......................................................................................
ERROR Pin Timing - Example 7 ........................................................................................
ESM Initialization .........................................................................................................
ESM Enable ERROR Pin Action/Response Register 1 (ESMEEPAPR1) [address = FFFF F500h]...........
ESM Disable ERROR Pin Action/Response Register 1 (ESMDEPAPR1) [address = FFFF F504h] ..........
ESM Interrupt Enable Set Register 1 (ESMIESR1) [address = FFFF F508h] ....................................
ESM Interrupt Enable Clear Register 1 (ESMIECR1) [address = FFFF F50Ch] .................................
ESM Interrupt Level Set Register 1 (ESMILSR1) [address = FFFF F510h] ......................................
ESM Interrupt Level Clear Register 1 (ESMILCR1) [address = FFFF F514h] ....................................
ESM Status Register 1 (ESMSR1) [address = FFFF F518h] .......................................................
ESM Status Register 2 (ESMSR2) [address = FFFF F51Ch] ......................................................
ESM Status Register 3 (ESMSR3) [address = FFFF F520h] .......................................................
ESM ERROR Pin Status Register (ESMEPSR) [address = FFFF F524h] ........................................
ESM Interrupt Offset High Register (ESMIOFFHR) [address = FFFF F528h] ....................................
ESM Interrupt Offset Low Register (ESMIOFFLR) [address = FFFF F52Ch] ....................................
ESM Low-Time Counter Register (ESMLTCR) [address = FFFF F530h] .........................................
ESM Low-Time Counter Preload Register (ESMLTCPR) [address = FFFF F534h] .............................
ESM Error Key Register (ESMEKR) [address = FFFF F538h] .....................................................
ESM Status Shadow Register 2 (ESMSSR2) [address = FFFF F53Ch] ..........................................
ESM Influence ERROR Pin Set Register 4 (ESMIEPSR4) [address = FFFF F540h] ...........................
ESM Influence ERROR Pin Clear Register 4 (ESMIEPCR4) [address = FFFF F544h] .........................
ESM Interrupt Enable Set Register 4 (ESMIESR4) [address = FFFF F548h] ....................................
ESM Interrupt Enable Clear Register 4 (ESMIECR4) [address = FFFF F54Ch] .................................
ESM Interrupt Level Set Register 4 (ESMILSR4) [address = FFFF F550h] ......................................
ESM Interrupt Level Clear Register 4 (ESMILCR4) [address = FFFF F554h] ....................................
List of Figures
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12-33. ESM Status Register 4 (ESMSR4) [address = FFFF F558h] ....................................................... 433
13-1.
RTI Block Diagram........................................................................................................ 436
13-2.
Counter Block Diagram .................................................................................................. 437
13-3.
Compare Unit Block Diagram (shows only 1 of 4 blocks for simplification) ....................................... 439
13-4.
Timebase Control ......................................................................................................... 440
13-5.
Clock Detection Scheme ................................................................................................. 440
13-6.
Switch to NTUx............................................................................................................ 441
13-7.
Missing NTUx Signal Example .......................................................................................... 442
13-8.
Digital Watchdog .......................................................................................................... 442
13-9.
DWD Operation ........................................................................................................... 443
13-10. Digital Windowed Watchdog Timing Example ........................................................................ 444
13-11. Digital Windowed Watchdog Operation Example (25% Window) .................................................. 444
13-12. RTI Global Control Register (RTIGCTRL) [offset = 00] .............................................................. 447
13-13. RTI Timebase Control Register (RTITBCTRL) [offset = 04h] ....................................................... 448
13-14. RTI Capture Control Register (RTICAPCTRL) [offset = 08h] ....................................................... 449
13-15. RTI Compare Control Register (RTICOMPCTRL) [offset = 0Ch]................................................... 450
13-16. RTI Free Running Counter 0 Register (RTIFRC0) [offset = 10h]................................................... 451
13-17. RTI Up Counter 0 Register (RTIUC0) [offset = 14h] ................................................................. 451
.................................................
RTI Capture Free Running Counter 0 Register (RTICAFRC0) [offset = 20h] ....................................
RTI Capture Up Counter 0 Register (RTICAUC0) [offset = 24h] ...................................................
RTI Free Running Counter 1 Register (RTIFRC1) [offset = 30h]...................................................
RTI Up Counter 1 Register (RTIUC1) [offset = 34h] .................................................................
RTI Compare Up Counter 1 Register (RTICPUC1) [offset = 38h] .................................................
RTI Capture Free Running Counter 1 Register (RTICAFRC1) [offset = 40h] ....................................
RTI Capture Up Counter 1 Register (RTICAUC1) [offset = 44h] ...................................................
RTI Compare 0 Register (RTICOMP0) [offset = 50h] ................................................................
RTI Update Compare 0 Register (RTIUDCP0) [offset = 54h] .......................................................
RTI Compare 1 Register (RTICOMP1) [offset = 58h] ................................................................
RTI Update Compare 1 Register (RTIUDCP1) [offset = 5Ch] ......................................................
RTI Compare 2 Register (RTICOMP2) [offset = 60h] ................................................................
RTI Update Compare 2 Register (RTIUDCP2) [offset = 64h] .......................................................
RTI Compare 3 Register (RTICOMP3) [offset = 68h] ................................................................
RTI Update Compare 3 Register (RTIUDCP3) [offset = 6Ch] ......................................................
RTI Timebase Low Compare Register (RTITBLCOMP) [offset = 70h] ............................................
RTI Timebase High Compare Register (RTITBHCOMP) [offset = 74h] ...........................................
RTI Set Interrupt Control Register (RTISETINTENA) [offset = 80h] ...............................................
RTI Clear Interrupt Control Register (RTICLEARINTENA) [offset = 84h] .........................................
RTI Interrupt Flag Register (RTIINTFLAG) [offset = 88h] ...........................................................
Digital Watchdog Control Register (RTIDWDCTRL) [offset = 90h] ................................................
Digital Watchdog Preload Register (RTIDWDPRLD) [offset = 94h] ................................................
Watchdog Status Register (RTIWDSTATUS) [offset = 98h] ........................................................
RTI Watchdog Key Register (RTIDWDKEY) [offset = 9Ch] .........................................................
RTI Watchdog Down Counter Register (RTIDWDCNTR) [offset = A0h] ..........................................
Digital Windowed Watchdog Reaction Control (RTIWWDRXNCTRL) [offset = A4h] ............................
Digital Windowed Watchdog Window Size Control (RTIWWDSIZECTRL) [offset = A8h].......................
RTI Compare Interrupt Clear Enable Register (RTIINTCLRENABLE) [offset = ACh] ...........................
RTI Compare 0 Clear Register (RTICMP0CLR) [offset = B0h] .....................................................
RTI Compare 1 Clear Register (RTICMP1CLR) [offset = B4h] .....................................................
13-18. RTI Compare Up Counter 0 Register (RTICPUC0) [offset = 18h]
452
13-19.
452
13-20.
13-21.
13-22.
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13-24.
13-25.
13-26.
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13-31.
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13-33.
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13-35.
13-36.
13-37.
13-38.
13-39.
13-40.
13-41.
13-42.
13-43.
13-44.
13-45.
13-46.
13-47.
13-48.
SPNU499C – March 2018
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List of Figures
Copyright © 2018, Texas Instruments Incorporated
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13-49. RTI Compare 2 Clear Register (RTICMP2CLR) [offset = B8h] ..................................................... 475
475
14-1.
478
14-2.
14-3.
14-4.
14-5.
14-6.
14-7.
14-8.
14-9.
14-10.
14-11.
14-12.
14-13.
14-14.
14-15.
14-16.
14-17.
14-18.
14-19.
14-20.
14-21.
14-22.
14-23.
14-24.
14-25.
14-26.
14-27.
14-28.
14-29.
14-30.
14-31.
14-32.
14-33.
14-34.
14-35.
14-36.
14-37.
14-38.
14-39.
14-40.
14-41.
14-42.
14-43.
15-1.
15-2.
15-3.
15-4.
38
....................................................
...................................................................
LFSR .......................................................................................................................
AUTO Mode Using Hardware Timer Trigger .........................................................................
AUTO Mode With Software CPU Trigger .............................................................................
Semi-CPU Mode With Hardware Timer Trigger ......................................................................
Timeout Example 1 ......................................................................................................
Timeout Example 2 ......................................................................................................
Timeout Example 3 ......................................................................................................
CRC Global Control Register 0 (CRC_CTRL0) [offset = 00h] ......................................................
CRC Global Control Register 1 (CRC_CTRL1) [offset = 08h] ......................................................
CRC Global Control Register 2 (CRC_CTRL2) [offset = 10h] ......................................................
CRC Interrupt Enable Set Register (CRC_INTS) [offset = 18h] ....................................................
CRC Interrupt Enable Reset Register (CRC_INTR) [offset = 20h] .................................................
CRC Interrupt Status Register (CRC_STATUS) [offset = 28h] .....................................................
CRC Interrupt Offset (CRC_INT_OFFSET_REG) [offset = 30h] ...................................................
CRC Busy Register (CRC_BUSY) [offset = 38h] .....................................................................
CRC Pattern Counter Preload Register 1 (CRC_PCOUNT_REG1) [offset = 40h] ..............................
CRC Sector Counter Preload Register 1 (CRC_SCOUNT_REG1) [offset = 44h] ...............................
CRC Current Sector Preload Register 1 (CRC_CURSEC_REG1) [offset = 48h] ................................
CRC Channel 1 Watchdog Timeout Preload Register A (CRC_WDTOPLD1) [offset = 4Ch] ..................
CRC Channel 1 Block Complete Timeout Preload Register B (CRC_BCTOPLD1) [offset = 50h].............
Channel 1 PSA Signature Low Register (PSA_SIGREGL1) [offset = 60h] .......................................
Channel 1 PSA Signature High Register (PSA_SIGREGH1) [offset = 64h] ......................................
Channel 1 CRC Value Low Register (CRC_REGL1) [offset = 68h]................................................
Channel 1 CRC Value High Register (CRC_REGH1) [offset = 6Ch] ..............................................
Channel 1 PSA Sector Signature Low Register (PSA_SECSIGREGL1) [offset = 70h] .........................
Channel 1 PSA Sector Signature High Register (PSA_SECSIGREGH1) [offset = 74h] ........................
Channel 1 Raw Data Low Register (RAW_DATAREGL1) [offset = 78h]..........................................
Channel 1 Raw Data High Register (RAW_DATAREGH1) [offset = 7Ch] ........................................
CRC Pattern Counter Preload Register 2 (CRC_PCOUNT_REG2) [offset = 80h] ..............................
CRC Sector Counter Preload Register 2 (CRC_SCOUNT_REG2) [offset = 84h] ...............................
CRC Current Sector Register 2 (CRC_CURSEC_REG2) [offset = 88h] ..........................................
CRC Channel 2 Watchdog Timeout Preload Register A (CRC_WDTOPLD2) [offset = 8Ch] ..................
CRC Channel 2 Block Complete Timeout Preload Register B (CRC_BCTOPLD2) [offset = 90h].............
Channel 2 PSA Signature Low Register (PSA_SIGREGL2) [offset = A0h] .......................................
Channel 2 PSA Signature High Register (PSA_SIGREGH2) [offset = A4h] ......................................
Channel 2 CRC Value Low Register (CRC_REGL2) [offset = A8h] ...............................................
Channel 2 CRC Value High Register (CRC_REGH2) [offset = ACh] ..............................................
Channel 2 PSA Sector Signature Low Register (PSA_SECSIGREGL2) [offset = B0h] .........................
Channel 2 PSA Sector Signature High Register (PSA_SECSIGREGH2) [offset = B4h] ........................
Channel 2 Raw Data Low Register (RAW_DATAREGL2) [offset = B8h] .........................................
Channel 2 Raw Data High Register (RAW_DATAREGH2) [offset = BCh] ........................................
Data Bus Selection Register (CRC_TRACE_BUS_SEL) [offset = 140h]..........................................
Device Level Interrupt Block Diagram .................................................................................
VIM Interrupt Handling Block Diagram .................................................................................
VIM Channel Mapping ...................................................................................................
VIM in Default State ......................................................................................................
13-50. RTI Compare 3 Clear Register (RTICMP3CLR) [offset = BCh]
CRC Controller Block Diagram For One Channel
List of Figures
480
483
483
484
486
487
487
494
494
495
496
498
500
502
503
503
504
504
505
505
506
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510
511
511
511
512
512
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513
514
516
519
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521
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15-5.
VIM in a Programmed State ............................................................................................. 521
15-6.
Interrupt Channel Management ......................................................................................... 522
15-7.
VIM Interrupt Address Memory Map ................................................................................... 523
15-8.
Parity Bit Mapping ........................................................................................................ 525
15-9.
Detail of the IRQ Input
...................................................................................................
526
15-10. Capture Event Sources .................................................................................................. 527
15-11. Interrupt Vector Table Parity Flag Register (PARFLG) [offset = ECh] ............................................. 531
15-12. Interrupt Vector Table Parity Control Register (PARCTL) [offset = F0h] .......................................... 531
15-13. Address Parity Error Register (ADDERR) [offset = F4h] ............................................................ 532
15-14. Fall-Back Address Parity Error Register (FBPARERR) [offset = F8h] ............................................. 532
......................................................
FIQ Index Offset Vector Register (FIQINDEX) [offset = 04h] .......................................................
FIQ/IRQ Program Control Register 0 (FIRQPR0) [offset = 10h] ...................................................
FIQ/IRQ Program Control Register 1 (FIRQPR1) [offset = 14h] ...................................................
FIQ/IRQ Program Control Register 2 (FIRQPR2) [offset = 18h] ...................................................
Pending Interrupt Read Location Register 0 (INTREQ0) [offset = 20h] ...........................................
Pending Interrupt Read Location Register 1 (INTREQ1) Register [offset = 24h] ................................
Pending Interrupt Read Location Register 2 (INTREQ2) Register [offset = 28h] ................................
Interrupt Enable Set Register 0 (REQENASET0) [offset = 30h] ....................................................
Interrupt Enable Set Register 1 (REQENASET1) [offset = 34h] ....................................................
Interrupt Enable Set Register 2 (REQENASET2) [offset = 38h] ....................................................
Interrupt Enable Clear Register 0 (REQENACLR0) [offset = 40h] .................................................
Interrupt Enable Clear Register 1 (REQENACLR1) [offset = 44h] .................................................
Interrupt Enable Clear Register 2 (REQENACLR2) [offset = 48h] .................................................
Wake-Up Enable Set Register 0 (WAKEENASET0) [offset = 50h] ................................................
Wake-Up Enable Set Register 1 (WAKEENASET1) [offset = 54h] ................................................
Wake-Up Enable Set Register 2 (WAKEENASET2) [offset = 58h] ................................................
Wake-Up Enable Clear Register 0 (WAKEENACLR0) [offset = 60h] ..............................................
Wake-Up Enable Clear Register 1 (WAKEENACLR1) [offset = 64h] ..............................................
Wake-Up Enable Clear Register 2 (WAKEENACLR2) [offset = 68h] ..............................................
IRQ Interrupt Vector Register (IRQVECREG) [offset = 70h] ........................................................
IRQ Interrupt Vector Register (FIQVECREG) [offset = 74h] ........................................................
Capture Event Register (CAPEVT) [offset = 78h] ....................................................................
Interrupt Control Registers (CHANCTRL[0:23]) [offset = 80h-DCh]................................................
DMA Block Diagram ......................................................................................................
Example of a DMA Transfer Using Frame Trigger Source ..........................................................
Example of a DMA Transfer Using Block Trigger Source ...........................................................
DMA Request Mapping and Control Packet Organization ..........................................................
Control Packet Organization and Memory Map ......................................................................
DMA Transfer Example 1 ................................................................................................
DMA Indexing Example 1 ................................................................................................
DMA Indexing Example 2 ................................................................................................
Fixed Priority Scheme ....................................................................................................
Example of Priority Queues .............................................................................................
Example Channel Assignments .........................................................................................
Example of DMA Data Unpacking ......................................................................................
Example of DMA Data Packing .........................................................................................
DMA Interrupts ............................................................................................................
Detailed Interrupt Structure (Frame Transfer Complete Path) ......................................................
15-15. IRQ Index Offset Vector Register (IRQINDEX) [offset = 00h]
534
15-16.
534
15-17.
15-18.
15-19.
15-20.
15-21.
15-22.
15-23.
15-24.
15-25.
15-26.
15-27.
15-28.
15-29.
15-30.
15-31.
15-32.
15-33.
15-34.
15-35.
15-36.
15-37.
15-38.
16-1.
16-2.
16-3.
16-4.
16-5.
16-6.
16-7.
16-8.
16-9.
16-10.
16-11.
16-12.
16-13.
16-14.
16-15.
SPNU499C – March 2018
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List of Figures
Copyright © 2018, Texas Instruments Incorporated
535
535
535
536
536
536
537
537
537
538
538
538
539
539
539
540
540
540
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541
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551
551
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555
556
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560
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563
16-17.
564
16-18.
16-19.
16-20.
16-21.
16-22.
16-23.
16-24.
16-25.
16-26.
16-27.
16-28.
16-29.
16-30.
16-31.
16-32.
16-33.
16-34.
16-35.
16-36.
16-37.
16-38.
16-39.
16-40.
16-41.
16-42.
16-43.
16-44.
16-45.
16-46.
16-47.
16-48.
16-49.
16-50.
16-51.
16-52.
16-53.
16-54.
16-55.
16-56.
16-57.
16-58.
16-59.
16-60.
16-61.
16-62.
16-63.
16-64.
40
..........................................................................................
Example of Protection Mechanism .....................................................................................
Global Control Register (GCTRL) [offset = 00] .......................................................................
Channel Pending Register (PEND) [offset = 04h] ....................................................................
DMA Status Register (DMASTAT) [offset = 0Ch] ....................................................................
HW Channel Enable Set and Status Register (HWCHENAS) [offset = 14h] .....................................
HW Channel Enable Reset and Status Register (HWCHENAR) [offset = 1Ch] ..................................
SW Channel Enable Set and Status Register (SWCHENAS) [offset = 24h]......................................
SW Channel Enable Reset and Status Register (SWCHENAR) [offset = 2Ch] ..................................
Channel Priority Set Register (CHPRIOS) [offset = 34h] ............................................................
Channel Priority Reset Register (CHPRIOR) [offset = 3Ch] ........................................................
Global Channel Interrupt Enable Set Register (GCHIENAS) [offset = 44h].......................................
Global Channel Interrupt Enable Reset Register (GCHIENAR) [offset = 4Ch] ...................................
DMA Request Assignment Register 0 (DREQASI0) [offset = 54h] ................................................
DMA Request Assignment Register 1 (DREQASI1) [offset = 58h] ................................................
DMA Request Assignment Register 2 (DREQASI2) [offset = 5Ch] ................................................
DMA Request Assignment Register 3 (DREQASI3) [offset = 60h] ................................................
Port Assignment Register 0 (PAR0) [offset = 94h] ...................................................................
Port Assignment Register 1 (PAR1) [offset = 98h] ...................................................................
FTC Interrupt Mapping Register (FTCMAP) [offset = B4h]..........................................................
LFS Interrupt Mapping Register (LFSMAP) [offset = BCh] ..........................................................
HBC Interrupt Mapping Register (HBCMAP) [offset = C4h].........................................................
BTC Interrupt Mapping Register (BTCMAP) [offset = CCh] .........................................................
FTC Interrupt Enable Set (FTCINTENAS) [offset = DCh] ...........................................................
FTC Interrupt Enable Reset (FTCINTENAR) [offset = E4h].........................................................
LFS Interrupt Enable Set (LFSINTENAS) [offset = ECh] ............................................................
LFS Interrupt Enable Reset (LFSINTENAR) [offset = F4h] .........................................................
HBC Interrupt Enable Set (HBCINTENAS) [offset = FCh] ..........................................................
HBC Interrupt Enable Reset (HBCINTENAR) [offset = 104h] ......................................................
BTC Interrupt Enable Set (BTCINTENAS) [offset = 10Ch] ..........................................................
BTC Interrupt Enable Reset (BTCINTENAR) [offset = 114h] .......................................................
Global Interrupt Flag Register (GINTFLAG) [offset = 11Ch] ........................................................
FTC Interrupt Flag Register (FTCFLAG) [offset = 124h] ............................................................
LFS Interrupt Flag Register (LFSFLAG) [offset = 12Ch] ............................................................
HBC Interrupt Flag Register (HBCFLAG) [offset = 134h] ...........................................................
BTC Interrupt Flag Register (BTCFLAG) [offset = 13Ch]............................................................
FTCA Interrupt Channel Offset Register (FTCAOFFSET) [offset = 14Ch] ........................................
LFSA Interrupt Channel Offset Register (LFSAOFFSET) [offset = 150h] .........................................
HBCA Interrupt Channel Offset Register (HBCAOFFSET) [offset = 154h] .......................................
BTCA Interrupt Channel Offset Register (BTCAOFFSET) [offset = 158h] ........................................
FTCB Interrupt Channel Offset Register (FTCBOFFSET) [offset = 160h] ........................................
LFSB Interrupt Channel Offset Register (LFSBOFFSET) [offset = 164h] .........................................
HBCB Interrupt Channel Offset Register (HBCBOFFSET) [offset = 168h] .......................................
BTCB Interrupt Channel Offset Register (BTCBOFFSET) [offset = 16Ch]........................................
Port Control Register (PTCRL) [offset = 178h] .......................................................................
RAM Test Control (RTCTRL) [offset = 17Ch] .........................................................................
Debug Control (DCTRL) [offset = 180h] ...............................................................................
Watch Point Register (WPR) [offset = 184h] ..........................................................................
Watch Mask Register (WMR) [offset = 188h] .........................................................................
16-16. Example of Channel Chaining
List of Figures
568
569
569
570
570
571
572
572
573
573
574
575
576
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578
579
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581
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596
596
598
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600
601
601
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16-65. Port B Active Channel Source Address Register (PBACDADDR) [offset = 198h] ............................... 602
16-66. Port B Active Channel Destination Address Register (PBACDADDR) [offset = 19Ch] .......................... 602
16-67. Port B Active Channel Transfer Count Register (PBACTC) [offset = 1A0h] ...................................... 603
..................................................................
DMA Parity Error Address Register (DMAPAR) [offset = 1ACh] ...................................................
DMA Memory Protection Control Register (DMAMPCTRL) [offset = 1B0h] ......................................
DMA Memory Protection Status Register (DMAMPST) [offset = 1B4h] ...........................................
DMA Memory Protection Region 0 Start Address Register (DMAMPR0S) [offset = 1B8h] .....................
DMA Memory Protection Region 0 End Address Register (DMAMPR0E) [offset = 1BCh] .....................
DMA Memory Protection Region 1 Start Address Register (DMAMPR1S) [offset = 1C0h].....................
DMA Memory Protection Region 1 End Address Register (DMAMPR1E) [offset = 1C4h] .....................
DMA Memory Protection Region 2 Start Address Register (DMAMPR2S) [offset = 1C8h].....................
DMA Memory Protection Region 2 End Address Register (DMAMPR2E) [offset = 1CCh] .....................
DMA Memory Protection Region 3 Start Address Register (DMAMPR3S) [offset = 1D0h].....................
DMA Memory Protection Region 3 End Address Register (DMAMPR3E) [offset = 1D4h] .....................
Initial Source Address (ISADDR) [offset = 00] ........................................................................
Initial Destination Address Register (IDADDR) [offset = 04h].......................................................
Initial Transfer Count Register (ITCOUNT) [offset = 08h] ...........................................................
Channel Control Register (CHCTRL) [offset = 10h] ..................................................................
Element Index Offset Register (EIOFF) [offset = 14h] ...............................................................
Frame Index Offset Register (FIOFF) [offset = 18h] .................................................................
Current Source Address Register (CSADDR) [offset = 800h] ......................................................
Current Destination Address Register (CDADDR) [offset = 804h] .................................................
Current Transfer Count Register (CTCOUNT) [offset = 808h] ......................................................
EMIF Functional Block Diagram ........................................................................................
Timing Waveform of SDRAM PRE Command ........................................................................
EMIF to 2M × 16 × 4 bank SDRAM Interface .........................................................................
EMIF to 512K × 16 × 2 bank SDRAM Interface ......................................................................
Timing Waveform for Basic SDRAM Read Operation ...............................................................
Timing Waveform for Basic SDRAM Write Operation ...............................................................
EMIF Asynchronous Interface ...........................................................................................
EMIF to 8-bit/16-bit Memory Interface .................................................................................
Common Asynchronous Interface ......................................................................................
Timing Waveform of an Asynchronous Read Cycle in Normal Mode..............................................
Timing Waveform of an Asynchronous Write Cycle in Normal Mode ..............................................
Timing Waveform of an Asynchronous Read Cycle in Select Strobe Mode ......................................
Timing Waveform of an Asynchronous Write Cycle in Select Strobe Mode ......................................
Asynchronous Read in Page Mode ....................................................................................
Module ID Register (MIDR) [offset = 00] ..............................................................................
Asynchronous Wait Cycle Configuration Register (AWCCR) [offset = 04h] ......................................
SDRAM Configuration Register (SDCR) [offset = 08h] ..............................................................
SDRAM Refresh Control Register (SDRCR) [offset = 0Ch] .........................................................
Asynchronous n Configuration Register (CEnCFG) [offset = 10h - 1Ch]..........................................
SDRAM Timing Register (SDTIMR) [offset = 20h] ...................................................................
SDRAM Self Refresh Exit Timing Register (SDSRETR) [offset = 3Ch] ...........................................
EMIF Interrupt Raw Register (INTRAW) [offset = 40h] ..............................................................
EMIF Interrupt Mask Register (INTMSK) [offset = 44h] .............................................................
EMIF Interrupt Mask Set Register (INTMSKSET) [offset = 48h] ...................................................
EMIF Interrupt Mask Clear Register (INTMSKCLR) [offset = 4Ch] ................................................
16-68. Parity Control Register (DMAPCR) [offset = 1A8h]
604
16-69.
605
16-70.
16-71.
16-72.
16-73.
16-74.
16-75.
16-76.
16-77.
16-78.
16-79.
16-80.
16-81.
16-82.
16-83.
16-84.
16-85.
16-86.
16-87.
16-88.
17-1.
17-2.
17-3.
17-4.
17-5.
17-6.
17-7.
17-8.
17-9.
17-10.
17-11.
17-12.
17-13.
17-14.
17-15.
17-16.
17-17.
17-18.
17-19.
17-20.
17-21.
17-22.
17-23.
17-24.
17-25.
SPNU499C – March 2018
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List of Figures
Copyright © 2018, Texas Instruments Incorporated
606
608
609
609
610
610
611
611
612
612
613
613
614
614
616
616
617
617
618
621
625
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17-26. Page Mode Control Register (PMCR) [offset = 68h] ................................................................. 665
17-27. Example Configuration Interface ........................................................................................ 667
17-28. SDRAM Timing Register (SDTIMR) .................................................................................... 668
17-29. SDRAM Self Refresh Exit Timing Register (SDSRETR) ............................................................ 669
17-30. SDRAM Refresh Control Register (SDRCR) .......................................................................... 670
17-31. SDRAM Configuration Register (SDCR)............................................................................... 671
17-32. LH28F800BJE-PTTL90 to EMIF Read Timing Waveforms ......................................................... 672
.........................................................
........................................
System Overlay Block Diagram .........................................................................................
Region Definition Example ..............................................................................................
POM Global Control Register (POMGLBCTRL) [address = FFA0 4000h] ........................................
POM Revision ID (POMREV) [address = FFA0 4004h] .............................................................
POM Clock Gate Control Register [address = FFA0 4008h]........................................................
POM Status Register [address = FFA0 400Ch] ......................................................................
17-33. LH28F800BJE-PTTL90 to EMIF Write Timing Waveforms
673
17-34. Asynchronous m Configuration Register (m = 1, 2) (CEnCFG (n = 2, 3))
674
18-1.
18-2.
18-3.
18-4.
18-5.
18-6.
677
678
680
681
681
682
18-7.
POM Program Region Start Register x (POMPROGSTARTx) [address = FFA0 4200h, FFA0 4210h, ...,
FFA0 43F0h] .............................................................................................................. 683
18-8.
POM Overlay Region Start Register x (POMOVLSTARTx) [address = FFA0 4204h, FFA0 4214h, ...,
FFA0 43F4h] .............................................................................................................. 683
18-9.
POM Region Size Register x (POMREGSIZEx) [address = FFA0 4208h, FFA0 4218h, ..., FFA0 43F8h] ... 684
18-10. POM Integration Control Register (POMITCTRL) [address = FFA0 4F00h] ...................................... 684
18-11. POM Claim Set Register (POMCLAIMSET) [address = FFA0 4FA0h] ............................................ 685
686
18-13.
687
18-14.
18-15.
18-16.
18-17.
18-18.
18-19.
18-20.
18-21.
18-22.
18-23.
18-24.
18-25.
18-26.
18-27.
18-28.
18-29.
19-1.
19-2.
19-3.
19-4.
19-5.
19-6.
19-7.
19-8.
19-9.
42
.........................................
POM Lock Access Register (POMLOCKACCESS) [address = FFA0 4FB0h] ....................................
POM Lock Status Register (POMLOCKSTATUS) [address = FFA0 4FB4h] .....................................
POM Authentication Status Register (POMAUTHSTATUS) [address = FFA0 4FB8h] ..........................
POM Device ID Register (POMDEVID) [address = FFA0 4FC8h] .................................................
POM Device Type Register (POMDEVTYPE) [address = FFA0 4FCCh] .........................................
POM Peripheral ID 4 Register (POMPERIPHERALID4) [address = FFA0 4FD0h] ..............................
POM Peripheral ID 5 Register (POMPERIPHERALID5) [address = FFA0 4FD4h] ..............................
POM Peripheral ID 6 Register (POMPERIPHERALID6) [address = FFA0 4FD8h] ..............................
POM Peripheral ID 7 Register (POMPERIPHERALID7) [address = FFA0 4FDCh] .............................
POM Peripheral ID 0 Register (POMPERIPHERALID0) [address = FFA0 4FE0h] ..............................
POM Peripheral ID 1 Register (POMPERIPHERALID1) [address = FFA0 4FE4] ...............................
POM Peripheral ID 2 Register (POMPERIPHERALID2) [address = FFA0 4FE8h] ..............................
POM Peripheral ID 3 Register (POMPERIPHERALID3) [address = FFA0 4FECh] .............................
POM Component ID 0 Register (POMCOMPONENTID0) [address = FFA0 4FF0h] ............................
POM Component ID 1 Register (POMCPOMPONENTID1) [address = FFA0 4FF4h] ..........................
POM Component ID 2 Register (POMCPOMPONENTID2) [address = FFA0 4FF8h] ..........................
POM Component ID 3 Register (POMCPOMPONENTID3) [address = FFA0 4FFCh] ..........................
Channel Assignments of Two ADC Cores ............................................................................
ADC Block Diagram ......................................................................................................
FIFO Implementation .....................................................................................................
Format of Conversion Result Read from FIFO, 12-bit ADC.........................................................
Format of Conversion Result Read from FIFO, 10-bit ADC.........................................................
ADC Memory Mapping ...................................................................................................
Format of Conversion Result Directly Read from ADC RAM, 12-bit ADC ........................................
Format of Conversion Result Directly Read from ADC RAM, 10-bit ADC ........................................
Conversion Results Storage.............................................................................................
18-12. POM Claim Clear Register (POMCLAIMCLR) [address = FFA0 4FA4h]
List of Figures
687
687
688
688
689
689
690
690
691
691
692
692
693
693
694
694
696
697
702
702
703
703
704
704
705
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19-10. ADC Groups’ Operating Mode Control and Status Registers ....................................................... 706
19-11. Self-Test and Calibration Logic ......................................................................................... 713
19-12. Mid-point Value Calculation
.............................................................................................
716
19-13. Self-Test and Calibration Logic ......................................................................................... 717
19-14. Timing for Self-Test Mode ............................................................................................... 718
.......................................................................
ADC Memory Map in Parity Test Mode ................................................................................
GPIO Functionality of ADxEVT .........................................................................................
ADC Reset Control Register (ADRSTCR) [offset = 00h] ............................................................
ADC Operating Mode Control Register (ADOPMODECR) [offset = 04h] .........................................
ADC Clock Control Register (ADCLOCKCR) [offset = 08h].........................................................
ADC Calibration Mode Control Register (ADCALCR) [offset = 0Ch] ..............................................
12-bit ADC Event Group Operating Mode Control Register (ADEVMODECR) [offset = 10h] ..................
10-bit ADC Event Group Operating Mode Control Register (ADEVMODECR) [offset = 10h] ..................
12-bit ADC Group1 Operating Mode Control Register (ADG1MODECR) [offset = 14h] ........................
10-bit ADC Group1 Operating Mode Control Register (ADG1MODECR) [offset = 14h] ........................
12-bit ADC Group2 Operating Mode Control Register (ADG2MODECR) [offset = 18h] ........................
10-bit ADC Group2 Operating Mode Control Register (ADG2MODECR) [offset = 18h] ........................
ADC Event Group Trigger Source Select Register (ADEVSRC) [offset = 1Ch] ..................................
ADC Group1 Trigger Source Select Register (ADG1SRC) [offset = 20h] .........................................
ADC Group2 Trigger Source Select Register (ADG2SRC) [offset = 24h] .........................................
ADC Event Group Interrupt Enable Control Register (ADEVINTENA) [offset = 28h] ............................
ADC Group1 Interrupt Enable Control Register (ADG1INTENA) [offset = 2Ch] .................................
ADC Group2 Interrupt Enable Control Register (ADG2INTENA) [offset = 30h] ..................................
ADC Event Group Interrupt Flag Register (ADEVINTFLG) [offset = 34h] .........................................
ADC Group1 Interrupt Flag Register (ADG1INTFLG) [offset = 38h] ...............................................
ADC Group2 Interrupt Flag Register (ADG2INTFLG) [offset = 3Ch] ..............................................
ADC Event Group Threshold Interrupt Control Register (ADEVTHRINTCR) [offset = 40h] ....................
ADC Group1 Threshold Interrupt Control Register (ADG1THRINTCR) [offset = 44h] ..........................
ADC Group2 Threshold Interrupt Control Register (ADG2THRINTCR) [offset = 48h] ..........................
ADC Event Group DMA Control Register (ADEVDMACR) [offset = 4Ch].........................................
ADC Group1 DMA Control Register (ADG1DMACR) [offset = 50h] ...............................................
ADC Group2 DMA Control Register (ADG2DMACR) [offset = 54h] ...............................................
ADC Results Memory Configuration Register (ADBNDCR) [offset = 58h] ........................................
ADC Results Memory Size Configuration Register (ADBNDEND) [offset = 5Ch] ................................
ADC Event Group Sampling Time Configuration Register (ADEVSAMP) [offset = 60h] ........................
ADC Group1 Sampling Time Configuration Register (ADG1SAMP) [offset = 64h] ..............................
ADC Group2 Sampling Time Configuration Register (ADG2SAMP) [offset = 68h] ..............................
ADC Event Group Status Register (ADEVSR) [offset = 6Ch] ......................................................
ADC Group1 Status Register (ADG1SR) [offset = 70h] .............................................................
ADC Group2 Status Register (ADG2SR) [offset = 74h] .............................................................
ADC Event Group Channel Select Register (ADEVSEL) [offset = 78h] ...........................................
ADC Group1 Channel Select Register (ADG1SEL) [offset = 7Ch] .................................................
ADC Group2 Channel Select Register (ADG2SEL) [offset = 80h] .................................................
12-bit ADC Calibration and Error Offset Correction Register (ADCALR) [offset = 84h] .........................
10-bit ADC Calibration and Error Offset Correction Register (ADCALR) [offset = 84h] .........................
ADC State Machine Status Register (ADSMSTATE) [offset = 88h] ...............................................
ADC Channel Last Conversion Value Register (ADLASTCONV) [offset = 8Ch] .................................
12-bit ADC Event Group Results' FIFO Register (ADEVBUFFER) [offset = 90h-AFh] ..........................
19-15. Timing for Sample Capacitor Discharge Mode
720
19-16.
722
19-17.
19-18.
19-19.
19-20.
19-21.
19-22.
19-23.
19-24.
19-25.
19-26.
19-27.
19-28.
19-29.
19-30.
19-31.
19-32.
19-33.
19-34.
19-35.
19-36.
19-37.
19-38.
19-39.
19-40.
19-41.
19-42.
19-43.
19-44.
19-45.
19-46.
19-47.
19-48.
19-49.
19-50.
19-51.
19-52.
19-53.
19-54.
19-55.
19-56.
19-57.
19-58.
SPNU499C – March 2018
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List of Figures
Copyright © 2018, Texas Instruments Incorporated
722
726
726
728
728
730
730
733
733
736
736
739
740
741
742
743
744
745
746
747
748
748
749
750
752
754
756
757
758
758
759
760
761
762
763
764
765
766
766
766
767
768
43
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19-59. 10-bit ADC Event Group Results' FIFO Register (ADEVBUFFER) [offset = 90h-AFh] .......................... 768
19-60. 12-bit ADC Group1 Results FIFO Register (ADG1BUFFER) [offset = B0h-CFh] ................................ 769
19-61. 10-bit ADC Group1 Results' FIFO Register (ADG1BUFFER) [offset = B0h-CFh]
...............................
769
19-62. 12-bit ADC Group2 Results FIFO Register (ADG2BUFFER) [offset = D0h-EFh] ................................ 770
19-63. 10-bit ADC Group2 Results' FIFO Register (ADG2BUFFER) [offset = D0h-EFh]
...............................
770
19-64. 12-bit ADC Event Group Results Emulation FIFO Register (ADEVEMUBUFFER) [offset = F0h] ............. 771
19-65. 10-bit ADC Event Group Results Emulation FIFO Register (ADEVEMUBUFFER) [offset = F0h] ............. 771
19-66. 12-bit ADC Group1 Results Emulation FIFO Register (ADG1EMUBUFFER) [offset = F4h] ................... 772
19-67. 10-bit ADC Group1 Results Emulation FIFO Register (ADG1EMUBUFFER) [offset = F4h] ................... 772
19-68. 12-bit ADC Group2 Results Emulation FIFO Register (ADG2EMUBUFFER) [offset = F8h] ................... 773
19-69. 10-bit ADC Group2 Results Emulation FIFO Register (ADG2EMUBUFFER) [offset = F8h] ................... 773
19-70. ADC ADEVT Pin Direction Control Register (ADEVTDIR) [offset = FCh] ......................................... 774
19-71. ADC ADEVT Pin Output Value Control Register (ADEVTOUT) [offset = 100h] .................................. 775
19-72. ADC ADEVT Pin Input Value Register (ADEVTIN) [offset = 104h] ................................................ 775
776
19-74. ADC ADEVT Pin Clear Register (ADEVTCLR) [offset = 10Ch]
776
19-75.
19-76.
19-77.
19-78.
19-79.
19-80.
19-81.
19-82.
19-83.
19-84.
19-85.
19-86.
19-87.
19-88.
19-89.
19-90.
19-91.
19-92.
19-93.
19-94.
19-95.
19-96.
19-97.
20-1.
20-2.
20-3.
20-4.
20-5.
20-6.
20-7.
20-8.
20-9.
20-10.
44
.......................................................
....................................................
ADC ADEVT Pin Open Drain Enable Register (ADEVTPDR) [offset = 110h] ....................................
ADC ADEVT Pin Pull Control Disable Register (ADEVTPDIS) [offset = 114h]...................................
ADC ADEVT Pin Pull Control Select Register (ADEVTPSEL) [offset = 118h] ...................................
ADC Event Group Sample Cap Discharge Control Register (ADEVSAMPDISEN) [offset = 11Ch] ...........
ADC Group1 Sample Cap Discharge Control Register (ADG1SAMPDISEN) [offset = 120h] ..................
ADC Group2 Sample Cap Discharge Control Register (ADG2SAMPDISEN) [offset = 124h] ..................
12-bit ADC Magnitude Compare Interrupt x Control Registers (ADMAGINTxCR) [offset = 128h-138h] ......
10-bit ADC Magnitude Compare Interrupt x Control Registers (ADMAGINTxCR) [offset = 128h-138h] ......
12-bit ADC Magnitude Compare Interrupt x Mask Register (ADMAGxMASK) [offset = 12Ch-13Ch] .........
10-bit ADC Magnitude Compare Interrupt x Mask Register (ADMAGxMASK) [offset = 12Ch-13Ch] .........
ADC Magnitude Compare Interrupt Enable Set Register (ADMAGINTENASET) [offset = 158h] ..............
ADC Magnitude Compare Interrupt Enable Clear Register (ADMAGINTENACLR) [offset = 15Ch] ...........
ADC Magnitude Compare Interrupt Flag Register (ADMAGINTFLG) [offset = 160h] ...........................
ADC Magnitude Compare Interrupt Offset Register (ADMAGINTOFF) [offset = 164h] .........................
ADC Event Group FIFO Reset Control Register (ADEVFIFORESETCR) [offset = 168h] ......................
ADC Group1 FIFO Reset Control Register (ADG1FIFORESETCR) [offset = 16Ch] ............................
ADC Group2 FIFO Reset Control Register (ADG2FIFORESETCR) [offset = 170h].............................
ADC Event Group RAM Write Address Register (ADEVRAMWRADDR) [offset = 174h] .......................
ADC Group1 RAM Write Address Register (ADG1RAMWRADDR) [offset = 178h] .............................
ADC Group2 RAM Write Address Register (ADG2RAMWRADDR) [offset = 17Ch] .............................
ADC Parity Control Register (ADPARCR) [offset = 180h] ...........................................................
ADC Parity Error Address Register (ADPARADDR) [offset = 184h] ...............................................
ADC Power-Up Delay Control Register (ADPWRUPDLYCTRL) [offset = 188h] .................................
N2HET Block Diagram ...................................................................................................
Specialized Timer Micromachine .......................................................................................
Program Flow Timings ...................................................................................................
Use of the Overflow Interrupt Flag (HETEXC2) ......................................................................
Multi-Resolution Operation Flow Example ............................................................................
Debug Control Configuration ............................................................................................
Prescaler Configuration ..................................................................................................
I/O Control .................................................................................................................
N2HET Loop Resolution Structure for Each Bit ......................................................................
Loop Resolution Instruction Execution Example .....................................................................
19-73. ADC ADEVT Pin Set Register (ADEVTSET) [offset = 108h]
List of Figures
777
777
778
778
779
780
781
781
783
783
784
784
785
785
786
786
787
787
788
788
789
790
790
793
797
798
799
800
801
805
808
809
810
SPNU499C – March 2018
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20-11. HR I/O Architecture ....................................................................................................... 811
20-12. Example of HR Structure Sharing for N2HET Pins 0/1 .............................................................. 812
20-13. XOR-shared HR I/O ...................................................................................................... 813
20-14. Symmetrical PWM with XOR-sharing Output ......................................................................... 814
20-15. AND-shared HR I/O
......................................................................................................
814
20-16. HR0 to HR1 Digital Loopback Logic: LBTYPE[0] = 0 ................................................................ 815
20-17. HR0 to HR1 Analog Loop Back Logic: LBTYPE[0] = 1 .............................................................. 816
20-18. N2HET Input Edge Detection ........................................................................................... 817
20-19. ECMP Execution Timings................................................................................................ 818
20-20. High/Low Resolution Modes for ECMP and PWCNT ................................................................ 819
20-21. PCNT Instruction Timing (With Capture Edge After HR Counter Overflow) ...................................... 820
20-22. PCNT Instruction Timing (With Capture Edge Before HR Counter Overflow) .................................... 820
20-23. WCAP Instruction Timing ................................................................................................ 821
20-24. I/O Block Diagram Including Pull Control Logic....................................................................... 822
20-25. N2HET Pin Disable Feature Diagram .................................................................................. 823
.................................................................................
Interrupt Functionality on Instruction Level ............................................................................
Interrupt Flag/Priority Level Architecture...............................................................................
Request Line Assignment Example ....................................................................................
Operation of N2HET Count Instructions ...............................................................................
SCNT Count Operation ..................................................................................................
ACNT Period Variation Compensations ...............................................................................
N2HET Timings Associated with the Gap Flag (ACNT Deceleration) .............................................
N2HET Timings Associated with the Gap Flag (ACNT Acceleration) .............................................
Angle Generator Principle ...............................................................................................
Hardware Angle Generator Block Diagram............................................................................
Angle Tick Generation Principle ........................................................................................
New Angle Tick Generation Architecture ..............................................................................
Angle Generation Using Time Based Algorithm ......................................................................
SCNT Stepping Compensation .........................................................................................
ACNT During Acceleration and Deceleration .........................................................................
Singularity Check, ACNT Reset and Timing Associated ............................................................
Example of HWAG Start Sequence ....................................................................................
Code ........................................................................................................................
Gap Verification Criteria For a 60-2 Toothed Wheel .................................................................
Using the ARST Bit in a Toothed Wheel Without Singularity .......................................................
Windowing Filter for Toothed Wheel Input on Falling Active Edge.................................................
Filtering During Singularity Tooth ......................................................................................
HWAG Interrupt Block Diagram .........................................................................................
Hardware Angle Generator/High End Timer Interface ...............................................................
Angle Count Within the HWAG at Resolution Clock .................................................................
Angle Count Within the NHET With Increments ......................................................................
Compare Without ACMP Instruction ...................................................................................
Example of ACMP Compare Within the NHET .......................................................................
NHET Interface Block Diagram .........................................................................................
Global Configuration Register (HETGCR) [offset = 00h] ............................................................
Prescale Factor Register (HETPFR) ...................................................................................
N2HET Current Address (HETADDR) .................................................................................
Offset Index Priority Level 1 Register (HETOFF1) ...................................................................
20-26. Suppression Filter Counter Operation
825
20-27.
826
20-28.
20-29.
20-30.
20-31.
20-32.
20-33.
20-34.
20-35.
20-36.
20-37.
20-38.
20-39.
20-40.
20-41.
20-42.
20-43.
20-44.
20-45.
20-46.
20-47.
20-48.
20-49.
20-50.
20-51.
20-52.
20-53.
20-54.
20-55.
20-56.
20-57.
20-58.
20-59.
SPNU499C – March 2018
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List of Figures
Copyright © 2018, Texas Instruments Incorporated
827
828
829
829
830
831
832
833
834
835
836
837
837
838
839
840
841
842
843
844
845
846
848
848
849
849
850
851
856
858
859
859
45
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20-60. Offset Index Priority Level 2 Register (HETOFF2) ................................................................... 860
20-61. Interrupt Enable Set Register (HETINTENAS)
.......................................................................
861
20-62. Interrupt Enable Clear (HETINTENAC) ................................................................................ 861
20-63. Exception Control Register (HETEXC1) ............................................................................... 862
20-64. Exception Control Register 2 (HETEXC2) ............................................................................. 863
..................................................................................
20-66. Interrupt Flag Register (HETFLG) ......................................................................................
20-67. AND Share Control Register (HETAND) ..............................................................................
20-68. HR Share Control Register (HETHRSH) ..............................................................................
20-69. XOR Share Control Register (HETXOR) ..............................................................................
20-70. Request Enable Set Register (HETREQENS) ........................................................................
20-71. Request Enable Clear Register (HETREQENC) .....................................................................
20-72. Request Destination Select Register (HETREQDS) [offset = FFF7 B844h] ......................................
20-73. N2HET Direction Register (HETDIR) ..................................................................................
20-74. N2HET Data Input Register (HETDIN) .................................................................................
20-75. N2HET Data Output Register (HETDOUT)............................................................................
20-76. N2HET Data Set Register (HETDSET) ................................................................................
20-77. N2HET Data Clear Register (HETDCLR) .............................................................................
20-78. N2HET Open Drain Register (HETPDR) .............................................................................
20-79. N2HET Pull Disable Register (HETPULDIS) .........................................................................
20-80. N2HET Pull Select Register (HETPSL) ................................................................................
20-81. Parity Control Register (HETPCR) .....................................................................................
20-82. Parity Address Register (HETPAR) ....................................................................................
20-83. Parity Pin Register (HETPPR) ..........................................................................................
20-84. Suppression Filter Preload Register (HETSFPRLD) .................................................................
20-85. Suppression Filter Enable Register (HETSFENA) ...................................................................
20-86. Loop Back Pair Select Register (HETLBPSEL) ......................................................................
20-87. Loop Back Pair Direction Register (HETLBPDIR) ....................................................................
20-88. N2HET Pin Disable Register (HETPINDIS) ...........................................................................
20-89. HWAG Pin Select Register (HWAPINSEL)............................................................................
20-90. HWAG Global Control Register 0 (HWAGCR0) ......................................................................
20-91. HWAG Global Control Register 1 (HWAGCR1) ......................................................................
20-92. HWAG Global Control Register 2 (HWAGCR2) ......................................................................
20-93. HWAG Interrupt Enable Set Register (HWAENASET) ..............................................................
20-94. HWAG Interrupt Enable Clear Register (HWAENACLR) ............................................................
20-95. HWAG Interrupt Level Set Register (HWALVLSET) .................................................................
20-96. HWAG Interrupt Level Clear Register (HWALVLCLR)...............................................................
20-97. HWAG Interrupt Flag Register (HWAFLG) ............................................................................
20-98. HWAG Interrupt Offset Register 0 (HWAOFF0) ......................................................................
20-99. HWAG Interrupt Offset Register 1 (HWAOFF1) ......................................................................
20-100. HWAG Angle Value Register (HWAACNT) ..........................................................................
20-101. HWAG Previous Tooth Period Value Register (HWAPCNT1).....................................................
20-102. HWAG Current Tooth Period Value Register (HWAPCNT)........................................................
20-103. HWAG Step Width Register (HWASTWD) ...........................................................................
20-104. HWAG Teeth Number Register (HWATHNB) .......................................................................
20-105. HWAG Current Teeth Number Register (HWATHVL) ..............................................................
20-106. HWAG Filter Register (HWAFIL) ......................................................................................
20-107. HWAG Filter Register 2 (HWAFIL2) ..................................................................................
20-108. HWAG Angle Increment Register (HWAANGI) ......................................................................
20-65. Interrupt Priority Register (HETPRY)
46
List of Figures
864
864
865
866
867
868
868
869
870
871
871
872
872
873
873
874
875
876
877
878
878
879
880
881
883
884
884
885
886
887
888
888
889
890
891
892
893
893
894
895
895
896
896
897
SPNU499C – March 2018
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20-109. ACMP Program Field (P31:P0) ........................................................................................ 903
20-110. ACMP Control Field (C31:C0) ......................................................................................... 903
20-111. ACMP Data Field (D31:D0) ............................................................................................ 903
20-112. ACNT Program Field (P31:P0) ........................................................................................ 905
20-113. ACNT Control Field (C31:C0) .......................................................................................... 905
20-114. ACNT Data Field (D31:D0) ............................................................................................. 905
20-115. ADCNST Program Field (P31:P0)..................................................................................... 908
20-116. ADCNST Control Field (C31:C0) ...................................................................................... 908
20-117. ADCNST Data Field (D31:D0) ......................................................................................... 908
20-118. ADCNST Operation If Remote Data Field[31:7] Is Not Zero
......................................................
909
20-119. ADCNST Operation if Remote Data Field [31:7] Is Zero ........................................................... 909
................................................
.................................................
ADC, ADD, AND, OR, SBB, SUB, XOR Data Field (D31:D0) .....................................................
ADM32 Program Field (P31:P0) .......................................................................................
ADM32 Control Field (C31:C0) ........................................................................................
ADM32 Data Field (D31:D0) ...........................................................................................
ADM32 Add and Move Operation for IM®TOREG (Case 00) ...............................................
ADM32 Add and Move Operation for REM®TOREG (Case 01) ............................................
APCNT Program Field (P31:P0) ......................................................................................
APCNT Control Field (C31:C0) ........................................................................................
APCNT Data Field (D31:D0) ...........................................................................................
BR Program Field (P31:P0) ............................................................................................
BR Control Field (C31:C0) .............................................................................................
BR Data Field (D31:D0) ................................................................................................
CNT Program Field (P31:P0) ..........................................................................................
CNT Control Field (C31:C0) ...........................................................................................
CNT Data Field (D31:D0) ..............................................................................................
DADM64 Program Field (P31:P0) .....................................................................................
DADM64 Control Field (C31:C0) ......................................................................................
DADM64 Data Field (D31:D0) .........................................................................................
DADM64 Add and Move Operation ..................................................................................
DJZ Program Field (P31:P0) ...........................................................................................
DJZ Control Field (C31:C0) ............................................................................................
DJZ Data Field (D31:D0) ...............................................................................................
ECMP Program Field (P31:P0) ........................................................................................
ECMP Control Field (C31:C0) .........................................................................................
ECMP Data Field (D31:D0) ............................................................................................
ECNT Program Field (P31:P0) ........................................................................................
ECNT Control Field (C31:C0) ..........................................................................................
ECNT Data Field (D31:D0) .............................................................................................
MCMP Program Field (P31:P0) .......................................................................................
MCMP Control Field (C31:C0) .........................................................................................
MCMP Data Field (D31:D0) ............................................................................................
MOV32 Program Field (P31:P0) ......................................................................................
MOV32 Control Field (C31:C0) ........................................................................................
MOV32 Data Field (D31:D0) ...........................................................................................
MOV32 Move Operation for IMTOREG (Case 00) ..................................................................
MOV32 Move Operation for IMTOREG&REM (Case 01) ..........................................................
20-120. ADC, ADD, AND, OR, SBB, SUB, XOR Program Field (P31:P0)
910
20-121. ADC, ADD, AND, OR, SBB, SUB, XOR Control Field (C31:C0)
910
20-122.
910
20-123.
20-124.
20-125.
20-126.
20-127.
20-128.
20-129.
20-130.
20-131.
20-132.
20-133.
20-134.
20-135.
20-136.
20-137.
20-138.
20-139.
20-140.
20-141.
20-142.
20-143.
20-144.
20-145.
20-146.
20-147.
20-148.
20-149.
20-150.
20-151.
20-152.
20-153.
20-154.
20-155.
20-156.
20-157.
SPNU499C – March 2018
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List of Figures
Copyright © 2018, Texas Instruments Incorporated
916
916
916
918
918
919
919
919
922
922
922
924
924
924
928
928
928
928
930
930
930
932
932
932
935
935
935
937
937
937
940
940
940
941
942
47
www.ti.com
20-158. MOV32 Move Operation for REGTOREM (Case 10) ............................................................... 942
20-159. MOV32 Move Operation for REMTOREG (Case 11) ............................................................... 942
20-160. MOV64 Program Field (P31:P0)
......................................................................................
945
20-161. MOV64 Control Field (C31:C0) ........................................................................................ 945
20-162. MOV64 Data Field (D31:D0) ........................................................................................... 945
...............................................................................................
20-164. PCNT Program Field (P31:P0) ........................................................................................
20-165. PCNT Control Field (C31:C0) ..........................................................................................
20-166. PCNT Data Field (D31:D0) .............................................................................................
20-167. PWCNT Program Field (P31:P0) ......................................................................................
20-168. PWCNT Control Field (C31:C0) .......................................................................................
20-169. PWCNT Data Field (D31:D0) ..........................................................................................
20-170. RADM64 Program Field (P31:P0) .....................................................................................
20-171. RADM64 Control Field (C31:C0) ......................................................................................
20-172. RADM64 Data Field (D31:D0) .........................................................................................
20-173. RADM64 Add and Move Operation ..................................................................................
20-174. RCNT Program Field (P31:P0) ........................................................................................
20-175. RCNT Control Field (C31:C0) .........................................................................................
20-176. RCNT Data Field (D31:D0) ............................................................................................
20-177. SCMP Program Field (P31:P0) ........................................................................................
20-178. SCMP Control Field (C31:C0) .........................................................................................
20-179. SCMP Data Field (D31:D0) ............................................................................................
20-180. SCNT Program Field (P31:P0) ........................................................................................
20-181. SCNT Control Field (C31:C0) ..........................................................................................
20-182. SCNT Data Field (D31:D0) .............................................................................................
20-183. SHFT Program Field (P31:P0).........................................................................................
20-184. SHFT Control Field (C31:C0) ..........................................................................................
20-185. SHFT Data Field (D31:D0) .............................................................................................
20-186. WCAP Program Field (P31:P0)........................................................................................
20-187. WCAP Control Field (C31:C0) .........................................................................................
20-188. WCAP Data Field (D31:D0) ............................................................................................
20-189. WCAPE Program Field (P31:P0) ......................................................................................
20-190. WCAPE Control Field (C31:C0) .......................................................................................
20-191. WCAPE Data Field (D31:D0) ..........................................................................................
21-1. System Block Diagram ...................................................................................................
21-2. HTU Block Diagram ......................................................................................................
21-3. Example of a HTU Transfer .............................................................................................
21-4. Single Buffer Timing and Memory Representation ...................................................................
21-5. Timing Example for Circular Buffer Mode .............................................................................
21-6. Dual Buffer Timing ........................................................................................................
21-7. Timing Example for Auto Switch Buffer Mode ........................................................................
21-8. Timing for Disabling Control Packets ..................................................................................
21-9. Timing Example Including Lost Requests .............................................................................
21-10. Timing that Generates No Request Lost Error ........................................................................
21-11. Timing that Generates a Request Lost Error..........................................................................
21-12. Timing Example for Two WCAP Instructions .........................................................................
21-13. Timing of the WCAP, ECNT, PCNT Example.........................................................................
21-14. Global Control Register (HTU GC) [offset = 00] ......................................................................
21-15. Control Packet Enable Register (HTU CPENA) [offset = 04h] ......................................................
20-163. MOV64 Move Operation
48
List of Figures
945
947
947
947
950
950
950
954
954
954
954
956
956
956
958
958
958
960
960
960
962
962
962
965
965
965
967
967
967
971
972
972
974
974
975
976
977
978
979
979
980
983
987
988
SPNU499C – March 2018
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21-16. Control Packet (CP) Busy Register 0 (HTU BUSY0) [offset = 08h] ................................................ 989
21-17. Control Packet (CP) Busy Register 1 (HTU BUSY1) [offset = 0Ch]
...............................................
990
21-18. Control Packet (CP) Busy Register 2 (HTU BUSY2) [offset = 10h] ................................................ 990
21-19. Control Packet (CP) Busy Register 3 (HTU BUSY3) [offset = 14h] ................................................ 991
21-20. Active Control Packet and Error Register (HTU ACPE) [offset = 18h]
............................................
991
21-21. Request Lost and Bus Error Control Register (HTU RLBECTRL) [offset = 20h] ................................. 993
21-22. Buffer Full Interrupt Enable Set Register (HTU BFINTS) [offset = 24h] ........................................... 994
21-23. Buffer Full Interrupt Enable Clear Register (HTU BFINTC) [offset = 28h]
........................................
994
21-24. Interrupt Mapping Register (HTU INTMAP) [offset = 2Ch] .......................................................... 995
21-25. Interrupt Offset Register 0 (HTU INTOFF0) [offset = 34h] .......................................................... 996
21-26. Interrupt Offset Register 1 (HTU INTOFF1) [offset = 38h] .......................................................... 997
21-27. Buffer Initialization Mode Register (HTU BIM) [offset = 3Ch] ....................................................... 998
21-28. Request Lost Flag Register (HTU RLOSTFL) [offset = 40h] ...................................................... 1000
21-29. Buffer Full Interrupt Flag Register (HTU BFINTFL) [offset = 44h] ................................................ 1000
21-30. BER Interrupt Flag Register (HTU BERINTFL) [offset = 48h] ..................................................... 1001
......................................
Memory Protection 1 End Address Register (HTU MP1E) [offset = 50h] ........................................
Debug Control Register (HTU DCTRL) [offset = 54h] ..............................................................
Watch Point Register (HTU WPR) [offset = 58h] ...................................................................
Watch Mask Register (HTU WMR) [offset = 5Ch] ..................................................................
Module Identification Register (HTU ID) [offset = 60h] .............................................................
Parity Control Register (HTU PCR) [offset = 64h] ..................................................................
Parity Address Register (HTU PAR) [offset = 68h] .................................................................
Memory Protection Control and Status Register (HTU MPCS) [offset = 70h]...................................
Memory Protection Start Address Register 0 (HTU MP0S) [offset = 74h] .......................................
Memory Protection End Address Register (HTU MP0E) [offset = 78h] ..........................................
Initial Full Address A Register (HTU IFADDRA) ....................................................................
Initial Full Address B Register (HTU IFADDRB) ....................................................................
Initial N2HET Address and Control Register (HTU IHADDRCT)..................................................
Initial Transfer Count Register (HTU ITCOUNT) ....................................................................
Current Full Address A Register (HTU CFADDRA) ................................................................
Current Full Address B Register (HTU CFADDRB) ................................................................
Current Frame Count Register (HTU CFCOUNT) ..................................................................
I/O Function Quick Start Flow Chart ..................................................................................
Interrupt Generation Function Quick Start Flow Chart .............................................................
GIO Module Diagram ...................................................................................................
GIO Block Diagram .....................................................................................................
GIO Global Control Register (GIOGCR0) [offset = 00h] ...........................................................
GIO Interrupt Detect Register (GIOINTDET) [offset = 08h] ........................................................
GIO Interrupt Polarity Register (GIOPOL) [offset = 0Ch] ..........................................................
GIO Interrupt Enable Set Register (GIOENASET) [offset = 10h] .................................................
GIO Interrupt Enable Clear Register (GIOENACLR) [offset = 14h]...............................................
GIO Interrupt Priority Register (GIOLVLSET) [offset = 18h] .......................................................
GIO Interrupt Priority Register (GIOLVLCLR) [offset = 1Ch] ......................................................
GIO Interrupt Flag Register (GIOFLG) [offset = 20h] ...............................................................
GIO Offset 1 Register (GIOOFF1) [offset = 24h] ....................................................................
GIO Offset 2 Register (GIOOFF2) [offset = 28h] ....................................................................
GIO Emulation 1 Register (GIOEMU1) [offset = 2Ch] ..............................................................
GIO Emulation 2 Register (GIOEMU2) [offset = 30h] ..............................................................
21-31. Memory Protection 1 Start Address Register (HTU MP1S) [offset = 4Ch]
21-32.
21-33.
21-34.
21-35.
21-36.
21-37.
21-38.
21-39.
21-40.
21-41.
21-42.
21-43.
21-44.
21-45.
21-46.
21-47.
21-48.
22-1.
22-2.
22-3.
22-4.
22-5.
22-6.
22-7.
22-8.
22-9.
22-10.
22-11.
22-12.
22-13.
22-14.
22-15.
22-16.
SPNU499C – March 2018
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List of Figures
Copyright © 2018, Texas Instruments Incorporated
1002
1002
1003
1004
1004
1005
1006
1007
1008
1011
1011
1013
1013
1014
1015
1016
1017
1018
1023
1024
1025
1027
1030
1031
1032
1033
1034
1035
1037
1038
1039
1040
1041
1042
49
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22-17. GIO Data Direction Registers (GIODIR[A-B]) [offset = 34h, 54h] ................................................. 1043
1043
22-19. GIO Data Output Registers (GIODOUT[A-B]) [offset = 3Ch, 5Ch]
1044
22-20.
1044
22-21.
22-22.
22-23.
22-24.
23-1.
23-2.
23-3.
23-4.
23-5.
23-6.
23-7.
23-8.
23-9.
23-10.
23-11.
23-12.
23-13.
23-14.
23-15.
23-16.
23-17.
23-18.
23-19.
23-20.
23-21.
23-22.
23-23.
23-24.
23-25.
23-26.
23-27.
23-28.
23-29.
23-30.
23-31.
23-32.
23-33.
23-34.
23-35.
23-36.
23-37.
23-38.
23-39.
23-40.
23-41.
50
.....................................................
...............................................
GIO Data Set Registers (GIODSET[A-B]) [offset = 40h, 60h] .....................................................
GIO Data Clear Registers (GIODCLR[A-B]) [offset = 44h, 64h] ..................................................
GIO Open Drain Registers (GIOPDR[A-B]) [offset = 48h, 68h] ...................................................
GIO Pull Disable Registers (GIOPULDIS[A-B]) [offset = 4Ch, 6Ch] ..............................................
GIO Pull Select Registers (GIOPSL[A-B]) [offset = 50h, 70h] .....................................................
Block Diagram ...........................................................................................................
FlexRay Module Blocks ................................................................................................
Transfer Unit .............................................................................................................
FlexRay Transfer Unit Operation Principle ...........................................................................
FlexRay Transfer Unit Operation Principle for Transfer FSM (simplified) .......................................
FlexRay Transfer Unit Operation Principle for Event FSM (simplified)...........................................
Example: FTU Read Transfer of 6 Words ...........................................................................
Example: FTU Write Transfer of 6 Words............................................................................
Transfer Start Address to Message Buffer Number Assignment .................................................
Structure of Communication Cycle ....................................................................................
Configuration of NIT Start and Offset Correction Start .............................................................
Overall State Diagram of Communication Controller ...............................................................
Structure of POC State WAKEUP ....................................................................................
Timing of Wake Up Pattern ............................................................................................
State Diagram Time-Triggered Startup ...............................................................................
FIFO Status: Empty, Not Empty, and Overrun ......................................................................
Host Access to Message RAM ........................................................................................
Double Buffer Structure Input Buffer ..................................................................................
Swapping of IBCM and IBCR Bits ....................................................................................
Double Buffer Structure Output Buffer................................................................................
Swapping of OBCM and OBCR Bits ..................................................................................
Access to Transient Buffer RAMs .....................................................................................
Configuration Example of Message Buffers in the Message RAM ...............................................
Header Section of Message Buffer in Message RAM ..............................................................
Example Structure of Data Partition in Message RAM .............................................................
Parity Structure ..........................................................................................................
Parity Generation and Check ..........................................................................................
Transfer Unit (TU) Interrupt Structure ................................................................................
Communication Controller (CC) Interrupt Structure ................................................................
Global Static Number 0 (GSN0) [offset_TU = 00h] .................................................................
Global Static Number 1 (GSN1) [offset_TU = 04h] .................................................................
Global Control Set (GCS) [offset_TU = 10h] ........................................................................
Global Control Reset (GCR) [offset_TU = 14h] .....................................................................
Transfer Status Current Buffer (TSCB) [offset_TU = 18h] .........................................................
Last Transferred Buffer to Communication Controller (LTBCC) [offset_TU = 1Ch] ............................
Last Transferred Buffer to System Memory (LTBSM) [offset_TU = 20h] ........................................
Transfer Base Address (TBA) [offset_TU = 24h]....................................................................
Next Transfer Base Address (NTBA) [offset_TU = 28h] ...........................................................
Base Address of Mirrored Status (BAMS) [offset_TU = 2Ch] .....................................................
Start Address of Memory Protection (SAMP) [offset_TU = 30h] ..................................................
End Address of Memory Protection (EAMP) [offset_TU = 34h] ...................................................
22-18. GIO Data Input Registers (GIODIN[A-B]) [offset = 38h, 58h]
List of Figures
1045
1045
1046
1046
1050
1053
1054
1055
1056
1057
1059
1059
1061
1064
1065
1069
1073
1075
1077
1087
1090
1091
1091
1092
1093
1095
1096
1097
1099
1100
1101
1104
1106
1110
1110
1111
1111
1114
1115
1115
1116
1116
1117
1117
1118
SPNU499C – March 2018
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...........................................
Transfer to System Memory Occurred 2 (TSMO2) [offset_TU = 44h] ...........................................
Transfer to System Memory Occurred 3 (TSMO3) [offset_TU = 48h] ...........................................
Transfer to System Memory Occurred 4 (TSMO4) [offset_TU = 4Ch] ...........................................
Transfer to Communication Controller Occurred 1 (TCCO1) [offset_TU = 50h] ................................
Transfer to Communication Controller Occurred 2 (TCCO2) [offset_TU = 54h] ................................
Transfer to Communication Controller Occurred 3 (TCCO3) [offset_TU = 58h] ................................
Transfer to Communication Controller Occurred 4 (TCCO4) [offset_TU = 5Ch]................................
Transfer Occurred Offset (TOOFF) [offset_TU = 60h] .............................................................
Parity Error Address (PEADR) [offset_TU = 70h] ...................................................................
Transfer Error Interrupt Flag (TEIF) [offset_TU = 74h] .............................................................
Transfer Error Interrupt Enable Set (TEIRES) [offset_TU = 78h] .................................................
Transfer Error Interrupt Enable Reset (TEIRER) [offset_TU = 7Ch] .............................................
Trigger Transfer to System Memory Set 1 (TTSMS1) [offset_TU = 80h] ........................................
Trigger Transfer to System Memory Reset 1 (TTSMR1) [offset_TU = 84h] .....................................
Trigger Transfer to System Memory Set 2 (TTSMS2) [offset_TU = 88h] ........................................
Trigger Transfer to System Memory Reset 2 (TTSMR2) [offset_TU = 8Ch] ....................................
Trigger Transfer to System Memory Set 3 (TTSMS3) [offset_TU = 90h] ........................................
Trigger Transfer to System Memory Reset 3 (TTSMR3) [offset_TU = 94h] .....................................
Trigger Transfer to System Memory Set 4 (TTSMS4) [offset_TU = 98h] ........................................
Trigger Transfer to System Memory Reset 4 (TTSMR4) [offset_TU = 9Ch] ....................................
Trigger Transfer to Communication Controller Set 1 (TTCCS1) [offset_TU = A0h] ............................
Trigger Transfer to Communication Controller Reset 1 (TTCCR1) [offset_TU = A4h] .........................
Trigger Transfer to Communication Controller Set 2 (TTCCS2) [offset_TU = A8h] ............................
Trigger Transfer to Communication Controller Reset 2 (TTCCR2) [offset_TU = ACh] ........................
Trigger Transfer to Communication Controller Set 3 (TTCCS3) [offset_TU = B0h] ............................
Trigger Transfer to Communication Controller Reset 3 (TTCCR3) [offset_TU = B4h] .........................
Trigger Transfer to Communication Controller Set 4 (TTCCS4) [offset_TU = B8h] ............................
Trigger Transfer to Communication Controller Reset 4 (TTCCR4) [offset_TU = BCh] ........................
Enable Transfer on Event to System Memory Set 1 (ETESMS1) [offset_TU = C0h] ..........................
Enable Transfer on Event to System Memory Reset 1 (ETESMR1) [offset_TU = C4h] .......................
Enable Transfer on Event to System Memory Set 2 (ETESMS2) [offset_TU = C8h] ..........................
Enable Transfer on Event to System Memory Reset 2 (ETESMR2) [offset_TU = CCh] ......................
Enable Transfer on Event to System Memory Set 3 (ETESMS3) [offset_TU = D0h] ..........................
Enable Transfer on Event to System Memory Reset 3 (ETESMR3) [offset_TU = D4h] .......................
Enable Transfer on Event to System Memory Set 4 (ETESMS4) [offset_TU = D8h] ..........................
Enable Transfer on Event to System Memory Reset 4 (ETESMR4) [offset_TU = DCh] ......................
Clear on Event to System Memory Set 1 (CESMS1) [offset_TU = E0h].........................................
Clear on Event to System Memory Reset 1 (CESMR1) [offset_TU = E4h] .....................................
Clear on Event to System Memory Set 2 (CESMS2) [offset_TU = E8h].........................................
Clear on Event to System Memory Reset 2 (CESMR2) [offset_TU = ECh] .....................................
Clear on Event to System Memory Set 3 (CESMS3) [offset_TU = F0h] .........................................
Clear on Event to System Memory Reset 3 (CESMR3) [offset_TU = F4h]......................................
Clear on Event to System Memory Set 4 (CESMS4) [offset_TU = F8h] .........................................
Clear on Event to System Memory Reset 4 (CESMR4) [offset_TU = FCh] .....................................
Transfer to System Memory Interrupt Enable Set 1 (TSMIES1) [offset_TU = 100h] ...........................
Transfer to System Memory Interrupt Enable Reset 1 (TSMIER1) [offset_TU = 104h]........................
Transfer to System Memory Interrupt Enable Set 2 (TSMIES2) [offset_TU = 108h] ...........................
Transfer to System Memory Interrupt Enable Reset 2 (TSMIER2) [offset_TU = 10Ch] .......................
23-42. Transfer to System Memory Occurred 1 (TSMO1) [offset_TU = 40h]
1119
23-43.
1119
23-44.
23-45.
23-46.
23-47.
23-48.
23-49.
23-50.
23-51.
23-52.
23-53.
23-54.
23-55.
23-56.
23-57.
23-58.
23-59.
23-60.
23-61.
23-62.
23-63.
23-64.
23-65.
23-66.
23-67.
23-68.
23-69.
23-70.
23-71.
23-72.
23-73.
23-74.
23-75.
23-76.
23-77.
23-78.
23-79.
23-80.
23-81.
23-82.
23-83.
23-84.
23-85.
23-86.
23-87.
23-88.
23-89.
23-90.
SPNU499C – March 2018
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List of Figures
Copyright © 2018, Texas Instruments Incorporated
1119
1119
1121
1121
1121
1121
1123
1124
1125
1127
1128
1129
1129
1130
1130
1131
1131
1132
1132
1133
1133
1134
1134
1135
1135
1136
1136
1137
1137
1138
1138
1139
1139
1140
1140
1141
1141
1142
1142
1143
1143
1144
1144
1145
1145
1146
1146
51
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23-91. Transfer to System Memory Interrupt Enable Set 3 (TSMIES3) [offset_TU = 110h] ........................... 1147
23-92. Transfer to System Memory Interrupt Enable Reset 3 (TSMIER3) [offset_TU = 114h]........................ 1147
23-93. Transfer to System Memory Interrupt Enable Set 4 (TSMIES4) [offset_TU = 118h] ........................... 1148
23-94. Transfer to System Memory Interrupt Enable Reset 4 (TSMIER4) [offset_TU = 11Ch] ....................... 1148
23-95. Transfer to Communication Controller Interrupt Enable Set 1 (TCCIES1) [offset_TU = 120h] ............... 1149
23-96. Transfer to Communication Controller Interrupt Enable Reset 1 (TCCIER1) [offset_TU = 124h] ............ 1149
23-97. Transfer to Communication Controller Interrupt Enable Set 2 (TCCIES2) [offset_TU = 128h] ............... 1150
23-98. Transfer to Communication Controller Interrupt Enable Reset 2 (TCCIER2) [offset_TU = 12Ch]............ 1150
23-99. Transfer to Communication Controller Interrupt Enable Set 3 (TCCIES3) [offset_TU = 130h] ............... 1151
23-100. Transfer to Communication Controller Interrupt Enable Reset 3 (TCCIER3) [offset_TU = 134h] ........... 1151
23-101. Transfer to Communication Controller Interrupt Enable Set 4 (TCCIES4) [offset_TU = 138h] .............. 1152
23-102. Transfer to Communication Controller Interrupt Enable Reset 4 (TCCIER4) [offset_TU = 13Ch] .......... 1152
23-103. Transfer Configuration RAM (TCR) [offset_TU_RAM = 0h-1FFh] ............................................... 1153
23-104. Parity Information in TCR Parity Test Mode [offset_TU_RAM = 200h-3FFh] .................................. 1154
23-105. Message Buffer Assignment.......................................................................................... 1155
23-106. Test Register 1 (TEST1) [offset_CC = 10h] ........................................................................ 1159
23-107. Test Register 2 (TEST2) [offset_CC = 14h] ........................................................................ 1163
23-108. Test Mode Access to Communication Controller RAM Blocks
..................................................
1164
23-109. Lock Register (LCK) [offset_CC = 1Ch]............................................................................. 1165
23-110. Error Interrupt Register (EIR) [offset_CC = 20h]................................................................... 1166
23-111. Status Interrupt Register (SIR) [offset_CC = 24h] ................................................................. 1168
23-112. Error Interrupt Line Select Register (EILS) [offset_CC = 28h] ................................................... 1171
23-113. Status Interrupt Line Select Register (SILS) [offset_CC = 2Ch] ................................................. 1173
23-114. Error Interrupt Enable Set/Reset Register (EIES/EIER) [offset_CC = 30h/34h] ............................... 1175
23-115. Status Interrupt Enable Set/Reset Register (SIES/SIER) [offset_CC = 38h/3Ch] ............................. 1177
23-116. Interrupt Line Enable Register (ILE) [offset_CC = 40h] ........................................................... 1179
23-117. Timer 0 Configuration Register (T0C) [offset_CC = 44h] ......................................................... 1180
23-118. Timer 1 Configuration Register (T1C) [offset_CC = 48h] ......................................................... 1181
23-119. Stop Watch Register 1 (STPW1) [offset_CC = 4Ch] .............................................................. 1182
23-120. Stop Watch Register 2 (STPW2) [offset_CC = 50h]
..............................................................
1183
23-121. SUC Configuration Register 1 (SUCC1) [offset_CC = 80h] ...................................................... 1184
23-122. SUC Configuration Register 2 (SUCC2) [offset_CC = 84h] ...................................................... 1188
23-123. SUC Configuration Register 3 (SUCC3) [offset_CC = 88h] ...................................................... 1189
23-124. NEM Configuration Register (NEMC) [offset_CC = 8Ch] ......................................................... 1189
23-125. PRT Configuration Register 1 (PRTC1) [offset_CC = 90h]....................................................... 1190
23-126. PRT Configuration Register 2 (PRTC2) [offset_CC = 94h]....................................................... 1191
23-127. MHD Configuration Register (MHDC) [offset_CC = 98h] ......................................................... 1192
23-128. GTU Configuration Register 1 (GTUC1) [offset_CC = A0h] ...................................................... 1193
23-129. GTU Configuration Register 2 (GTUC2) [offset_CC = A4h] ...................................................... 1193
23-130. GTU Configuration Register 3 (GTUC3) [offset_CC = A8h] ...................................................... 1194
23-131. GTU Configuration Register 4 (GTUC4) [offset_CC = ACh] ..................................................... 1195
23-132. GTU Configuration Register 5 (GTUC5) [offset_CC = B0h] ...................................................... 1195
23-133. GTU Configuration Register 6 (GTUC6) [offset_CC = B4h] ...................................................... 1196
23-134. GTU Configuration Register 7 (GTUC7) [offset_CC = B8h] ...................................................... 1196
23-135. GTU Configuration Register 8 (GTUC8) [offset_CC = BCh] ..................................................... 1197
1197
23-137.
1198
23-138.
23-139.
52
.....................................................
GTU Configuration Register 10 (GTUC10) [offset_CC = C4h] ..................................................
GTU Configuration Register 11 (GTUC11) [offset_CC = C8h] ..................................................
Communication Controller Status Vector Register (CCSV) [offset_CC = 100h] ...............................
23-136. GTU Configuration Register 9 (GTUC9) [offset_CC = C0h]
List of Figures
1199
1200
SPNU499C – March 2018
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23-140. Communication Controller Error Vector Register (CCEV) [offset_CC = 104h] ................................ 1202
23-141. Slot Counter Vector Register (SCV) [offset_CC = 110h] ......................................................... 1203
23-142. Macrotick and Cycle Counter Register (MTCCV) [offset_CC = 114h] .......................................... 1203
23-143. Rate Correction Value Register (RCV) [offset_CC = 118h] ...................................................... 1204
23-144. Offset Correction Value Register (OCV) [offset_CC = 11Ch] .................................................... 1204
23-145. Sync Frame Status Register (SFS) [offset_CC = 120h] .......................................................... 1205
23-146. Symbol Window and NIT Status Register (SWNIT) [offset_CC = 124h]
.......................................
1206
23-147. Aggregated Channel Status Register (ACS) [offset_CC = 128h] ................................................ 1207
23-148. Even Sync ID Registers (ESIDn) [offset_CC = 130h-168h] ...................................................... 1209
23-149. Odd Sync ID Registers (OSIDn) [offset_CC = 170h-1A8h]
......................................................
1210
23-150. Network Management Registers (NMVn) [offset_CC = 1B0h-1B8h] ............................................ 1211
23-151. Message RAM Configuration Register (MRC) [offset_CC = 300h] .............................................. 1212
23-152. FIFO Rejection Filter Register (FRF) [offset_CC = 304h] ........................................................ 1214
23-153. FIFO Rejection Filter Mask Register (FRFM) [offset_CC = 308h] ............................................... 1215
23-154. FIFO Critical Level Register (FCL) [offset_CC = 30Ch]
..........................................................
1215
23-155. Message Handler Status (MHDS) [offset_CC = 310h] ............................................................ 1216
23-156. Last Dynamic Transmit Slot (LDTS) [offset_CC = 314h] ......................................................... 1217
23-157. FIFO Status Register (FSR) [offset_CC = 318h]
..................................................................
1218
23-158. Message Handler Constraints Flags (MHDF) [offset_CC = 31Ch] .............................................. 1219
23-159. Transmission Request Register 1 (TXRQ1) [offset_CC = 320h] ................................................ 1221
23-160. Transmission Request Register 2 (TXRQ2) [offset_CC = 324h] ................................................ 1221
23-161. Transmission Request Register 3 (TXRQ3) [offset_CC = 328h] ................................................ 1221
23-162. Transmission Request Register 4 (TXRQ4) [offset_CC = 32Ch] ................................................ 1221
...............................................................
23-164. New Data Register 2 (NDAT2) [offset_CC = 334h] ...............................................................
23-165. New Data Register 3 (NDAT3) [offset_CC = 338h] ...............................................................
23-166. New Data Register 4 (NDAT4) [offset_CC = 33Ch] ...............................................................
23-167. Message Buffer Status Changed Register 1 (MBSC1) [offset_CC = 340h] ....................................
23-168. Message Buffer Status Changed Register 2 (MBSC2) [offset_CC = 344h] ....................................
23-169. Message Buffer Status Changed Register 3 (MBSC3) [offset_CC = 348h] ....................................
23-170. Message Buffer Status Changed Register 4 (MBSC4) [offset_CC = 34Ch] ...................................
23-171. Core Release Register (CREL) [offset_CC = 3F0h]...............................................................
23-172. Endian Register (ENDN) [offset_CC = 3F4h] ......................................................................
23-173. Write Data Section Registers (WRDSn) [offset_CC = 400h-4FCh] .............................................
23-174. Write Header Section Register 1 (WRHS1) [offset_CC = 500h] .................................................
23-175. Write Header Section Register 2 (WRHS2) [offset_CC = 504h] .................................................
23-176. Write Header Section Register 3 (WRHS3) [offset_CC = 508h] .................................................
23-177. Input Buffer Command Mask Register (IBCM) [offset_CC = 510h] .............................................
23-178. Input Buffer Command Request Register (IBCR) [offset_CC = 514h] ..........................................
23-179. Read Data Section Registers (RDDSn) [offset_CC = 600h-6FCh] ..............................................
23-180. Read Header Section Register 1 (RDHS1) [offset_CC = 700h] .................................................
23-181. Read Header Section Register 2 (RDHS2) [offset_CC = 704h] .................................................
23-182. Read Header Section Register 3 (RDHS3) [offset_CC = 708h] .................................................
23-183. Message Buffer Status Register (MBS) [offset_CC = 70Ch] .....................................................
23-184. Output Buffer Command Mask Register (OBCM) [offset_CC = 700h] ..........................................
23-185. Output Buffer Command Mask Register (OBCR) [offset_CC = 714h] ..........................................
24-1. Block Diagram ...........................................................................................................
24-2. Bit Timing .................................................................................................................
24-3. CAN Bit-timing Configuration ..........................................................................................
23-163. New Data Register 1 (NDAT1) [offset_CC = 330h]
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List of Figures
Copyright © 2018, Texas Instruments Incorporated
1222
1222
1222
1222
1224
1224
1224
1224
1225
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1239
1240
1247
1249
1253
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24-4.
Structure of a Message Object ........................................................................................ 1255
24-5.
Message RAM Representation in Debug/Suspend Mode ......................................................... 1258
24-6.
Message RAM Representation in RAM Direct Access Mode ..................................................... 1258
24-7.
Data Transfer Between IF1 / IF2 Registers and Message RAM .................................................. 1260
24-8.
Initialization of a Transmit Object
1262
24-9.
Initialization of a Single Receive Object for Data Frames
1262
24-10.
24-11.
24-12.
24-13.
24-14.
24-15.
24-16.
24-17.
24-18.
24-19.
24-20.
24-21.
24-22.
24-23.
24-24.
24-25.
24-26.
24-27.
24-28.
24-29.
24-30.
24-31.
24-32.
24-33.
24-34.
24-35.
24-36.
24-37.
24-38.
24-39.
24-40.
24-41.
24-42.
24-43.
24-44.
24-45.
24-46.
24-47.
24-48.
24-49.
24-50.
24-51.
24-52.
54
.....................................................................................
.........................................................
Initialization of a Single Receive Object for Remote Frames ......................................................
CPU Handling of a FIFO Buffer (Interrupt Driven) ..................................................................
CAN Interrupt Topology 1 ..............................................................................................
CAN Interrupt Topology 2 ..............................................................................................
Local Power-Down Mode Flow Diagram .............................................................................
CAN Core in Silent Mode ..............................................................................................
CAN Core in Loop Back Mode ........................................................................................
CAN Core in External Loop Back Mode ..............................................................................
CAN Core in Loop Back Combined with Silent Mode ..............................................................
CAN Control Register (DCAN CTL) [offset = 00] ...................................................................
Error and Status Register (DCAN ES) [offset = 04h] ...............................................................
Error Counter Register (DCAN ERRC) [offset = 08h] ..............................................................
Bit Timing Register (DCAN BTR) [offset = 0Ch] ....................................................................
Interrupt Register (DCAN INT) [offset = 10h] ........................................................................
Test Register (DCAN TEST) [offset = 14h] ..........................................................................
Parity Error Code Register (DCAN PERR) [offset = 1Ch] .........................................................
Core Release Register (DCAN REL) [offset = 20h] ................................................................
Auto-Bus-On Time Register (DCAN ABOTR) [offset = 80h].......................................................
Transmission Request X Register (DCAN TXRQ X) [offset = 84h] ...............................................
Transmission Request 12 Register [offset = 88h] ...................................................................
Transmission Request 34 Register [offset = 8Ch] ..................................................................
Transmission Request 56 Register [offset = 90h] ...................................................................
Transmission Request 78 Register [offset = 94h] ...................................................................
New Data X Register (DCAN NWDAT X) [offset = 98h] ...........................................................
New Data 12 Register [offset = 9Ch] .................................................................................
New Data 34 Register [offset = A0h] .................................................................................
New Data 56 Register [offset = A4h] .................................................................................
New Data 78 Register [offset = A8h] .................................................................................
Interrupt Pending X Register (DCAN INTPND X) [offset = ACh] .................................................
Interrupt Pending 12 Register [offset = B0h] ........................................................................
Interrupt Pending 34 Register [offset = B4h] ........................................................................
Interrupt Pending 56 Register [offset = B8h] ........................................................................
Interrupt Pending 78 Register [offset = BCh] ........................................................................
Message Valid X Register (DCAN MSGVAL X) [offset = C0h]....................................................
Message Valid 12 Register [offset = C4h] ...........................................................................
Message Valid 34 Register [offset = C8h] ...........................................................................
Message Valid 56 Register [offset = CCh] ...........................................................................
Message Valid 78 Register [offset = D0h] ...........................................................................
Interrupt Multiplexer 12 Register [offset = D8h] .....................................................................
Interrupt Multiplexer 34 Register [offset = DCh] .....................................................................
Interrupt Multiplexer 56 Register [offset = E0h] .....................................................................
Interrupt Multiplexer 78 Register [offset = E4h] .....................................................................
IF1 Command Registers (DCAN IF1CMD) [offset = 100h] ........................................................
List of Figures
1263
1268
1271
1272
1274
1275
1276
1277
1278
1282
1284
1286
1287
1288
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1290
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1300
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24-53. IF2 Command Registers (DCAN IF2CMD) [offset = 120h] ........................................................ 1300
24-54. IF1 Mask Register (DCAN IF1MSK) [offset = 104h] ................................................................ 1303
24-55. IF2 Mask Register (DCAN IF2MSK) [offset = 124h] ................................................................ 1303
24-56. IF1 Arbitration Register (DCAN IF1ARB) [offset = 108h] .......................................................... 1304
24-57. IF2 Arbitration Register (DCAN IF2ARB) [offset = 128h] .......................................................... 1304
24-58. IF1 Message Control Register (DCAN IF1MCTL) [offset = 10Ch] ................................................ 1305
24-59. IF2 Message Control Register (DCAN IF2MCTL) [offset = 12Ch] ................................................ 1305
24-60. IF1 Data A Register (DCAN IF1DATA) [offset = 110h] ............................................................. 1307
24-61. IF1 Data B Register (DCAN IF1DATB) [offset = 114h] ............................................................. 1307
24-62. IF2 Data A Register (DCAN IF2DATA) [offset = 130h] ............................................................. 1307
24-63. IF2 Data B Register (DCAN IF2DATB) [offset = 134h] ............................................................. 1307
24-64. IF3 Observation Register (DCAN IF3OBS) [offset = 140h] ........................................................ 1308
24-65. IF3 Mask Register (DCAN IF3MSK) [offset = 144h] ................................................................ 1310
24-66. IF3 Arbitration Register (DCAN IF3ARB) [offset = 148h] .......................................................... 1311
24-67. IF3 Message Control Register (DCAN IF3MCTL) [offset = 14Ch]
...............................................
1312
24-68. IF3 Data A Register (DCAN IF3DATA) [offset = 150h] ............................................................. 1313
24-69. IF3 Data B Register (DCAN IF3DATB) [offset = 154h] ............................................................. 1313
.....................................................................
.....................................................................
IF3 Update Enable 56 Register [offset = 168h] .....................................................................
IF3 Update Enable 78 Register [offset = 16Ch] .....................................................................
CAN TX IO Control Register (DCAN TIOC) [offset = 1E0h] .......................................................
CAN RX IO Control Register (DCAN RIOC) [offset = 1E4h] ......................................................
SPI Functional Logic Diagram .........................................................................................
SPI Three-Pin Operation ...............................................................................................
Operation with SPICS ..................................................................................................
Operation with SPIENA .................................................................................................
SPI Five-Pin Option with SPIENA and SPICS ......................................................................
Format for Transmitting an 12-Bit Word ..............................................................................
Format for Receiving an 10-Bit Word .................................................................................
Clock Mode with Polarity = 0 and Phase = 0 ........................................................................
Clock Mode with Polarity = 0 and Phase = 1 ........................................................................
Clock Mode with Polarity = 1 and Phase = 0 ........................................................................
Clock Mode with Polarity = 1 and Phase = 1 ........................................................................
Five Bits per Character (5-Pin Option) ...............................................................................
Typical Diagram when a Buffer in Master is in CSHOLD Mode (SPI-SPI) ......................................
Block Diagram Shift Register, MSB First .............................................................................
Block Diagram Shift Register, LSB First .............................................................................
2-data Line Mode (Phase 0, Polarity 0) ..............................................................................
Two-Pin Parallel Mode Timing Diagram (Phase 0, Polarity 0) ....................................................
4-Data Line Mode (Phase 0, Polarity 0) ..............................................................................
4 Pins Parallel Mode Timing Diagram (Phase 0, Polarity 0).......................................................
8-data Line Mode (Phase 0, Polarity 0) ..............................................................................
8 Pins Parallel Mode Timing Diagram (Phase 0, Polarity 0).......................................................
I/O Paths during I/O Loopback Modes ...............................................................................
TG Interrupt Structure ..................................................................................................
SPIFLG Interrupt Structure.............................................................................................
DMA Channel and Request Line (Logical) Structure in Multi-buffer Mode ......................................
SPI Global Control Register 0 (SPIGCR0) [offset = 00] ............................................................
24-70. IF3 Update Enable 12 Register [offset = 160h]
1314
24-71. IF3 Update Enable 34 Register [offset = 164h]
1314
24-72.
1314
24-73.
24-74.
24-75.
25-1.
25-2.
25-3.
25-4.
25-5.
25-6.
25-7.
25-8.
25-9.
25-10.
25-11.
25-12.
25-13.
25-14.
25-15.
25-16.
25-17.
25-18.
25-19.
25-20.
25-21.
25-22.
25-23.
25-24.
25-25.
25-26.
SPNU499C – March 2018
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List of Figures
Copyright © 2018, Texas Instruments Incorporated
1314
1315
1316
1322
1323
1324
1325
1326
1327
1327
1328
1328
1329
1329
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25-27. SPI Global Control Register 1 (SPIGCR1) [offset = 04h] .......................................................... 1351
25-28. SPI Interrupt Register (SPIINT0) [offset = 08h] ..................................................................... 1352
25-29. SPI Interrupt Level Register (SPILVL) [offset = 0Ch] ............................................................... 1354
..........................................................................
SPI Pin Control Register 0 (SPIPC0) [offset = 14h] ................................................................
SPI Pin Control Register 1 (SPIPC1) [offset = 18h] ...............................................................
SPI Pin Control Register 2 (SPIPC2) [offset = 1Ch] ................................................................
SPI Pin Control Register 3 (SPIPC3) [offset = 20h] ...............................................................
SPI Pin Control Register 4 (SPIPC4) [offset = 24h] ...............................................................
SPI Pin Control Register 5 (SPIPC5) [offset = 28h] ...............................................................
SPI Pin Control Register 6 (SPIPC6) [offset = 2Ch] ...............................................................
SPI Pin Control Register 7 (SPIPC7) [offset = 30h] ...............................................................
SPI Pin Control Register 8 (SPIPC8) [offset = 34h] ...............................................................
SPI Transmit Data Register 0 (SPIDAT0) [offset = 38h] ...........................................................
SPI Transmit Data Register 1 (SPIDAT1) [offset = 3Ch]...........................................................
SPI Receive Buffer Register (SPIBUF) [offset = 40h] ..............................................................
SPI Emulation Register (SPIEMU) [offset = 44h] ...................................................................
SPI Delay Register (SPIDELAY) [offset = 48h] .....................................................................
Example: tC2TDELAY= 8 VCLK Cycles....................................................................................
Example: tT2CDELAY= 4 VCLK Cycles....................................................................................
Transmit-Data-Finished-to-ENA-Inactive-Timeout ..................................................................
Chip-Select-Active-to-ENA-Signal-Active-Timeout ..................................................................
SPI Default Chip Select Register (SPIDEF) [offset = 4Ch] ........................................................
SPI Data Format Registers (SPIFMT[3:0]) [offset = 5Ch-50h] ....................................................
Interrupt Vector 0 (NTVECT0) [offset = 60h] ........................................................................
Interrupt Vector 1 (INTVECT1) [offset = 64h]........................................................................
SPI Pin Control Register 9 (SPIPC9) [offset = 68h] ...............................................................
Parallel/Modulo Mode Control Register (SPIPMCTRL) [offset = 6Ch] ...........................................
Multi-buffer Mode Enable Register (MIBSPIE) [offset = 70h]......................................................
TG Interrupt Enable Set Register (TGITENST) [offset = 74h] .....................................................
TG Interrupt Enable Clear Register (TGITENCR) [offset = 78h] ..................................................
Transfer Group Interrupt Level Set Register (TGITLVST) [offset = 7Ch] ........................................
Transfer Group Interrupt Level Clear Register (TGITLVCR) [offset = 80h] ......................................
Transfer Group Interrupt Flag Register (TGINTFLG) [offset = 84h] ..............................................
Tick Counter Operation .................................................................................................
Tick Count Register (TICKCNT) [offset = 90h] ......................................................................
Last TG End Pointer (LTGPEND) [offset = 94h] ....................................................................
MibSPI TG Control Registers (TGxCTRL) [offsets = 98h-D4h] ...................................................
DMA Channel Control Register (DMAxCTRL) [offset = D8h-F4h] ................................................
DMAxCOUNT Register (ICOUNT) [offset = F8h-114h] ............................................................
DMA Large Count Register (DMACNTLEN) [offset = 118h] .......................................................
Multi-buffer RAM Uncorrectable Parity Error Control Register (UERRCTRL) [offset = 120h] .................
Multi-buffer RAM Uncorrectable Parity Error Status Register (UERRSTAT) [offset = 124h] ..................
RXRAM Uncorrectable Parity Error Address Register (UERRADDR1) [offset = 128h] ........................
TXRAM Uncorrectable Parity Error Address Register (UERRADDR0) [offset = 12Ch] ........................
RXRAM Overrun Buffer Address Register (RXOVRN_BUF_ADDR) [offset = 130h] ...........................
I/O-Loopback Test Control Register (IOLPBKTSTCR) [offset = 134h] ...........................................
25-30. SPI Flag Register (SPIFLG) [offset = 10h]
25-31.
25-32.
25-33.
25-34.
25-35.
25-36.
25-37.
25-38.
25-39.
25-40.
25-41.
25-42.
25-43.
25-44.
25-45.
25-46.
25-47.
25-48.
25-49.
25-50.
25-51.
25-52.
25-53.
25-54.
25-55.
25-56.
25-57.
25-58.
25-59.
25-60.
25-61.
25-62.
25-63.
25-64.
25-65.
25-66.
25-67.
25-68.
25-69.
25-70.
25-71.
25-72.
25-73.
1355
1358
1359
1361
1362
1363
1365
1366
1368
1369
1370
1372
1375
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1404
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1406
1407
1408
1409
25-74. SPI Extended Prescale Register 1 (EXTENDED_PRESCALE1 for SPIFMT0 and SPIFMT1) [offset =
138h] ...................................................................................................................... 1411
56
List of Figures
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25-75. SPI Extended Prescale Register 2 (EXTENDED_PRESCALE2 for SPIFMT2 and SPIFMT3) [offset =
13Ch]...................................................................................................................... 1413
.......................................................................................
Multi-Buffer RAM Transmit Data Register (TXRAM) [offset = RAM Base + 0h-1FFh] .........................
Multi-Buffer RAM Receive Buffer Register (RXRAM) [offset = RAM Base + 200h-3FFh] .....................
Memory Map for Parity Locations During Normal and Test Mode ................................................
Example of Memory-Mapped Parity Locations During Test Mode................................................
SPI/MibSPI Pins During Master Mode 3-pin Configuration ........................................................
SPI/MibSPI Pins During Master Mode 4-pin with SPICS Configuation ..........................................
SPI/MibSPI Pins During Master Mode 4-pin with SPIENA Configuration........................................
SPI/MibSPI Pins During Master/Slave Mode with 5-pin Configuration ...........................................
SPI/MibSPI Pins During Slave Mode 3-pin Configuration .........................................................
SPI/MibSPI Pins During Slave Mode 4-pin with SPIENA Configuration .........................................
SPI/MibSPI Pins During Slave Mode in 5-pin Configuration - (Single Slave) ...................................
SPI/MibSPI Pins During Slave Mode in 5-pin Configuration - (Single/Multi Slave) .............................
Detailed SCI Block Diagram ...........................................................................................
SCI/LIN Block Diagram .................................................................................................
Typical SCI Data Frame Formats .....................................................................................
Asynchronous Communication Bit Timing ...........................................................................
Superfractional Divider Example ......................................................................................
Idle-Line Multiprocessor Communication Format ...................................................................
Address-Bit Multiprocessor Communication Format................................................................
Receive Buffers ..........................................................................................................
Transmit Buffers .........................................................................................................
General Interrupt Scheme ..............................................................................................
Interrupt Generation for Given Flags .................................................................................
LIN Protocol Message Frame Format: Master Header and Slave Response ...................................
Header 3 Fields: Synch Break, Synch, and ID ......................................................................
Response Format of LIN Message Frame ...........................................................................
Message Header in Terms of Tbit ......................................................................................
ID Field ...................................................................................................................
Measurements for Synchronization ...................................................................................
Synchronization Validation Process and Baud Rate Adjustment .................................................
Optional Embedded Checksum in Response for Extended Frames .............................................
Checksum Compare and Send for Extended Frames..............................................................
TXRX Error Detector ....................................................................................................
Classic Checksum Generation at Transmitting Node ..............................................................
LIN 2.0-Compliant Checksum Generation at Transmitting Node .................................................
ID Reception, Filtering and Validation ................................................................................
LIN Message Frame Showing LIN Interrupt Timing and Sequence ..............................................
Wakeup Signal Generation ............................................................................................
SCI Global Control Register 0 (SCIGCR0) [offset = 00] ...........................................................
SCI Global Control Register 1 (SCIGCR1) [offset = 04h] ..........................................................
SCI Global Control Register 2 (SCIGCR2) [offset = 08h] ..........................................................
SCI Set Interrupt Register (SCISETINT) [offset = 0Ch] ............................................................
SCI Clear Interrupt Register (SCICLEARINT) [offset = 10h] ......................................................
SCI Set Interrupt Level Register (SCISETINTLVL) [offset = 14h] ................................................
SCI Clear Interrupt Level Register (SCICLEARINTLVL) [offset = 18h] ..........................................
SCI Flags Register (SCIFLR) [offset = 1Ch] .........................................................................
25-76. Multi-Buffer RAM Configuration
25-77.
25-78.
25-79.
25-80.
25-81.
25-82.
25-83.
25-84.
25-85.
25-86.
25-87.
25-88.
26-1.
26-2.
26-3.
26-4.
26-5.
26-6.
26-7.
26-8.
26-9.
26-10.
26-11.
26-12.
26-13.
26-14.
26-15.
26-16.
26-17.
26-18.
26-19.
26-20.
26-21.
26-22.
26-23.
26-24.
26-25.
26-26.
26-27.
26-28.
26-29.
26-30.
26-31.
26-32.
26-33.
26-34.
SPNU499C – March 2018
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List of Figures
Copyright © 2018, Texas Instruments Incorporated
1415
1417
1420
1423
1424
1425
1425
1426
1426
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1427
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26-35. SCI Interrupt Vector Offset 0 (SCIINTVECT0) [offset = 20h] ...................................................... 1502
26-36. SCI Interrupt Vector Offset 1 (SCIINTVECT1) [offset = 24h] ...................................................... 1502
26-37. SCI Format Control Register (SCIFORMAT) [offset = 28h]
.......................................................
1503
26-38. Baud Rate Selection Register (BRS) [offset = 2Ch] ................................................................ 1504
26-39. Receiver Emulation Data Buffer (SCIED) [offset = 30h]
...........................................................
1505
26-40. Receiver Data Buffer (SCIRD) [offset = 34h] ........................................................................ 1506
26-41. Transmit Data Buffer Register (SCITD) [offset = 38h] .............................................................. 1507
26-42. SCI Pin I/O Control Register 0 (SCIPIO0) [offset = 3Ch]
.........................................................
1507
26-43. SCI Pin I/O Control Register 1 (SCIPIO1) [offset = 40h] ........................................................... 1508
26-44. SCI Pin I/O Control Register 2 (SCIPIO2) [offset = 44h]
..........................................................
1509
26-45. SCI Pin I/O Control Register 3 (SCIPIO3) [offset = 48h] ........................................................... 1510
26-46. SCI Pin I/O Control Register 4 (SCIPIO4) [offset = 4Ch]
.........................................................
1511
26-47. SCI Pin I/O Control Register 5 (SCIPIO5) [offset = 50h] ........................................................... 1512
1513
26-49.
1514
26-50.
26-51.
26-52.
26-53.
26-54.
26-55.
26-56.
26-57.
26-58.
26-59.
26-60.
27-1.
27-2.
27-3.
27-4.
27-5.
27-6.
27-7.
27-8.
27-9.
27-10.
27-11.
27-12.
27-13.
27-14.
27-15.
27-16.
27-17.
27-18.
27-19.
27-20.
27-21.
27-22.
27-23.
58
..........................................................
SCI Pin I/O Control Register 7 (SCIPIO7) [offset = 58h] ...........................................................
SCI Pin I/O Control Register 8 (SCIPIO8) [offset = 5Ch] .........................................................
LIN Compare Register (LINCOMPARE) [offset = 60h] .............................................................
LIN Receive Buffer 0 Register (LINRD0) [offset = 64h] ............................................................
LIN Receive Buffer 1 Register (RD1) [offset = 68h] ................................................................
LIN Mask Register (LINMASK) [offset = 6Ch] .......................................................................
LIN Identification Register (LINID) [offset = 70h] ....................................................................
LIN Transmit Buffer 0 Register (LINTD0) [offset = 74h] ............................................................
LIN Transmit Buffer 1 Register (LINTD1) [offset = 78h] ............................................................
Maximum Baud Rate Selection Register (MBRS) [offset = 7Ch] .................................................
Input/Output Error Enable Register (IODFTCTRL) [offset = 90h] .................................................
GPIO Functionality ......................................................................................................
Detailed SCI Block Diagram ...........................................................................................
Typical SCI Data Frame Formats .....................................................................................
Asynchronous Communication Bit Timing ...........................................................................
Idle-Line Multiprocessor Communication Format ...................................................................
Address-Bit Multiprocessor Communication Format................................................................
General Interrupt Scheme ..............................................................................................
Interrupt Generation for Given Flags .................................................................................
SCI Global Control Register 0 (SCIGCR0) [offset = 00] ...........................................................
SCI Global Control Register 1 (SCIGCR1) [offset = 04h] ..........................................................
SCI Set Interrupt Register (SCISETINT) [offset = 0Ch] ............................................................
SCI Clear Interrupt Register (SCICLEARINT) [offset = 10h] ......................................................
SCI Set Interrupt Level Register (SCISETINTLVL) [offset = 14h] ................................................
SCI Clear Interrupt Level Register (SCICLEARINTLVL) [offset = 18h] ..........................................
SCI Flags Register (SCIFLR) [offset = 1Ch] .........................................................................
SCI Interrupt Vector Offset 0 (SCIINTVECT0) [offset = 20h] ......................................................
SCI Interrupt Vector Offset 1 (SCIINTVECT1) [offset = 24h] ......................................................
SCI Format Control Register (SCIFORMAT) [offset = 28h] .......................................................
Baud Rate Selection Register (BRS) [offset = 2Ch] ................................................................
Receiver Emulation Data Buffer (SCIED) [offset = 30h] ...........................................................
Receiver Data Buffer (SCIRD) [offset = 34h] ........................................................................
Transmit Data Buffer Register (SCITD) [offset = 38h] ..............................................................
SCI Pin I/O Control Register 0 (SCIPIO0) [offset = 3Ch] .........................................................
SCI Pin I/O Control Register 1 (SCIPIO1) [offset = 40h] ...........................................................
26-48. SCI Pin I/O Control Register 6 (SCIPIO6) [offset = 54h]
List of Figures
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1561
SPNU499C – March 2018
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..........................................................
SCI Pin I/O Control Register 3 (SCIPIO3) [offset = 48h] ...........................................................
SCI Pin I/O Control Register 4 (SCIPIO4) [offset = 4Ch] .........................................................
SCI Pin I/O Control Register 5 (SCIPIO5) [offset = 50h] ...........................................................
SCI Pin I/O Control Register 6 (SCIPIO6) [offset = 54h] ..........................................................
SCI Pin I/O Control Register 7 (SCIPIO7) [offset = 58h] ...........................................................
SCI Pin I/O Control Register 8 (SCIPIO8) [offset = 5Ch] .........................................................
Input/Output Error Enable Register (IODFTCTRL) [offset = 90h] .................................................
GPIO Functionality ......................................................................................................
Multiple I2C Modules Connection Diagram ..........................................................................
Simple I2C Block Diagram .............................................................................................
Clocking Diagram for the I2C Module ................................................................................
Bit Transfer on the I2C Bus ............................................................................................
I2C Module START and STOP Conditions ..........................................................................
I2C Module Data Transfer..............................................................................................
I2C Module 7-Bit Addressing Format .................................................................................
I2C Module 10-bit Addressing Format ................................................................................
I2C Module 7-Bit Addressing Format with Repeated START .....................................................
I2C Module in Free Data Format ......................................................................................
Arbitration Procedure Between Two Master Transmitters .........................................................
Synchronization of Two I2C Clock Generators During Arbitration ................................................
I2C Own Address Manager Register (I2COAR) [offset = 00h] ....................................................
I2C Interrupt Mask Register (I2CIMR) [offset = 04h] ...............................................................
I2C Status Register (I2CSR) [offset = 08h] ..........................................................................
I2C Clock Divider Low Register (I2CCKL) [offset = 0Ch] ..........................................................
I2C Clock Control High Register (I2CCKH) [offset = 10h] .........................................................
I2C Data Count Register (I2CCNT) [offset = 14h] ..................................................................
I2C Data Receive Register (I2CDRR) [offset = 18h] ...............................................................
I2C Slave Address Register (I2CSAR) [offset = 1Ch] ..............................................................
I2C Data Transmit Register (I2CDXR) [offset = 20h] ...............................................................
I2C Mode Register (I2CMDR) [offset = 24h] .........................................................................
Typical Timing Diagram of Repeat Mode ............................................................................
I2C Interrupt Vector Register (I2CIVR) [offset = 28h] ..............................................................
I2C Extended Mode Register (I2CEMDR) [offset = 2Ch] ..........................................................
I2C Prescale Register (I2CPSC) [offset = 30h] .....................................................................
I2C Peripheral ID Register 1 (I2CPID1) [offset = 34h] .............................................................
I2C Peripheral ID Register 2 (I2CPID2) [offset = 38h] .............................................................
I2C DMA Control Register (I2CDMACR) [offset = 3Ch] ............................................................
I2C Pin Function Register (I2CPFNC) [offset = 48h] ...............................................................
I2C Pin Direction Register (I2CPDIR) [offset = 4Ch] ...............................................................
I2C Data Input Register (I2CDIN) [offset = 50h] ....................................................................
I2C Data Output Register (I2CDOUT) [offset 0x54] ................................................................
I2C Data Set Register (I2CDSET) [offset = 58h] ....................................................................
I2C Data Clear Register (I2CDCLR) [offset = 5Ch] .................................................................
I2C Pin Open Drain Register (I2CPDR) [offset = 60h] .............................................................
I2C Pull Disable Register (I2CPDIS) [offset = 64h] .................................................................
I2C Pull Select Register (I2CPSEL) [offset = 68h] ..................................................................
I2C Pins Slew Rate Select Register (I2CSRS) [offset = 6Ch] .....................................................
Difference between Normal Operation and Backward Compatibility Mode......................................
27-24. SCI Pin I/O Control Register 2 (SCIPIO2) [offset = 44h]
1562
27-25.
1563
27-26.
27-27.
27-28.
27-29.
27-30.
27-31.
27-32.
28-1.
28-2.
28-3.
28-4.
28-5.
28-6.
28-7.
28-8.
28-9.
28-10.
28-11.
28-12.
28-13.
28-14.
28-15.
28-16.
28-17.
28-18.
28-19.
28-20.
28-21.
28-22.
28-23.
28-24.
28-25.
28-26.
28-27.
28-28.
28-29.
28-30.
28-31.
28-32.
28-33.
28-34.
28-35.
28-36.
28-37.
28-38.
28-39.
28-40.
SPNU499C – March 2018
Submit Documentation Feedback
List of Figures
Copyright © 2018, Texas Instruments Incorporated
1564
1565
1566
1567
1567
1568
1570
1573
1575
1576
1577
1578
1578
1579
1579
1579
1580
1583
1584
1589
1590
1591
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1594
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1595
1596
1596
1597
1599
1600
1601
1601
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1602
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1603
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1605
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1608
1609
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29-1.
29-2.
29-3.
29-4.
29-5.
29-6.
29-7.
29-8.
29-9.
29-10.
29-11.
29-12.
29-13.
29-14.
29-15.
29-16.
29-17.
29-18.
29-19.
29-20.
29-21.
29-22.
29-23.
29-24.
29-25.
29-26.
29-27.
29-28.
29-29.
29-30.
29-31.
29-32.
29-33.
29-34.
29-35.
29-36.
29-37.
29-38.
29-39.
29-40.
29-41.
29-42.
29-43.
29-44.
29-45.
29-46.
29-47.
29-48.
29-49.
60
.....................................................................................
Ethernet Configuration—MII Connections ...........................................................................
Ethernet Configuration—RMII Connections..........................................................................
Ethernet Frame Format .................................................................................................
Basic Descriptor Format ................................................................................................
Typical Descriptor Linked List .........................................................................................
Transmit Packet Add Flow Chart ......................................................................................
Generate Transmit Packet Flow Chart ...............................................................................
Transmit Queue Interrupt Processing Flow Chart ..................................................................
Transmit Buffer Descriptor Format ....................................................................................
Receive Buffer Descriptor Format.....................................................................................
EMAC Control Module Block Diagram ...............................................................................
MDIO Module Block Diagram ..........................................................................................
EMAC Module Block Diagram .........................................................................................
EMAC Control Module Revision ID Register (REVID) .............................................................
EMAC Control Module Software Reset Register (SOFTRESET) .................................................
EMAC Control Module Interrupt Control Register (INTCONTROL) ..............................................
EMAC Control Module Receive Threshold Interrupt Enable Register (C0RXTHRESHEN) ...................
EMAC Control Module Receive Interrupt Enable Register (C0RXEN) ...........................................
EMAC Control Module Transmit Interrupt Enable Register (C0TXEN) ..........................................
EMAC Control Module Miscellaneous Interrupt Enable Register (C0MISCEN) ................................
EMAC Control Module Receive Threshold Interrupt Status Register (C0RXTHRESHSTAT) ................
EMAC Control Module Receive Interrupt Status Register (C0RXSTAT) ........................................
EMAC Control Module Transmit Interrupt Status Register (C0TXSTAT) ........................................
EMAC Control Module Miscellaneous Interrupt Status Register (C0MISCSTAT) ..............................
EMAC Control Module Receive Interrupts Per Millisecond Register (C0RXIMAX) .............................
EMAC Control Module Transmit Interrupts Per Millisecond Register (C0TXIMAX) ............................
MDIO Revision ID Register (REVID) .................................................................................
MDIO Control Register (CONTROL)..................................................................................
PHY Acknowledge Status Register (ALIVE) .........................................................................
PHY Link Status Register (LINK)......................................................................................
MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) .....................................
MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) ...................................
MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) ............................
MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) ..........................
MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) ........................
MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) ..................
MDIO User Access Register 0 (USERACCESS0) ..................................................................
MDIO User PHY Select Register 0 (USERPHYSEL0) .............................................................
MDIO User Access Register 1 (USERACCESS1) ..................................................................
MDIO User PHY Select Register 1 (USERPHYSEL1) .............................................................
Transmit Revision ID Register (TXREVID) ..........................................................................
Transmit Control Register (TXCONTROL) ...........................................................................
Transmit Teardown Register (TXTEARDOWN) .....................................................................
Receive Revision ID Register (RXREVID) ...........................................................................
Receive Control Register (RXCONTROL) ...........................................................................
Receive Teardown Register (RXTEARDOWN) .....................................................................
Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) .............................................
Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) ...........................................
EMAC and MDIO Block Diagram
List of Figures
1612
1614
1616
1618
1619
1620
1622
1623
1624
1626
1629
1633
1635
1639
1661
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1689
1689
1690
1690
1691
1691
1692
1693
SPNU499C – March 2018
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29-50. Transmit Interrupt Mask Set Register (TXINTMASKSET) ......................................................... 1694
29-51. Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) ................................................... 1695
29-52. MAC Input Vector Register (MACINVECTOR) ...................................................................... 1696
29-53. MAC End Of Interrupt Vector Register (MACEOIVECTOR) ....................................................... 1697
29-54. Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW)
.............................................
1698
29-55. Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) ............................................ 1699
29-56. Receive Interrupt Mask Set Register (RXINTMASKSET) .......................................................... 1700
29-57. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)
...................................................
1701
29-58. MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) ............................................... 1702
29-59. MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) ............................................. 1702
29-60. MAC Interrupt Mask Set Register (MACINTMASKSET) ........................................................... 1703
29-61. MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) ..................................................... 1703
29-62. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE)..................... 1704
29-63. Receive Unicast Enable Set Register (RXUNICASTSET) ......................................................... 1706
29-64. Receive Unicast Clear Register (RXUNICASTCLEAR) ............................................................ 1707
29-65. Receive Maximum Length Register (RXMAXLEN) ................................................................. 1707
29-66. Receive Buffer Offset Register (RXBUFFEROFFSET)
............................................................
1708
29-67. Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) ............................ 1708
...................................
Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) ...........................................
MAC Control Register (MACCONTROL) .............................................................................
MAC Status Register (MACSTATUS) ................................................................................
Emulation Control Register (EMCONTROL).........................................................................
FIFO Control Register (FIFOCONTROL) ............................................................................
MAC Configuration Register (MACCONFIG) ........................................................................
Soft Reset Register (SOFTRESET) ..................................................................................
MAC Source Address Low Bytes Register (MACSRCADDRLO) .................................................
MAC Source Address High Bytes Register (MACSRCADDRHI) .................................................
MAC Hash Address Register 1 (MACHASH1) ......................................................................
MAC Hash Address Register 2 (MACHASH2) ......................................................................
Back Off Random Number Generator Test Register (BOFFTEST) ..............................................
Transmit Pacing Algorithm Test Register (TPACETEST) ..........................................................
Receive Pause Timer Register (RXPAUSE).........................................................................
Transmit Pause Timer Register (TXPAUSE) ........................................................................
MAC Address Low Bytes Register (MACADDRLO) ................................................................
MAC Address High Bytes Register (MACADDRHI) ................................................................
MAC Index Register (MACINDEX) ....................................................................................
Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP) ........................................
Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP) .........................................
Transmit Channel n Completion Pointer Register (TXnCP) .......................................................
Receive Channel n Completion Pointer Register (RXnCP) ........................................................
Statistics Register .......................................................................................................
DMM Block Diagram ....................................................................................................
Trace Mode Packet Format ............................................................................................
Direct Data Mode Packet Format .....................................................................................
Packet Sync Signal Example ..........................................................................................
Example Single Packet Transmission ................................................................................
Interrupt Structure .......................................................................................................
DMM Global Control Register (DMMGLBCTRL) [offset = 00h] ...................................................
29-68. Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH)
1709
29-69.
1709
29-70.
29-71.
29-72.
29-73.
29-74.
29-75.
29-76.
29-77.
29-78.
29-79.
29-80.
29-81.
29-82.
29-83.
29-84.
29-85.
29-86.
29-87.
29-88.
29-89.
29-90.
29-91.
30-1.
30-2.
30-3.
30-4.
30-5.
30-6.
30-7.
SPNU499C – March 2018
Submit Documentation Feedback
List of Figures
Copyright © 2018, Texas Instruments Incorporated
1710
1712
1714
1714
1715
1715
1716
1716
1717
1717
1718
1718
1719
1719
1720
1721
1721
1722
1722
1723
1723
1724
1734
1736
1736
1738
1738
1739
1741
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30-8.
DMM Interrupt Set Register (DMMINTSET) [offset = 04h]......................................................... 1743
30-9.
DMM Interrupt Clear Register (DMMINTCLR) [offset = 08h] ...................................................... 1747
30-10. DMM Interrupt Level Register (DMMINTLVL) [offset = 0Ch] ...................................................... 1752
1754
30-12.
1758
30-13.
30-14.
30-15.
30-16.
30-17.
30-18.
30-19.
30-20.
30-21.
30-22.
30-23.
30-24.
30-25.
30-26.
30-27.
30-28.
30-29.
30-30.
31-1.
31-2.
31-3.
31-4.
31-5.
31-6.
31-7.
31-8.
31-9.
31-10.
31-11.
31-12.
31-13.
31-14.
31-15.
31-16.
31-17.
31-18.
31-19.
31-20.
31-21.
31-22.
31-23.
31-24.
32-1.
32-2.
62
.......................................................
DMM Interrupt Offset 1 Register (DMMOFF1) [offset = 14h] ......................................................
DMM Interrupt Offset 2 Register (DMMOFF2) [offset = 18h] ......................................................
DMM Direct Data Mode Destination Register (DMMDDMDEST) [offset = 1Ch] ................................
DMM Direct Data Mode Blocksize Register (DMMDDMBL) [offset = 20h] ......................................
DMM Direct Data Mode Pointer Register (DMMDDMPT) [offset = 24h] .........................................
DMM Direct Data Mode Interrupt Pointer Register (DMMINTPT) [offset = 28h] ................................
DMM Destination x Region 1 (DMMDESTxREG1) [offset = 2Ch, 3Ch, 4Ch, 5Ch] .............................
DMM Destination x Blocksize 1 (DMMDESTxBL1) [offset = 30h, 40h, 50h, 60h] ..............................
DMM Destination x Region 2 (DMMDESTxREG2) [offset = 34h, 44h, 54h, 64h] ..............................
DMM Destination x Blocksize 2 (DMMDESTxBL2) [offset = 38h, 48h, 58h, 68h] ..............................
DMM Pin Control 0 (DMMPC0) [offset = 6Ch] ......................................................................
DMM Pin Control 1 (DMMPC1) [offset = 70h] .......................................................................
DMM Pin Control 2 (DMMPC2) [offset = 74h] .......................................................................
DMM Pin Control 3 (DMMPC3) [offset = 78h] .......................................................................
DMM Pin Control 4 (DMMPC4) [offset = 7Ch] ......................................................................
DMM Pin Control 5 (DMMPC5) [offset = 80h] .......................................................................
DMM Pin Control 6 (DMMPC6) [offset = 84h] .......................................................................
DMM Pin Control 7 (DMMPC7) [offset = 88h] .......................................................................
DMM Pin Control 8 (DMMPC8) [offset = 8Ch] ......................................................................
Block Diagram RAM Trace Port Module .............................................................................
Packet Format Trace Mode for RAM Locations .....................................................................
Packet Format Trace Mode for Peripheral Locations ..............................................................
Packet Format in Direct Data Mode ..................................................................................
Example for Trace Region Setup .....................................................................................
FIFO Overflow Handling ................................................................................................
RTP Packet Transfer with Sync Signal ...............................................................................
Packet Format in Trace Mode .........................................................................................
RTP Global Control Register (RTPGLBCTRL) [offset = 00h] .....................................................
RTP Trace Enable Register (RTPTRENA) [offset = 04h] ..........................................................
RTP Global Status Register (RTPGSR) [offset = 08h] .............................................................
RTP RAM 1 Trace Region [1:2] Register (RTPRAM1REG[1:2]) [offset = 0Ch, 10h]...........................
RTP RAM 2 Trace Region [1:2] Register (RTPRAM2REG[1:2]) [offset = 14h, 18h] ...........................
RTP Peripheral Trace Region [1:2] Register (RTPPERREG[1:2]) [offset = 24h, 28h] .........................
RTP Direct Data Mode Write Register (RTPDDMW) [offset = 2Ch] ..............................................
RTP Pin Control 0 Register (RTPPC0) [offset = 34h] ..............................................................
RTP Pin Control 1 Register (RTPPC1) [offset = 38h] ..............................................................
RTP Pin Control 2 Register (RTPPC2) [offset = 3Ch] ..............................................................
RTP Pin Control 3 Register (RTPPC3) [offset = 40h] ..............................................................
RTP Pin Control 4 Register (RTPPC4) [offset = 44h] ..............................................................
RTP Pin Control 5 Register (RTPPC5) [offset = 48h] ..............................................................
RTP Pin Control 6 Register (RTPPC6) [offset = 4Ch] ..............................................................
RTP Pin Control 7 Register (RTPPC7) [offset = 50h] ..............................................................
RTP Pin Control 8 Register (RTPPC8) [offset = 54h] ..............................................................
eFuse Self Test Flow Chart ............................................................................................
EFC Boundary Control Register (EFCBOUND) [offset = 1Ch] ....................................................
30-11. DMM Interrupt Flag Register (DMMINTFLG) [offset = 10h]
List of Figures
1759
1760
1760
1761
1761
1762
1763
1764
1765
1766
1767
1769
1770
1771
1773
1774
1776
1777
1780
1781
1781
1783
1784
1785
1786
1786
1788
1791
1792
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1806
1807
1811
1812
SPNU499C – March 2018
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32-3.
32-4.
32-5.
32-6.
......................................................................
EFC Error Status Register (EFCERRSTAT) [offset = 3Ch] ........................................................
EFC Self Test Cycles Register (EFCSTCY) [offset = 48h] ........................................................
EFC Self Test Cycles Register (EFCSTSIG) [offset = 4Ch] .......................................................
EFC Pins Register (EFCPINS) [offset = 2Ch]
SPNU499C – March 2018
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List of Figures
Copyright © 2018, Texas Instruments Incorporated
1814
1815
1815
1816
63
www.ti.com
List of Tables
2-1.
Definition of Terms........................................................................................................ 100
2-2.
Bus Master / Slave Access Privileges
2-3.
2-4.
2-5.
2-6.
2-7.
2-8.
2-9.
2-10.
2-11.
2-12.
2-13.
2-14.
2-15.
2-16.
2-17.
2-18.
2-19.
2-20.
2-21.
2-22.
2-23.
2-24.
2-25.
2-26.
2-27.
2-28.
2-29.
2-30.
2-31.
2-32.
2-33.
2-34.
2-35.
2-36.
2-37.
2-38.
2-39.
2-40.
2-41.
2-42.
2-43.
2-44.
2-45.
2-46.
2-47.
64
.................................................................................
Module Registers / Memories Memory-Map ..........................................................................
Flash Memory Banks and Sectors......................................................................................
PBIST Memory Grouping ................................................................................................
PBIST Algorithm Mapping ...............................................................................................
Memory Initialization Select Mapping .................................................................................
Causes of Resets .........................................................................................................
Clock Sources .............................................................................................................
Clock Domains ............................................................................................................
Typical Low-Power Modes...............................................................................................
Clock Test Mode Options ................................................................................................
EXTCTL_Out_Port Register Field Descriptions ......................................................................
DCC1 Counter 0 Clock Inputs ..........................................................................................
DCC1 Counter 1 Clock / Signal Inputs .................................................................................
DCC2 Counter 0 Clock Inputs ..........................................................................................
DCC2 Counter 1 Clock / Signal Inputs .................................................................................
Primary System Control Registers .....................................................................................
SYS Pin Control Register 1 (SYSPC1) Field Descriptions ..........................................................
SYS Pin Control Register 2 (SYSPC2) Field Descriptions ..........................................................
SYS Pin Control Register 3 (SYSPC3) Field Descriptions ..........................................................
SYS Pin Control Register 4 (SYSPC4) Field Descriptions ..........................................................
SYS Pin Control Register 5 (SYSPC5) Field Descriptions ..........................................................
SYS Pin Control Register 6 (SYSPC6) Field Descriptions ..........................................................
SYS Pin Control Register 7 (SYSPC7) Field Descriptions ..........................................................
SYS Pin Control Register 8 (SYSPC8) Field Descriptions ..........................................................
SYS Pin Control Register 9 (SYSPC9) Field Descriptions ..........................................................
Clock Source Disable Register (CSDIS) Field Descriptions ........................................................
Clock Sources Table .....................................................................................................
Clock Source Disable Set Register (CSDISSET) Field Descriptions ..............................................
Clock Source Disable Clear Register (CSDISCLR) Field Descriptions ............................................
Clock Domain Disable Register (CDDIS) Field Descriptions .......................................................
Clock Domain Disable Set Register (CDDISSET) Field Descriptions .............................................
Clock Domain Disable Clear Register (CDDISCLR) Field Descriptions ...........................................
GCLK, HCLK, VCLK, and VCLK2 Source Register (GHVSRC) Field Descriptions .............................
Peripheral Asynchronous Clock Source Register (VCLKASRC) Field Descriptions .............................
RTI Clock Source Register (RCLKSRC) Field Descriptions ........................................................
Clock Source Valid Register (CSVSTAT) Field Descriptions .......................................................
Memory Self-Test Global Control Register (MSTGCR) Field Descriptions .......................................
Memory Hardware Initialization Global Control Register (MINITGCR) Field Descriptions ......................
MBIST Controller/Memory Initialization Enable Register (MSINENA) Field Descriptions .......................
MSTC Global Status Register (MSTCGSTAT) Field Descriptions .................................................
Memory Hardware Initialization Status Register (MINISTAT) Field Descriptions ................................
PLL Control Register 1 (PLLCTL1) Field Descriptions ..............................................................
PLL Control Register 2 (PLLCTL2) Field Descriptions ..............................................................
SYS Pin Control Register 10 (SYSPC10) Field Descriptions .......................................................
Die Identification Register, Lower Word (DIEIDL) Field Descriptions ..............................................
List of Tables
102
104
108
110
111
114
115
118
119
122
123
124
126
126
126
126
127
129
129
130
130
131
131
132
132
133
134
134
135
136
137
139
141
143
144
145
146
147
148
149
150
151
152
153
154
155
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2-48.
Die Identification Register, Upper Word (DIEIDH) Field Descriptions ............................................. 155
2-49.
LPO/Clock Monitor Control Register (LPOMONCTL) Field Descriptions.......................................... 156
2-50.
Clock Test Register (CLKTEST) Field Descriptions.................................................................. 159
2-51.
DFT Control Register (DFTCTRLREG) Field Descriptions .......................................................... 161
2-52.
DFT Control Register 2 (DFTCTRLREG2) Field Descriptions
2-53.
General Purpose Register (GPREG1) Field Descriptions ........................................................... 163
2-54.
Imprecise Fault Status Register (IMPFASTS) Field Descriptions .................................................. 165
2-55.
Imprecise Fault Write Address Register (IMPFTADD) Field Descriptions
2-56.
System Software Interrupt Request 1 Register (SSIR1) Field Descriptions ...................................... 167
2-57.
System Software Interrupt Request 2 Register (SSIR2) Field Descriptions ...................................... 167
2-58.
System Software Interrupt Request 3 Register (SSIR3) Field Descriptions ...................................... 168
2-59.
System Software Interrupt Request 4 Register (SSIR4) Field Descriptions ...................................... 168
2-60.
RAM Control Register (RAMGCR) Field Descriptions ............................................................... 169
2-61.
Bus Matrix Module Control Register 1 (BMMCR) Field Descriptions .............................................. 170
2-62.
CPU Reset Control Register (CPURSTGCR) Field Descriptions
2-63.
Clock Control Register (CLKCNTL) Field Descriptions .............................................................. 172
2-64.
ECP Control Register (ECPCNTL) Field Descriptions ............................................................... 173
2-65.
DEV Parity Control Register 1 (DEVCR1) Field Descriptions
2-66.
System Exception Control Register (SYSECR) Field Descriptions ................................................ 174
2-67.
System Exception Status Register (SYSESR) Field Descriptions
175
2-68.
System Test Abort Status Register (SYSTASR) Field Descriptions
176
2-69.
2-70.
2-71.
2-72.
2-73.
2-74.
2-75.
2-76.
2-77.
2-78.
2-79.
2-80.
2-81.
2-82.
2-83.
2-84.
2-85.
2-86.
2-87.
2-88.
2-89.
2-90.
2-91.
2-92.
2-93.
2-94.
2-95.
2-96.
.....................................................
........................................
..................................................
......................................................
.................................................
..............................................
Global Status Register (GLBSTAT) Field Descriptions ..............................................................
Device Identification Register (DEVID) Field Descriptions ..........................................................
Software Interrupt Vector Register (SSIVEC) Field Descriptions ..................................................
System Software Interrupt Flag Register (SSIF) Field Descriptions ...............................................
Secondary System Control Registers ..................................................................................
PLL Control Register 3 (PLLCTL3) Field Descriptions ..............................................................
CPU Logic BIST Clock Prescaler (STCLKDIV) Field Descriptions .................................................
Clock 2 Control Register (CLK2CNTRL) Field Descriptions .......................................................
Peripheral Asynchronous Clock Configuration 1 Register (VCLKACON1) Field Descriptions ................
Clock Slip Register (CLKSLIP) Field Descriptions ...................................................................
EFUSE Controller Control Register (EFC_CTLREG) Field Descriptions ..........................................
Die Identification Register, Lower Word (DIEIDL_REG0) Field Descriptions .....................................
Die Identification Register, Upper Word (DIEIDH_REG1) Field Descriptions ....................................
Die Identification Register, Lower Word (DIEIDL_REG2) Field Descriptions .....................................
Die Identification Register, Upper Word (DIEIDH_REG3) Field Descriptions ....................................
Peripheral Central Resource Control Registers ......................................................................
Peripheral Memory Protection Set Register 0 (PMPROTSET0) Field Descriptions .............................
Peripheral Memory Protection Set Register 1 (PMPROTSET1) Field Descriptions .............................
Peripheral Memory Protection Clear Register 0 (PMPROTCLR0) Field Descriptions ...........................
Peripheral Memory Protection Clear Register 1 (PMPROTCLR1) Field Descriptions ...........................
Peripheral Protection Set Register 0 (PPROTSET0) Field Descriptions ..........................................
Peripheral Protection Set Register 1 (PPROTSET1) Field Descriptions ..........................................
Peripheral Protection Set Register 2 (PPROTSET2) Field Descriptions ..........................................
Peripheral Protection Set Register 3 (PPROTSET3) Field Descriptions ..........................................
Peripheral Protection Clear Register 0 (PPROTCLR0) Field Descriptions .......................................
Peripheral Protection Clear Register 1 (PPROTCLR1) Field Descriptions .......................................
Peripheral Protection Clear Register 2 (PPROTCLR2) Field Descriptions .......................................
Peripheral Protection Clear Register 3 (PPROTCLR3) Field Descriptions .......................................
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List of Tables
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162
166
171
174
177
178
179
180
181
182
183
183
184
185
186
186
187
187
188
189
190
190
191
191
192
193
193
194
194
195
195
196
65
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2-97.
Peripheral Memory Power-Down Set Register 0 (PCSPWRDWNSET0) Field Descriptions ................... 197
2-98.
Peripheral Memory Power-Down Set Register 1 (PCSPWRDWNSET1) Field Descriptions ................... 197
2-99.
Peripheral Memory Power-Down Clear Register 0 (PCSPWRDWNCLR0) Field Descriptions ................. 198
2-100. Peripheral Memory Power-Down Set Register 1 (PCSPWRDWNCLR1) Field Descriptions ................... 198
2-101. Peripheral Power-Down Set Register 0 (PSPWRDWNSET0) Field Descriptions ................................ 199
2-102. Peripheral Power-Down Set Register 1 (PSPWRDWNSET1) Field Descriptions ................................ 200
2-103. Peripheral Power-Down Set Register 2 (PSPWRDWNSET2) Field Descriptions ................................ 200
2-104. Peripheral Power-Down Set Register 3 (PSPWRDWNSET3) Field Descriptions ................................ 201
2-105. Peripheral Power-Down Clear Register 0 (PSPWRDWNCLR0) Field Descriptions ............................. 201
2-106. Peripheral Power-Down Clear Register 1 (PSPWRDWNCLR1) Field Descriptions ............................. 202
2-107. Peripheral Power-Down Clear Register 2 (PSPWRDWNCLR2) Field Descriptions ............................. 202
2-108. Peripheral Power-Down Clear Register 3 (PSPWRDWNCLR3) Field Descriptions ............................. 203
3-1.
PMM Registers ............................................................................................................ 211
3-2.
Logic Power Domain Control Register (LOGICPDPWRCTRL0) Field Descriptions ............................. 212
3-3.
Memory Power Domain Control Register 0 (MEMPDPWRCTRL0) Field Descriptions
213
3-4.
Power Domain Clock Disable Register (PDCLKDISREG) Field Descriptions
214
3-5.
3-6.
3-7.
3-8.
3-9.
3-10.
3-11.
3-12.
3-13.
3-14.
3-15.
3-16.
3-17.
3-18.
3-19.
3-20.
3-21.
4-1.
4-2.
4-3.
4-4.
4-5.
4-6.
4-7.
4-8.
4-9.
4-10.
4-11.
4-12.
4-13.
4-14.
4-15.
4-16.
66
.........................
...................................
Power Domain Clock Disable Set Register (PDCLKDISSETREG) Field Descriptions .........................
Power Domain Clock Disable Clear Register (PDCLKDISCLRREG) Field Descriptions .......................
Logic Power Domain PD2 Power Status Register (LOGICPDPWRSTAT0) Field Descriptions ...............
Logic Power Domain PD3 Power Status Register (LOGICPDPWRSTAT1) Field Descriptions ...............
Logic Power Domain PD4 Power Status Register (LOGICPDPWRSTAT2) Field Descriptions ...............
Logic Power Domain PD5 Power Status Register (LOGICPDPWRSTAT3) Field Descriptions ...............
Memory Power Domain RAM_PD1 Power Status Register (MEMPDPWRSTAT0) Field Descriptions ......
Memory Power Domain RAM_PD2 Power Status Register (MEMPDPWRSTAT1) Field Descriptions ......
Memory Power Domain RAM_PD3 Power Status Register (MEMPDPWRSTAT2) Field Descriptions ......
Global Control Register 1 (GLOBALCTRL1) Field Descriptions ...................................................
Global Status Register (GLOBALSTAT) Field Descriptions ........................................................
PSCON Diagnostic Compare Key Register (PRCKEYREG) Field Descriptions ................................
LogicPD PSCON Diagnostic Compare Status Register 1 (LPDDCSTAT1) Field Descriptions ...............
LogicPD PSCON Diagnostic Compare Status Register 2 (LPDDCSTAT2) Field Descriptions ...............
Memory PD PSCON Diagnostic Compare Status Register 1 (MPDDCSTAT1) Field Descriptions ...........
Memory PD PSCON Diagnostic Compare Status Register 2 (MPDDCSTAT2) Field Descriptions ...........
Isolation Diagnostic Status Register (ISODIAGSTAT) Field Descriptions ........................................
Input Multiplexing on 144QFP Parts ...................................................................................
Input Multiplexing on 337BGA Parts ...................................................................................
IOMM Registers ...........................................................................................................
Revision Register Field Descriptions ...................................................................................
Device Endianness Register Field Descriptions .....................................................................
Kicker Register 0 Field Descriptions ..................................................................................
Kicker Register 1 Field Descriptions ..................................................................................
Error Raw Status / Set Register Field Descriptions ..................................................................
Error Signaling Enabled Status / Clear Register Field Descriptions ..............................................
Error Enable Register Field Descriptions ..............................................................................
Interrupt Enable Clear Register Field Descriptions ..................................................................
Fault Address Register Field Descriptions ............................................................................
Fault Status Register Field Descriptions ..............................................................................
FAULT_CLEAR_REG: Fault Clear Register Field Descriptions ...................................................
Pin Multiplexing Control Registers Field Descriptions ..............................................................
Multiplexing and Control .................................................................................................
List of Tables
215
216
217
218
219
220
221
222
223
224
225
225
226
227
228
229
230
233
234
237
237
238
239
239
240
241
242
243
243
244
245
245
246
SPNU499C – March 2018
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www.ti.com
5-1.
ECC Encoding for BE32 Devices ....................................................................................... 254
5-2.
Syndrome Table, Decode to Bit in Error ............................................................................... 255
5-3.
Alternate Syndrome Table ............................................................................................... 256
5-4.
TI OTP Bank 0 Sector Information Field Descriptions ............................................................... 258
5-5.
TI OTP Sector Information Address .................................................................................... 258
5-6.
TI OTP Bank 0 Package and Memory Size Information Field Descriptions
5-7.
5-8.
5-9.
5-10.
5-11.
5-12.
5-13.
5-14.
5-15.
5-16.
5-17.
5-18.
5-19.
5-20.
5-21.
5-22.
5-23.
5-24.
5-25.
5-26.
5-27.
5-28.
5-29.
5-30.
5-31.
5-32.
5-33.
5-34.
5-35.
5-36.
5-37.
5-38.
5-39.
5-40.
5-41.
5-42.
5-43.
5-44.
5-45.
5-46.
5-47.
5-48.
5-49.
......................................
TI OTP Bank 0 LPO Trim and Max HCLK Information Field Descriptions ........................................
DIAG_MODE Encoding ..................................................................................................
Bus 1 Diagnostic Mode Summary ......................................................................................
Bus 2 and ECC Diagnostic Mode Summary ..........................................................................
Port Signals Diagnostic Mode Summary ..............................................................................
Flash Control Registers ..................................................................................................
Flash Option Control Register (FRDCNTL) Field Descriptions .....................................................
Flash Error Detection and Correction Control Register 1 (FEDACCTRL1) Field Descriptions .................
Flash Error Correction Control and Correction Register 2 (FEDACCTRL2) Field Descriptions ................
Flash Correctable Error Count Register (FCOR_ERR_CNT) Field Descriptions ................................
Flash Correctable Error Address Register (FCOR_ERR_ADD) Field Descriptions ..............................
Flash Correctable Error Position Register (FCOR_ERR_POS) Field Descriptions ..............................
Flash Error Detection and Correction Status Register (FEDACSTATUS) Field Descriptions ..................
Flash Uncorrectable Error Address Register (FUNC_ERR_ADD) Field Descriptions ...........................
Flash Error Detection and Correction Sector Disable Register (FEDACSDIS) Field Descriptions ............
Primary Address Tag Register (FPRIM_ADD_TAG) Field Descriptions ..........................................
Duplicate Address Tag Register (FDUP_ADD_TAG) Field Descriptions..........................................
Flash Bank Protection Register (FBPROT) Field Descriptions .....................................................
Flash Bank Sector Enable Register (FBSE) Field Descriptions ....................................................
Flash Bank Busy Register (FBBUSY) Field Descriptions ...........................................................
Flash Bank Access Control Register (FBAC) Field Descriptions ..................................................
Flash Bank Fallback Power Register (FBFALLBACK) Field Descriptions ........................................
Flash Pump Access Control Register 1 (FPAC1) Field Descriptions ..............................................
Flash Pump Access Control Register 1 (FPAC1) Field Descriptions ..............................................
Flash Pump Access Control Register 2 (FPAC2) Field Descriptions ..............................................
Flash Module Access Control Register (FMAC) Field Descriptions ................................................
Flash Module Status Register (FMSTAT) Field Descriptions ......................................................
EEPROM Emulation Data MSW Register (FEMU_DMSW) Field Descriptions ..................................
EEPROM Emulation Data LSW Register (FEMU_DLSW) Field Descriptions ....................................
EEPROM Emulation ECC Register (FEMU_ECC) Field Descriptions .............................................
EEPROM Emulation Address Register (FEMU_ADDR) Field Descriptions ......................................
Diagnostic Control Register (FDIAGCTRL) Field Descriptions .....................................................
Uncorrected Raw Data High Register (FRAW_DATAH) Field Descriptions ......................................
Uncorrected Raw Data Low Register (FRAW_DATAL) Field Descriptions .......................................
Uncorrected Raw ECC Register (FRAW_ECC) Field Descriptions ................................................
Parity Override Register (FPAR_OVR) Field Descriptions ..........................................................
Flash Error Detection and Correction Sector Disable Register (FEDACSDIS2) Field Descriptions ...........
FSM Register Write Enable (FSM_WR_ENA) Field Descriptions .................................................
FSM Sector Register (FSM_SECTOR) Field Descriptions .........................................................
EPROM Emulation Configuration Register (EEPROM_CONFIG) Field Descriptions ..........................
EEPROM Emulation Error Detection and Correction Control Register 1 (EE_CTRL1) Field Descriptions ...
EEPROM Emulation Error Correction Control Register 2 (EE_CTRL2) Field Descriptions ....................
EEPROM Emulation Correctable Error Count Register (EE_COR_ERR_CNT) Field Descriptions ...........
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List of Tables
Copyright © 2018, Texas Instruments Incorporated
259
259
261
265
266
267
268
269
270
272
272
273
274
275
278
279
280
280
281
281
282
283
284
285
286
287
287
288
290
290
291
292
293
295
295
296
297
298
299
299
300
301
303
303
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5-50.
EEPROM Emulation Correctable Error Address Register (EE_COR_ERR_ADD) Field Descriptions ........ 304
5-51.
EEPROM Emulation Correctable Error Position Register (EE_COR_ERR_POS) Field Descriptions......... 305
5-52.
EEPROM Emulation Error Status Register (EE_STATUS) Field Descriptions ................................... 306
5-53.
EEPROM Emulation Uncorrectable Error Address Register (EE_UNC_ERR_ADD) Field Descriptions...... 307
5-54.
Flash Bank Configuration Register (FCFG_BANK) Field Descriptions ............................................ 308
6-1.
TCRAM Module Control and Status Registers........................................................................ 314
6-2.
TCRAM Module Control Register (RAMCTRL) Field Descriptions ................................................. 315
6-3.
TCRAM Module Single-Bit Error Correction Threshold Register (RAMTHRESHOLD) Field Descriptions
6-4.
TCRAM Module Single-Bit Error Occurrences Counter Register (RAMOCCUR) Field Descriptions .......... 317
6-5.
TCRAM Module Interrupt Control Register (RAMINTCTRL) Field Descriptions.................................. 317
6-6.
TCRAM Module Error Status Register (RAMERRSTATUS) Field Descriptions .................................. 318
6-7.
TCRAM Module Single-Bit Error Address Register (RAMSERRADDR) Field Descriptions .................... 319
6-8.
TCRAM Module Uncorrectable Error Address Register (RAMUERRADDR) Field Descriptions ............... 320
6-9.
TCRAM Module Test Mode Control Register (RAMTEST) Field Descriptions ................................... 321
6-10.
TCRAM Module Test Mode Vector Register (RAMADDRDEVECT) Field Descriptions
6-11.
TCRAM Module Parity Error Address Register (RAMPERRADDR) Field Descriptions ......................... 322
6-12.
Auto-Memory Initialization Enable Register (INIT_DOMAIN) Field Descriptions ................................. 323
7-1.
PBIST Registers .......................................................................................................... 331
7-2.
RAM Configuration Register (RAMT) Field Descriptions ............................................................ 332
7-3.
Datalogger Register (DLR) Field Descriptions ........................................................................ 333
7-4.
PBIST Activate/ROM Clock Enable Register (PACT) Field Descriptions ......................................... 334
7-5.
PBIST ID Register Field Descriptions .................................................................................. 335
7-6.
Override Register (OVER) Field Descriptions......................................................................... 336
7-7.
Fail Status Fail Register 0 (FSRF0) Field Descriptions .............................................................. 337
7-8.
Fail Status Count 0 Register (FSRC0) Field Descriptions........................................................... 338
7-9.
Fail Status Count Register 1 (FSRC1) Field Descriptions........................................................... 338
7-10.
Fail Status Address 0 Register (FSRA0) Field Descriptions ........................................................ 339
7-11.
Fail Status Address 1 Register (FSRA1) Field Descriptions ........................................................ 339
7-12.
Fail Status Data Register 0 (FSRDL0) Field Descriptions........................................................... 340
7-13.
Fail Status Data Register 1 (FSRDL1) Field Descriptions........................................................... 340
7-14.
ROM Mask Register (ROM) Field Descriptions ....................................................................... 341
7-15.
Algorithm Mask Register (ALGO) Field Descriptions
7-16.
RAM Info Mask Lower Register (RINFOL) Field Descriptions ...................................................... 342
7-17.
RAM Info Mask Upper Register (RINFOU) Field Descriptions
8-1.
8-2.
8-3.
8-4.
8-5.
8-6.
8-7.
8-8.
8-9.
8-10.
8-11.
8-12.
8-13.
9-1.
9-2.
68
...
........................
................................................................
.....................................................
STC Test Coverage and Duration ......................................................................................
Typical STC Execution Times ...........................................................................................
STC Control Registers ...................................................................................................
STC Global Control Register 0 (STCGCR0) Field Descriptions ....................................................
STC Global Control Register 1 (STCGCR1) Field Descriptions ....................................................
Self-Test Run Timeout Counter Preload Register (STCTPR) ......................................................
STC Current ROM Address Register (STC_CADDR) Field Descriptions .........................................
STC Current Interval Count Register (STCCICR) Field Descriptions ..............................................
Self-Test Global Status Register (STCGSTAT) Field Descriptions ................................................
Self-Test Fail Status Register (STCFSTAT) Field Descriptions ....................................................
CPU1 Current MISR Register (CPU1_CURMISR[3:0]) Field Descriptions .......................................
CPU2 Current MISR Register (CPU2_CURMISR[3:0]) Field Descriptions .......................................
Signature Compare Self-Check Regsiter (STCSCSCR) Field Descriptions ......................................
Compare Match Test Sequence ........................................................................................
Compare Mismatch Test Sequence ...................................................................................
List of Tables
316
322
341
343
351
351
352
353
353
354
354
355
356
357
358
359
360
365
366
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9-3.
9-4.
9-5.
10-1.
10-2.
10-3.
10-4.
10-5.
10-6.
10-7.
10-8.
11-1.
11-2.
11-3.
11-4.
11-5.
11-6.
11-7.
11-8.
11-9.
11-10.
11-11.
11-12.
12-1.
12-2.
12-3.
12-4.
12-5.
12-6.
12-7.
12-8.
12-9.
12-10.
12-11.
12-12.
12-13.
12-14.
12-15.
12-16.
12-17.
12-18.
12-19.
12-20.
12-21.
12-22.
12-23.
12-24.
12-25.
13-1.
............................................................................................
CCM-R4F Status Register (CCMSR) Field Descriptions ...........................................................
CCM-R4F Key Register (CCMKEYR) Field Descriptions ...........................................................
Valid Frequency Ranges for PLL .......................................................................................
PLL Value Encoding ......................................................................................................
Summary of PLL Timings ................................................................................................
PLL Module Registers ....................................................................................................
LPOCLKDET Module Registers ........................................................................................
SSW PLL BIST Control Register 1 (SSWPLL1) Field Descriptions ................................................
SSW PLL BIST Control Register 2 (SSWPLL2) Field Descriptions ................................................
SSW PLL BIST Control Register 3 (SSWPLL3) Field Descriptions ................................................
DCC Control Registers ..................................................................................................
DCC Global Control Register (DCCGCTRL) Field Descriptions ...................................................
DCC Revision Id Register (DCCREV) Field Descriptions ..........................................................
DCC Counter0 Seed Register (DCCCNT0SEED) Field Descriptions .............................................
DCC Valid0 Seed Register (DCCVALID0SEED) Field Descriptions ..............................................
DCC Counter1 Seed Register (DCCCNT0SEED) Field Descriptions .............................................
DCC Status Register (DCCSTAT) Field Descriptions ...............................................................
DCC Counter0 Value Register (DCCCNT0) Field Descriptions ...................................................
DCC Valid0 Value Register (DCCVALID0) Field Descriptions .....................................................
DCC Counter1 Value Register (DCCCNT1) Field Descriptions ...................................................
DCC Counter1 Clock Source Selection Register (DCCCNT1CLKSRC) Field Descriptions ...................
DCC Counter0 Clock Source Selection Register (DCCCNT0CLKSRC) Field Descriptions ...................
ESM Interrupt and ERROR Pin Behavior .............................................................................
ESM Module Registers...................................................................................................
ESM Enable ERROR Pin Action/Response Register 1 (ESMEEPAPR1) Field Descriptions ..................
ESM Disable ERROR Pin Action/Response Register 1 (ESMDEPAPR1) Field Descriptions ..................
ESM Interrupt Enable Set Register 1 (ESMIESR1) Field Descriptions ............................................
ESM Interrupt Enable Clear Register 1 (ESMIECR1) Field Descriptions .........................................
ESM Interrupt Level Set Register 1 (ESMILSR1) Field Descriptions ..............................................
ESM Interrupt Level Clear Register 1 (ESMILCR1) Field Descriptions ...........................................
ESM Status Register 1 (ESMSR1) Field Descriptions ..............................................................
ESM Status Register 2 (ESMSR2) Field Descriptions ..............................................................
ESM Status Register 3 (ESMSR3) Field Descriptions ..............................................................
ESM ERROR Pin Status Register (ESMEPSR) Field Descriptions ................................................
ESM Interrupt Offset High Register (ESMIOFFHR) Field Descriptions............................................
ESM Interrupt Offset Low Register (ESMIOFFLR) Field Descriptions .............................................
ESM Low-Time Counter Register (ESMLTCR) Field Descriptions .................................................
ESM Low-Time Counter Preload Register (ESMLTCPR) Field Descriptions .....................................
ESM Error Key Register (ESMEKR) Field Descriptions .............................................................
ESM Status Shadow Register 2 (ESMSSR2) Field Descriptions ..................................................
ESM Influence ERROR Pin Set Register 4 (ESMIEPSR4) Field Descriptions ...................................
ESM Influence ERROR Pin Clear Register 4 (ESMIEPCR4) Field Descriptions ................................
ESM Interrupt Enable Set Register 4 (ESMIESR4) Field Descriptions ............................................
ESM Interrupt Enable Clear Register 4 (ESMIECR4) Field Descriptions .........................................
ESM Interrupt Level Set Register 4 (ESMILSR4) Field Descriptions ..............................................
ESM Interrupt Level Clear Register 4 (ESMILCR4) Field Descriptions ...........................................
ESM Status Register 4 (ESMSR4) Field Descriptions ...............................................................
RTI Registers ..............................................................................................................
CCM-R4F Control Registers
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List of Tables
Copyright © 2018, Texas Instruments Incorporated
367
368
369
378
379
383
388
388
389
390
391
403
404
405
405
406
406
407
408
409
409
410
411
414
420
421
421
422
422
423
423
424
424
425
425
426
427
428
428
429
429
430
430
431
431
432
432
433
446
69
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13-2.
RTI Global Control Register (RTIGCTRL) Field Descriptions....................................................... 447
13-3.
RTI Timebase Control Register (RTITBCTRL) Field Descriptions ................................................. 448
13-4.
RTI Capture Control Register (RTICAPCTRL) Field Descriptions ................................................. 449
13-5.
RTI Compare Control Register (RTICOMPCTRL) Field Descriptions ............................................. 450
13-6.
RTI Free Running Counter 0 Register (RTIFRC0) Field Descriptions ............................................. 451
13-7.
RTI Up Counter 0 Register (RTIUC0) Field Descriptions
13-8.
13-9.
13-10.
13-11.
13-12.
13-13.
13-14.
13-15.
13-16.
13-17.
13-18.
13-19.
13-20.
13-21.
13-22.
13-23.
13-24.
13-25.
13-26.
13-27.
13-28.
13-29.
13-30.
13-31.
13-32.
13-33.
13-34.
13-35.
13-36.
13-37.
13-38.
13-39.
13-40.
13-41.
14-1.
14-2.
14-3.
14-4.
14-5.
14-6.
14-7.
14-8.
14-9.
70
...........................................................
RTI Compare Up Counter 0 Register (RTICPUC0) Field Descriptions ............................................
RTI Capture Free Running Counter 0 Register (RTICAFRC0) Field Descriptions ...............................
RTI Capture Up Counter 0 Register (RTICAUC0) Field Descriptions .............................................
RTI Free Running Counter 1 Register (RTIFRC1) Field Descriptions .............................................
RTI Up Counter 1 Register (RTIUC1) Field Descriptions ...........................................................
RTI Compare Up Counter 1 Register (RTICPUC1) Field Descriptions ............................................
RTI Capture Free Running Counter 1 Register (RTICAFRC1) Field Descriptions ...............................
RTI Capture Up Counter 1 Register (RTICAUC1) Field Descriptions .............................................
RTI Compare 0 Register (RTICOMP0) Field Descriptions ..........................................................
RTI Update Compare 0 Register (RTIUDCP0) Field Descriptions .................................................
RTI Compare 1 Register (RTICOMP1) Field Descriptions ..........................................................
RTI Update Compare 1 Register (RTIUDCP1) Field Descriptions .................................................
RTI Compare 2 Register (RTICOMP2) Field Descriptions ..........................................................
RTI Update Compare 2 Register (RTIUDCP2) Field Descriptions .................................................
RTI Compare 3 Register (RTICOMP3) Field Descriptions ..........................................................
RTI Update Compare 3 Register (RTIUDCP3) Field Descriptions .................................................
RTI Timebase Low Compare Register (RTITBLCOMP) Field Descriptions ......................................
RTI Timebase High Compare Register (RTITBHCOMP) Field Descriptions .....................................
RTI Set Interrupt Control Register (RTISETINTENA) Field Descriptions .........................................
RTI Clear Interrupt Control Register (RTICLEARINTENA) Field Descriptions ...................................
RTI Interrupt Flag Register (RTIINTFLAG) Field Descriptions......................................................
Digital Watchdog Control Register (RTIDWDCTRL) Field Descriptions ...........................................
Digital Watchdog Preload Register (RTIDWDPRLD) Field Descriptions ..........................................
Watchdog Status Register (RTIWDSTATUS) Field Descriptions ..................................................
RTI Watchdog Key Register (RTIDWDKEY) Field Descriptions....................................................
Example of a WDKEY Sequence .......................................................................................
RTI Watchdog Down Counter Register (RTIDWDCNTR) Field Descriptions .....................................
Digital Windowed Watchdog Reaction Control (RTIWWDRXNCTRL) Field Descriptions ......................
Digital Windowed Watchdog Window Size Control (RTIWWDSIZECTRL) Field Descriptions .................
RTI Compare Interrupt Clear Enable Register (RTIINTCLRENABLE) Field Descriptions ......................
RTI Compare 0 Clear Register (RTICMP0CLR) Field Descriptions ...............................................
RTI Compare 1 Clear Register (RTICMP1CLR) Field Descriptions ...............................................
RTI Compare 2 Clear Register (RTICMP2CLR) Field Descriptions ...............................................
RTI Compare 3 Clear Register (RTICMP3CLR) Field Descriptions ...............................................
CRC Modes in Which DMA Request and Counter Logic are Active or Inactive .................................
Modes in Which Interrupt Condition Can Occur .....................................................................
Interrupt Offset Mapping ................................................................................................
CRC Control Registers ...................................................................................................
CRC Global Control Register 0 (CRC_CTRL0) Field Descriptions ................................................
CRC Global Control Register 1 (CRC_CTRL1) Field Descriptions ................................................
CRC Global Control Register 2 (CRC_CTRL2) Field Descriptions ................................................
CRC Interrupt Enable Set Register (CRC_INTS) Field Descriptions ..............................................
CRC Interrupt Enable Reset Register (CRC_INTR) Field Descriptions ...........................................
List of Tables
451
452
452
453
453
454
455
456
456
457
457
458
458
459
459
460
460
461
461
462
464
466
467
468
469
470
470
471
471
472
473
474
474
475
475
484
485
488
493
494
494
495
496
498
SPNU499C – March 2018
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...............................................
CRC Interrupt Offset (CRC_INT_OFFSET_REG) Field Descriptions .............................................
CRC Busy Register (CRC_BUSY) Field Descriptions ...............................................................
CRC Pattern Counter Preload Register 1 (CRC_PCOUNT_REG1) Field Descriptions .........................
CRC Sector Counter Preload Register 1 (CRC_SCOUNT_REG1) Field Descriptions ..........................
CRC Current Sector Register 1 (CRC_CURSEC_REG1) Field Descriptions ....................................
CRC Channel 1 Watchdog Timeout Preload Register A (CRC_WDTOPLD1) Field Descriptions .............
CRC Channel 1 Block Complete Timeout Preload Register B (CRC_BCTOPLD1) Field Descriptions .......
Channel 1 PSA Signature Low Register (PSA_SIGREGL1) Field Descriptions .................................
Channel 1 PSA Signature High Register (PSA_SIGREGH1) Field Descriptions ................................
Channel 1 CRC Value Low Register (CRC_REGL1) Field Descriptions ..........................................
Channel 1 CRC Value High Register (CRC_REGH1) Field Descriptions .........................................
Channel 1 PSA Sector Signature Low Register (PSA_SECSIGREGL1) Field Descriptions ...................
Channel 1 PSA Sector Signature High Register (PSA_SECSIGREGH1) Field Descriptions ..................
Channel 1 Raw Data Low Register (RAW_DATAREGL1) Field Descriptions ....................................
Channel 1 Raw Data High Register (RAW_DATAREGH1) Field Descriptions ...................................
CRC Pattern Counter Preload Register 2 (CRC_PCOUNT_REG2) Field Descriptions .........................
CRC Sector Counter Preload Register 2 (CRC_SCOUNT_REG2) Field Descriptions ..........................
CRC Current Sector Register 2 (CRC_CURSEC_REG2) Field Descriptions ....................................
CRC Channel 2 Watchdog Timeout Preload Register A (CRC_WDTOPLD2) Field Descriptions .............
CRC Channel 2 Block Complete Timeout Preload Register B (CRC_BCTOPLD2) Field Descriptions .......
Channel 2 PSA Signature Low Register (PSA_SIGREGL2) Field Descriptions .................................
Channel 2 PSA Signature High Register (PSA_SIGREGH2) Field Descriptions ................................
Channel 2 CRC Value Low Register (CRC_REGL2) Field Descriptions ..........................................
Channel 2 CRC Value High Register (CRC_REGH2) Field Descriptions .........................................
Channel 2 PSA Sector Signature Low Register (PSA_SECSIGREGL2) Field Descriptions ...................
Channel 2 PSA Sector Signature High Register (PSA_SECSIGREGH2) Field Descriptions ..................
Channel 2 Raw Data Low Register (RAW_DATAREGL2) Field Descriptions ....................................
Channel 2 Raw Data High Register (RAW_DATAREGH2) Field Descriptions ...................................
Data Bus Selection Register Field Descriptions ......................................................................
VIM Control Registers ....................................................................................................
Interrupt Vector Table Parity Flag Register (PARFLG) Field Descriptions ........................................
Interrupt Vector Table Parity Control Register (PARCTL) Field Descriptions ....................................
Address Parity Error Register (ADDERR) Field Descriptions .......................................................
Fall Back Address Parity Error Register (FBPARERR) Field Descriptions .......................................
Interrupt Dispatch .........................................................................................................
IRQ Index Offset Vector Register (IRQINDEX) Field Descriptions .................................................
FIQ Index Offset Vector Register (FIQINDEX) Field Descriptions .................................................
FIQ/IRQ Program Control Registers (FIRQPRx) Field Descriptions ...............................................
Pending Interrupt Read Location Registers (INTREQx) Field Descriptions ......................................
Interrupt Enable Set Registers (REQENASETx) Field Descriptions ..............................................
Interrupt Enable Clear Registers (REQENACLRx) Field Descriptions.............................................
Wake-Up Enable Set Registers (WAKEENASETx) Field Descriptions ............................................
Wake-Up Enable Clear Registers (WAKEENACLRx) Field Descriptions .........................................
IRQ Interrupt Vector Register (IRQVECREG) Field Descriptions ..................................................
FIQ Interrupt Vector Register (FIQVECREG) Field Descriptions ...................................................
Capture Event Register (CAPEVT) Field Descriptions ..............................................................
Interrupt Control Registers Organization ..............................................................................
Interrupt Control Registers (CHANCTRLx) Field Descriptions......................................................
14-10. CRC Interrupt Status Register (CRC_STATUS) Field Descriptions
500
14-11.
502
14-12.
14-13.
14-14.
14-15.
14-16.
14-17.
14-18.
14-19.
14-20.
14-21.
14-22.
14-23.
14-24.
14-25.
14-26.
14-27.
14-28.
14-29.
14-30.
14-31.
14-32.
14-33.
14-34.
14-35.
14-36.
14-37.
14-38.
14-39.
15-1.
15-2.
15-3.
15-4.
15-5.
15-6.
15-7.
15-8.
15-9.
15-10.
15-11.
15-12.
15-13.
15-14.
15-15.
15-16.
15-17.
15-18.
15-19.
SPNU499C – March 2018
Submit Documentation Feedback
List of Tables
Copyright © 2018, Texas Instruments Incorporated
503
503
504
504
505
505
506
506
506
507
507
507
508
508
508
509
509
510
510
511
511
511
512
512
512
513
513
514
530
531
531
532
532
533
534
534
535
536
537
538
539
540
541
541
542
543
543
71
www.ti.com
16-1.
Arbitration According to Priority Queues and Priority Schemes .................................................... 553
16-2.
DMA Request Line Connection ......................................................................................... 557
16-3.
Maximum Number of DMA Transactions per Channel in Non-Bypass Mode..................................... 562
16-4.
Maximum Number of DMA Transactions per Channel in Bypass Mode
16-5.
16-6.
16-7.
16-8.
16-9.
16-10.
16-11.
16-12.
16-13.
16-14.
16-15.
16-16.
16-17.
16-18.
16-19.
16-20.
16-21.
16-22.
16-23.
16-24.
16-25.
16-26.
16-27.
16-28.
16-29.
16-30.
16-31.
16-32.
16-33.
16-34.
16-35.
16-36.
16-37.
16-38.
16-39.
16-40.
16-41.
16-42.
16-43.
16-44.
16-45.
16-46.
16-47.
16-48.
16-49.
72
..........................................
Control Packet RAM ......................................................................................................
Control Packet RAM ......................................................................................................
Parity RAM.................................................................................................................
DMA Control Registers...................................................................................................
Control Packet Memory Map ............................................................................................
Global Control Register (GCTRL) Field Descriptions ................................................................
Channel Pending Register (PEND) Field Descriptions ..............................................................
DMA Status Register (DMASTAT) Field Descriptions ...............................................................
HW Channel Enable Set and Status Register (HWCHENAS) Field Descriptions................................
HW Channel Enable Reset and Status Register (HWCHENAR) Field Descriptions ............................
SW Channel Enable Set and Status Register (SWCHENAS) Field Descriptions ................................
SW Channel Enable Reset and Status Register (SWCHENAR) Field Descriptions .............................
Channel Priority Set Register (CHPRIOS) Field Descriptions ......................................................
Channel Priority Reset Register (CHPRIOR) Field Descriptions ...................................................
Global Channel Interrupt Enable Set Register (GCHIENAS) Field Descriptions .................................
Global Channel Interrupt Enable Reset Register (GCHIENAR) Field Descriptions ..............................
DMA Request Assignment Register 0 (DREQASI0) Field Descriptions ...........................................
DMA Request Assignment Register 1 (DREQASI1) Field Descriptions ...........................................
DMA Request Assignment Register 2 (DREQASI2) Field Descriptions ...........................................
DMA Request Assignment Register 3 (DREQASI3) Field Descriptions ...........................................
Port Assignment Register 0 (PAR0) Field Descriptions .............................................................
Port Assignment Register 1 (PAR1) Field Descriptions .............................................................
FTC Interrupt Mapping Register (FTCMAP) Field Descriptions ....................................................
LFS Interrupt Mapping Register (LFSMAP) Field Descriptions .....................................................
HBC Interrupt Mapping Register (HBCMAP) Field Descriptions ...................................................
BTC Interrupt Mapping Register (BTCMAP) Field Descriptions ....................................................
FTC Interrupt Enable Set (FTCINTENAS) Field Descriptions ......................................................
FTC Interrupt Enable Reset (FTCINTENAR) Field Descriptions ...................................................
LFS Interrupt Enable Set (LFSINTENAS) Field Descriptions .......................................................
LFS Interrupt Enable Reset (LFSINTENAR) Field Descriptions ....................................................
HBC Interrupt Enable Set (HBCINTENAS) Field Descriptions .....................................................
HBC Interrupt Enable Reset (HBCINTENAR) Field Descriptions ..................................................
BTC Interrupt Enable Reset (BTCINTENAS) Field Descriptions ...................................................
BTC Interrupt Enable Reset (BTCINTENAR) Field Descriptions ...................................................
Global Interrupt Flag Register (GINTFLAG) Field Descriptions ....................................................
FTC Interrupt Flag Register (FTCFLAG) Field Descriptions ........................................................
LFS Interrupt Flag Register (LFSFLAG) Field Descriptions .........................................................
HBC Interrupt Flag (HBCFLAG) Field Descriptions ..................................................................
BTC Interrupt Flag Register (BTCFLAG) Field Descriptions ........................................................
FTCA Interrupt Channel Offset Register (FTCAOFFSET) Field Descriptions ....................................
LFSA Interrupt Channel Offset Register (LFSAOFFSET) Field Descriptions .....................................
HBCA Interrupt Channel Offset Register (HBCAOFFSET) Field Descriptions ...................................
BTCA Interrupt Channel Offset Register (BTCAOFFSET) Field Descriptions ....................................
FTCB Interrupt Channel Offset Register (FTCBOFFSET) Field Descriptions ....................................
LFSB Interrupt Channel Offset Register (LFSBOFFSET) Field Descriptions .....................................
List of Tables
562
565
565
565
566
567
568
569
569
570
570
571
572
572
573
573
574
575
576
577
578
579
580
581
581
582
582
583
583
584
584
585
585
586
586
587
587
588
588
589
590
590
592
592
594
594
SPNU499C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
www.ti.com
16-50. HBCB Interrupt Channel Offset Register (HBCBOFFSET) Field Descriptions ................................... 596
16-51. BTCB Interrupt Channel Offset Register (BTCBOFFSET) Field Descriptions .................................... 596
16-52. Port Control Register (PTCRL) Field Descriptions ................................................................... 598
16-53. RAM Test Control (RTCTRL) Field Descriptions ..................................................................... 599
16-54. Debug Control (DCTRL) Field Descriptions ........................................................................... 600
16-55. Watch Point Register (WPR) Field Descriptions ...................................................................... 601
16-56. Watch Mask Register (WMR) Field Descriptions ..................................................................... 601
16-57. Port B Active Channel Source Address Register (PBACDADDR) Field Descriptions ........................... 602
16-58. Port B Active Channel Destination Address Register (PBACDADDR) Field Descriptions ...................... 602
16-59. Port B Active Channel Transfer Count Register (PBACTC) Field Descriptions .................................. 603
..............................................................
DMA Parity Error Address Register (DMAPAR) Field Descriptions ................................................
DMA Memory Protection Control Register (DMAMPCTRL) Field Descriptions ..................................
DMA Memory Protection Status Register (DMAMPST) Field Descriptions .......................................
DMA Memory Protection Region 0 Start Address Register (DMAMPR0S) Field Descriptions .................
DMA Memory Protection Region 0 End Address Register (DMAMPR0E) Field Descriptions ..................
DMA Memory Protection Region 1 Start Address Register (DMAMPR1S) Field Descriptions .................
DMA Memory Protection Region 1 End Address Register (DMAMPR1E) Field Descriptions ..................
DMA Memory Protection Region 2 Start Address Register (DMAMPR2S) Field Descriptions .................
DMA Memory Protection Region 2 End Address Register (DMAMPR2E) Field Descriptions ..................
DMA Memory Protection Region 3 Start Address Register (DMAMPR3S) Field Descriptions .................
DMA Memory Protection Region 3 End Address Register (DMAMPR3E) Field Descriptions ..................
Initial Source Address (ISADDR) Field Descriptions .................................................................
Initial Destination Address Register (IDADDR) Field Descriptions .................................................
Initial Transfer Count Register (ITCOUNT) Field Descriptions .....................................................
Channel Control Register (CHCTRL) Field Descriptions ............................................................
Element Index Offset Register (EIOFF) Field Descriptions ........................................................
Frame Index Offset Register (FIOFF) Field Descriptions ...........................................................
Current Source Address Register (CSADDR) Field Descriptions .................................................
Current Destination Address Register (CDADDR) Field Descriptions .............................................
Current Transfer Count Register (CTCOUNT) Field Descriptions .................................................
EMIF Pins Used to Access Both SDRAM and Asynchronous Memories .........................................
EMIF Pins Specific to SDRAM ..........................................................................................
EMIF Pins Specific to Asynchronous Memory ........................................................................
EMIF SDRAM Commands ...............................................................................................
Truth Table for SDRAM Commands ...................................................................................
16-bit EMIF Address Pin Connections .................................................................................
Description of the SDRAM Configuration Register (SDCR) .........................................................
Description of the SDRAM Refresh Control Register (SDRCR) ....................................................
Description of the SDRAM Timing Register (SDTIMR) ..............................................................
Description of the SDRAM Self Refresh Exit Timing Register (SDSRETR) ......................................
SDRAM LOAD MODE REGISTER Command ........................................................................
Refresh Urgency Levels .................................................................................................
Mapping from Logical Address to EMIF Pins for 16-bit SDRAM ...................................................
Normal Mode vs. Select Strobe Mode .................................................................................
Description of the Asynchronous m Configuration Register (CEnCFG) ...........................................
Description of the Asynchronous Wait Cycle Configuration Register (AWCC) ..................................
Description of the EMIF Interrupt Mask Set Register (INTMSKSET) ..............................................
Description of the EMIF Interrupt Mast Clear Register (INTMSKCLR) ............................................
16-60. Parity Control Register (DMAPCR) Field Descriptions
16-61.
16-62.
16-63.
16-64.
16-65.
16-66.
16-67.
16-68.
16-69.
16-70.
16-71.
16-72.
16-73.
16-74.
16-75.
16-76.
16-77.
16-78.
16-79.
16-80.
17-1.
17-2.
17-3.
17-4.
17-5.
17-6.
17-7.
17-8.
17-9.
17-10.
17-11.
17-12.
17-13.
17-14.
17-15.
17-16.
17-17.
17-18.
SPNU499C – March 2018
Submit Documentation Feedback
List of Tables
Copyright © 2018, Texas Instruments Incorporated
604
605
606
608
609
609
610
610
611
611
612
612
613
613
614
615
616
616
617
617
618
622
623
623
624
624
626
627
627
628
628
629
630
635
636
638
639
639
639
73
www.ti.com
17-19. Asynchronous Read Operation in Normal Mode ..................................................................... 640
17-20. Asynchronous Write Operation in Normal Mode
.....................................................................
642
17-21. Asynchronous Read Operation in Select Strobe Mode .............................................................. 644
17-22. Asynchronous Write Operation in Select Strobe Mode .............................................................. 646
17-23. Interrupt Monitor and Control Bit Fields ................................................................................ 650
17-24. External Memory Interface (EMIF) Registers ......................................................................... 654
17-25. Module ID Register (MIDR) Field Descriptions ....................................................................... 654
17-26. Asynchronous Wait Cycle Configuration Register (AWCCR) Field Descriptions ................................. 655
17-27. SDRAM Configuration Register (SDCR) Field Descriptions ........................................................ 656
17-28. SDRAM Refresh Control Register (SDRCR) Field Descriptions
...................................................
657
17-29. Asynchronous n Configuration Register (CEnCFG) Field Descriptions ........................................... 658
17-30. SDRAM Timing Register (SDTIMR) Field Descriptions.............................................................. 659
17-31. SDRAM Self Refresh Exit Timing Register (SDSRETR) Field Descriptions ...................................... 660
........................................................
EMIF Interrupt Mask Register (INTMSK) Field Descriptions ........................................................
EMIF Interrupt Mask Set Register (INTMSKSET) Field Descriptions ..............................................
EMIF Interrupt Mask Clear Register (INTMSKCLR) Field Descriptions ...........................................
Page Mode Control Register (PMCR) Field Descriptions ...........................................................
SR Field Value For the EMIF to K4S641632H-TC(L)70 Interface .................................................
SDTIMR Field Calculations for the EMIF to K4S641632H-TC(L)70 Interface ....................................
RR Calculation for the EMIF to K4S641632H-TC(L)70 Interface ..................................................
RR Calculation for the EMIF to K4S641632H-TC(L)70 Interface ..................................................
SDCR Field Values For the EMIF to K4S641632H-TC(L)70 Interface ............................................
AC Characteristics for a Read Access .................................................................................
AC Characteristics for a Write Access .................................................................................
POM Registers ............................................................................................................
POM Global Control Register (POMGLBCTRL) Field Descriptions ................................................
POM Revision ID (POMREV) Field Descriptions .....................................................................
POM Clock Gate Control Register (POMCLKCTRL) Field Descriptions ..........................................
POM Status Register (POMFLG) Field Descriptions.................................................................
POM Program Region Start Address Register x (POMPROGSTARTx) Field Descriptions ....................
POM Overlay Region Start Address Register x (POMOVLSTARTx) Field Descriptions ........................
POM Region Size Register x (POMREGSIZEx) Field Descriptions ...............................................
POM Integration Control Register (POMITCTRL) Field Descriptions ..............................................
POM Claim Set Register (POMCLAIMSET) Field Descriptions ....................................................
POM Claim Clear Register (POMCLAIMCLR) Field Descriptions ..................................................
POM Lock Access Register (POMLOCKACCESS) Field Descriptions ............................................
POM Lock Status Register (POMLOCKSTATUS) Field Descriptions .............................................
POM Authentication Status Register (POMAUTHSTATUS) Field Descriptions ..................................
POM Device ID Register (POMDEVID) Field Descriptions .........................................................
POM Device Type Register (POMDEVTYPE) Field Descriptions ..................................................
POM Peripheral ID 4 Register (POMPERIPHERALID4) Field Descriptions ......................................
POM Peripheral ID 5 Register (POMPERIPHERALID5) Field Descriptions ......................................
POM Peripheral ID 6 Register (POMPERIPHERALID6) Field Descriptions ......................................
POM Peripheral ID 7 Register (POMPERIPHERALID7) Field Descriptions ......................................
POM Peripheral ID 0 Register (POMPERIPHERALID0) Field Descriptions ......................................
POM Peripheral ID 1 Register (POMPERIPHERALID1) Field Descriptions ......................................
POM Peripheral ID 2 Register (POMPERIPHERALID2) Field Descriptions ......................................
POM Peripheral ID 3 Register (POMPERIPHERALID3) Field Descriptions ......................................
17-32. EMIF Interrupt Raw Register (INTRAW) Field Descriptions
17-33.
17-34.
17-35.
17-36.
17-37.
17-38.
17-39.
17-40.
17-41.
17-42.
17-43.
18-1.
18-2.
18-3.
18-4.
18-5.
18-6.
18-7.
18-8.
18-9.
18-10.
18-11.
18-12.
18-13.
18-14.
18-15.
18-16.
18-17.
18-18.
18-19.
18-20.
18-21.
18-22.
18-23.
18-24.
74
List of Tables
661
662
663
664
665
666
668
669
670
671
672
672
679
680
681
681
682
683
683
684
684
685
686
687
687
687
688
688
689
689
690
690
691
691
692
692
SPNU499C – March 2018
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18-25. POM Component ID 0 Register (POMCOMPONENTID0) Field Descriptions .................................... 693
18-26. POM Component ID 1 Register (POMCOMPONENTID1) Field Descriptions .................................... 693
18-27. POM Component ID 2 Register (POMCOMPONENTID2) Field Descriptions .................................... 694
18-28. POM Component ID 3 Register (POMCOMPONENTID3) Field Descriptions .................................... 694
19-1.
Calibration Reference Voltages ......................................................................................... 714
19-2.
Self-Test Reference Voltages ........................................................................................... 717
19-3.
Determination of ADC Input Channel Condition ...................................................................... 718
19-4.
Output Buffer and Pull Control Behavior for ADxEVT as GPIO Pins .............................................. 723
19-5.
ADC Registers
19-6.
19-7.
19-8.
19-9.
19-10.
19-11.
19-12.
19-13.
19-14.
19-15.
19-16.
19-17.
19-18.
19-19.
19-20.
19-21.
19-22.
19-23.
19-24.
19-25.
19-26.
19-27.
19-28.
19-29.
19-30.
19-31.
19-32.
19-33.
19-34.
19-35.
19-36.
19-37.
19-38.
19-39.
19-40.
19-41.
19-42.
19-43.
19-44.
19-45.
............................................................................................................
ADC Reset Control Register (ADRSTCR) Field Descriptions ......................................................
ADC Operating Mode Control Register (ADOPMODECR) Field Descriptions ...................................
ADC Clock Control Register (ADCLOCKCR) Field Descriptions ...................................................
ADC Calibration Mode Control Register (ADCALCR) Field Descriptions .........................................
ADC Event Group Operating Mode Control Register (ADEVMODECR) Field Descriptions ....................
ADC Group1 Operating Mode Control Register (ADG1MODECR) Field Descriptions ..........................
ADC Group 2 Operating Mode Control Register (ADG2MODECR) Field Descriptions .........................
ADC Event Group Trigger Source Select Register (ADEVSRC) Field Descriptions .............................
ADC Group1 Trigger Source Select Register (ADG1SRC) Field Descriptions ...................................
ADC Group2 Trigger Source Select Register (ADG2SRC) Field Descriptions ...................................
ADC Event Group Interrupt Enable Control Register (ADEVINTENA) Field Descriptions ......................
ADC Group1 Interrupt Enable Control Register (ADG1INTENA) Field Descriptions ............................
ADC Group2 Interrupt Enable Control Register (ADG2INTENA) Field Descriptions ............................
ADC Event Group Interrupt Flag Register (ADEVINTFLG) Field Descriptions ...................................
ADC Group1 Interrupt Flag Register (ADG1INTFLG) Field Descriptions .........................................
ADC Group2 Interrupt Flag Register (ADG2INTFLG) Field Descriptions .........................................
ADC Event Group Threshold Interrupt Control Register (ADEVTHRINTCR) Field Descriptions ..............
ADC Group1 Threshold Interrupt Control Register (ADG1THRINTCR) Field Descriptions .....................
ADC Group2 Threshold Interrupt Control Register (ADG2THRINTCR) Field Descriptions .....................
ADC Event Group DMA Control Register (ADEVDMACR) Field Descriptions ...................................
ADC Group1 DMA Control Register (ADG1DMACR) Field Descriptions .........................................
ADC Group2 DMA Control Register (ADG2DMACR) Field Descriptions .........................................
ADC Results Memory Configuration Register (ADBNDCR) Field Descriptions ..................................
ADC Results Memory Size Configuration Register (ADBNDEND) Field Descriptions ..........................
ADC Event Group Sampling Time Configuration Register (ADEVSAMP) Field Descriptions ..................
ADC Group1 Sampling Time Configuration Register (ADG1SAMP) Field Descriptions ........................
ADC Group2 Sampling Time Configuration Register (ADG2SAMP) Field Descriptions ........................
ADC Event Group Status Register (ADEVSR) Field Descriptions .................................................
ADC Group1 Status Register (ADG1SR) Field Descriptions .......................................................
ADC Group2 Status Register (ADG2SR) Field Descriptions .......................................................
ADC Event Group Channel Select Register (ADEVSEL) Field Descriptions .....................................
ADC Group1 Channel Select Register (ADG1SEL) Field Descriptions ...........................................
ADC Group2 Channel Select Register (ADG2SEL) Field Descriptions ...........................................
ADC Calibration and Error Offset Correction Register (ADCALR) Field Descriptions ...........................
ADC State Machine Status Register (ADSMSTATE) Field Descriptions ..........................................
ADC Channel Last Conversion Value Register (ADLASTCONV) Field Descriptions ............................
ADC Event Group Results' FIFO Register (ADEVBUFFER) Field Descriptions .................................
ADC Group1 Results FIFO Register (ADG1BUFFER) Field Descriptions ........................................
ADC Group2 Results FIFO Register (ADG2BUFFER) Field Descriptions ........................................
ADC Event Group Results Emulation FIFO Register (ADEVEMUBUFFER) Field Descriptions ...............
SPNU499C – March 2018
Submit Documentation Feedback
List of Tables
Copyright © 2018, Texas Instruments Incorporated
724
726
726
728
728
731
734
737
739
740
741
742
743
744
745
746
747
748
748
749
750
752
754
756
757
758
758
759
760
761
762
763
764
765
766
766
767
768
769
770
771
75
www.ti.com
19-46. ADC Group1 Results Emulation FIFO Register (ADG1EMUBUFFER) Field Descriptions ..................... 772
19-47. ADC Group2 Results Emulation FIFO Register (ADG2EMUBUFFER) Field Descriptions ..................... 773
19-48. ADC ADEVT Pin Direction Control Register (ADEVTDIR) Field Descriptions .................................... 774
775
19-50.
775
19-51.
19-52.
19-53.
19-54.
19-55.
19-56.
19-57.
19-58.
19-59.
19-60.
19-61.
19-62.
19-63.
19-64.
19-65.
19-66.
19-67.
19-68.
19-69.
19-70.
19-71.
19-72.
19-73.
20-1.
20-2.
20-3.
20-4.
20-5.
20-6.
20-7.
20-8.
20-9.
20-10.
20-11.
20-12.
20-13.
20-14.
20-15.
20-16.
20-17.
20-18.
20-19.
20-20.
20-21.
76
.............................
ADC ADEVT Pin Input Value Register (ADEVTIN) Field Descriptions ............................................
ADC ADEVT Pin Set Register (ADEVTSET) Field Descriptions ...................................................
ADC ADEVT Pin Clear Register (ADEVTCLR) Field Descriptions .................................................
ADC ADEVT Pin Open Drain Enable Register (ADEVTPDR) Field Descriptions ................................
ADC ADEVT Pin Pull Control Disable Register (ADEVTPDIS) Field Descriptions ..............................
ADC ADEVT Pin Pull Control Select Register (ADEVTPSEL) Field Descriptions ...............................
ADC Event Group Sample Cap Discharge Control Register (ADEVSAMPDISEN) Field Descriptions .......
ADC Group1 Sample Cap Discharge Control Register (ADG1SAMPDISEN) Field Descriptions ..............
ADC Group2 Sample Cap Discharge Control Register (ADG2SAMPDISEN) Field Descriptions ..............
ADC Magnitude Compare Interrupt x Control Registers (ADMAGINTxCR) Field Descriptions ................
ADC Magnitude Compare Interrupt x Mask Register (ADMAGxMASK) Field Descriptions ....................
ADC Magnitude Compare Interrupt Enable Set Register (ADMAGINTENASET) Field Descriptions..........
ADC Magnitude Compare Interrupt Enable Clear Register (ADMAGINTENACLR) Field Descriptions .......
ADC Magnitude Compare Interrupt Flag Register (ADMAGINTFLG) Field Descriptions .......................
ADC Magnitude Compare Interrupt Offset Register (ADMAGINTOFF) Field Descriptions .....................
ADC Event Group FIFO Reset Control Register (ADEVFIFORESETCR) Field Descriptions ..................
ADC Group1 FIFO Reset Control Register (ADG1FIFORESETCR) Field Descriptions ........................
ADC Group2 FIFO Reset Control Register (ADG2FIFORESETCR) Field Descriptions ........................
ADC Event Group RAM Write Address Register (ADEVRAMWRADDR) Field Descriptions ...................
ADC Group1 RAM Write Address Register (ADG1RAMWRADDR) Field Descriptions .........................
ADC Group2 RAM Write Address Register (ADG2RAMWRADDR) Field Descriptions .........................
ADC Parity Control Register (ADPARCR) Field Descriptions ......................................................
ADC Parity Error Address Register (ADPARADDR) Field Descriptions ...........................................
ADC Power-Up Delay Control Register (ADPWRUPDLYCTRL) Field Descriptions .............................
N2HET RAM Base Addresses ..........................................................................................
N2HET RAM Bank Structure ............................................................................................
Pin Safe State Upon Parity Error Detection ...........................................................................
N2HET Parity Bit Mapping ...............................................................................................
Prescale Factor Register Encoding ....................................................................................
Interpretation of the 7-Bit HR Data Field...............................................................................
Edge Detection Input Timing for Loop Resolution Instructions .....................................................
Edge Detection Input Timing for High Resolution Instructions......................................................
Input Buffer, Output Buffer, and Pull Control Behavior ..............................................................
N2HET Pin Disable Feature .............................................................................................
Pulse Length Examples for Suppression Filter .......................................................................
Interrupt Sources and Corresponding Offset Values in Registers HETOFFx.....................................
HWAG Interrupt Sources and Offset Values ..........................................................................
HWAG Interrupt Descriptions ...........................................................................................
N2HET Registers .........................................................................................................
Global Configuration Register (HETGCR) Field Descriptions ......................................................
Prescale Factor Register (HETPFR) Field Descriptions .............................................................
N2HET Current Address (HETADDR) Field Descriptions ...........................................................
Offset Index Priority Level 1 Register (HETOFF1) Field Descriptions .............................................
Interrupt Offset Encoding Format .......................................................................................
Offset Index Priority Level 2 Register (HETOFF2) Field Descriptions .............................................
19-49. ADC ADEVT Pin Output Value Control Register (ADEVTOUT) Field Descriptions
List of Tables
776
776
777
777
778
778
779
780
782
783
784
784
785
785
786
786
787
787
788
788
789
790
790
801
802
803
804
805
806
817
817
823
824
825
825
846
847
855
856
858
859
859
860
860
SPNU499C – March 2018
Submit Documentation Feedback
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www.ti.com
20-22. Interrupt Enable Set Register (HETINTENAS) Field Descriptions ................................................. 861
.................................................
......................................................
Exception Control Register 2 (HETEXC2) Field Descriptions ......................................................
Interrupt Priority Register (HETPRY) Field Descriptions ............................................................
Interrupt Flag Register (HETFLG) Field Descriptions ................................................................
AND Share Control Register (HETAND) Field Descriptions ........................................................
HR Share Control Register (HETHRSH) Field Descriptions ........................................................
XOR Share Control Register (HETXOR) Field Descriptions ........................................................
Request Enable Set Register (HETREQENS) Field Descriptions ..................................................
Request Enable Clear Register (HETREQENC) Field Descriptions ...............................................
Request Destination Select Register (HETREQDS) Field Descriptions ...........................................
N2HET Direction Register (HETDIR) Field Descriptions ............................................................
N2HET Data Input Register (HETDIN) Field Descriptions ..........................................................
N2HET Data Output Register (HETDOUT) Field Descriptions .....................................................
N2HET Data Set Register (HETDSET) Field Descriptions ..........................................................
N2HET Data Clear Register (HETDCLR) Field Descriptions .......................................................
N2HET Open Drain Register (HETPDR) Field Descriptions ........................................................
N2HET Pull Disable Register (HETPULDIS) Field Descriptions ...................................................
N2HET Pull Select Register (HETPSL) Field Descriptions..........................................................
Parity Control Register (HETPCR) Field Descriptions ...............................................................
Parity Address Register (HETPAR) Field Descriptions ..............................................................
Parity Pin Register (HETPPR) Field Descriptions ....................................................................
Known State on Parity Error .............................................................................................
Suppression Filter Preload Register (HETSFPRLD) Field Descriptions...........................................
Suppression Filter Enable Register (HETSFENA) Field Descriptions .............................................
Loop Back Pair Select Register (HETLBPSEL) Field Descriptions ................................................
Loop Back Pair Direction Register (HETLBPDIR) Field Descriptions .............................................
NHET Pin Disable Register (HETPINDIS) Field Descriptions ......................................................
HWAG Registers ..........................................................................................................
HWAG Pin Select Register (HWAPINSEL) Field Descriptions .....................................................
HWAG Global Control Register 0 (HWAGCR0) Field Descriptions ................................................
HWAG Global Control Register 1 (HWAGCR1) Field Descriptions ................................................
HWAG Global Control Register 2 (HWAGCR2) Field Descriptions ................................................
HWAG Interrupt Enable Set Register (HWAENASET) Field Descriptions ........................................
HWAG Interrupts ..........................................................................................................
HWAG Interrupt Enable Clear Register (HWAENACLR) Field Descriptions......................................
HWAG Interrupt Level Set Register (HWALVLSET) Field Descriptions ...........................................
HWAG Interrupt Level Clear Register (HWALVLCLR) Field Descriptions ........................................
HWAG Interrupt Flag Register (HWAFLG) Field Descriptions ......................................................
HWAG Interrupt Offset Register 0 (HWAOFF0) Field Descriptions ................................................
HWAG Interrupt Offset Register 1 (HWAOFF1) Field Descriptions ................................................
HWAG Angle Value Register (HWAACNT) Field Descriptions .....................................................
HWAG Previous Tooth Period Value Register (HWAPCNT1) Field Descriptions ................................
HWAG Current Tooth Period Value Register (HWAPCNT) Field Descriptions ...................................
HWAG Step Width Register (HWASTWD) Field Descriptions ......................................................
HWAG Teeth Number Register (HWATHNB) Field Descriptions ..................................................
HWAG Current Teeth Number Register (HWATHVL) Field Descriptions .........................................
HWAG Filter Register (HWAFIL) Field Descriptions .................................................................
20-23. NHET Interrupt Enable Clear (HETINTENAC) Field Descriptions
861
20-24. Exception Control Register 1 (HETEXC1) Field Descriptions
862
20-25.
863
20-26.
20-27.
20-28.
20-29.
20-30.
20-31.
20-32.
20-33.
20-34.
20-35.
20-36.
20-37.
20-38.
20-39.
20-40.
20-41.
20-42.
20-43.
20-44.
20-45.
20-46.
20-47.
20-48.
20-49.
20-50.
20-51.
20-52.
20-53.
20-54.
20-55.
20-56.
20-57.
20-58.
20-59.
20-60.
20-61.
20-62.
20-63.
20-64.
20-65.
20-66.
20-67.
20-68.
20-69.
20-70.
SPNU499C – March 2018
Submit Documentation Feedback
List of Tables
Copyright © 2018, Texas Instruments Incorporated
864
864
865
866
867
868
868
869
870
871
871
872
872
873
873
874
875
876
877
877
878
878
879
880
881
882
883
884
884
885
886
886
887
888
888
889
890
891
892
893
893
894
895
895
896
77
www.ti.com
20-71. HWAG Filter Register 2 (HWAFIL2) Field Descriptions ............................................................. 896
20-72. HWAG Angle Increment Register (HWAANGI) Field Descriptions ................................................. 897
20-73. Instruction Summary
.....................................................................................................
898
20-74. FLAGS Generated by Instruction ....................................................................................... 899
20-75. Interrupt Capable Instructions ........................................................................................... 899
911
20-77.
911
20-78.
20-79.
20-80.
20-81.
20-82.
20-83.
20-84.
20-85.
20-86.
20-87.
20-88.
20-89.
20-90.
20-91.
20-92.
20-93.
20-94.
20-95.
20-96.
20-97.
21-1.
21-2.
21-3.
21-4.
21-5.
21-6.
21-7.
21-8.
21-9.
21-10.
21-11.
21-12.
21-13.
21-14.
21-15.
21-16.
21-17.
21-18.
21-19.
21-20.
21-21.
21-22.
78
..............................................................................
Source Operand Choices ...............................................................................................
Destination Operand Choices ..........................................................................................
Shift Encoding .............................................................................................................
Execution Time for ADC, ADD, AND, OR, SBB, SUB, XOR Instructions ........................................
Move Types for ADM32 .................................................................................................
Edge Select Encoding for APCNT .....................................................................................
Branch Condition Encoding for BR ....................................................................................
DADM64 Control Field Description ....................................................................................
Event Encoding Format for ECNT .....................................................................................
Magnitude Compare Order for MCMP ................................................................................
Move Type Encoding Selection ........................................................................................
MOV64 Control Field Descriptions ....................................................................................
Comparison Type Encoding Format ...................................................................................
Counter Type Encoding Format ........................................................................................
Comparison Type Encoding Format ...................................................................................
RADM64 Control Field Descriptions ...................................................................................
Step Width Encoding for SCNT ........................................................................................
SHIFT MODE Encoding Format ........................................................................................
SHIFT Condition Encoding ..............................................................................................
Event Encoding Format for WCAP ....................................................................................
Event Encoding Format for WCAPE ..................................................................................
CPENA / TMBx Priority Rules ...........................................................................................
Triggered Control Packets ...............................................................................................
DCP RAM ..................................................................................................................
DCP Parity RAM ..........................................................................................................
Field Addresses of the WCAP, ECNT, PCNT Example .............................................................
32-Bit-Transfer of Data Fields ...........................................................................................
Destination Buffer Values ................................................................................................
64-Bit-Transfer of Control Field and Data Fields .....................................................................
Destination Buffer Values ................................................................................................
HTU Control Registers ...................................................................................................
Global Control Register (HTU GC) Field Descriptions ...............................................................
Control Packet Enable Register (HTU CPENA) Field Descriptions ................................................
CPENA Write Results ....................................................................................................
CPENA Read Results ....................................................................................................
Control Packet (CP) Busy Register 0 (HTU BUSY0) Field Descriptions ..........................................
Control Packet (CP) Busy Register 1 (HTU BUSY1) Field Descriptions ..........................................
Control Packet (CP) Busy Register 2 (HTU BUSY2) Field Descriptions ..........................................
Control Packet (CP) Busy Register 3 (HTU BUSY3) Field Descriptions ..........................................
Active Control Packet and Error Register (HTU ACPE) Field Descriptions .......................................
Request Lost and Bus Error Control Register (HTU RLBECTRL) Field Descriptions ...........................
Buffer Full Interrupt Enable Set Register (HTU BFINTS) Field Descriptions .....................................
Buffer Full Interrupt Enable Clear Register (HTU BFINTC) Field Descriptions ...................................
20-76. Arithmetic / Bitwise Logic Sub-Opcodes
List of Tables
911
912
912
917
920
923
928
936
938
941
945
946
948
955
955
961
963
963
966
968
977
980
982
982
983
984
984
985
985
986
987
988
988
988
989
990
990
991
991
993
994
994
SPNU499C – March 2018
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Copyright © 2018, Texas Instruments Incorporated
www.ti.com
21-23. Interrupt Mapping Register (HTU INTMAP) Field Descriptions ..................................................... 995
21-24. Interrupt Offset Register 0 (HTU INTOFF0) Field Descriptions..................................................... 996
21-25. Interrupt Offset Register 1 (HTU INTOFF1) Field Descriptions..................................................... 997
21-26. Buffer Initialization Mode Register (HTU BIM) Field Descriptions .................................................. 998
21-27. Buffer Initialization ........................................................................................................ 998
................................................
Buffer Full Interrupt Flag Register (HTU BFINTFL) Field Descriptions ..........................................
BER Interrupt Flag Register (HTU BERINTFL) Field Descriptions ...............................................
Memory Protection 1 Start Address Register (HTU MP1S) Field Descriptions .................................
Memory Protection 1 End Address Register (HTU MP1E) Field Descriptions ..................................
Debug Control Register (HTU DCTRL) Field Descriptions ........................................................
Watch Point Register (HTU WPR) Field Descriptions ..............................................................
Watch Mask Register (HTU WMR) Field Descriptions .............................................................
Module Identification Register (HTU ID) Field Descriptions .......................................................
Parity Control Register (HTU PCR) Field Descriptions.............................................................
Parity Address Register (HTU PAR) Field Descriptions ...........................................................
Memory Protection Control and Status Register (HTU MPCS) Field Descriptions .............................
Memory Protection 0 Start Address Register (HTU MP0S) Field Descriptions .................................
Memory Protection End Address Register (HTU MP0E) Field Descriptions ....................................
Double Control Packet Memory Map .................................................................................
Initial Full Address A Register (HTU IFADDRA) Field Descriptions ..............................................
Initial Full Address B Register (HTU IFADDRB) Field Descriptions ..............................................
Initial N2HET Address and Control Register (HTU IHADDRCT) Field Descriptions ...........................
Initial Transfer Count Register (HTU ITCOUNT) Field Descriptions .............................................
Current Full Address A Register (HTU CFADDRA) Field Descriptions ..........................................
Current Full Address B Register (HTU CFADDRB) Field Descriptions ..........................................
Current Frame Count Register (HTU CFCOUNT) Field Descriptions ............................................
Application Examples for Setting the Transfer Modes of CP A and B of a DCP ...............................
GIO Control Registers ..................................................................................................
GIO Global Control Register (GIOGCR0) Field Descriptions .....................................................
GIO Interrupt Detect Register (GIOINTDET) Field Descriptions ..................................................
GIO Interrupt Polarity Register (GIOPOL) Field Descriptions .....................................................
GIO Interrupt Enable Set Register (GIOENASET) Field Descriptions ...........................................
GIO Interrupt Enable Clear Register (GIOENACLR) Field Descriptions .........................................
GIO Interrupt Priority Register (GIOLVLSET) Field Descriptions .................................................
GIO Interrupt Priority Register (GIOLVLCLR) Field Descriptions .................................................
GIO Interrupt Flag Register (GIOFLG) Field Descriptions .........................................................
GIO Offset 1 Register (GIOOFF1) Field Descriptions ..............................................................
GIO Offset 2 Register (GIOOFF2) Field Descriptions ..............................................................
GIO Emulation 1 Register (GIOEMU1) Field Descriptions ........................................................
GIO Emulation 2 Register (GIOEMU2) Field Descriptions ........................................................
GIO Data Direction Registers (GIODIR[A-B]) Field Descriptions .................................................
GIO Data Input Registers (GIODIN[A-B]) Field Descriptions ......................................................
GIO Data Output Registers (GIODOUT[A-B]) Field Descriptions .................................................
GIO Data Set Registers (GIODSET[A-B]) Field Descriptions .....................................................
GIO Data Clear Registers (GIODCLR[A-B]) Field Descriptions ...................................................
GIO Open Drain Registers (GIOPDR[A-B]) Field Descriptions ...................................................
GIO Pull Disable Registers (GIOPULDIS[A-B]) Field Descriptions ..............................................
GIO Pull Select Registers (GIOPSL[A-B]) Field Descriptions .....................................................
21-28. Request Lost Flag Register (HTU RLOSTFL) Field Descriptions
21-29.
21-30.
21-31.
21-32.
21-33.
21-34.
21-35.
21-36.
21-37.
21-38.
21-39.
21-40.
21-41.
21-42.
21-43.
21-44.
21-45.
21-46.
21-47.
21-48.
21-49.
21-50.
22-1.
22-2.
22-3.
22-4.
22-5.
22-6.
22-7.
22-8.
22-9.
22-10.
22-11.
22-12.
22-13.
22-14.
22-15.
22-16.
22-17.
22-18.
22-19.
22-20.
22-21.
SPNU499C – March 2018
Submit Documentation Feedback
List of Tables
Copyright © 2018, Texas Instruments Incorporated
1000
1000
1001
1002
1002
1003
1004
1004
1005
1006
1007
1008
1011
1011
1012
1013
1013
1014
1015
1016
1017
1018
1019
1029
1030
1031
1032
1033
1034
1035
1037
1038
1039
1040
1041
1042
1043
1043
1044
1044
1045
1045
1046
1046
79
www.ti.com
1047
23-1.
1053
23-2.
23-3.
23-4.
23-5.
23-6.
23-7.
23-8.
23-9.
23-10.
23-11.
23-12.
23-13.
23-14.
23-15.
23-16.
23-17.
23-18.
23-19.
23-20.
23-21.
23-22.
23-23.
23-24.
23-25.
23-26.
23-27.
23-28.
23-29.
23-30.
23-31.
23-32.
23-33.
23-34.
23-35.
23-36.
23-37.
23-38.
23-39.
23-40.
23-41.
23-42.
23-43.
23-44.
23-45.
23-46.
23-47.
23-48.
80
.............................................................
FlexRay Address Range Table ........................................................................................
FlexRay Transfer Unit Event Trigger Conditions ....................................................................
Mirroring Address Mapping ............................................................................................
Mirroring Address Mapping ............................................................................................
Error Modes of the POC (Degradation Model) ......................................................................
State Transitions of Communication Controller Overall State Machine ..........................................
State Transitions WAKEUP ............................................................................................
Definition of Cycle Set ..................................................................................................
Examples for Valid Cycle Sets ........................................................................................
Channel Filtering Configuration .......................................................................................
Scan of Message RAM .................................................................................................
Assignment of Input Buffer Command Mask Bits ...................................................................
Assignment of Input Buffer Command Request Bits ...............................................................
Assignment of Output Buffer Command Mask Bits .................................................................
Assignment of Output Buffer Command Request Bits .............................................................
Module Interrupt Flags and Interrupt Line Enable ..................................................................
Transfer Unit Registers .................................................................................................
Global Static Number 0 (GSN0) Field Descriptions ................................................................
Global Static Number 1 (GSN1) Field Descriptions ................................................................
Global Control Set/Reset (GCS/GCR) Field Descriptions .........................................................
Transfer Status Current Buffer (TSCB) Field Descriptions ........................................................
Last Transferred Buffer to Communication Controller (LTBCC) Field Descriptions ............................
Last Transferred Buffer to System Memory (LTBSM) Field Descriptions........................................
Transfer Base Address (TBA) Field Descriptions ...................................................................
Next Transfer Base Address (NTBA) Field Descriptions ...........................................................
Base Address of Mirrored Status (BAMS) Field Descriptions .....................................................
Start Address of Memory Protection (SAMP) Field Descriptions .................................................
End Address of Memory Protection (EAMP) Field Descriptions ..................................................
Transfer to System Memory Occurred (TSMOn) Field Descriptions .............................................
Transfer to Communication Controller Occurred (TCCOn) Field Descriptions ..................................
Transfer Occurred Offset (TOOFF) Field Descriptions .............................................................
Parity Error Address (PEADR) Field Descriptions ..................................................................
Coding of Parity Error Address ........................................................................................
Transfer Error Interrupt Flag (TEIF) Field Descriptions ............................................................
Transfer Error Interrupt Enable Set (TEIRES) Field Descriptions ................................................
Transfer Error Interrupt Enable Reset (TEIRER) Field Descriptions .............................................
Trigger Transfer to System Memory Set 1 (TTSMS1) Field Descriptions .......................................
Trigger Transfer to System Memory Reset 1 (TTSMR1) Field Descriptions ....................................
Trigger Transfer to System Memory Set 2 (TTSMS2) Field Descriptions .......................................
Trigger Transfer to System Memory Reset 2 (TTSMR2) Field Descriptions ....................................
Trigger Transfer to System Memory Set 3 (TTSMS3) Field Descriptions .......................................
Trigger Transfer to System Memory Reset 3 (TTSMR3) Field Descriptions ....................................
Trigger Transfer to System Memory Set 4 (TTSMS4) Field Descriptions .......................................
Trigger Transfer to System Memory Reset 4 (TTSMR4) Field Descriptions ....................................
Trigger Transfer to Communication Controller Set 1 (TTCCS1) Field Descriptions ............................
Trigger Transfer to Communication Controller Reset 1 (TTCCR1) Field Descriptions.........................
Trigger Transfer to Communication Controller Set 2 (TTCCS2) Field Descriptions ............................
Trigger Transfer to Communication Controller Reset 2 (TTCCR2) Field Descriptions ........................
22-22. Output Buffer and Pull Control Behavior for GIO Pins
List of Tables
1058
1060
1061
1067
1070
1073
1082
1082
1083
1089
1092
1092
1094
1094
1107
1108
1110
1110
1112
1114
1115
1115
1116
1116
1117
1117
1118
1120
1122
1123
1124
1124
1125
1127
1128
1129
1129
1130
1130
1131
1131
1132
1132
1133
1133
1134
1134
SPNU499C – March 2018
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23-49. Trigger Transfer to Communication Controller Set 3 (TTCCS3) Field Descriptions ............................ 1135
23-50. Trigger Transfer to Communication Controller Reset 3 (TTCCR3) Field Descriptions......................... 1135
23-51. Trigger Transfer to Communication Controller Set 4 (TTCCS4) Field Descriptions ............................ 1136
23-52. Trigger Transfer to Communication Controller Reset 4 (TTCCR4) Field Descriptions......................... 1136
23-53. Enable Transfer on Event to System Memory Set 1 (ETESMS1) Field Descriptions .......................... 1137
23-54. Enable Transfer on Event to System Memory Reset 1 (ETESMR1) Field Descriptions ....................... 1137
23-55. Enable Transfer on Event to System Memory Set 2 (ETESMS2) Field Descriptions .......................... 1138
23-56. Enable Transfer on Event to System Memory Reset 2 (ETESMR2) Field Descriptions ....................... 1138
23-57. Enable Transfer on Event to System Memory Set 3 (ETESMS3) Field Descriptions .......................... 1139
23-58. Enable Transfer on Event to System Memory Reset 3 (ETESMR3) Field Descriptions ....................... 1139
23-59. Enable Transfer on Event to System Memory Set 4 (ETESMS4) Field Descriptions .......................... 1140
23-60. Enable Transfer on Event to System Memory Reset 4 (ETESMR4) Field Descriptions ....................... 1140
23-61. Clear on Event to System Memory Set 1 (CESMS1) Field Descriptions ........................................ 1141
23-62. Clear on Event to System Memory Reset 1 (CESMR1) Field Descriptions ..................................... 1141
23-63. Clear on Event to System Memory Set 2 (CESMS2) Field Descriptions ........................................ 1142
23-64. Clear on Event to System Memory Reset 2 (CESMR2) Field Descriptions ..................................... 1142
23-65. Clear on Event to System Memory Set 3 (CESMS3) Field Descriptions ........................................ 1143
23-66. Clear on Event to System Memory Reset 3 (CESMR3) Field Descriptions ..................................... 1143
23-67. Clear on Event to System Memory Set 4 (CESMS4) Field Descriptions ........................................ 1144
23-68. Clear on Event to System Memory Reset 4 (CESMR4) Field Descriptions ..................................... 1144
23-69. Transfer to System Memory Interrupt Enable Set 1 (TSMIES1) Field Descriptions ............................ 1145
23-70. Transfer to System Memory Interrupt Enable Reset 1 (TSMIER1) Field Descriptions
........................
1145
23-71. Transfer to System Memory Interrupt Enable Set 2 (TSMIES2) Field Descriptions ............................ 1146
........................
Transfer to System Memory Interrupt Enable Set 3 (TSMIES3) Field Descriptions ............................
Transfer to System Memory Interrupt Enable Reset 3 (TSMIER3) Field Descriptions ........................
Transfer to System Memory Interrupt Enable Set 4 (TSMIES4) Field Descriptions ............................
Transfer to System Memory Interrupt Enable Reset 4 (TSMIER4) Field Descriptions ........................
Transfer to Communication Controller Interrupt Enable Set 1 (TCCIES1) Field Descriptions ................
Transfer to Communication Controller Interrupt Enable Reset 1 (TCCIER1) Field Descriptions .............
Transfer to Communication Controller Interrupt Enable Set 2 (TCCIES2) Field Descriptions ................
Transfer to Communication Controller Interrupt Enable Reset 2 (TCCIER2) Field Descriptions .............
Transfer to Communication Controller Interrupt Enable Set 3 (TCCIES3) Field Descriptions ................
Transfer to Communication Controller Interrupt Enable Reset 3 (TCCIER3) Field Descriptions .............
Transfer to Communication Controller Interrupt Enable Set 4 (TCCIES4) Field Descriptions ................
Transfer to Communication Controller Interrupt Enable Reset 4 (TCCIER4) Field Descriptions .............
Transfer Configuration RAM (TCR) Field Descriptions .............................................................
Parity Information in TCR Parity Test Mode Field Descriptions ...................................................
Communication Controller Registers .................................................................................
Test Register 1 (TEST1) Field Descriptions .........................................................................
Test Register 2 (TEST2) Field Descriptions .........................................................................
Lock Register (LCK) Field Descriptions ..............................................................................
Error Interrupt Register (EIR) Field Descriptions ....................................................................
Status Interrupt Register (SIR) Field Descriptions ..................................................................
Error Interrupt Line Select Register (EILS) Field Descriptions ....................................................
Status Interrupt Line Select Register (SILS) Field Descriptions ..................................................
Error Interrupt Set/Reset Register (EIES/EIER) Field Descriptions ..............................................
Status Interrupt Enable Set/Reset Register (SIES/SIER) Field Descriptions ...................................
Interrupt Line Enable Register (ILE) Field Descriptions ............................................................
23-72. Transfer to System Memory Interrupt Enable Reset 2 (TSMIER2) Field Descriptions
23-73.
23-74.
23-75.
23-76.
23-77.
23-78.
23-79.
23-80.
23-81.
23-82.
23-83.
23-84.
23-85.
23-86.
23-87.
23-88.
23-89.
23-90.
23-91.
23-92.
23-93.
23-94.
23-95.
23-96.
23-97.
SPNU499C – March 2018
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List of Tables
Copyright © 2018, Texas Instruments Incorporated
1146
1147
1147
1148
1148
1149
1149
1150
1150
1151
1151
1152
1152
1153
1154
1156
1159
1163
1165
1166
1168
1171
1173
1175
1177
1179
81
www.ti.com
23-98. Timer 0 Configuration Register (T0C) Field Descriptions .......................................................... 1180
23-99. Timer 1 Configuration Register (T1C) Field Descriptions .......................................................... 1181
23-100. Stop Watch Register 1 (STPW1) Field Descriptions .............................................................. 1182
23-101. Stop Watch Register 2 (STPW2) Field Descriptions .............................................................. 1183
23-102. SUC Configuration Register 1 (SUCC1) Field Descriptions ...................................................... 1184
23-103. SUC Configuration Register 2 (SUCC2) Field Descriptions ...................................................... 1188
23-104. SUC Configuration Register 3 (SUCC3) Field Descriptions ...................................................... 1189
23-105. NEM Configuration Register (NEMC) Field Descriptions ......................................................... 1189
23-106. PRT Configuration Register 1 (PRTC1) Field Descriptions ...................................................... 1190
23-107. PRT Configuration Register 2 (PRTC2) Field Descriptions ...................................................... 1191
23-108. MHD Configuration Register (MHDC) Field Descriptions......................................................... 1192
23-109. GTU Configuration Register 1 (GTUC1) Field Descriptions ...................................................... 1193
23-110. GTU Configuration Register 2 (GTUC2) Field Descriptions ...................................................... 1193
23-111. GTU Configuration Register 3 (GTUC3) Field Descriptions ...................................................... 1194
23-112. GTU Configuration Register 4 (GTUC4) Field Descriptions ...................................................... 1195
23-113. GTU Configuration Register 5 (GTUC5) Field Descriptions ...................................................... 1195
23-114. GTU Configuration Register 6 (GTUC6) Field Descriptions ...................................................... 1196
23-115. GTU Configuration Register 7 (GTUC7) Field Descriptions ...................................................... 1196
23-116. GTU Configuration Register 8 (GTUC8) Field Descriptions ...................................................... 1197
23-117. GTU Configuration Register 9 (GTUC9) Field Descriptions ...................................................... 1197
23-118. GTU Configuration Register 10 (GTUC10) Field Descriptions ................................................... 1198
23-119. GTU Configuration Register 11 (GTUC11) Field Descriptions ................................................... 1199
23-120. Communication Controller Status Vector Register (CCSV) Field Descriptions ................................ 1200
1202
23-122.
1203
23-123.
23-124.
23-125.
23-126.
23-127.
23-128.
23-129.
23-130.
23-131.
23-132.
23-133.
23-134.
23-135.
23-136.
23-137.
23-138.
23-139.
23-140.
23-141.
23-142.
23-143.
23-144.
23-145.
23-146.
82
.................................
Slot Counter Vector Register (SCV) Field Descriptions ..........................................................
Macrotick and Cycle Counter Register (MTCCV) Field Descriptions ...........................................
Rate Correction Value Register (RCV) Field Descriptions .......................................................
Offset Correction Value Register (OCV) Field Descriptions ......................................................
Sync Frame Status Register (SFS) Field Descriptions ...........................................................
Symbol Window and NIT Status Register (SWNIT) Field Descriptions .........................................
Aggregated Channel Status Register (ACS) Field Descriptions .................................................
Even Sync ID Registers (ESIDn) Field Descriptions ..............................................................
Odd Sync ID Registers (OSIDn) Field Descriptions ...............................................................
Assignment of Data Bytes to Network Management Vector .....................................................
Message RAM Configuration Register (MRC) Field Descriptions ...............................................
Buffer Configuration ...................................................................................................
FIFO Rejection Filter Register (FRF) Field Descriptions .........................................................
FIFO Rejection Filter Mask Register (FRFM) Field Descriptions ................................................
FIFO Critical Level Register (FCL) Field Descriptions ............................................................
Message Handler Status (MHDS) Field Descriptions .............................................................
Last Dynamic Transmit Slot (LDTS) Field Descriptions ..........................................................
FIFO Status Register (FSR) Field Descriptions ....................................................................
Message Handler Constraint Flags (MHDF) Field Descriptions .................................................
Transmission Request Registers (TXRQn) Field Descriptions ..................................................
New Data Registers (NDATn) Field Descriptions..................................................................
Message Buffer Status Changed Register (MBSCn) Field Descriptions .......................................
Core Release Register (CREL) Field Descriptions ................................................................
Release Coding ........................................................................................................
Endian Register (ENDN) Field Descriptions........................................................................
23-121. Communication Controller Error Vector Register (CCEV) Field Descriptions
List of Tables
1203
1204
1204
1205
1206
1207
1209
1210
1211
1212
1213
1214
1215
1215
1216
1217
1218
1219
1221
1223
1224
1225
1225
1225
SPNU499C – March 2018
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www.ti.com
23-147. Write Data Section Registers (WRDSn) Field Descriptions ...................................................... 1226
23-148. Write Header Section Register 1 (WRHS1) Field Descriptions .................................................. 1227
23-149. Channel Filter Control Bit Descriptions
.............................................................................
1228
23-150. Write Header Section Register 2 (WRHS2) Field Descriptions .................................................. 1228
23-151. Write Header Section Register 3 (WRHS3) Field Descriptions .................................................. 1229
..............................................
23-153. Input Buffer Command Request Register (IBCR) Field Descriptions ...........................................
23-154. Read Data Section Registers (RDDSn) Field Descriptions ......................................................
23-155. Read Header Section Register 1 (RDHS1) Field Descriptions ..................................................
23-156. Read Header Section Register 2 (RDHS2) Field Descriptions ..................................................
23-157. Read Header Section Register 3 (RDHS3) Field Descriptions ..................................................
23-158. Message Buffer Status Register (MBS) Field Descriptions ......................................................
23-159. Output Buffer Command Mask Register (OBCM) Field Descriptions ...........................................
23-160. Output Buffer Command Mask Register (OBCR) Field Descriptions ...........................................
23-161. Assignment of FlexRay Configuration Parameters ...............................................................
24-1. Parameters of the CAN Bit Time ......................................................................................
24-2. Message Object Field Descriptions ...................................................................................
24-3. Message RAM Addressing in Debug/Suspend and RDA Mode ..................................................
24-4. Message Interface Register Sets 1 and 2............................................................................
24-5. Message Interface Register 3 .........................................................................................
24-6. DCAN Control Registers ...............................................................................................
24-7. CAN Control Register Field Descriptions ............................................................................
24-8. Error and Status Register Field Descriptions ........................................................................
24-9. Error Counter Register Field Descriptions ...........................................................................
24-10. Bit Timing Register Field Descriptions................................................................................
24-11. Interrupt Register Field Descriptions..................................................................................
24-12. Test Register Field Descriptions ......................................................................................
24-13. Parity Error Code Register Field Descriptions .......................................................................
24-14. Core Release Register (DCAN REL) Field Descriptions ...........................................................
24-15. Auto-Bus-On Time Register Field Descriptions .....................................................................
24-16. Transmission Request Registers Field Descriptions ...............................................................
24-17. New Data Registers Field Descriptions ..............................................................................
24-18. Interrupt Pending Registers Field Descriptions......................................................................
24-19. Message Valid Registers Field Descriptions.........................................................................
24-20. Interrupt Multiplexer Registers Field Descriptions ..................................................................
24-21. IF1/IF2 Command Register Field Descriptions ......................................................................
24-22. IF1/IF2 Mask Register Field Descriptions ............................................................................
24-23. IF1/IF2 Arbitration Register Field Descriptions ......................................................................
24-24. IF1/IF2 Message Control Register Field Descriptions ..............................................................
24-25. IF3 Observation Register Field Descriptions ........................................................................
24-26. IF3 Mask Register Field Descriptions ................................................................................
24-27. IF3 Arbitration Register Field Descriptions ...........................................................................
24-28. IF3 Message Control Register Field Descriptions ..................................................................
24-29. IF3 Update Control Register Field Descriptions .....................................................................
24-30. CAN TX IO Control Register Field Descriptions ....................................................................
24-31. CAN RX IO Control Register Field Descriptions ....................................................................
25-1. Pin Configurations .......................................................................................................
25-2. Clocking Modes..........................................................................................................
25-3. Pin Mapping for SIMO Pin with MSB First ...........................................................................
23-152. Input Buffer Command Mask Register (IBCM) Field Descriptions
SPNU499C – March 2018
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List of Tables
Copyright © 2018, Texas Instruments Incorporated
1230
1231
1232
1233
1234
1235
1236
1239
1240
1243
1249
1255
1257
1259
1261
1280
1282
1284
1286
1287
1288
1289
1290
1290
1291
1292
1294
1296
1298
1299
1301
1303
1304
1306
1308
1310
1311
1312
1314
1315
1316
1321
1328
1335
83
www.ti.com
25-4.
Pin Mapping for SOMI Pin with MSB First ........................................................................... 1335
25-5.
Pin Mapping for SIMO Pin with LSB First ............................................................................ 1336
25-6.
Pin Mapping for SOMI Pin with LSB First ............................................................................ 1336
25-7.
SPI Registers ............................................................................................................ 1349
25-8.
SPI Global Control Register 0 (SPIGCR0) Field Descriptions
1350
25-9.
SPI Global Control Register 1 (SPIGCR1) Field Descriptions
1351
25-10.
25-11.
25-12.
25-13.
25-14.
25-15.
25-16.
25-17.
25-18.
25-19.
25-20.
25-21.
25-22.
25-23.
25-24.
25-25.
25-26.
25-27.
25-28.
25-29.
25-30.
25-31.
25-32.
25-33.
25-34.
25-35.
25-36.
25-37.
25-38.
25-39.
25-40.
25-41.
25-42.
25-43.
25-44.
25-45.
25-46.
25-47.
25-48.
25-49.
25-50.
25-51.
25-52.
84
....................................................
....................................................
SPI Interrupt Register (SPIINT0) Field Descriptions ................................................................
SPI Interrupt Level Register (SPILVL) Field Descriptions .........................................................
SPI Flag Register (SPIFLG) Field Descriptions .....................................................................
SPI Pin Control (SPIPC0) Field Descriptions ........................................................................
SPI Pin Control Register (SPIPC1) Field Descriptions .............................................................
SPI Pin Control Register 2 (SPIPC2) Field Descriptions...........................................................
SPI Pin Control Register 3 (SPIPC3) Field Descriptions...........................................................
SPI Pin Control Register 4 (SPIPC4) Field Descriptions...........................................................
SPI Pin Control Register 5 (SPIPC5) Field Descriptions...........................................................
SPI Pin Control Register 6 (SPIPC6) Field Descriptions...........................................................
SPI Pin Control Register 7 (SPIPC7) Field Descriptions...........................................................
SPI Pin Control Register 8 (SPIPC8) Field Descriptions...........................................................
SPI Transmit Data Register 0 (SPIDAT0) Field Descriptions .....................................................
SPI Transmit Data Register 1 (SPIDAT1) Field Descriptions .....................................................
Chip Select Number Active ............................................................................................
SPI Receive Buffer Register (SPIBUF) Field Descriptions ........................................................
SPI Emulation Register (SPIEMU) Field Descriptions..............................................................
SPI Delay Register (SPIDELAY) Field Descriptions ................................................................
SPI Default Chip Select Register (SPIDEF) Field Descriptions ...................................................
SPI Data Format Registers (SPIFMT) Field Descriptions..........................................................
Transfer Group Interrupt Vector 0 (INTVECT0) .....................................................................
Transfer Group Interrupt Vector 1 (INTVECT1) .....................................................................
SPI Pin Control Register 9 (SPIPC9) Field Descriptions...........................................................
SPI Parallel/Modulo Mode Control Register (SPIPMCTRL) Field Descriptions .................................
Multi-buffer Mode Enable Register (MIBSPIE) Field Descriptions ................................................
TG Interrupt Enable Set Register (TGITENST) Field Descriptions ...............................................
TG Interrupt Enable Clear Register (TGITENCR) Field Descriptions ............................................
Transfer Group Interrupt Level Set Register (TGITLVST) Field Descriptions ...................................
Transfer Group Interrupt Level Clear Register (TGITLVCR) Field Descriptions ................................
Transfer Group Interrupt Flag Register (TGINTFLG) Field Descriptions ........................................
Tick Count Register (TICKCNT) Field Descriptions ................................................................
Last TG End Pointer (LTGPEND) Field Descriptions ..............................................................
TG Control Registers (TGxCTRL) Field Descriptions ..............................................................
DMA Channel Control Register (DMAxCTRL) Field Descriptions ................................................
MibSPI DMAxCOUNT Register (ICOUNT) Field Descriptions ....................................................
MibSPI DMA Large Count Register (DMACNTLEN) Field Descriptions .........................................
Multi-buffer RAM Uncorrectable Parity Error Control Register (UERRCTRL) Field Descriptions ............
Multi-buffer RAM Uncorrectable Parity Error Status Register (UERRSTAT) Field Descriptions ..............
RXRAM Uncorrectable Parity Error Address Register (UERRADDR1) Field Descriptions ....................
TXRAM Uncorrectable Parity Error Address Register (UERRADDR0) Field Descriptions ....................
RXRAM Overrun Buffer Address Register (RXOVRN_BUF_ADDR) Field Descriptions ......................
I/O-Loopback Test Control Register (IOLPBKTSTCR) Field Descriptions.......................................
SPI Extended Prescale Register 1 (EXTENDED_PRESCALE1) Field Descriptions ...........................
List of Tables
1352
1354
1355
1358
1359
1361
1362
1363
1365
1367
1368
1369
1371
1372
1374
1375
1377
1377
1380
1381
1383
1384
1386
1387
1390
1391
1392
1393
1394
1395
1396
1397
1398
1401
1403
1404
1404
1405
1406
1407
1408
1409
1411
SPNU499C – March 2018
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Copyright © 2018, Texas Instruments Incorporated
www.ti.com
25-53. SPI Extended Prescale Register 2 (EXTENDED_PRESCALE2) Field Descriptions ........................... 1413
25-54. Multi-Buffer RAM Register Summary ................................................................................. 1416
25-55. Multi-Buffer RAM Transmit Data Register (TXRAM) Field Descriptions ......................................... 1417
............................................................................................
Multi-Buffer Receive Buffer Register (RXRAM) Field Descriptions ...............................................
Superfractional Bit Modulation for SCI Mode (Normal Configuration) ............................................
Superfractional Bit Modulation for SCI Mode (Maximum Configuration) .........................................
SCI Mode (Minimum Configuration) ..................................................................................
SCI/LIN Interrupts .......................................................................................................
Response Length Info Using IDBYTE Field Bits [5:4] for LIN Standards Earlier than 1.3 .....................
Response Length with SCIFORMAT[18:16] Programming ........................................................
Superfractional Bit Modulation for LIN Master Mode and Slave Mode ...........................................
Timeout Values in Tbit Units ............................................................................................
SCI/LIN Control Registers ..............................................................................................
SCI Global Control Register 0 (SCIGCR0) Field Descriptions ....................................................
SCI Global Control Register 1 (SCIGCR1) Field Descriptions ....................................................
SCI Receiver Status Flags .............................................................................................
SCI Transmitter Status Flags ..........................................................................................
SCI Global Control Register 2 (SCIGCR2) Field Descriptions ....................................................
SCI Set Interrupt Register (SCISETINT) Field Descriptions .......................................................
SCI Clear Interrupt Register (SCICLEARINT) Field Descriptions.................................................
SCI Set Interrupt Level Register (SCISETINTLVL) Field Descriptions ...........................................
SCI Clear Interrupt Level Register (SCICLEARINTLVL) Field Descriptions ....................................
SCI Flags Register (SCIFLR) Field Descriptions....................................................................
SCI Interrupt Vector Offset 0 (SCIINTVECT0) Field Descriptions ................................................
SCI Interrupt Vector Offset 1 (SCIINTVECT1) Field Descriptions ................................................
SCI Format Control Register (SCIFORMAT) Field Descriptions ..................................................
Baud Rate Selection Register (BRS) Field Descriptions ...........................................................
Comparative Baud Values for Different P Values, Asynchronous Mode ........................................
Receiver Emulation Data Buffer (SCIED) Field Descriptions ......................................................
Receiver Data Buffer (SCIRD) Field Descriptions ..................................................................
Transmit Data Buffer Register (SCITD) Field Descriptions ........................................................
SCI Pin I/O Control Register 0 (SCIPIO0) Field Descriptions .....................................................
SCI Pin I/O Control Register 1 (SCIPIO1) Field Descriptions .....................................................
LINTX Pin Control ......................................................................................................
LINRX Pin Control ......................................................................................................
SCI Pin I/O Control Register 2 (SCIPIO2) Field Descriptions ....................................................
SCI Pin I/O Control Register 3 (SCIPIO3) Field Descriptions ....................................................
SCI Pin I/O Control Register 4 (SCIPIO4) Field Descriptions ....................................................
SCI Pin I/O Control Register 5 (SCIPIO5) Field Descriptions ....................................................
SCI Pin I/O Control Register 6 (SCIPIO6) Field Descriptions .....................................................
SCI Pin I/O Control Register 7 (SCIPIO7) Field Descriptions .....................................................
SCI Pin I/O Control Register 8 (SCIPIO8) Field Descriptions ....................................................
LIN Compare Register (LINCOMPARE) Field Descriptions .......................................................
LIN Receive Buffer 0 Register (LINRD0) Field Descriptions ......................................................
LIN Receive Buffer 1 Register (RD1) Field Descriptions...........................................................
LIN Mask Register (LINMASK) Field Descriptions ..................................................................
LIN Identification Register (LINID) Field Descriptions ..............................................................
LIN Transmit Buffer 0 Register (LINTD0) Field Descriptions ......................................................
25-56. Chip Select Number Active
1419
25-57.
1420
26-1.
26-2.
26-3.
26-4.
26-5.
26-6.
26-7.
26-8.
26-9.
26-10.
26-11.
26-12.
26-13.
26-14.
26-15.
26-16.
26-17.
26-18.
26-19.
26-20.
26-21.
26-22.
26-23.
26-24.
26-25.
26-26.
26-27.
26-28.
26-29.
26-30.
26-31.
26-32.
26-33.
26-34.
26-35.
26-36.
26-37.
26-38.
26-39.
26-40.
26-41.
26-42.
26-43.
26-44.
SPNU499C – March 2018
Submit Documentation Feedback
List of Tables
Copyright © 2018, Texas Instruments Incorporated
1437
1438
1438
1445
1452
1452
1454
1461
1474
1475
1476
1479
1479
1480
1482
1485
1489
1492
1495
1502
1502
1503
1504
1505
1505
1506
1507
1507
1508
1508
1508
1509
1510
1511
1512
1513
1514
1514
1515
1516
1516
1517
1518
1519
85
www.ti.com
26-45. LIN Transmit Buffer 1 Register (LINTD1) Field Descriptions ...................................................... 1519
26-46. Maximum Baud Rate Selection Register (MBRS) Field Descriptions ............................................ 1520
26-47. Input/Output Error Enable Register (IODFTCTRL) Field Descriptions ........................................... 1521
1524
27-1.
1535
27-2.
27-3.
27-4.
27-5.
27-6.
27-7.
27-8.
27-9.
27-10.
27-11.
27-12.
27-13.
27-14.
27-15.
27-16.
27-17.
27-18.
27-19.
27-20.
27-21.
27-22.
27-23.
27-24.
27-25.
27-26.
27-27.
27-28.
27-29.
27-30.
27-31.
27-32.
27-33.
28-1.
28-2.
28-3.
28-4.
28-5.
28-6.
28-7.
28-8.
28-9.
28-10.
28-11.
28-12.
86
...........................................
SCI Interrupts ............................................................................................................
DMA and Interrupt Requests in Multiprocessor Modes ............................................................
SCI Control Registers Summary ......................................................................................
SCI Global Control Register 0 (SCIGCR0) Fied Descriptions .....................................................
SCI Global Control Register 1 (SCIGCR1) Field Descriptions ....................................................
SCI Set Interrupt Register (SCISETINT) Field Descriptions .......................................................
SCI Clear Interrupt Register (SCICLEARINT) Field Descriptions.................................................
SCI Set Interrupt Level Register (SCISETINTLVL) Field Descriptions ...........................................
SCI Clear Interrupt Level Register (SCICLEARINTLVL) Field Descriptions ....................................
SCI Flags Register (SCIFLR) Field Descriptions....................................................................
SCI Receiver Status Flags ............................................................................................
SCI Transmitter Status Flags .........................................................................................
SCI Interrupt Vector Offset 0 (SCIINTVECT0) Field Descriptions ................................................
SCI Interrupt Vector Offset 1 (SCIINTVECT1) Field Descriptions ................................................
SCI Format Control Register (SCIFORMAT) Field Descriptions ..................................................
Baud Rate Selection Register (BRS) Field Descriptions ..........................................................
Comparative Baud Values (Asynchronous Mode) .................................................................
Receiver Emulation Data Buffer (SCIED) Field Descriptions ......................................................
Receiver Data Buffer (SCIRD) Field Descriptions ..................................................................
Transmit Data Buffer Register (SCITD) Field Descriptions ........................................................
SCI Pin I/O Control Register 0 (SCIPIO0) Field Descriptions .....................................................
SCI Pin I/O Control Register 1 (SCIPIO1) Field Descriptions .....................................................
SCITX Pin Control ......................................................................................................
SCIRX Pin Control .....................................................................................................
SCI Pin I/O Control Register 2 (SCIPIO2) Field Descriptions ....................................................
SCI Pin I/O Control Register 3 (SCIPIO3) Field Descriptions ....................................................
SCI Pin I/O Control Register 4 (SCIPIO4) Field Descriptions ....................................................
SCI Pin I/O Control Register 5 (SCIPIO5) Field Descriptions ....................................................
SCI Pin I/O Control Register 6 (SCIPIO6) Field Descriptions .....................................................
SCI Pin I/O Control Register 7 (SCIPIO7) Field Descriptions .....................................................
SCI Pin I/O Control Register 8 (SCIPIO8) Field Descriptions ....................................................
Input/Output Error Enable Register (IODFTCTRL) Field Descriptions ...........................................
Input Buffer, Output Buffer, and Pull Control Behavior as GPIO Pins ...........................................
Ways to Generate a NACK Bit ........................................................................................
Interrupt Requests Generated by I2C Module .......................................................................
I2C Control Registers ...................................................................................................
I2C Own Address Manager Register (I2COAR) Field Descriptions ..............................................
Correct Mode for OA Bits ..............................................................................................
I2C Interrupt Mask Register (I2CIMR) Field Descriptions..........................................................
I2C Status Register (I2CSTR) Field Descriptions ...................................................................
I2C Clock Divider Low Register (I2CCKL) Field Descriptions .....................................................
I2C Clock Control High Register (I2CCKH) Field Descriptions ...................................................
I2C Data Count Register (I2CCNT) Field Descriptions.............................................................
I2C Data Receive Register (I2CDRR) Field Descriptions ..........................................................
I2C Slave Address Register (I2CSAR) Field Descriptions .........................................................
26-48. Input Buffer, Output Buffer, and Pull Control Behavior as GPIO Pins
List of Tables
1536
1540
1541
1542
1545
1547
1549
1550
1552
1555
1555
1556
1556
1557
1558
1558
1559
1559
1560
1560
1561
1561
1561
1562
1563
1564
1565
1566
1567
1567
1568
1571
1580
1585
1588
1589
1589
1590
1591
1594
1594
1595
1595
1596
SPNU499C – March 2018
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Copyright © 2018, Texas Instruments Incorporated
www.ti.com
28-13. Correct Mode for SA Bits ............................................................................................... 1596
28-14. I2C Data Transmit Register (I2CDXR) Field Descriptions ......................................................... 1596
28-15. I2C Mode Register (I2CMDR) Field Descriptions ................................................................... 1597
28-16. I2C Module Condition, Bus Activity, and Mode...................................................................... 1599
28-17. I2C Module Operating Modes
.........................................................................................
1599
28-18. Number of Bits Sent on Bus ........................................................................................... 1599
28-19. I2C Interrupt Vector Register (I2CIVR) Field Descriptions ......................................................... 1600
28-20. Interrupt Codes for INTCODE Bits .................................................................................... 1600
28-21. I2C Extended Mode Register (I2CEMDR) Field Descriptions ..................................................... 1601
28-22. I2C Prescale Register (I2CPSC) Field Descriptions ................................................................ 1601
28-23. I2C Peripheral ID Register 1 (I2CPID1) Field Descriptions ........................................................ 1602
28-24. I2C Peripheral ID Register 2 (I2CPID2) Field Descriptions ........................................................ 1602
......................................................
.........................................................
I2C Pin Direction Register (I2CPDIR) Field Descriptions ..........................................................
I2C Data Input Register (I2CDIN) Field Descriptions ...............................................................
I2C Data Output Register (I2CDOUT) Field Descriptions..........................................................
I2C Data Set Register (I2CDSET) Field Description ...............................................................
I2C Data Clear Register (I2CDSET) Field Descriptions ............................................................
I2C Pin Open Drain Register (I2CPDR) Field Descriptions........................................................
I2C Pull Disable Register (I2CPDIS) Field Descriptions ...........................................................
I2C Pull Select Register (I2CPSEL) Field Descriptions ............................................................
Input Buffer, Output Buffer, and Pull Control Behavior as GPIO Pins ...........................................
I2C Pins Slew Rate Select Register (I2CSRS) Field Descriptions................................................
EMAC and MDIO Signals for MII Interface ..........................................................................
EMAC and MDIO Signals for RMII Interface ........................................................................
MDIO Multiplexing Control .............................................................................................
MII / RMII Multiplexing Control ........................................................................................
Ethernet Frame Description ............................................................................................
Basic Descriptor Description ...........................................................................................
Receive Frame Treatment Summary .................................................................................
Middle of Frame Overrun Treatment .................................................................................
Emulation Control .......................................................................................................
EMAC Control Module Registers ......................................................................................
EMAC Control Module Revision ID Register (REVID) Field Descriptions .......................................
EMAC Control Module Software Reset Register (SOFTRESET) .................................................
EMAC Control Module Interrupt Control Register (INTCONTROL) ..............................................
EMAC Control Module Receive Threshold Interrupt Enable Register (C0RXTHRESHEN) ...................
EMAC Control Module Receive Interrupt Enable Register (C0RXEN) ...........................................
EMAC Control Module Transmit Interrupt Enable Register (C0TXEN) ..........................................
EMAC Control Module Miscellaneous Interrupt Enable Register (C0MISCEN) ................................
EMAC Control Module Receive Threshold Interrupt Status Register (C0RXTHRESHSTAT) ................
EMAC Control Module Receive Interrupt Status Register (C0RXSTAT) ........................................
EMAC Control Module Transmit Interrupt Status Register (C0TXSTAT) ........................................
EMAC Control Module Miscellaneous Interrupt Status Register (C0MISCSTAT) ..............................
EMAC Control Module Receive Interrupts Per Millisecond Register (C0RXIMAX) .............................
EMAC Control Module Transmit Interrupts Per Millisecond Register (C0TXIMAX) ............................
Management Data Input/Output (MDIO) Registers .................................................................
MDIO Revision ID Register (REVID) Field Descriptions ...........................................................
28-25. I2C DMA Control Register (I2CDMACR) Field Descriptions
1603
28-26. I2C Pin Function Register (I2CPFNC) Field Descriptions
1603
28-27.
28-28.
28-29.
28-30.
28-31.
28-32.
28-33.
28-34.
28-35.
28-36.
29-1.
29-2.
29-3.
29-4.
29-5.
29-6.
29-7.
29-8.
29-9.
29-10.
29-11.
29-12.
29-13.
29-14.
29-15.
29-16.
29-17.
29-18.
29-19.
29-20.
29-21.
29-22.
29-23.
29-24.
29-25.
SPNU499C – March 2018
Submit Documentation Feedback
List of Tables
Copyright © 2018, Texas Instruments Incorporated
1604
1604
1605
1605
1606
1606
1607
1607
1608
1608
1615
1616
1617
1617
1618
1620
1648
1649
1659
1660
1661
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1673
87
www.ti.com
29-26. MDIO Control Register (CONTROL) Field Descriptions ........................................................... 1674
29-27. PHY Acknowledge Status Register (ALIVE) Field Descriptions
..................................................
1675
29-28. PHY Link Status Register (LINK) Field Descriptions ............................................................... 1675
..............
MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) Field Descriptions .............
MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) Field Descriptions .....
MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) Field Descriptions ....
MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) Field Descriptions ..
29-29. MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) Field Descriptions
1676
29-30.
1677
29-31.
29-32.
29-33.
1678
1679
1680
29-34. MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) Field
Descriptions .............................................................................................................. 1681
29-35. MDIO User Access Register 0 (USERACCESS0) Field Descriptions............................................ 1682
29-36. MDIO User PHY Select Register 0 (USERPHYSEL0) Field Descriptions ....................................... 1683
29-37. MDIO User Access Register 1 (USERACCESS1) Field Descriptions............................................ 1684
29-38. MDIO User PHY Select Register 1 (USERPHYSEL1) Field Descriptions ....................................... 1685
29-39. Ethernet Media Access Controller (EMAC) Registers .............................................................. 1686
29-40. Transmit Revision ID Register (TXREVID) Field Descriptions .................................................... 1689
29-41. Transmit Control Register (TXCONTROL) Field Descriptions
....................................................
1689
29-42. Transmit Teardown Register (TXTEARDOWN) Field Descriptions............................................... 1690
29-43. Receive Revision ID Register (RXREVID) Field Descriptions ..................................................... 1690
29-44. Receive Control Register (RXCONTROL) Field Descriptions ..................................................... 1691
29-45. Receive Teardown Register (RXTEARDOWN) Field Descriptions ............................................... 1691
29-46. Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) Field Descriptions ....................... 1692
29-47. Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) Field Descriptions ..................... 1693
29-48. Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions ................................... 1694
29-49. Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Descriptions ............................. 1695
29-50. MAC Input Vector Register (MACINVECTOR) Field Descriptions ................................................ 1696
29-51. MAC End Of Interrupt Vector Register (MACEOIVECTOR) Field Descriptions
................................
1697
29-52. Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Field Descriptions ....................... 1698
29-53. Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Field Descriptions...................... 1699
29-54. Receive Interrupt Mask Set Register (RXINTMASKSET) Field Descriptions ................................... 1700
29-55. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Field Descriptions ............................. 1701
29-56. MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) Field Descriptions ......................... 1702
29-57. MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) Field Descriptions ....................... 1702
29-58. MAC Interrupt Mask Set Register (MACINTMASKSET) Field Descriptions ..................................... 1703
29-59. MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) Field Descriptions ............................... 1703
29-60. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field
Descriptions .............................................................................................................. 1704
29-61. Receive Unicast Enable Set Register (RXUNICASTSET) Field Descriptions................................... 1706
29-62. Receive Unicast Clear Register (RXUNICASTCLEAR) Field Descriptions ...................................... 1707
29-63. Receive Maximum Length Register (RXMAXLEN) Field Descriptions ........................................... 1707
29-64. Receive Buffer Offset Register (RXBUFFEROFFSET) Field Descriptions ...................................... 1708
29-65. Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) Field Descriptions ...... 1708
29-66. Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH) Field Descriptions ............. 1709
29-67. Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) Field Descriptions
....................
1709
29-68. MAC Control Register (MACCONTROL) Field Descriptions ...................................................... 1710
29-69. MAC Status Register (MACSTATUS) Field Descriptions .......................................................... 1712
29-70. Emulation Control Register (EMCONTROL) Field Descriptions .................................................. 1714
29-71. FIFO Control Register (FIFOCONTROL) Field Descriptions ...................................................... 1714
29-72. MAC Configuration Register (MACCONFIG) Field Descriptions .................................................. 1715
88
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29-73. Soft Reset Register (SOFTRESET) Field Descriptions ............................................................ 1715
29-74. MAC Source Address Low Bytes Register (MACSRCADDRLO) Field Descriptions ........................... 1716
29-75. MAC Source Address High Bytes Register (MACSRCADDRHI) Field Descriptions ........................... 1716
29-76. MAC Hash Address Register 1 (MACHASH1) Field Descriptions ................................................ 1717
29-77. MAC Hash Address Register 2 (MACHASH2) Field Descriptions ................................................ 1717
..........................................................
Transmit Pacing Algorithm Test Register (TPACETEST) Field Descriptions ...................................
Receive Pause Timer Register (RXPAUSE) Field Descriptions ..................................................
Transmit Pause Timer Register (TXPAUSE) Field Descriptions ..................................................
MAC Address Low Bytes Register (MACADDRLO) Field Descriptions ..........................................
MAC Address High Bytes Register (MACADDRHI) Field Descriptions ..........................................
MAC Index Register (MACINDEX) Field Descriptions .............................................................
Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP) Field Descriptions ..................
Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP) Field Descriptions ...................
Transmit Channel n Completion Pointer Register (TXnCP) Field Descriptions .................................
Receive Channel n Completion Pointer Register (RXnCP) Field Descriptions .................................
Encoding of Destination Bits in Trace Mode Packet Format ......................................................
Encoding of Status Bits in Trace Mode Packet Format ............................................................
Encoding of Write Size in Packet Format ............................................................................
Number of Clock Cycles per Packet ..................................................................................
Pins Used for Data Communication ..................................................................................
DMM Registers ..........................................................................................................
DMM Global Control Register (DMMGLBCTRL) Field Descriptions..............................................
DMM Interrupt Set Register (DMMINTSET) Field Descriptions ...................................................
DMM Interrupt Clear Register (DMMINTCLR) Field Descriptions ................................................
DMM Interrupt Level Register (DMMINTLVL) Field Descriptions .................................................
DMM Interrupt Flag Register (DMMINTFLG) Field Descriptions ..................................................
DMM Interrupt Offset 1 Register (DMMOFF1) Field Descriptions ................................................
DMM Interrupt Offset 2 Register (DMMOFF1) Field Descriptions ................................................
DMM Direct Data Mode Destination Register (DMMDDMDEST) Field Descriptions...........................
DMM Direct Data Mode Blocksize Register (DMMDDMBL) Field Descriptions.................................
DMM Direct Data Mode Pointer Register (DMMDDMPT) Field Descriptions ...................................
DMM Direct Data Mode Interrupt Pointer Register (DMMINTPT) Field Descriptions ..........................
DMM Destination x Region 1 (DMMDESTxREG1) Field Descriptions ...........................................
DMM Destination x Blocksize 1 (DMMDESTxBL1) Field Descriptions ...........................................
DMM Destination x Region 2 (DMMDESTxREG2) Field Descriptions ...........................................
DMM Destination x Blocksize 2 (DMMDESTxBL2) Field Descriptions ...........................................
DMM Pin Control 0 (DMMPC0) Field Descriptions .................................................................
DMM Pin Control 1 (DMMPC1) Field Descriptions .................................................................
DMM Pin Control 2 (DMMPC2) Field Descriptions .................................................................
DMM Pin Control 3 (DMMPC3) Field Descriptions .................................................................
DMM Pin Control 4 (DMMPC4) Field Descriptions .................................................................
DMM Pin Control 5 (DMMPC5) Field Descriptions .................................................................
DMM Pin Control 6 (DMMPC6) Field Descriptions .................................................................
DMM Pin Control 7 (DMMPC7) Field Descriptions .................................................................
DMM Pin Control 8 (DMMPC8) Field Descriptions .................................................................
Encoding of RAM Bits in Trace Mode Packet Format ..............................................................
Encoding of Status Bits in Trace Mode Packet Format ............................................................
Encoding of SIZE bits in Trace Mode Packet Format ..............................................................
29-78. Back Off Test Register (BOFFTEST) Field Descriptions
1718
29-79.
1718
29-80.
29-81.
29-82.
29-83.
29-84.
29-85.
29-86.
29-87.
29-88.
30-1.
30-2.
30-3.
30-4.
30-5.
30-6.
30-7.
30-8.
30-9.
30-10.
30-11.
30-12.
30-13.
30-14.
30-15.
30-16.
30-17.
30-18.
30-19.
30-20.
30-21.
30-22.
30-23.
30-24.
30-25.
30-26.
30-27.
30-28.
30-29.
30-30.
31-1.
31-2.
31-3.
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1719
1719
1720
1721
1721
1722
1722
1723
1723
1736
1736
1736
1737
1737
1740
1741
1743
1747
1752
1754
1758
1759
1760
1760
1761
1761
1762
1763
1764
1765
1766
1767
1769
1770
1771
1773
1774
1776
1777
1781
1782
1782
89
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31-4.
Encoding of REG in Trace Mode Packet Format ................................................................... 1782
31-5.
Number of Transfers/Packet ........................................................................................... 1782
31-6.
RTP Module Registers.................................................................................................. 1787
31-7.
RTP Global Control Register (RTPGLBCTRL) Field Descriptions ................................................ 1788
31-8.
FIFO Corresponding Addresses....................................................................................... 1790
31-9.
Pins Used for Data Communication
31-10.
31-11.
31-12.
31-13.
31-14.
31-15.
31-16.
31-17.
31-18.
31-19.
31-20.
31-21.
31-22.
31-23.
31-24.
32-1.
32-2.
32-3.
32-4.
32-5.
32-6.
32-7.
90
..................................................................................
RTP Trace Enable Register (RTPTRENA) Field Descriptions ....................................................
RTP Global Status Register (RTPGSR) [offset = 08h] Field Descriptions .......................................
RTP RAM 1 Trace Region [1:2] Register (RTPRAM1REG[1:2]) Field Descriptions ...........................
RTP RAM 2 Trace Region [1:2] Register (RTPRAM2REG[1:2]) Field Descriptions ...........................
RTP Peripheral Trace Region [1:2] Register (RTPPERREG[1:2]) Field Descriptions .........................
RTP Direct Data Mode Write Register (RTPDDMW) Field Descriptions ........................................
RTP Pin Control 0 Register (RTPPC0) Field Descriptions ........................................................
RTP Pin Control 1 Register (RTPPC1) Field Descriptions ........................................................
RTP Pin Control 2 Register (RTPPC2) Field Descriptions ........................................................
RTP Pin Control 3 Register (RTPPC3) Field Descriptions ........................................................
RTP Pin Control 4 Register (RTPPC4) Field Descriptions ........................................................
RTP Pin Control 5 Register (RTPPC5) Field Descriptions ........................................................
RTP Pin Control 6 Register (RTPPC6) Field Descriptions ........................................................
RTP Pin Control 7 Register (RTPPC7) Field Descriptions ........................................................
RTP Pin Control 8 Register (RTPPC8) Field Descriptions ........................................................
ESM Signals Set by eFuse Controller ................................................................................
eFuse Controller Registers.............................................................................................
EFC Boundary Register (EFCBOUND) Field Descriptions .......................................................
EFC Pins Register (EFCPINS) Field Descriptions ..................................................................
EFC Error Status Register (EFCERRSTAT) Field Descriptions ..................................................
EFC Self Test Cycles Register (EFCSTCY) Field Descriptions ..................................................
EFC Self Test Cycles Register (EFCSTSIG) Field Descriptions ..................................................
List of Tables
1790
1791
1792
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1806
1807
1809
1812
1812
1814
1815
1815
1816
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Preface
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Read This First
About This Manual
This Technical Reference Manual (TRM) details the integration, the environment, the functional
description, and the programming models for each peripheral and subsystem in the device.
The TRM should not be considered a substitute for the data manual, rather a companion guide that should
be used alongside the device-specific data manual to understand the details to program the device. The
primary purpose of the TRM is to abstract the programming details of the device from the data manual.
This allows the data manual to outline the high-level features of the device without unnecessary
information about register descriptions or programming models.
Notational Conventions
This document uses the following conventions.
• Hexadecimal numbers may be shown with the suffix h or the prefix 0x. For example, the following
number is 40 hexadecimal (decimal 64): 40h or 0x40.
• Registers in this document are shown in figures and described in tables.
– Each register figure shows a rectangle divided into fields that represent the fields of the register.
Each field is labeled with its bit name, its beginning and ending bit numbers above, and its
read/write properties with default reset value below. A legend explains the notation used for the
properties.
– Reserved bits in a register figure can have one of multiple meanings:
• Not implemented on the device
• Reserved for future device expansion
• Reserved for TI testing
• Reserved configurations of the device that are not supported
– Writing nondefault values to the Reserved bits could cause unexpected behavior and should be
avoided.
Glossary
TI Glossary — This glossary lists and explains terms, acronyms, and definitions.
Related Documentation From Texas Instruments
For product information, visit the Texas Instruments website at http://www.ti.com.
SPNA106— Initialization of Hercules™ ARM® Cortex®-R4F Microcontrollers Application Report.
Provides a brief overview and initialization procedure of the TMS570LS31x series and the RM4x
series of microcontrollers in the Hercules family.
SPNS162—
TMS570LS3137 16/32-Bit RISC Flash Microcontroller Data Manual.
SPNS164—
TMS570LS31x5/21x5 16/32-Bit RISC Flash Microcontroller Data Manual.
SPNS165—
TMS570LS31x4/21x4 16/32-Bit RISC Flash Microcontroller Data Manual.
SPNS230—
TMS570LS3137-EP 16-/32-Bit RISC Flash Microcontroller Data Manual.
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SPNU509— TMS570LS31x Hercules™ Development Kit (HDK) User's Guide. Describes the board level
operations of the TMS570LS31 Hercules Development Kit (HDK). The HDK is based on the Texas
Instruments TMS570LS3137 Microcontroller. The TMS570LS31 HDK is a table top card that allows
engineers and software developers to evaluate certain characteristics of the TMS570LS3137
microcontroller to determine if the microcontroller meets the designer's application requirements as
well as begin early application development. Evaluators can create software to execute on board or
expand the system in a variety of ways.
SPNU511— Safety Manual for TMS570LS31x/21x Hercules™ ARM® Safety Critical Microcontrollers
User's Guide. A safety manual for the Texas Instruments Hercules safety critical microcontroller
product family. The product family utilizes a common safety architecture that is implemented in
multiple application focused products.
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Online Community— TI's Engineer-to-Engineer (E2E) Community. Created to foster
collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore
ideas and help solve problems with fellow engineers.
TI Embedded Processors Wiki— Texas Instruments Embedded Processors Wiki. Established to help
developers get started with Embedded Processors from Texas Instruments and to foster innovation
and growth of general knowledge about the hardware and software surrounding these devices.
Trademarks
Hercules, E2E are trademarks of Texas Instruments.
CoreSight is a trademark of ARM Limited.
ARM, Cortex are registered trademarks of ARM Limited.
92
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Chapter 1
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Introduction
Topic
1.1
1.2
1.3
...........................................................................................................................
Page
Designed for Safety Applications ......................................................................... 94
Family Description ............................................................................................. 94
Endianism Considerations .................................................................................. 97
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Designed for Safety Applications
1.1
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Designed for Safety Applications
The TMS570LS31x/21x device architecture has been designed from the ground up to simplify
development of functionally safe systems. The basic architectural concept is known as a safe island
approach. Power, clock, reset, and basic processing function are protected to a high level of diagnostic
coverage in hardware. Some of the key features of the safe island region are:
• A dual core lockstep processing solution built around ARM® Cortex®-R4F CPU that detects failures at
the core boundary on a cycle by cycle basis. Special measures in processor layout, clock distribution,
power distribution, reset distribution, and temporal diversity are all implemented to mitigate common
cause failures of the logical CPU and its checker. For complete details on the ARM® Cortex®-R4F
CPU, refer to the ARM® Cortex®-R4F Technical Reference Manual.
• Hardware BIST controllers that provide an extremely high level of diagnostic coverage for the lockstep
CPUs and SRAMs in the system, while executing faster and consuming less memory than equivalent
software-based self-test solutions
• ECC on the SRAM and flash memories tightly coupled to the R4F. The ECC controllers are located
inside the CPU. This approach has two key advantages:
– The interconnect between CPU and the memory is also covered by the diagnostic
– The ECC logic itself is checked on a cycle by cycle basis
• Onboard voltage and reset monitoring logic
• Onboard oscillator and PLL failure detection logic including a backup RC oscillator that can be utilized
upon failure
The TMS570LS31x/21x device architecture also includes many features to simplify diagnostics of
remaining logic such as:
• Continuous parity diagnostics on all peripheral memories
• Analog and digital loopback to test for shorts on I/O
• HW self-test and diagnostics on the ADC module to check integrity of both analog inputs and the ADC
core conversion function
• A DMA driven hardware engine for the background calculation of CRC signatures during data transfers
• A centralized error reporting function including a status output pin to enable external monitoring of the
device status
1.2
Family Description
The TMS570LS31x/21x integrates the ARM® Cortex®-R4F Floating Point CPU that offers an efficient 1.6
DMIPS/MHz and has configurations that can run up to 180MHz providing up to 288 DMIPS. The device
supports the big-endian [BE32] format.
The TMS570LS31x/21x has up to 3MB integrated Flash and up to 256KB data RAM configurations with
single bit error correction and double bit error detection. The flash memory on this device is a nonvolatile,
electrically erasable and programmable memory implemented with a 64-bit-wide data bus interface. The
flash operates on a 3.3V supply input (same level as I/O supply) for all read, program and erase
operations. When in pipeline mode, the flash operates with a system clock frequency of up to 180MHz.
The SRAM supports single-cycle read/write accesses in byte, halfword, and word modes.
The TMS570LS31x/21x device features peripherals for real-time control-based applications, including two
Next Generation High End Timer (N2HET) timing coprocessors with up to 40 total IO terminals and a 12bit A to D converter supporting up to 24 inputs.
The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time
applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer
micromachine and an attached I/O port. The N2HET can be used for pulse width modulated outputs,
capture or compare inputs, or general-purpose I/O. It is especially well suited for applications requiring
multiple sensor information and drive actuators with complex and accurate time pulses. A High End Timer
Transfer Unit (HET-TU) can perform DMA type transactions to transfer N2HET data to or from main
memory. A Memory Protection Unit (MPU) is built into the HET-TU.
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The device has two 12-bit-resolution MibADCs with 24 total channels and 64 words of parity protected
buffer RAM each. The MibADC channels can be converted individually or can be grouped by software for
sequential conversion sequences. Sixteen channels are shared between the two MibADCs. There are
three separate groupings. Each sequence can be converted once when triggered or configured for
continuous conversion mode.
The device has multiple communication interfaces: three MibSPIs, up to two SPIs, one LIN, one SCI, three
DCANs, one I2C, one Ethernet, and one FlexRay™ controller. The SPI provides a convenient method of
serial interaction for high-speed communications between similar shift-register type devices. The LIN
supports the Local Interconnect standard 2.0 and can be used as a UART in full-duplex mode using the
standard Non-Return-to-Zero (NRZ) format. The DCAN supports the CAN 2.0B protocol standard and
uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with
robust communication rates of up to 1 megabit per second (Mbps). The DCAN is ideal for applications
operating in noisy and harsh environments (for example, automotive and industrial fields) that require
reliable serial communication or multiplexed wiring. The FlexRay uses a dual channel serial, fixed time
base multimaster communication protocol with communication rates of 10 megabits per second (Mbps)
per channel. A FlexRay Transfer Unit (FTU) enables autonomous transfers of FlexRay data to and from
main CPU memory. Transfers are protected by a dedicated, built-in Memory Protection Unit (MPU). The
Ethernet module supports MII and MDIO interfaces.
The I2C module is a multi-master communication module providing an interface between the
microcontroller and an I2C compatible device via the I2C serial bus. The I2C supports both 100 Kbps and
400 Kbps speeds.
The frequency-modulated phase-locked loop (FMPLL) clock module is used to multiply the external
frequency reference to a higher frequency for internal use. The FMPLL provides one of the seven possible
clock source inputs to the global clock module (GCM). The GCM module manages the mapping between
the available clock sources and the device clock domains.
The device also has an external clock prescaler (ECP) module that when enabled, outputs a continuous
external clock on the ECLK pin/ball. The ECLK frequency is a user-programmable ratio of the peripheral
interface clock (VCLK) frequency. This low frequency output can be monitored externally as an indicator of
the device operating frequency.
The Direct Memory Access Controller (DMA) has 16 channels, 32 control packets and parity protection on
its memory. A Memory Protection Unit (MPU) is built into the DMA to protect memory against erroneous
transfers.
The Error Signaling Module (ESM) monitors all device errors and determines whether an interrupt or
external Error pin/ball is triggered when a fault is detected. The nERROR can be monitored externally as
an indicator of a fault condition in the microcontroller.
The External Memory Interface (EMIF) provides a memory extension to asynchronous and synchronous
memories or other slave devices.
Several interfaces are implemented to enhance the debugging capabilities of application code. In addition
to the built in ARM® Cortex®-R4F CoreSight™ debug features. An External Trace Macrocell (ETM)
provides instruction and data trace of program execution. For instrumentation purposes, a RAM Trace Port
Module (RTP) is implemented to support high-speed tracing of RAM and peripheral accesses by the CPU
or any other master. A Data Modification Module (DMM) gives the ability to write external data into the
device memory. Both the RTP and DMM have no or only minimum impact on the program execution time
of the application code. A Parameter Overlay Module (POM) can re-route Flash accesses to internal
memory or to the EMIF, thus avoiding the re-programming steps necessary for parameter updates in
Flash.
With integrated safety features and a wide choice of communication and control peripherals, the
TMS570LS31x/21x is an ideal solution for high performance real time control applications with safety
critical requirements.
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Family Description
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TRACECTL
ETMDATA[31:0]
TRACECLKOUT
DMMSYNC
DMMDATA[15:0]
Color Legend for Power Domains
Core/RAM
always on
POM
HTU1
DMM
RAM
Core
#1
#2
ETM-R4
RTP
DMA
Dual Cortex-R4F
CPUs in Lockstep
TRACECLKIN
64K
64K
64K
DMMCLK
DMMnENA
256K
RAM
with
ECC
RTPnSYNC
RTPDATA[15:0]
RTPCLK
64K
3M
Flash
with
ECC
RTPnENA
Figure 1-1. Block Diagram
#3
#1
#2
#4
#3
#5
FTU
HTU2
EMAC
Switched Central Resource Switched Central Resource Switched Central Resource
Main Cross Bar: Arbitration and Prioritization Control
64 KB Flash
for EEPROM
Emulation
with ECC
CRC
Peripheral Central Resource Bridge
Switched Central Resource
SYS
IOMM
EMAC Slaves
MDCLK
MDIO
MII_RXD[3:0]
MII_RXER
MII_TXD[3:0]
MII_TXEN
MII_TXCLK
MII_RXCLK
MII_CRS
MII_RXDV
MII_COL
ESM
MDIO
PMM
EMIF_nWAIT
EMIF_CLK
EMIF_CKE
EMIF_nCS[4:2]
EMIF_nCS[0]
EMIF_ADDR[21:0]
EMIF_BA[1:0]
EMIF_DATA[15:0]
EMIF_nDQM[1:0]
EMIF_nOE
EMIF_nWE
EMIF_nRAS
EMIF_nCAS
MII
EMIF
DCAN1
DCAN2
VIM
DCAN3
MibSPI1
RTI
MibADC2
N2HET1
N2HET2
GIO
DCC1
SPI2
DCC2
MibSPI3
FlexRay
I2C
I2C_SCL
I2C_SDA
FRAY_RX2
FRAY_TX2
FRAY_TXEN2
FRAY_RX1
FRAY_TX1
FRAY_TXEN1
GIOA[7:0]
GIOB[7:0]
N2HET2_PIN_nDIS
N2HET2[18,16]
N2HET2[15:0]
N2HET1[31:0]
N2HET1_PIN_nDIS
ADREFLO
AD2EVT
VCCAD
VSSAD
ADREFHI
AD2IN[15:0]
ADREFLO
AD1EVT
AD1IN[7:0]
AD1IN[23:8]
VCCAD
VSSAD
ADREFHI
MibSPI5
96
nERROR
CAN1_RX
CAN1_TX
CAN2_RX
CAN2_TX
CAN3_RX
CAN3_TX
MIBSPI1_CLK
MIBSPI1_SIMO[1:0]
MIBSPI1_SOMI[1:0]
MIBSPI1_nCS[5:0]
MIBSPI1_nENA
SPI4
MibADC1
nPORRST
nRST
ECLK
Introduction
LIN
SCI
SPI2_CLK
SPI2_SIMO
SPI2_SOMI
SPI2_nCS[1:0]
SPI2_nENA
MIBSPI3_CLK
MIBSPI3_SIMO
MIBSPI3_SOMI
MIBSPI3_nCS[5:0]
MIBSPI3_nENA
SPI4_CLK
SPI4_SIMO
SPI4_SOMI
SPI4_nCS
SPI4_nENA
MIBSPI5_CLK
MIBSPI5_SIMO[3:0]
MIBSPI5_SOMI[3:0]
MIBSPI5_nCS[3:0]
MIBSPI5_nENA
LIN_RX
LIN_TX
SCI_RX
SCI_TX
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Endianism Considerations
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1.3
Endianism Considerations
1.3.1 TMS570: Big Endian (BE32)
The TMS570 family is based on the ARM® Cortex®-R4F core. ARM has designed this core to be used in
big-endian and little-endian systems. For the TI TMS570 family, the endianness has been configured to
BE32. Big-endian systems store the most-significant byte of a multi-byte data field in the lowest memory
address. Also, the address of the multi-byte data field is the lowest address. Following is an example of
the physical addresses of individual bytes.
Figure 1-2. Example: SPIDELAY – 0xFFF7F448
31
24
23
16
C2TDELAY[7:0]
T2CDELAY[7:0]
Byte 3 - 0xFFF7F448
Byte 2 - 0xFFF7F449
15
8
7
0
T2EDELAY[7:0]
C2EDELAY[7:0]
Byte 1 - 0xFFF7F44A
Byte 0 - 0xFFF7F44B
32-bit accesses to this register should use the lowest address, that is, 0xFFF7F448. Writing 0x11223344
to address 0xFFF7F448 shows the following when viewing the memory in 8-bit and 32-bit modes.
As such the headers provided as part of HALCoGen do take the endianness into account and provide
header structures that are agnostic to endianness. This is achieved by using C directives for the compiler
that make use of the compile options configured for the project by the user (__little_endian__ used in
Code Composer Studio codegen tools). This directive may need to be adapted for other compilers.
#ifdef __little_endian__
char C2EDELAY
:
char T2EDELAY
:
char T2CDELAY
:
char C2TDELAY
:
#else
char C2TDELAY
:
char T2CDELAY
:
char T2EDELAY
:
char C2EDELAY
:
8U;
8U;
8U;
8U;
/**lt;
/**lt;
/**lt;
/**lt;
0xF448:
0xF449:
0xF44A:
0xF44B:
CS to ENA
Transmit to ENA
Transmit to CS
CS to Transmit
*/
*/
*/
*/
8U;
8U;
8U;
8U;
/**lt;
/**lt;
/**lt;
/**lt;
0xF448:
0xF449:
0xF44A:
0xF44B:
CS to Transmit
Transmit to CS
Transmit to ENA
CS to ENA
*/
*/
*/
*/
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Chapter 2
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Architecture
This chapter consists of five sections. The first section describes specific aspects of the device
architecture. The second section describes the clocking structure of the microcontrollers. The third section
gives an overview of the device memory organization. The fourth section details exceptions on the device,
and the last section describes the system and peripheral control registers of the microcontroller.
Topic
2.1
2.2
2.3
2.4
2.5
98
...........................................................................................................................
Page
Introduction ....................................................................................................... 99
Memory Organization ........................................................................................ 103
Exceptions....................................................................................................... 115
Clocks ............................................................................................................. 118
System and Peripheral Control Registers ............................................................ 127
Architecture
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2.1
Introduction
The TMS570LS31x/21x family of microcontrollers is based on the Texas Instruments TMS570
Architecture. This chapter describes specific aspects of the architecture as applicable to the
TMS570LS31x/21x family of microcontrollers.
2.1.1 Architecture Block Diagram
The TMS570LS31x/21x microcontrollers are based on the TMS570 Platform architecture, which defines
the interconnect between the bus masters and the bus slaves.
Figure 2-1 shows a high-level architectural block diagram for the superset microcontroller.
Figure 2-1. Architectural Block Diagram
Flash
3MB
w/ ECC
RAM
256KB
w/ ECC
Dual Cortex-R4F
in LockStep
DMA
DMM
POM
HTU1
DAP
SCR1: AHB Bus Master Matrix
(AHB BMM)
HTU2
FTU
SCR2: VBUSP SCR
EMAC
SCR3: VBUSP SCR
VBUSM Switched Central Resource Controller
(VBUSM SCR)
PCR: Peripheral Central Resource Controller
SCR4: VBUSP SCR
Flash
EMIF
Slaves
EMAC
Slaves
64KB
VBUSP: Peripheral Interface Bus
CRC
EEPROM Emulation
Flash Bank
ADC1
ADC2
DCAN1
DCAN2
MibSPI1
SPI2
N2HET1
DCAN3
MibSPI3
N2HET2
LIN
SCI
SPI4
GIO
I2C
FlexRay
MibSPI5
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2.1.2 Definitions of Terms
Table 2-1 provides a definition of terms used in the architectural block diagram.
Table 2-1. Definition of Terms
Acronym/Term
Full Form
Description
ADCx
Analog-to-Digital Converter
The ADC uses the Successive Approximation Register architecture. It features a
selectable 10-bit or 12-bit resolution. The ADC module also includes a RAM to
hold the conversion results. A digital logic wrapper manages accesses to the
control and status registers. There are two ADC modules on this device.
CRC
Cyclic Redundancy Checker
The CRC module provides two channels to perform background signature
verification on any memory region. It also supports maximum-length Parallel
Signature Analysis (PDS) based on a 64-bit primitive polynomial. The CRC
module is a bus slave in this device.
DAP
Debug Access Port
The DAP allows a tool such as a debugger to read from or write to any region in
the device memory-map. The DAP is a bus master in this device.
DCANx
Controller Area Network
controller
The DCAN supports the CAN 2.0B protocol standard and uses a serial, multimaster communication protocol that efficiently supports distributed real-time
control with robust communication rates of up to 1 megabit per second (Mbps).
The DCAN is ideal for applications operating in noisy and harsh environments
(e.g., automotive and industrial fields) that require reliable serial communication
or multiplexed wiring.
DMA
Direct Memory Access
The DMA module is used for transferring 8-, 16-, 32- or 64-bit data across the
entire device memory-map. The DMA module is one of the bus masters on the
device. That is, it can initiate a read or a write transaction.
DMM
Data Modification Module
The DMM allows a tool to use the special DMM I/O interface to modify any data
value in any RAM on the device. This modification is done with minimal
interruption to the application execution, and can be used for calibration of
application algorithms. The DMM is also a bus master in this device.
eFuse
Electronically Programmable
Fuse controller
Electrically programmable fuses (eFuses) are used to configure the device after
Fuse controller deassertion of PORRST. The eFuse values are read and loaded
into internal registers as part of the power-on-reset sequence. The eFuse values
are protected with Single-Bit Error Correction Double-Bit Error Detection
(SECDED) codes. These fuses are programmed during the initial factory test of
the device. The eFuse controller is designed so that the state of the eFuses
cannot be changed once the device is packaged.
ECC
Error Correction Code
This is a code that is used by the Single-Bit Error Correction Double-Bit Error
Detection (SECDED) logic inside the two Cortex-R4F processors (CPUs). There
are 8 bits of ECC for every 64 bits of data accessed from the CPU tightlycoupled memories (flash and RAM).
EEPROM
Emulation Flash
Bank
Emulated Electrically
Erasable Programmable
Read-Only Memory
This is a flash bank that is dedicated for use as an emulated EEPROM. This
device supports 64KB of flash for emulated EEPROM.
EMAC
Ethernet Media Access
Controller
The EMAC has a dedicated DMA-type component that is used to transfer data to
/ from the EMAC descriptor memory from / to another memory in the device
memory-map. This DMA-type component of the EMAC is a bus master in this
device.
EMAC slaves
Ethernet Media Access
Controller slave ports
There are four EMAC slaves:
1.
2.
3.
4.
EMAC Control Module: this provides an interface between the EMAC and
MDIO modules and the bus masters. It also includes 8KB of RAM to hold
EMAC packet buffer descriptors.
EMAC: The EMAC module interfaces to the other devices on the Ethernet
Network using the Media Independent Interface (MII) or Reduced Media
Independent Interface (RMII).
Management Data Input / Output (MDIO): The MDIO module is used to
manage the physical layer (PHY) device connected to the EMAC module.
Communications Port Programming Interface (CPPI): This is the 8KB of
RAM used to hold the EMAC packet buffer descriptors.
EMIF slaves
External Memory Interface
slave ports
There are five EMIF slaves:- External SDRAM memory: EMIF chip select 0External asynchronous memories: EMIF chip selects 2, 3 and 4- EMIF module
control and status registers
FlexRay
FlexRay communication
controller
The FlexRay uses a dual channel serial, fixed time base multi-master communication protocol with communication rates of 10 megabits per second (Mbps)
per channel.
100 Architecture
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Table 2-1. Definition of Terms (continued)
Acronym/Term
Full Form
Description
FTU
FlexRay Transfer Unit
The FTU is a dedicated transfer unit for the FlexRay communication interface
controller. The FTU has a native interface to the FlexRay message RAM and is
used to transfer data to / from the FlexRay message RAM from / to another
region in the device memory-map. The FTU is a bus master in this device.
GIO
General-purpose Input/Output The GIO module allows up to 16 terminals to be used as general-purpose Input
or Output. Each of these are also capable of generating an interrupt to the CPU.
HTUx
High-end timer Transfer Unit
The HTU is a dedicated transfer unit for the New Enhanced High-End Timer
module. The HTU has a native interface to the N2HET RAM, and is used to
transfer data to / from the N2HET RAM from / to another region in the device
memory-map. There is one HTU per N2HET module, so that there are 2 HTU
modules on the device. The HTUx are bus masters in this device.
I2C
Inter-Integrated Circuit
controller
The I2C module is a multi-master communication module providing an interface
between the device and an I2C-compatible device via the I2C serial bus. The
I2C supports both 100 Kbps and 400 Kbps speeds.
LIN
Local Interconnect Network
controller
The LIN module supports the Local Interconnect standard revision 2.1 and can
be used as a UART in full-duplex mode using the standard Non-Return-to-Zero
(NRZ) format.
Lockstep
–
This is the mode of operation of the dual ARM Cortex-R4F CPUs. The outputs of
the two CPUs are compared on each CPU clock cycle. Any miscompare is
flagged as an error of the highest severity level.
MibSPIx
Multi-Buffered Serial
Peripheral Interface
The MibSPIx modules also support the standard SPI communication protocol.
The transfers are all grouped into transfer chunks called “transfer groups”. These
transfer groups are made up of one ore more buffers in the MibSPIx RAM. The
RAM is used to hold the control information and data to be transmitted, as well
as the status information and data that is received. There are three MibSPI
modules in this device.
N2HETx
New Enhanced High-End
Timer
The N2HET is an advanced intelligent timer that provides sophisticated timing
functions for real-time applications. The timer is software-controlled, using a
reduced instruction set, with a specialized timer micromachine and an attached
I/O port. The N2HET can be used for pulse width modulated outputs, capture or
compare inputs, or general-purpose I/O.
PCR
Peripheral Central Resource
controller
The PCR manages the accesses to the peripheral registers and peripheral
memories. It provides a global reset for all the peripherals. It also supports the
capability to selectively enable or disable the clock for each peripheral
individually. The PCR also manages the accesses to the system module
registers required to configure the device’s clocks, interrupts, and so on. The
system module registers also include status flags for indicating exception
conditions – resets, aborts, errors, interrupts.
POM
Parameter Overlay Module
The parameter overlay module redirects accesses to a programmable region in
flash memory (read-only) to a RAM memory, either on-chip or via the external
memory interface (EMIF). This allows a user to evaluate the impact of changing
values of constants stored in the flash memory without actually having to erase
and reprogram the flash. The POM is also a bus master in this device.
SCI
Serial Communication
Interface
The SCI module supports the standard UART in full-duplex mode using the
standard Non-Return-to-Zero (NRZ) format.
SCR1:
AHB BMM
AMBA High-Performance Bus The DMA, DMM, POM and DAP all act as masters on the AMBA HighMatrix Module
performance Bus (AHB). The BMM arbitrates between concurrent accesses by
these masters using a fixed priority scheme. The modules in descending order
of priority are POM —> DMA —> DMM —> DAP.
SCR2:
VBUSP SCR
VBUSP Switched Central
Resource Controller
The SCR2 arbitrates between concurrent accesses by the HTUx and FTU
modules. A round-robin priority scheme is used between the HTUx and FTU.
SCR3:
VBUSP SCR
VBUSP Switched Central
Resource Controller
The SCR3 arbitrates between concurrent accesses by the EMAC and another
module that is not available in this configuration of the device.
SCR4:
VBUSP SCR
VBUSP Switched Central
Resource Controller
The SCR4 is used to decode the accesses to the bus slaves for the EMAC and
EMIF modules. SCR4 is a bus slave in this device.
SPIx
Serial Peripheral Interface
The SPIx modules provide a clocked serial communication interface for reliable
communication between the device and other serial devices with the standard
SPI interface. There are two SPI modules on this device.
VBUSM SCR
VBUSM Switched Central
Resource Controller
This is the main device SCR. It arbitrates between the accesses from multiple
bus masters to the bus slaves using a round robin priority scheme.
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2.1.3 Bus Master / Slave Access Privileges
This device implements some restrictions on the bus slave access privileges in order to improve the
overall throughput of the interconnect shown in Figure 2-1.
Table 2-2. Bus Master / Slave Access Privileges
Bus Slaves Being Accessed
102
Masters
Master
ID
Access
Mode
CPU Read
0
CPU Write
1
POM
EEPROM Bank,
ECC Bits,
OTP Regions
Non-CPU
Accesses to CPU
Flash and RAM
CRC
Module
EMAC and EMIF
Slaves
PCR
Modules
User/Privilege
Allowed
Allowed
Allowed
Allowed
Allowed
User/Privilege
Not allowed
Allowed
Allowed
Allowed
Allowed
2
User
Allowed
Allowed
Allowed
Allowed
Allowed
DMA
3
User
Allowed
Allowed
Allowed
Allowed
Allowed
DMM
4
User
Allowed
Allowed
Allowed
Allowed
Allowed
DAP
5
Privilege
Allowed
Allowed
Allowed
Allowed
Allowed
HTU1
6
Privilege
Not allowed
Allowed
Allowed
Allowed
Allowed
Allowed
FTU
7
User
Not allowed
Allowed
Allowed
Allowed
HTU2
8
Privilege
Not allowed
Allowed
Allowed
Allowed
Allowed
EMAC
9
User
Not allowed
Allowed
Not allowed
Allowed
Not allowed
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2.2
Memory Organization
2.2.1 Memory-Map Overview
The Cortex-R4F CPU uses a 32-bit address bus, giving it access to a memory space of 4GB. This space
is divided into several regions, each addressed by different memory selects. Figure 2-2 shows the
memory-map of the microcontroller.
Figure 2-2. Memory-Map
0xFFFFFFFF
SYSTEM Modules
0xFFF80000
Peripherals - Frame 1
0xFF000000
0xFE000000
CRC
RESERVED
0xFCFFFFFF
0xFC000000
Peripherals - Frame 2
RESERVED
0xF07FFFFF
Flash Module Bus2 Interface
(Flash ECC, OTP and EEPROM accesses)
0xF0000000
RESERVED
0x87FFFFFF
0x80000000
0x6FFFFFFF
0x60000000
EMIF (128MB)
SDRAM
RESERVED
CS0
reserved
0x6C000000
CS4
0x68000000
CS3
0x64000000
CS2
EMIF (16MB * 3)
Async RAM
RESERVED
0x202FFFFF
0x20000000
Flash (3MB) (Mirrored Image)
RESERVED
0x0843FFFF
0x08400000
RAM - ECC
RESERVED
0x0803FFFF
0x08000000
0x002FFFFF
0x00000000
RAM (256KB)
RESERVED
Flash (3MB)
The main flash instruction memory is addressed starting at 0x00000000 by default. This is also the reset
vector location – the ARM Cortex-R4F processor core starts execution from the reset vector address of
0x00000000 whenever the core gets reset.
The CPU data RAM is addressed starting at 0x08000000 by default.
The device also supports the swapping of the CPU instruction memory (flash) and data memory (RAM).
This can be done by configuring the MEM SWAP field of the Bus Matrix Module Control Register 1
(BMMCR1).
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After swapping, the data RAM is accessed starting from 0x00000000 and the RAM ECC locations are
accessed starting from 0x00400000. The flash memory is now accessed starting from 0x08000000.
2.2.2 Memory-Map Table
The control and status registers for each module are mapped within the CPU’s 4GB memory space. Some
modules also have associated memories, which are also mapped within this space.
Table 2-3 shows the starting and ending addresses of each module’s register frame and any associated
memory. The table also shows the response generated by the module or the interconnect whenever an
access is made to an unimplemented location inside the register or memory frame.
Table 2-3. Module Registers / Memories Memory-Map
Frame Address
Name
Memory Select
Start
End
Frame
Size
Actual
Size
Response for Access to
Unimplemented
Location in Frame
CPU Tightly-Coupled Memories
TCM Flash
CS0
0x0000_0000
0x00FF_FFFF
16MB
3MB
TCM RAM + RAM
ECC
CSRAM0
0x0800_0000
0x0BFF_FFFF
64MB
256KB
Mirrored Flash
Flash mirror frame
0x2000_0000
0x20FF_FFFF
16MB
3MB
Abort
External Memory Accesses
EMIF Chip Select 2
(asynchronous)
EMIF select 2
0x6000_0000
0x63FF_FFFF
64MB
16MB
EMIF Chip Select 3
(asynchronous)
EMIF select 3
0x6400_0000
0x67FF_FFFF
64MB
16MB
EMIF Chip Select 4
(asynchronous)
EMIF select 4
0x6800_0000
0x6BFF_FFFF
64MB
16MB
EMIF Chip Select 0
(synchronous)
EMIF select 0
0x8000_0000
0x87FF_FFFF
128MB
128MB
Access to “Reserved”
space will generate Abort
Flash Bus2 Interface: OTP, ECC, EEPROM Bank
Customer OTP,TCM
Flash Bank 0
0xF000_0000
0xF000_1FFF
8KB
4KB
Customer OTP,TCM
Flash Bank 1
0xF000_2000
0xF000_3FFF
8KB
4KB
Customer OTP,
EEPROM Bank
0xF000_E000
0xF000_FFFF
8KB
4KB
Customer
OTP–ECC,TCM Flash
Bank 0
0xF004_0000
0xF004_03FF
1KB
512B
Customer
OTP–ECC,TCM Flash
Bank 1
0xF004_0400
0xF000_07FF
1KB
512B
Customer OTP–ECC,
EEPROM Bank
0xF004_1C00
0xF004_1FFF
1KB
512KB
TI OTP, TCM Flash
Bank 0
0xF008_0000
0xF008_1FFF
8KB
4KB
TI OTP, TCM Flash
Bank 1
0xF008_2000
0xF008_3FFF
8KB
4KB
TI OTP, EEPROM
Bank
0xF008_E000
0xF008_FFFF
8KB
4KB
TI OTP–ECC,TCM
Flash Bank 0
0xF00C_0000
0xF00C_03FF
1KB
512B
TI OTP–ECC,TCM
Flash Bank 1
0xF00C_0400
0xF00C_07FF
1KB
512B
TI OTP–ECC,
EEPROM Bank
0xF00C_1C00
0xF00C_1FFF
1KB
512KB
EEPROM Bank–ECC
0xF010_0000
0xF013_FFFF
256KB
8KB
Abort
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Table 2-3. Module Registers / Memories Memory-Map (continued)
Frame Address
Start
End
Frame
Size
EEPROM Bank
0xF020_0000
0xF03F_FFFF
2MB
64KB
Flash Data Space
ECC
0xF040_0000
0xF04F_FFFF
1MB
384KB
Name
Memory Select
Actual
Size
Response for Access to
Unimplemented
Location in Frame
Abort
EMAC and EMIF Slaves
CPPI Memory Slave
(Ethernet RAM)
0xFC52_0000
0xFC52_1FFF
8KB
8KB
Abort
CPGMAC Slave
(Ethernet Slave)
0xFCF7_8000
0xFCF7_87FF
2KB
2KB
No error
CPGMACSS Wrapper
(Ethernet Wrapper)
0xFCF7_8800
0xFCF7_88FF
256B
256B
No error
Ethernet MDIO
Interface
0xFCF7_8900
0xFCF7_89FF
256B
256B
No error
0xFCFF_E800
0xFCFF_E8FF
256B
256B
Abort
16MB
512B
Accesses above 0x200
generate abort.
EMIF Registers
Cyclic Redundancy Checker (CRC) Module Register Frame
CRC
CRC frame
0xFE00_0000
0xFEFF_FFFF
Peripheral Memories
MIBSPI5 RAM
PCS[5]
0xFF0A_0000
0xFF0B_FFFF
128KB
2KB
Abort for accesses above
2KB
MIBSPI3 RAM
PCS[6]
0xFF0C_0000
0xFF0D_FFFF
128KB
2KB
Abort for accesses above
2KB
MIBSPI1 RAM
PCS[7]
0xFF0E_0000
0xFF0F_FFFF
128KB
2KB
Abort for accesses above
2KB
2KB
Wrap around for
accesses to
unimplemented address
offsets lower than 0x7FF.
Abort generated for
accesses beyond offset
0x800.
2KB
Wrap around for
accesses to
unimplemented address
offsets lower than 0x7FF.
Abort generated for
accesses beyond offset
0x800.
2KB
Wrap around for
accesses to
unimplemented address
offsets lower than 0x7FF.
Abort generated for
accesses beyond offset
0x800.
8KB
Wrap around for
accesses to
unimplemented address
offsets lower than
0x1FFF. Abort generated
for accesses beyond
0x1FFF.
8KB
Wrap around for
accesses to
unimplemented address
offsets lower than
0x1FFF. Abort generated
for accesses beyond
0x1FFF.
DCAN3 RAM
DCAN2 RAM
DCAN1 RAM
MIBADC2 RAM
MIBADC1 RAM
PCS[13]
PCS[14]
PCS[15]
PCS[29]
PCS[31]
0xFF1A_0000
0xFF1C_0000
0xFF1E_0000
0xFF3A_0000
0xFF3E_0000
0xFF1B_FFFF
0xFF1D_FFFF
0xFF1F_FFFF
0xFF3B_FFFF
0xFF3F_FFFF
128KB
128KB
128KB
128KB
128KB
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Table 2-3. Module Registers / Memories Memory-Map (continued)
Frame Address
Name
NHET2 RAM
Memory Select
PCS[34]
Start
0xFF44_0000
End
0xFF45_FFFF
Frame
Size
128KB
Actual
Size
Response for Access to
Unimplemented
Location in Frame
16KB
Wrap around for
accesses to
unimplemented address
offsets lower than
0x3FFF. Abort generated
for accesses beyond
0x3FFF.
NHET1 RAM
PCS[35]
0xFF46_0000
0xFF47_FFFF
128KB
16KB
Wrap around for
accesses to
unimplemented address
offsets lower than
0x3FFF. Abort generated
for accesses beyond
0x3FFF.
HET TU2 RAM
PCS[38]
0xFF4C_0000
0xFF4D_FFFF
128KB
1KB
Abort
HET TU1 RAM
PCS[39]
0xFF4E_0000
0xFF4F_FFFF
128KB
1KB
Abort
FlexRay TU RAM
PCS[40]
0xFF50_0000
0xFF51_FFFF
128KB
1KB
Abort
Debug Components
CoreSight Debug
ROM
CSCS0
0xFFA0_0000
0xFFA0_0FFF
4KB
4KB
Reads return zeros,
writes have no effect
Cortex-R4F Debug
CSCS1
0xFFA0_1000
0xFFA0_1FFF
4KB
4KB
Reads return zeros,
writes have no effect
ETM-R4
CSCS2
0xFFA0_2000
0xFFA0_2FFF
4KB
4KB
Reads return zeros,
writes have no effect
CoreSight TPIU
CSCS3
0xFFA0_3000
0xFFA0_3FFF
4KB
4KB
Reads return zeros,
writes have no effect
POM
CSCS4
0xFFA0_4000
0xFFA0_4FFF
4KB
4KB
Abort
Peripheral Control Registers
FTU
PS[23]
0xFFF7_A000
0xFFF7_A1FF
512B
512B
Reads return zeros,
writes have no effect
HTU1
PS[22]
0xFFF7_A400
0xFFF7_A4FF
256B
256B
Reads return zeros,
writes have no effect
HTU2
PS[22]
0xFFF7_A500
0xFFF7_A5FF
256B
256B
Reads return zeros,
writes have no effect
NHET1
PS[17]
0xFFF7_B800
0xFFF7_B8FF
256B
256B
Reads return zeros,
writes have no effect
NHET2
PS[17]
0xFFF7_B900
0xFFF7_B9FF
256B
256B
Reads return zeros,
writes have no effect
GIO
PS[16]
0xFFF7_BC00
0xFFF7_BCFF
256B
256B
Reads return zeros,
writes have no effect
MIBADC1
PS[15]
0xFFF7_C000
0xFFF7_C1FF
512B
512B
Reads return zeros,
writes have no effect
MIBADC2
PS[15]
0xFFF7_C200
0xFFF7_C3FF
512B
512B
Reads return zeros,
writes have no effect
FlexRay
PS[12]+PS[13]
0xFFF7_C800
0xFFF7_CFFF
2KB
2KB
Reads return zeros,
writes have no effect
I2C
PS[10]
0xFFF7_D400
0xFFF7_D4FF
256B
256B
Reads return zeros,
writes have no effect
DCAN1
PS[8]
0xFFF7_DC00
0xFFF7_DDFF
512B
512B
Reads return zeros,
writes have no effect
DCAN2
PS[8]
0xFFF7_DE00
0xFFF7_DFFF
512B
512B
Reads return zeros,
writes have no effect
DCAN3
PS[7]
0xFFF7_E000
0xFFF7_E1FF
512B
512B
Reads return zeros,
writes have no effect
106 Architecture
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Table 2-3. Module Registers / Memories Memory-Map (continued)
Frame Address
Actual
Size
Response for Access to
Unimplemented
Location in Frame
Start
End
Frame
Size
PS[6]
0xFFF7_E400
0xFFF7_E4FF
256B
256B
Reads return zeros,
writes have no effect
SCI
PS[6]
0xFFF7_E500
0xFFF7_E5FF
256B
256B
Reads return zeros,
writes have no effect
MibSPI1
PS[2]
0xFFF7_F400
0xFFF7_F5FF
512B
512B
Reads return zeros,
writes have no effect
SPI2
PS[2]
0xFFF7_F600
0xFFF7_F7FF
512B
512B
Reads return zeros,
writes have no effect
MibSPI3
PS[1]
0xFFF7_F800
0xFFF7_F9FF
512B
512B
Reads return zeros,
writes have no effect
SPI4
PS[1]
0xFFF7_FA00
0xFFF7_FBFF
512B
512B
Reads return zeros,
writes have no effect
MibSPI5
PS[0]
0xFFF7_FC00
0xFFF7_FDFF
512B
512B
Reads return zeros,
writes have no effect
DMA RAM
PPCS0
Name
Memory Select
LIN
System Modules Control Registers and Memories
0xFFF8_0000
0xFFF8_0FFF
4KB
4KB
Abort
VIM RAM
PPCS2
0xFFF8_2000
0xFFF8_2FFF
4KB
1KB
Wrap around for
accesses to
unimplemented address
offsets lower than 0x3FF.
Abort generated for
accesses beyond 0x3FF.
RTP RAM
PPCS3
0xFFF8_3000
0xFFF8_3FFF
4KB
4KB
Abort
Flash Wrapper
PPCS7
0xFFF8_7000
0xFFF8_7FFF
4KB
4KB
Abort
eFuse Farm
Controller
PPCS12
0xFFF8_C000
0xFFF8_CFFF
4KB
4KB
Abort
Power Management
Module (PMM)
PPSE0
0xFFFF_0000
0xFFFF_01FF
512B
512B
Abort
Test Controller
(FMTM)
PPSE1
0xFFFF_0400
0xFFFF_07FF
1KB
1KB
Reads return zeros,
writes have no effect
PCR registers
PPS0
0xFFFF_E000
0xFFFF_E0FF
256B
256B
Reads return zeros,
writes have no effect
System Module Frame 2
PPS0
0xFFFF_E100
0xFFFF_E1FF
256B
256B
Reads return zeros,
writes have no effect
PBIST
PPS1
0xFFFF_E400
0xFFFF_E5FF
512B
512B
Reads return zeros,
writes have no effect
STC
PPS1
0xFFFF_E600
0xFFFF_E6FF
256B
256B
Reads return zeros,
writes have no effect
IOMM Multiplexing
Control Module
PPS2
0xFFFF_EA00
0xFFFF_EBFF
512B
512B
Generates address error
interrupt, if enabled
DCC1
PPS3
0xFFFF_EC00
0xFFFF_ECFF
256B
256B
Reads return zeros,
writes have no effect
DMA
PPS4
0xFFFF_F000
0xFFFF_F3FF
1KB
1KB
Reads return zeros,
writes have no effect
DCC2
PPS5
0xFFFF_F400
0xFFFF_F4FF
256B
256B
Reads return zeros,
writes have no effect
ESM
PPS5
0xFFFF_F500
0xFFFF_F5FF
256B
256B
Reads return zeros,
writes have no effect
CCMR4
PPS5
0xFFFF_F600
0xFFFF_F6FF
256B
256B
Reads return zeros,
writes have no effect
DMM
PPS5
0xFFFF_F700
0xFFFF_F7FF
256B
256B
Reads return zeros,
writes have no effect
RAM ECC even
PPS6
0xFFFF_F800
0xFFFF_F8FF
256B
256B
Reads return zeros,
writes have no effect
Architecture 107
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Table 2-3. Module Registers / Memories Memory-Map (continued)
Frame Address
Actual
Size
Response for Access to
Unimplemented
Location in Frame
Start
End
Frame
Size
PPS6
0xFFFF_F900
0xFFFF_F9FF
256B
256B
Reads return zeros,
writes have no effect
RTP
PPS6
0xFFFF_FA00
0xFFFF_FAFF
256B
256B
Reads return zeros,
writes have no effect
RTI + DWWD
PPS7
0xFFFF_FC00
0xFFFF_FCFF
256B
256B
Reads return zeros,
writes have no effect
VIM Parity
PPS7
0xFFFF_FD00
0xFFFF_FDFF
256B
256B
Reads return zeros,
writes have no effect
VIM
PPS7
0xFFFF_FE00
0xFFFF_FEFF
256B
256B
Reads return zeros,
writes have no effect
System Module Frame 1
PPS7
0xFFFF_FF00
0xFFFF_FFFF
256B
256B
Reads return zeros,
writes have no effect
Name
Memory Select
RAM ECC odd
2.2.3 Flash Memory
The TMS570LS31x/21x microcontrollers support up to 3MB of flash for use as program memory. This is
divided into two separate flash banks, each 1.5MB. The microcontrollers also support a separate 64KB
flash bank for use as emulated EEPROM.
2.2.3.1
Flash Bank Sectoring Configuration
Each bank is divided into multiple sectors. A flash sector is the smallest region in the flash bank that must
be erased. The sectoring configuration of each flash bank is shown in Table 2-4.
1. The Flash banks are 144-bit wide bank with ECC support.
2. The flash bank7 can be programmed while executing code from flash bank0 or bank1.
3. Code execution is not allowed from flash bank7.
Refer to the device datasheet for electrical and timing specifications related to the flash module.
Table 2-4. Flash Memory Banks and Sectors
Sector NO.
SECTOR SIZE
Low Address
High address
Bank 0: 1.5M Bytes
0
32K Bytes
0x0000_0000
0x0000_7FFF
1
32K Bytes
0x0000_8000
0x0000_FFFF
2
32K Bytes
0x0001_0000
0x0001_7FFF
3
32K Bytes
0x0001_8000
0x0001_FFFF
4
128K Bytes
0x0002_0000
0x0003_FFFF
5
128K Bytes
0x0004_0000
0x0005_FFFF
6
128K Bytes
0x0006_0000
0x0007_FFFF
7
128K Bytes
0x0008_0000
0x0009_FFFF
8
128K Bytes
0x000A_0000
0x000B_FFFF
9
128K Bytes
0x000C_0000
0x000D_FFFF
10
128K Bytes
0x000E_0000
0x000F_FFFF
11
128K Bytes
0x0010_0000
0x0011_FFFF
12
128K Bytes
0x0012_0000
0x0013_FFFF
13
128K Bytes
0x0014_0000
0x0015_FFFF
14
128K Bytes
0x0016_0000
0x0017_FFFF
Bank 1: 1.5M Bytes
0
128K Bytes
0x0018_0000
108 Architecture
0x0019_FFFF
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Table 2-4. Flash Memory Banks and Sectors (continued)
Sector NO.
SECTOR SIZE
Low Address
High address
1
128K Bytes
0x001A_0000
0x001B_FFFF
2
128K Bytes
0x001C_0000
0x001D_FFFF
3
128K Bytes
0x001E_0000
0x001F_FFFF
4
128K Bytes
0x0020_0000
0x0021_FFFF
5
128K Bytes
0x0022_0000
0x0023_FFFF
6
128K Bytes
0x0024_0000
0x0025_FFFF
7
128K Bytes
0x0026_0000
0x0027_FFFF
8
128K Bytes
0x0028_0000
0x0029_FFFF
9
128K Bytes
0x002A_0000
0x002B_FFFF
10
128K Bytes
0x002C_0000
0x002D_FFFF
11
128K Bytes
0x002E_0000
0x002F_FFFF
0
16K Bytes
0xF020_0000
1
16K Bytes
0xF020_4000
0xF020_7FFF
2
16K Bytes
0xF020_8000
0xF020_BFFF
3
16K Bytes
0xF020_C000
0xF020_FFFF
Bank 7: 64K Bytes, dedicated for EEPROM emulation
2.2.3.2
0xF020_3FFF
ECC Protection for Flash Accesses
The TMS570LS31x/21x microcontrollers protect all accesses to the on-chip flash memory by dedicated
Single-Bit Error Correction Double-Bit Error Detection (SECDED) logic.
The accesses to the program memory – flash bank 0 and flash bank 1, are protected by SECDED logic
implemented inside the ARM Cortex-R4F CPU. Accesses to the EEPROM emulation flash bank (bank 7)
are protected by dedicated SECDED logic inside the digital interface to the flash banks.
Both the SECDED logic implementations use Error Correction Codes (ECC) for correcting single-bit errors
and for detecting multiple-bit errors in the values read from the flash arrays. There is an 8-bit ECC for
every 64 bits of data. The ECC for the flash memory contents needs to be calculated by an external tool
such as nowECC. The ECC can then be programmed into the flash array along with the actual application
code.
The ECC for the flash array is stored in the flash itself, and is mapped to a region starting at 0xF040 0000
for the main flash banks 0 and 1, and to a region starting at 0xF010 0000 for the EEPROM emulation
flash bank 7.
NOTE: ECC Protection Not Enabled By Default
The SECDED logic inside the CPU is not enabled by default and must be enabled by the
application.
Code Example for Enabling ECC Protection for Main Flash Accesses:
The following code example can be used to enable the ECC protection for accesses to the main flash
array.
MRC p15, #0, r1, c1, c0, #1
ORR r1, r1, #0x02000000
DMB
MCR p15, #0, r1, c1, c0, #1
;Enable ECC checking for ATCM
The ECC protection for accesses to the EEPROM emulation flash bank can be enabled by writing 0xA to
the EDACEN field of the flash module’s Error Correction Control Register 1 (FEDACCTRL1). See
Chapter 5 for more details.
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When the CPU detects an ECC single-, or double-bit error on a read from the flash memory, it signals this
on a dedicated “Event” bus. This event bus signaling is also not enabled by default and must be enabled
by the application. The following code example can be used to enable the CPU event signaling.
MRC
ORR
MCR
MRC
p15,#0,r1,c9,c12,#0
r1, r1, #0x00000010
p15,#0,r1,c9,c12,#0
p15,#0,r1,c9,c12,#0
;Enabling Event monitor states
;Set 4th bit ('X') of PMNC register
The digital logic that interfaces the ARM Cortex-R4F CPU to the flash banks captures the ECC error
events signaled by the CPU, and in turn generates error signals that are input to the central Error
Signaling Module (ESM).
2.2.4 On-Chip SRAM
Several SRAM modules are implemented on the device to support the functionality of the modules
included.
Reads from the CPU data RAM are protected by ECC calculated inside the CPU. Reads from all other
memories are protected by configurable odd or even parity that is evaluated in parallel with the actual
read.
The TMS570LS31x/21x microcontrollers are targeted towards safety-critical applications, and it is critical
for any failures in the on-chip SRAM modules to be identified before these modules are used for safetycritical functions. These microcontrollers support a Programmable Built-In Self-Test (PBIST) mechanism
that is used to test each on-chip SRAM module for faults. The PBIST is usually run on device start-up as it
is a destructive test and all contents of the tested SRAM module are overwritten during the test.
The microcontrollers also support a hardware-based auto-initialization of on-chip SRAM modules. This
process also takes into account the read protection scheme implemented for each SRAM module – ECC
or parity.
TI recommends that the PBIST routines be executed on the SRAM modules prior to the auto-initialization.
The following section describe these two processes.
2.2.4.1
PBIST RAM Grouping and Algorithm Mapping For On-Chip SRAM Modules
Table 2-5 shows the groupings of the various on-chip memories for PBIST. It also lists the memory types
and their assigned RAM Group Select (RGS) and Return Data Select (RDS). See Chapter 7 for more
details on the usage of the RGS and RDS information.
Table 2-5. PBIST Memory Grouping
Memory
RAM Group #
Memory Type
RGS
RDS
PBIST_ROM
1
ROM
1
0
STC_ROM
2
ROM
2
0
DCAN1
3
Dual-port
3
0 .. 5
DCAN2
4
Dual-port
4
0 .. 5
DCAN3
5
Dual-port
5
0 .. 5
ESRAM1
6
Single-port
6
0/1 .. 4
MIBSPI1
7
Dual-port
7
0 .. 3
MIBSPI3
8
Dual-port
7
4 .. 7
MIBSPI5
9
Dual-port
7
8 .. 11
0 .. 1
VIM
10
Dual-port
8
MIBADC1
11
Dual-port
9
0
DMA
12
Dual-port
10
0 .. 5
N2HET1
13
Dual-port
11
0 .. 11
HET TU1
14
Dual-port
12
0 .. 5
RTP
15
Dual-port
13
0 .. 8
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Table 2-5. PBIST Memory Grouping (continued)
Memory
FLEXRAY
RAM Group #
Memory Type
RGS
RDS
16
Dual-port
14
0 .. 13
17
Single-port
MIBADC2
18
Dual-port
15
0
N2HET2
19
Dual-port
16
0 .. 11
HET TU2
20
Dual-port
17
0 .. 5
ESRAM5
21
Single-port
18
0/1 .. 4
ESRAM6
22
Single-port
19
0/1 .. 4
23
Dual-port
20
0 .. 6
25
0/1 .. 4
ETHERNET
ESRAM8
24
Dual-port
25
Single-port
28
Single-port
Table 2-6 maps the different algorithms supported in application mode for the RAM groups. The table also
lists the background pattern options available for each algorithm.
Table 2-6. PBIST Algorithm Mapping
No.
ALGO
Register
Value
Algorithm
Memories
Tested
1
0x00000001
triple_read_slow_read
2
0x00000002
triple_read_fast_read
3
0x00000004
march13n
Available
Background
Patterns
Valid RAM Groups
Valid RINFO
Register Value
ROM
1,2
0x00000003
ROM
1,2
0x00000003
Dual-port
0x00000000,
0x96699669,
0x0F0F0F0F,
0xAA55AA55,
0xC3C3C3C3
3,4,5,7,8,9,10,11,12,13,14,
15,16,18,19,20,23,24
0x00CEFFDC
6,17,21,22,25,28
0x09310020
4
0x00000008
march13n
Single-port
0x00000000,
0x96699669,
0x0F0F0F0F,
0xAA55AA55,
0xC3C3C3C3
5
0x00000010
down1A_red
Dual-port
0xFFFFFFFF,
0xAAAAAAAA
3,4,5,7,8,9,10,11,12,13,14,
15,16,18,19,20,23,24
0x00CEFFDC
6
0x00000020
down1A_red
Single-port
0xFFFFFFFF,
0xAAAAAAAA
6,17,21,22,25,28
0x09310020
7
0x00000040
mapcolumn
Dual-port
0xFFFFFFFF,
0x00000000
3,4,5,7,8,9,10,11,12,13,14,
15,16,18,19,20,23,24
0x00CEFFDC
8
0x00000080
mapcolumn
Single-port
0xFFFFFFFF,
0x00000000
6,17,21,22,25,28
0x09310020
9
0x00000100
precharge
Dual-port
0xFFFFFFFF,
0x00000000
3,4,5,7,8,9,10,11,12,13,14,
15,16,18,19,20,23,24
0x00CEFFDC
10
0x00000200
precharge
Single-port
0xFFFFFFFF,
0x00000000
6,17,21,22,25,28
0x09310020
11
0x00000400
dtxn2
Dual-port
0xFFFFFFFF,
0x00000000
3,4,5,7,8,9,10,11,12,13,14,
15,16,18,19,20,23,24
0x00CEFFDC
12
0x00000800
dtxn2
Single-port
0xFFFFFFFF,
0x00000000
6,17,21,22,25,28
0x09310020
13
0x00001000
pmos_open
Dual-port
0xFFFFFFFF,
0x00000000
3,4,5,7,8,9,11,14,15,16,18,
20,24
0x028AE5DC
14
0x00002000
pmos_open
Single-port
0xFFFFFFFF,
0x00000000
6,17,21,22,25,28
0x09310020
15
0x00004000
pmos_open_slice1
Dual-port
0xFFFFFFFF,
0x00000000
10,12,13,19,23
0x00441A00
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Table 2-6. PBIST Algorithm Mapping (continued)
No.
ALGO
Register
Value
Algorithm
Memories
Tested
Available
Background
Patterns
Valid RAM Groups
Valid RINFO
Register Value
16
0x00008000
pmos_open_slice2
Dual-port
0xFFFFFFFF,
0x00000000
10,12,13,19,23
0x00441A00
17
0x00010000
flip10
Dual-port
0xFFFFFFFF
3,4,5,7,8,9,10,11,12,13,14,
15,16,18,19,20,23,24
0x00CEFFDC
18
0x00020000
flip10
Single-port
0xFFFFFFFF
6,17,21,22,25,28
0x09310020
3,4,5,7,8,9,10,11,12,13,14,
15,16,18,19,20,23,24
0x00CEFFDC
19
0x00040000
iddq
Dual-port
0x00000000
20
0x00080000
iddq
Single-port
0x00000000
6,17,21,22,25,28
0x09310020
3,4,5,7,8,9,10,11,12,13,14,
15,16,18,19,20,23,24
0x00CEFFDC
21
0x00100000
retention
Dual-port
0x00000000
22
0x00200000
retention
Single-port
0x00000000
6,17,21,22,25,28
0x09310020
0x00CEFFDC
23
0x00400000
iddq
Dual-port
0xFFFFFFFF
3,4,5,7,8,9,10,11,12,13,14,
15,16,18,19,20,23,24
24
0x00800000
iddq
Single-port
0xFFFFFFFF
6,17,21,22,25,28
0x09310020
25
0x01000000
retention
Dual-port
0xFFFFFFFF
3,4,5,7,8,9,10,11,12,13,14,
15,16,18,19,20,23,24
0x00CEFFDC
26
0x02000000
retention
Single-port
0xFFFFFFFF
6,17,21,22,25,28
0x09310020
27
0x04000000
iddqrowstripe
Dual-port
0x00000000
3,4,5,7,8,9,10,11,12,13,14,
15,16,18,19,20,23,24
0x00CEFFDC
28
0x08000000
iddqrowstripe
Single-port
0x00000000
6,17,21,22,25,28
0x09310020
3,4,5,7,8,9,10,11,12,13,14,
15,16,18,19,20,23,24
0x00CEFFDC
29
0x10000000
iddqrowstripe
Dual-port
0xFFFFFFFF
30
0x20000000
iddqrowstripe
Single-port
0xFFFFFFFF
6,17,21,22,25,28
0x09310020
0x0007FFFF
0x03F80000
31
0x40000000
powerup_invpowerup
Dual-port
0xAAAAAAAA
33,34,35,36,37,38,39,40,
41,42,43,44,45,46,47,48,
49,50,51
32
0x80000000
powerup_invpowerup
Single-port
0xAAAAAAAA
52,53,54,55,56,57,58
NOTE: Recommended Memory Test Algorithm
March13 is the most recommended algorithm for the memory self-test.
For HCLK = 180 MHz, VCLK = 90 MHz, PBIST ROM_CLK = 90 MHz, the March13 algorithm takes 14.02
ms to run on all on-chip SRAMs.
112
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2.2.4.2
Auto-Initialization of On-Chip SRAM Modules
The device system provides the capability to perform a hardware initialization on most memories on the
system bus and on the peripheral bus. The memory used for the FlexRay message objects is not directly
CPU addressable, hence there is no memory auto-initialization support for this memory.
The intent of having the hardware initialization is to program the memory arrays with error detection
capability to a known state based on their error detection scheme – odd/even parity or ECC. For example,
the contents of the CPU data RAM after power-on reset is unknown. A hardware auto-initialization can be
started to that there is no ECC error.
NOTE: Effect of ECC or Parity on Memory Auto-Initialization
The ECC or parity should be enabled on the RAMs before hardware auto-initialization starts
if parity or ECC is being used.
Auto-Initialization Sequence:
1. Enable the global hardware memory initialization key by programming 0xA into MINITGCR[3:0], the
Memory Initialization Key field (MINITGENA) of the Memory Hardware Initialization Global Control
Register (MINITGCR) register.
2. Select the module on which the memory hardware initialization has to be performed by programming
the appropriate value into the MSINENA(31–0) bits in the MSINENA register. See Table 2-7.
3. If the global auto-initialization scheme is enabled, the corresponding module will initialize its memories
based on its memory error checking scheme (even parity or odd parity or ECC).
4. When the memory initialization is complete, the module will signal “memory initialization done”, which
sets the corresponding bit in the system module MIDONE field of the MINISTAT register to indicate the
completion of its memory initialization.
5. When the memory hardware initialization completes for all modules, (indicated by each module’s
MIDONE bit being set), the memory hardware initialization done bit (MINIDONE) is set in the
MSTCGSTAT register.
Figure 2-3. Hardware Memory Initialization Protocol
VCLK
Write to enable
MINTIGENA key
Write to enable
MSINENAn
(where n = 31:0)
When each enabled module completes
its hardware initialization, the
corresponding MIIDONE bit is set.
Poll MIDONEn field of
MINISTAT register
(where n = 31:0)
After all enabled modules’ hardware initialization
completes, the MINIDONE bit is set, indicating
all hardware memory initialization is done.
Poll MINIDONE bit,
MSTCGSTAT[8]
Memory
module
hardware
initialization
SYS_MMISTARTn
(where n = 31:0)
(from System module
to memory modules)
DEV_MMIDONEn
(where n = 31:0)
(from memory modules
to System module)
Black indicates System register activity.
Gray indicates inter-module activity, not accessible via System register.
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Table 2-7. Memory Initialization Select Mapping
Memory
(1)
(2)
(3)
114
Address Range
(1) (2)
MSINENA Register Bit #
Start
End
RAM
0x08000000
0x08013FFF
0
RAM (always ON domain, PD#1)
0x08000000
0x0800FFFF
0
RAM (RAM_PD#1)
0x08010000
0x0801FFFF
0
RAM (RAM_PD#2)
0x08020000
0x0802FFFF
0
RAM (RAM_PD#3)
0x08030000
0x0803FFFF
0
MIBSPI5 RAM
0xFF0A0000
0xFF0BFFFF
12 (3)
MIBSPI3 RAM
0xFF0C0000
0xFF0DFFFF
11 (3)
MIBSPI1 RAM
0xFF0E0000
0xFF0FFFFF
7 (3)
DCAN3 RAM
0xFF1A0000
0xFF1BFFFF
10
DCAN2 RAM
0xFF1C0000
0xFF1DFFFF
6
DCAN1 RAM
0xFF1E0000
0xFF1FFFFF
5
MIBADC2 RAM
0xFF3A0000
0xFF3BFFFF
14
MIBADC1 RAM
0xFF3E0000
0xFF3FFFFF
8
NHET2 RAM
0xFF440000
0xFF45FFFF
15
NHET1 RAM
0xFF460000
0xFF47FFFF
3
HET TU2 RAM
0xFF4C0000
0xFF4DFFFF
16
HET TU1 RAM
0xFF4E0000
0xFF4FFFFF
4
DMA RAM
0xFFF80000
0xFFF80FFF
1
VIM RAM
0xFFF82000
0xFFF82FFF
2
Ethernet RAM (CPPI Memory Slave)
0xFC520000
0xFC521FFF
N/A
FlexRay TU RAM
0xFF500000
0xFF51FFFF
13
If ECC protection is enabled for the CPU data RAM, then the auto-initialization process also initializes the corresponding ECC
space.
If parity protection is enabled for the peripheral SRAM modules, then the parity bits will also be initialized along with the SRAM
modules.
The MibSPIx modules perform an initialization of the transmit and receive RAMs as soon as the multi-buffered mode is enabled.
This is independent of whether the application has already initialized these RAMs using the auto-initialization method or not. The
MibSPIx modules need to be released from reset by writing 1 to their SPIGCR0 registers before starting auto-initialization on
their respective RAMs.
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2.3
Exceptions
An “Exception” is an event that makes the processor temporarily halt the normal flow of program
execution, for example, to service an interrupt from a peripheral. Before attempting to handle an
exception, the processor preserves the critical parts of the current processor state so that the original
program can resume when the handler routine has finished.
The following sections describe three exceptions – Reset, Abort and the System Software Interrupts.
For complete details on all exceptions, refer to the ARM® Cortex®-R4F Technical Reference Manual.
2.3.1 Resets
The TMS570LS31x/21x microcontroller can be reset by either of the conditions described in Table 2-8.
Each reset condition is indicated in the System Exception Status Register (SYSESR).
The device nRST terminal is an I/O. It can be driven low by an external circuit to force a warm reset on the
microcontroller. This terminal will be driven low as an output for a minimum of 32 peripheral clock (VCLK)
cycles for any device system reset condition. As a result the EXTRST bit in the SYSESR register,
SYSESR[3], gets set for all reset conditions listed in Table 2-8. The nRST is driven low as an output for a
longer duration during device power-up or whenever the power-on reset (nPORRST) is driven low
externally. Refer to the device datasheet for the electrical and timing specifications for the nRST.
Table 2-8. Causes of Resets
Condition
Description
Driving nPORRST pin low
externally
Cold reset, or power-on reset. This reset signal is typically driven by an external voltage
supervisor. This reset is flagged by the PORST bit in the SYSESR register, SYSESR[15].
Voltage Monitor reset
The microcontroller has an embedded voltage monitor that generates a power-on reset when
the core voltage gets out of a valid range, or when the I/O voltage falls below a threshold.
This reset is also flagged by the PORST bit in the SYSESR register, SYSESR[15].
Note: The voltage monitor is not an alternative for an external voltage supervisor.
Driving nRST pin low externally
Warm reset. This reset input is typically used in a system with multiple ICs and which requires
that the microcontroller also gets reset whenever the other IC detects a fault condition. This
reset is flagged by the EXTRST bit in the SYSESR, register SYSESR[3].
Oscillator failure
This reset is generated by the system module when the clock monitor detects an oscillator fail
condition. Whether or not a reset is generated is also dictated by a register in the system
module. This reset is flagged by the OSCRST bit in the SYSESR register, SYSESR[14].
Software reset
This reset is generated by the application software writing a 1 to bit 15 of System Exception
Control Register (SYSECR) or a 0 to bit 14 of SYSECR. It is typically used by a bootloader
type of code that uses a software reset to allow the code execution to branch to the
application code once it is programmed into the program memory. This reset is flagged by the
SWRST bit in the SYSESR register, SYSESR[4].
CPU reset
This reset is generated by the CPU self-test controller (LBIST) or by changing the memory
protection (MMU/MPU) configuration in the CPURSTCR register. This reset is flagged by the
CPURST bit in the SYSESR register, SYSESR[5].
Debug reset
The ICEPICK logic implemented on the microcontroller allows a system reset to be generated
via the debug logic. This reset is flagged by the WDRST bit in the SYSESR register,
SYSESR[13].
Watchdog reset
This reset is generated by the digital windowed watchdog (DWWD) module on the
microcontroller. The DWWD can generate a reset whenever the watchdog service window is
violated. This reset is flagged by the WDRST bit in the SYSESR register, SYSESR[13].
2.3.2 Aborts
When the ARM Cortex-R4F processor's memory system cannot complete a memory access successfully,
an abort is generated. An error occurring on an instruction fetch generates a prefetch abort. Errors
occurring on data accesses generate data aborts. Aborts are also categorized as being either precise or
imprecise.
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Prefetch Aborts
When a Prefetch Abort (PABT) occurs, the processor marks the prefetched instruction as invalid, but does
not take the exception until the instruction is to be executed. If the instruction is not executed, for example
because a branch occurs while it is in the pipeline, the abort does not take place.
All prefetch aborts are precise aborts.
2.3.2.2
Data Aborts
An error occurring on a data memory access can generate a data abort. If the instruction generating the
memory access is not executed, for example, because it fails its condition codes, or is interrupted, the
data abort does not take place.
A Data Abort (DABT) can be either precise or imprecise, depending on the type of fault that caused it.
2.3.2.3
Precise Aborts
A precise abort, also known as a synchronous abort, is one for which the exception is guaranteed to be
taken on the instruction that generated the aborting memory access. The abort handler can use the value
in the Link Register (r14_abt) to determine which instruction generated the abort, and the value in the
Saved Program Status Register (SPSR_abt) to determine the state of the processor when the abort
occurred.
2.3.2.4
Imprecise Aborts
An imprecise abort, also known as an asynchronous abort, is one for which the exception is taken on a
later instruction to the instruction that generated the aborting memory access. The abort handler cannot
determine which instruction generated the abort, or the state of the processor when the abort occurred.
Therefore, imprecise aborts are normally fatal.
Imprecise aborts can be generated by store instructions to normal-type or device-type memory. When the
store instruction is committed, the data is normally written into a buffer that holds the data until the
memory system has sufficient bandwidth to perform the write access. This gives read accesses higher
priority. The write data can be held in the buffer for a long period, during which many other instructions
can complete. If an error occurs when the write is finally performed, this generates an imprecise abort.
The TMS570LS31x/21x microcontroller architecture applies techniques at the system level to mitigate the
impact of imprecise aborts. System level adoption of write status sidebands to the data path allow bus
masters to comprehend imprecise aborts, turning them into precise aborts. In cases where this approach
is not feasible, buffering bridges or other sources of imprecision may build a FIFO of current transactions
such that an imprecise abort may be registered at the point of imprecision for later analysis.
Masking Of Imprecise Aborts:
The nature of imprecise aborts means that they can occur while the processor is handling a different
abort. If an imprecise abort generates a new exception in such a situation, the banked link register
(R14_abt) and the Saved Processor Status Register (SPSR_abt) values are overwritten. If this occurs
before the data is pushed to the stack in memory, the state information about the first abort is lost. To
prevent this from happening, the Current Processor Status Register (CPSR) contains a mask bit to
indicate that an imprecise abort cannot be accepted, the A-bit. When the A-bit is set, any imprecise abort
that occurs is held pending by the processor until the A-bit is cleared, when the exception is actually
taken. The A-bit is automatically set when abort, IRQ or FIQ exceptions are taken, and on reset. The
application must only clear the A-bit in an abort handler after the state information has either been stacked
to memory, or is no longer required.
NOTE: Default Behavior for Imprecise Aborts
The A-bit in the CPSR is set by default. This means that no imprecise abort exception will
occur. The application must enable imprecise abort exception generation by clearing the Abit of the CPSR.
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2.3.2.5
Conditions That Generate Aborts
An Abort is generated under the following conditions on the TMS570LS31x/21x microcontrollers.
• Access to an illegal address (a nonimplemented address)
• Access to a protected address (protection violation)
• Parity / ECC / Time-out Error on a valid access
Illegal Addresses:
The illegal addresses and the responses to an access to these addresses are defined in Table 2-3.
Addresses Protected By MPU:
Memory access permissions can be configured via the ARM Cortex-R4F processor’s Memory Protection
Unit (MPU). For more details on the MPU configuration, refer to the ARM® Cortex®-R4F Technical
Reference Manual.
A memory access violation is logged as a permission fault in the CPU’s fault status register and the virtual
address of the access is logged into the CPU’s fault address register.
Protection of Peripheral Register and Memory Frames:
Accesses to the peripheral register and memory frames can be protected either by configuring the MPU or
by configuring the Peripheral Central Resource (PCR) controller registers.
The PCR module PPROTSETx registers contain one bit per peripheral select quadrant. These bits define
the access permissions to the peripheral register frames. If the CPU attempts to write to a peripheral
register for which it does not have the correct permissions, a protection violation is detected and an Abort
occurs.
Some modules also enforce register updates to only be allowed when the CPU is in a privileged mode of
operation. If the CPU writes to these registers in user mode, the writes are ignored.
The PCR module PMPROTSETx registers contain one bit per peripheral memory frame. These bits define
the access permissions to the peripheral memory frames. If the CPU attempts to write to a peripheral
memory for which it does not have the correct permissions, a protection violation is detected and an Abort
occurs.
NOTE: No Access Protection for Reads
The PCR PPROTSETx and PMPROTSETx registers protect the peripheral registers and
memories against illegal writes by the CPU. The CPU can read from the peripheral registers
and memories in both user and privileged modes.
2.3.3 System Software Interrupts
The system module provides the capability of generating up to four software interrupts. A software
interrupt is generated by writing the correct key value to either of the four System Software Interrupt
Registers (SSIRx). The SSI registers also allow the application to provide a label for that software
interrupt. This label is an 8-bit value that can then be used by the interrupt service routine to perform the
required task based on the value provided. The source of the system software interrupt is reflected in the
system software interrupt vector (SSIVEC) register.
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This section describes the clocking structure of the TMS570LS31x/21x microcontrollers.
2.4.1 Clock Sources
The devices support up to 7 clock sources. These are shown in Table 2-9. The electrical specifications as
well as the timing requirements for each of the clock sources in Table 2-9 is specified in the device
datasheet.
Table 2-9. Clock Sources
2.4.1.1
Clock Source #
Clock Source Name
Description
0
OSCIN
Main oscillator. This is the primary clock for the microcontroller and is the
primary input to the phase-locked loops. The oscillator frequency must be
between 5 and 20 MHz.
1
PLL1
This is the output of the main PLL. The PLL is capable of modulating its
output frequency in a controlled manner to reduce the radiated emissions.
2
Not implemented
This clock source is not available and must not be enabled or used as source
for any clock domain.
3
EXTCLKIN1
External clock input 1. A square wave input can be applied to this device input
and used as a clock source inside the device.
4
LF LPO
(Low-Frequency LPO)
(CLK80K)
This is the low-frequency output of the internal reference oscillator. This is
typically an 80 KHz signal (CLK80K) that is used by the real-time interrupt
module for generating periodic interrupts to wake up from a low power mode.
5
HF LPO
(High-Frequency LPO)
(CLK10M)
This is the high-frequency output of the internal reference oscillator. This is
typically a 10 MHz signal (CLK10M) that is used by the clock monitor module
as a reference clock to monitor the main oscillator frequency.
6
PLL2
This is the output of the second PLL. There is no option of modulating this
PLL’s output signal. This separate non-modulating PLL allows the generation
of an asynchronous clock source that is independent of the CPU clock
frequency.
7
EXTCLKIN2
External clock input 2. A square wave input can be applied to this device input
and used as a clock source inside the device.
Enabling / Disabling Clock Sources
Each clock source can be independently enabled or disabled using the set of Clock Source Disable
registers – CSDIS, CSDISSET and CSDISCLR.
Each bit in these registers corresponds to the clock source number indicated in Table 2-9. For example,
setting bit 1 in the CSDIS or CSDISSET registers disables the PLL#1.
NOTE: Disabling the Main Oscillator or HF LPO
By default, the clock monitoring circuit is enabled and checks for the main oscillator
frequency to be within a certain range using the HF LPO as a reference. If the main oscillator
and/or the HF LPO are disabled with the clock monitoring still enabled, the clock monitor will
indicate an oscillator fault. Clock monitoring must be disabled before disabling the main
oscillator or the HF LPO clock source(s).
A clock source is only disabled once there is no active clock domain that is using that clock source. Also,
see Chapter 10 for more information on enabling/disabling the oscillator and PLL.
On the TMS570LS31x/21x microcontrollers, the clock sources 0, 4, and 5 are enabled by default.
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2.4.1.2
Checking for Valid Clock Sources
The application can check whether a clock source is valid or not by checking the corresponding bit to be
set in the Clock Source Valid Status (CSVSTAT) register. For example, the application can check if bit 1 in
CSVSTAT is set before using the output of PLL1 as the source for any clock domain.
NOTE: The clock sources LF LPO, EXTCLKIN1, and EXTCLKIN2 have no validity check. These
clock sources are considered to be always valid and are available for use by a clock domain
as soon as they are enabled. The application must ensure that a valid clock signal is present
on the EXTCLKINx inputs before enabling these clock sources.
2.4.2 Clock Domains
The clocking on this device is divided into multiple clock domains for flexibility in control as well as clock
source selection. There are 10 clock domains on this device. Each of these are described in Table 2-10.
Table 2-10. Clock Domains
Clock Domain
Clock
Domain #
GCLK
0
Default
Source
OSCIN
Source
Selection
Register
Special Considerations
GHVSRC
• Clock domain used by one of the two Cortex-R4F CPUs operating
in lock-step
• Always the same frequency as HCLK
• In phase with HCLK
• Is disabled separately from HCLK via the CDDISx registers bit 0
• Can be divided by 1 up to 8 when running CPU selftest (LBIST)
using the CLKDIV field of the STCCLKDIV register at address
0xFFFFE108
GCLK2
0
OSCIN
GHVSRC
• Clock domain used by the second Cortex-R4F CPU operating in
lock-step
• Always the same frequency as GCLK
• 2 cycles delayed from GCLK
• Is disabled along with GCLK
• Gets divided by the same divider setting as that for GCLK when
running CPU selftest (LBIST)
HCLK
1
OSCIN
GHVSRC
• Clock domain used by the high-speed system modules: Flash
memory interfaces, TCRAM interface, Error Signaling Module
(ESM), DMA
• Is disabled via the CDDISx registers bit 1
GHVSRC
• Clock domain used by some system modules (VIM), peripheral
modules accessed via the Peripheral Central Resource (PCR)
controller, and all other register interfaces also accessed via the
PCR
• Divided down from HCLK
• Can be HCLK/1, HCLK/2,... or HCLK/16
• Is disabled separately from HCLK via the CDDISx registers bit 2
GHVSRC
• Clock domain used by the timer modules: N2HET1, N2HET2 and
the dedicated transfer units: HTU1, HTU2
• Divided down from HCLK
• Can be HCLK/1, HCLK/2,... or HCLK/16
• Frequency must be an integer multiple of VCLK frequency
• Is disabled separately from HCLK via the CDDISx registers bit 3
GHVSRC
•
•
•
•
VCLK
VCLK2
VCLK3
2
3
8
OSCIN
OSCIN
OSCIN
Clock domain used for EMAC and EMIF slave interfaces
Divided down from HCLK
Can be HCLK/1, HCLK/2,... or HCLK/16
Is disabled separately from HCLK via the CDDISx registers bit 8
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Table 2-10. Clock Domains (continued)
Clock Domain
VCLKA1
VCLKA2
VCLKA4
RTICLK
Clock
Domain #
4
5
11
6
Default
Source
VCLK
VCLK
VCLK
VCLK
Source
Selection
Register
Special Considerations
VCLKASRC
• Clock domain dedicated for the CAN controllers: DCAN1, DCAN2,
DCAN3, used for baud-rate generation
• Defaults to VCLK as the source
• Frequency can be as fast as HCLK frequency
• Is disabled via the CDDISx registers bit 4
VCLKASRC
• Clock domain dedicated for the FlexRay controller and the
dedicated transfer unit
• Defaults to VCLK as the source
• Frequency can be as fast as HCLK frequency
• Is disabled via the CDDISx registers bit 5
VCLKACON1
• Clock domain dedicated for the Ethernet controller (EMAC) when
the TX and RX clocks are internally generated
• Defaults to VCLK as the source
• Frequency can be as fast as HCLK frequency
• Is disabled via the CDDISx registers bit 11
RCLKSRC
• Clock domain dedicated for timebase generation in the Real-Time
Interrupt (RTI) generation module
• Defaults to VCLK as the source
• If a clock source other than VCLK is selected for RTICLK, then
the RTICLK frequency must be less than or equal to VCLK/3
• Application can ensure this by programming the RTI1DIV field of
the RCLKSRC register, if necessary
• Is disabled via the CDDISx registers bit 6
Each of the control registers indicated in Table 2-10 are defined in Section 2.5. The AC timing
characteristics for each clock domain are specified in the device datasheet.
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2.4.2.1
Enabling / Disabling Clock Domains
Each clock domain can be independently enabled or disabled using the set of Clock Domain Disable
registers – CDDIS, CDDISSET, and CDDISCLR.
Each bit in these registers corresponds to the clock domain number indicated in Table 2-10. For example,
setting bit 1 in the CDDIS or CDDISSET registers disables the HCLK clock domain. The clock domain will
be turned off only when every module that uses the HCLK domain gives the “permission” for HCLK to be
turned off.
All clock domains are enabled by default, or upon a system reset, or whenever a wake up condition is
detected.
2.4.2.2
Mapping Clock Sources to Clock Domains
Each clock domain needs to be mapped to a valid clock source. There are control registers that allow an
application to choose the clock sources for each clock domain.
• Selecting clock source for GCLK, HCLK and VCLKx domains
The CPU clock (GCLK), the system module clock (HCLK), and the peripheral bus clocks (VCLKx) all use
the same clock source. This clock source is selected via the GHVSRC register. The default source for the
GCLK, HCLK and VCLKx is the main oscillator. That is, after power up, the GCLK and HCLK are running
at the OSCIN frequency, while the VCLKx frequency is the OSCIN frequency divided by 2.
• Selecting clock source for VCLKA1 and VCLKA2 domains
The clock source for VCLKA1 and VCLKA2 domains is selected via the VCLKASRC register. The default
source for the and VCLKA2 domains is VCLK.
• Selecting clock source for VCLKA4 domain
The clock source for VCLKA4 domain is selected via the VCLKACON1 register. The default source for the
VCLKA4 domain is VCLK.
• Selecting clock source for RTICLK domain
The clock source for RTICLK domain is selected via the RCLKSRC register. The default source for the
RTICLK domain is VCLK.
NOTE: Selecting a clock source for RTICLK that is not VCLK
When the application chooses a clock source for RTICLK domain that is not VCLK, then the
application must ensure that the resulting RTICLK frequency must be less than or equal to
VCLK frequency divided by 3. The application can configure the RTI1DIV field of the
RCLKSRC register for dividing the selected clock source frequency by 1, 2, 4 or 8 to meet
this requirement.
2.4.3 Low Power Modes
All clock domains are active in the normal operating mode. This is the default mode of operation. As
described in Section 2.4.1.1 and Section 2.4.2.1, the application can choose to disable any particular clock
source and domain that it does not plan to use. Also, the peripheral central resource controller (PCR) has
control registers to enable / disable the peripheral clock (VCLK) for each peripheral select. This offers the
application a large number of choices for enabling / disabling clock sources, or clock domains, or clocks to
specific peripherals.
This section describes three particular low-power modes and their typical characteristics. They are not the
only low-power modes configurable by the application, as just described.
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Table 2-11. Typical Low-Power Modes
Mode
Name
Doze
Snooze
Sleep
Active Clock
Source(s)
Main oscillator
LF LPO
None
Active
Clock
Domain(s)
Wake Up Options
RTICLK
RTI interrupt,
GIO interrupt,
CAN message,
SCI message
RTICLK
None
RTI interrupt,
GIO interrupt,
CAN message,
SCI message
GIO interrupt,
CAN message,
SCI message
Suggested
Wake Up
Clock
Source(s)
Wake Up Time (wake up detected -to- CPU
code execution start)
Main oscillator
Flash pump sleep -> active transition time
+
Flash bank sleep -> standby transition time
+
Flash bank standby -> active transition time
HF LPO
HF LPO warm start-up time
+
Flash pump sleep -> active transition time
+
Flash bank sleep -> standby transition time
+
Flash bank standby -> active transition time
HF LPO
HF LPO warm start-up time
+
Flash pump sleep -> active transition time
+
Flash bank sleep -> standby transition time
+
Flash bank standby -> active transition time
2.4.3.1 Typical Software Sequence to Enter a Low-Power Mode
1. Program the flash banks and flash pump fall-back modes to be “sleep”.
The flash pump transitions from active to sleep mode only after all the flash banks have switched from
active to sleep mode. The flash banks start switching from active to sleep mode only after the banks
are not accessed for at least a duration defined by the Active Grace Period (AGP) parameter
configured for the banks. See Chapter 5 for more details.
2. Disable the clock sources that are not required to be kept active.
A clock source does not get disabled until all clock domains using that clock source are disabled first,
or are configured to use an alternate clock source.
3. Disable the clock domains that are not required to be kept active.
A clock domain does not get disabled until all modules using that clock domain “give their permission”
for that clock domain to be turned off.
4. Idle the Cortex-R4F core.
The ARM Cortex-R4F CPU has internal power management logic, and requires a dedicated instruction
to be used in order to enter a low power mode. This is the Wait For Interrupt (WFI) instruction.
When a WFI instruction is executed, the Cortex-R4F core flushes its pipeline, flushes all write buffers,
and completes all pending bus transactions. At this time the core indicates to the system that the clock
to the core can be stopped. This indication is used by the Global Clock Module (GCM) to turn off the
CPU clock domain (GCLK) if the CDDIS register bit 0 is set.
2.4.3.2
Special Considerations for Entry to Low Power Modes
Some bus master modules – High-End Timer Transfer Units (HTUx), FlexRay Transfer Unit (FTU), Data
Modification Module (DMM), and Parameter Overlay Module (POM), can have ongoing transactions when
the application wants to enter a low power mode to turn off the clocks to those modules. This is not
recommended as it could leave the device in an unpredictable state. Refer to the individual module
chapters for more information about the sequence to be followed to safely enter a low-power mode.
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2.4.3.3
Selecting Clock Source Upon Wake Up
The domains for CPU clock (GCLK), the system clock (HCLK) and the peripheral clock (VCLKx) use the
same clock source selected via the GHVSRC field of the GHVSRC register. The GHVSRC register also
allows the application to choose the clock source after wake up via the GHVWAKE field.
When a wake up condition is detected, if the selected wake up clock source is not already active, the
global clock module (GCM) will enable this selected clock source, wait for it to become valid, and then use
it for the GCLK, HCLK and VCLKx domains. The other clock domains VCLKAx and RTICLK retain the
configuration for their clock source selection registers – VCLKASRC, VCLKACON1 and RCLKSRC.
2.4.4 Clock Test Mode
The TMS570LS31x/21x microcontrollers support a test mode which allows a user to bring out several
different clock sources and clock domains on to the ECLK terminal. This is very useful information for
debug purposes. Each clock source also has a corresponding clock source valid status flag in the Clock
Source Valid Status (CSVSTAT) register. The clock source valid status flags can also be brought out on to
the NHET1[12] terminal in this clock test mode.
The clock test mode is controlled by the CLKTEST register in the system module register frame.
Figure 2-4. Clock Test Register (CLKTEST) [offset = FFFF FFF8Ch]
31
27
26
25
24
Reserved
ALTLIMPCLOCK
ENABLE
RANGEDET
CTRL
RANGEDET
ENASSEL
R-0
R/WP-0
R/WP-0
R/WP-0
23
20
15
19
16
Reserved
CLK_TEST_EN
R-0
R/WP-Ah
12
11
8
7
4
3
0
Reserved
SEL_GIO_PIN
Reserved
SEL_ECP_PIN
R-0
R/WP-0
R-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
The clock test mode is enabled by writing 5h to the CLK_TEST_EN field.
The signal to be brought out on to the ECLK terminal is defined by the SEL_ECP_PIN field, and the signal
to be brought out on to the NHET1[12] terminal is defined by the SEL_GIO_PIN field.
The choices for these selections are defined in Table 2-12.
Table 2-12. Clock Test Mode Options
SEL_ECP_PIN
Signal on ECLK
SEL_GIO_PIN
Signal on NHET1[12]
0000
Oscillator
0000
Oscillator Valid status
0001
PLL1 free-running clock output
0001
PLL1 Valid status
0010
Reserved
0010
Reserved
0011
EXTCLKIN1
0011
Reserved
0100
Low-frequency LPO
(Low-Power Oscillator) clock
0100
Reserved
0101
High-frequency LPO
(Low-Power Oscillator) clock
0101
HF LPO Valid status
0110
PLL2 free-running clock output
0110
PLL2 Valid status
0111
EXTCLKIN2
0111
Reserved
1000
GCLK
1000
LF LPO Valid status
1001
RTI Base
1001
Reserved
1010
Reserved
1010
Reserved
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Table 2-12. Clock Test Mode Options (continued)
SEL_ECP_PIN
Signal on ECLK
SEL_GIO_PIN
Signal on NHET1[12]
1011
VCLKA1
1011
Reserved
1100
VCLKA2
1100
Reserved
1101
Reserved
1101
Reserved
1110
VCLKA4
1110
Reserved
1111
Reserved
1111
Reserved
2.4.5 Embedded Trace Macrocell (ETM-R4)
The TMS570LS31x/21x microcontrollers contain an ETM-R4 module with a 32-bit internal data port. The
ETM-R4 module is connected to a Trace Port Interface Unit (TPIU) with a 32-bit data bus; the TPIU
provides a 35-bit (32-bit data and 3-bit control) external interface for trace. The ETM-R4 is CoreSight
compliant and follows the ETM v3 specification. For more details on the ETM-R4 specification, refer to the
Embedded Trace Macrocell Architecture Specification.
The ETM clock source is selected as either VCLK or the external ETMTRACECLKIN pin. The selection is
done by the EXTCTLOUT control bits of the TPIU EXTCTL_Out_Port register. The address of this register
is TPIU base address + 0x404.
Before you begin accessing TPIU registers, the TPIU should be unlocked via the CoreSight key and 1h or
2h should be written to this register.
Figure 2-5. EXTCTL_Out_Port Register [offset = 404h]
31
16
Reserved
R-0
15
2
1
0
Reserved
EXTCTLOUT
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 2-13. EXTCTL_Out_Port Register Field Descriptions
Bit
Field
31-2
Reserved
1-0
EXTCTLOUT
124
Value
0
Description
Reads return 0. Writes have no effect.
EXTCTL output control.
0
Tied-zero
1h
VCLK
2h
ETMTRACECLKIN
3h
Tied-zero
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2.4.6 Safety Considerations for Clocks
The TMS570LS31x/21x microcontrollers are targeted for use in several safety-critical applications. The
following sections describe the internal or external monitoring mechanisms that detect and signal clock
source failures.
2.4.6.1
Oscillator Monitor
The oscillator clock frequency is monitored by a dedicated circuitry called CLKDET using the HF LPO as
the reference clock. The CLKDET flags an oscillator fail condition whenever the OSCIN frequency falls
outside of a range which is defined by the HF LPO frequency.
The valid OSCIN range is defined as a minimum of f(HF LPO) / 4 to a maximum of f(HF LPO) * 4.
Refer the specific device datasheet to identify the range of the primary oscillator frequency that is
considered valid.
The application can select the device response to an oscillator fail indication. See Chapter 10 for more
details on the oscillator monitoring and the system response choices.
2.4.6.2
PLL Slip Detector
Both the PLL macros implemented on the microcontrollers have an embedded slip detection circuit. A PLL
slip is detected by the slip detector under the following conditions:
1. Reference cycle slip, RFSLIP — the output clock is running too fast relative to the reference clock
2. Feedback cycle slip, FBSLIP — the output clock is running too slow relative to the reference clock
The device also includes optional filters that can be enabled before a slip indication from the PLL is
actually logged in the system module Global Status Register (GLBSTAT). Also, once a PLL slip condition
is logged in the system module global status register, the application can choose the device’s response to
the slip indication. See Chapter 10 for more details on PLL slip and the system response choices.
2.4.6.3
External Clock Monitor
The microcontrollers support a terminal called ECLK – External Clock, which is used to output a slow
frequency which is divided down from the device system clock frequency. An external circuit can monitor
the ECLK frequency in order to check that the device is operating at the correct frequency.
The frequency of the signal output on the ECLK pin can be divided down by 1 to 65536 from the
peripheral clock (VCLK) frequency using the External Clock Prescaler Control Register (ECPCNTL). The
actual clock output on ECLK is enabled by setting the ECP CLK FUN bit of the SYSPC1 control register.
2.4.6.4
Dual-Clock Comparators
The microcontrollers include two instances of the dual-clock comparator module. This module includes two
down counters which independently count from two separate seed values at the rate of two independent
clock frequencies. One of the clock inputs is a reference clock input, selectable between the main
oscillator or the HF LPO in functional mode. The second clock input is selectable from among a set of
defined signals as described in Section 2.4.6.4.1 and Section 2.4.6.4.2. This mechanism can be used to
use a known-good clock to measure the frequency of another clock.
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2.4.6.4.1 DCC1
Table 2-14. DCC1 Counter 0 Clock Inputs
Clock Source [3-0]
Clock / Signal Name
All other values
Oscillator (OSCIN)
0x5
HF LPO
0xA
Test clock (TCK)
Table 2-15. DCC1 Counter 1 Clock / Signal Inputs
Key [3-0]
0xA
All other values
Clock Source [3-0]
Clock / Signal Name
0x0
PLL1 free-running clock output
0x1
PLL2 free-running clock output
0x2
LF LPO
0x3
HF LPO
0x4
Reserved
0x5
EXTCLKIN1
0x6
EXTCLKIN2
0x7
Reserved
0x8-0xF
VCLK
Any value
N2HET1[31]
As can be seen, the main oscillator (OSCIN) can be used for counter 0 as a “known-good” reference
clock. The clock for counter 1 can be selected from among 8 options. See Chapter 11 for more details on
the DCC usage.
2.4.6.4.2 DCC2
Table 2-16. DCC2 Counter 0 Clock Inputs
Clock Source [3-0]
Clock / Signal Name
All other values
Oscillator (OSCIN)
0xA
Test clock (TCK)
Table 2-17. DCC2 Counter 1 Clock / Signal Inputs
Key [3-0]
0xA
All other values
Clock Source [3-0]
Clock / Signal Name
0x0-0x7
Reserved
0x8-0xF
VCLK
Any value
N2HET2[0]
As can be seen, the main oscillator (OSCIN) can be used for counter 0 as a “known-good” reference
clock. The clock for counter 1 can be selected from among 2 options. See Chapter 11 for more details on
the DCC usage.
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2.5
System and Peripheral Control Registers
The following sections describe the system and peripheral control registers of the TMS570LS31x/21x
microcontroller.
2.5.1 Primary System Control Registers (SYS)
This section describes the System registers. These registers are divided into two separate frames. The
start address of the primary system module frame is FFFF FF00h. The start address of the secondary
system module frame is FFFF E100h. The registers support 32-, 16-, and 8-bit writes. The offset is relative
to the system module frame start address.
Table 2-18 contains a list of the primary system control registers.
Table 2-18. Primary System Control Registers
Offset
Acronym
Register Description
00h
SYSPC1
SYS Pin Control Register 1
Section 2.5.1.1
Section
04h
SYSPC2
SYS Pin Control Register 2
Section 2.5.1.2
08h
SYSPC3
SYS Pin Control Register 3
Section 2.5.1.3
0Ch
SYSPC4
SYS Pin Control Register 4
Section 2.5.1.4
10h
SYSPC5
SYS Pin Control Register 5
Section 2.5.1.5
14h
SYSPC6
SYS Pin Control Register 6
Section 2.5.1.6
18h
SYSPC7
SYS Pin Control Register 7
Section 2.5.1.7
1Ch
SYSPC8
SYS Pin Control Register 8
Section 2.5.1.8
20h
SYSPC9
SYS Pin Control Register 9
Section 2.5.1.9
30h
CSDIS
Clock Source Disable Register
Section 2.5.1.10
34h
CSDISSET
Clock Source Disable Set Register
Section 2.5.1.11
38h
CSDISCLR
Clock Source Disable Clear Register
Section 2.5.1.12
3Ch
CDDIS
Clock Domain Disable Register
Section 2.5.1.13
40h
CDDISSET
Clock Domain Disable Set Register
Section 2.5.1.14
44h
CDDISCLR
Clock Domain Disable Clear Register
Section 2.5.1.15
48h
GHVSRC
GCLK, HCLK, VCLK, and VCLK2 Source Register
Section 2.5.1.16
4Ch
VCLKASRC
Peripheral Asynchronous Clock Source Register
Section 2.5.1.17
50h
RCLKSRC
RTI Clock Source Register
Section 2.5.1.18
54h
CSVSTAT
Clock Source Valid Status Register
Section 2.5.1.19
58h
MSTGCR
Memory Self-Test Global Control Register
Section 2.5.1.20
5Ch
MINITGCR
Memory Hardware Initialization Global Control Register
Section 2.5.1.21
60h
MSINENA
Memory Self-Test/Initialization Enable Register
Section 2.5.1.22
64h
Reserved
Reserved
68h
MSTCGSTAT
MSTC Global Status Register
Section 2.5.1.23
6Ch
MINISTAT
Memory Hardware Initialization Status Register
Section 2.5.1.24
70h
PLLCTL1
PLL Control Register 1
Section 2.5.1.25
74h
PLLCTL2
PLL Control Register 2
Section 2.5.1.26
78h
SYSPC10
SYS Pin Control Register 10
Section 2.5.1.27
7Ch
DIEIDL
Die Identification Register, Lower Word
Section 2.5.1.28
80h
DIEIDH
Die Identification Register, Upper Word
Section 2.5.1.29
88h
LPOMONCTL
LPO/Clock Monitor Control Register
Section 2.5.1.30
8Ch
CLKTEST
Clock Test Register
Section 2.5.1.31
90h
DFTCTRLREG
DFT Control Register
Section 2.5.1.32
94h
DFTCTRLREG2
DFT Control Register 2
Section 2.5.1.33
98h-9Ch
Reserved
Reserved
A0h
GPREG1
General Purpose Register
Section 2.5.1.34
A8h
IMPFASTS
Imprecise Fault Status Register
Section 2.5.1.35
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Table 2-18. Primary System Control Registers (continued)
Offset
128
Acronym
Register Description
ACh
IMPFTADD
Imprecise Fault Write Address Register
Section 2.5.1.36
B0h
SSIR1
System Software Interrupt Request 1 Register
Section 2.5.1.37
B4h
SSIR2
System Software Interrupt Request 2 Register
Section 2.5.1.38
B8h
SSIR3
System Software Interrupt Request 3 Register
Section 2.5.1.39
BCh
SSIR4
System Software Interrupt Request 4 Register
Section 2.5.1.40
C0h
RAMGCR
RAM Control Register
Section 2.5.1.41
C4h
BMMCR1
Bus Matrix Module Control Register 1
Section 2.5.1.42
C8h
Reserved
Reserved
CCh
CPURSTCR
CPU Reset Control Register
Section 2.5.1.43
D0h
CLKCNTL
Clock Control Register
Section 2.5.1.44
D4h
ECPCNTL
ECP Control Register
Section 2.5.1.45
DCh
DEVCR1
DEV Parity Control Register 1
Section 2.5.1.46
E0h
SYSECR
System Exception Control Register
Section 2.5.1.47
E4h
SYSESR
System Exception Status Register
Section 2.5.1.48
E8h
SYSTASR
System Test Abort Status Register
Section 2.5.1.49
ECh
GLBSTAT
Global Status Register
Section 2.5.1.50
F0h
DEVID
Device Identification Register
Section 2.5.1.51
F4h
SSIVEC
Software Interrupt Vector Register
Section 2.5.1.52
F8h
SSIF
System Software Interrupt Flag Register
Section 2.5.1.53
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2.5.1.1
SYS Pin Control Register 1 (SYSPC1)
The SYSPC1 register, shown in Figure 2-6 and described in Table 2-19, controls the function of the ECLK
pin.
Figure 2-6. SYS Pin Control Register 1 (SYSPC1) [offset = 00h]
31
16
Reserved
R-0
15
1
0
Reserved
ECPCLKFUN
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 2-19. SYS Pin Control Register 1 (SYSPC1) Field Descriptions
Bit
Field
31-1
Value
Reserved
0
0
ECPCLKFUN
Description
Reads return 0. Writes have no effect.
ECLK function. This bit changes the function of the ECLK pin.
0
ECLK is in GIO mode.
1
ECLK is in functional mode as a clock output.
Note: Proper ECLK duty cycle is not assured until 1 ECLK cycle has elapsed after switching
into functional mode.
2.5.1.2
SYS Pin Control Register 2 (SYSPC2)
The SYSPC2 register, shown in Figure 2-7 and described in Table 2-20, controls whether the pin is an
input or an output when in GIO mode.
Figure 2-7. SYS Pin Control Register 2 (SYSPC2) [offset = 04h]
31
16
Reserved
R-0
15
1
0
Reserved
ECPCLKDIR
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 2-20. SYS Pin Control Register 2 (SYSPC2) Field Descriptions
Bit
31-1
0
Field
Value
Reserved
0
ECPCLKDIR
Description
Reads return 0. Writes have no effect.
ECLK data direction. This bit controls the direction of the ECLK pin when it is configured to be in
GIO mode only.
0
The ECLK pin is an input.
Note: If the pin direction is set as an input , the output buffer is tristated.
1
The ECLK pin is an output.
Note: The ECLK pin is placed into GIO mode by clearing the ECPCLKFUN bit to 0 in the
SYSPC1 register.
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SYS Pin Control Register 3 (SYSPC3)
The SYSPC3 register, shown in Figure 2-8 and described in Table 2-21, displays the logic state of the
ECLK pin when it is in GIO mode.
Figure 2-8. SYS Pin Control Register 3 (SYSPC3) [offset = 08h]
31
16
Reserved
R-0
15
1
0
Reserved
ECPCLKDIN
R-0
R-U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -U = Undefined
Table 2-21. SYS Pin Control Register 3 (SYSPC3) Field Descriptions
Bit
Field
31-1
Reserved
0
Value
0
ECPCLKDIN
2.5.1.4
Description
Reads return 0. Writes have no effect.
ECLK data in. This bit displays the logic state of the ECLK pin when it is configured to be in GIO
mode.
0
The ECLK pin is at logic low (0).
1
The ECLK pin is at logic high (1).
SYS Pin Control Register 4 (SYSPC4)
The SYSPC4 register, shown in Figure 2-9 and described in Table 2-22, controls the logic level output
function of the ECLK pin when when it is configured as an output in GIO mode.
Figure 2-9. SYS Pin Control Register 4 (SYSPC4) [offset = 0Ch]
31
16
Reserved
R-0
15
1
0
Reserved
ECPCLKDOUT
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 2-22. SYS Pin Control Register 4 (SYSPC4) Field Descriptions
Bit
31-1
0
Field
Reserved
Value
0
ECPCLKDOUT
Description
Reads return 0. Writes have no effect.
ECLK data out write. This bit is only active when the ECLK pin is configured to be in GIO mode.
Writes to this bit will only take effect when the ECLK pin is configured as an output in GIO mode.
The current logic state of the ECLK pin will be displayed by this bit in both input and output GIO
mode.
0
The ECLK pin is driven to logic low (0).
1
The ECLK pin is driven to logic high (1).
Note: The ECLK pin is placed into GIO mode by setting the ECPCLKFUN bit to 0 in the
SYSPC1 register. The ECLK pin is placed in output mode by setting the ECPCLKDIR bit to 1
in the SYSPC2 register.
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2.5.1.5
SYS Pin Control Register 5 (SYSPC5)
The SYSPC5 register, shown in Figure 2-10 and described in Table 2-23, controls the set function of the
ECLK pin when when it is configured as an output in GIO mode.
Figure 2-10. SYS Pin Control Register 5 (SYSPC5) [offset = 10h]
31
16
Reserved
R-0
15
1
0
Reserved
ECPCLKSET
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 2-23. SYS Pin Control Register 5 (SYSPC5) Field Descriptions
Bit
Field
31-1
Value
Reserved
0
0
ECPCLKSET
Description
Reads return 0. Writes have no effect.
ECLK data out set. This bit drives the output of the ECLK pin high when set in GIO output mode.
0
Write: Writing a 0 has no effect.
1
Write: The ECLK pin is driven to logic high (1).
Note: The current logic state of the ECPCLKDOUT bit will also be displayed by this bit when
the pin is configured in GIO output mode.
Note: The ECLK pin is placed into GIO mode by setting the ECPCLKFUN bit to 0 in the
SYSPC1 register. The ECLK pin is placed in output mode by setting the ECPCLKDIR bit to 1
in the SYSPC2 register.
2.5.1.6
SYS Pin Control Register 6 (SYSPC6)
The SYSPC6 register, shown in Figure 2-11 and described in Table 2-24, controls the clear function of the
ECLK pin when it is configured as an output in GIO mode..
Figure 2-11. SYS Pin Control Register 6 (SYSPC6) [offset = 14h]
31
16
Reserved
R-0
15
1
0
Reserved
ECPCLKCLR
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 2-24. SYS Pin Control Register 6 (SYSPC6) Field Descriptions
Bit
31-1
0
Field
Value
Reserved
0
ECPCLKCLR
Description
Reads return 0. Writes have no effect.
ECLK data out clear. This bit drives the output of the ECLK pin low when set in GIO output mode.
0
Write: The ECLK pin value is unchanged.
1
Write: The ECLK pin is driven to logic low (0).
Note: The current logic state of the ECPCLKDOUT bit will also be displayed by this bit when
the pin is configured in GIO output mode.
Note: The ECLK pin is placed into GIO mode by setting the ECPCLKFUN bit to 0 in the
SYSPC1 register. The ECLK pin is placed in output mode by setting the ECPCLKDIR bit to 1
in the SYSPC2 register.
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SYS Pin Control Register 7 (SYSPC7)
The SYSPC7 register, shown in Figure 2-12 and described in Table 2-25, controls the open drain function
of the ECLK pin.
Figure 2-12. SYS Pin Control Register 7 (SYSPC7) [offset = 18h]
31
16
Reserved
R-0
15
1
0
Reserved
ECPCLKODE
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 2-25. SYS Pin Control Register 7 (SYSPC7) Field Descriptions
Bit
Field
31-1
Reserved
0
Value
0
ECPCLKODE
Description
Reads return 0. Writes have no effect.
ECLK open drain enable. This bit is only active when ECLK is configured to be in GIO mode.
0
The ECLK pin is configured in push/pull (normal GIO) mode.
1
The ECLK pin is configured in open drain mode. The ECPCLKDOUT bit in the SYSPC4 register
controls the state of the ECLK output buffer:
ECPCLKDOUT = 0: The ECLK output buffer is driven low.
ECPCLKDOUT = 1: The ECLK output buffer is tristated.
Note: The ECLK pin is placed into GIO mode by setting the ECPCLKFUN bit to 0 in the
SYSPC1 register.
2.5.1.8
SYS Pin Control Register 8 (SYSPC8)
The SYSPC8 register, shown in Figure 2-13 and described in Table 2-26, controls the pull enable function
of the ECLK pin when it is configured as an input in GIO mode.
Figure 2-13. SYS Pin Control Register 8 (SYSPC8) [offset = 1Ch]
31
16
Reserved
R-0
15
1
0
Reserved
ECPCLKPUE
R-0
R/W-D
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; D = value is device specific
Table 2-26. SYS Pin Control Register 8 (SYSPC8) Field Descriptions
Bit
31-1
0
Field
Reserved
Value
0
ECPCLKPUE
Description
Reads return 0. Writes have no effect.
ECLK pull enable. Writes to this bit will only take effect when the ECLK pin is configured as an
input in GIO mode.
0
ECLK pull enable is active.
1
ECLK pull enable is inactive.
Note: The pull direction (up/down) is selected by the ECPCLKPS bit in the SYSPC9 register.
Note: The ECLK pin is placed into GIO mode by setting the ECPCLKFUN bit to 0 in the
SYSPC1 register. The ECLK pin is placed in input mode by setting the ECPCLKDIR bit to 0 in
the SYSPC2 register.
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2.5.1.9
SYS Pin Control Register 9 (SYSPC9)
The SYSPC9 register, shown in Figure 2-14 and described in Table 2-27, controls the pull up/pull down
configuration of the ECLK pin when it is configured as an input in GIO mode.
Figure 2-14. SYS Pin Control Register 9 (SYSPC9) [offset = 20h]
31
16
Reserved
R-0
15
1
0
Reserved
ECPCLKPS
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 2-27. SYS Pin Control Register 9 (SYSPC9) Field Descriptions
Bit
31-1
0
Field
Value
Reserved
0
ECPCLKPS
Description
Reads return 0. Writes have no effect.
ECLK pull up/pull down select. This bit is only active when ECLK is configured as an input in GIO
mode and the pull up/pull down logic is enabled.
0
ECLK pull down is selected, when pull up/pull down logic is enabled.
1
ECLK pull up is selected, when pull up/pull down logic is enabled.
Note: The ECLK pin pull up/pull down logic is enabled by setting the ECPCLKPUE bit to 0 in
the SYSPC8 register.
Note: The ECLK pin is placed into GIO mode by setting the ECPCLKFUN bit to 0 in the
SYSPC1 register. The ECLK pin is placed in input mode by setting the ECPCLKDIR bit to 0 in
the SYSPC2 register.
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2.5.1.10 Clock Source Disable Register (CSDIS)
The CSDIS register, shown in Figure 2-15 and described in Table 2-28, controls and displays the state of
the device clock sources.
Figure 2-15. Clock Source Disable Register (CSDIS) [offset = 30h]
31
8
Reserved
R-0
7
6
5
4
3
2
1
0
CLKSR7OFF
CLKSR6OFF
CLKSR5OFF
CLKSR4OFF
CLKSR3OFF
Reserved
CLKSR1OFF
CLKSR0OFF
R/WP-1
R/WP-1
R/WP-0
R/WP-0
R/WP-1
R-1
R/WP-1
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 2-28. Clock Source Disable Register (CSDIS) Field Descriptions
Bit
Field
31-8
Reserved
7-3
CLKSR[7-3]OFF
Value
0
Description
Reads return 0. Writes have no effect.
Clock source[7-3] off.
0
Clock source[7-3] is enabled.
1
Clock source[7-3] is disabled.
Note: On wakeup, only clock sources 0, 4 and 5 are enabled.
2
1-0
Reserved
Reads return one. Writes have no effect.
CLKSR[1-0]OFF
Clock source[1-0] off.
0
Clock source[1-0] is enabled.
1
Clock source[1-0] is disabled.
Note: On wakeup, only clock sources 0, 4 and 5 are enabled.
Table 2-29. Clock Sources Table
Clock Source #
Clock Source Name
Clock Source 0
Oscillator
Clock Source 1
PLL1
Clock Source 2
Not Implemented
Clock Source 3
EXTCLKIN
Clock Source 4
Low Frequency LPO (Low Power Oscillator) clock
Clock Source 5
High Frequency LPO (Low Power Oscillator) clock
Clock Source 6
PLL2
Clock Source 7
EXTCLKIN2
NOTE: Nonimplemented clock sources should not be enabled or used.
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2.5.1.11 Clock Source Disable Set Register (CSDISSET)
The CSDISSET register, shown in Figure 2-16 and described in Table 2-30, sets clock sources to the
disabled state.
Figure 2-16. Clock Source Disable Set Register (CSDISSET) [offset = 34h]
31
8
Reserved
R-0
7
6
5
4
3
2
1
0
SETCLKSR7
OFF
SETCLKSR6
OFF
SETCLKSR5
OFF
SETCLKSR4
OFF
SETCLKSR3
OFF
Reserved
SETCLKSR1
OFF
SETCLKSR0
OFF
R/WP-1
R/WP-1
R/WP-0
R/WP-0
R/WP-1
R-1
R/WP-1
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 2-30. Clock Source Disable Set Register (CSDISSET) Field Descriptions
Bit
Field
31-8
Reserved
7-3
SETCLKSR[7-3]OFF
Value
0
Description
Reads return 0. Writes have no effect.
Set clock source[7-3] to the disabled state.
0
Read: Clock source[7-3] is enabled.
Write: Clock source[7-3] is unchanged.
1
Read: Clock source[7-3] is disabled.
Write: Clock source[7-3] is set to the disabled state.
Note: After a new clock source disable bit is set via the CSDISSET register, the new
status of the bit will be reflected in the CSDIS register (offset 30h), the CSDISSET
register (offset 34h) and the CSDISCLR register (offset 38h).
2
1-0
Reserved
1
SETCLKSR[1-0]OFF
Reads return 1. Writes have no effect.
Set clock source[1-0] to the disabled state.
0
Read: Clock source[1-0] is enabled.
Write: Clock source[1-0] is unchanged.
1
Read: Clock source[1-0] is disabled.
Write: Clock source[1-0] is set to the disabled state.
Note: After a new clock source disable bit is set via the CSDISSET register, the new
status of the bit will be reflected in the CSDIS register (offset 30h), the CSDISSET
register (offset 34h) and the CSDISCLR register (offset 38h).
NOTE: A list of the available clock sources is shown in Table 2-29.
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2.5.1.12 Clock Source Disable Clear Register (CSDISCLR)
The CSDISCLR register, shown in Figure 2-17 and described in Table 2-31, clears clock sources to the
enabled state.
Figure 2-17. Clock Source Disable Clear Register (CSDISCLR) [offset = 38h]
31
8
Reserved
R-0
7
6
5
4
3
2
1
0
CLRCLKSR7
OFF
CLRCLKSR6
OFF
CLRCLKSR5
OFF
CLRCLKSR4
OFF
CLRCLKSR3
OFF
Reserved
CLRCLKSR1
OFF
CLRCLKSR0
OFF
R/WP-1
R/WP-1
R/WP-0
R/WP-0
R/WP-1
R-1
R/WP-1
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 2-31. Clock Source Disable Clear Register (CSDISCLR) Field Descriptions
Bit
Field
31-8
Reserved
7-3
CLRCLKSR[7-3]OFF
Value
0
Description
Reads return 0. Writes have no effect.
Enables clock source[7-3].
0
Read: Clock source[7-3] is enabled.
Write: Clock source[7-3] is unchanged.
1
Read: Clock source[7-3] is enabled.
Write: Clock source[7-3] is set to the enabled state.
Note: After a new clock source disable bit is set via the CSDISSET register, the new
status of the bit will be reflected in the CSDIS register (offset 30h), the CSDISSET
register (offset 34h) and the CSDISCLR register (offset 38h).
2
1-0
Reserved
1
CLRCLKSR[1-0]OFF
Reads return 1. Writes have no effect.
Enables clock source[1-0].
0
Read: Clock source[1-0] is enabled.
Write: Clock source[1-0] is unchanged.
1
Read: Clock source[1-0] is enabled.
Write: Clock source[1-0] is set to the enabled state.
Note: After a new clock source disable bit is set via the CSDISSET register, the new
status of the bit will be reflected in the CSDIS register (offset 30h), the CSDISSET
register (offset 34h) and the CSDISCLR register (offset 38h).
NOTE: A list of the available clock sources is shown in Table 2-29.
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2.5.1.13 Clock Domain Disable Register (CDDIS)
The CDDIS register, shown in Figure 2-18 and described in Table 2-32, controls the state of the clock
domains.
NOTE: All the clock domains are enabled on wakeup.
The application should guarantee that when HCLK and VCLK_sys are turned off through the
HCLKOFF bit, the GCLK domain is also turned off.
The register bits in CDDIS are designated as high-integrity bits and have been implemented
with error-correcting logic such that each bit, although read and written as a single bit, is
actually a multi-bit key with error correction capability. As such, single-bit flips within the “key”
can be corrected allowing protection of the system as a whole. An error detected is signaled
to the ESM module.
Figure 2-18. Clock Domain Disable Register (CDDIS) [offset = 3Ch]
31
16
Reserved
R-0
15
11
10
9
8
Reserved
12
VCLKA4OFF
Reserved
Reserved
VCLK3OFF
R-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
7
6
5
4
3
2
1
0
Reserved
RTICLK1OFF
VCLKA2OFF
VCLKA1OFF
VCLK2OFF
VCLKPOFF
HCLKOFF
GCLKOFF
R/WP-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 2-32. Clock Domain Disable Register (CDDIS) Field Descriptions
Bit
Field
31-12 Reserved
11
Value
0
VCLKA4OFF
Description
Reads return 0. Writes have no effect.
VCLKA4 domain off.
0
The VCLKA4 domain is enabled.
1
The VCLKA4 domain is disabled.
10
Reserved
0-1
Reads return 0 or 1 and privilege mode writes allowed.
9
Reserved
0-1
Reads return 0 or 1 and privilege mode writes allowed.
8
VCLK3OFF
7
Reserved
6
RTICLK1OFF
5-4
3
2
VCLK3 domain off.
0
The VCLK3 domain is enabled.
1
The VCLK3 domain is disabled.
0-1
Reads return 0 or 1 and privilege mode writes allowed.
RTICLK1 domain off.
0
The RTICLK1 domain is enabled.
1
The RTICLK1 domain is disabled.
VCLKA[2-1]OFF
VCLKA[2-1] domain off.
0
The VCLKA[2-1] domain is enabled.
1
The VCLKA[2-1] domain is disabled.
VCLK2OFF
VCLK2 domain off.
0
The VCLK2 domain is enabled.
1
The VCLK2 domain is disabled.
VCLKPOFF
VCLK_periph domain off.
0
The VCLK_periph domain is enabled.
1
The VCLK_periph domain is disabled.
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Table 2-32. Clock Domain Disable Register (CDDIS) Field Descriptions (continued)
Bit
1
0
138
Field
Value
HCLKOFF
Description
HCLK and VCLK_sys domains off.
0
The HCLK and VCLK_sys domains are enabled.
1
The HCLK and VCLK_sys domains are disabled.
GCLKOFF
GCLK domain off.
0
The GCLK domain is enabled.
1
The GCLK domain is disabled.
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2.5.1.14 Clock Domain Disable Set Register (CDDISSET)
This CDDISSET register, shown in Figure 2-19 and described in Table 2-33, sets clock domains to the
disabled state.
Figure 2-19. Clock Domain Disable Set Register (CDDISSET) [offset = 40h]
31
16
Reserved
R-0
15
11
10
9
8
Reserved
12
SETVCLKA4
OFF
Reserved
Reserved
SETVCLK3
OFF
R-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
7
6
5
4
3
2
1
0
Reserved
SETRTI1CLK
OFF
SETVCLKA2
OFF
SETVCLKA1
OFF
SETVCLK2
OFF
SETVCLKP
OFF
SETHCLK
OFF
SETGCLK
OFF
R/WP-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 2-33. Clock Domain Disable Set Register (CDDISSET) Field Descriptions
Bit
31-12
11
Field
Reserved
Value
0
SETVCLKA4OFF
Description
Reads return 0. Writes have no effect.
Set VCLKA4 domain.
0
Read: The VCLKA4 domain is enabled.
Write: The VCLKA4 domain is unchanged.
1
Read: The VCLKA4 domain is disabled.
Write: The VCLKA4 domain is set to the enabled state.
10
Reserved
0-1
Reads return 0 or 1 and privilege mode writes allowed.
9
Reserved
0-1
Reads return 0 or 1 and privilege mode writes allowed.
8
SETVCLK3OFF
Set VCLK3 domain.
0
Read: The VCLK3 domain is enabled.
Write: The VCLK3 domain is unchanged.
1
Read: The VCLK3 domain is disabled.
Write: The VCLK3 domain is set to the enabled state.
7
Reserved
6
SETRTI1CLKOFF
0-1
Reads return 0 or 1 and privilege mode writes allowed.
Set RTICLK1 domain.
0
Read: The RTICLK1 domain is enabled.
Write: The RTICLK1 domain is unchanged.
1
Read: The RTICLK1 domain is disabled.
Write: The RTICLK1 domain is set to the enabled state.
5
SETVCLKA2OFF
Set VCLKA2 domain.
0
Read: The VCLKA2 domain is enabled.
Write: The VCLKA2 domain is unchanged.
1
Read: The VCLKA2 domain is disabled.
Write: The VCLKA2 domain is set to the enabled state.
4
SETVCLKA1OFF
Set VCLKA1 domain.
0
Read: The VCLKA1 domain is enabled.
Write: The VCLKA1 domain is unchanged.
1
Read: The VCLKA1 domain is disabled.
Write: The VCLKA1 domain is set to the enabled state.
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Table 2-33. Clock Domain Disable Set Register (CDDISSET) Field Descriptions (continued)
Bit
Field
3
Value
SETVCLK2OFF
Description
Set VCLK2 domain.
0
Read: The VCLK2 domain is enabled.
Write: The VCLK2 domain is unchanged.
1
Read: The VCLK2 domain is disabled.
Write: The VCLK2 domain is set to the enabled state.
2
SETVCLKPOFF
Set VCLK_periph domain.
0
Read: The VCLK_periph domain is enabled.
Write: The VCLK_periph domain is unchanged.
1
Read: The VCLK_periph domain is disabled.
Write: The VCLK_periph domain is set to the enabled state.
1
SETHCLKOFF
Set HCLK and VCLK_sys domains.
0
Read: The HCLK and VCLK_sys domain is enabled.
Write: The HCLK and VCLK_sys domain is unchanged.
1
Read: The HCLK and VCLK_sys domain is disabled.
Write: The HCLK and VCLK_sys domain is set to the enabled state.
0
SETGCLKOFF
Set GCLK domain.
0
Read: The GCLK domain is enabled.
Write: The GCLK domain is unchanged.
1
Read: The GCLK domain is disabled.
Write: The GCLK domain is set to the enabled state.
2.5.1.15 Clock Domain Disable Clear Register (CDDISCLR)
The CDDISCLR register, shown in Figure 2-20 and described in Table 2-34, clears clock domains to the
enabled state.
Figure 2-20. Clock Domain Disable Clear Register (CDDISCLR) [offset = 44h]
31
16
Reserved
R-0
15
11
10
9
8
Reserved
12
CLRVCLKA4
OFF
Reserved
Reserved
CLRVCLK3
OFF
R-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
7
6
5
4
3
2
1
0
Reserved
CLRRTI1CLK
OFF
CLRVCLKA2
OFF
CLRVCLKA1
OFF
CLRVCLK2
OFF
CLRVCLKP
OFF
CLRHCLK
OFF
CLRGCLK
OFF
R/WP-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; R = Read only; WP = Write in privileged mode only; -n = value after reset
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Table 2-34. Clock Domain Disable Clear Register (CDDISCLR) Field Descriptions
Bit
31-12
11
Field
Reserved
Value
0
CLRVCLKA4OFF
Description
Reads return 0. Writes have no effect.
Clear VCLKA4 domain.
0
Read: The VCLKA4 domain is enabled.
Write: The VCLKA4 domain is unchanged.
1
Read: The VCLKA4 domain is disabled.
Write: The VCLKA4 domain is cleared to the enabled state.
10
Reserved
0-1
Reads return 0 or 1 and privilege mode writes allowed.
9
Reserved
0-1
Reads return 0 or 1 and privilege mode writes allowed.
8
CLRVCLK3OFF
Clear VCLK3 domain.
0
Read: The VCLK3 domain is enabled.
Write: The VCLK3 domain is unchanged.
1
Read: The VCLK3 domain is disabled.
Write: The VCLK3 domain is cleared to the enabled state.
7
Reserved
6
CLRRTI1CLKOFF
0-1
Reads return 0 or 1 and privilege mode writes allowed.
Clear RTICLK1 domain.
0
Read: The RTICLK1 domain is enabled.
Write: The RTICLK1 domain is unchanged.
1
Read: The RTICLK1 domain is disabled.
Write: The RTICLK1 domain is cleared to the enabled state.
5
CLRVCLKA2OFF
Clear VCLKA2 domain.
0
Read: The VCLKA2 domain is enabled.
Write: The VCLKA2 domain is unchanged.
1
Read: The VCLKA2 domain is disabled.
Write: The VCLKA2 domain is cleared to the enabled state.
4
CLRVCLKA1OFF
Clear VCLKA1 domain.
0
Read: The VCLKA1 domain is enabled.
Write: The VCLKA1 domain is unchanged.
1
Read: The VCLKA1 domain is disabled.
Write: The VCLKA1 domain is cleared to the enabled state.
3
CLRVCLK2OFF
Clear VCLK2 domain.
0
Read: The VCLK2 domain is enabled.
Write: The VCLK2 domain is unchanged.
1
Read: The VCLK2 domain is disabled.
Write: The VCLK2 domain is cleared to the enabled state.
2
CLRVCLKPOFF
Clear VCLK_periph domain.
0
Read: The VCLK_periph domain is enabled.
Write: The VCLK_periph domain is unchanged.
1
Read: The VCLK_periph domain is disabled.
Write: The VCLK_periph domain is cleared to the enabled state.
1
CLRHCLKOFF
Clear HCLK and VCLK_sys domains.
0
Read: The HCLK and VCLK_sys domain is enabled.
Write: The HCLK and VCLK_sys domain is unchanged.
1
Read: The HCLK and VCLK_sys domain is disabled.
Write: The HCLK and VCLK_sys domain is cleared to the enabled state.
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Table 2-34. Clock Domain Disable Clear Register (CDDISCLR) Field Descriptions (continued)
Bit
0
Field
Value
CLRGCLKOFF
Description
Clear GCLK domain.
0
Read: The GCLK domain is enabled.
Write: The GCLK domain is unchanged.
1
Read: The GCLK domain is disabled.
Write: The GCLK domain is cleared to the enabled state.
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2.5.1.16 GCLK, HCLK, VCLK, and VCLK2 Source Register (GHVSRC)
The GHVSRC register, shown in Figure 2-21 and described in Table 2-35, controls the clock source
configuration for the GCLK, HCLK, VCLK and VCLK2 clock domains.
Figure 2-21. GCLK, HCLK, VCLK, and VCLK2 Source Register (GHVSRC) [offset = 48h]
31
28
27
24
23
20
19
16
Reserved
GHVWAKE
Reserved
HVLPM
R-0
R/WP-0
R-0
R/WP-0
15
4
3
0
Reserved
GHVSRC
R-0
R/WP-0
LEGEND: R = Read only; R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 2-35. GCLK, HCLK, VCLK, and VCLK2 Source Register (GHVSRC) Field Descriptions
Bit
Field
31-28
Reserved
27-24
GHVWAKE
Value
0
Reserved
19-16
HVLPM
GCLK, HCLK, VCLK, VCLK2 source on wakeup.
Clock source0 is the source for GCLK, HCLK, VCLK, VCLK2 on wakeup.
1h
Clock source1 is the source for GCLK, HCLK, VCLK, VCLK2 on wakeup.
2h
Clock source2 is the source for GCLK, HCLK, VCLK, VCLK2 on wakeup.
3h
Clock source3 is the source for GCLK, HCLK, VCLK, VCLK2 on wakeup.
4h
Clock source4 is the source for GCLK, HCLK, VCLK, VCLK2 on wakeup.
5h
Clock source5 is the source for GCLK, HCLK, VCLK, VCLK2 on wakeup.
6h
Clock source6 is the source for GCLK, HCLK, VCLK, VCLK2 on wakeup.
7h
Clock source7 is the source for GCLK, HCLK, VCLK, VCLK2 on wakeup.
0
Reserved
3-0
GHVSRC
Reserved
Reads return 0. Writes have no effect.
HCLK, VCLK, VCLK2 source on wakeup when GCLK is turned off.
0
Clock source0 is the source for HCLK, VCLK, VCLK2 on wakeup.
1h
Clock source1 is the source for HCLK, VCLK, VCLK2 on wakeup.
2h
Clock source2 is the source for HCLK, VCLK, VCLK2 on wakeup.
3h
Clock source3 is the source for HCLK, VCLK, VCLK2 on wakeup.
4h
Clock source4 is the source for HCLK, VCLK, VCLK2 on wakeup.
5h
Clock source5 is the source for HCLK, VCLK, VCLK2 on wakeup.
6h
Clock source6 is the source for HCLK, VCLK, VCLK2 on wakeup.
7h
Clock source7 is the source for HCLK, VCLK, VCLK2 on wakeup.
8h-Fh
15-4
Reads return 0. Writes have no effect.
0
8h-Fh
23-20
Description
0
Reserved
Reads return 0. Writes have no effect.
GCLK, HCLK, VCLK, VCLK2 current source.
Note: The GHVSRC[3-0] bits are updated with the HVLPM[3-0] setting when GCLK is turned
off, and are updated with the GHVWAKE[3-0] setting on system wakeup.
0
Clock source0 is the source for GCLK, HCLK, VCLK, VCLK2.
1h
Clock source1 is the source for GCLK, HCLK, VCLK, VCLK2.
2h
Clock source2 is the source for GCLK, HCLK, VCLK, VCLK2.
3h
Clock source3 is the source for GCLK, HCLK, VCLK, VCLK2.
4h
Clock source4 is the source for GCLK, HCLK, VCLK, VCLK2.
5h
Clock source5 is the source for GCLK, HCLK, VCLK, VCLK2.
6h
Clock source6 is the source for GCLK, HCLK, VCLK, VCLK2.
7h
Clock source7 is the source for GCLK, HCLK, VCLK, VCLK2.
8h-Fh
Reserved
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NOTE: Non implemented clock sources should not be enabled or used. A list of the available clock
sources is shown in Table 2-29.
2.5.1.17 Peripheral Asynchronous Clock Source Register (VCLKASRC)
The VCLKASRC register, shown in Figure 2-22 and described in Table 2-36, sets the clock source for the
asynchronous peripheral clock domains to be configured to run from a specific clock source.
Figure 2-22. Peripheral Asynchronous Clock Source Register (VCLKASRC) [offset = 4Ch]
31
16
Reserved
R-0
15
12
11
8
7
4
3
0
Reserved
VCLKA2S
Reserved
VCLKA1S
R-0
R/WP-9h
R-0
R/WP-9h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 2-36. Peripheral Asynchronous Clock Source Register (VCLKASRC) Field Descriptions
Bit
Field
31-12
Reserved
11-8
VCLKA2S
Value
0
Reserved
3-0
VCLKA1S
Reads return 0. Writes have no effect.
Peripheral asynchronous clock2 source.
0
Clock source0 is the source for peripheral asynchronous clock2.
1h
Clock source1 is the source for peripheral asynchronous clock2.
2h
Clock source2 is the source for peripheral asynchronous clock2.
3h
Clock source3 is the source for peripheral asynchronous clock2.
4h
Clock source4 is the source for peripheral asynchronous clock2.
5h
Clock source5 is the source for peripheral asynchronous clock2.
6h
Clock source6 is the source for peripheral asynchronous clock2.
7h
Clock source7 is the source for peripheral asynchronous clock2.
8h-Fh
7-4
Description
0
VCLK is the source for peripheral asynchronous clock2.
Reads return 0. Writes have no effect.
Peripheral asynchronous clock1 source.
0
Clock source0 is the source for peripheral asynchronous clock1.
1h
Clock source1 is the source for peripheral asynchronous clock1.
2h
Clock source2 is the source for peripheral asynchronous clock1.
3h
Clock source3 is the source for peripheral asynchronous clock1.
4h
Clock source4 is the source for peripheral asynchronous clock1.
5h
Clock source5 is the source for peripheral asynchronous clock1.
6h
Clock source6 is the source for peripheral asynchronous clock1.
7h
Clock source7 is the source for peripheral asynchronous clock1.
8h-Fh
VCLK is the source for peripheral asynchronous clock1.
NOTE: Non implemented clock sources should not be enabled or used. A list of the available clock
sources is shown in Table 2-29.
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2.5.1.18 RTI Clock Source Register (RCLKSRC)
The RCLKSRC register, shown in Figure 2-23 and described in Table 2-37, controls the RTI (Real Time
Interrupt) clock source selection.
NOTE: Important constraint when the RTI clock source is not VCLK
If the RTIx clock source is chosen to be anything other than the default VCLK, then the RTI
clock needs to be at least three times slower than the VCLK. This can be achieved by
configuring the RTIxCLK divider in this register. This divider is internally bypassed when the
RTIx clock source is VCLK.
Figure 2-23. RTI Clock Source Register (RCLKSRC) [offset = 50h]
31
26
25
24
23
20
19
16
Reserved
Reserved
Reserved
Reserved
R-0
R/WP-1h
R-0
R/WP-9h
15
10
9
8
7
4
3
0
Reserved
RTI1DIV
Reserved
RTI1SRC
R-0
R/WP-1h
R-0
R/WP-9h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 2-37. RTI Clock Source Register (RCLKSRC) Field Descriptions
Bit
Field
Value
Description
31-26
Reserved
0
Reads return 0. Writes have no effect.
25-24
Reserved
0
Reads return value and privilege mode writes allowed.
23-20
Reserved
0
Reads return 0. Writes have no effect.
19-16
Reserved
0
Reads return value and privilege mode writes allowed.
15-10
Reserved
0
Reads return 0. Writes have no effect.
9-8
RTI1DIV
7-4
Reserved
3-0
RTI1SRC
RTI clock1 Divider.
0
RTICLK1 divider value is 1.
1h
RTICLK1 divider value is 2.
2h
RTICLK1 divider value is 4.
3h
RTICLK1 divider value is 8.
0
Reads return 0. Writes have no effect.
RTI clock1 source.
0
Clock source0 is the source for RTICLK1.
1h
Clock source1 is the source for RTICLK1.
2h
Clock source2 is the source for RTICLK1.
3h
Clock source3 is the source for RTICLK1.
4h
Clock source4 is the source for RTICLK1.
5h
Clock source5 is the source for RTICLK1.
6h
Clock source6 is the source for RTICLK1.
7h
Clock source7 is the source for RTICLK1.
8h-Fh
VCLK is the source for RTICLK1.
NOTE: A list of the available clock sources is shown in Table 2-29.
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2.5.1.19 Clock Source Valid Status Register (CSVSTAT)
The CSVSTAT register, shown in Figure 2-24 and described in Table 2-38, indicates the status of usable
clock sources.
Figure 2-24. Clock Source Valid Status Register (CSVSTAT) [offset = 54h]
31
8
Reserved
R-0
7
6
5
4
3
2
1
0
CLKSR7V
CLKSR6V
CLKSR5V
CLKSR4V
CLKSR3V
Reserved
CLKSR1V
CLKSR0V
R-1
R-0
R-0
R-1
R-1
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 2-38. Clock Source Valid Register (CSVSTAT) Field Descriptions
Bit
Field
31-8
Reserved.
7-3
CLKSR[7-3]V
Value
0
Description
Reads return 0. Writes have no effect.
Clock source[7-3] valid.
0
Clock source[7-3] is not valid.
1
Clock source[7-3] is valid.
Note: If the valid bit of the source of a clock domain is not set (that is, the clock source is
not fully stable), the respective clock domain is disabled by the Global Clock Module (GCM).
2
1-0
Reserved.
0
CLKSR[1-0]V
Reads return 0. Writes have no effect.
Clock source[1-0] valid.
0
Clock source[1-0] is not valid.
1
Clock source[1-0] is valid.
Note: If the valid bit of the source of a clock domain is not set (that is, the clock source is
not fully stable), the respective clock domain is disabled.
NOTE: A list of the available clock sources is shown in Table 2-29.
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2.5.1.20 Memory Self-Test Global Control Register (MSTGCR)
The MSTGCR register, shown in Figure 2-25 and described in Table 2-39, controls several aspects of the
PBIST (Programmable Built-In Self Test) memory controller.
Figure 2-25. Memory Self-Test Global Control Register (MSTGCR) [offset = 58h]
31
16
Reserved
R-0
15
10
9
8
7
4
3
0
Reserved
ROM_DIV
Reserved
MSTGENA
R-0
R/WP-0
R-0
R/WP-5h
LEGEND: R = Read only; R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 2-39. Memory Self-Test Global Control Register (MSTGCR) Field Descriptions
Bit
Field
31-10
Reserved
9-8
ROM_DIV
7-4
Reserved
3-0
MSTGENA
Value
0
Description
Reads return 0. Writes have no effect.
Prescaler divider bits for ROM clock source.
0
ROM clock source is HCLK divided by 1. PBIST will reset for 16 VBUS cycles.
1h
ROM clock source is HCLK divided by 2. PBIST will reset for 32 VBUS cycles.
2h
ROM clock source is HCLK divided by 4. PBIST will reset for 64 VBUS cycles.
3h
ROM clock source is HCLK divided by 8. PBIST will reset for 96 VBUS cycles.
0
Reads return 0. Writes have no effect.
Memory self-test controller global enable key
Note: Enabling the MSTGENA key will generate a reset to the state machine of the
selected PBIST controller.
Ah
Memory self-test controller is enabled.
All other values
Memory self-test controller is disabled.
Note: It is recommended that a value of 0101b be used to disable the memory self-test
controller. This value will give maximum protection from a bit flip inducing event that
would inadvertently enable the controller.
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2.5.1.21 Memory Hardware Initialization Global Control Register (MINITGCR)
The MINITGCR register, shown in Figure 2-26 and described in Table 2-40, enables automatic hardware
memory initialization.
Figure 2-26. Memory Hardware Initialization Global Control Register (MINITGCR) [offset = 5Ch]
31
16
Reserved
R-0
15
4
3
0
Reserved
MINITGENA
R-0
R/WP-5h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 2-40. Memory Hardware Initialization Global Control Register (MINITGCR) Field Descriptions
Bit
Field
31-4
Reserved
3-0
MINITGENA
Value
0
Description
Reads return 0. Writes have no effect.
Memory hardware initialization global enable key.
Ah
Global memory hardware initialization is enabled.
All other values
Global memory hardware initialization is disabled.
Note: It is recommended that a value of 5h be used to disable memory hardware
initialization. This value will give maximum protection from an event that would
inadvertently enable the controller.
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2.5.1.22 MBIST Controller/ Memory Initialization Enable Register (MSINENA)
The MSINENA register, shown in Figure 2-27 and described in Table 2-41, enables PBIST controllers for
memory self test and the memory modules initialized during automatic hardware memory initialization.
Figure 2-27. MBIST Controller/Memory Initialization Enable Register (MSINENA) [offset = 60h]
31
0
MSIENA
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 2-41. MBIST Controller/Memory Initialization Enable Register (MSINENA) Field Descriptions
Bit
31-0
Field
Value
MSIENA
Description
PBIST controller and memory initialization enable register. In memory self-test mode, all the
corresponding bits of the memories to be tested should be set before enabling the global memory selftest controller key (MSTGENA) in the MSTGCR register (offset 58h). The reason for this is that
MSTGENA, in addition to being the global enable for all individual PBIST controllers, is the source for
the reset generation to all the PBIST controller state machines. Disabling the MSTGENA or
MINITGENA key (by writing from Ah to any other value) will reset all the MSIENA [31-0] bits to their
default values.
0
In memory self-test mode (MSTGENA = Ah):
PBIST controller [31-0] is disabled.
In memory Initialization mode (MINITGENA = Ah):
Memory module [31-0] auto hardware initialization is disabled.
1
In memory self-test mode (MSTGENA = Ah):
PBIST controller [31-0] is enabled.
In memory Initialization mode (MINITGENA = Ah):
Memory module [31-0] auto hardware initialization is enabled.
Note: Software should ensure that both the memory self-test global enable key (MSTGENA) and
the memory hardware initialization global key (MINITGENA) are not enabled at the same time.
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2.5.1.23 MSTC Global Status Register (MSTCGSTAT)
The MSTCGSTAT register, shown in Figure 2-28 and described in Table 2-42, shows the status of the
memory hardware initialization and the memory seft-test.
Figure 2-28. MSTC Global Status Register (MSTCGSTAT) [offset = 68h]
31
16
Reserved
R-0
15
9
Reserved
8
7
MINIDONE
R-0
1
Reserved
R/WPC-0
0
MSTDONE
R-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; C = Clear; WP = Write in privileged mode only; -n = value after reset
Table 2-42. MSTC Global Status Register (MSTCGSTAT) Field Descriptions
Bit
31-9
8
Field
Reserved
Value
0
MINIDONE
Description
Reads return 0. Writes have no effect.
Memory hardware initialization complete status.
Note: Disabling the MINITGENA key (by writing from Ah to any other value) will clear the
MINIDONE status bit to 0.
Note: Individual memory initialization status is shown in the MINISTAT register.
0
Read: Memory hardware initialization is not complete for all memory.
Write: A write of 0 has no effect.
1
Read: Hardware initialization of all memory is completed.
Write: The bit is cleared to 0.
7-1
0
Reserved
0
MSTDONE
Reads return 0. Writes have no effect.
Memory self-test run complete status.
Note: Disabling the MSTGENA key (by writing from Ah to any other value) will clear the
MSTDONE status bit to 0.
0
Read: Memory self-test is not completed.
Write: A write of 0 has no effect.
1
Read: Memory self-test is completed.
Write: The bit is cleared to 0.
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2.5.1.24 Memory Hardware Initialization Status Register (MINISTAT)
The MINISTAT register, shown in Figure 2-29 and described in Table 2-43, indicates the status of
hardware memory initialization.
Figure 2-29. Memory Hardware Initialization Status Register (MINISTAT) [offset = 6Ch]
31
0
MIDONE
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 2-43. Memory Hardware Initialization Status Register (MINISTAT) Field Descriptions
Bit
Field
31-0
Value
MIDONE
Description
Memory hardware initialization status bit.
0
Read: Memory module[31-0] hardware initialization is not completed.
Write: A write of 0 has no effect.
1
Read: Memory module[31-0] hardware initialization is completed.
Write: The bit is cleared to 0.
Note: Disabling the MINITGENA key (by writing from Ah to any other value) will reset all the
individual status bits to 0.
2.5.1.25 PLL Control Register 1 (PLLCTL1)
The PLLCTL1 register, shown in Figure 2-30 and described in Table 2-44, controls the output frequency of
PLL1 (Clock Source 1 - FMzPLL). It also controls the behavior of the device if a PLL slip or oscillator
failure is detected.
Figure 2-30. PLL Control Register 1 (PLLCTL1) [offset = 70h]
31
30
29
28
24
ROS
MASK_SLIP
PLLDIV
R/WP-0
R/WP-1h
R/WP-Fh
23
22
21
16
ROF
Reserved
REFCLKDIV
R/WP-0
R-0
R/WP-2h
15
0
PLLMUL
R/WP-5F00h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
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Table 2-44. PLL Control Register 1 (PLLCTL1) Field Descriptions
Bit
Field
31
ROS
Value
Description
Reset on PLL Slip
0
Do not reset system when PLL slip is detected.
1
Reset when PLL slip is detected.
Note: MASK_SLIP (Bits 30-29) must also be enabled for ROS to be enabled.
30-29
MASK_SLIP
Mask detection of PLL slip
2h
Others
Bypass on PLL Slip is disabled. If a PLL Slip is detected no action is taken.
Bypass on PLL Slip is enabled. If a PLL Slip is detected the device will automatically bypass the
PLL and use the oscillator to provide the device clock.
Note: If ROS (Bit 31) is set to 1, the device will be reset if a PLL Slip and the PLL will be
bypassed after the reset occurs.
28-24
PLLDIV
PLL Output Clock Divider
R = PLLDIV + 1
f PLL CLK= f post_ODCLK / R
0
f PLL CLK= f post-ODCLK / 1
1h
f PLL CLK= f post-ODCLK / 2
:
1Fh
23
ROF
22
Reserved
21-16
:
f PLL CLK= f post-ODCLK / 32
Reset on Oscillator Fail
0
Do not reset system when oscillator is out of range.
1
Reset system when oscillator is out of range.
0
Value has no effect on PLL operation.
REFCLKDIV
Reference Clock Divider
NR = REFCLKDIV + 1
f INT CLK= f OSCIN / NR
0
f INT CLK= f OSCIN / 1
1h
f INT CLK= f OSCIN / 2
:
3Fh
15-0
PLLMUL
:
f INT CLK= f OSCIN / 64
PLL Multiplication Factor
NF = (PLLMUL / 256) + 1, valid multiplication factors are from 1 to 256.
f VCO CLK= f INT CLK x NF
0h
f VCO CLK= f INT CLK x 1
100h
f VCO CLK= f INT CLK x 2
:
f VCO CLK= f INT CLK x 92
5C00h
f VCO CLK= f INT CLK x 93
:
FF00h
152
:
5B00h
:
f VCO CLK= f INT CLK x 256
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2.5.1.26 PLL Control Register 2 (PLLCTL2)
The PLLCTL2 register, shown in Figure 2-31 and described in Table 2-45, controls the modulation
characteristics and the output divider of the PLL.
Figure 2-31. PLL Control Register 2 (PLLCTL2) [offset = 74h]
31
30
22
FMENA
SPREADINGRATE
R/WP-0
R/WP-1FFh
15
12
11
9
21
20
16
Rsvd
MULMOD
R-0
R/WP-0
8
0
MULMOD
ODPLL
SPR_AMOUNT
R/WP-7h
R/WP-1h
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 2-45. PLL Control Register 2 (PLLCTL2) Field Descriptions
Bit
Field
31
FMENA
30-22
Value
Frequency Modulation Enable.
0
Disable frequency modulation.
1
Enable frequency modulation.
SPREADINGRATE
NS = SPREADINGRATE + 1
f mod= f s= f INT CLK/(2 × NS)
0
f mod= f s= f INT CLK / (2 × 1)
1h
f mod= f s= f INT CLK / (2 × 2)
:
1FFh
21
Reserved
20-12
MULMOD
Description
0
:
f mod= f s= f INT CLK / (2 × 512)
Value has no effect on PLL operation.
Multiplier Correction when Frequency Modulation is enabled.
When FMENA = 0, MUL_when_MOD = 0; when FMENA = 1, MUL_when_MOD =
(MULMOD / 256)
0
No adder to NF
8h
MUL_when_MOD = 8/256
9h
MUL_when_MOD = 9/256
:
1FFh
11-9
ODPLL
:
MUL_when_MOD = 511/256
Internal PLL Output Divider.
OD = ODPLL + 1
f post-ODCLK= f VCO CLK/OD
0
f post-ODCLK= f VCO CLK / 1
1h
f post-ODCLK= f VCO CLK / 2
:
7h
:
f post-ODCLK= f VCO CLK / 8
Note: PLL output clock is gated off, if ODPLL is changed while the PLL is active.
8-0
SPR_AMOUNT
Spreading Amount.
NV = (SPR_AMOUNT + 1)/2048
NV ranges from 1/2048 to 512/2048
Note that the PLL output clock is disabled for 1 modulation period, if the SPR_AMOUNT
field is changed while the frequency modulation is enabled. If frequency modulation is
disabled and SPR_AMOUNT is changed, there is no effect on the PLL output clock.
0
NV = 1/2048
1h
NV = 2/2048
:
1FFh
:
NV = 512/2048
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2.5.1.27 SYS Pin Control Register 10 (SYSPC10)
The SYSPC10 register, shown in Figure 2-32 and described in Table 2-46, controls the function of the
ECPCLK slew mode.
Figure 2-32. SYS Pin Control Register 10 (SYSPC10) [offset = 78h]
31
16
Reserved
R-0
15
1
0
Reserved
ECPCLK_SLEW
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 2-46. SYS Pin Control Register 10 (SYSPC10) Field Descriptions
Bit
31-1
0
154
Field
Reserved
Value
0
ECPCLK_SLEW
Description
Reads return 0. Writes have no effect.
ECPCLK slew control. This bit controls between the fast or slow slew mode.
0
Fast mode is enabled; the normal output buffer is used for this pin.
1
Slow mode is enabled; slew rate control is used for this pin.
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2.5.1.28 Die Identification Register Lower Word (DIEIDL)
The DIEIDL register, shown in Figure 2-33 and described in Table 2-47, contains information about the die
wafer number, and X, Y wafer coordinates.
Figure 2-33. Die Identification Register, Lower Word (DIEIDL) [offset = 7Ch]
31
24
15
23
16
WAFER #
Y WAFER COORDINATE
R-D
R-D
12
11
0
Y WAFER COORDINATE
X WAFER COORDINATE
R-D
R-D
LEGEND: R = Read only; -n = value after reset; D = value is device specific
Table 2-47. Die Identification Register, Lower Word (DIEIDL) Field Descriptions
Bit
Field
Description
31-24
WAFER #
These read-only bits contain the wafer number of the device.
23-12
Y WAFER COORDINATE
These read-only bits contain the Y wafer coordinate of the device.
11-0
X WAFER COORDINATE
These read-only bits contain the X wafer coordinate of the device.
NOTE: Die Identification Information
The die identification information will vary from unit to unit. This information is programmed
by TI as part of the initial device test procedure.
2.5.1.29 Die Identification Register Upper Word (DIEIDH)
The DIEIDH register, shown in Figure 2-34 and described in Table 2-48, contains information about the
die lot number.
Figure 2-34. Die Identification Register, Upper Word (DIEIDH) [offset = 80h]
31
24
23
16
Reserved
LOT #
R-0
R-D
15
0
LOT #
R-D
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; D = value is device dependent
Table 2-48. Die Identification Register, Upper Word (DIEIDH) Field Descriptions
Bit
Field
Description
31-24
Reserved
Reserved for TI use. Writes have no effect.
23-0
LOT #
This read-only register contains the device lot number.
NOTE: Die Identification Information
The die identification information will vary from unit to unit. This information is programmed
by TI as part of the initial device test procedure.
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2.5.1.30 LPO/Clock Monitor Control Register (LPOMONCTL)
The LPOMONCTL register, shown in Figure 2-35 and described in Table 2-49, controls the Low
Frequency (Clock Source 4) and High Frequency (Clock Source 5) Low Power Oscillator's trim values.
Figure 2-35. LPO/Clock Monitor Control Register (LPOMONCTL) [offset = 88h]
31
25
15
24
23
17
16
Reserved
BIAS ENABLE
Reserved
OSCFRQCONFIGCNT
R-0
R/WP-1
R-0
R/WP-0
13
12
8
7
5
4
0
Reserved
HFTRIM
Reserved
LFTRIM
R-0
R/WP-10h
R-0
R/WP-10h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 2-49. LPO/Clock Monitor Control Register (LPOMONCTL) Field Descriptions
Bit
Field
31-25 Reserved
24
0
BIAS ENABLE
23-17 Reserved
16
Value
Description
Reads return 0. Writes have no effect.
Bias enable.
0
The bias circuit inside the low-power oscillator (LPO) is disabled.
1
The bias circuit inside LPO is enabled.
0
Reads return 0. Writes have no effect.
OSCFRQCONFIGCNT
Configures the counter based on OSC frequency.
0
Read: OSC freq is ≤ 20MHz
Write: A write of 0 has no effect.
1
Read: OSC freq is > 20MHz and ≤ 80MHz
Write: A write of 1 has no effect.
15-13 Reserved
156
0
Reads return 0. Writes have no effect.
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Table 2-49. LPO/Clock Monitor Control Register (LPOMONCTL) Field Descriptions (continued)
Bit
12-8
Field
Value
HFTRIM
Description
High-frequency oscillator trim value. This five-bit value is used to center the HF oscillator's
frequency.
Caution: This value should only be changed when the HF oscillator is not the
source for a clock domain; otherwise, a system failure could result.
The following values are the ratio: f / fo in the F021 process.
7-5
Reserved
0
29.52
1h
34.24%
2h
38.85%
3h
43.45%
4h
47.99%
5h
52.55%
6h
57.02%
7h
61.46%
8h
65.92%
9h
70.17
Ah
74.55%
Bh
78.92%
Ch
83.17%
Dh
87.43%
Eh
91.75%
Fh
95.89%
10h
100.00% Default at Reset.
11h
104.09
12h
108.17
13h
112.32
14h
116.41
15h
120.67
16h
124.42
17h
128.38
18h
132.24
19h
136.15
1Ah
140.15
1Bh
143.94
1Ch
148.02
1Dh
151.80x
1Eh
155.50x
1Fh
159.35%
0
Reads return 0. Writes have no effect.
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Table 2-49. LPO/Clock Monitor Control Register (LPOMONCTL) Field Descriptions (continued)
Bit
Field
4-0
LFTRIM
Value
Description
Low-frequency oscillator trim value. This five-bit value is used to center the LF oscillator's
frequency.
Caution: This value should only be changed when the LF oscillator is not the
source for a clock domain; otherwise, a system failure could result.
The following values are the ratio: f / fo in the F021 process.
158
0
20.67
1h
25.76
2h
30.84
3h
35.90
4h
40.93
5h
45.95
6h
50.97
7h
55.91
8h
60.86
9h
65.78
Ah
70.75
Bh
75.63
Ch
80.61
Dh
85.39
Eh
90.23
Fh
95.11
10h
100.00% Default at Reset
11h
104.84
12h
109.51
13h
114.31
14h
119.01
15h
123.75
16h
128.62
17h
133.31
18h
138.03
19h
142.75
1Ah
147.32
1Bh
152.02
1Ch
156.63
1Dh
161.38
1Eh
165.90
1Fh
170.42
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2.5.1.31 Clock Test Register (CLKTEST)
The CLKTEST register, shown in Figure 2-36 and described in Table 2-50, controls the clock signal that is
supplied to the ECLK pin for test and debug purposes.
NOTE: Clock Test Register Usage
This register should only be used for test and debug purposes.
Figure 2-36. Clock Test Register (CLKTEST) [offset = 8Ch]
31
26
25
24
Reserved
27
ALTLIMPCLOCK
ENABLE
RANGEDET
CTRL
RANGEDET
ENASSEL
R-0
R/WP-0
R/WP-0
R/WP-0
23
20
15
19
16
Reserved
CLK_TEST_EN
R-0
R/WP-Ah
12
11
8
7
4
3
0
Reserved
SEL_GIO_PIN
Reserved
SEL_ECP_PIN
R-0
R/WP-0
R-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 2-50. Clock Test Register (CLKTEST) Field Descriptions
Bit
31-27
26
25
24
Field
Reserved
Value
Description
0
Reads return 0. Writes have no effect.
ALTLIMPCLOCKENABLE
This bit selects a clock driven by the GIOB[0] pin as an alternate limp clock to the clock
monitor phase frequency detect (PFD).
0
The 10-MHz LPO fast clock is the compare clock for the clock detect PFD circuit and the
source to limp clock on a clock fail.
1
The ALTLIMPCLOCK driven on the GIOB[0] pin is the compare clock for the clock detect
PFD circuit and the source to limp clock on a clock fail.
RANGEDETCTRL
Range detection control. This bit's functionality is dependant on the state of the
RANGEDETENSSEL bit (Bit 24) of the CLKTEST register.
0
The clock monitor range detection circuitry (RANGEDETECTENABLE) is disabled.
1
The clock monitor range detection circuitry (RANGEDETECTENABLE) is enabled.
RANGEDETENASSEL
23-20
Reserved
19-16
CLK_TEST_EN
Selects range detection enable. This bit resets asynchronously on power on reset.
0
The range detect enable is generated by the hardware in the clock monitor wrapper.
1
The range detect enable is controlled by the RANGEDETCTRL bit (Bit 25) of the
CLKTEST register.
0
Reads return 0. Writes have no effect.
Clock test enable. This bit enables the clock going to the ECLK pin.
Note: The ECLK pin must also be placed into Functional mode by setting the
ECPCLKFUN bit to 1 in the SYSPC1 register.
15-12
Reserved
5h
Clock going to ECLK pin is enabled.
Others
Clock going to ECLK pin is disabled.
0
Reads return 0. Writes have no effect.
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Table 2-50. Clock Test Register (CLKTEST) Field Descriptions (continued)
Bit
11-8
Field
Value
SEL_GIO_PIN
GIOB[0] pin clock source valid, clock source select
0
Oscillator valid status
1h
PLL1 valid status
2h-4h
Reserved
3-0
SEL_ECP_PIN
Reserved
5h
High-frequency LPO (Low-Power Oscillator) clock valid status
6h
PLL2 valid status
7h
Reserved
8h
Low-frequency LPO (Low-Power Oscillator) clock valid status
9h-Fh
7-4
Description
0
Reserved
Reads return 0. Writes have no effect.
ECLK pin clock source select
Note: Only valid clock sources can be selected for the ECLK pin. Valid clock
sources are displayed by the CSVSTAT register.
0
Oscillator clock
1h
PLL1 clock output
2h
Reserved
3h
EXTCLKIN1
4h
Low-frequency LPO (Low-Power Oscillator) clock
5h
High-frequency LPO (Low-Power Oscillator) clock
6h
PLL2 clock output
7h
EXTCLKIN2
8h
GCLK
9h
RTI Base
Ah
Reserved
Bh
VCLKA1
Ch
VCLKA2
Dh
Reserved
Eh
VCLKA4
Fh
Reserved
NOTE: Nonimplemented clock sources should not be enabled or used.
160
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2.5.1.32 DFT Control Register (DFTCTRLREG)
This register is shown in Figure 2-37 and described in Table 2-51.
Figure 2-37. DFT Control Register (DFTCTRLREG) [offset = 90h]
31
16
Reserved
R-0
15
14
13
12
11
10
9
8
7
4
3
0
Reserved
DFTWRITE
Reserved
DFTREAD
Reserved
TEST_MODE_KEY
R-0
R/WP-2h
R-0
R/WP-2h
R-0
R/WP-5h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 2-51. DFT Control Register (DFTCTRLREG) Field Descriptions
Bit
Field
31-14
Reserved
13-12
DFTWRITE
Value
0
Description
Reads return 0. Writes have no effect.
DFT logic access.
For F021:
DFTWRITE[0] = 0 and DFTREAD[0] = 0 configured in stress mode
DFTWRITE[1] = 0 and DFTREAD[1] = 0 configured in stress mode
DFTWRITE[0] = 0 and DFTREAD[0] = 0 configured in fast mode
DFTWRITE[1] = 1 and DFTREAD[1] = 1 configured in fast mode
DFTWRITE[0] = 1 and DFTREAD[0] = 1 configured in slow mode
DFTWRITE[1] = 0 and DFTREAD[1] = 0 configured in slow mode
DFTWRITE[0] = 1 and DFTREAD[0] = 1 configured in screen mode
DFTWRITE[1] = 1 and DFTREAD[1] = 1 configured in screen mode
11-10
Reserved
9-8
DFTREAD
0
Reads return 0. Writes have no effect.
DFT logic access.
For F021:
DFTWRITE[0] = 0 and DFTREAD[0] = 0 configured in stress mode
DFTWRITE[1] = 0 and DFTREAD[1] = 0 configured in stress mode
DFTWRITE[0] = 0 and DFTREAD[0] = 0 configured in fast mode
DFTWRITE[1] = 1 and DFTREAD[1] = 1 configured in fast mode
DFTWRITE[0] = 1 and DFTREAD[0] = 1 configured in slow mode
DFTWRITE[1] = 0 and DFTREAD[1] = 0 configured in slow mode
DFTWRITE[0] = 1 and DFTREAD[0] = 1 configured in screen mode
DFTWRITE[1] = 1 and DFTREAD[1] = 1 configured in screen mode
7-4
Reserved
3-0
TEST_MODE_KEY
0
Reads return 0. Writes have no effect.
Test mode key. This register is for internal TI use only.
0-Fh
(except Ah)
Register key disable. All bits in this register will maintain their default value and cannot be
written.
Ah
Register key enable. All the bits can be written to only when the key is enabled. On reset,
these bits will be set to 5h.
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2.5.1.33 DFT Control Register 2 (DFTCTRLREG2)
This register is shown in Figure 2-38 and described in Table 2-52.
Figure 2-38. DFT Control Register 2 (DFTCTRLREG2) [offset = 94h]
31
16
IMPDF(27:12)
R/WP-0
15
4
3
0
IMPDF(11:0)
TEST_MODE_KEY
R/WP-0
R/WP-5h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 2-52. DFT Control Register 2 (DFTCTRLREG2) Field Descriptions
Bit
31-4
3-0
Field
Value
IMPDF[27:0]
DFT Implementation defined bits.
0
IMPDF[27:0] - Disabled
1
IMPDF[27:0] - Enabled
TEST_MODE_KEY
Test mode key. This register is for internal TI use only.
0-Fh
(except Ah)
Ah
162
Description
Register key disable. All bits in this register will maintain their default value and cannot be
written.
Register key enable. All the bits can be written to only when the key is enabled.
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2.5.1.34 General Purpose Register (GPREG1)
This register is shown in Figure 2-39 and described in Table 2-53. For information on filtering the RFSLIP,
see Section 2.5.2.5.
Figure 2-39. General Purpose Register (GPREG1) [offset = A0h]
31
30
26
25
20
19
16
EMIF_FUNC
Reserved
PLL1_FBSLIP_FILTER_COUNT
PLL1_FBSLIP_FILTER_KEY
R/WP-0
R-0
R/WP-0
R/WP-5h
15
0
OUTPUT_BUFFER_LOW_EMI_MODE
R/WP-FFFFh
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 2-53. General Purpose Register (GPREG1) Field Descriptions
Bit
Field
Value
Description
31
EMIF_FUNC
0
Enable EMIF functions to be output. EMIF_ADDR[0], EMIF_ADDR[1],
EMIF_ADDR[6], EMIF_ADDR[7], EMIF_ADDR[8], EMIF_BA[1],
EMIF_nCS[0], and EMIF_nCS[3] are multiplexed with N2HET2
signals. By default, these terminals are tri-stated and pulled down.
Any application that requires the EMIF functionality must set the
EMIF_FUNC bit. This allows these 8 EMIF module outputs to be
driven on to the assigned balls.
30-26
Reserved
0
Reads return 0. Writes have no effect.
25-20
PLL1_FBSLIP_FILTER_ COUNT
FBSLIP down counter programmed value.
Configures the system response when a FBSLIP is indicated by the
PLL macro. When PLL1_FBSLIP_FILTER_KEY is not Ah, the down
counter counts from the programmed value on every LPO highfrequency clock once PLL macro indicates FBSLIP. When the count
reaches 0, if the synchronized FBSLIP signal is still high, an FBSLIP
condition is indicated to the system module and is captured in the
global status register. When the FBSLIP signal from the PLL macro is
de-asserted before the count reaches 0, the counter is reloaded with
the programmed value.
On reset, counter value is 0. Counter must be programmed to a nonzero value and enabled for the filtering to be enabled.
0
Filtering is disabled.
1h
Filtering is enabled. Every slip is recognized.
2h
Filtering is enabled. The slip must be at least 2 HF LPO cycles wide
in order to be recognized as a slip.
:
3Fh
19-16
PLL1_FBSLIP_FILTER_ KEY
Filtering is enabled. The slip must be at least 63 HF LPO cycles wide
in order to be recognized as a slip.
Enable the FBSLIP filtering.
5h
On reset, the FBSLIP filter is disabled and the FBSLIP passes
through.
Fh
This is an unsupported value. You should avoid writing this value to
this bit field.
All other
values
FBSLIP filtering is enabled. Recommended to program Ah in this bit
field. Enabling of the FBSLIP occurs when the KEY is programmed
and a non-zero value is present in the COUNT field.
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Table 2-53. General Purpose Register (GPREG1) Field Descriptions (continued)
Bit
15-0
Field
Value
OUTPUT_BUFFER_LOW_EMI_MODE
Description
Control field for the low-EMI mode of output buffers for
module/signals:
bit[0] controls MiBSPI1
bit[1] controls SPI2
bit[2] controls MiBSPI3
bit[3] controls SPI4
bit[4] controls MiBSPI5
bit[5] controls FlexRay
bit[6] controls EMIF
bit[7] controls ETM
bit[8] controls signal TMS
bit[9] controls signal TDI
bit[10] controls signal TDO
bit[11] controls signal RTCK
bit[12] controls signal TEST
bit[13] controls signal nERROR
bit[14] controls signal ADEVT
bit[15] controls signal RTP
0
Enable EMI mode for each connected output buffers.
1h-FFFEh Enable/Disable EMI mode for connected output buffers.
FFFFh
164
Disable EMI mode for each connected output buffer.
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2.5.1.35 Imprecise Fault Status Register (IMPFASTS)
The IMPFASTS register, shown in Figure 2-40 and described in Table 2-54, displays information about
imprecise aborts that have occurred.
Figure 2-40. Imprecise Fault Status Register (IMPFASTS) [offset = A8h]
31
24
23
16
Reserved
MASTERID
R-0
R-0
15
10
9
8
Reserved
11
EMIFA
NCBA
VBUSA
7
Reserved
1
ATYPE
0
R-0
R-0
R-0
R-0
R-0
R/WC-0
LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset
Table 2-54. Imprecise Fault Status Register (IMPFASTS) Field Descriptions
Bit
Field
31-24
Reserved
23-16
MASTERID
Value
0
0-FFh
Description
Reads return 0. Writes have no effect.
Master ID. This register indicates which master is responsible for the imprecise abort. The master ID
value depends on device implementation, see Table 2-2 for MASTERID values for each bus master.
Notes:
• These bits are only updated when an imprecise abort occurs
• These bits are cleared to 0 only on power-on reset. The value of these bits remains unchanged after
all other resets.
15-11
10
Reserved
0
EMIFA
Reads return 0. Writes have no effect.
EMIF imprecise abort. This register indicates the imprecise abort was generated writing into the EMIF.
Notes:
• This bit is only updated when an imprecise abort occurs
• This bit is cleared to 0 only on power-on reset. The value of this register remains unchanged after all
other resets.
9
0
EMIF did not generate the last imprecise abort.
1
EMIF was written with an illegal address and generated an imprecise abort.
NCBA
Non-cacheable, bufferable abort (NCBA). This register indicates the imprecise abort was generated by
a non-cacheable, bufferable write or shared device write through the write buffer of the CPU.
Notes:
• This bit is only updated when an imprecise abort generated by a non-cacheable, bufferable write or
shared device write occurs.
• This bit is cleared to 0 only on power-on reset. The value of this register remains unchanged after all
other resets.
8
0
A NCBA is not responsible for the last imprecise abort.
1
A NCBA was written with an illegal address and generated an imprecise abort.
VBUSA
VBUS abort. This register indicates the imprecise abort was generated when writing into the peripheral
frame.
Notes:
• This bit is only updated when an imprecise abort is generated when writing into the peripheral frame
• This bit is cleared to 0 only on power-on reset. The value of this register remains unchanged after all
other resets.
7-1
Reserved
0
The peripheral frame did not generate the last imprecise abort.
1
The peripheral frame was written with an illegal address and generated an imprecise abort.
0
Reads return 0. Writes have no effect.
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Table 2-54. Imprecise Fault Status Register (IMPFASTS) Field Descriptions (continued)
Bit
0
Field
Value
ATYPE
Description
Abort type. This bit indicates to the CPU whether the last abort was an imprecise abort or a precise
abort.
Notes:
• This bit is updated after each abort is generated to the CPU.
• This bit is cleared on CPU read.
• This bit is cleared to 0 only on power-on reset. The value of this bit remains unchanged after all other
resets
0
The last abort generated was a precise abort. MASTERID, VBUSA, NCBA, EMIFA and IMPFTADD
were not updated.
1
The last abort generated was an imprecise abort. MASTERID, VBUSA, NCBA, EMIFA and IMPFTADD
were updated.
Note: Once ATYPE is set, the IMPFAWADD and IMPFASTS bits are not updated by subsequent
ABORT signals.
NOTE: The DMA, DMM, and the peripheral master port will also generate an imprecise abort to the
CPU when writing to the peripheral region or to the EMIF region. This will be indicated in the
Master ID field of this register.
2.5.1.36 Imprecise Fault Address Register (IMPFTADD)
This IMPFTADD register, shown in Figure 2-41 and described in Table 2-55, shows the address at which
an imprecise abort occurred.
Figure 2-41. Imprecise Fault Write Address Register (IMPFTADD) [offset = ACh]
31
0
IMPFTADD
R-0
LEGEND: R = Read only; -n = value after reset
Table 2-55. Imprecise Fault Write Address Register (IMPFTADD) Field Descriptions
Bit
31-0
Field
IMPFTADD
Value
0-FFFF FFFFh
Description
These bits contain the fault address when an imprecise abort occurs.
Note: These bits are only updated when an imprecise abort occurs.
Note: These bits are cleared to 0 only on power-on reset. The value of this register
remains unchanged after all other resets.
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2.5.1.37 System Software Interrupt Request 1 Register (SSIR1)
The SSIR1 register, shown in Figure 2-42 and described in Table 2-56, is used for software interrupt
generation.
Figure 2-42. System Software Interrupt Request 1 Register (SSIR1) [offset = B0h]
31
16
Reserved
R-0
15
8
7
0
SSKEY1
SSDATA1
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 2-56. System Software Interrupt Request 1 Register (SSIR1) Field Descriptions
Bit
Field
Value
Description
31-16
Reserved
0
15-8
SSKEY1
0-FFh
Reads return 0. Writes have no effect.
System software interrupt request key. A 075h written to these bits initiates IRQ/FIQ interrupts.
Data in this field is always read as 0. The SSKEY1 field can be written into only if the write data
matches the key (75h). The SSDATA1 field can only be written into if the write data into this field,
the SSKEY1 field, matches the key (75h).
7-0
SSDATA1
0-FFh
System software interrupt data. These bits contain user read/write register bits. They may be used
by the application software as different entry points for the interrupt routine. The SSDATA1 field
cannot be written into unless the write data into the SSKEY1 field matches the key (75h);
therefore, byte writes cannot be performed on the SSDATA1 field.
NOTE: This register is mirrored at offset FCh for compatibility reasons.
2.5.1.38 System Software Interrupt Request 2 Register (SSIR2)
The SSIR2 register, shown in Figure 2-43 and described in Table 2-57, is used for software interrupt
generation.
Figure 2-43. System Software Interrupt Request 2 Register (SSIR2) [offset = B4h]
31
16
Reserved
R-0
15
8
7
0
SSKEY2
SSDATA2
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 2-57. System Software Interrupt Request 2 Register (SSIR2) Field Descriptions
Bit
Field
Value
Description
31-16
Reserved
0
Reads return 0. Writes have no effect.
15-8
SSKEY2
0-FFh
System software interrupt2 request key. A 84h written to these bits initiates IRQ/FIQ interrupts.
Data in this field is always read as 0. The SSKEY2 field can be written into only if the write data
matches the key (84h). The SSDATA2 field can only be written into if the write data into this field,
the SSKEY2 field, matches the key (84h).
7-0
SSDATA2
0-FFh
System software interrupt data. These bits contain user read/write register bits. They may be used
by the application software as different entry points for the interrupt routine. The SSDATA2 field
cannot be written into unless the write data into the SSKEY2 field matches the key (84h);
therefore, byte writes cannot be performed on the SSDATA2 field.
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2.5.1.39 System Software Interrupt Request 3 Register (SSIR3)
The SSIR3 register, shown in Figure 2-44 and described in Table 2-58, is used for software interrupt
generation.
Figure 2-44. System Software Interrupt Request 3 Register (SSIR3) [offset = B8h]
31
16
Reserved
R-0
15
8
7
0
SSKEY3
SSDATA3
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 2-58. System Software Interrupt Request 3 Register (SSIR3) Field Descriptions
Bit
Field
Value
Description
31-16
Reserved
0
15-8
SSKEY3
0-FFh
Reads return 0. Writes have no effect.
System software interrupt request key. A 93h written to these bits initiates IRQ/FIQ interrupts. Data
in this field is always read as 0. The SSKEY3 field can be written into only if the write data
matches the key (93h). The SSDATA3 field can only be written into if the write data into this field,
the SSKEY3 field, matches the key (93h).
7-0
SSDATA3
0-FFh
System software interrupt data. These bits contain user read/write register bits. They may be used
by the application software as different entry points for the interrupt routine. The SSDATA3 field
cannot be written into unless the write data into the SSKEY3 field matches the key (93h);
therefore, byte writes cannot be performed on the SSDATA3 field.
2.5.1.40 System Software Interrupt Request 4 Register (SSIR4)
The SSIR4 register, shown in Figure 2-45 and described in Table 2-59, is used for software interrupt
generation.
Figure 2-45. System Software Interrupt Request 4 Register (SSIR4) [offset = BCh]
31
16
Reserved
R-0
15
8
7
0
SSKEY4
SSDATA4
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 2-59. System Software Interrupt Request 4 Register (SSIR4) Field Descriptions
Bit
Field
Value
Description
31-16
Reserved
0
15-8
SSKEY4
0-FFh
System software interrupt2 request key. A A2h written to these bits initiates IRQ/FIQ interrupts.
Data in this field is always read as 0. The SSKEY4 field can be written into only if the write data
matches the key (A2h). The SSDATA4 field can only be written into if the write data into this field,
the SSKEY4 field, matches the key (A2h).
7-0
SSDATA4
0-FFh
System software interrupt data. These bits contain user read/write register bits. They may be used
by the application software as different entry points for the interrupt routine. The SSDATA4 field
cannot be written into unless the write data into the SSKEY4 field matches the key (A2h);
therefore, byte writes cannot be performed on the SSDATA4 field.
168
Reads return 0. Writes have no effect.
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2.5.1.41 RAM Control Register (RAMGCR)
The RAMGCR register, shown in Figure 2-46 and described in Table 2-60, is used to configure eSRAM
data and address wait states.
NOTE: The RAM_DFT_EN bits are for TI internal use only.
The contents of the RAM_DFT_EN field should not be changed.
Figure 2-46. RAM Control Register (RAMGCR) [offset = C0h]
31
20
19
16
Reserved
RAM_DFT_EN
R-0
R/WP-5h
15
8
Reserved
R-0
7
2
1
0
Reserved
3
WST_AENA0
Reserved
WST_DENA0
R-0
R/WP-0
R-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 2-60. RAM Control Register (RAMGCR) Field Descriptions
Bit
Field
31-20
Reserved
19-16
RAM_DFT_EN
Value
0
Description
Reads return 0. Writes have no effect.
Functional mode RAM DFT (Design For Test) port enable key.
Note: For TI internal use only.
Ah
RAM DFT port is enabled.
Others
RAM DFT port is disabled.
Note: It is recommended that a value of 5h be used to disable the RAM DFT port. This value
will give maximum protection from a bit flip inducing event that would inadvertently enable
the controller.
15-3
2
Reserved
0
WST_AENA0
1
Reserved
0
WST_DENA0
Reads return 0. Writes have no effect.
eSRAM data phase wait state enable bit.
0
The default address setup time for eSRAM0 is used.
1
The eSRAM address setup time is increased by one HCLK cycle.
0
Reads return 0. Writes have no effect.
eSRAM data phase wait state enable bit.
0
There are no wait states for eSRAM during the data phase.
1
The eSRAM data phase setup time is increased by one HCLK cycle.
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2.5.1.42 Bus Matrix Module Control Register 1 (BMMCR1)
The BMMCR1 register, shown in Figure 2-47 and described in Table 2-61, allows RAM and Program
(Flash) memory addresses to be swapped.
Figure 2-47. Bus Matrix Module Control Register 1 (BMMCR) [offset = C4h]
31
16
Reserved
R-0
15
4
3
0
Reserved
MEMSW
R-0
R/WP-Ah
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 2-61. Bus Matrix Module Control Register 1 (BMMCR) Field Descriptions
Bit
Field
31-4
Reserved
3-0
MEMSW
Value
0
Description
Reads return 0. Writes have no effect.
Memory swap key.
Note: A CPU reset must be issued after the memory swap key has been changed for the
memory swap to occur. A CPU reset can be initiated by changing the state of the CPU
RESET bit in the CPURSTCR register.
5h
Swapped memory-map:
eSRAM starts at address 0. Program memory (Flash) starts at address 800 0000h.
Ah
Default memory-map:
Program memory (Flash) starts at address 0. eSRAM starts at address 800 0000h.
All other values
170
The device memory-map is unchanged.
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2.5.1.43
CPU Reset Control Register (CPURSTCR)
The CPURSTCR register shown in Figure 2-48 and described in Table 2-62 allows a reset to the CortexR4F CPU to be generated.
NOTE: The register bits in CPURSTCR are designated as high-integrity bits and have been
implemented with error-correcting logic such that each bit, although read and written as a
single bit, is actually a multi-bit key with error correction capability. As such, single-bit flips
within the “key” can be corrected allowing protection of the system as a whole. An error
detected is signaled to the ESM module.
Figure 2-48. CPU Reset Control Register (CPURSTCR) [offset = CCh]
31
16
Reserved
R-0
15
1
0
Reserved
CPU RESET
R-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 2-62. CPU Reset Control Register (CPURSTGCR) Field Descriptions
Bit
31-1
0
Field
Reserved
CPU RESET
Value
0
Description
Reads return 0. Writes have no effect.
CPU Reset.
Only the CPU is reset whenever this bit is toggled. There is no system reset.
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2.5.1.44 Clock Control Register (CLKCNTL)
The CLKCNTL register, shown in Figure 2-49 and described in Table 2-63, controls peripheral reset and
the peripheral clock divide ratios.
NOTE: VCLK and VCLK2 clock ratio restrictions.
The VCLK2 frequency must always be greater than or equal to the VCLK frequency. The
VCLK2 frequency must be an integer multiple of the VCLK frequency.
In addition, the VCLK and VCLK2 clock ratios must not be changed simultaneously. When
increasing the frequency (decreasing the divider), first change the VCLK2R field and then
change the VCLKR field. When reducing the frequency (increasing the divider), first change
the VCLKR field and then change the VCLK2R field.
You should do a read-back between the two writes. This assures that there are enough clock
cycles between the two writes.
Figure 2-49. Clock Control Register (CLKCNTL) [offset = D0h]
31
28
27
24
23
20
19
16
Reserved
VCLK2R
Reserved
VCLKR
R-0
R/WP-1h
R-0
R/WP-1h
15
9
8
7
0
Reserved
PENA
Reserved
R-0
R/WP-0
R-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 2-63. Clock Control Register (CLKCNTL) Field Descriptions
Bit
Field
31-28
Reserved
27-24
VCLK2R
Value
0
Description
Reads return 0. Writes have no effect.
VBUS clock2 ratio.
Note: The VCLK2 frequency must always be greater than or equal to the VCLK frequency. The
VCLK2 frequency must be an integer multiple of the VCLK frequency. In addition, the VCLK and
VCLK2 clock ratios must not be changed simultaneously.
0
The VCLK2 speed is HCLK divided by 1.
:
:
Fh
23-20
Reserved
19-16
VCLKR
0
The VCLK2 speed is HCLK divided by 16.
Reads return 0. Writes have no effect.
VBUS clock ratio.
Note: The VCLK2 frequency must always be greater than or equal to the VCLK frequency. The
VCLK2 frequency must be an integer multiple of the VCLK frequency. In addition, the VCLK and
VCLK2 clock ratios must not be changed simultaneously.
0
The VCLK speed is HCLK divided by 1.
:
:
Fh
15-9
8
7-0
172
Reserved
0
PENA
Reserved
The VCLK speed is HCLK divided by 16.
Reads return 0. Writes have no effect.
Peripheral enable bit. The application must set this bit before accessing any peripheral.
0
The global peripheral/peripheral memory frames are in reset.
1
All peripheral/peripheral memory frames are out of reset.
0
Reads return 0. Writes have no effect.
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2.5.1.45 ECP Control Register (ECPCNTL)
The ECP register, shown in Figure 2-50 and described in Table 2-64, configures the ECLK pin in
functional mode.
NOTE: ECLK Functional mode configuration.
The ECLK pin must be placed into Functional mode by setting the ECPCLKFUN bit to 1 in
the SYSPC1 register before a clock source will be visible on the ECLK pin.
Figure 2-50. ECP Control Register (ECPCNTL) [offset = D4h]
31
25
Reserved
24
23
22
ECPSSEL ECPCOS
R-0
R/W-0
R/W-0
18
17
16
Reserved
ECPINSEL
R-0
R/W-0
15
0
ECPDIV
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 2-64. ECP Control Register (ECPCNTL) Field Descriptions
Bit
Field
31-25
Reserved
24
ECPSSEL
Value
0
Description
Reads return 0. Writes have no effect.
This bit allows the selection between VCLK and OSCIN as the clock source for ECLK.
Note: Other ECLK clock sources are available for debug purposes by configuring the
CLKTEST register.
23
0
VCLK is selected as the ECP clock source.
1
OSCIN is selected as the ECP clock source.
ECPCOS
ECP continue on suspend.
Note: Suspend mode is entered while performing certain JTAG debugging operations.
22-18
Reserved
17-16
ECPINSEL
15-0
ECPDIV
0
ECLK output is disabled in suspend mode. ECLK output will be shut off and will not be seen on
the I/O pin of the device.
1
ECLK output is not disabled in suspend mode. ECLK output will not be shut off and will be seen
on the I/O pin of the device.
0
Reads return 0. Writes have no effect.
Select ECP input clock source.
0
Tied Low
1h
HCLK
2h
External clock
3h
Tied Low
0-FFFFh
ECP divider value. The value of ECPDIV bits determine the external clock (ECP clock) frequency
as a ratio of VBUS clock or OSCIN as shown in the formula:
ECLK =
V C L K o r O S C IN
(E C P D I V + 1 )
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2.5.1.46 DEV Parity Control Register 1 (DEVCR1)
This register is shown in Figure 2-51 and described in Table 2-65.
Figure 2-51. DEV Parity Control Register 1 (DEVCR1) [offset = DCh]
31
16
Reserved
R-0
15
4
3
0
Reserved
DEVPARSEL
R-0
R/WP-Ah
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 2-65. DEV Parity Control Register 1 (DEVCR1) Field Descriptions
Bit
Field
Value
31-4
Reserved
0
3-0
DEVPARSEL
Description
Reads return 0. Writes have no effect.
Device parity select bit key.
Note: After an odd (DEVPARSEL = Ah) or even (DEVPARSEL = 5h) scheme is
programmed into the DEVPARSEL register, any one bit change can be detected and will
retain its programmed scheme. More than one bit changes in DEVPARSELwill cause a
default to odd parity scheme.
5h
The device parity is even.
Ah
The device parity is odd.
2.5.1.47 System Exception Control Register (SYSECR)
The SYSECR register, shown in Figure 2-52 and described in Table 2-66, is used to generate a software
reset.
NOTE: The register bits in SYSECR are designated as high-integrity bits and have been
implemented with error-correcting logic such that each bit, although read and written as a
single bit, is actually a multi-bit key with error correction capability. As such, single-bit flips
within the “key” can be corrected allowing protection of the system as a whole. An error
detected is signaled to the ESM module.
Figure 2-52. System Exception Control Register (SYSECR) [offset = E0h]
31
16
Reserved
R-0
15
14
RESET1
RESET0
13
Reserved
0
R/WP-0
R/WP-1
R-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 2-66. System Exception Control Register (SYSECR) Field Descriptions
Bit
Field
31-16
Reserved
15-14
RESET[1-0]
Value
0
0, 2h-3h
174
Reserved
Reads return 0. Writes have no effect.
Software reset bits. Setting RESET1 or clearing RESET0 causes a system software reset.
1h
13-0
Description
0
No reset will occur.
A global system reset will occur.
Reads return 0. Writes have no effect.
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2.5.1.48 System Exception Status Register (SYSESR)
The SYSESR register, shown in Figure 2-53 and described in Table 2-67, shows the source for different
resets encountered. Previous reset source status bits are not automatically cleared if new resets occur.
After reading this register, the software should clear any flags that are set so that the source of future
resets can be determined. Any bit in this register can be cleared by writing a 1 to the bit.
Figure 2-53. System Exception Status Register (SYSESR) [offset = E4h]
31
16
Reserved
R-0
15
14
13
PORST
OSCRST
WDRST
12
Reserved
R/WC-X
R/WC-X*
R/WC-X*
R-0
7
6
5
4
8
3
2
0
Reserved
CPURST
SWRST
EXTRST
Reserved
R-0
R/WC-X*
R/WC-X*
R/WC-X*
R-0
LEGEND: R/W = Read/Write; R = Read only; C= Clear; X = value unchanged after reset; X* = 0 after PORST but unchanged after other
resets; -n = value after reset
Table 2-67. System Exception Status Register (SYSESR) Field Descriptions
Bit
31-16
15
14
Field
Reserved
Value
0
PORST
Description
Reads return 0. Writes have no effect.
Power-on reset. This bit is set when a power-on reset occurs, either internally asserted by the VMON or
externally asserted by the nPORRST pin.
0
No power-on reset has occurred since this bit was last cleared.
1
A reset was caused by a power-on reset. (This bit should be cleared after being read so that
subsequent resets can be properly identified as not being power-on resets.)
OSCRST
Reset caused by an oscillator failure or PLL cycle slip. This bit is set when a reset is caused by an
oscillator failure or PLL slip.
Note: The action taken when an oscillator failure or PLL slip is detected must configured in the
PLLCTL1 register.
13
0
No reset has occurred due to an oscillator failure or a PLL cycle slip.
1
A reset was caused by an oscillator failure or a PLL cycle slip.
WDRST
Watchdog reset flag. This bit is set when the last reset was caused by the digital windowed watchdog.
During debugging, the ICEPICK logic implemented on the microcontroller also allows a system reset to
be generated via the debug logic (DBGRST). This DBGRST reset is also indicated on the WDRST bit of
the SYSESR. This flag can also be set via a reset driven by ICEPICK.
12-6
Reserved
5
CPURST
0
No reset has occurred because of the DWWD.
1
A reset was caused by the DWWD.
0
Reads return 0. Writes have no effect.
CPU reset flag. This bit is set when the CPU is reset.
Note: A CPU reset can be initiated by the CPU self-test controller (LBIST) or by changing the
memory protection (MMU/MPU) configuration in CPURSTCR register.
4
0
No CPU reset has occurred.
1
A CPU reset occurred.
SWRST
Software reset flag. This bit is set when a software system reset has occurred.
Note: A software system reset can be initiated by writing to the RESET bits in the SYSECR
register.
0
No software reset has occurred.
1
A software reset occurred.
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Table 2-67. System Exception Status Register (SYSESR) Field Descriptions (continued)
Bit
3
2-0
Field
Value
EXTRST
Description
External reset flag. This bit is set when a reset is caused by the external reset pin nRST or by any reset
that also asserts the nRST pin (PORST, OSCRST, WDRST and SWRST).
Reserved
0
The external reset pin has not asserted a reset.
1
A reset has been caused by the external reset pin.
0
Reads return 0. Writes have no effect.
2.5.1.49 System Test Abort Status Register (SYSTASR)
This register is shown in Figure 2-54 and described in Table 2-68.
Figure 2-54. System Test Abort Status Register (SYSTASR) [offset = E8h]
31
16
Reserved
R-0
15
5
4
0
Reserved
EFUSE_Abort
R-0
R/WPC-X/0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; C = Clear; -X = Value unchanged after reset; -n = value
after reset
Table 2-68. System Test Abort Status Register (SYSTASR) Field Descriptions
Bit
Field
31-5
Reserved
4-0
EFUSE_Abort
Value
0
Reads return 0. Writes have no effect.
Test Abort status flag. These bits are set when test abort occurred:
0
Read: The last operation (if any) completed successfully. This is also the value that the
error/status register is set to after reset.
1h
Read: Controller times out because there is no last row sent from the FuseROM.
2h
Read: The autoload machine was started, either through the SYS_INITZ signal from the system or
the JTAG data register. In either case, the autoload machine did not find enough FuseROM data
to fill the scan chain.
3h
Read: The autoload machine was started, either through the SYS_INITZ signal from the system or
the JTAG data register. In either case, the autoload machine starts the scan chain with a signature
it expects to see after the scan chain is full. The autoload machine was able to fill the scan chain,
but the wrong signature was returned.
4h
Read: The autoload machine was started, either through the SYS_INITZ signal from the system or
the JTAG data register. In either case, the autoload machine was not able or not allowed to
complete its operation.
Others
1Fh
176
Description
Read: Reserved.
Write: These bits are cleared to 0.
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2.5.1.50 Global Status Register (GLBSTAT)
The GLBSTAT register, shown in Figure 2-55 and described in Table 2-69, indicates the FMzPLL (PLL1)
slip status and the oscillator fail status.
NOTE: PLL and OSC fail behavior
The device behavior after a PLL slip or an oscillator failure is configured in the PLLCTL1
register.
Figure 2-55. Global Status Register (GLBSTAT) [offset = ECh]
31
16
Reserved
R-0
15
9
8
Reserved
10
FBSLIP
RFSLIP
7
Reserved
1
OSCFAIL
0
R-0
R/W1C-n
R/W1C-n
R-0
R/W1C-n
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to Clear; -n = value after reset
Table 2-69. Global Status Register (GLBSTAT) Field Descriptions
Bit
31-10
9
Field
Reserved
Value
0
FBSLIP
Description
Reads return 0. Writes have no effect.
PLL over cycle slip detection. (cleared by nPORRST, maintains its previous value for all other resets)
0
Read: No PLL over cycle slip has been detected.
Write: The bit is unchanged.
1
Read: A PLL over cycle slip has been detected.
Write: The bit is cleared to 0.
8
RFSLIP
PLL under cycle slip detection. (cleared by nPORRST, maintains its previous value for all other resets)
0
Read: No PLL under cycle slip has been detected.
Write: The bit is unchanged.
1
Read: A PLL under cycle slip has been detected.
Write: The bit is cleared to 0.
7-1
Reserved
0
OSCFAIL
0
Reads return 0. Writes have no effect.
Oscillator fail flag bit. (cleared by nPORRST, maintains its previous value for all other resets)
0
Read: No oscillator failure has been detected.
Write: The bit is unchanged.
1
Read: An oscillator failure has been detected.
Write: The bit is cleared to 0.
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2.5.1.51 Device Identification Register (DEVID)
The DEVID is a read-only register. It contains device-specific information that is hard-coded during device
manufacture. For the initial silicon version, the device identification code value is 802A AD05h. This
register is shown in Figure 2-56 and described in Table 2-70.
Figure 2-56. Device Identification Register (DEVID) [offset = F0h]
31
30
17
16
CP15
UNIQUE ID
TECH
R-K
R-K
R-K
15
12
11
TECH
13
I/O VOLTAGE
PERIPHERAL
PARITY
FLASH ECC
RAM ECC
R-K
R-K
R-K
R-K
R-K
7
3
10
9
2
8
1
VERSION
PLATFORM ID
R-K
R-K
0
LEGEND: R = Read only; -n = value after reset; K = Constant value
Table 2-70. Device Identification Register (DEVID) Field Descriptions
Bit
Field
31
CP15
30-17
UNIQUE ID
16-13
TECH
Value
CP15 CPU. This bit indicates whether the CPU has a coprocessor 15 (CP15).
0
The CPU has no CP15 present.
1
The CPU has a CP15 present. The CPU ID can be read using the CP15 C0,C0,0 register.
0-3FFFh
11
0
Device manufactured in the C05 process technology.
1h
Device manufactured in the F05 process technology.
2h
Device manufactured in the C035 process technology.
3h
Device manufactured in the F035 process technology.
4h
Device manufactured in the C021 process technology.
5h
Device manufactured in the F021 process technology.
10-9
8
I/O VOLTAGE
PERIPHERAL
PARITY
2-0
PLATFORM ID
178
Input/output voltage. This bit defines the I/O voltage of the device.
The I/O voltage is 3.3 V.
1
The I/O voltage is 5 V.
Peripheral parity. This bit indicates whether or not peripheral memory parity is present.
0
The peripheral memories have no parity.
1
The peripheral memories have parity.
These bits indicate which parity is present for the program memory.
0
No memory protection is present.
1h
The program memory (Flash) has single-bit parity.
2h
The program memory (Flash) has ECC.
3h
This combination is reserved.
RAM ECC
VERSION
Reserved
0
FLASH ECC
7-3
Device ID. The device ID is unique by device configuration.
These bits define the process technology by which the device was manufactured.
6h-Fh
12
Description
RAM ECC. This bit indicates whether or not RAM memory ECC is present.
0
The RAM memories do not have ECC.
1
The RAM memories have ECC.
0-1Fh
5h
Version. These bits provide the revision of the device.
The device is part of the TMS570 family. The TMS570 ID is always 5h.
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2.5.1.52 Software Interrupt Vector Register (SSIVEC)
The SSIVEC register, shown in Figure 2-57 and described in Table 2-71, contains information about
software interrupts.
Figure 2-57. Software Interrupt Vector Register (SSIVEC) [offset = F4h]
31
16
Reserved
R-0
15
8
7
0
SSIDATA
SSIVECT
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 2-71. Software Interrupt Vector Register (SSIVEC) Field Descriptions
Bit
Field
Value
31-16
Reserved
0
15-8
SSIDATA
0-FFh
7-0
SSIVECT
Description
Reads return 0. Writes have no effect.
System software interrupt data key. These bits contain the data key value of the source for the
system software interrupt, which is indicated by the vector in the SSIVEC[7-0] field.
These bits contain the source for the system software interrupt.
Note: A read from the SSIVECT bits clears the corresponding SSI_FLAG[4-1] bit in the
SSIF register, corresponding to the source vector of the system software interrupt.
Note: The SSIR[4-1] interrupt has the following priority order:
SSIR1 has the highest priority.
SSIR4 has the lowest priority.
0
No software interrupt is pending.
1h
A software interrupt has been generated by writing the correct key value to The SSIR1 register.
2h
A software interrupt has been generated by writing the correct key value to The SSIR2 register.
3h
A software interrupt has been generated by writing the correct key value to The SSIR3 register.
4h
A software interrupt has been generated by writing the correct key value to The SSIR4 register.
5h-FFh
Reserved
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2.5.1.53 System Software Interrupt Flag Register (SSIF)
The SSIF register, shown in Figure 2-58 and described in Table 2-72, contains software interrupt flag
status information.
Figure 2-58. System Software Interrupt Flag Register (SSIF) [offset = F8h]
31
16
Reserved
R-0
15
8
Reserved
R-0
7
3
2
1
0
Reserved
4
SSI_FLAG4
SSI_FLAG3
SSI_FLAG2
SSI_FLAG1
R-0
R/WC-0
R/WC-0
R/WC-0
R/WC-0
LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset
Table 2-72. System Software Interrupt Flag Register (SSIF) Field Descriptions
Bit
Field
31-4
Reserved
3-0
SSI_FLAG[4-1]
Value
0
Description
Reads return 0. Writes have no effect.
System software interrupt flag[4-1]. This flag is set when the correct SSKEY is written to the
SSIR register[4-1].
Note: A read from the SSIVEC register clears the corresponding SSI_FLAG[4-1] bit in the
SSIF, corresponding to the source vector of the system software interrupt.
0
Read: No IRQ/FIQ interrupt was generated since the bit was last cleared.
Write: The bit is unchanged.
1
Read: An IRQ/FIQ interrupt was generated.
Write: The bit is cleared to 0.
180
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2.5.2 Secondary System Control Registers (SYS2)
This section describes the secondary frame of system registers. The start address of the secondary
system module frame is FFFF E100. The registers support 32-, 16-, and 8-bit writes. The offset is relative
to the system module frame start address.
Table 2-73 contains a list of the secondary system control registers.
Table 2-73. Secondary System Control Registers
Offset
Acronym
Register Description
Section
00
PLLCTL3
PLL Control Register 3
Section 2.5.2.1
04h
Reserved
Reserved
08h
STCCLKDIV
CPU Logic BIST Clock Divider
0Ch-20h
Reserved
Reserved
24h
ECPCNTL
ECP Control Register
28h-38h
Reserved
Reserved
3Ch
CLK2CNTRL
Clock 2 Control Register
Section 2.5.2.3
40h
VCLKACON1
Peripheral Asynchronous Clock Configuration 1 Register
Section 2.5.2.4
44h-6Ch
Reserved
Reserved
70h
CLKSLIP
Clock Slip Register
74h-E8h
Reserved
Reserved
ECh
EFC_CTLREG
EFUSE Controller Control Register
Section 2.5.2.6
F0h
DIEIDL_REG0
Die Identification Register Lower Word
Section 2.5.2.7
F4h
DIEIDH_REG1
Die Identification Register Upper Word
Section 2.5.2.8
F8h
DIEIDL_REG2
Die Identification Register Lower Word
Section 2.5.2.9
FCh
DIEIDH_REG3
Die Identification Register Upper Word
Section 2.5.2.10
Section 2.5.2.2
Section 2.5.1.45
Section 2.5.2.5
NOTE: All additional registers in the secondary system frame are reserved.
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PLL Control Register 3 (PLLCTL3)
The PLLCTL3 register is shown in Figure 2-59 and described in Table 2-74; controls the settings of PLL2
(Clock Source 6 - FPLL).
Figure 2-59. PLL Control Register 3 (PLLCTL3) [offset = 00]
31
29
28
24
23
22
21
16
ODPLL2
PLLDIV2
Reserved
REFCLKDIV2
R/WP-1h
R/WP-Fh
R-0
R/WP-2h
15
0
PLL_MUL2
R/WP-5F00h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 2-74. PLL Control Register 3 (PLLCTL3) Field Descriptions
Bit
31-29
Field
Value
ODPLL2
Description
Internal PLL Output Divider
OD2 = ODPLL2 + 1, ranges from 1 to 8.
fpost_ODCLK2 = foutput_CLK2 / OD2
0
fpost_ODCLK2 = foutput_CLK2 / 1
1h
fpost_ODCLK2 = foutput_CLK2 / 2
:
7h
:
fpost_ODCLK2 = foutput_CLK2 / 8
Note: PLL output clock is gated off, if ODPLL2 is changed while the PLL2 is active.
28-24
PLLDIV2
PLL2 Output Clock Divider
R2 = PLLDIV2 + 1, ranges from 1 to 32.
fPLL2 CLK = fpost_ODCLK2 / R2
0
f PLL2 CLK = f post_ODCLK2 /1
1h
f PLL2 CLK = f post_ODCLK2 /2
:
1Fh
23-22
Reserved
21-16
REFCLKDIV2
0
:
f PLL2 CLK = f post_ODCLK2 /32
Value has no effect on PLL operation.
Reference Clock Divider
NR2 = REFCLKDIV2 + 1, ranges from 1 to 64.
fINTCLK2 = fOSCIN / NR2
0
f INTCLK2= f OSCIN /1
1h
f INTCLK2= f OSCIN /2
:
3Fh
:
f INTCLK2= f OSCIN /64
Note: This value should not be changed while the PLL2 is active.
15-0
PLLMUL2
PLL2 Multiplication Factor
NF2 = (PLLMUL2 / 256) + 1, valid multiplication factors are from 1 to 256.
fVCOCLK2 = fINTCLK2 x NF2
User and privileged mode (read):
Privileged mode (write):
100h
:
:
5B00h
fVCOCLK2 = fINTCLK2 x 92
5C00h
fVCOCLK2 = fINTCLK2 x 93
:
FF00h
182
f VCOCLK2= f INTCLK2 x 1
:
fVCOCLK2 = fINTCLK2 x 256
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2.5.2.2
CPU Logic Bist Clock Divider (STCLKDIV)
This register is shown in Figure 2-60 and described in Table 2-75.
Figure 2-60. CPU Logic BIST Clock Prescaler (STCLKDIV) [offset = 08h]
31
27
26
24
23
16
Reserved
CLKDIV
Reserved
R-0
R/WP-0
R-0
15
0
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 2-75. CPU Logic BIST Clock Prescaler (STCLKDIV) Field Descriptions
Bit
Field
Value
Description
31-27
Reserved
0
Reads return 0. Writes have no effect.
26-24
CLKDIV
0
Clock divider/prescaler for CPU clock during logic BIST
23-0
Reserved
0
Reads return 0. Writes have no effect.
2.5.2.3
Clock 2 Control Register (CLK2CNTRL)
This register is shown in Figure 2-61 and described in Table 2-76.
Figure 2-61. Clock 2 Control Register (CLK2CNTRL) [offset = 3Ch]
31
16
Reserved
R-0
15
12
11
8
7
4
3
0
Reserved
Reserved
Reserved
VCLK3R
R-0
R/WP-1h
R-0
R/WP-1h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 2-76. Clock 2 Control Register (CLK2CNTRL) Field Descriptions
Bit
Field
31-12
Reserved
11-8
Reserved
7-4
Reserved
3-0
VCLK3R
Value
0
Description
Reads return 0. Writes have no effect.
Reads return value and writes allowed in privilege mode.
0
Reads return 0. Writes have no effect.
VBUS clock3 ratio.
0
The ratio is HCLK divide by 1.
:
:
Fh
The ratio is HCLK divided by 16.
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Peripheral Asynchronous Clock Configuration 1 Register (VCLKACON1)
This register is shown in Figure 2-62 and described in Table 2-77.
Figure 2-62. Peripheral Asynchronous Clock Configuration 1 Register (VCLKACON1) [offset = 40h]
31
27
26
24
Reserved
VCLKA4R
R-0
R/WP-1h
23
21
20
19
16
Reserved
VCLKA4_DIV_
CDDIS
VCLKA4S
R-0
R/WP-0
R/WP-9h
15
11
10
8
7
5
4
0
Reserved
Reserved
Reserved
Reserved
R-0
R/WP-1h
R-0
R/WP-9h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 2-77. Peripheral Asynchronous Clock Configuration 1 Register (VCLKACON1)
Field Descriptions
Bit
Field
31-27 Reserved
Value
0
26-24 VCLKA4R
Description
Reads return 0. Writes have no effect.
Clock divider for the VCLKA4 source. Output will be present on VCLKA4_DIVR.
VCLKA4 domain will be enabled by writing to the CDDIS register and VCLKA4_DIV_CDDIS bit.
It can be inferred that VCLKA4_DIV clock is disabled when VCLKA4 clock is disabled.
23-21 Reserved
20
0
The ratio is VCLKA4 divided by 1.
:
:
7h
The ratio is VCLKA4 divided by 8.
0
Reads return 0. Writes have no effect.
VCLKA4_DIV_CDDIS
Disable the VCLKA4 divider output.
VCLKA4 domain will be enabled by writing to the CDDIS register
0
Enable the prescaled VCLKA4 clock on VCLKA4_DIVR.
1
Disable the prescaled VCLKA4 clock on VCLKA4_DIVR.
19-16 VCLKA4S
15-0
Reserved
Peripheral asynchronous clock4 source.
0
Clock source0 is the source for peripheral asynchronous clock4.
1h
Clock source1 is the source for peripheral asynchronous clock4.
2h
Clock source2 is the source for peripheral asynchronous clock4.
3h
Clock source3 is the source for peripheral asynchronous clock4.
4h
Clock source4 is the source for peripheral asynchronous clock4.
5h
Clock source5 is the source for peripheral asynchronous clock4.
6h
Clock source6 is the source for peripheral asynchronous clock4.
7h
Clock source7 is the source for peripheral asynchronous clock4.
8h-Fh
VCLK or a divided VCLK is the source for peripheral asynchronous clock4. See the devicespecific data manual for details.
109h
Reserved
NOTE: Non implemented clock sources should not be enabled or used. A list of the available clock
sources is shown in Table 2-29.
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2.5.2.5
Clock Slip Register (CLKSLIP)
This register is shown in Figure 2-63 and described in Table 2-78. For information on filtering the FBSLIP
see Section 2.5.1.34.
Figure 2-63. Clock Slip Register (CLKSLIP) [offset = 70h]
31
16
Reserved
R-0
15
14
13
8
7
4
3
0
Reserved
PLL1_RFSLIP_FILTER_COUNT
Reserved
PLL1_RFSLIP_FILTER_KEY
R-0
R/WP-0
R-0
R/WP-5h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 2-78. Clock Slip Register (CLKSLIP) Field Descriptions
Bit
Field
31-14
Reserved
13-8
PLL1_RFSLIP_FILTER_COUNT
Value
0
Description
Reads return 0. Writes have no effect.
PLL RFSLIP down counter programmed value. Count is on 10M clock.
On reset, counter value is 0. Counter must be programmed to a non-zero value
and enabled for the filtering to be enabled.
0
Filtering is disabled.
1h
Filtering is enabled. Every slip is recognized.
2h
Filtering is enabled. The slip must be at least 2 HF LPO cycles wide in order to
be recognized as a slip.
:
3Fh
7-4
Reserved
3-0
PLL1_RFSLIP_FILTER_KEY
0
:
Filtering is enabled. The RFSLIP must be at least 63 HF LPO cycles wide in
order to be recognized as a slip.
Reads return 0. Writes have no effect.
Enable the PLL RFSLIP filtering.
5h
On reset, the PLL RFSLIP filter is disabled and the PLL RFSLIP passes through.
Fh
This is an unsupported value. You should avoid writing this value to this bit field.
Others
PLL RFSLIP filtering is enabled. Recommended to program Ah in this bit field.
Enabling of the PLL RFSLIP occurs when the KEY is programmed and a nonzero value is present in the COUNT field.
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EFUSE Controller Control Register (EFC_CTLREG)
This register is shown in Figure 2-64 and described in Table 2-79.
Figure 2-64. EFUSE Controller Control Register (EFC_CTLREG) [offset = ECh]
31
16
Reserved
R-0
15
4
3
0
Reserved
EFC_INSTR_WEN
R-0
R/WP-5h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 2-79. EFUSE Controller Control Register (EFC_CTLREG) Field Descriptions
Bit
Field
Value
31-4
Reserved
0
3-0
EFC_INSTR_WEN
Description
Reads return 0. Writes have no effect.
Enable user write of 4 EFUSE controller instructions.
SYS module generates the enable signal which will be tied to
OCP_FROM_WRITE_DISABLE on efuse controller port
2.5.2.7
Ah
Writing of instructions (Program, ProgramCRA, RunAutoload, and LoadFuseScanchain) to
EFC is allowed enabled.
Others
Writing of instructions (Program, ProgramCRA, RunAutoload, and LoadFuseScanchain) in
EFC registers is blocked.
Die Identification Register Lower Word (DIEIDL_REG0)
The DIEIDL_REG0 is a duplicate of DIEIDL, see Section 2.5.1.28. The DIEIDL_REG0, shown in Figure 265 and described in Table 2-80, contains information about the die wafer number, and X, Y wafer
coordinates.
Figure 2-65. Die Identification Register, Lower Word (DIEIDL_REG0) [offset = F0h]
31
24
15
23
16
WAFER #
Y WAFER COORDINATE
R-D
R-D
12
11
0
Y WAFER COORDINATE
X WAFER COORDINATE
R-D
R-D
LEGEND: R = Read only; -n = value after reset; D = value is device specific
Table 2-80. Die Identification Register, Lower Word (DIEIDL_REG0) Field Descriptions
Field
Description
31-24
Bit
WAFER #
These read-only bits contain the wafer number of the device.
23-12
Y WAFER COORDINATE
These read-only bits contain the Y wafer coordinate of the device.
11-0
X WAFER COORDINATE
These read-only bits contain the X wafer coordinate of the device.
NOTE: Die Identification Information
The die identification information will vary from unit to unit. This information is programmed
by TI as part of the initial device test procedure.
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2.5.2.8
Die Identification Register Upper Word (DIEIDH_REG1)
The DIEIDH_REG1 is a duplicate of DIEIDH, see Section 2.5.1.29. The DIEIDH_REG1, shown in
Figure 2-66 and described in Table 2-81, contains information about the die lot number.
Figure 2-66. Die Identification Register, Upper Word (DIEIDH_REG1) [offset = F4h]
31
24
23
16
Reserved
LOT #
R-0
R-D
15
0
LOT #
R-D
LEGEND: R = Read only; -n = value after reset; D = value is device dependent
Table 2-81. Die Identification Register, Upper Word (DIEIDH_REG1) Field Descriptions
Bit
Field
Description
31-24
Reserved
Reserved for TI use. Writes have no effect.
23-0
LOT #
This read-only register contains the device lot number.
NOTE: Die Identification Information
The die identification information will vary from unit to unit. This information is programmed
by TI as part of the initial device test procedure.
2.5.2.9
Die Identification Register Lower Word (DIEIDL_REG2)
This register is shown in Figure 2-67 and described in Table 2-82.
Figure 2-67. Die Identification Register, Lower Word (DIEIDL_REG2) [offset = F8h]
31
0
DIEIDL2
R-X
LEGEND: R = Read only; -n = value after reset; X = value is unchanged after reset
Table 2-82. Die Identification Register, Lower Word (DIEIDL_REG2) Field Descriptions
Bit
31-0
Field
DIEIDL2(95-64)
Value
0-FFFF FFFFh
Description
This read-only register contains the lower word (95:64) of the die ID information. The
contents of this register is reserved.
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2.5.2.10 Die Identification Register Upper Word (DIEIDH_REG3)
This register is shown in Figure 2-68 and described in Table 2-83.
Figure 2-68. Die Identification Register, Upper Word (DIEIDH_REG3) [offset = FCh]
31
0
DIEIDH2
R-X
LEGEND: R = Read only; -n = value after reset; X = value is unchanged after reset
Table 2-83. Die Identification Register, Upper Word (DIEIDH_REG3) Field Descriptions
Bit
31-0
188
Field
DIEIDH2(127-96)
Value
Description
0-FFFF FFFFh
This read-only register contains the upper word (127:97) of the die ID information. The
contents of this register is reserved.
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2.5.3 Peripheral Central Resource (PCR) Control Registers
This section describes the Peripheral Central Resource (PCR) control registers. The start address of the
PCR register frame is FFFF E000h. Table 2-84 lists the registers in the PCR, which are used to configure
protection to the peripherals in PCS and PS regions. Not all chip selects exist on this device.
Table 2-84. Peripheral Central Resource Control Registers
Offset
Acronym
Register Description
00h
PMPROTSET0
Peripheral Memory Protection Set Register 0
Section 2.5.3.1
04h
PMPROTSET1
Peripheral Memory Protection Set Register 1
Section 2.5.3.2
Reserved
Reserved
10h
PMPROTCLR0
Peripheral Memory Protection Clear Register 0
Section 2.5.3.3
14h
PMPROTCLR1
Peripheral Memory Protection Clear Register 1
Section 2.5.3.4
Reserved
Reserved
20h
PPROTSET0
Peripheral Protection Set Register 0
Section 2.5.3.5
24h
PPROTSET1
Peripheral Protection Set Register 1
Section 2.5.3.6
28h
PPROTSET2
Peripheral Protection Set Register 2
Section 2.5.3.7
2Ch
PPROTSET3
Peripheral Protection Set Register 3
Section 2.5.3.8
08h-0Ch
18h-1Ch
30h-3Ch
Section
Reserved
Reserved
40h
PPROTCLR0
Peripheral Protection Clear Register 0
Section 2.5.3.9
44h
PPROTCLR1
Peripheral Protection Clear Register 1
Section 2.5.3.10
48h
PPROTCLR2
Peripheral Protection Clear Register 2
Section 2.5.3.11
4Ch
PPROTCLR3
Peripheral Protection Clear Register 3
Section 2.5.3.12
Reserved
Reserved
60h
PCSPWRDWNSET0
Peripheral Memory Power-Down Set Register 0
Section 2.5.3.13
64h
PCSPWRDWNSET1
Peripheral Memory Power-Down Set Register 1
Section 2.5.3.14
Reserved
Reserved
70h
PCSPWRDWNCLR0
Peripheral Memory Power-Down Clear Register 0
Section 2.5.3.15
74h
PCSPWRDWNCLR1
Peripheral Memory Power-Down Clear Register 1
Section 2.5.3.16
Reserved
Reserved
80h
PSPWRDWNSET0
Peripheral Power-Down Set Register 0
Section 2.5.3.17
84h
PSPWRDWNSET1
Peripheral Power-Down Set Register 1
Section 2.5.3.18
88h
PSPWRDWNSET2
Peripheral Power-Down Set Register 2
Section 2.5.3.19
8Ch
PSPWRDWNSET3
Peripheral Power-Down Set Register 3
Section 2.5.3.20
Reserved
Reserved
A0h
PSPWRDWNCLR0
Peripheral Power-Down Clear Register 0
Section 2.5.3.21
A4h
PSPWRDWNCLR1
Peripheral Power-Down Clear Register 1
Section 2.5.3.22
A8h
PSPWRDWNCLR2
Peripheral Power-Down Clear Register 2
Section 2.5.3.23
ACh
PSPWRDWNCLR3
Peripheral Power-Down Clear Register 3
Section 2.5.3.24
50h-5Ch
68h-6Ch
78h-7Ch
90h-9Ch
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Peripheral Memory Protection Set Register 0 (PMPROTSET0)
This register is shown in Figure 2-69 and described in Table 2-85.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to nonimplemented bits have no effect and reads are 0.
Figure 2-69. Peripheral Memory Protection Set Register 0 (PMPROTSET0) [offset = 00]
31
0
PCS[31-0]PROTSET
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 2-85. Peripheral Memory Protection Set Register 0 (PMPROTSET0) Field Descriptions
Bit
Field
31-0
Value
PCS[31-0]PROTSET
Description
Peripheral memory frame protection set.
0
Read: The peripheral memory framen can be written to and read from in both user and
privileged modes.
Write: The bit is unchanged.
1
Read: The peripheral memory framen can be written to only in privileged mode, but it can be
read in both user and privileged modes.
Write: The corresponding bit in PMPROTSET0 and PMPROTCLR0 registers is set to 1.
2.5.3.2
Peripheral Memory Protection Set Register 1 (PMPROTSET1)
This register is shown in Figure 2-70 and described in Table 2-86.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to nonimplemented bits have no effect and reads are 0.
Figure 2-70. Peripheral Memory Protection Set Register 1 (PMPROTSET1) [offset = 04h]
31
0
PCS[63-32]PROTSET
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 2-86. Peripheral Memory Protection Set Register 1 (PMPROTSET1) Field Descriptions
Bit
31-0
Field
Value
PCS[63-32]PROTSET
Description
Peripheral memory frame protection set.
0
Read: The peripheral memory framen can be written to and read from in both user and
privileged modes.
Write: The bit is unchanged.
1
Read: The peripheral memory framen can be written to only in privileged mode, but it can be
read in both user and privileged modes.
Write: The corresponding bit in PMPROTSET1 and PMPROTCLR1 registers is set to 1.
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2.5.3.3
Peripheral Memory Protection Clear Register 0 (PMPROTCLR0)
This register is shown in Figure 2-71 and described in Table 2-87.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to nonimplemented bits have no effect and reads are 0.
Figure 2-71. Peripheral Memory Protection Clear Register 0 (PMPROTCLR0) [offset = 10h]
31
0
PCS[31-0]PROTCLR
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 2-87. Peripheral Memory Protection Clear Register 0 (PMPROTCLR0) Field Descriptions
Bit
Field
31-0
Value
PCS[31-0]PROTCLR
Description
Peripheral memory frame protection clear.
0
Read: The peripheral memory framen can be written to and read from in both user and
privileged modes.
Write: The bit is unchanged.
1
Read: The peripheral memory framen can be written to only in privileged mode, but it can be
read in both user and privileged modes.
Write: The corresponding bit in PMPROTSET0 and PMPROTCLR0 registers is cleared to 0.
2.5.3.4
Peripheral Memory Protection Clear Register 1 (PMPROTCLR1)
This register is shown in Figure 2-72 and described in Table 2-88.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to nonimplemented bits have no effect and reads are 0.
Figure 2-72. Peripheral Memory Protection Clear Register 1 (PMPROTCLR1) [offset = 14h]
31
0
PCS[63-32]PROTCLR
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 2-88. Peripheral Memory Protection Clear Register 1 (PMPROTCLR1) Field Descriptions
Bit
31-0
Field
Value
PCS[63-32]PROTCLR
Description
Peripheral memory frame protection clear.
0
Read: The peripheral memory framen can be written to and read from in both user and
privileged modes.
Write: The bit is unchanged.
1
Read: The peripheral memory framen can be written to only in privileged mode, but it can be
read in both user and privileged modes.
Write: The corresponding bit in PMPROTSET1 and PMPROTCLR1 registers is cleared to 0.
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Peripheral Protection Set Register 0 (PPROTSET0)
There is one bit for each quadrant for PS0 to PS7.
The following are the ways in which quadrants are used within a PS frame:
a. The slave uses all the four quadrants.
Only the bit corresponding to the quadrant 0 of PSn is implemented. It protects the whole 1K-byte
frame. The remaining three bits are not implemented.
b. The slave uses two quadrants.
Each quadrant has to be in one of these groups: (Quad 0 and Quad 1) or (Quad 2 and Quad 3).
For the group Quad0/Quad1, the bit quadrant 0 protects both quadrants 0 and 1. The bit quadrant 1 is
not implemented.
For the group Quad2/Quad3, the bit quadrant 2 protects both quadrants 2 and 3. The bit quadrant 3 is
not implemented
c. The slave uses only one quadrant.
In this case, the bit, as specified in Table 2-89, protects the slave.
The above arrangement is true for all the peripheral select (PS0 to PS31) presented in Section 2.5.3.6 to
Section 2.5.3.12. This register holds bits for PS0 to PS7 and is shown in Figure 2-73 and described in
Table 2-89.
NOTE: Writes to nonimplemented bits have no effect and reads are 0.
Figure 2-73. Peripheral Protection Set Register 0 (PPROTSET0) [offset = 20h]
31
0
PS[7-0]QUAD[3-0]PROTSET
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 2-89. Peripheral Protection Set Register 0 (PPROTSET0) Field Descriptions
Bit
31-0
Field
PS[7-0]QUAD[3-0]
PROTSET
Value
Description
Peripheral select quadrant protection set.
0
Read: The peripheral select quadrant an be written to and read from in both user and
privileged modes.
Write: The bit is unchanged.
1
Read: The peripheral select quadrant can be written to only in privileged mode, but it can be
read in both user and privileged modes.
Write: The corresponding bit in PPROTSET0 and PPROTCLR0 registers is set to 1.
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2.5.3.6
Peripheral Protection Set Register 1 (PPROTSET1)
There is one bit for each quadrant for PS8 to PS15. The protection scheme is described in
Section 2.5.3.5. This register is shown in Figure 2-74 and described in Table 2-90.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to nonimplemented bits have no effect and reads are 0.
Figure 2-74. Peripheral Protection Set Register 1 (PPROTSET1) [offset = 24h]
31
0
PS[15-8]QUAD[3-0]PROTSET
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 2-90. Peripheral Protection Set Register 1 (PPROTSET1) Field Descriptions
Bit
Field
31-0
Value
PS[15-8]QUAD[3-0]
PROTSET
Description
Peripheral select quadrant protection set.
0
Read: The peripheral select quadrant can be written to and read from in both user and
privileged modes.
Write: The bit is unchanged.
1
Read: The peripheral select quadrant can be written to only in privileged mode, but it can be
read in both user and privileged modes.
Write: The corresponding bit in PPROTSET1 and PPROTCLR1 registers is set to 1.
2.5.3.7
Peripheral Protection Set Register 2 (PPROTSET2)
There is one bit for each quadrant for PS16 to PS23. The protection scheme is described in
Section 2.5.3.5. This register is shown in Figure 2-75 and described in Table 2-91.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to nonimplemented bits have no effect and reads are 0.
Figure 2-75. Peripheral Protection Set Register 2 (PPROTSET2) [offset = 28h]
31
0
PS[23-16]QUAD[3-0]PROTSET
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 2-91. Peripheral Protection Set Register 2 (PPROTSET2) Field Descriptions
Bit
31-0
Field
PS[23-16]QUAD[3-0]
PROTSET
Value
Description
Peripheral select quadrant protection set.
0
Read: The peripheral select quadrant can be written to and read from in both user and
privileged modes.
Write: The bit is unchanged.
1
Read: The peripheral select quadrant can be written to only in privileged mode, but it can be
read in both user and privileged modes.
Write: The corresponding bit in PPROTSET2 and PPROTCLR2 registers is set to 1.
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Peripheral Protection Set Register 3 (PPROTSET3)
There is one bit for each quadrant for PS24 to PS31. The protection scheme is described in
Section 2.5.3.5. This register is shown in Figure 2-76 and described in Table 2-92.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to nonimplemented bits have no effect and reads are 0.
Figure 2-76. Peripheral Protection Set Register 3 (PPROTSET3) [offset = 2Ch]
31
0
PS[31-24]QUAD[3-0]PROTSET
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 2-92. Peripheral Protection Set Register 3 (PPROTSET3) Field Descriptions
Bit
Field
31-0
Value
PS[31-24]QUAD[3-0]
PROTSET
Description
Peripheral select quadrant protection set.
0
Read: The peripheral select quadrant can be written to and read from in both user and
privileged modes.
Write: The bit is unchanged.
1
Read: The peripheral select quadrant can be written to only in privileged mode, but it can be
read in both user and privileged modes.
Write: The corresponding bit in PPROTSET3 and PPROTCLR3 registers is set to 1.
2.5.3.9
Peripheral Protection Clear Register 0 (PPROTCLR0)
There is one bit for each quadrant for PS0 to PS7. The protection scheme is described in Section 2.5.3.5.
This register is shown in Figure 2-77 and described in Table 2-93.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to nonimplemented bits have no effect and reads are 0.
Figure 2-77. Peripheral Protection Clear Register 0 (PPROTCLR0) [offset = 40h]
31
0
PS[7-0]QUAD[3-0]PROTCLR
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 2-93. Peripheral Protection Clear Register 0 (PPROTCLR0) Field Descriptions
Bit
31-0
Field
PS[7-0]QUAD[3-0]
PROTCLR
Value
Description
Peripheral select quadrant protection clear.
0
Read: The peripheral select quadrant can be written to and read from in both user and
privileged modes.
Write: The bit is unchanged.
1
Read: The peripheral select quadrant can be written to only in privileged mode, but it can be
read in both user and privileged modes.
Write: The corresponding bit in PPROTSET0 and PPROTCLR0 registers is cleared to 0.
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2.5.3.10 Peripheral Protection Clear Register 1 (PPROTCLR1)
There is one bit for each quadrant for PS8 to PS15. The protection scheme is described in
Section 2.5.3.5. This register is shown in Figure 2-78 and described in Table 2-94.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to nonimplemented bits have no effect and reads are 0.
Figure 2-78. Peripheral Protection Clear Register 1 (PPROTCLR1) [offset = 44h]
31
0
PS[15-8]QUAD[3-0]PROTCLR
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 2-94. Peripheral Protection Clear Register 1 (PPROTCLR1) Field Descriptions
Bit
31-0
Field
Value
PS[15-8]QUAD[3-0]
PROTCLR
Description
Peripheral select quadrant protection clear.
0
Read: The peripheral select quadrant can be written to and read from in both user and
privileged modes.
Write: The bit is unchanged.
1
Read: The peripheral select quadrant can be written to only in privileged mode, but it can be
read in both user and privileged modes.
Write: The corresponding bit in PPROTSET1 and PPROTCLR1 registers is cleared to 0.
2.5.3.11 Peripheral Protection Clear Register 2 (PPROTCLR2)
There is one bit for each quadrant for PS16 to PS23. The protection scheme is described in
Section 2.5.3.5. This register is shown in Figure 2-79 and described in Table 2-95.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to nonimplemented bits have no effect and reads are 0.
Figure 2-79. Peripheral Protection Clear Register 2 (PPROTCLR2) [offset = 48h]
31
0
PS[23-16]QUAD[3-0]PROTCLR
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 2-95. Peripheral Protection Clear Register 2 (PPROTCLR2) Field Descriptions
Bit
31-0
Field
PS[23-16]QUAD[3-0]
PROTCLR
Value
Description
Peripheral select quadrant protection clear.
0
Read: The peripheral select quadrant can be written to and read from in both user and
privileged modes.
Write: The bit is unchanged.
1
Read: The peripheral select quadrant can be written to only in privileged mode, but it can be
read in both user and privileged modes.
Write: The corresponding bit in PPROTSET2 and PPROTCLR2 registers is cleared to 0.
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2.5.3.12 Peripheral Protection Clear Register 3 (PPROTCLR3)
There is one bit for each quadrant for PS24 to PS31. The protection scheme is described in
Section 2.5.3.5. This register is shown in Figure 2-80 and described in Table 2-96.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to nonimplemented bits have no effect and reads are 0.
Figure 2-80. Peripheral Protection Clear Register 3 (PPROTCLR3) [offset = 4Ch]
31
0
PS[31-24]QUAD[3-0]PROTCLR
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 2-96. Peripheral Protection Clear Register 3 (PPROTCLR3) Field Descriptions
Bit
31-0
Field
PS[31-24]QUAD[3-0]
PROTCLR
Value
Description
Peripheral select quadrant protection clear.
0
Read: The peripheral select quadrant can be written to and read from in both user and
privileged modes.
Write: The bit is unchanged.
1
Read: The peripheral select quadrant can be written to only in privileged mode, but it can be
read in both user and privileged modes.
Write: The corresponding bit in PPROTSET3 and PPROTCLR3 registers is cleared to 0.
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2.5.3.13 Peripheral Memory Power-Down Set Register 0 (PCSPWRDWNSET0)
Each bit corresponds to a bit at the same index in the PMPROT register in that they both relate to the
same peripheral. This register is shown in Figure 2-81 and described in Table 2-97.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to nonimplemented bits have no effect and reads are 0.
Figure 2-81. Peripheral Memory Power-Down Set Register 0 (PCSPWRDWNSET0) [offset = 60h]
31
0
PCS[31-0]PWRDNSET
R/WP-1
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 2-97. Peripheral Memory Power-Down Set Register 0 (PCSPWRDWNSET0) Field Descriptions
Bit
31-0
Field
Value
PCS[31-0]PWRDNSET
Description
Peripheral memory clock power-down set.
0
Read: The peripheral memory clock[31-0] is active.
Write: The bit is unchanged.
1
Read: The peripheral memory clock[31-0] is inactive.
Write: The corresponding bit in the PCSPWRDWNSET0 and PCSPWRDWNCLR0 registers
is set to 1.
2.5.3.14 Peripheral Memory Power-Down Set Register 1 (PCSPWRDWNSET1)
This register is shown in Figure 2-82 and described in Table 2-98.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to nonimplemented bits have no effect and reads are 0.
Figure 2-82. Peripheral Memory Power-Down Set Register 1 (PCSPWRDWNSET1) [offset = 64h]
31
0
PCS[63-32]PWRDNSET
R/WP-1
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 2-98. Peripheral Memory Power-Down Set Register 1 (PCSPWRDWNSET1) Field Descriptions
Bit
31-0
Field
Value
PCS[63-32]PWRDNSET
Description
Peripheral memory clock power-down set.
0
Read: The peripheral memory clock[63-32] is active.
Write: The bit is unchanged.
1
Read: The peripheral memory clock[63-32] is inactive.
Write: The corresponding bit in the PCSPWRDWNSET1 and PCSPWRDWNCLR1 registers
is set to 1.
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2.5.3.15 Peripheral Memory Power-Down Clear Register 0 (PCSPWRDWNCLR0)
This register is shown in Figure 2-83 and described in Table 2-99.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to nonimplemented bits have no effect and reads are 0.
Figure 2-83. Peripheral Memory Power-Down Clear Register 0 (PCSPWRDWNCLR0) [offset = 70h]
31
0
PCS[31-0]PWRDNCLR
R/WP-1
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 2-99. Peripheral Memory Power-Down Clear Register 0 (PCSPWRDWNCLR0) Field
Descriptions
Bit
31-0
Field
Value
PCS[31-0]PWRDNCLR
Description
Peripheral memory clock power-down clear.
0
Read: The peripheral memory clock[31-0] is active.
Write: The bit is unchanged.
1
Read: The peripheral memory clock[31-0] is inactive.
Write: The corresponding bit in the PCSPWRDWNSET0 and PCSPWRDWNCLR0 registers
is cleared to 0.
2.5.3.16 Peripheral Memory Power-Down Clear Register 1 (PCSPWRDWNCLR1)
This register is shown in Figure 2-84 and described in Table 2-100.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to nonimplemented bits have no effect and reads are 0.
Figure 2-84. Peripheral Memory Power-Down Clear Register 1 (PCSPWRDWNCLR1) [offset = 74h]
31
0
PCS[63-32]PWRDNCLR
R/WP-1
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 2-100. Peripheral Memory Power-Down Set Register 1 (PCSPWRDWNCLR1) Field
Descriptions
Bit
31-0
Field
Value
PCS[63-32]PWRDNCLR
Description
Peripheral memory clock power-down clear.
0
Read: The peripheral memory clock[63-32] is active.
Write: The bit is unchanged.
1
Read: The peripheral memory clock[63-32] is inactive.
Write: The corresponding bit in the PCSPWRDWNSET1 and PCSPWRDWNCLR1 registers
is cleared to 0.
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2.5.3.17 Peripheral Power-Down Set Register 0 (PSPWRDWNSET0)
There is one bit for each quadrant for PS0 to PS7. Each bit of this register corresponds to the bit at the
same index in the corresponding PPROT register in that they relate to the same peripheral. These bits are
used to power down/power up the clock to the corresponding peripheral.
For every bit implemented in the PPROT register, there is one bit in the PSnPWRDWN register, except
when two peripherals (both in PS area) share buses. In that case, only one Power-Down bit is
implemented, at the position corresponding to that peripheral whose quadrant comes first (the lower
numbered).
The ways in which quadrants can be used within a frame are identical to what is described under
PPROTSET0, Section 2.5.3.5.
This arrangement is the same for bits of PS8 to PS31, presented in Section 2.5.3.18 - Section 2.5.3.24.
This register holds bits for PS0 to PS7. This register is shown in Figure 2-85 and described in Table 2101.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to nonimplemented bits have no effect and reads are 0.
Figure 2-85. Peripheral Power-Down Set Register 0 (PSPWRDWNSET0) [offset = 80h]
31
0
PS[7-0]QUAD[3-0]PWRDWNSET
R/WP-1
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 2-101. Peripheral Power-Down Set Register 0 (PSPWRDWNSET0) Field Descriptions
Bit
31-0
Field
PS[7-0]QUAD[3-0]
PWRDWNSET
Value
Description
Peripheral select quadrant clock power-down set.
0
Read: The clock to the peripheral select quadrant is active.
Write: The bit is unchanged.
1
Read: The clock to the peripheral select quadrant is inactive.
Write: The corresponding bit in PSPWRDWNSET0 and PSPWRDWNCLR0 registers is set
to 1.
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2.5.3.18 Peripheral Power-Down Set Register 1 (PSPWRDWNSET1)
There is one bit for each quadrant for PS8 to PS15. The protection scheme is described in
Section 2.5.3.17. This register is shown in Figure 2-86 and described in Table 2-102.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to nonimplemented bits have no effect and reads are 0.
Figure 2-86. Peripheral Power-Down Set Register 1 (PSPWRDWNSET1) [offset = 84h]
31
0
PS[15-8]QUAD[3-0]PWRDWNSET
R/WP-1
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 2-102. Peripheral Power-Down Set Register 1 (PSPWRDWNSET1) Field Descriptions
Bit
31-0
Field
Value
PS[15-8]QUAD[3-0]
PWRDWNSET
Description
Peripheral select quadrant clock power-down set.
0
Read: The clock to the peripheral select quadrant is active.
Write: The bit is unchanged.
1
Read: The clock to the peripheral select quadrant is inactive.
Write: The corresponding bit in PSPWRDWNSET1 and PSPWRDWNCLR1 registers is set
to 1.
2.5.3.19 Peripheral Power-Down Set Register 2 (PSPWRDWNSET2)
There is one bit for each quadrant for PS16 to PS23. The protection scheme is described in
Section 2.5.3.17. This register is shown in Figure 2-87 and described in Table 2-103.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to nonimplemented bits have no effect and reads are 0.
Figure 2-87. Peripheral Power-Down Set Register 2 (PSPWRDWNSET2) [offset = 88h]
31
0
PS[23-16]QUAD[3-0]PWRDWNSET
R/WP-1
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 2-103. Peripheral Power-Down Set Register 2 (PSPWRDWNSET2) Field Descriptions
Bit
31-0
Field
PS[23-16]QUAD[3-0]
PWRDWNSET
Value
Description
Peripheral select quadrant clock power-down set.
0
Read: The clock to the peripheral select quadrant is active.
Write: The bit is unchanged.
1
Read: The clock to the peripheral select quadrant is inactive.
Write: The corresponding bit in PSPWRDWNSET2 and PSPWRDWNCLR2 registers is set
to 1.
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2.5.3.20 Peripheral Power-Down Set Register 3 (PSPWRDWNSET3)
There is one bit for each quadrant for PS24 to PS31. The protection scheme is described in
Section 2.5.3.17. This register is shown in Figure 2-88 and described in Table 2-104.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to nonimplemented bits have no effect and reads are 0.
Figure 2-88. Peripheral Power-Down Set Register 3 (PSPWRDWNSET3) [offset = 8Ch]
31
0
PS[31-24]QUAD[3-0]PWRDWNSET
R/WP-1
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 2-104. Peripheral Power-Down Set Register 3 (PSPWRDWNSET3) Field Descriptions
Bit
31-0
Field
Value
PS[31-24]QUAD[3-0]
PWRDWNSET
Description
Peripheral select quadrant clock power-down set.
0
Read: The clock to the peripheral select quadrant is active.
Write: The bit is unchanged.
1
Read: The clock to the peripheral select quadrant is inactive.
Write: The corresponding bit in PSPWRDWNSET3 and PSPWRDWNCLR3 registers is set
to 1.
2.5.3.21 Peripheral Power-Down Clear Register 0 (PSPWRDWNCLR0)
There is one bit for each quadrant for PS0 to PS7. The protection scheme is described in
Section 2.5.3.17. This register is shown in Figure 2-89 and described in Table 2-105.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to nonimplemented bits have no effect and reads are 0.
Figure 2-89. Peripheral Power-Down Clear Register 0 (PSPWRDWNCLR0) [offset = A0h]
31
0
PS[7-0]QUAD[3-0]PWRDWNCLR
R/WP-1
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 2-105. Peripheral Power-Down Clear Register 0 (PSPWRDWNCLR0) Field Descriptions
Bit
31-0
Field
PS[7-0]QUAD[3-0]
PWRDWNCLR
Value
Description
Peripheral select quadrant clock power-down clear.
0
Read: The clock to the peripheral select quadrant is active.
Write: The bit is unchanged.
1
Read: The clock to the peripheral select quadrant is inactive.
Write: The corresponding bit in PSPWRDWNSET0 and PSPWRDWNCLR0 registers is
cleared to 0.
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2.5.3.22 Peripheral Power-Down Clear Register 1 (PSPWRDWNCLR1)
There is one bit for each quadrant for PS8 to PS15. The protection scheme is described in
Section 2.5.3.17. This register is shown in Figure 2-90 and described in Table 2-106.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to nonimplemented bits have no effect and reads are 0.
Figure 2-90. Peripheral Power-Down Clear Register 1 (PSPWRDWNCLR1) [offset = A4h]
31
0
PS[15-8]QUAD[3-0]PWRDWNCLR
R/WP-1
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 2-106. Peripheral Power-Down Clear Register 1 (PSPWRDWNCLR1) Field Descriptions
Bit
31-0
Field
Value
PS[15-8]QUAD[3-0]
PWRDWNCLR
Description
Peripheral select quadrant clock power-down clear.
0
Read: The clock to the peripheral select quadrant is active.
Write: The bit is unchanged.
1
Read: The clock to the peripheral select quadrant is inactive.
Write: The corresponding bit in PSPWRDWNSET1 and PSPWRDWNCLR1 registers is
cleared to 0.
2.5.3.23 Peripheral Power-Down Clear Register 2 (PSPWRDWNCLR2)
There is one bit for each quadrant for PS16 to PS23. The protection scheme is described in
Section 2.5.3.17. This register is shown in Figure 2-91 and described in Table 2-107.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to nonimplemented bits have no effect and reads are 0.
Figure 2-91. Peripheral Power-Down Clear Register 2 (PSPWRDWNCLR2) [offset = A8h]
31
0
PS[23-16]QUAD[3-0]PWRDWNCLR
R/WP-1
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 2-107. Peripheral Power-Down Clear Register 2 (PSPWRDWNCLR2) Field Descriptions
Bit
31-0
Field
PS[23-16]QUAD[3-0]
PWRDWNCLR
Value
Description
Peripheral select quadrant clock power-down clear.
0
Read: The clock to the peripheral select quadrant is active.
Write: The bit is unchanged.
1
Read: The clock to the peripheral select quadrant is inactive.
Write: The corresponding bit in PSPWRDWNSET2 and PSPWRDWNCLR2 registers is
cleared to 0.
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2.5.3.24 Peripheral Power-Down Clear Register 3 (PSPWRDWNCLR3)
There is one bit for each quadrant for PS24 to PS31. The protection scheme is described in
Section 2.5.3.17. This register is shown in Figure 2-92 and described in Table 2-108.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to nonimplemented bits have no effect and reads are 0.
Figure 2-92. Peripheral Power-Down Clear Register 3 (PSPWRDWNCLR) [offset = ACh]
31
0
PS[31-24]QUAD[3-0]PWRDWNCLR
R/WP-1
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 2-108. Peripheral Power-Down Clear Register 3 (PSPWRDWNCLR3) Field Descriptions
Bit
31-0
Field
PS[31-24]QUAD[3-0]
PWRDWNCLR
Value
Description
Peripheral select quadrant clock power-down clear.
0
Read: The clock to the peripheral select quadrant is active.
Write: The bit is unchanged.
1
Read: The clock to the peripheral select quadrant is inactive.
Write: The corresponding bit in PSPWRDWNSET3 and PSPWRDWNCLR3 registers is
cleared to 0.
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Chapter 3
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Power Management Module (PMM)
This chapter describes the power management module (PMM).
204
Topic
...........................................................................................................................
3.1
3.2
3.3
3.4
Overview .........................................................................................................
Power Domains ................................................................................................
PMM Operation.................................................................................................
PMM Registers .................................................................................................
Power Management Module (PMM)
Page
205
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208
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3.1
Overview
The microcontroller is part of the Hercules family of microcontrollers from Texas Instruments for safetycritical applications. Several functions are implemented on this microcontroller targeted towards varied
applications. The core logic is divided into several domains that can be independently turned on or off
based on the application’s requirements. This allows an application to reduce the leakage current for a
core domain that has modules that are not being used by the application.
This chapter describes the Power Management Module (PMM). The PMM provides memory-mapped
registers that control the states of the supported power domains. The PMM includes interfaces to the
Power Mode Controller (PMC) and the Power State Controller (PSCON). The PMC and PSCON control
the power up/down sequence of each power domain.
3.1.1 Main Features of the Power Management Module (PMM)
The main features of the PMM implemented on the microcontroller are:
• Supports 5 logic power domains: PD1, PD2, PD3, PD4 and PD5
Note that PD1 is an always-ON power domain and is not controlled by the PMM.
• Supports 3 memory-only power domains: RAM_PD1, RAM_PD2 and RAM_PD3
• Manages the clocks for each power domain
• Manages the resets to each power domain
• Includes failsafe compare logic to continuously monitor the states of each power domain
• Supports diagnostic and self-test logic to validate failsafe compare logic
3.1.2 Block Diagram
Figure 3-1. PMM Block Diagram
PMM
Wake Up Control
Self-test
PMC
Diagnostic
Register
Interface
PSCON
Diagnostic
Compare
Diagnostic
Diagnostic
PSCON(1)
PSCON(1)
Primary
PSCON(1)
Primary
PSCON(n)
Power
Domain(1)
Power
Domain(n)
Register
File
Clock
Management
System
Interface
Reset
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PMM consists of several key components:
• Register interface – the PMM control registers are mapped to the device memory space and start at
address 0xFFFF0000.
• System Interface – the PMM receives the clocks, resets, errors and all other control signals through
this interface.
• PSCON Diagnostic Compare – this block compares the outputs of each primary PSCON and the
respective diagnostic PSCON implemented for failsafe safety.
• Self-Test Diagnostic – this block contains the logic to place the PSCON diagnostic compare block in a
self-test mode in order to test the failsafe feature.
• Clock management – the PMM provides independent clock gating and handshaking controls for each
power domain and also generates the clock domains for each power domain.
• Reset Management – the PMM provides independent reset signals for each power domain.
• Power State Controller (PSCON) – The PSCON is a finite state machine that controls the power
sequence of a power domain from one state to another. Each power domain is controlled by one
dedicated PSCON.
• Power Domain – A power domain is a group of logic and/or memories which is separated from the
global power supply via power switches. These power switches are controlled by the PSCON and can
be turned on or off.
3.2
Power Domains
Figure 3-2 shows the core and memory power domains implemented on the microcontroller.
This device has 8 separate core power domains:
• PD1 is an always-ON domain and is not controlled by PMM. It contains the CPU as well as other
principal modules and the interconnect required for operation of the microcontroller. This domain also
includes 64KB of the tightly-coupled RAM. The PD1 can operate on its own even when all the other
core power domains are turned off by the PMM. Note that all I/Os are in this always-ON domain as
well.
Core power domains PD2 through PD5 and RAM_PD1 through RAM_PD3 are controlled by the PMM.
• PD2 contains the Embedded Trace Macrocell (ETM-R4), RAM Trace Port (RTP), and Data
Modification Module (DMM) components of the debug sub-system as well as the Parameter Overlay
Module (POM).
• PD3 contains some additional peripheral modules as an enhanced configuration over and above the
peripheral set available in PD1. These include a second High-End Timer (NHET2) with its dedicated
transfer unit (HTU2), a second Analog-to-Digital Converter (ADC2), a Serial Communication Interface
(SCI), an Inter-Integrated Circuit controller (I2C), a third Controller Area Network controller (DCAN3),
and a fourth Serial Peripheral Interface module (SPI4).
• PD4 contains the FlexRay controller and its dedicated transfer unit (FTU).
• PD5 contains the Ethernet controller (EMAC), the External Memory Interface (EMIF), as well as some
components of the interconnect fabric required by these modules.
• RAM_PD1, RAM_PD2 and RAM_PD3 each contain 64KB of tightly-coupled RAM.
NOTE: Switching of Power Domains
The microcontrollers only support static switching of the power domains. That is, the power
domains can be turned ON or OFF one time during device initialization. Once configured, it is
not allowed to change the state of a power domain without first asserting a system reset.
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TRACECTL
ETMDATA[31:0]
TRACECLKOUT
DMMSYNC
DMMDATA[15:0]
Color Legend for Power Domains
Core/RAM
always on
POM
HTU1
DMM
RAM
Core
#1
#2
ETM-R4
RTP
DMA
Dual Cortex-R4F
CPUs in Lockstep
TRACECLKIN
64K
64K
64K
DMMCLK
DMMnENA
256K
RAM
with
ECC
RTPnSYNC
RTPDATA[15:0]
RTPCLK
64K
3M
Flash
with
ECC
RTPnENA
Figure 3-2. Core Power Domains
#3
#1
#2
#4
#3
#5
FTU
EMAC
HTU2
Switched Central Resource Switched Central Resource Switched Central Resource
Main Cross Bar: Arbitration and Prioritization Control
64 KB Flash
for EEPROM
Emulation
with ECC
CRC
Peripheral Central Resource Bridge
Switched Central Resource
SYS
IOMM
EMAC Slaves
MDCLK
MDIO
MII_RXD[3:0]
MII_RXER
MII_TXD[3:0]
MII_TXEN
MII_TXCLK
MII_RXCLK
MII_CRS
MII_RXDV
MII_COL
ESM
EMIF_nWAIT
EMIF_CLK
EMIF_CKE
EMIF_nCS[4:2]
EMIF_nCS[0]
EMIF_ADDR[21:0]
EMIF_BA[1:0]
EMIF_DATA[15:0]
EMIF_nDQM[1:0]
EMIF_nOE
EMIF_nWE
EMIF_nRAS
EMIF_nCAS
EMIF_RnW
MDIO
MII
EMIF
PMM
DCAN1
DCAN2
VIM
DCAN3
MibSPI1
RTI
MibADC2
N2HET1
N2HET2
GIO
DCC1
SPI2
DCC2
MibSPI3
FlexRay
I2C
I2C_SCL
I2C_SDA
FRAY_RX2
FRAY_TX2
FRAY_TXEN2
FRAY_RX1
FRAY_TX1
FRAY_TXEN1
GIOA[7:0]
GIOB[7:0]
N2HET2_PIN_nDIS
N2HET2[18,16]
N2HET2[15:0]
N2HET1[31:0]
N2HET1_PIN_nDIS
ADREFLO
AD2EVT
VCCAD
VSSAD
ADREFHI
AD2IN[15:0]
ADREFLO
AD1EVT
AD1IN[7:0]
AD1IN[23:8]
MibSPI5
VCCAD
VSSAD
ADREFHI
nERROR
CAN1_RX
CAN1_TX
CAN2_RX
CAN2_TX
CAN3_RX
CAN3_TX
MIBSPI1_CLK
MIBSPI1_SIMO[1:0]
MIBSPI1_SOMI[1:0]
MIBSPI1_nCS[5:0]
MIBSPI1_nENA
SPI4
MibADC1
nPORRST
nRST
ECLK
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LIN
SCI
SPI2_CLK
SPI2_SIMO
SPI2_SOMI
SPI2_nCS[1:0]
SPI2_nENA
MIBSPI3_CLK
MIBSPI3_SIMO
MIBSPI3_SOMI
MIBSPI3_nCS[5:0]
MIBSPI3_nENA
SPI4_CLK
SPI4_SIMO
SPI4_SOMI
SPI4_nCS
SPI4_nENA
MIBSPI5_CLK
MIBSPI5_SIMO[3:0]
MIBSPI5_SOMI[3:0]
MIBSPI5_nCS[3:0]
MIBSPI5_nENA
LIN_RX
LIN_TX
SCI_RX
SCI_TX
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PMM Operation
It is important to understand some fundamental concepts beforehand.
3.3.1 Power Switch
A power domain gets its power supply via a power switch. The power switch creates a link between the
global core supply plane and the local switchable power domain supply. Each power domain uses multiple
power switches, which are daisy-chained together.
3.3.2 Power Domain State
Each core power domain can be in one of three states: Active, Idle, or Off.
In the active state, a power domain is fully powered with normal supply voltage.
In the idle state, all clocks to a power domain are turned off (driven low). The supply voltage is still
maintained at the normal level.
In the off state, a power domain is completely cut off from the power supply.
3.3.3 Default Power Domain State
The default state of each power domain, except for PD1, is controlled by TI during production testing via
programmation of individual bits within the reset configuration word in the TI-OTP sector of flash bank 0.
This allows each power domain to default to either the active state or the off state.
3.3.4 Disabling a Power Domain Permanently
TI can also permanently disable any power domain, except for PD1. This is also controlled by
programmation of individual bits within the reset configuration word in the TI-OTP sector of flash bank 0.
3.3.5 Changing Power Domain State
A domain can only change state when commanded by the application. Each domain has an associated 4bit key to define the intended power state. When the correct key is programmed, the PMM initiates the
sequence to transition that domain to the commanded state.
A power state transition is considered complete only when every single power switch for that domain has
switched over to the commanded state.
3.3.5.1
Turning a Power Domain Off
It is necessary to turn off all clocks going to a power domain before that domain can be powered down.
PMM contains the hardware interlocks to handle this. Each power domain has an associated memorymapped register which allows the application to turn off clocks to that power domain.
Steps to power down a domain with logic – PD2, PD3, PD4, PD5:
1. Write to the PDCLK_DISx register to disable all clocks to the power domain.
2. Write 0xA to the LOGICPDPWRCTRL0 register to power down each domain.
3. Poll for LOGICPDPWRSTATx.LOGICPDPWR_STATx to become “00”. The power domain is now
powered down.
A power domain with only SRAM macros does not have a clock input, so the sequence is shorter. This
applies to RAM_PD1, RAM_PD2 and RAM_PD3 power domains shown in Figure 3-2:
1. Write the correct key to the MEMPDONx register to power down the domain.
2. Poll for MEMPDPWRSTATx.MEMPDPWR_STATx to become “00”. The power domain is now powered
down.
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3.3.5.2
Turning a Power Domain On
A power domain can be turned on by writing the correct key to the LOGICPDPWRCTRL0.LOGICPDONx
or MEMPDPWRCTRL0.MEMPDONx. PMM will automatically restart the clocks to the power domain once
the power is restored if the “automatic clock enable upon wake up” option is selected. If this option is not
selected, the application can turn on clocks to the power domain by clearing the PDCLK_DIS register. The
application must poll the LOGICPDPWRSTATx.DOMAIN_ONx to ensure that the power has been fully
restored before enabling the clocks.
NOTE: if a power domain is permanently disabled by TI, then the application cannot turn that power
domain back on. No error is generated if the application attempts to do so.
3.3.6 Reset Management
PMM handles the reset sequence for each power domain. When a power domain is turned on from an off
state, the PMM will reset the power domain to ensure that all logic begins in its default reset state.
PMM generates nPORRST (power-on reset), nRST (system reset), nPRST (peripheral reset), and nTRST
(test / debug logic reset) for each domain.
3.3.7 Diagnostic Power State Controller (PSCON)
Each power domain state is controlled by a primary PSCON. There is a second PSCON as well for each
power domain. This is the diagnostic PSCON. All power management inputs to a power domain are
controlled only by the primary PSCON. All power management outputs from the power domain are fed
back to both the primary and the diagnostic PSCON.
The PMM commands both the PSCON identically so that they are always in a lock-step operating mode. A
dedicated compare unit checks the outputs of the two PSCON modules on every cycle.
3.3.8 PSCON Compare Block
The diagnostic compare block can operate in one of four modes:
3.3.8.1
Lock-Step Mode
This is the default mode of operation of the PSCON compare block. The PSCON diagnostic compare
block compares the outputs from the two PSCONs on every cycle. Any mismatch in the PSCON outputs is
indicated as a PSCON compare error. This error signal is mapped to the Error Signaling Module’s (ESM)
Group1 channel 38. The application can define the response to this error.
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Self-Test Mode
A self-test mechanism is provided to check the PSCON compare logic for faults. The compare error signal
output is disabled in self-test mode. The PSCON diagnostic compare block generates two types of
patterns during self-test mode: compare match test followed by compare mismatch test. During the selftest, each test pattern is applied on both PSCON signal ports of the PSCON diagnostic compare block
and then is clocked for one cycle. The duration of the self-test is 24 cycles. Any detected fault is indicated
as a self-test error, mapped to ESM group1 channel 39. If no fault is detected, the self-test complete flag
is set.
The application can poll for this flag to be set and then switch the mode of the PSCON compare block
back to lock-step mode by writing to the mode key register.
NOTE: PSCON operation when compare block is in self-test mode
When the PSCON compare block is in its self-test mode, both PSCONs continue to function
normally. However, there is no comparison done on the PSCON outputs.
Compare match test:
An identical vector is applied to both input ports at the same time, thereby expecting a compare match. If
the compare unit produces a mismatch then the self-test error flag is set and the self-test error signal is
generated. The compare match test is terminated if a compare mismatch is detected. The compare match
test takes 4 cycles to complete when the test passes.
Compare mismatch test:
A vector with all 1's is applied to the PSCON diagnostic compare block’s primary input port and the same
input is also applied to the secondary input port but with one bit flipped starting from bit position 0. The
unequal vectors should cause the PSCON diagnostic compare block to generate a compare mismatch at
bit position 0. In case a mismatch is not detected, a self-test error is indicated. This compare mismatch
test algorithm is repeated until every single bit position is verified on both PSCON signal ports.
3.3.8.3
Error-Forcing Mode
This mode is designed specifically to ensure that the error signal output from the PSCON compare block
is not stuck inactive. In this mode, a test pattern is applied to the PSCON related inputs of the compare
logic to force an error. During error forcing mode, both the error signal and the self-test error signal will be
asserted to the ESM. The application can clear flags for ESM group1 channel 38 and ESM group1
channel 39 once the error is flagged. If the two ESM flags do not get set, this indicates that the PSCON
compare error signal is stuck inactive and cannot be relied upon to detect a PSCON mismatch.
3.3.8.4
Self-Test Error-Forcing Mode
In this mode, an error is forced so that the self-test error output from the PSCON compare block is
activated. The application can clear the flag for ESM group1 channel 39 once the error is flagged. If the
ESM group1 channel 39 flag does not get set, this indicates that the PSCON compare block self-test error
signal is stuck inactive and there is no self-test mechanism available for the PSCON compare block.
3.3.8.5
PMM Operation During CPU Halt Debug Mode
No compare errors are generated when the CPU is halted in debug mode, regardless of the mode of the
diagnostic compare block. No status flags are updated in this mode. Normal operation of the compare
block is resumed once the CPU exits the debug mode.
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3.4
PMM Registers
Table 3-1 shows a summary of the control registers in the PMM module. The registers support 32-bit, 16bit and 8-bit accesses. The address offset is specified from the base address of FFFF 0000h. Any access
to an unimplemented location within the PMM register frame will generate a bus error that results in an
Abort exception.
Table 3-1. PMM Registers
Offset
00h
04h-0Ch
10h
14h-1Ch
Acronym
Register Description
Section
LOGICPDPWRCTRL0
Logic Power Domain Control Register 0
Reserved
Reserved
MEMPDPWRCTRL0
Memory Power Domain Control Register 0
Section 3.4.1
Section 3.4.2
Reserved
Reserved
20h
PDCLKDISREG
Power Domain Clock Disable Register
Section 3.4.3
24h
PDCLKDISSETREG
Power Domain Clock Disable Set Register
Section 3.4.4
28h
PDCLKDISCLRREG
Power Domain Clock Disable Clear Register
Section 3.4.5
30h-3Ch
Reserved
Reserved
40h
LOGICPDPWRSTAT0
Logic Power Domain PD2 Power Status Register
Section 3.4.6
44h
LOGICPDPWRSTAT1
Logic Power Domain PD3 Power Status Register
Section 3.4.7
48h
LOGICPDPWRSTAT2
Logic Power Domain PD4 Power Status Register
Section 3.4.8
4Ch
LOGICPDPWRSTAT3
Logic Power Domain PD5 Power Status Register
Section 3.4.9
Reserved
Reserved
80h
MEMPDPWRSTAT0
Memory Power Domain RAM_PD1 Power Status Register
Section 3.4.10
84h
MEMPDPWRSTAT1
Memory Power Domain RAM_PD2 Power Status Register
Section 3.4.11
88h
MEMPDPWRSTAT2
Memory Power Domain RAM_PD3 Power Status Register
Section 3.4.12
Reserved
Reserved
A0h
GLOBALCTRL1
Global Control Register 1
Section 3.4.13
A8h
GLOBALSTAT
Global Status Register
Section 3.4.14
ACh
PRCKEYREG
PSCON Diagnostic Compare Key Register
Section 3.4.15
B0h
LPDDCSTAT1
LogicPD PSCON Diagnostic Compare Status Register 1
Section 3.4.16
B4h
LPDDCSTAT2
LogicPD PSCON Diagnostic Compare Status Register 2
Section 3.4.17
B8h
MPDDCSTAT1
Memory PD PSCON Diagnostic Compare Status Register 1
Section 3.4.18
BCh
MPDDCSTAT2
Memory PD PSCON Diagnostic Compare Status Register 2
Section 3.4.19
C0h
ISODIAGSTAT
Isolation Diagnostic Status Register
Section 3.4.20
50h-7Fh
8Ch-9Fh
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3.4.1 Logic Power Domain Control Register (LOGICPDPWRCTRL0)
The default values of the control fields are determined by the device reset configuration word stored in the
TI-OTP region of flash bank 0.
Figure 3-3. Logic Power Domain Control Register (LOGICPDPWRCTRL0) [offset = 00h]
31
28
27
24
23
20
19
16
Reserved
LOGICPDON0
Reserved
LOGICPDON1
R-0
R/WP-n
R-0
R/WP-n
15
12
11
8
7
4
3
0
Reserved
LOGICPDON2
Reserved
LOGICPDON3
R-0
R/WP-n
R-0
R/WP-n
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 3-2. Logic Power Domain Control Register (LOGICPDPWRCTRL0) Field Descriptions
Bit
Field
31-28
Reserved
27-24
LOGICPDON0
Value
0
Description
Read returns 0. Writes have no effect.
Read in User and Privileged Mode. Write in Privileged Mode only.
Ah
Read: Power domain PD2 is in OFF state.
Write: Power domain PD2 is commanded to switch to OFF state.
9h
Any other value
Reserved
Read: Power domain PD2 is in Active state.
Write: Power domain PD2 is commanded to switch to Active state.
23-20
Reserved
19-16
LOGICPDON1
0
Read returns 0. Writes have no effect.
Read in User and Privileged Mode. Write in Privileged Mode only.
Ah
Read: Power domain PD3 is in OFF state.
Write: Power domain PD3 is commanded to switch to OFF state.
9h
Any other value
Reserved
Read: Power domain PD3 is in Active state.
Write: Power domain PD3 is commanded to switch to Active state.
15-12
Reserved
11-8
LOGICPDON2
0
Read returns 0. Writes have no effect.
Read in User and Privileged Mode. Write in Privileged Mode only.
Ah
Read: Power domain PD4 is in OFF state.
Write: Power domain PD4 is commanded to switch to OFF state.
9h
Any other value
Reserved
Read: Power domain PD4 is in Active state.
Write: Power domain PD4 is commanded to switch to Active state.
7-4
Reserved
3-0
LOGICPDON3
0
Read returns 0. Writes have no effect.
Read in User and Privileged Mode. Write in Privileged Mode only.
Ah
Read: Power domain PD5 is in OFF state.
Write: Power domain PD5 is commanded to switch to OFF state.
9h
Any other value
Reserved
Read: Power domain PD5 is in Active state.
Write: Power domain PD5 is commanded to switch to Active state.
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3.4.2 Memory Power Domain Control Register 0 (MEMPDPWRCTRL0)
The default values of the control fields are determined by the device reset configuration word stored in the
TI-OTP region of flash bank 0.
Figure 3-4. Memory Power Domain Control Register 0 (MEMPDPWRCTRL0) [offset = 10h]
31
28
27
24
23
20
19
16
Reserved
MEMPDON0
Reserved
MEMPDON1
R-0
R/WP-n
R-0
R/WP-n
15
12
11
8
7
0
Reserved
MEMPDON2
Reserved
R-0
R/WP-n
R-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 3-3. Memory Power Domain Control Register 0 (MEMPDPWRCTRL0) Field Descriptions
Bit
Field
31-28
Reserved
27-24
MEMPDON0
Value
0
Description
Read returns 0. Writes have no effect.
Read in User and Privileged Mode. Write in Privileged Mode only.
Ah
Read: Power domain RAM_PD1 is in OFF state.
Write: Power domain RAM_PD1 is commanded to switch to OFF state.
9h
Any other value
Reserved
Read: Power domain RAM_PD1 is in Active state.
Write: Power domain RAM_PD1 is commanded to switch to Active state.
23-20
Reserved
19-16
MEMPDON1
0
Read returns 0. Writes have no effect.
Read in User and Privileged Mode. Write in Privileged Mode only.
Ah
Read: Power domain RAM_PD2 is in OFF state.
Write: Power domain RAM_PD2 is commanded to switch to OFF state.
9h
Any other value
Reserved
Read: Power domain RAM_PD2 is in Active state.
Write: Power domain RAM_PD2 is commanded to switch to Active state.
15-12
Reserved
11-8
MEMPDON2
0
Read returns 0. Writes have no effect.
Read in User and Privileged Mode. Write in Privileged Mode only.
Ah
Read: Power domain RAM_PD3 is in OFF state.
Write: Power domain RAM_PD3 is commanded to switch to OFF state.
9h
Any other value
Reserved
Read: Power domain RAM_PD3 is in Active state.
Write: Power domain RAM_PD3 is commanded to switch to Active state.
7-0
Reserved
0
Read returns 0. Writes have no effect.
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3.4.3 Power Domain Clock Disable Register (PDCLKDISREG)
The default values of the control fields are determined by the device reset configuration word stored in the
TI-OTP region of flash bank 0.
Figure 3-5. Power Domain Clock Disable Register (PDCLKDISREG) [offset = 20h]
31
8
Reserved
R-0
7
3
2
1
0
Reserved
4
PDCLK_DIS[3]
PDCLK_DIS[2]
PDCLK_DIS[1]
PDCLK_DIS[0]
R-0
R/WP-n
R/WP-n
R/WP-n
R/WP-n
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 3-4. Power Domain Clock Disable Register (PDCLKDISREG) Field Descriptions
Bit
Field
31-4 Reserved
3
2
1
0
214
Value
0
PDCLK_DIS[3]
Description
Read returns 0. Writes have no effect.
Read in User and Privileged Mode returns the current value of PDCLK_DIS[3]. Write in Privileged
Mode only.
0
Enable clocks to logic power domain PD5.
1
Disable clocks to logic power domain PD5.
PDCLK_DIS[2]
Read in User and Privileged Mode returns the current value of PDCLK_DIS[2]. Write in Privileged
Mode only
0
Enable clocks to logic power domain PD4.
1
Disable clocks to logic power domain PD4.
PDCLK_DIS[1]
Read in User and Privileged Mode returns the current value of PDCLK_DIS[1]. Write in Privileged
Mode only.
0
Enable clocks to logic power domain PD3.
1
Disable clocks to logic power domain PD3.
PDCLK_DIS[0]
Read in User and Privileged Mode returns the current value of PDCLK_DIS[0]. Write in Privileged
Mode only.
0
Enable clocks to logic power domain PD2.
1
Disable clocks to logic power domain PD2.
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3.4.4 Power Domain Clock Disable Set Register (PDCLKDISSETREG)
The default values of the control fields are determined by the device reset configuration word stored in the
TI-OTP region of flash bank 0.
Figure 3-6. Power Domain Clock Disable Set Register (PDCLKDISSETREG) [offset = 24h]
31
8
Reserved
R-0
7
4
Reserved
3
2
1
0
PDCLK_DISSET[3] PDCLK_DISSET[2] PDCLK_DISSET[1] PDCLK_DISSET[0]
R-0
R/WP-n
R/WP-n
R/WP-n
R/WP-n
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 3-5. Power Domain Clock Disable Set Register (PDCLKDISSETREG) Field Descriptions
Bit
Field
31-4 Reserved
3
2
1
0
Value
0
PDCLK_DISSET[3]
Description
Read returns 0. Writes have no effect.
Read in User and Privileged Mode returns the current value of PDCLK_DISSET[3]. Write in
Privileged Mode only.
0
No effect to state of clocks to power domain PD5.
1
Disable clocks to logic power domain PD5.
PDCLK_DISSET[2]
Read in User and Privileged Mode returns the current value of PDCLK_DISSET[2]. Write in
Privileged Mode only.
0
No effect to state of clocks to power domain PD4.
1
Disable clocks to logic power domain PD4.
PDCLK_DISSET[1]
Read in User and Privileged Mode returns the current value of PDCLK_DISSET[1]. Write in
Privileged Mode only.
0
No effect to state of clocks to power domain PD3.
1
Disable clocks to logic power domain PD3.
PDCLK_DISSET[0]
Read in User and Privileged Mode returns the current value of PDCLK_DISSET[0]. Write in
Privileged Mode only.
0
No effect to state of clocks to power domain PD2.
1
Disable clocks to logic power domain PD2.
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3.4.5 Power Domain Clock Disable Clear Register (PDCLKDISCLRREG)
The default values of the control fields are determined by the device reset configuration word stored in the
TI-OTP region of flash bank 0.
Figure 3-7. Power Domain Clock Disable Clear Register (PDCLKDISCLRREG) [offset = 28h]
31
8
Reserved
R-0
7
4
Reserved
3
2
1
0
PDCLK_DISCLR[3] PDCLK_DISCLR[2] PDCLK_DISCLR[1] PDCLK_DISCLR[0]
R-0
R/WP-n
R/WP-n
R/WP-n
R/WP-n
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 3-6. Power Domain Clock Disable Clear Register (PDCLKDISCLRREG) Field Descriptions
Bit
Field
31-4 Reserved
3
2
1
0
216
Value
0
PDCLK_DISCLR[3]
Description
Read returns 0. Writes have no effect.
Read in User and Privileged Mode returns the current value of PDCLK_DIS[3]. Write in Privileged
Mode only.
0
No effect to state of clocks to power domain PD5.
1
Enable clocks to logic power domain PD5.
PDCLK_DISCLR[2]
Read in User and Privileged Mode returns the current value of PDCLK_DIS[2]. Write in Privileged
Mode only.
0
No effect to state of clocks to power domain PD4.
1
Enable clocks to logic power domain PD4.
PDCLK_DISCLR[1]
Read in User and Privileged Mode returns the current value of PDCLK_DIS[1]. Write in Privileged
Mode only.
0
No effect to state of clocks to power domain PD3.
1
Enable clocks to logic power domain PD3.
PDCLK_DISCLR[0]
Read in User and Privileged Mode returns the current value of PDCLK_DIS[0]. Write in Privileged
Mode only.
0
No effect to state of clocks to power domain PD2.
1
Enable clocks to logic power domain PD2.
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3.4.6 Logic Power Domain PD2 Power Status Register (LOGICPDPWRSTAT0)
This is a read-only register. All writes are ignored.
The default values of the control fields are determined by the device reset configuration word stored in the
TI-OTP region of flash bank 0.
Figure 3-8. Logic Power Domain PD2 Power Status Register (LOGICPDPWRSTAT0)
[offset = 40h]
31
25
24
23
17
16
Reserved
LOGIC IN
TRANS0
Reserved
MEM IN
TRANS0
R-0
R-n
R-0
R-n
15
9
8
7
DOMAIN
ON0
Reserved
R-0
R-n
2
Reserved
1
0
LOGICPDPWR
STAT0
R-0
R-n
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 3-7. Logic Power Domain PD2 Power Status Register (LOGICPDPWRSTAT0)
Field Descriptions
Bit
31-25
24
Field
Reserved
Value
0
LOGIC IN TRANS0
Description
Read returns 0. Writes have no effect.
Logic in transition status for power domain PD2.
Read in User and Privileged Mode.
23-17
16
Reserved
0
Logic in power domain PD2 is in the steady Active or OFF state.
1
Logic in power domain PD2 is in the process of power-down/up.
0
Read returns 0. Writes have no effect.
MEM IN TRANS0
Memory in transition status for power domain PD2.
Read in User and Privileged Mode.
15-9
8
Reserved
0
Memory in power domain PD2 is in the steady Active or OFF state.
1
Memory in power domain PD2 is in the process of power-down/up.
0
Read returns 0. Writes have no effect.
DOMAIN ON0
Current state of power domain PD2.
Read in User and Privileged Mode.
7-2
Reserved
1-0
LOGICPDPWR STAT0
0
Power domain PD2 is in the OFF state.
1
Power domain PD2 is in the Active state.
0
Read returns 0. Writes have no effect.
Logic power domain PD2 power state.
Read in User and Privileged Mode.
0
Logic power domain PD2 is switched OFF.
1h
Logic power domain PD2 is in the Idle state.
2h
Reserved
3h
Logic power domain PD2 is in the Active state.
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3.4.7 Logic Power Domain PD3 Power Status Register (LOGICPDPWRSTAT1)
This is a read-only register. All writes are ignored.
The default values of the control fields are determined by the device reset configuration word stored in the
TI-OTP region of flash bank 0.
Figure 3-9. Logic Power Domain PD3 Power Status Register (LOGICPDPWRSTAT1)
[offset = 44h]
31
25
24
23
17
16
Reserved
LOGIC IN
TRANS1
Reserved
MEM IN
TRANS1
R-0
R-n
R-0
R-n
15
9
8
7
DOMAIN
ON1
Reserved
R-0
2
1
0
Reserved
LOGICPDPWR
STAT1
R-0
R-n
R-n
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 3-8. Logic Power Domain PD3 Power Status Register (LOGICPDPWRSTAT1)
Field Descriptions
Bit
Field
31-25
24
Reserved
Value
0
LOGIC IN TRANS1
Description
Read returns 0. Writes have no effect.
Logic in transition status for power domain PD3.
Read in User and Privileged Mode.
23-17
16
Reserved
0
Logic in power domain PD3 is in the steady Active or OFF state.
1
Logic in power domain PD3 is in the process of power-down/up.
0
Read returns 0. Writes have no effect.
MEM IN TRANS1
Memory in transition status for power domain PD3.
Read in User and Privileged Mode.
15-9
8
Reserved
0
Memory in power domain PD3 is in the steady Active or OFF state.
1
Memory in power domain PD3 is in the process of power-down/up.
0
Read returns 0. Writes have no effect.
DOMAIN ON1
Current state of power domain PD3.
Read in User and Privileged Mode.
7-2
Reserved
1-0
LOGICPDPWR STAT1
0
Power domain PD3 is in the OFF state.
1
Power domain PD3 is in the Active state.
0
Read returns 0. Writes have no effect.
Logic power domain PD3 power state.
Read in User and Privileged Mode.
218
0
Logic power domain PD3 is switched OFF.
1h
Logic power domain PD3 is in the Idle state.
2h
Reserved
3h
Logic power domain PD3 is in the Active state.
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3.4.8 Logic Power Domain PD4 Power Status Register (LOGICPDPWRSTAT2)
This is a read-only register. All writes are ignored.
The default values of the control fields are determined by the device reset configuration word stored in the
TI-OTP region of flash bank 0.
Figure 3-10. Logic Power Domain PD4 Power Status Register (LOGICPDPWRSTAT2)
[offset = 48h]
31
25
24
23
17
16
Reserved
LOGIC IN
TRANS2
Reserved
MEM IN
TRANS2
R-0
R-n
R-0
R-n
15
9
8
7
DOMAIN
ON2
Reserved
R-0
R-n
2
Reserved
1
0
LOGICPDPWR
STAT2
R-0
R-n
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 3-9. Logic Power Domain PD4 Power Status Register (LOGICPDPWRSTAT2)
Field Descriptions
Bit
31-25
24
Field
Reserved
Value
0
LOGIC IN TRANS2
Description
Read returns 0. Writes have no effect.
Logic in transition status for power domain PD4.
Read in User and Privileged Mode.
23-17
16
Reserved
0
Logic in power domain PD4 is in the steady Active or OFF state.
1
Logic in power domain PD4 is in the process of power-down/up.
0
Read returns 0. Writes have no effect.
MEM IN TRANS2
Memory in transition status for power domain PD4.
Read in User and Privileged Mode.
15-9
8
Reserved
0
Memory in power domain PD4 is in the steady Active or OFF state.
1
Memory in power domain PD4 is in the process of power-down/up.
0
Read returns 0. Writes have no effect.
DOMAIN ON2
Current state of power domain PD4.
Read in User and Privileged Mode.
7-2
Reserved
1-0
LOGICPDPWR STAT2
0
Power domain PD4 is in the OFF state.
1
Power domain PD4 is in the Active state.
0
Read returns 0. Writes have no effect.
Logic power domain PD4 power state.
Read in User and Privileged Mode.
0
Logic power domain PD4 is switched OFF.
1h
Logic power domain PD4 is in the Idle state.
2h
Reserved
3h
Logic power domain PD4 is in the Active state.
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3.4.9 Logic Power Domain PD5 Power Status Register (LOGICPDPWRSTAT3)
This is a read-only register. All writes are ignored.
The default values of the control fields are determined by the device reset configuration word stored in the
TI-OTP region of flash bank 0.
Figure 3-11. Logic Power Domain PD5 Power Status Register (LOGICPDPWRSTAT3)
[offset = 4Ch]
31
25
24
23
17
16
Reserved
LOGIC IN
TRANS3
Reserved
MEM IN
TRANS3
R-0
R-n
R-0
R-n
15
9
8
7
DOMAIN
ON3
Reserved
R-0
R-n
2
1
0
LOGICPDPWR
STAT3
Reserved
R-0
R-n
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 3-10. Logic Power Domain PD5 Power Status Register (LOGICPDPWRSTAT3)
Field Descriptions
Bit
Field
31-25
24
Reserved
Value
0
LOGIC IN TRANS3
Description
Read returns 0. Writes have no effect.
Logic in transition status for power domain PD5.
Read in User and Privileged Mode.
23-17
16
Reserved
0
Logic in power domain PD5 is in the steady Active or OFF state.
1
Logic in power domain PD5 is in the process of power-down/up.
0
Read returns 0. Writes have no effect.
MEM IN TRANS3
Memory in transition status for power domain PD5.
Read in User and Privileged Mode.
15-9
8
Reserved
0
Memory in power domain PD5 is in the steady Active or OFF state.
1
Memory in power domain PD5 is in the process of power-down/up.
0
Read returns 0. Writes have no effect.
DOMAIN ON3
Current state of power domain PD5.
Read in User and Privileged Mode.
7-2
Reserved
1-0
LOGICPDPWR STAT3
0
Power domain PD5 is in the OFF state.
1
Power domain PD5 is in the Active state.
0
Read returns 0. Writes have no effect.
Logic power domain PD5 power state.
Read in User and Privileged Mode.
220
0
Logic power domain PD5 is switched OFF.
1h
Logic power domain PD5 is in the Idle state.
2h
Reserved
3h
Logic power domain PD5 is in the Active state.
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3.4.10 Memory Power Domain RAM_PD1 Power Status Register (MEMPDPWRSTAT0)
This is a read-only register. All writes are ignored.
The default values of the control fields are determined by the device reset configuration word stored in the
TI-OTP region of flash bank 0.
Figure 3-12. Memory Power Domain RAM_PD1 Power Status Register (MEMPDPWRSTAT0)
[offset = 80h]
31
25
24
23
17
16
Reserved
LOGIC IN
TRANS0
Reserved
MEM IN
TRANS0
R-0
R-n
R-0
R-n
15
9
8
7
DOMAIN
ON0
Reserved
R-0
2
Reserved
R-n
R-0
1
0
MEMPDPWR
STAT0
R-n
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 3-11. Memory Power Domain RAM_PD1 Power Status Register (MEMPDPWRSTAT0)
Field Descriptions
Bit
31-25
24
Field
Reserved
Value
0
LOGIC IN TRANS0
Description
Read returns 0. Writes have no effect.
Logic in transition status for power domain RAM_PD1. This power domain only contains
SRAM macros. However, an SRAM macro also has some digital logic controlled by the
PSCON. Therefore, a memory power domain also contains a logic status indicator.
Read in User and Privileged Mode.
23-17
16
Reserved
0
Logic in power domain RAM_PD1 is in the steady Active or OFF state.
1
Logic in power domain RAM_PD1 is in the process of power-down/up.
0
Read returns 0. Writes have no effect.
MEM IN TRANS0
Memory in transition status for power domain RAM_PD1.
Read in User and Privileged Mode.
15-9
8
Reserved
0
Memory in power domain RAM_PD1 is in the steady Active or OFF state.
1
Memory in power domain RAM_PD1 is in the process of power-down/up.
0
Read returns 0. Writes have no effect.
DOMAIN ON0
Current state of power domain RAM_PD1.
Read in User and Privileged Mode.
7-2
Reserved
1-0
MEMPDPWR STAT0
0
Power domain RAM_PD1 is in the OFF state.
1
Power domain RAM_PD1 is in the Active state.
0
Read returns 0. Writes have no effect.
Memory power domain RAM_PD1 power state.
Read in User and Privileged Mode.
0
Memory power domain RAM_PD1 is switched OFF.
1h
Reserved
2h
Reserved
3h
Memory power domain RAM_PD1 is in the Active state.
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3.4.11 Memory Power Domain RAM_PD2 Power Status Register (MEMPDPWRSTAT1)
This is a read-only register. All writes are ignored.
The default values of the control fields are determined by the device reset configuration word stored in the
TI-OTP region of flash bank 0.
Figure 3-13. Memory Power Domain RAM_PD2 Power Status Register (MEMPDPWRSTAT1)
[offset = 84h]
31
25
24
23
17
16
Reserved
LOGIC IN
TRANS1
Reserved
MEM IN
TRANS1
R-0
R-n
R-0
R-n
15
9
8
7
DOMAIN
ON1
Reserved
R-0
2
Reserved
R-n
1
0
MEMPDPWR
STAT1
R-0
R-n
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 3-12. Memory Power Domain RAM_PD2 Power Status Register (MEMPDPWRSTAT1)
Field Descriptions
Bit
Field
31-25
24
Reserved
Value
0
LOGIC IN TRANS1
Description
Read returns 0. Writes have no effect.
Logic in transition status for power domain RAM_PD2. This power domain only contains
SRAM macros. However, an SRAM macro also has some digital logic controlled by the
PSCON. Therefore, a memory power domain also contains a logic status indicator.
Read in User and Privileged Mode.
23-17
16
Reserved
0
Logic in power domain RAM_PD2 is in the steady Active or OFF state.
1
Logic in power domain RAM_PD2 is in the process of power-down/up.
0
Read returns 0. Writes have no effect.
MEM IN TRANS1
Memory in transition status for power domain RAM_PD2.
Read in User and Privileged Mode.
15-9
8
Reserved
0
Memory in power domain RAM_PD2 is in the steady Active or OFF state.
1
Memory in power domain RAM_PD2 is in the process of power-down/up.
0
Read returns 0. Writes have no effect.
DOMAIN ON1
Current state of power domain RAM_PD2.
Read in User and Privileged Mode.
7-2
Reserved
1-0
MEMPDPWR STAT1
0
Power domain RAM_PD2 is in the OFF state.
1
Power domain RAM_PD2 is in the Active state.
0
Read returns 0. Writes have no effect.
Memory power domain RAM_PD2 power state.
Read in User and Privileged Mode.
222
0
Memory power domain RAM_PD2 is switched OFF.
1h
Reserved
2h
Reserved
3h
Memory power domain RAM_PD2 is in the Active state.
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3.4.12 Memory Power Domain RAM_PD3 Power Status Register (MEMPDPWRSTAT2)
This is a read-only register. All writes are ignored.
The default values of the control fields are determined by the device reset configuration word stored in the
TI-OTP region of flash bank 0.
Figure 3-14. Memory Power Domain RAM_PD3 Power Status Register (MEMPDPWRSTAT2)
[offset = 88h]
31
25
24
23
17
16
Reserved
LOGIC IN
TRANS2
Reserved
MEM IN
TRANS2
R-0
R-n
R-0
R-n
15
9
8
7
DOMAIN
ON2
Reserved
R-0
2
Reserved
R-n
R-0
1
0
MEMPDPWR
STAT2
R-n
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 3-13. Memory Power Domain RAM_PD3 Power Status Register (MEMPDPWRSTAT2)
Field Descriptions
Bit
31-25
24
Field
Reserved
Value
0
LOGIC IN TRANS2
Description
Read returns 0. Writes have no effect.
Logic in transition status for power domain RAM_PD3. This power domain only contains
SRAM macros. However, an SRAM macro also has some digital logic controlled by the
PSCON. Therefore, a memory power domain also contains a logic status indicator.
Read in User and Privileged Mode.
23-17
16
Reserved
0
Logic in power domain RAM_PD3 is in the steady Active or OFF state.
1
Logic in power domain RAM_PD3 is in the process of power-down/up.
0
Read returns 0. Writes have no effect.
MEM IN TRANS2
Memory in transition status for power domain RAM_PD3.
Read in User and Privileged Mode.
15-9
8
Reserved
0
Memory in power domain RAM_PD3 is in the steady Active or OFF state.
1
Memory in power domain RAM_PD3 is in the process of power-down/up.
0
Read returns 0. Writes have no effect.
DOMAIN ON2
Current state of power domain RAM_PD3.
Read in User and Privileged Mode.
7-2
Reserved
1-0
MEMPDPWR STAT2
0
Power domain RAM_PD3 is in the OFF state.
1
Power domain RAM_PD3 is in the Active state.
0
Read returns 0. Writes have no effect.
Memory power domain RAM_PD3 power state.
Read in User and Privileged Mode.
0
Memory power domain RAM_PD3 is switched OFF.
1h
Reserved
2h
Reserved
3h
Memory power domain RAM_PD3 is in the Active state.
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3.4.13 Global Control Register 1 (GLOBALCTRL1)
Figure 3-15. Global Control Register 1 (GLOBALCTRL1) [offset = A0h]
31
16
Reserved
R-0
15
9
Reserved
8
PMCTRL PWRDN
R-0
7
R/WP-0
1
0
Reserved
AUTO CLK WAKE ENA
R-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 3-14. Global Control Register 1 (GLOBALCTRL1) Field Descriptions
Bit
Field
31-9 Reserved
8
Value
0
PMCTRL PWRDN
Description
Read returns 0. Writes have no effect.
PMC/PSCON Power Down
Read in User and Privileged Mode returns current value of PMCTRL PWRDN. Write in
Privileged mode only.
7-1
0
Reserved
0
Enable the clock to pmctrl_wakeup block.
1
Disable the clock to pmctrl_wakeup block, which contains PMC and all PSCONs.
0
Read returns 0. Writes have no effect.
AUTO CLK WAKE ENA
Automatic Clock Enable on Wake Up
Read in User and Privileged Mode returns current value of AUTO CLK WAKE ENA. Write in
Privileged mode only.
224
0
Disable automatic clock wake up. The application must enable clocks by clearing the correct
bit in the PDCLK_DIS register.
1
Enable automatic clock wake up when a power domain transitions to Active state.
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3.4.14 Global Status Register (GLOBALSTAT)
Figure 3-16. Global Status Register (GLOBALSTAT) [offset = A8h]
31
16
Reserved
R-0
15
1
0
Reserved
PMCTRL IDLE
R-0
R-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 3-15. Global Status Register (GLOBALSTAT) Field Descriptions
Bit
Field
Value
31-1 Reserved
0
0
PMCTRL IDLE
Description
Read returns 0. Writes have no effect.
State of PMC and all PSCONs. The PMM captures the status of PMC and PSCONs as they do not
have a register interface to the host CPU.
0
PMC and PSCONs for all power domains are in the process of generating power state transition
control sequence for logic and/or SRAM.
1
PMC and PSCONs for all power domains have completed generating power state transition control
sequence triggered by PMC input control signals.
3.4.15 PSCON Diagnostic Compare Key Register (PRCKEYREG)
Figure 3-17. PSCON Diagnostic Compare Key Register (PRCKEYREG) [offset = ACh]
31
16
Reserved
R-0
15
4
3
0
Reserved
MKEY
R-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 3-16. PSCON Diagnostic Compare Key Register (PRCKEYREG) Field Descriptions
Bit
Field
31-4 Reserved
3-0
Value
0
MKEY
Description
Read returns 0. Writes have no effect.
Diagnostic PSCON Mode Key. The mode key is applied to all individual PSCON compare units.
Read in User and Privileged mode returns the current value of MKEY. Write in Privileged mode only.
0
Lock Step mode
6h
Self-test mode
9h
Error Forcing mode
Fh
Self-test Error Forcing Mode
All others Lock Step mode
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3.4.16 LogicPD PSCON Diagnostic Compare Status Register 1 (LPDDCSTAT1)
Figure 3-18. LogicPD PSCON Diagnostic Compare Status Register 1 (LPDDCSTAT1)
[offset = B0h]
31
24
Reserved
R-0
23
19
18
17
16
Reserved
20
LCMPE[3]
LCMPE[2]
LCMPE[1]
LCMPE[0]
R-0
R/W1CP-0
R/W1CP-0
R/W1CP-0
R/W1CP-0
15
8
Reserved
R-0
7
3
2
1
0
Reserved
4
LSTC[3]
LSTC[2]
LSTC[1]
LSTC[0]
R-0
R-0
R-0
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; W1CP = Write 1 to clear in privilege mode only; -n = value after reset
Table 3-17. LogicPD PSCON Diagnostic Compare Status Register 1 (LPDDCSTAT1)
Field Descriptions
Bit
Field
31-20
Reserved
19-16
LCMPE[3-0]
Value
0
Description
Read returns 0. Writes have no effect.
Logic Power Domain Compare Error
Each of these bits corresponds to a logic power domain:
Bit 3 for PD5,
Bit 2 for PD4,
Bit 1 for PD3,
Bit 0 for PD2.
Read in User and Privileged Mode. Write in Privileged mode only.
0
Read: PSCON signals are identical.
Write: Writing 0 has no effect.
1
Read: PSCON signal compare mismatch identified.
Write: Clears the corresponding LCMPE bit, if set.
15-4
Reserved
3-0
LSTC[3-0]
0
Read returns 0. Writes have no effect.
Logic Power Domain Self-test Complete
Each of these bits corresponds to a logic power domain:
Bit 3 for PD5,
Bit 2 for PD4,
Bit 1 for PD3,
Bit 0 for PD2.
Read in User and Privileged Mode. Writes have no effect.
226
0
Self-test is ongoing if self-test mode is entered.
1
Self-test is complete.
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3.4.17 LogicPD PSCON Diagnostic Compare Status Register 2 (LPDDCSTAT2)
Figure 3-19. LogicPD PSCON Diagnostic Compare Status Register 2 (LPDDCSTAT2)
[offset = B4h]
31
24
Reserved
R-0
23
19
18
17
16
Reserved
20
LSTET[3]
LSTET[2]
LSTET[1]
LSTET[0]
R-0
R-0
R-0
R-0
R-0
15
8
Reserved
R-0
7
3
2
1
0
Reserved
4
LSTE[3]
LSTE[2]
LSTE[1]
LSTE[0]
R-0
R-0
R-0
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 3-18. LogicPD PSCON Diagnostic Compare Status Register 2 (LPDDCSTAT2)
Field Descriptions
Bit
Field
31-20
Reserved
19-16
LSTET[3-0]
Value
0
Description
Read returns 0. Writes have no effect.
Logic Power Domain Self-test Error Type
Each of these bits corresponds to a logic power domain:
Bit 3 for PD5,
Bit 2 for PD4,
Bit 1 for PD3,
Bit 0 for PD2.
Read in User and Privileged Mode. Writes have no effect.
15-4
Reserved
3-0
LSTE[3-0]
0
Self-test failed during compare match test.
1
Self-test failed during compare mismatch test.
0
Read returns 0. Writes have no effect.
Logic Power Domain Self-test Error
Each of these bits corresponds to a logic power domain:
Bit 3 for PD5,
Bit 2 for PD4,
Bit 1 for PD3,
Bit 0 for PD2.
Read in User and Privileged Mode. Writes have no effect.
0
Self-test passed.
1
Self-test failed.
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3.4.18 Memory PD PSCON Diagnostic Compare Status Register 1 (MPDDCSTAT1)
This register shows the interrupt status (before enabling) and allows setting of the interrupt status.
Figure 3-20. Memory PD PSCON Diagnostic Compare Status Register 1 (MPDDCSTAT1)
[offset = B8h]
31
24
Reserved
R-0
23
18
17
16
Reserved
19
MCMPE[2]
MCMPE[1]
MCMPE[0]
R-0
R/W1CP-0
R/W1CP-0
R/W1CP-0
15
8
Reserved
R-0
7
2
1
0
Reserved
3
MSTC[2]
MSTC[1]
MSTC[0]
R-0
R-0
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; W1CP = Write 1 to clear in privilege mode only; -n = value after reset
Table 3-19. Memory PD PSCON Diagnostic Compare Status Register 1 (MPDDCSTAT1)
Field Descriptions
Bit
Field
31-19
Reserved
18-16
MCMPE[2-0]
Value
0
Description
Read returns 0. Writes have no effect.
Memory Power Domain Compare Error
Each of these bits corresponds to a memory power domain:
Bit 2 for RAM_PD3,
Bit 1 for RAM_PD2,
Bit 0 for RAM_PD1.
Read in User and Privileged Mode. Write in Privileged mode only.
0
Read: PSCON signals are identical.
Write: Writing 0 has no effect.
1
Read: PSCON signal compare mismatch identified.
Write: Clears the corresponding MCMPE bit, if set.
15-3
Reserved
2-0
MSTC[2-0]
0
Read returns 0. Writes have no effect.
Memory Power Domain Self-test Complete
Each of these bits corresponds to a memory power domain:
Bit 2 for RAM_PD3,
Bit 1 for RAM_PD2,
Bit 0 for RAM_PD1.
Read in User and Privileged Mode. Writes have no effect.
228
0
Self-test is ongoing if self-test mode is entered.
1
Self-test is complete.
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3.4.19 Memory PD PSCON Diagnostic Compare Status Register 2 (MPDDCSTAT2)
Figure 3-21. Memory PD PSCON Diagnostic Compare Status Register 2 (MPDDCSTAT2)
[offset = BCh]
31
24
Reserved
R-0
23
18
17
16
Reserved
19
MSTET[2]
MSTET[1]
MSTET[0]
R-0
R-0
R-0
R-0
15
8
Reserved
R-0
7
2
1
0
Reserved
3
MSTE[2]
MSTE[1]
MSTE[0]
R-0
R-0
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 3-20. Memory PD PSCON Diagnostic Compare Status Register 2 (MPDDCSTAT2)
Field Descriptions
Bit
Field
31-19
Reserved
18-16
MSTET[2-0]
Value
0
Description
Read returns 0. Writes have no effect.
Memory Power Domain Self-test Error Type
Each of these bits corresponds to a memory power domain:
Bit 2 for RAM_PD3,
Bit 1 for RAM_PD2,
Bit 0 for RAM_PD1.
Read in User and Privileged Mode. Writes have no effect.
15-3
Reserved
2-0
MSTE[2-0]
0
Self-test failed during compare match test.
1
Self-test failed during compare mismatch test.
0
Read returns 0. Writes have no effect.
Memory Power Domain Self-test Error
Each of these bits corresponds to a memory power domain:
Bit 2 for RAM_PD3,
Bit 1 for RAM_PD2,
Bit 0 for RAM_PD1.
Read in User and Privileged Mode. Writes have no effect.
0
Self-test passed.
1
Self-test failed.
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3.4.20 Isolation Diagnostic Status Register (ISODIAGSTAT)
There is an ISO_DIAG cell implemented separately for each logic power domain. This is a special tie-off
cell that reads a value of 1 when the logic power domain is powered up. This cell has an isolation value of
0. That is, when this logic power domain is turned off, this cell will read 0. The ISO_DIAG statuses for
each logic power domain is reflected in the ISODIAGSTAT register. The application can poll this
diagnostic register to make sure that a domain that has been commanded to turn off has actually received
the command.
Figure 3-22. Isolation Diagnostic Status Register (ISODIAGSTAT) [offset = C0h]
31
8
Reserved
R-0
3
2
1
0
Reserved
4
ISO DIAG[3]
ISO DIAG[2]
ISO DIAG[1]
ISO DIAG[0]
R-0
R-0
R-0
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 3-21. Isolation Diagnostic Status Register (ISODIAGSTAT) Field Descriptions
Bit
Field
31-4 Reserved
3-0
Value
0
ISO DIAG[3-0]
Description
Read returns 0. Writes have no effect.
Isolation Diagnostic
Each of these bits corresponds to a logic power domain:
Bit 3 for PD5,
Bit 2 for PD4,
Bit 1 for PD3,
Bit 0 for PD2.
Read in User and Privileged Mode. Writes have no effect.
230
0
Isolation is enabled for corresponding power domain.
1
Isolation is disabled for corresponding power domain.
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Chapter 4
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I/O Multiplexing and Control Module (IOMM)
This chapter describes the I/O Multiplexing and Control Module (IOMM).
Topic
...........................................................................................................................
4.1
4.2
4.3
4.4
4.5
4.6
Overview ........................................................................................................
Main Features of I/O Multiplexing Module (IOMM) ................................................
Control of Multiplexed Functions .......................................................................
Safety Features ...............................................................................................
IOMM Registers ................................................................................................
Signal Multiplexing and Control .........................................................................
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232
232
232
236
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231
Overview
4.1
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Overview
This chapter describes the overall features of the module which controls the I/O multiplexing on the
device. The mapping of control registers to multiplexing options is specified in Section 4.6.
4.2
Main Features of I/O Multiplexing Module (IOMM)
The IOMM contains memory-mapped registers (MMR) that control device-specific multiplexed functions.
The safety and diagnostic features of the IOMM are:
• Kicker mechanism to protect the MMRs from accidental writes
• Error indication for access violations
4.3
Control of Multiplexed Functions
Several functions are multiplexed on this microcontroller. The following sections describe the multiplexing
scheme and its implementation.
4.3.1 Control of Multiplexed Outputs
The signal multiplexing controlled by each memory-mapped control register (PINMMRn) is described in
Table 4-16. Each byte in the PINMMRs control the functionality output on a single terminal. Consider the
following example for the PINMMR10 control register.
Figure 4-1. PINMMR10 Control Register, Address = FFFF EB38h
31
26
25
24
Reserved
EMIF DATA[2]
ETM DATA[18]
RWP-0
R/WP-0
R/WP-1
23
17
16
Reserved
18
RTP DATA[15]
EMIF nCS[0]
RWP-0
R/WP-0
R/WP-1
15
9
8
Reserved
10
EMIF DATA[3]
ETM DATA[19]
RWP-0
R/WP-0
R/WP-1
7
2
1
0
Reserved
3
RMII_RX_ER
MII_RX_ER
AD1 EVT
RWP-0
R/WP-0
R/WP-0
R/WP-1
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
•
•
•
Consider the multiplexing controlled by PINMMR10[15–8]. These bits control the multiplexing between
the ETMDATA[19] and EMIF_DATA[3] on the ball N15 of the 337BGA package for this device. The
default function on the N15 ball is ETMDATA[19]. This is indicated by bit 8 of the PINMMR10 register
being set.
If the application wants to use N15 as an EMIF_DATA[3] signal, then bit 8 of PINMMR10 must be
cleared and bit 9 must be set.
Each feature of the output function is determined by the function selected to be output on a terminal.
For example, the ball N15 on the 337BGA package is driven by an output buffer with an 8mA drive
strength and which supports the adaptive impedance control mode for reduced electromagnetic emissions.
This output buffer has the following signals: A (signal to be output), GZ (output enable), SBEN (Standard
Buffer Enable) and LPM (Low Power Mode). Each of these signals is an output of a multiplexor which
allows the selected function to control all available features of the output buffer.
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•
The PINMMR control registers are used to implement a one-hot encoding scheme for selecting the
multiplexed function.
– For example, for the N15 ball on the 337BGA package for this device at least one out of bit 8 or bit
9 must be set.
– If the application clears both bits 8 and 9, then the default function will be selected for output on
N15.
– If the application sets both bits 8 and 9, then the default function will be selected for output on N15.
– If the application sets one ore more reserved bit(s) within the byte 15–8, then the default function
will be selected for output on N15.
Figure 4-2 shows the multiplexing between the output functions for the N15 ball. This terminal uses an
8mA low-EMI output buffer.
Figure 4-2. Output Multiplexing Example
PINMMR10[8, 9]
8mA low-EMI output buffer
TIED ZERO
GZ
EMIF_DATA[3]_nEN
ETM_DATA[19]
A
Y
EMIF_DATA[3]
pad
not(GPREG1.7) for ETM
SBEN
not(GPREG1.6) for EMIF
Notes on Figure 4-2:
• ETM_DATA[19] is an output-only signal. Therefore the GZ is tied to zero when the ETM functionality is
selected to be output on this pad.
• The low-EMI mode controls for the EMIF and ETM signals are independent. These controls are
multiplexed and chosen as per the function being output on this pad.
4.3.2 Control of Multiplexed Inputs
The microcontrollers are available in two package options – 337-ball grid array (BGA) and 144-pin Quad
Flat Pack (QFP). Input multiplexing is not required for the 337BGA package except for GIOB[2] and all the
SPI4 signals. For the 144QFP package, some signals have a multiplexor implemented on their input side.
The selection between the two input paths is done by a combination of two control registers. These
registers are described in Table 4-1.
Table 4-1. Input Multiplexing on 144QFP Parts
Signal
144QFP Dedicated
Input Pin #
144QFP Multiplexed
Input Pin #
SPI4SIMO
–
SPI4SOMI
–
SPI4CLK
SPI4NENA
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Control Register Bit A
Control Register Bit B
30
PINMMR5[9]
PINMMR23[16]
31
PINMMR5[17]
PINMMR23[24]
–
25
PINMMR5[1]
PINMMR23[8]
–
23
PINMMR4[17]
PINMMR24[0]
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Table 4-1. Input Multiplexing on 144QFP Parts (continued)
Signal
144QFP Dedicated
Input Pin #
144QFP Multiplexed
Input Pin #
Control Register Bit A
Control Register Bit B
SPI4NCS[0]
–
24
PINMMR4[25]
PINMMR24[8]
N2HET1[17]
–
130
PINMMR20[17]
PINMMR24[16]
N2HET1[19]
–
40
PINMMR8[9]
PINMMR24[24]
N2HET1[23]
–
96
PINMMR12[17]
PINMMR25[8]
N2HET1[25]
–
37
PINMMR7[9]
PINMMR25[16]
N2HET1[27]
–
4
PINMMR0[26]
PINMMR25[24]
N2HET1[29]
–
3
PINMMR0[18]
PINMMR26[0]
N2HET1[31]
–
54
PINMMR9[10]
PINMMR26[8]
GIOB[2]
142
55
PINMMR29[16]
PINMMR29[16]
For signals with a “–” in the column for dedicated input pin #, these signals do have a dedicated pad on
the die. The default input for these signals comes from the dedicated pad. To be able to drive in the input
from the multiplexed pins on the 144QFP package, the IOMM registers need to be configured.
Table 4-2. Input Multiplexing on 337BGA Parts
Signal
337BGA Dedicated
Input Ball #
337BGA
Multiplexed Input
Ball #
SPI4SIMO
–
SPI4SOMI
–
Control Register Bit A
Control Register Bit B
W5
PINMMR5[9]
PINMMR23[16]
V6
PINMMR5[17]
PINMMR23[24]
SPI4CLK
–
K18
PINMMR5[1]
PINMMR23[8]
SPI4NENA
–
V2
PINMMR4[17]
PINMMR24[0]
SPI4NCS[0]
–
U1
PINMMR4[25]
PINMMR24[8]
GIOB[2]
F2
V10
PINMMR29[16]
PINMMR29[16]
Table 4-1 and Table 4-2 show two controls for selecting the input path for each of these signals: A and B.
A indicates the control register bit to be set to enable the corresponding signal to be output on the
multiplexed pin.
B is another control register bit that is used to select between the dedicated input terminal and the
multiplexed pin.
• The input to a module comes from the multiplexed pin when the condition [ A and not(B) ] = TRUE.
• The input to a module comes from the dedicated pad when the condition [ not(A) or (A and B) ] =
TRUE.
NOTE: Inputs are broadcast to all multiplexed functions
The input signals are broadcast to all modules hooked up to a terminal. The application must
ensure that modules that are not being used in the application do not react to a change on
their input functions. e.g. a GIO signal toggle can trigger an interrupt request, when the
application actually is using the function multiplexed with this GIO signal.
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Figure 4-3. Input Multiplexing Example
dedicated SPI4CLK pad
Combination of PINMMR5[1]
and PINMMR23[8]
SPI4
SPI4CLK_IN
multiplexed SPI4CLK pad
to other input functions
multiplexed with SPI4CLK
4.3.3 Control of Special Multiplexed Options
PINMMR29 and PINMMR30 registers are used to control some specific device functions.
• EMIF_CLK Control:
PINMMR29[8] is set by default. This is used to block the EMIF_CLK from being output from the
microcontroller. If the EMIF is used to connect to an external SDRAM module, then the application must
enable the EMIF_CLK output by clearing the PINMMR29[8] bit.
• Control for other EMIF Signals:
Bit 31 of the system module control register GPREG1 at address 0xFFFFFFA0 is used to gate off the
EMIF module outputs: EMIF_ADDR[0], EMIF_ADDR[1], EMIF_ADDR[6], EMIF_ADDR[7], EMIF_ADDR[8],
EMIF_BA[1], EMIF_nCS[0], EMIF_nCS[3]. These 8 signals are multiplexed with NHET2 signals. By
default, these terminals are tri-stated and pulled down. Any application that requires the EMIF functionality
must set GPREG1[31]. This allows these 8 EMIF module outputs to be driven on to the assigned balls.
• Ethernet Controller Mode Control:
PINMMR29[24] is set by default. This bit is used to enable the Reduced Media Independent Interface of
the Ethernet controller. If the application desires to use the Media Independent Interface of the Ethernet
controller, then the PINMMR29[24] must be cleared.
• ADC Trigger Control:
The microcontrollers contain two Analog-to-Digital Converter (ADC) modules. The ADC conversions can
be started using a rising or falling or both edges as the trigger event. Both the ADC modules support up to
eight event trigger inputs. There are two sets of these 8 inputs for each ADC. The first set is the default
set and is selected by setting the PINMMR30[0]. The PINMMR30[0] is also set by default. The alternate
set of 8 event trigger options are selected by clearing PINMMR30[0] bit.
• Generating Interrupt when fault is indicated to N2HET2
The N2HET modules on this microcontroller support a mechanism to respond to faults indicated on their
PIN_nDIS inputs. This input for the N2HET2 module is connected to the MibSPI3_nCS[0]/AD2EVT
terminal. When this terminal is driven low, the N2HET2 can be configured to tri-state all PWMs output from
the N2HET2. It is very useful to be able to generate an interrupt to the host CPU when this happens.
Therefore, the MibSPI3_nCS[0] / AD2EVT signal is also available to be connected to the GIOB[2] signal.
This device also contains a dedicated terminal for the GIOB[2] signal. This necessitates a multiplexor on
the input connection to the GIOB[2]. This multiplexor's selection is controlled by PINMMR29[16]. When
PINMMR29[16] is cleared (0, default), the connection to the GIOB[2] comes from the dedicated terminal.
When PINMMR29[16] is set, the connection to the GIOB[2] comes from the MibSPI3_nCS[0] / AD2EVT
terminal. Enabling this connection to the GIOB[2] allows the application to generate a GIO interrupt to the
host CPU when the external fault monitor circuitry drives the MibSPI3_nCS[0] / AD2EVT terminal low to
indicate a fault condition to the N2HET2 module.
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Safety Features
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Safety Features
The IOMM supports certain safety functions that are designed to prevent unintentional changes to the I/O
multiplexing configuration. These are described in the following sections.
4.4.1 Locking Mechanism for Memory-Mapped Registers
The IOMM contains a mechanism to prevent any spurious writes from changing any of the IOMM control
register values. The control registers other than the KICK0 and KICK1 registers are locked by default and
after any system reset. None of the IOMM control registers can be written under this condition. The
application can read any of the IOMM registers regardless of the state of the locking mechanism.
• Enabling Write Access to the IOMM Registers
To enable write access to the IOMM registers other than Kick0 and Kick1 registers, the CPU must write
0x83e70b13 to the kick0 register followed by a write of 0x95a4f1e0 to the kick1 register.
• Disabling Write Access to the IOMM Registers
It is recommended to disable write access to the IOMM registers once the I/O multiplexing configuration is
completed. This can be done by:
• writing any other data value to either of the kick registers, or
• restarting the unlock sequence by writing 0x83e70b13 to the kick0 register, and not writing the
correct key to the kick1 register
NOTE: No Error On Write to Locked IOMM Registers
There is no error response on any write accesses to the IOMM registers when write access
is disabled. None of the IOMM registers change state due to this write.
4.4.2 Error Conditions
The IOMM generates one error signal that is mapped to the Error Signaling Module’s Group 1, channel
37. This error signal is generated under either of the following two conditions:
• Address Error – occurs when there is a read or a write access to an non-implemented memory location
within the IOMM register frame.
• Protection Error – occurs when the CPU writes to an IOMM register while not in a privileged mode of
operation.
The application can read the Error Raw Status register (Section 4.5.5) to determine the actual cause of
the error.
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4.5
IOMM Registers
Table 4-3 shows a summary of the control registers in the IOMM. The address offset is specified from the
base address of FFFF EA00h.
Table 4-3. IOMM Registers
Offset
Acronym
Register Description
00h
REVISION_REG
Revision Register
Section 4.5.1
Section
20h
ENDIAN_REG
Device Endianness Register
Section 4.5.2
38h
KICK_REG0
Kicker Register 0
Section 4.5.3
3Ch
KICK_REG1
Kicker Register 1
Section 4.5.4
E0h
ERR_RAW_STATUS_REG
Error Raw Status / Set Register
Section 4.5.5
E4h
ERR_ENABLED_STATUS_REG
Error Enabled Status / Clear Register
Section 4.5.6
E8h
ERR_ENABLE_REG
Error Signaling Enable Register
Section 4.5.7
ECh
ERR_ENABLE_CLR_REG
Error Signaling Enable Clear Register
Section 4.5.8
F4h
FAULT_ADDRESS_REG
Fault Address Register
Section 4.5.9
F8h
FAULT_STATUS_REG
Fault Status Register
Section 4.5.10
FCh
FAULT_CLEAR_REG
Fault Clear Register
Section 4.5.11
PINMMRnn
Pin Multiplexing Control Registers
Section 4.5.12
B10h-B88h
4.5.1 REVISION_REG: Revision Register
This is a read-only register that provides the revision information about the I/O Multiplexing Module
(IOMM).
Figure 4-4. REVISION_REG: Revision Register (Address = FFFFEA00h)
31
30
29
28
27
16
REV SCHEME
Reserved
REV MODULE
R-01
R-0
R-E84h
15
11
10
8
7
6
5
0
REV RTL
REV MAJOR
REV CUSTOM
REV MINOR
R-0
R-001
R-0
R-2h
LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset
Table 4-4. Revision Register Field Descriptions
Bit
Field
Value
Description
31-30 REV SCHEME
01
Revision Scheme
29-28 Reserved
0
Reads return zeros, writes have no effect.
27-16 REV MODULE
15-11 REV RTL
E84h
0
RTL Revision
10-8
REV MAJOR
7-6
REV CUSTOM
0
Custom Revision
5-0
REV MINOR
2h
Minor Revision
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Major Revision
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4.5.2 ENDIAN_REG: Device Endianness Register
This is a read-only register that reflects the state of the device endianness.
Figure 4-5. ENDIAN_REG: Device Endianness Register (Address = FFFFEA20h)
31
16
Reserved
R-0
15
1
0
Reserved
ENDIAN
R-0
R-D
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; R-D = Value read is determined by external configuration
Table 4-5. Device Endianness Register Field Descriptions
Bit
Field
31-1
Reserved
0
ENDIAN
238
Value
0
Description
Reads return zeros, writes have no effect.
Device endianness
0
Device is configured in little-endian mode.
1
Device is configured in big-endian mode.
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4.5.3 KICK_REG0: Kicker Register 0
This register forms the first part of the unlock sequence for being able to update the I/O multiplexing
control registers (PINMMRnn).
Figure 4-6. KICK_REG0: Kicker Register 0 (Address = FFFFEA38h)
31
16
KICK0
R/W-0
15
0
KICK0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 4-6. Kicker Register 0 Field Descriptions
Bit
Field
Value
31-0
KICK0
0
Description
Kicker 0 Register. The value 83E7 0B13h must be written to KICK0 as part of the process to unlock the
CPU write access to the PINMMRnn registers.
4.5.4 KICK_REG1: Kicker Register 1
This register forms the second part of the unlock sequence for being able to update the I/O multiplexing
control registers (PINMMRnn).
Figure 4-7. KICK_REG1: Kicker Register 1 (Address = FFFFEA3Ch)
31
16
KICK1
R/W-0
15
0
KICK1
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 4-7. Kicker Register 1 Field Descriptions
Bit
Field
Value
31-0
KICK1
0
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Description
Kicker 1 Register. The value 95A4 F1E0h must be written to the KICK1 as part of the process to unlock
the CPU write access to the PINMMRnn registers.
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4.5.5 ERR_RAW_STATUS_REG: Error Raw Status / Set Register
This register shows the status of the error conditions (before enabling) and allows setting the error status.
The IOMM module error signal is connected to the device's Error Signaling Module (ESM) group1 channel
37. The application can choose to generate an interrupt whenever this ESM channel flag gets set. This
interrupt service routine can then read this Error Raw Status Register to determine the actual cause of the
error condition.
The Error Raw Status register is also writable by the application in order to test the ESM signaling and
interrupt generation mechanism.
Figure 4-8. ERR_RAW_STATUS_REG: Error Raw Status / Set Register (Address = FFFFEAE0h)
31
8
Reserved
R-0
7
1
0
Reserved
2
ADDR_ERR
PROT_ERR
R-0
R/WP-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 4-8. Error Raw Status / Set Register Field Descriptions
Bit
31-2
1
Field
Reserved
Value
0
ADDR_ERR
Description
Read returns zeros, writes have no effect.
Addressing Error Status. An Addressing Error occurs when an unimplemented location inside the IOMM
register frame is accessed.
0
Read: Addressing Error has not occurred.
Write: Writing 0 has no effect.
1
Read: Addressing Error has been detected.
Write: Addressing Error status is set.
0
PROT_ERR
Protection Error Status. A Protection Error occurs when any control register inside the IOMM is written
in the CPU's user mode of operation.
0
Read: Protection Error has not occurred.
Write: Writing 0 has no effect.
1
Read: Protection Error has been detected.
Write: Protection Error status is set.
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4.5.6 ERR_ENABLED_STATUS_REG: Error Enabled Status / Clear Register
This register shows the status of the error conditions and allows clearing of the error status.
Figure 4-9. ERR_ENABLED_STATUS_REG: Error Enabled Status / Clear Register
(Address = FFFFEAE4h)
31
8
Reserved
R-0
7
2
Reserved
R-0
1
0
ENABLED_
ADDR_ERR
ENABLED_
PROT_ERR
R/WP-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 4-9. Error Signaling Enabled Status / Clear Register Field Descriptions
Bit
31-2
1
Field
Reserved
Value
0
ENABLED_ADDR_ERR
Description
Read returns zeros, writes have no effect.
Addressing Error Signaling Enable and Status Clear
0
Read: Addressing Error Signaling is disabled.
Write: Writing 0 has no effect.
1
Read: Addressing Error Signaling is enabled.
Write: Addressing Error status is cleared.
0
ENABLED_PROT_ERR
Protection Error Signaling Enable and Status Clear
0
Read: Protection Error Signaling is disabled.
Write: Writing 0 has no effect.
1
Read: Protection Error Signaling is enabled.
Write: Protection Error status is cleared.
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4.5.7 ERR_ENABLE_REG: Error Signaling Enable Register
This register shows the interrupt enable status and allows enabling of the interrupts.
Figure 4-10. ERR_ENABLE_REG: Error Signaling Enable Register (Address = FFFFEAE8h)
31
8
Reserved
R-0
7
2
Reserved
1
ADDR_ERR_EN
R-0
R/WP-0
0
PROT_ERR_EN
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 4-10. Error Enable Register Field Descriptions
Bit
31-2
1
Field
Reserved
Value
0
ADDR_ERR_EN
Description
Read returns zeros, writes have no effect.
Addressing Error Signaling Enable
0
Read: Addressing Error Signaling is disabled.
Write: Writing 0 has no effect.
1
Read: Addressing Error Signaling is enabled.
Write: Addressing Error Signaling is enabled.
0
PROT_ERR_EN
Protection Error Signaling Enable
0
Read: Protection Error Signaling is disabled.
Write: Writing 0 has no effect.
1
Read: Protection Error Signaling is enabled.
Write: Protection Error Signaling is enabled.
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4.5.8 ERR_ENABLE_CLR_REG: Error Signaling Enable Clear Register
This register shows the error signaling enable status and allows disabling of the error signaling.
Figure 4-11. ERR_ENABLE_CLR_REG: Error Signaling Enable Clear Register
(Address = FFFFEAECh)
31
8
Reserved
R-0
7
1
0
Reserved
2
ADDR_ERR_
EN_CLR
PROT_ERR_
EN_CLR
R-0
R/WP-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 4-11. Interrupt Enable Clear Register Field Descriptions
Bit
31-2
1
Field
Value
Reserved
0
ADDR_ERR_EN_CLR
Description
Read returns zeros, writes have no effect.
Addressing Error Signaling Enable Clear
0
Read: Addressing Error signaling is disabled.
Write: Writing 0 has no effect.
1
Read: Addressing Error signaling is enabled.
Write: Addressing Error signaling is disabled.
0
PROT_ERR_EN_CLR
Protection Error Signaling Enable Clear
0
Read: Protection Error signaling is disabled.
Write: Writing 0 has no effect.
1
Read: Protection Error signaling is enabled.
Write: Protection Error signaling is disabled.
4.5.9 FAULT_ADDRESS_REG: Fault Address Register
This register holds the address offset of the first fault transfer.
Figure 4-12. FAULT_ADDRESS_REG: Fault Address Register (Address = FFFFEAF4h)
31
16
Reserved
R-0
15
9
8
0
Reserved
FAULT_ADDR
R-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 4-12. Fault Address Register Field Descriptions
Bit
Field
Value
Description
31-9
Reserved
0
Read returns zeros, writes have no effect.
8-0
FAULT_ADDR
0
Fault Address. The fault address offset in case of an address error or a protection error
condition.
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4.5.10 FAULT_STATUS_REG: Fault Status Register
This register holds the status and attributes of the first fault transfer.
Figure 4-13. FAULT_STATUS_REG: Fault Status Register (Address = FFFFEAF8h)
31
28
27
24
23
16
Reserved
FAULT_ID
FAULT_MSTID
R-0
R-0
R-0
15
13
Reserved
12
9
FAULT_PRIVID
R-0
R-0
8
7
6
Rsvd
Rsvd
Rsvd
R-0
R-0
R-0
5
0
FAULT_TYPE
R-0
LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset
Table 4-13. Fault Status Register Field Descriptions
Bit
Field
31-28
Reserved
27-24
FAULT_ID
23-16
FAULT_MSTID
15-13
Reserved
12-9
FAULT_PRIVID
8-6
Reserved
5-0
FAULT_TYPE
244
Value
0
Description
Reads return zeros, writes have no effect.
Faulting Transaction ID
ID of Master that initiated the faulting transaction
0
Reads return zeros, writes have no effect.
Faulting Privilege ID
0
Reads return zeros, writes have no effect.
Type of fault detected
0
No fault
1h
User execute fault
2h
User write fault
4h
User read fault
8h
Supervisor execute fault
10h
Supervisor write fault
20h
Supervisor read fault
I/O Multiplexing and Control Module (IOMM)
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4.5.11 FAULT_CLEAR_REG: Fault Clear Register
This register allows the application to clear the current fault so that another can be captured when 1 is
written to this register.
Figure 4-14. FAULT_CLEAR_REG: Fault Clear Register (Address = FFFFEAFCh )
31
16
Reserved
R-0
15
1
0
Reserved
FAULT_CLEAR
R-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 4-14. FAULT_CLEAR_REG: Fault Clear Register Field Descriptions
Bit
31-1
0
Field
Value
Reserved
0
FAULT_CLEAR
Description
Reads return zeros, writes have no effect.
Fault Clear
0
Read: Current value of the FAULT_CLEAR bit is 0.
Write: Writing 0 has no effect.
1
Read: Current value of the FAULT_CLEAR bit is 1.
Write: Writing a 1 clears the current fault.
4.5.12 PINMMRnn: Pin Multiplexing Control Registers
These registers control the multiplexing of the functionality available on each pad. There are 31 such
registers – PINMMR0 through PINMMR31. Each 8-bit field of a PINMMR register controls the functionality
of a single ball/pin. The mapping between the PINMMRx control registers and the functionality selected on
a given terminal is defined in Section 4.6. Some of the PINMMRnn registers are also used to control
special multiplexed functions on the device. These are described in Section 4.3.3.
Figure 4-15. PINMMRnn: Pin Multiplexing Control Registers (Address = FFFFEB10h-FFFFEB88h)
31
24
23
16
PINMMRx[31-24]
PINMMRx[23-16]
R/WP-1
R/WP-1
15
8
7
0
PINMMRx[15-8]
PINMMRx[7-0]
R/WP-1
R/WP-1
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 4-15. Pin Multiplexing Control Registers Field Descriptions
Bit
Field
Value
31-24
PINMMRx[31-24]
1h
23-16
PINMMRx[23-16]
1h
15-8
PINMMRx[15-8]
1h
7-0
PINMMRx[7-0]
1h
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Description
Each of these byte-fields control the functionality on a given ball/pin. Please refer to Table 4-16
for a list of multiplexed signals sorted by the control registers.
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Signal Multiplexing and Control
Table 4-16 shows the multiplexing implemented on this microcontroller as well as the memory-mapped registers (PINMMRx) that control these
multiplexors. These are all 32-bit registers and can be addressed using byte, half-word, or word accesses. Any bit not shown in the table is
reserved and will read as zero.
Table 4-16. Multiplexing and Control
Control Register
Address
Default Function
Selection Bit
Alternate
Function 1
Selection Bit
Alternate Function
2
Selection Bit
Alternate
Function 3
Selection Bit
Alternate Function
4
GIOB[3]
PINMMR0[0]
RESERVED
PINMMR0[1]
RESERVED
PINMMR0[2]
RESERVED
PINMMR0[3]
RESERVED
PINMMR0[4]
GIOA[0]
PINMMR0[8]
RESERVED
PINMMR0[9]
RESERVED
PINMMR0[10]
RESERVED
PINMMR0[11]
RESERVED
PINMMR0[12]
MIBSPI3NCS[3]
PINMMR0[16]
I2C_SCL
PINMMR0[17]
N2HET1[29]
PINMMR0[18]
RESERVED
PINMMR0[19]
RESERVED
PINMMR0[20]
MIBSPI3NCS[2]
PINMMR0[24]
I2C_SDA
PINMMR0[25]
N2HET1[27]
PINMMR0[26]
RESERVED
PINMMR0[27]
RESERVED
PINMMR0[28]
GIOA[1]
PINMMR1[0]
RESERVED
PINMMR1[1]
RESERVED
PINMMR1[2]
RESERVED
PINMMR1[3]
RESERVED
PINMMR1[4]
N2HET1[11]
PINMMR1[8]
MIBSPI3NCS[4]
PINMMR1[9]
N2HET2[18]
PINMMR1[10]
RESERVED
PINMMR1[11]
RESERVED
PINMMR1[12]
ETMDATA[20]
PINMMR1[16]
EMIF_DATA[4]
PINMMR1[17]
RESERVED
PINMMR1[18]
RESERVED
PINMMR1[19]
RESERVED
PINMMR1[20]
ETMDATA[21]
PINMMR1[24]
EMIF_DATA[5]
PINMMR1[25]
RESERVED
PINMMR1[26]
RESERVED
PINMMR1[27]
RESERVED
PINMMR1[28]
GIOA[2]
PINMMR2[0]
RESERVED
PINMMR2[1]
RESERVED
PINMMR2[2]
N2HET2[0]
PINMMR2[3]
RESERVED
PINMMR2[4]
ETMDATA[22]
PINMMR2[8]
EMIF_DATA[6]
PINMMR2[9]
RESERVED
PINMMR2[10]
RESERVED
PINMMR2[11]
RESERVED
PINMMR2[12]
GIOA[3]
PINMMR2[16]
N2HET2[2]
PINMMR2[17]
RESERVED
PINMMR2[18]
RESERVED
PINMMR2[19]
RESERVED
PINMMR2[20]
GIOA[5]
PINMMR2[24]
EXTCLKIN
PINMMR2[25]
RESERVED
PINMMR2[26]
RESERVED
PINMMR2[27]
RESERVED
PINMMR2[28]
ETMDATA[23]
PINMMR3[0]
EMIF_DATA[7]
PINMMR3[1]
RESERVED
PINMMR3[2]
RESERVED
PINMMR3[3]
RESERVED
PINMMR3[4]
N2HET1[22]
PINMMR3[8]
RESERVED
PINMMR3[9]
RESERVED
PINMMR3[10]
RESERVED
PINMMR3[11]
RESERVED
PINMMR3[12]
Selection Bit
FFFF EB10h
FFFF EB14h
FFFF EB18h
FFFF EB1Ch
GIOA[6]
PINMMR3[16]
N2HET2[4]
PINMMR3[17]
RESERVED
PINMMR3[18]
RESERVED
PINMMR3[19]
RESERVED
PINMMR3[20]
ETMDATA[24]
PINMMR3[24]
EMIF_DATA[8]
PINMMR3[25]
RESERVED
PINMMR3[26]
RESERVED
PINMMR3[27]
RESERVED
PINMMR3[28]
GIOA[7]
PINMMR4[0]
N2HET2[6]
PINMMR4[1]
RESERVED
PINMMR4[2]
RESERVED
PINMMR4[3]
RESERVED
PINMMR4[4]
ETMDATA[25]
PINMMR4[8]
EMIF_DATA[9]
PINMMR4[9]
RESERVED
PINMMR4[10]
RESERVED
PINMMR4[11]
RESERVED
PINMMR4[12]
N2HET1[01]
PINMMR4[16]
SPI4NENA
PINMMR4[17]
RESERVED
PINMMR4[18]
RESERVED
PINMMR4[19]
N2HET2[8]
PINMMR4[20]
N2HET1[03]
PINMMR4[24]
SPI4NCS[0]
PINMMR4[25]
RESERVED
PINMMR4[26]
RESERVED
PINMMR4[27]
N2HET2[10]
PINMMR4[28]
N2HET1[0]
PINMMR5[0]
SPI4CLK
PINMMR5[1]
RESERVED
PINMMR5[2]
RESERVED
PINMMR5[3]
RESERVED
PINMMR5[4]
N2HET1[02]
PINMMR5[8]
SPI4SIMO
PINMMR5[9]
RESERVED
PINMMR5[10]
RESERVED
PINMMR5[11]
RESERVED
PINMMR5[12]
FFFF EB20h
FFFF EB24h
N2HET1[05]
PINMMR5[16]
SPI4SOMI
PINMMR5[17]
N2HET2[12]
PINMMR5[18]
RESERVED
PINMMR5[19]
RESERVED
PINMMR5[20]
ETMDATA[26]
PINMMR5[24]
EMIF_DATA[10]
PINMMR5[25]
RESERVED
PINMMR5[26]
RESERVED
PINMMR5[27]
RESERVED
PINMMR5[28]
N2HET1[07]
PINMMR6[0]
RESERVED
PINMMR6[1]
RESERVED
PINMMR6[2]
N2HET2[14]
PINMMR6[3]
RESERVED
PINMMR6[4]
ETMDATA[27]
PINMMR6[8]
EMIF_DATA[11]
PINMMR6[9]
RESERVED
PINMMR6[10]
RESERVED
PINMMR6[11]
RESERVED
PINMMR6[12]
FFFF EB28h
N2HET1[09]
PINMMR6[16]
N2HET2[16]
PINMMR6[17]
RESERVED
PINMMR6[18]
RESERVED
PINMMR6[19]
RESERVED
PINMMR6[20]
ETMDATA[28]
PINMMR6[24]
EMIF_DATA[12]
PINMMR6[25]
RESERVED
PINMMR6[26]
RESERVED
PINMMR6[27]
RESERVED
PINMMR6[28]
ETMDATA[29]
PINMMR7[0]
EMIF_DATA[13]
PINMMR7[1]
RESERVED
PINMMR7[2]
RESERVED
PINMMR7[3]
RESERVED
PINMMR7[4]
MIBSPI3NCS[1]
PINMMR7[8]
N2HET1[25]
PINMMR7[9]
MDCLK
PINMMR7[10]
RESERVED
PINMMR7[11]
RESERVED
PINMMR7[12]
N2HET1[06]
PINMMR7[16]
SCIRX
PINMMR7[17]
RESERVED
PINMMR7[18]
RESERVED
PINMMR7[19]
RESERVED
PINMMR7[20]
ETMDATA[30]
PINMMR7[24]
EMIF_DATA[14]
PINMMR7[25]
RESERVED
PINMMR7[26]
RESERVED
PINMMR7[27]
RESERVED
PINMMR7[28]
FFFF EB2Ch
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Table 4-16. Multiplexing and Control (continued)
Control Register
Address
Default Function
Selection Bit
Alternate
Function 1
Selection Bit
Alternate Function
2
Selection Bit
Alternate
Function 3
Selection Bit
Alternate Function
4
N2HET1[13]
PINMMR8[0]
SCITX
PINMMR8[1]
RESERVED
PINMMR8[2]
RESERVED
PINMMR8[3]
RESERVED
PINMMR8[4]
MIBSPI1NCS[2]
PINMMR8[8]
N2HET1[19]
PINMMR8[9]
MDIO
PINMMR8[10]
RESERVED
PINMMR8[11]
RESERVED
PINMMR8[12]
Selection Bit
FFFF EB30h
N2HET1[15]
PINMMR8[16]
MIBSPI1NCS[4]
PINMMR8[17]
RESERVED
PINMMR8[18]
RESERVED
PINMMR8[19]
RESERVED
PINMMR8[20]
ETMDATA[31]
PINMMR8[24]
EMIF_DATA[15]
PINMMR8[25]
RESERVED
PINMMR8[26]
RESERVED
PINMMR8[27]
RESERVED
PINMMR8[28]
ETMTRACECLKIN
PINMMR9[0]
EXTCLKIN2
PINMMR9[1]
RESERVED
PINMMR9[2]
RESERVED
PINMMR9[3]
RESERVED
PINMMR9[4]
MIBSPI3NENA
PINMMR9[8]
MIBSPI3NCS[5]
PINMMR9[9]
N2HET1[31]
PINMMR9[10]
RESERVED
PINMMR9[11]
RESERVED
PINMMR9[12]
MIBSPI3NCS[0]
PINMMR9[16]
AD2EVT
PINMMR9[17]
GIOB[2]
PINMMR9[18]
RESERVED
PINMMR9[19]
RESERVED
PINMMR9[20]
MIBSPI1NCS[3]
PINMMR9[24]
N2HET1[21]
PINMMR9[25]
RESERVED
PINMMR9[26]
RESERVED
PINMMR9[27]
RESERVED
PINMMR9[28]
AD1EVT
PINMMR10[0]
MII_RX_ER
PINMMR10[1]
RMII_RX_ER
PINMMR10[2]
RESERVED
PINMMR10[3]
RESERVED
PINMMR10[4]
ETMDATA[19]
PINMMR10[8]
EMIF_DATA[3]
PINMMR10[9]
RESERVED
PINMMR10[10]
RESERVED
PINMMR10[11]
RESERVED
PINMMR10[12]
FFFF EB34h
FFFF EB38h
EMIF_nCS[0]
PINMMR10[16]
RTP_DATA[15]
PINMMR10[17]
N2HET2[7]
PINMMR10[18]
RESERVED
PINMMR10[19]
RESERVED
PINMMR10[20]
ETMDATA[18]
PINMMR10[24]
EMIF_DATA[2]
PINMMR10[25]
RESERVED
PINMMR10[26]
RESERVED
PINMMR10[27]
RESERVED
PINMMR10[28]
EMIF_nCS[3]
PINMMR11[0]
RTP_DATA[14]
PINMMR11[1]
N2HET2[9]
PINMMR11[2]
RESERVED
PINMMR11[3]
RESERVED
PINMMR11[4]
EMIF_nCS[4]
PINMMR11[8]
RTP_DATA[07]
PINMMR11[9]
RESERVED
PINMMR11[10]
RESERVED
PINMMR11[11]
RESERVED
PINMMR11[12]
ETMDATA[17]
PINMMR11[16]
EMIF_DATA[1]
PINMMR11[17]
RESERVED
PINMMR11[18]
RESERVED
PINMMR11[19]
RESERVED
PINMMR11[20]
N2HET1[24]
PINMMR11[24]
MIBSPI1NCS[5]
PINMMR11[25]
MII_RXD[0]
PINMMR11[26]
RMII_RXD[0]
PINMMR11[27]
RESERVED
PINMMR11[28]
N2HET1[26]
PINMMR12[0]
MII_RXD[1]
PINMMR12[1]
RMII_RXD[1]
PINMMR12[2]
RESERVED
PINMMR12[3]
RESERVED
PINMMR12[4]
ETMDATA[16]
PINMMR12[8]
EMIF_DATA[0]
PINMMR12[9]
RESERVED
PINMMR12[10]
RESERVED
PINMMR12[11]
RESERVED
PINMMR12[12]
MIBSPI1NENA
PINMMR12[16]
N2HET1[23]
PINMMR12[17]
MII_RXD[2]
PINMMR12[18]
RESERVED
PINMMR12[19]
RESERVED
PINMMR12[20]
MIBSPI5NENA
PINMMR12[24]
DMM_DATA[7]
PINMMR12[25]
MII_RXD[3]
PINMMR12[26]
RESERVED
PINMMR12[27]
RESERVED
PINMMR12[28]
MIBSPI5SOMI[0]
PINMMR13[0]
DMM_DATA[12]
PINMMR13[1]
MII_TXD[0]
PINMMR13[2]
RMII_TXD[0]
PINMMR13[3]
RESERVED
PINMMR13[4]
MIBSPI5SIMO[0]
PINMMR13[8]
DMM_DATA[8]
PINMMR13[9]
MII_TXD[1]
PINMMR13[10]
RMII_TXD[1]
PINMMR13[11]
RESERVED
PINMMR13[12]
FFFF EB3Ch
FFFF EB40h
FFFF EB44h
MIBSPI5CLK
PINMMR13[16]
DMM_DATA[4]
PINMMR13[17]
MII_TXEN
PINMMR13[18]
RMII_TXEN
PINMMR13[19]
RESERVED
PINMMR13[20]
MIBSPI1NCS[0]
PINMMR13[24]
MIBSPI1SOMI[1]
PINMMR13[25]
MII_TXD[2]
PINMMR13[26]
RESERVED
PINMMR13[27]
RESERVED
PINMMR13[28]
N2HET1[8]
PINMMR14[0]
MIBSPI1SIMO[1]
PINMMR14[1]
MII_TXD[3]
PINMMR14[2]
RESERVED
PINMMR14[3]
RESERVED
PINMMR14[4]
N2HET1[28]
PINMMR14[8]
MII_RXCLK
PINMMR14[9]
RMII_REFCLK
PINMMR14[10]
MII_RX_AVCLK4
PINMMR14[11]
RESERVED
PINMMR14[12]
FFFF EB48h
EMIF_nWE
PINMMR14[16]
RESERVED
PINMMR14[17]
RESERVED
PINMMR14[18]
RESERVED
PINMMR14[19]
RESERVED
PINMMR14[20]
EMIF_BA[1]
PINMMR14[24]
N2HET2[5]
PINMMR14[25]
RESERVED
PINMMR14[26]
RESERVED
PINMMR14[27]
RESERVED
PINMMR14[28]
EMIF_ADDR[21]
PINMMR15[0]
RTP_CLK
PINMMR15[1]
RESERVED
PINMMR15[2]
RESERVED
PINMMR15[3]
RESERVED
PINMMR15[4]
EMIF_ADDR[20]
PINMMR15[8]
RTP_nSYNC
PINMMR15[9]
RESERVED
PINMMR15[10]
RESERVED
PINMMR15[11]
RESERVED
PINMMR15[12]
EMIF_ADDR[19]
PINMMR15[16]
RTP_nENA
PINMMR15[17]
RESERVED
PINMMR15[18]
RESERVED
PINMMR15[19]
RESERVED
PINMMR15[20]
EMIF_ADDR[18]
PINMMR15[24]
RTP_DATA[0]
PINMMR15[25]
RESERVED
PINMMR15[26]
RESERVED
PINMMR15[27]
RESERVED
PINMMR15[28]
ETMDATA[12]
PINMMR16[0]
EMIF_BA[0]
PINMMR16[1]
RESERVED
PINMMR16[2]
RESERVED
PINMMR16[3]
RESERVED
PINMMR16[4]
EMIF_ADDR[17]
PINMMR16[8]
RTP_DATA[01]
PINMMR16[9]
RESERVED
PINMMR16[10]
RESERVED
PINMMR16[11]
RESERVED
PINMMR16[12]
EMIF_ADDR[16]
PINMMR16[16]
RTP_DATA[02]
PINMMR16[17]
RESERVED
PINMMR16[18]
RESERVED
PINMMR16[19]
RESERVED
PINMMR16[20]
ETMDATA[13]
PINMMR16[24]
EMIF_nOE
PINMMR16[25]
RESERVED
PINMMR16[26]
RESERVED
PINMMR16[27]
RESERVED
PINMMR16[28]
FFFF EB4Ch
FFFF EB50h
I/O Multiplexing and Control Module (IOMM) 247
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Table 4-16. Multiplexing and Control (continued)
Control Register
Address
Default Function
Selection Bit
Alternate
Function 1
Selection Bit
Alternate Function
2
Selection Bit
Alternate
Function 3
Selection Bit
Alternate Function
4
Selection Bit
N2HET1[10]
PINMMR17[0]
MII_TX_CLK
PINMMR17[1]
RESERVED
PINMMR17[2]
MII_TX_AVCLK4
PINMMR17[3]
RESERVED
PINMMR17[4]
ETMDATA[14]
PINMMR17[8]
EMIF_nDQM[1]
PINMMR17[9]
RESERVED
PINMMR17[10]
RESERVED
PINMMR17[11]
RESERVED
PINMMR17[12]
N2HET1[12]
PINMMR17[16]
MII_CRS
PINMMR17[17]
RMII_CRS_DV
PINMMR17[18]
RESERVED
PINMMR17[19]
RESERVED
PINMMR17[20]
ETMDATA[8]
PINMMR17[24]
EMIF_ADDR[5]
PINMMR17[25]
RESERVED
PINMMR17[26]
RESERVED
PINMMR17[27]
RESERVED
PINMMR17[28]
EMIF_ADDR[15]
PINMMR18[0]
RTP_DATA[03]
PINMMR18[1]
RESERVED
PINMMR18[2]
RESERVED
PINMMR18[3]
RESERVED
PINMMR18[4]
N2HET1[14]
PINMMR18[8]
RESERVED
PINMMR18[9]
RESERVED
PINMMR18[10]
RESERVED
PINMMR18[11]
RESERVED
PINMMR18[12]
EMIF_ADDR[14]
PINMMR18[16]
RTP_DATA[04]
PINMMR18[17]
RESERVED
PINMMR18[18]
RESERVED
PINMMR18[19]
RESERVED
PINMMR18[20]
GIOB[0]
PINMMR18[24]
RESERVED
PINMMR18[25]
RESERVED
PINMMR18[26]
RESERVED
PINMMR18[27]
RESERVED
PINMMR18[28]
ETMDATA[09]
PINMMR19[0]
EMIF_ADDR[4]
PINMMR19[1]
RESERVED
PINMMR19[2]
RESERVED
PINMMR19[3]
RESERVED
PINMMR19[4]
N2HET1[30]
PINMMR19[8]
MII_RX_DV
PINMMR19[9]
RESERVED
PINMMR19[10]
RESERVED
PINMMR19[11]
RESERVED
PINMMR19[12]
ETMDATA[15]
PINMMR19[16]
EMIF_nDQM[0]
PINMMR19[17]
RESERVED
PINMMR19[18]
RESERVED
PINMMR19[19]
RESERVED
PINMMR19[20]
ETMDATA[10]
PINMMR19[24]
EMIF_ADDR[3]
PINMMR19[25]
RESERVED
PINMMR19[26]
RESERVED
PINMMR19[27]
RESERVED
PINMMR19[28]
EMIF_ADDR[13]
PINMMR20[0]
RTP_DATA[05]
PINMMR20[1]
RESERVED
PINMMR20[2]
RESERVED
PINMMR20[3]
RESERVED
PINMMR20[4]
EMIF_ADDR[12]
PINMMR20[8]
RTP_DATA[06]
PINMMR20[9]
RESERVED
PINMMR20[10]
RESERVED
PINMMR20[11]
RESERVED
PINMMR20[12]
FFFF EB54h
FFFF EB58h
FFFF EB5Ch
FFFF EB60h
MIBSPI1NCS[1]
PINMMR20[16]
N2HET1[17]
PINMMR20[17]
MII_COL
PINMMR20[18]
RESERVED
PINMMR20[19]
RESERVED
PINMMR20[20]
EMIF_ADDR[11]
PINMMR20[24]
RTP_DATA[8]
PINMMR20[25]
RESERVED
PINMMR20[26]
RESERVED
PINMMR20[27]
RESERVED
PINMMR20[28]
EMIF_ADDR[1]
PINMMR21[0]
N2HET2[3]
PINMMR21[1]
RESERVED
PINMMR21[2]
RESERVED
PINMMR21[3]
RESERVED
PINMMR21[4]
GIOB[1]
PINMMR21[8]
RESERVED
PINMMR21[9]
RESERVED
PINMMR21[10]
RESERVED
PINMMR21[11]
RESERVED
PINMMR21[12]
EMIF_ADDR[10]
PINMMR21[16]
RTP_DATA[09]
PINMMR21[17]
RESERVED
PINMMR21[18]
RESERVED
PINMMR21[19]
RESERVED
PINMMR21[20]
EMIF_ADDR[9]
PINMMR21[24]
RTP_DATA[10]
PINMMR21[25]
RESERVED
PINMMR21[26]
RESERVED
PINMMR21[27]
RESERVED
PINMMR21[28]
EMIF_ADDR[0]
PINMMR22[0]
N2HET2[1]
PINMMR22[1]
RESERVED
PINMMR22[2]
RESERVED
PINMMR22[3]
RESERVED
PINMMR22[4]
EMIF_ADDR[7]
PINMMR22[8]
RTP_DATA[12]
PINMMR22[9]
N2HET2[13]
PINMMR22[10]
RESERVED
PINMMR22[11]
RESERVED
PINMMR22[12]
EMIF_ADDR[6]
PINMMR22[16]
RTP_DATA[13]
PINMMR22[17]
N2HET2[11]
PINMMR22[18]
RESERVED
PINMMR22[19]
RESERVED
PINMMR22[20]
ETMDATA[11]
PINMMR22[24]
EMIF_ADDR[2]
PINMMR22[25]
RESERVED
PINMMR22[26]
RESERVED
PINMMR22[27]
RESERVED
PINMMR22[28]
EMIF_ADDR[8]
PINMMR23[0]
RTP_DATA[11]
PINMMR23[1]
N2HET2[15]
PINMMR23[2]
RESERVED
PINMMR23[3]
RESERVED
PINMMR23[4]
SPI4CLK
PINMMR23[8]
RESERVED
PINMMR23[9]
RESERVED
PINMMR23[10]
RESERVED
PINMMR23[11]
RESERVED
PINMMR23[12]
SPI4SIMO
PINMMR23[16]
RESERVED
PINMMR23[17]
RESERVED
PINMMR23[18]
RESERVED
PINMMR23[19]
RESERVED
PINMMR23[20]
SPI4SOMI
PINMMR23[24]
RESERVED
PINMMR23[25]
RESERVED
PINMMR23[26]
RESERVED
PINMMR23[27]
RESERVED
PINMMR23[28]
SPI4NENA
PINMMR24[0]
RESERVED
PINMMR24[1]
RESERVED
PINMMR24[2]
RESERVED
PINMMR24[3]
RESERVED
PINMMR24[4]
SPI4NCS[0]
PINMMR24[8]
RESERVED
PINMMR24[9]
RESERVED
PINMMR24[10]
RESERVED
PINMMR24[11]
RESERVED
PINMMR24[12]
N2HET1[17]
PINMMR24[16]
RESERVED
PINMMR24[17]
RESERVED
PINMMR24[18]
RESERVED
PINMMR24[19]
RESERVED
PINMMR24[20]
N2HET1[19]
PINMMR24[24]
RESERVED
PINMMR24[25]
RESERVED
PINMMR24[26]
RESERVED
PINMMR24[27]
RESERVED
PINMMR24[28]
N2HET1[21]
PINMMR25[0]
RESERVED
PINMMR25[1]
RESERVED
PINMMR25[2]
RESERVED
PINMMR25[3]
RESERVED
PINMMR25[4]
N2HET1[23]
PINMMR25[8]
RESERVED
PINMMR25[9]
RESERVED
PINMMR25[10]
RESERVED
PINMMR25[11]
RESERVED
PINMMR25[12]
N2HET1[25]
PINMMR25[16]
RESERVED
PINMMR25[17]
RESERVED
PINMMR25[18]
RESERVED
PINMMR25[19]
RESERVED
PINMMR25[20]
N2HET1[27]
PINMMR25[24]
RESERVED
PINMMR25[25]
RESERVED
PINMMR25[26]
RESERVED
PINMMR25[27]
RESERVED
PINMMR25[28]
FFFF EB64h
FFFF EB68h
FFFF EB6Ch
FFFF EB70h
FFFF EB74h
248 I/O Multiplexing and Control Module (IOMM)
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Signal Multiplexing and Control
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Table 4-16. Multiplexing and Control (continued)
Control Register
Address
Default Function
Selection Bit
Alternate
Function 1
Selection Bit
Alternate Function
2
Selection Bit
Alternate
Function 3
Selection Bit
Alternate Function
4
Selection Bit
N2HET1[29]
PINMMR26[0]
RESERVED
PINMMR26[1]
RESERVED
PINMMR26[2]
RESERVED
PINMMR26[3]
RESERVED
PINMMR26[4]
N2HET1[31]
PINMMR26[8]
RESERVED
PINMMR26[9]
RESERVED
PINMMR26[10]
RESERVED
PINMMR26[11]
RESERVED
PINMMR26[12]
MIBSPI5NCS[2]
PINMMR26[16]
DMM_DATA[2]
PINMMR26[17]
RESERVED
PINMMR26[18]
RESERVED
PINMMR26[19]
RESERVED
PINMMR26[20]
MIBSPI5NCS[3]
PINMMR26[24]
DMM_DATA[3]
PINMMR26[25]
RESERVED
PINMMR26[26]
RESERVED
PINMMR26[27]
RESERVED
PINMMR26[28]
MIBSPI5NCS[0]
PINMMR27[0]
DMM_DATA[5]
PINMMR27[1]
RESERVED
PINMMR27[2]
RESERVED
PINMMR27[3]
RESERVED
PINMMR27[4]
MIBSPI5NCS[1]
PINMMR27[8]
DMM_DATA[6]
PINMMR27[9]
RESERVED
PINMMR27[10]
RESERVED
PINMMR27[11]
RESERVED
PINMMR27[12]
MIBSPI5SIMO[1]
PINMMR27[16]
DMM_DATA[9]
PINMMR27[17]
RESERVED
PINMMR27[18]
RESERVED
PINMMR27[19]
RESERVED
PINMMR27[20]
MIBSPI5SIMO[2]
PINMMR27[24]
DMM_DATA[10]
PINMMR27[25]
RESERVED
PINMMR27[26]
RESERVED
PINMMR27[27]
RESERVED
PINMMR27[28]
MIBSPI5SIMO[3]
PINMMR28[0]
DMM_DATA[11]
PINMMR28[1]
RESERVED
PINMMR28[2]
RESERVED
PINMMR28[3]
RESERVED
PINMMR28[4]
MIBSPI5SOMI[1]
PINMMR28[8]
DMM_DATA[13]
PINMMR28[9]
RESERVED
PINMMR28[10]
RESERVED
PINMMR28[11]
RESERVED
PINMMR28[12]
MIBSPI5SOMI[2]
PINMMR28[16]
DMM_DATA[14]
PINMMR28[17]
RESERVED
PINMMR28[18]
RESERVED
PINMMR28[19]
RESERVED
PINMMR28[20]
MIBSPI5SOMI[3]
PINMMR28[24]
DMM_DATA[15]
PINMMR28[25]
RESERVED
PINMMR28[26]
RESERVED
PINMMR28[27]
RESERVED
PINMMR28[28]
SPI2NENA
PINMMR29[0]
SPI2NCS[1]
PINMMR29[1]
RESERVED
PINMMR29[2]
RESERVED
PINMMR29[3]
RESERVED
PINMMR29[4]
EMIF_CLK_SEL
PINMMR29[8]
RESERVED
PINMMR29[9]
RESERVED
PINMMR29[10]
RESERVED
PINMMR29[11]
RESERVED
PINMMR29[12]
FFFF EB78h
FFFF EB7Ch
FFFF EB80h
FFFF EB84h
GIOB[2]
PINMMR29[16]
RESERVED
PINMMR29[17]
RESERVED
PINMMR29[18]
RESERVED
PINMMR29[19]
RESERVED
PINMMR29[20]
GMII_SEL
PINMMR29[24]
RESERVED
PINMMR29[25]
RESERVED
PINMMR29[26]
RESERVED
PINMMR29[27]
RESERVED
PINMMR29[28]
ADC_TRG1
PINMMR30[0]
ADC_TRG2
PINMMR30[1]
RESERVED
PINMMR30[2]
RESERVED
PINMMR30[3]
RESERVED
PINMMR30[4]
RESERVED
PINMMR30[8]
RESERVED
PINMMR30[9]
RESERVED
PINMMR30[10]
RESERVED
PINMMR30[11]
RESERVED
PINMMR30[12]
RESERVED
PINMMR30[16]
RESERVED
PINMMR30[17]
RESERVED
PINMMR30[18]
RESERVED
PINMMR30[19]
RESERVED
PINMMR30[20]
RESERVED
PINMMR30[24]
RESERVED
PINMMR30[25]
RESERVED
PINMMR30[26]
RESERVED
PINMMR30[27]
RESERVED
PINMMR30[28]
FFFF EB88h
I/O Multiplexing and Control Module (IOMM) 249
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Chapter 5
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F021 Flash Module Controller (FMC)
The Flash electrically-erasable programmable read-only memory module is a type of nonvolatile memory
that has fast read access times and is able to be reprogrammed in the field or in the application. This
chapter describes the F021 Flash module controller (FMC).
250
Topic
...........................................................................................................................
5.1
5.2
5.3
5.4
5.5
5.6
5.7
Overview ........................................................................................................
Default Flash Configuration ..............................................................................
SECDED .........................................................................................................
Memory Map ...................................................................................................
Power On, Power Off, and Reset Considerations .................................................
Emulation and SIL3 Diagnostic Modes ................................................................
Control Registers ............................................................................................
F021 Flash Module Controller (FMC)
Page
251
252
253
257
260
261
267
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Overview
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5.1
Overview
The F021 Flash is used to provide non-volatile memory for instruction execution or data storage. The
Flash can be electrically programmed and erased many times to ease code development.
Refer to the following documents for support in how to initialize and use the on-chip Flash and its API:
• Initialization of Hercules ARM Cortex-R4F Microcontrollers Application Report (SPNA106)
• F021 (Texas Instruments 65nm Flash) Flash API Reference Guide (SPNU501)
5.1.1 Features
•
•
•
•
•
Read, program and erase with a single 3.3 V supply voltage
Supports error detection and correction
– Single Error Correction and Double Error Detection (SECDED)
– Error Correction Code (ECC) is evaluated in the CPU for the main Flash bank arrays and in the
Flash Wrapper for the EEPROM emulation Flash banks
– Address bits included in ECC calculation
Provides different read modes to optimize performance and verify the integrity of Flash contents
Provides built-in power mode control logic
Integrated program/erase state machine
– Simplifies software algorithms
– Supports simultaneous read access on a bank while performing a write or erase operation on any
one of the remaining banks
– Suspend command allows read access to a sector being programmed/erased
– Fast erase and program times (for details, see the device-specific data sheet)
For the actual size of the Flash memory for the device, see the device-specific data sheet.
5.1.2 Definition of Terms
Terms used in this document have the following meaning:
• ATCM: Port A tightly coupled memory
• BAGP (Bank Active Grace Period): Time (in HCLK cycles) from the most recent Flash access of a
particular bank until that bank enters fallback power mode. This reduces power consumption by the
Flash. However, it can also increase access time.
• bw: Normal data space bank data width of a Flash bank. The bw is 128 bits (144 bits including the
error correction bits).
• bwe: EEPROM emulation bank is 128-bits wide (144 bits including the error correction bits).
• Charge pump: Voltage generators and associated control (logic, oscillator, and bandgap, for example).
• CSM: Program/erase command state machine
• Fallback power mode: The power mode (active, standby or sleep, depending on which mode is
selected) into which a bank or the charge pump falls back each time the active grace period expires.
• Flash bank: A group of Flash sectors that share input/output buffers, data paths, sense amplifiers, and
control logic.
• FEE - Flash EEPROM Emulation. Features on the FMC to support using a Flash type memory in place
of an EEPROM Flash memory. EEPROM is erasable by the word while this Flash memory is only
erasable by the sector. The FEE bank is accessible only through Bus 2 in a special address range and
always resides in bank 7.
• Flash module: Flash banks, charge pump, and Flash wrapper.
• Flash wrapper: Power and mode control logic, data path, wait logic, and write/erase state machines.
• FMC: Flash Module Controller.
• Command: A sequence of coded instructions to Flash module to execute a certain task.
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Overview
•
•
•
•
•
•
•
•
•
www.ti.com
FSM (Flash State Machine): State machine that parses and decodes FSM commands. It executes
embedded algorithms and generates control signals to both Flash bank and charge pump during the
actual program/erase operation.
OTP (one-time programmable): A program-only-once Flash sector (cannot be erased)
PAGP (Pump Active Grace Period): Time (in HCLK cycles) from when the last of the banks have
entered fallback power mode until the pump enters a fallback power mode. This can reduce power
consumption by the Flash; however, it can also increase access time.
Pipeline mode: The mode in which Flash is read 128 bits (+ 16 bit ECC) at a time, providing higher
throughput.
Sector: A contiguous region of Flash memory which must be erased simultaneously.
Wide_Word: The width of the data output from the Flash bank. This is 144-bits wide for main Flash and
for the FEE bank.
Standard read mode: The mode assumed when the pipeline mode is disabled. Physically, 128 (+ 16 bit
ECC) is read at a time. However, only 32 bits of data is used while the other bits of data are discarded.
Read Margin 1 mode: More stringent read mode designed for early detection of marginally erased bits.
Read Margin 0 mode: More stringent read mode designed for early detection of marginally
programmed bits.
5.1.3 F021 Flash Tools
Texas Instruments provides the following tools for F021 Flash:
• nowECC Generation Tool - to generate the Flash ECC from the Flash data.
• nowFLASH Programming Tool - to erase/program/verify the device Flash content through JTAG.
• Code Composer Studio - the development environment with integrated Flash programming capabilities.
• F021 Flash API Library - a set of software peripheral functions to program/erase the Flash module.
Refer to F021 Flash API Reference Guide (SPNU501) for more information.
5.2
Default Flash Configuration
At
•
•
•
•
•
252
power up, the Flash module state exhibits the following properties:
Wait states are set to 1 data wait state and 0 address wait states
Pipeline mode is disabled
The Flash content is protected from modification
Power modes are set to Active (no power savings)
The boot code must initialize the wait states (including data wait states and address wait states) and
the desired pipeline mode by initializing the FRDCNTL register to achieve the optimum system
performance. This needs to be done before switching to the final device operating frequency. Refer to
Initialization of Hercules ARM Cortex-R4F Microcontrollers Application Report (SPNA106) for more
information.
F021 Flash Module Controller (FMC)
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SECDED
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5.3
SECDED
The Flash memory can be protected by Single Error Correction Double Error Detection (SECDED). The
main program memory is protected by the SECDED circuit inside of the Cortex-R4 CPU. All OTP and the
FEE memory (bank 7) is protected by SECDED logic in the Flash wrapper.
5.3.1 SECDED Initialization
Flash error detection and correction is not enabled at reset. To enable SECDED, error correction detection
must be enabled in the Flash wrapper, the CPU event bus must be enabled and SECDED must be
enabled within the CPU. Refer to Initialization of Hercules ARM Cortex-R4F Microcontrollers Application
Report (SPNA106) for information on these steps.
The ECC values for all of the ATCM program memory space (Flash banks 0 through 6) must be
programmed into the Flash before SECDED is enabled. This can be done by generating the correct
values of the ECC with an external tool such as nowECC or may be generated by the programming tool.
The Cortex-R4 CPU may generate speculative fetches to any location within the ATCM memory space. A
speculative fetch to a location with invalid ECC, which is subsequently not used, will not create an abort,
but will set the ESM flags for a correctable or uncorrectable error. An uncorrectable error will
unconditionally cause the nERROR pin to toggle low. Therefore care must be taken to generate the
correct ECC for the entire ATCM space including the holes between sections and any unused or blank
Flash areas.
The Cortex-R4 CPU does not generate speculative fetches into the address space of bank 7, the
EEPROM Emulation Flash. It is only necessary to initialize the ECC values of the locations which will be
intentionally read by the CPU or other bus masters.
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SECDED
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5.3.2 ECC Encoding
Nineteen address lines are also included in the ECC calculation. A failure of a single address line inside of
the bank will be treated as an uncorrectable error. The ECC encoding is shown in Table 5-1. Bits 31:0
come from the word at the address ending in 0x0 or 0x8, Bits 63:31 come from the word at the address
ending in 0x4 or 0xC.
Table 5-1. ECC Encoding for BE32 Devices
8
2
8
1
8
0
7
9
7
8
7
7
7
6
7
5
7
4
7
3
7
2
7
1
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
7
0
6
9
6
8
6
7
6
6
6
5
6
4
Participating Address Bits
ADDR_MSW_LSW
ECC Bit
0007F_00FFFF00_FF0000FF
7
7FF80_FF0000FF_FF0000FF
6
07F80_00FF00FF_00FF00FF
5
19F83_FCC0FCC0_FCC0FCC0
4
6A78D_E338E338_E338E338
3
2A9B5_99A699A6_99A699A6
2
0BAD1_57155715_57155715
1
554EA_D1B4D1B4_2E4B2E4B
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
9
0
8
0
7
0
6
0
5
0
4
0
3
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Participating Data Bits
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
5
5
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
3
8
3
7
3
6
3
5
3
4
3
3
3
2
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
3
9
x
x
x
x
x
x
Participating Data Bits
2
6
2
5
2
4
x
x
x
x
x
x
x
x
x
x
x
(1)
(2)
254
2
2
x
x
x
x
x
x
x
2
3
2
1
x
x
x
2
0
x
x
1
9
x
x
x
x
x
1
7
x
1
6
x
x
x
1
4
1
3
x
x
x
x
x
x
x
x
x
1
5
1
2
1
1
1
0
0
9
0
8
x
x
x
x
1
8
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
3
0
2
9
2
8
2
7
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Parity (1)
Check Bits (2)
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
x
x
x
x
x
x
x
x
Even
ECC[7]
x
x
x
x
x
x
x
x
Even
ECC[6]
x
x
x
x
x
x
x
x
Even
ECC[5]
x
x
Even
ECC[4]
Odd
ECC[3]
Odd
ECC[2]
x
Even
ECC[1]
x
Even
ECC[0]
x
x
x
3
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
For Odd parity, XOR a 1 to the row’s XOR result. For even Parity, use the row’s XOR result directly.
Each ECC[x] bit represents the XOR of all the address and data bits marked with x in the same row.
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5.3.3 Syndrome Table: Decode to Bit in Error
The syndrome is an 8-bit value that decodes to the bit in error. The bit in error can be a bit among the 64
data bits, the 19 address bits, or a bit among the 8 ECC check bits. A syndrome value of 00000000
indicates there is no error. Any other syndrome combinations not shown in the table are uncorrectable
multi-bit error. Errors of three of more bits may escape detection. The syndrome decoding is shown in
Table 5-2.
Table 5-2. Syndrome Table, Decode to Bit in Error
Address Bit Error Position
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
1
0
1
0
0
1
1
1
1
0
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
1
1
0
1
0
1
0
0
0
1
0
1
1
1
0
1
0
1
1
0
1
0
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
1
1
0
1
0
1
0
Data Bit Error Position
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
0
0
1
1
1
0
0
0
1
1
1
0
0
1
0
0
1
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
1
0
1
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
0
1
1
0
1
1
0
1
0
0
1
1
0
1
0
0
0
1
1
0
1
1
0
1
0
0
0
0
1
0
1
Data Bit Error Position
ECC Error Bit
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0 Bit[7]
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0 Bit[6]
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
0
0
0
0
0 Bit[5]
1
0
0
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0 Bit[4]
0
1
1
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
0
0
1
1
1
0
0
0
0
0
0
0
1
0
0
0 Bit[3]
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
0
1
1
0
1
0
0
1
1
0
0
0
0
0
0
1
0
0 Bit[2]
1
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
0
0
1
0
1
0
1
0
0
0
0
0
0
1
0
1
1
0
0
1
0
0
1
0
1
1
0
0
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
0
0
0
0
0
0
1 Bit[0]
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Bit1]
255
SECDED
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5.3.4 Syndrome Table: An Alternate Method
Table 5-3. Alternate Syndrome Table
•
•
•
•
•
256
Syndrome msb 7:4
Syndrome
lsb: 3:0
0x
1x
2x
3x
4x
5x
6x
7x
8x
9x
Ax
Bx
Cx
Dx
Ex
x0
good
E04
E05
D
E06
D
D
D38
E07
D
D
D54
D
M
M
D
x1
E00
D
D
D22
D
A19
A17
D
D
A04
M
D
M
D
D
D06
x2
E01
D
D
M
D
D58
D32
D
D
D42
D48
D
M
D
D
M
x3
D
D10
D16
D
M
D
D
A15
A09
D
D
M
D
D26
D00
D
x4
E02
D
D
D23
D
D59
D33
D
D
D43
D49
D
M
D
D
D07
x5
D
D11
D17
D
M
D
D
D39
A08
D
D
D55
D
D27
D01
D
x6
D
D12
D18
D
M
D
D
A14
A07
D
D
M
D
D28
D02
D
x7
M
D
D
M
D
D60
D34
D
D
D44
D50
D
M
D
D
M
x8
E03
D
D
M
D
D61
D35
D
D
D45
D51
D
M
D
D
M
D
Fx
x9
D
D13
D19
D
A21
D
D
A13
A06
D
D
M
D
D29
D03
xA
D
D14
D20
D
D57
D
D
A12
D41
D
D
M
D
D30
D04
D
xB
D09
D
D
M
D
D62
D36
D
D
D46
D52
D
D25
D
D
M
xC
D
D15
D21
D
A20
D
D
A11
A05
D
D
M
D
D31
D05
D
xD
M
D
D
M
D
D63
D37
D
D
D47
D53
D
M
D
D
M
xE
D08
D
D
M
D
A18
A16
D
D
A03
M
D
D24
D
D
M
xF
D
M
M
D
D56
D
D
A10
D40
D
D
M
D
M
M
D
E0x - Single-bit ECC error, correctable
Dxx - Single-bit data error, correctable
Axx - Single-bit address error, uncorrectable
D - Double-bit error, uncorrectable
M - Multi-bit errors, uncorrectable
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5.4
Memory Map
The Flash module contains the program memory, which is mapped starting at location 0, and one
Customer OTP sector and one TI OTP sector per bank. The Customer OTP sectors may be programmed
by the customer, but cannot be erased. They are typically blank in new parts. The TI OTP sectors are
used to contain manufacturing information. They may be read by the customer but can not be
programmed or erased. The TI OTP sectors contain settings used by the Flash API to setup the Flash
state machine for erase and program operations.
All of these OTP regions are memory-mapped to facilitate ease of access by the CPU. They are memory
mapped to an offset starting at F000 0000h in the CPU’s memory map.
The RWAIT value is used to define the number of wait states for the program-memory Flash. The EWAIT
value is used to define the number of wait states for the data Flash in bank 7. Bank 7 starting at offset
F020 0000h is dedicated for data storages such as EEPROM Emulation.
5.4.1 Location of Flash ECC Bits
The Flash ECC bits can be read starting at address 0xF0400000. The ECC bits are packed in their
memory space as shown in Figure 5-1. The ECC bytes must be read as bytes or halfwords. Reading a
single ECC byte with ECC enabled will actually cause 144 bits to be read from the Flash, and the ECC
bits will be corrected if necessary. Any errors in either of the two double-words accessed will be recorded
in the FEDACSTATUS register (main memory) or the EE_STATUS register (bank 7).
Figure 5-1. ECC Organization for Program Flash (144-Bits Wide)
Big Endian
8-bit Read
0x00000028
64 – bit data word 5
0x00000020
64 – bit data word 4
0x00000018
64 – bit data word 3
0xF0400005
ECC5
0xF0400004
ECC4
0xF0400003
ECC3
ECC5
0xF0400002
ECC2
ECC1
ECC0
16-bit Read
64 – bit data word 2
0xF0400004
0x00000008
64 – bit data word 1
0xF0400002
ECC2
ECC3
0xF0400001
0x00000000
64 – bit data word 0
0xF0400000
ECC0
ECC1
0xF0400000
0x00000010
ECC4
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5.4.2 OTP Memory
5.4.2.1
Flash Bank and Sector Sizes
Flash Bank/Sectoring information can be determined from the device-specific datasheet or can be
computed by reading locations in the TI OTP and FMC registers.
The number of banks, which banks are available, and the number of sectors for bank 0 can be read from
TI OTP location F008 0158h as shown in Figure 5-2 and described in Table 5-4.
Figure 5-2. TI OTP Bank 0 Sector Information
31
24
23
16
Reserved
BX_NUM_Sectors
R
R
15
14
13
12
11
10
9
8
B7
B6
B5
B4
B3
B2
B1
B0
7
NUM_Banks
0
R-1
R-0
R-0
R-0
R-0
R-0
R-1
R-1
R
LEGEND: R = Read only
Table 5-4. TI OTP Bank 0 Sector Information Field Descriptions
Bit
Field
Value
31-24
Reserved
0
23-16
BX_NUM_Sectors
Description
Reserved. All bits will be read as 0.
1-32
Number of sectors in this bank.
15
B7
1
1 = Bank 7 is present
14
B6
0
0 = Bank 6 is not present
13
B5
0
0 = Bank 5 is not present
12
B4
0
0 = Bank 4 is not present
11
B3
0
0 = Bank 3 is not present
10
B2
0
0 = Bank 2 is not present
9
B1
1
1 = Bank 1 is present
8
B0
1
1 = Bank 0 is present
7-0
NUM_Banks
2 or 3
Number of banks on this part.
The bank sector information is repeated once for each bank in the device. The number of sectors is
unique for each bank. The number of banks and which banks are implemented is repeated in each
location. Use the TI OTP information for bank 0 to determine which banks are in the device, and then read
the number of sectors for each bank using the TI OTP locations shown in Table 5-5.
Table 5-5. TI OTP Sector Information Address
258
Bank
TI OTP Address
0
F008 0158h
1
F008 2158h
2
F008 4158h
3
F008 6158h
4
F008 8158h
5
F008 A158h
6
F008 C158h
7
F008 E158h
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5.4.2.2
Package and Memory Size
Package and memory size information can be determined from the device-specific datasheet, or can be
computed by reading locations in the TI OTP Bank 0 registers.
The package and memory size can be read from TI OTP location F008 015Ch as shown in Figure 5-3 and
described in Table 5-6.
Figure 5-3. TI OTP Bank 0 Package and Memory Size Information (F008 015Ch)
31
28
27
16
Reserved
PACKAGE
R
R
15
0
MEMORY_SIZE
R
LEGEND: R = Read only
Table 5-6. TI OTP Bank 0 Package and Memory Size Information Field Descriptions
Bit
Field
Description
31-28
Reserved
Reserved
27-16
PACKAGE
Count of pins in the package
15-0
MEMORY_SIZE
Flash memory size in Kbytes
5.4.2.3
LPO Trim and Max HCLK
The HF LPO trim solution, LF LPO trim solution and maximum HCLK frequency can be read from TI OTP
location F008 01B4h as shown in Figure 5-4 and described in Table 5-7.
Figure 5-4. TI OTP Bank 0 LPO Trim and Max HCLK Information (F008 01B4h)
31
24
23
16
HFLPO_TRIM
LFLPO_TRIM
R
R
15
0
MAX_HCLK
R
LEGEND: R = Read only
Table 5-7. TI OTP Bank 0 LPO Trim and Max HCLK Information Field Descriptions
Field
Description
31-24
Bit
HFLPO_TRIM
HF LPO Trim Solution
23-16
LFLPO_TRIM
LF LPO Trim Solution
15-0
MAX_HCLK
Maximum HCLK Speed
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5.4.2.4
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Part Number Symbolization
Device part number symbolization information can be determined from the device-specific datasheet or
can be computed by reading locations in the TI OTP bank 0 registers.
For example the device part number symbolization "TMS570LS3137CPGEQQ1" can be read from TI OTP
bank 0 location F008 01E0h through F008 01FFh as shown in Figure 5-5.
Figure 5-5. TI OTP Bank 0 Symbolization Information (F008 01E0h-F008 01FFh)
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x54
0x4D
0x53
0x35
0x37
0x30
0x4C
0x53
0x33
0x31
0x33
0x37
0x43
0x50
0x47
0x45
R
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x51
0x51
0x31
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
R
LEGEND: R = Read only
5.4.2.5
Deliberate ECC Errors for FMC ECC Checking
Deliberate single-bit and double-bit errors have been placed in the OTP for checking the FMC ECC
functionality. Any portion of the 64 bits in TI OTP bank 0 location F008 03F0h through F008 03F7h as
shown in Figure 5-6 will generate a single-bit error. Any portion of the 64 bits in TI OTP bank 0 location
F008 03F8h through F008 03FFh as shown in Figure 5-6 will generate a double-bit error.
Figure 5-6. TI OTP Bank 0 Deliberate ECC Error Information (F008 03F0h-F008 03FFh)
0x00
0x04
0x08
0x0C
0x12345678
0x9ABCDEF1
0x12345678
0x9ABCDEF3
R
R
R
R
LEGEND: R = Read only, ECC is calculated for the value 0x123456789ABCDEF0
5.5
Power On, Power Off, and Reset Considerations
5.5.1 Error Checking at Power On
As the device is coming out of the device reset sequence, the Flash wrapper reads two configuration
words from the TI OTP section of bank 0, the hardware configuration word at address 0xF0080140, and
then the AJSM visible password at address 0xF0000000. During these reads ECC is enabled. Single-bit
errors are corrected and generate an ESM group 1 channel 6 error event. The first failing address will be
latched in the FCOR_ERR_ADD register along with the bit position in FCOR_ERR_POS register and the
FEDACSTATUS register flags will be updated to indicate the type of error. Uncorrectable errors will
generate an ESM group 3 channel 7 error event, the ERROR pin will be activated, the first failing address
will be latched in the FUNC_ERR_ADD register and the FEDACSTATUS register flags will be updated to
indicate the type of error.
5.5.2 Flash Integrity when Reset while Programming or Erasing
If a device is reset while programming, then the bits being programmed when reset is asserted are
indeterminate; however, the other bits in the Flash are not disturbed. Likewise, If the device is reset while
being erased, the sector or sectors being erased will have indeterminate bits; however, the other sectors
in the same bank and the other banks will not be disturbed.
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5.5.3 Flash Integrity at Power Off
If power is lost during a programming or erase operation, a power-on reset must be asserted before the
core supply voltage drops below specification. The PORRST pin has a glitch filter which means that the
PORRST pin must be asserted low tf(nPORRST) (2µs) before the core supply drops below VccMIN (1.14V). If
this requirement is met, then the bits being programmed when PORRST goes low are indeterminate;
however, the other bits in the Flash are not disturbed. Likewise, if this requirement is met, and PORRST is
asserted while erasing, the sector or sectors being erased will have indeterminate bits; however, the other
sectors in the same bank and the other banks will not be disturbed.
5.6
Emulation and SIL3 Diagnostic Modes
5.6.1 System Emulation
During emulation when the SUSPEND signal is high, the data read from memory is still passed to
SECDED for correction if ECC_ENABLE is active. If a correctable error is detected, then it is corrected but
error event is not generated and error occurrence counter is not incremented if in profiling mode. If a
double error is detected, then the raw data is returned without generating a double-error signal.
The SUSPEND signal can be disable by using the SUSP_IGNR bit in the Flash error detection and
correction control register 1 (FEDACCTRL1). The SUSPEND signal should not be confused with the
suspend_now operation for the FSM.
5.6.2 Diagnostic Mode
The Flash wrapper can be put in diagnostic mode to verify various logic. There are multiple diagnostic
modes supported by the wrapper. A specific diagnostic mode is selected via the DIAG_MODE control bits
in the diagnostic control register (FDIAGCTRL), as listed in Table 5-8.
The diagnostic mode is only enabled by a 4-bit key stored in the DIAG_EN_KEY bits in FDIAGCTRL
register. Only DIAG_EN_KEY = 0101 enables any diagnostic mode and all diagnostic modes use the
DIAG_TRIG bit in FDIAGCTRL register to initiate the action.
All tests run from any pipeline mode. Some of the diagnostic modes can corrupt the Flash data access,
and generate errors as part of the test. Running in non-pipeline may minimize some of these conditions.
For all modes it is best to follow this sequence:
1. Write 0101 to the DIAG_EN_KEY bits and set the desired DIAG_MODE control bits. This blocks many
UERR sources.
2. Set any data registers needed for this mode.
3. Write 1 to the DIAG_TRIG bit to initiate the action and allow UERRs to happen for one cycle.
4. Write 1010 to the DIAG_EN_KEY bits to disable the diagnostic modes.
When the CONF_TYPE is 5, the ECC logic is in the CPU and most diagnostic modes are removed. Some
because the logic they test no longer exists and the rest because the path is validated via the ECC path to
the CPU.
Table 5-8. DIAG_MODE Encoding
Mode
DIAG_MODE Bits
Description
0
0
0
0
Diagnostic mode is disabled. Same as DIAG_EN_KEY not equal to 5h.
1
0
0
1
ECC Data Correction test mode
2
0
1
0
ECC Syndrome Reporting test mode
3
0
1
1
ECC Malfunction test mode 1 (same data)
4
1
0
0
ECC Malfunction test mode 2 (inverted data)
5
1
0
1
Address Tag Register test mode
6
1
1
0
Reserved
7
1
1
1
ECC Data Correction Diagnostic test mode
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ECC Data Correction Test Mode: DIAG_MODE = 1
This diagnostic mode can be enabled while ECC logic is also enabled for normal bank read. The Flash
wrapper will arbitrate the usage of the ECC logic if a conflict occurs between a normal bank read and
diagnostic checking.
When in diagnostic data correction mode, FEMU_xxxx registers contain the 64-bit EEPROM emulation
data register, the 19-bit emulation address register and the 8-bit emulation check-bit register. These
values are used to enter diagnostic data to exercise the SECDED logic. The user can apply a value with
an error in any bit location. When the DIAG_TRIG is set, the SECDED calculation is done and the
corrected values are saved back into the same FEMU_xxxx registers. The error position register is also
updated to indicate the bit position in error. Either ERR_ONE_FLG or ERR_ZERO_FLG bit is set when a
correctable error is detected. The D_COR_ERR bit will also be set in FEDACSTATUS register. For
uncorrectable error, the error status bit ERR_PRF_FLG is set as well as the D_UNC_ERR bit in the same
register. Status bits should be cleared by the user before applying a new diagnostic data.
It takes multiple CPU transactions to preload the registers with diagnostic values. During this time, the
result of the diagnostic logic such as comparator can change. User should apply a trigger by setting
DIAG_TRIG bit to 1 as a qualifier after all registers are loaded with intended values. The DIAG_TRIG
serves to validate the diagnostic result. Only when DIAG_TRIG is high and a failing result in the diagnostic
logic will update the corresponding status flag and the position register.
5.6.2.2
ECC Syndrome Reporting Test Mode: DIAG_MODE = 2
When in diagnostic syndrome reporting mode, the resulting syndrome calculated by SECDED is captured
into the ECC check-bit register FEMU_ECC. The syndrome can be read by the user and compare with a
known syndrome value. Diagnostic data in FEMU_DxSW and FEMU_ADDR is not corrected and the error
position register is not updated. The FEDACSTATUS register error bits are not updated during this mode.
For devices with ECC_IN_CPU (CONF_TYPE = 5), the resulting FEMU_ECC value represents the 32-bit
byte swapped values. Here, bytes 7654_3210 are rearranged to 4567_0123. For instance, if the syndrome
shows an error in data bit 33, it would really be an error in EMU_DMW bit 57. You can also XOR the data
bit position with “011000”. (21h XOR 18h => 39h)
NOTE: The user should pre-load the registers with the test values with DIAG_TRIG = 0. After all test
values are written, the DIAG_TRIG should then be set high to validate the diagnostic result.
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5.6.2.3
ECC Malfunction Test Mode 1: DIAG_MODE = 3
There are three inputs to the malfunction detection logic: the resulting syndrome, the original uncorrected
data, and the final corrected data.
In normal function, the malfunction detection logic will detect an error if the syndrome is 0 and if the data
before the correction and the data after the correction is not equal; or if the syndrome is not 0 and if the
data before the correction and data after the correction is equal to each other. During diagnostic mode 3
or 4, user supplied values are sent to the malfunction logic. No functional checking is done by the
ecc_malfunction logic while the mode is 3 or 4.
Diagnostic mode 3 is also known as “same data” mode. A diagnostic value can be stored in the ECC
checkbit register. The value stored in the 64-bit Raw data register will be supplied to the two inputs of the
malfunction comparator logic. If a non-zero value is stored in the Raw ECC checkbit register
(FRAW_ECC), then the malfunction logic should detect it as an error. The DIAG_TRIG is set to initiate this
mode.
5.6.2.4
ECC Malfunction Test Mode 2: DIAG_MODE = 4
Diagnostic mode 4 is also known as “inverted data” mode. A diagnostic value can be stored in the ECC
checkbit register. A value stored in the 64-bit Raw data register and its bit-wise inverted counterpart will be
supplied to the two inputs of the malfunction comparator logic. If a zero value is stored in the Raw ECC
checkbit register (FRAW_ECC), then the malfunction logic should detect it as an error.
Set the DIAG_ECC_SEL bits before entering mode 4 or enter mode 4 from a non-mode 4 and set the
DIAG_ECC_SEL bits at the same time.
5.6.2.5
Address Tag Register Test Mode: DIAG_MODE = 5
NOTE: The test code for Diag mode 5 needs to be executed from RAM or when executed from
Flash, the Flash Address Wait State (ASWSTEN) bit in the FRDCNTL register should be set
to 1. This is due to conflicting accesses by the CPU and Flash wrapper during the test
execution.
There are four sets of address tag registers. Each set consists of a primary and a duplicate address tag
registers. Normally, these registers store the recently issued CPU addresses during pipeline mode. To
detect errors in these registers, the primary and duplicate address tag registers are continuously
compared to each other if the buffer is valid. If they are different, then an address tag register error event
is generated.
These registers are memory-mapped. All primary address tag registers are memory-mapped to one
address and, likewise, all duplicate tag registers are mapped to another single address. During diagnostic
mode, each individual set can be selected by the DIAG_BUF_SEL (Diagnostic Buffer Select) bit in the
FDIAGCTRL register. User-supplied values can be written into the selected set during a diagnostic mode.
If different values are written into the primary and the duplicate address tag registers, then the
ADD_TAG_ERR (Address Tag Error) flag in the FEDACSTATUS register will be set. This diagnostic mode
uses the FRAW_DATAL register to supply the alternate address when DIAG_TRIG is set. The
FUNC_ERR_ADD register will not contain useful information during Diag mode 5. It will also trigger the
normal uncorrectable register freeze.
All address tags and buffer valid bits will be cleared to 0 when leaving Diag mode 5. Going to mode 5 and
back out clears the pipeline buffers and is useful for other test modes also. No functional checking is done
by the address tag logic while the mode is 5.
NOTE: The user should pre-load the registers with the test values with DIAG_TRIG = 0. After all test
values are written, the DIAG_TRIG should then be set high to validate the diagnostic result.
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ECC Data Correction Diagnostic Test Mode: DIAG_MODE = 7
Testing the error correction and ECC logic in the CPU involves corrupting the ECC value returned to the
CPU. By inverting one or more bits of the ECC, the CPU will detect errors in a selected data or ECC bit, or
in any possible value returned by the ECC.
To set an error for a particular bit use the syndrome, see Section 5.3.3. For example, if you want to
corrupt data bit 62 then put the value 5Bh into the test register.
The method uses the DATA_INV_PAR value in the FPAR_OVR register to alter the ECC during a slave
access cycle. The value in the DATA_INV_PAR register will be XORed with the current ECC to give a bad
ECC value to the CPU. This only will occur when the DIAG_MODE is 7, the PAR_OVR_KEY is 5, the
DIAG_EN_KEY in the FDIAGCTRL register is 5 and the access is a slave cycle.
This mode can set the FEDACSTATUS register status error bits B1_UNC_ERR or ERR_ZERO_FLG, but
it will not set the D_UNC_ERR nor D_COR_ERR bits.
The sequence to do this test is:
1. Make sure the true DMA module is off.
2. Put 5h in BUS_PAR_DIS and 5h in PAR_OVR_KEY fields (00005Axxh) of the FPAR_OVR register.
3. Put the desired value in DAT_INV_PAR field of the FPAR_OVR register.
4. Put 7h in DIAG_MODE and 5h in DIAG_EN_KEY fields of the FDIAGCTRL register.
5. Read desired address from the mirrored Flash location. Mirrored Flash starts at address 0x20000000.
6. Put 0 in DIAG_MODE or Ah in one of the key fields to turn off this test.
7. Check error registers (FCOR_ERR_ADD, FEDACSTATUS, and FUNC_ERR_ADD) for ECC errors.
8. Repeat as necessary to test out the ECC.
9. Put 0 in DIAG_MODE field of the FDIAGCTRL register and Ah in both of the key fields to completely
disable this test at the end of the test.
10. Put 2h in PAR_OVR_KEY field (00005400h) of the FPAR_OVR register to clear DAT_INV_PAR field.
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5.6.3 Diagnostic Mode Summary
The following tables give a summary of the input registers needed for each mode, the possible registers
that can change, and the possible error bits in FEDACSTATUS register that may set.
Table 5-9. Bus 1 Diagnostic Mode Summary
DIAG
MODE
Name
Inputs
Possible Error Bits
Set
Possible Outputs
Notes
1
ECC Data Correction
test mode
Not Applicable
2
ECC Syndrome Reporting
test mode
Not Applicable
3
ECC Malfunction
test mode 1
Not Applicable
4
ECC Malfunction
test mode 2
Not Applicable
5
Address Tag Register
test mode
FPRIM_ADD_TAG
FUNC_ERR_ADD
(1)
ADD_TAG_ERR
FDUP_ADD_TAG
FRAW_DATAL
(1)
6
Reserved
7
ECC Data Correction
Diagnostic test mode
DAT_INV_PAR
FUNC_ERR_ADD
B1_UNC_ERR
FCOR_ERR_ADD
ERR_ZERO_FLG
Slave access
only
Register output value will change, but will not contain useful information.
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Table 5-10. Bus 2 and ECC Diagnostic Mode Summary
DIAG
MODE Name
1
ECC Data Correction
test mode
Inputs
Possible Outputs
Possible Error Bits Set
FEUM_DMSW
FEMU_ECC
D_UNC_ERR
FEMU_DLSW
FUNC_ERR_ADD
D_COR_ERR
FEMU_ECC
FCOR_ERR_ADD
ERR_ONE_FLG
FEMU_ADDR
FCOR_ERR_POS
ERR_ZERO_FLG
Notes
ERR_PRF_FLG
FEMU_ECC
EE_D_UNC_ERR
EE_UNC_ERR_ADD
EE_D_COR_ERR
EE_COR_ERR_ADD
EE_ERR_ONE_FLG
EE_COR_ERR_POS
EE_ERR_ZERO_FLG
EE_ERR_PRF_FLG
2
ECC Syndrome
Reporting test mode
FEMU_DMSW
FEMU_ECC
NA
FEMU_DLSW
FEMU_ECC
FEMU_ADDR
3
ECC Malfunction
test mode 1
FRAW_DATAH
(1)
ECC_B2_MAL_ERR
FRAW_DATAL
FRAW_DATAL
(1)
D_UNC_ERR
FRAW_ECC
FRAW_ECC
FRAW_DATAH
(1)
FUNC_ERR_ADD
(1)
FRAW_DATAH
(1)
EE_CME
FRAW_DATAL
(1)
EE_D_UNC_ERR
FRAW_ECC
(1)
EE_UNC_ERR_ADD
4
ECC Malfunction
test mode 2
FRAW_DATAH
FRAW_DATAH
(1)
FRAW_DATAL
FRAW_DATAL
(1)
FRAW_ECC
FRAW_ECC
(1)
ECC_B2_MAL_ERR
(1)
FRAW_DATAH
(1)
EE_CMG
FRAW_DATAL
(1)
EE_CME
FRAW_ECC
(1)
EE_UNC_ERR_ADD
266
COMB2_MAL_G
D_UNC_ERR
FUNC_ERR_ADD
(1)
(1)
EE_D_UNC_ERR
(1)
5
Address Tag Register
test mode
Not applicable
6
Reserved
Not applicable
7
ECC Data Correction
Diagnostic test mode
Not applicable
Register output value will change, but will not contain useful information.
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Table 5-11. Port Signals Diagnostic Mode Summary
DIAG
MODE Name
1
Error In
Uncorrectable
Error
Correctable
Error
Address Bus
Parity Error
FEE
Uncorrectable
Error
FEE
Correctable
Error
ESM Group 3
Channel 7
ESM Group 1
Channel 6
ESM Group 2
Channel 4
ESM Group 1
Channel 36
ESM Group 1
Channel 35
ECC Data Correction
test mode
Bus 2
Yes
Yes
No
No
No
EEPROM
No
No
No
Yes
Yes
ECC Syndrome
Reporting test mode
Bus 2
No
No
No
No
No
EEPROM
No
No
No
No
No
3
ECC Malfunction
test mode 1
Bus 2
Yes
No
No
No
No
EEPROM
No
No
No
Yes
No
4
ECC Malfunction
test mode 2
Bus 2
Yes
No
No
No
No
EEPROM
No
No
No
Yes
No
Yes
No
No
No
No
Yes
Yes
No
No
No
2
5
Address Tag Register Bus 1
test mode
6
Reserved
7
ECC Data Correction
Diagnostic test mode
Bus 1
5.6.4 Read Margin
When the bits are programmed or erased, they are checked against a program_verify or erase_verify
reference level that is far away from the normal read reference point. Over time, bit levels may drift toward
the normal read point and if it is too much then a bit will read the wrong value. To counteract this, the bits
can be read using different read_margin reference points to give an early detection of the problem. The
bits can then be either re-programmed (most common) or the sector can be erased and reprogrammed.
5.7
Control Registers
This section details the Flash module registers, summarized in Table 5-12. A detailed description of each
register and its bits is also provided.
The Flash module control registers can only be read and/or written by the CPU while in privileged mode.
Each register begins on a word boundary. All registers are 32-bit, 16-bit and 8-bit accessible. The start
address of the Flash module is FFF8 7000h.
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Table 5-12. Flash Control Registers
268
Address
Acronym
Register Description
FFF8 7000h
FRDCNTL
Flash Option Control Register
Section 5.7.1
Section
FFF8 7008h
FEDACTRL1
Flash Error Detection and Correction Control Register 1
Section 5.7.2
FFF8 700Ch
FEDACTRL2
Flash Error Detection and Correction Control Register 2
Section 5.7.3
FFF8 7010h
FCOR_ERR_CNT
Flash Correctable Error Count Register
Section 5.7.4
FFF8 7014h
FCOR_ERR_ADD
Flash Correctable Error Address Register
Section 5.7.5
FFF8 7018h
FCOR_ERR_POS
Flash Correctable Error Position Register
Section 5.7.6
FFF8 701Ch
FEDACSTATUS
Flash Error Detection and Correction Status Register
Section 5.7.7
FFF8 7020h
FUNC_ERR_ADD
Flash Uncorrectable Error Address Register
Section 5.7.8
FFF8 7024h
FEDACSDIS
Flash Error Detection and Correction Sector Disable Register
Section 5.7.9
FFF8 7028h
FPRIM_ADD_TAG
Flash Primary Address Tag Register
Section 5.7.10
FFF8 702Ch
FDUP_ADD_TAG
Flash Duplicate Address Tag Register
Section 5.7.11
FFF8 7030h
FBPROT
Flash Bank Protection Register
Section 5.7.12
FFF8 7034h
FBSE
Flash Bank Sector Enable Register
Section 5.7.13
FFF8 7038h
FBBUSY
Flash Bank Busy Register
Section 5.7.14
FFF8 703Ch
FBAC
Flash Bank Access Control Register
Section 5.7.15
FFF8 7040h
FBFALLBACK
Flash Bank Fallback Power Register
Section 5.7.16
FFF8 7044h
FBPRDY
Flash Bank/Pump Ready Register
Section 5.7.17
FFF8 7048h
FPAC1
Flash Pump Access Control Register 1
Section 5.7.18
FFF8 704Ch
FPAC2
Flash Pump Access Control Register 2
Section 5.7.19
FFF8 7050h
FMAC
Flash Module Access Control Register
Section 5.7.20
FFF8 7054h
FMSTAT
Flash Module Status Register
Section 5.7.21
FFF8 7058h
FEMU_DMSW
EEPROM Emulation Data MSW Register
Section 5.7.22
FFF8 705Ch
FEMU_DLSW
EEPROM Emulation Data LSW Register
Section 5.7.23
FFF8 7060h
FEMU_ECC
EEPROM Emulation ECC Register
Section 5.7.24
FFF8 7068h
FEMU_ADDR
EEPROM Emulation Address Register
Section 5.7.25
FFF8 706Ch
FDIAGCTRL
Diagnostic Control Register
Section 5.7.26
FFF8 7070h
FRAW_DATAH
Uncorrected Raw Data High Register
Section 5.7.27
FFF8 7074h
FRAW_DATAL
Uncorrected Raw Data Low Register
Section 5.7.28
FFF8 7078h
FRAW_ECC
Uncorrected Raw ECC Register
Section 5.7.29
FFF8 707Ch
FPAR_OVR
Parity Override Register
Section 5.7.30
FFF8 70C0h
FEDACSDIS2
Flash Error Detection and Correction Sector Disable Register 2
Section 5.7.31
FFF8 7288h
FSM_WR_ENA
FSM Register Write Enable
Section 5.7.32
FFF8 72A4h
FSM_SECTOR
FSM Sector Register
Section 5.7.33
FFF8 72B8h
EEPROM_CONFIG
EEPROM Emulation Configuration Register
Section 5.7.34
FFF8 7308h
EE_CTRL1
EEPROM Emulation Error Detection and Correction Control
Register 1
Section 5.7.35
FFF8 730Ch
EE_CTRL2
EEPROM Emulation Error Detection and Correction Control
Register 2
Section 5.7.36
FFF8 7310h
EE_COR_ERR_CNT
EEPROM Emulation Correctable Error Count Register
Section 5.7.37
FFF8 7314h
EE_COR_ERR_ADD
EEPROM Emulation Correctable Error Address Register
Section 5.7.38
FFF8 7318h
EE_COR_ERR_POS
EEPROM Emulation Correctable Error Bit Position Register
Section 5.7.39
FFF8 731Ch
EE_STATUS
EEPROM Emulation Error Status Register
Section 5.7.40
FFF8 7320h
EE_UNC_ERR_ADD
EEPROM Emulation Uncorrectable Error Address Register
Section 5.7.41
FFF8 7400h
FCFG_BANK
Flash Bank Configuration Register
Section 5.7.42
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5.7.1 Flash Option Control Register (FRDCNTL)
FRDCNTL supports pipeline mode. This register controls Flash timings for the main Flash banks. For the
equivalent register that controls Flash timings for the EEPROM Emulation Flash bank (bank 7), see
Section 5.7.34.
Figure 5-7. Flash Option Control Register (FRDCNTL) [offset = 00h]
31
16
Reserved
R-0
15
12
11
8
Reserved
RWAIT
R-0
R/WP-1
7
5
4
3
1
0
Reserved
ASWSTEN
Reserved
ENPIPE
R-0
R/WP-0
R-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privilege Mode; -n = value after reset
Table 5-13. Flash Option Control Register (FRDCNTL) Field Descriptions
Bit
Field
31-12
Reserved
11-8
RWAIT
Value
0
0-Fh
Description
Reads return 0. Writes have no effect.
Random/data Read Wait State
The random read wait state bits indicate how many wait states are added to a Flash read access.
In Pipeline mode there is always one wait state even when RWAIT is cleared to 0.
Note: The required wait states for each HCLK frequency can be found in the device-specific data
manual.
7-5
4
Reserved
0
ASWSTEN
Reads return 0. Writes have no effect.
Address Setup Wait State Enable
0
Address Setup Wait State is disabled.
1
Address Setup Wait State is enabled. Address is latched one cycle before decoding to determine
pipeline hit or miss. Address Setup Wait State is only available in pipeline mode.
Note: The required address wait state for each HCLK frequency can be found in the device-specific
data manual.
3-1
0
Reserved
0
ENPIPE
Reads return 0. Writes have no effect.
Enable Pipeline Mode
0
Pipeline mode is disabled.
1
Pipeline mode is enabled.
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5.7.2 Flash Error Detection and Correction Control Register 1 (FEDACCTRL1)
This register controls ECC event detection for the main Flash banks. For the equivalent register that
controls ECC event detection for the EEPROM Emulation Flash bank (bank 7), see Section 5.7.35.
Figure 5-8. Flash Error Detection and Correction Control Register 1 (FEDACCTRL1) [offset = 08h]
31
25
24
Reserved
SUSP_IGNR
R-0
R/WP-0
23
20
19
16
Reserved
EDACMODE
R-0
R/WP-Ah
15
10
9
8
Reserved
11
EOFEN
EZFEN
EPEN
R-0
R/WP-0
R/WP-0
R/WP-0
7
4
3
0
Reserved
EDACEN
R-0
R/WP-5h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privilege Mode; -n = value after reset
Table 5-14. Flash Error Detection and Correction Control Register 1 (FEDACCTRL1)
Field Descriptions
Bit
31-25
24
Field
Reserved
Value
0
SUSP_IGNR
Description
Reads return 0. Writes have no effect.
Suspend Ignore
In emulation mode, for example, viewing memory in the debugger's window, the CPU
suspend signal is set. This bit determines whether the CPU suspend signal is ignored by the
Flash module.
0
CPU suspend signal blocks error bits setting and unfreezing.
The Flash module blocks all errors from setting the error bits in emulation mode and blocks
the unfreezing of the bits and registers by reading the FUNC_ERR_ADD register.
1
CPU suspend has no effect on error bit setting and unfreezing.
The Flash module ignores the CPU suspend signal and allows the error bits to set even in
emulation mode. It also allows the Flash module to unfreeze the error bits and other registers
by reading the FUNC_ERR_ADD register even in emulation mode.
23-20
Reserved
19-16
EDACMODE
0
Reads return 0. Writes have no effect.
Error Correction Mode for the main Flash banks. For EEPROM Emulation Flash bank (bank
7), see Section 5.7.35.
5h
Single-bit errors during reads from OTP, ECC and the mirrored space (starting at
0x20000000) of banks 0 through 6, will be treated as uncorrectable errors by the Flash
wrapper. The wrapper will assert an ESM group 3 error on channel 7 and the ERROR pin
will be activated. No abort will be taken by the CPU.
All Other Values Single-bit errors during reads from OTP, ECC and the mirrored space (starting at
0x20000000) of banks 0 through 6, will be treated as correctable errors by the Flash
wrapper. The wrapper will assert an ESM group 1 error on channel 6. The single-bit error will
be corrected.
Note: This mode does not affect reads from the main program Flash starting at address 0.
Note: Reading ECC bits will generate an ECC error based on the contents of the 8 ECC bits
and the 64 data bits they protect.
15-11
270
Reserved
0
Reads return 0. Writes have no effect.
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Table 5-14. Flash Error Detection and Correction Control Register 1 (FEDACCTRL1)
Field Descriptions (continued)
Bit
Field
10
EOFEN
Value
Description
Event on One's Fail Enable
0
No ESM error event is generated on a single-bit error where a 1 reads as a 0 when reading
from the OTP or ECC memory locations.
1
An ESM error event is generated on a single-bit error where a 1 reads as a 0 when reading
from the OTP or ECC memory locations.
Note: When either the EOFEN or the EZFEN bit is set, an error event will be generated on
ESM group 1 channel 6 when any correctable error is generated by reading the main
memory.
9
EZFEN
Event on Zero's Fail Enable
0
No ESM error event is generated on a single-bit error where a 0 reads as a 1 when reading
from the OTP or ECC memory locations.
1
An ESM error event is generated on a single-bit error where a 0 reads as a 1 when reading
from the OTP or ECC memory locations.
Note: When either the EOFEN or the EZFEN bit is set, an error event will be generated on
ESM group 1 channel 6 when any correctable error is generated by reading the main
memory.
8
EPEN
Error Profiling Enable.
0
Error profiling is disabled.
1
Error profiling is enabled.
The correctable error event is generated (ESM group 1 channel 6) when the number of CPU
accesses of correctable bit errors detected and corrected has reached the threshold value
defined in the FEDACCTRL2 register.
7-4
Reserved
3-0
EDACEN
0
Reads return 0. Writes have no effect.
Error Detection and Correction Enable
5h
CPU single and double error event signals are blocked.
Note: It is recommended to enable ECC in the Flash wrapper by writing 1010 to these bits
before enabling ECC in the CPU. If ECC is enabled in the CPU, but not in the wrapper, the
CPU will still check and correct single-bit ECC errors, and generate aborts on uncorrectable
errors for the main Flash. However, the generation of ESM events, the capture of failing
addresses and the detections and correction of errors in the OTP will be prevented.
All Other Values Error Detection and Correction events are captured and sent to the ESM.
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5.7.3 Flash Error Correction and Correction Control Register 2 (FEDACCTRL2)
This register applies to ECC event detection for the main Flash banks. For the equivalent register that
applies to the EEPROM Emulation Flash bank (bank 7), see Section 5.7.36.
Figure 5-9. Flash Error Correction and Correction Control Register 2 (FEDACCTRL2)
[offset = 0Ch]
31
16
Reserved
R-0
15
0
SEC_THRESHOLD
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privilege Mode; -n = value after reset
Table 5-15. Flash Error Correction Control and Correction Register 2 (FEDACCTRL2)
Field Descriptions
Bit
Field
Value
31-16
Reserved
15-0
SEC_THRESHOLD
0
Description
Reads return 0. Writes have no effect.
Single Error Correction Threshold
When error profiling is enabled, this register contains the threshold value for the SEC
(single error correction) occurrences before a correctable error event is generated (ESM
group 1, channel 6). A threshold of zero disables the threshold so that it does not generate
an event.
5.7.4 Flash Correctable Error Count Register (FCOR_ERR_CNT)
This register applies to the main Flash banks. For the equivalent register that applies to the EEPROM
Emulation Flash bank (bank 7), see Section 5.7.37.
Figure 5-10. Flash Correctable Error Count Register (FCOR_ERR_CNT) [offset = 10h]
31
16
Reserved
R-0
15
0
FERRCNT
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privilege Mode; -n = value after reset
Table 5-16. Flash Correctable Error Count Register (FCOR_ERR_CNT) Field Descriptions
Bit
Field
31-16
Reserved
15-0
FERRCNT
Value
0
Description
Reads return 0. Writes have no effect.
Single Error Correction Count
This register contains the number of SEC (single error correction) occurrences. Writing any value to
this register resets the count value to 0. The counter resets to 0 when it increments to be equal to
the single error correction threshold. This register only increments when profiling mode is enabled.
This register is not affected by the EOFEN or EZEFEN error control bits in the FEDACCTRL1
register.
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5.7.5 Flash Correctable Error Address Register (FCOR_ERR_ADD)
This register applies to the main Flash banks. For the equivalent register that applies to the EEPROM
Emulation Flash bank (bank 7), see Section 5.7.38.
The error address is captured during errors when either EOFEN or EZFEN enable bit is set. During error
profiling mode when only EPEN is set, the error address is not captured if a correctable error is detected.
This register is frozen while either the ERR_ZERO_FLG or the ERR_ONE_FLG bit is set in the
FEDACSTATUS register.
During emulation mode, this address is frozen even when read. By setting the SUSP_IGNR bit (see
Table 5-14), this register can be unfrozen in emulation mode.
This register is not changed with the reset signal and contains unknown data at power-up.
Figure 5-11. Flash Correctable Error Address Register (FCOR_ERR_ADD) [offset = 14h]
31
16
COR_ERR_ADD
R-u
15
3
2
0
COR_ERR_ADD
B_OFF
R-u
R-u
LEGEND: R = Read only; -n = value after reset; -u = unchanged value on internal reset, cleared on power up
Table 5-17. Flash Correctable Error Address Register (FCOR_ERR_ADD) Field Descriptions
Bit
31-3
Field
COR_ERR_ADD
Value
Description
0-1FFF FFFFh
Correctable Error Address
COR_ERR_ADD records the CPU logical address of which a correctable error is
detected by the ECC logic. This error address is frozen from begin updated until it is
read by the CPU. Additional error are blocked until this register is read.
2-0
B_OFF
0-7h
Byte Offset
Since ECC is checked on 64 bit data, when checking main memory or OTP, the
address captured is aligned to a 64-bit boundary with address bits[2:0] equal to
0.When reading from the ECC bytes, these bits will indicate the failing address of the
ECC location associated with the failure. When reading an ECC byte, the ECC is
checked against the 64 data bits they protect.
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5.7.6 Flash Correctable Error Position Register (FCOR_ERR_POS)
This register applies to the main Flash banks. For the equivalent register that applies to the EEPROM
Emulation Flash bank (bank 7), see Section 5.7.39.
Note: The bit error position is only detected during reads of the OTP, the mirrored Flash image or the
ECC bytes. Single-bit errors corrected during reads of the main memory will only capture the failing
address, but not the bit position. The bit position is captured during errors when either EOFEN or EZFEN
enable bit is set. During error profiling mode when only EPEN is set, the bit position is not captured if a
correctable error is detected. This register is frozen while either the ERR_ZERO_FLG or the
ERR_ONE_FLG bit is set in the FEDACSTATUS register.
During emulation mode, this address is frozen even when read. By setting the SUSP_IGNR bit, this
register can be unfrozen in emulation mode.
This register is not changed with the reset signal and contains unknown data at power-up.
Figure 5-12. Flash Correctable Error Position Register (FCOR_ERR_POS) [offset = 18h]
31
16
Reserved
R-0
15
9
8
Reserved
10
BUS2
TYPE
7
ERR_POS
0
R-0
R-u
R-u
R-u
LEGEND: R = Read only; -n = value after reset; -u = unchanged value on internal reset, cleared on power up
Table 5-18. Flash Correctable Error Position Register (FCOR_ERR_POS) Field Descriptions
Bit
31-10
9
8
7-0
274
Field
Reserved
Value
0
BUS2
Reads return 0. Writes have no effect.
Bus 2 Error
0
The error was in the main Flash.
1
The error was from an OTP read.
TYPE
ERR_POS
Description
ErrorType
0
The error was one of the 64 data bits.
1
The error was one of the 8 check bits.
The bit address of the single-bit error.
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5.7.7 Flash Error Detection and Correction Status Register (FEDACSTATUS)
This register applies to the main Flash banks. For the equivalent register that applies to the EEPROM
Emulation Flash bank (bank 7), see Section 5.7.40.
All these error status bits can be cleared by writing a 1 to the bit. Writing a 0 has no effect.
The correctable errors in bits 2:0, and FSM_DONE bit 24, must be cleared before the end of their error
event service routine or else the error event will re-issue.
Figure 5-13. Flash Error Detection and Correction Status Register (FEDACSTATUS)
[offset = 1Ch]
31
25
24
Reserved
26
Reserved
FSM_DONE
R-0
R-0
RCP-u
23
20
Reserved
19
18
COMB2_MAL_ ECC_B2_MAL_
G
ERR
R-0
RCP-u
15
13
RCP-u
17
16
B2_UNC_
ERR
B2_COR_
ERR
RCP-u
RCP-u
12
11
10
9
8
Reserved
D_UNC_
ERR
ADD_TAG_
ERR
ADD_PAR_
ERR
Reserved
B1_UNC_
ERR
R-0
RCP-u
RCP-u
RCP-u
R-0
RCP-u
4
3
2
1
0
Reserved
D_COR_
ERR
ERR_ONE_
FLG
ERR_ZERO_
FLG
ERR_PRF_
FLG
R-0
RCP-u
RCP-u
RCP-u
RCP-u
7
LEGEND: R = Read only; RCP = Read and Clear in Privilege Mode; -n = value after reset; -u = unchanged value on internal reset, cleared
on power up
Table 5-19. Flash Error Detection and Correction Status Register (FEDACSTATUS)
Field Descriptions
Bit
Field
Value
Description
31-26
Reserved
0
Reads return 0. Writes have no effect.
25
Reserved
0
Reserved
24
FSM_DONE
Flash State Machine Done
This bit is set to 1 when the Flash state machine completes a program or erase operation.
This bit will generate an interrupt on VIM channel 61 if the FSM_EVT_EN bit of the
FSM_ST_MACHINE register is set. This bit must be cleared by writing a 1 to it in the
interrupt routine to clear the interrupt request.
23-20
19
Reserved
0
COMB2_MAL_G
Reads return 0. Writes have no effect.
Bus 2 Compare Malfunction Flag
0
Compare Malfunction is detected on the Bus 2 SECDED in diagnostic mode 4 or is not in
diagnostic mode.
1
Compare Malfunction is not detected on the Bus 2 SECDED or entered diagnostic mode 4.
This bit becomes 1 when entering diagnostic mode 4, with DIAG_ECC_SEL field set to 0 or
1, and will be cleared if diagnostic mode 4 triggers an error. This bit will reset to 0 and will
be 0 outside of diagnostic mode 4. Writing a 1 will set this bit to 1 only in diagnostic mode 4;
otherwise, writes have no effect.
18
ECC_B2_MAL_ ERR
Bus 2 ECC Malfunction Error Flag
0
SECDED malfunction is not detected on Bus 2.
1
SECDED malfunction is detected on Bus 2.
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Table 5-19. Flash Error Detection and Correction Status Register (FEDACSTATUS)
Field Descriptions (continued)
Bit
Field
17
B2_UNC_ERR
Value
Description
Bus 2 Uncorrectable Error Flag
0
No bus 2 uncorrectable errors were detected.
1
A bus 2 uncorrectable error was detected.
Two or more bits in the data, or ECC field; or a single-bit error in the address field have
been found in error. Address-bit errors are considered an uncorrectable error. The
FUNC_ERR_ADD register should contain the Bus 2 error location. This error will generate
an ESM group 3 channel 7 event.
16
B2_COR_ERR
Bus 2 Correctable Error Flag
0
No bus 2 correctable error was detected.
1
A bus 2 correctable error was detected.
One bit in the data, or ECC field has been found in error. Either the ERR_ONE_FLAG or
ERR_ZERO_FLAG should be set in this register along with this bit. The FCOR_ERR_ADD
register should contain the error address, and the FCOR_ERR_POS register should contain
the failing bit position. This error will generate an ESM group 1 channel 6 event.
15-13
12
Reserved
0
D_UNC_ERR
Reads return 0. Writes have no effect.
Diagnostic Uncorrectable Error Flag
This bit sets when diagnostic mode 1 discovers a multi-bit error using the ECC. This means
two or more bits in the data, address or ECC field have been found in error. The ECC is
capable of correcting a single-bit error and this would show up in the D_COR_ERR bit. The
ECC can always detect two bit errors. Three or more bit errors may escape detection with
the ECC. This bit also may set during other uncorrectable errors and during the diagnostic
mode like address tag errors and ECC malfunctions.
11
ADD_TAG_ERR
Address Tag Register Error Flag
0
No address tag register error was detected.
1
An address tag register error was detected.
This bit is set if the primary address tag has a hit but the duplicate address tag does not
match the primary address tag. This bit is functional only when pipeline mode is enabled.
This error will create an ESM group 3 channel 7 event.
10
ADD_PAR_ERR
Address Parity Error Flag
0
No address parity error was detected.
1
A parity error was detected on the incoming address bus.
The full 32 bit address will be stored in FUNC_ERR_ADD register. This error will create an
ESM group 2 channel 4 event.
9
Reserved
8
B1_UNC_ERR
0
Reads return 0. Writes have no effect.
Bus 1 Uncorrectable Error Flag
0
No bus 1 uncorrectable errors were detected.
1
A bus 1 uncorrectable error was detected.
Two or more bits in the data, or ECC field; or a single-bit error in the address field have
been found in error. Address-bit errors are considered an uncorrectable error. The
FUNC_ERR_ADD register will contain the Bus 1 error location. This error will generate an
ESM group 3 channel 7 event..
7-4
3
Reserved
0
D_COR_ERR
Reads return 0. Writes have no effect.
Diagnostic Correctable Error Status Flag
This bit sets when diagnostic mode 1 discovers a single-bit correctable error using the ECC.
Multi-bit errors are flagged using the D_UNC_ERR bit. The uncorrectable error address
must be unfrozen in order to set this bit.
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Table 5-19. Flash Error Detection and Correction Status Register (FEDACSTATUS)
Field Descriptions (continued)
Bit
2
Field
Value
ERR_ONE_FLG
Description
Error on One Fail Status Flag
0
No correctable error where a 1 was read as a 0 on bus 2.
1
A correctable error occurred on bus 2 where a 1 was read as a 0.
This bit is set if the EOFEN (Error on One Fail Enable) bit is set then, and one bit in the
data, or ECC field which should have been read as a 1 reads as a 0. During the read, the
bit is corrected to a 1. The FCOR_ERR_ADD register will contain the bus 2 error address,
and the FCOR_ERR_POS register will contain the failing bit position. This error will
generate an ESM group 1 channel 6 event. When this bit is set, the B2_CORR_ERR bit will
also be set. This error will generate an ESM group 1 channel 6 event.
1
ERR_ZERO_ FLG
Error on Zero Fail Status Flag
0
No correctable errors on bus 1 nor any correctable errors on bus 2 where a 0 was read as a
1.
1
A correctable error occurred on bus 1, or a correctable error occurred on bus 2 where a 0
was read as a 1.
This bit is set if the EZFEN (Error on Zero Fail Enable) bit is set and a correctable error is
detected on bus 2 where a 0 is read as a 1 and corrected to a 0, or if either the EZFEN or
the EOFEN bits are set and any single-bit error is detected and corrected on bus 1. The
FCOR_ERR_ADD register will contain the error address. If the error was on bus 2, then the
B2_COR_ERR bit will also be set and the FCOR_ERR_POS register will contain the failing
bit position. The FCOR_ERR_POS register will not indicate the failing bit position for a bus
1 error. This error will generate an ESM group 1 channel 6 event.
0
ERR_PRF_FLG
Error Profiling Status Flag
0
Error profiling is not enabled, or the number of correctable errors has not reached the
threshold programmed into the SEC_THRESHOLD register.
1
Error profiling is enabled and the number of correctable errors has reached the threshold
programmed into the SEC_THRESHOLD register.
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5.7.8 Flash Uncorrectable Error Address Register (FUNC_ERR_ADD)
This register applies to ECC event detection for the main Flash banks. For the equivalent register that
applies to the EEPROM Emulation Flash bank (bank 7), see Section 5.7.41.
During emulation mode, this address is frozen even when read. By setting the SUSP_IGNR bit, (see
Table 5-14) this register can be unfrozen in emulation mode.
This register is not changed with the reset signal and contains unknown data at power-up.
Figure 5-14. Flash Uncorrectable Error Address Register (FUNC_ERR_ADD) [offset = 20h]
31
16
UNC_ERR_ADD
R-u
15
3
2
0
UNC_ERR_ADD
B_OFF
R-u
R-u
LEGEND: R = Read only; -n = value after reset; -u = unchanged value on internal reset, cleared on power up
Table 5-20. Flash Uncorrectable Error Address Register (FUNC_ERR_ADD) Field Descriptions
Bit
31-3
Field
UNC_ERR_ADD
Value
Description
0-1FFF FFFFh
Uncorrectable Error Address
UNC_ERR_ADD records the CPU logical address of which an uncorrectable error is
detected by the ECC logic in the CPU. The UNC_ERR_ADD also captures the error
address when a address bus parity mismatch is detected. This error address is frozen
from begin updated until it is read by the CPU. Additional error are blocked until this
register is read.
This register captures the full 32-bit incoming address when there is a bus parity
error. It only captures address of 22:3 for multiple bit ECC errors. Address parity
errors take priority over other errors that happen in the same cycle.
2-0
B_OFF
0-7h
Byte offset
Since ECC is checked on 64 bit data, when checking main memory or OTP, the
address captured is aligned to a 64-bit boundary with address bits[2:0] equal to
0.When reading from the ECC bytes, these bits will indicate the failing address of the
ECC location associated with the failure. When reading an ECC byte, the ECC is
checked against the 64 data bits they protect.
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5.7.9 Flash Error Detection and Correction Sector Disable Register (FEDACSDIS)
This register is used to disable the SECDED function for one or two sectors from the EEPROM Emulation
Flash (bank 7). An additional two sectors can have SECDED disabled by the use of the FEDACSDIS2
register (see Section 5.7.31).
Figure 5-15. Flash Error Detection and Correction Sector Disable Register (FEDACSDIS)
[offset = 24h]
31
29
28
27
24
23
21
20
19
16
BankID1_Inverse
Rsvd
SectorID1_inverse
BankID1
Rsvd
SectorID1
R/WP-0
R-0
R/WP-0
R/WP-0
R-0
R/WP-0
15
13
12
11
8
7
5
4
3
0
BankID0_Inverse
Rsvd
SectorID0_inverse
BankID0
Rsvd
SectorID0
R/WP-0
R-0
R/WP-0
R/WP-0
R-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privilege Mode; -n = value after reset
Table 5-21. Flash Error Detection and Correction Sector Disable Register (FEDACSDIS)
Field Descriptions
Bit
31-29
Field
Value
BankID1_Inverse
The bank ID inverse bits are used with the bank ID bits to select the bank for which a sector
is disabled. The only bank that supports sector disable is bank 7.
0
28
Reserved
Description
If BankID1 = 7h and BankID1_inverse = 0, then if a valid sector is selected by SectorID1
and SectorID1_inverse that sector will have ECC checking disabled.
other
No sector is disabled by disable ID 1.
0
Reads return 0. Writes have no effect.
27-24
SectorID1_inverse
The sector ID inverse bits are used with the sector ID bits to determine which sector is
disabled. If the sector ID bits are not pointing to a valid sector (0-3) or the sector ID inverse
bits are not an inverse of the sector ID bits, then no sector is disabled by disable ID 1.
23-21
BankID1
The bank ID bits are used with the bank ID inverse bits to select the bank for which a sector
is disabled. The only bank that supports sector disable is bank 7.
7h
If BankID1 = 7h and BankID1_inverse = 0, then if a valid sector is selected by SectorID1
and SectorID1_inverse that sector will have ECC checking disabled.
other
No sector is disabled by disable ID 1.
0
Reads return 0. Writes have no effect.
20
Reserved
19-16
SectorID1
The sector ID bits are used with the sector ID inverse bits to determine which sector is
disabled. If the sector ID bits are not pointing to a valid sector (0-3) or the sector ID inverse
bits are not an inverse of the sector ID bits, then no sector is disabled by disable ID 1.
15-13
BankID0_Inverse
The bank ID inverse bits are used with the bank ID bits to select the bank for which a sector
is disabled. The only bank that supports sector disable is bank 7.
0
12
Reserved
If BankID0 = 7h and BankID0_inverse = 0, then if a valid sector is selected by SectorID0
and SectorID0_inverse that sector will have ECC checking disabled.
other
No sector is disabled by disable ID 0.
0
Reads return 0. Writes have no effect.
11-8
SectorID0_inverse
The sector ID inverse bits are used with the sector ID bits to determine which sector is
disabled. If the sector ID bits are not pointing to a valid sector (0-3) or the sector ID inverse
bits are not an inverse of the sector ID bits, then no sector is disabled by disable ID 0.
7-5
BankID0
The bank ID bits are used with the bank ID inverse bits to select the bank for which a sector
is disabled. The only bank that supports sector disable is bank 7.
7h
If BankID0 = 7h and BankID0_inverse = 0, then if a valid sector is selected by SectorID0
and SectorID0_inverse that sector will have ECC checking disabled.
other
No sector is disabled by disable ID 0.
4
Reserved
0
Reads return 0. Writes have no effect.
3-0
SectorID0
0-Fh
The sector ID bits are used with the sector ID inverse bits to determine which sector is
disabled. If the sector ID bits are not pointing to a valid sector (0-3) or the sector ID inverse
bits are not an inverse of the sector ID bits, then no sector is disabled by disable ID 0.
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5.7.10 Primary Address Tag Register (FPRIM_ADD_TAG)
This register is used to test the pipeline address tag registers (see Section 5.6.2.5).
Figure 5-16. Primary Address Tag Register (FPRIM_ADD_TAG) [offset = 28h]
31
16
PRIM_ADD_TAG[31:16]
R/WP-0
15
4
3
0
PRIM_ADD_TAG[15:4]
0000
R/WP-0
R-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privilege Mode; -n = value after reset;
Table 5-22. Primary Address Tag Register (FPRIM_ADD_TAG) Field Descriptions
Bit
31-4
Field
Value
PRIM_ADD_TAG
Description
Primary Address Tag Register
The primary address tag register selected via DIAG_BUF_SEL bits in FDIAGCTRL register is
memory mapped here. (see Section 5.7.26) This register can only be written in privileged mode
when diagnostic mode is enabled with DIAG_EN_KEY = 5h and DIAG_MODE = 5h. This
register will not update with new Flash data if DIAG_EN_KEY is not equal to 5h or
DIAG_MODE is 0 or 7h. Valid reads can occur in any mode. The register will clear when an
address tag error is found and when leaving DIAG_MODE 5.
3-0
0
Always 0000
5.7.11 Duplicate Address Tag Register (FDUP_ADD_TAG)
This register is used to test the pipeline address tag registers (see Section 5.6.2.5).
Figure 5-17. Duplicate Address Tag Register (FDUP_ADD_TAG) [offset = 2Ch]
31
16
DUP_ADD_TAG[31:16]
R/WP-0
15
4
3
0
DUP_ADD_TAG[15:4]
0000
R/WP-0
R-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privilege Mode; -n = value after reset;
Table 5-23. Duplicate Address Tag Register (FDUP_ADD_TAG) Field Descriptions
Bit
31-4
Field
Value
DUP_ADD_TAG
Description
Primary Address Tag Register
The duplicate address tag register selected via DIAG_BUF_SEL bits in FDIAGCTRL register is
memory mapped here. (see Section 5.7.26) This register can only be written in privileged mode
when diagnostic mode is enabled with DIAG_EN_KEY = 5h and DIAG_MODE = 5h. This
register will not update with new Flash data if DIAG_EN_KEY is not equal to 5h or
DIAG_MODE is 0 or 7h. Valid reads can occur in any mode. The register will clear when an
address tag error is found and when leaving DIAG_MODE 5.
3-0
280
0
Always 0000
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5.7.12 Flash Bank Protection Register (FBPROT)
Figure 5-18. Flash Bank Protection Register (FBPROT) [offset = 30h]
31
16
Reserved
R-0
15
1
0
Reserved
PROTL1DIS
R-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privilege Mode; -n = value after reset
Table 5-24. Flash Bank Protection Register (FBPROT) Field Descriptions
Bit
31-1
0
Field
Value
Reserved
0
PROTL1DIS
Description
Reads return 0. Writes have no effect.
PROTL1DIS: Level 1 Protection Disabled
Level 1 Protection Disable bit. Setting this bit disables protection from writing to the
OTPPROTDIS bits as well as the Sector Enable registers FBSE for all banks. Clearing this bit
enables protection and disables write access to the OTPPROTDIS register bits and FBSE
register.
0
Level 1 protection is enabled.
1
Level 1 protection is disabled.
5.7.13 Flash Bank Sector Enable Register (FBSE)
FBSE provides one enable bit per sector for up to 16 sectors per bank. Each bank in the Flash module
has one FBSE register. The bank is selected via the BANK[2:0] bits of the FMAC register (see
Section 5.7.20). As only one bank at a time can be selected by FMAC, only the register for the bank
selected appears at this address.
Figure 5-19. Flash Bank Sector Enable Register (FBSE) [offset = 34h]
31
16
Reserved
R-0
15
0
BSE
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privilege Mode; -n = value after reset
Table 5-25. Flash Bank Sector Enable Register (FBSE) Field Descriptions
Bit
Field
31-16
Reserved
15-0
BSE
Value
0
Description
Reads return 0. Writes have no effect.
Bank Sector Enable
Each bit corresponds to a Flash sector in the bank specified by the FMAC register. Bit 0
corresponds to sector 0, bit 1 corresponds to sector 1, and so on. These bits can be set only when
PROTL1DIS = 1 and in privilege mode.
0
The corresponding numbered sector is disabled for program or erase access.
1
The corresponding numbered sector is enabled for program or erase access.
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5.7.14 Flash Bank Busy Register (FBBUSY)
Figure 5-20. Flash Bank Busy Register (FBBUSY) [offset = 38h]
31
16
Reserved
R-0
15
8
7
0
BUSY[7:0]
R/WP-0
R-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privilege Mode; -n = value after reset
Table 5-26. Flash Bank Busy Register (FBBUSY) Field Descriptions
Bit
Field
31-8
Reserved
7-0
BUSY[7:0]
Value
0
Description
Reads return 0. Writes have no effect.
Bank Busy
Each bit corresponds to a Flash bank.
282
0
The corresponding bank is not busy.
1
The corresponding bank is busy with a state machine or bus 2 operation, or the bank is not
implemented.
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5.7.15 Flash Bank Access Control Register (FBAC)
Figure 5-21. Flash Bank Access Control Register (FBAC) [offset = 3Ch]
31
24
23
16
Reserved
OTPPROTDIS
R-0
R/WP-0
15
8
7
0
BAGP
VREADST
R/WP-0
R/WP-Fh
LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privilege Mode; -n = value after reset
Table 5-27. Flash Bank Access Control Register (FBAC) Field Descriptions
Bit
Field
31-24
Reserved
23-16
OTPPROTDIS
Value
0
Description
Reads return 0. Writes have no effect.
OTP Sector Protection Disable
Each bit corresponds to a Flash bank. This bit can be set only when PROTL1DIS = 1 and in
privilege mode.
15-8
BAGP
0
Programming of the OTP sector is disabled.
1
Programming of the OTP sector is enabled.
0-FFh
Bank Active Grace Period
These bits contain the starting count value for the BAGP down counter. Any access to a given
bank causes its BAGP counter to reload the BAGP value for that bank. After the last access to
this Flash bank, the down counter delays from 0 to 255 prescaled HCLK clock cycles before
putting the bank into one of the fallback power modes as determined by the FBFALLBACK
register. This value must be greater than 1 when the fallback mode is not ACTIVE.
Note: The prescaled clock used for the BAGP down counter is a clock divided by 16 from
HCLK.
7-0
VREADST
0-FFh
VREAD Setup
VREAD is generated by the Flash pump and used for Flash read operation. The bank power up
sequencing starts VREADST HCLK cycles after VREAD power supply becomes stable.
Note: There is not a programmable Bank Sleep counter and Standby counter register. The
number of clock cycles to transition from sleep to standby and standby to active is hardcoded in
the Flash wrapper design.
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5.7.16 Flash Bank Fallback Power Register (FBFALLBACK)
Figure 5-22. Flash Bank Fallback Power Register (FBFALLBACK) [offset = 40h]
31
16
Reserved
R-0505h
15
14
13
4
3
2
1
0
BANKPWR7
Reserved
BANKPWR1
BANKPWR0
R/WP-3h
R/WP-3FFh
R/WP-3h
R/WP-3h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privilege Mode; -n = value after reset
Table 5-28. Flash Bank Fallback Power Register (FBFALLBACK) Field Descriptions
Bit
Field
Value
Description
31-16
Reserved
0505h
Do not write to these bits.
15-14
BANKPWR7
13-4
Reserved
3-2
BANKPWR1
1-0
284
Bank 7 Fallback Power Mode
0
Bank sleep mode
1h
Bank standby mode
2h
Reserved
3h
Bank active mode
3FFh
Do not write to these bits.
Bank 1 Fallback Power Mode
0
Bank sleep mode
1h
Bank standby mode
2h
Reserved
3h
Bank active mode
BANKPWR0
Bank 0 Fallback Power Mode
0
Bank sleep mode
1h
Bank standby mode
2h
Reserved
3h
Bank active mode
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5.7.17 Flash Bank/Pump Ready Register (FBPRDY)
Figure 5-23. Flash Bank/Pump Ready Register (FBPRDY) [offset = 44h]
31
24
15
23
16
Reserved
BANKBUSY[7:0]
R-0
R-1 (Unimplemented banks) or R-0 (Implemented banks)
14
8
7
0
PUMPRDY
Reserved
BANKRDY[7:0]
R-1
R-0
R-1
LEGEND: R = Read only; -n = value after reset
Table 5-29. Flash Pump Access Control Register 1 (FPAC1) Field Descriptions
Bit
Field
31-24
Reserved
23-16
BANKBUSY[7:0]
Value
0
Description
Reads return 0. Writes have no effect.
Bank busy bits (one bit for each bank)
0
The bank is not busy.
1
The bank is busy, not ready or this bank is not implemented.
Note: A bank is considered busy if it is being accessed by the TCM, Bus 2 or the Flash state
machine.
15
PUMPRDY
14-8
Reserved
7-0
BANKRDY[7:0]
Flash pump ready flag
0
Pump is not ready (Code must be executing from somewhere other than internal Flash).
1
Pump is ready for Flash accesses.
0
Reads return 0. Writes have no effect.
Bank ready bits (one bit for each bank)
0
Flash bank is in the sleep or standby state.
1
Flash bank is in the active state, or the bank is not implemented.
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5.7.18 Flash Pump Access Control Register 1 (FPAC1)
Figure 5-24. Flash Pump Access Control Register 1 (FPAC1) [offset = 48h]
31
27
26
16
Reserved
PSLEEP
R-0
R/WP-64h
15
1
0
Reserved
PUMPPWR
R-0
R/WP-1
LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privilege Mode; -n = value after reset
Table 5-30. Flash Pump Access Control Register 1 (FPAC1) Field Descriptions
Bit
Field
31-12
Reserved
26-16
PSLEEP
Value
0
Description
Reads return 0. Writes have no effect.
Pump Sleep
These bits contain the starting count value for the charge pump sleep down counter. While the
charge pump is in sleep mode, the power mode management logic holds the charge pump sleep
counter at this value. When the charge pump exits sleep power mode, the down counter delays
from 0 to PSLEEP pump sleep down clock cycles before putting the charge pump into active power
mode.
Note: Pump sleep down counter clock is a divide by 2 input of HCLK. That is, there are 2*HCLK
cycles for every PSLEEP counter cycle.
15-1
0
286
Reserved
0
PUMPPWR
Reads return 0. Writes have no effect.
Flash Charge Pump Fallback Power Mode
0
Sleep (all pump circuits disabled).
1
Active (all pump circuits active).
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5.7.19 Flash Pump Access Control Register 2 (FPAC2)
Figure 5-25. Flash Pump Access Control Register 2 (FPAC2) [offset = 4Ch]
31
16
Reserved
R-0
15
0
PAGP
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privilege Mode; -n = value after reset
Table 5-31. Flash Pump Access Control Register 2 (FPAC2) Field Descriptions
Bit
Field
31-16
Reserved
15-0
PAGP
Value
0
Description
Reads return 0. Writes have no effect.
Pump Active Grace Period
This register contains the starting count value for the PAGP mode down counter. Any access to
Flash memory causes the counter to reload with the PAGP value. After the last access to Flash
memory, the down counter delays from 0 to 65535 prescaled HCLK clock cycles before entering
one of the charge pump fallback power modes as determined by PUMPPWR in the FPAC1 register.
Note: The PAGP down counter is clocked by the same prescaled clock as the BAGP down counter
which is a divide by 16 of HCLK.
5.7.20 Flash Module Access Control Register (FMAC)
Figure 5-26. Flash Module Access Control Register (FMAC) [offset = 50h]
31
16
Reserved
R-0
15
3
2
0
Reserved
BANK
R-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privilege Mode; -n = value after reset
Table 5-32. Flash Module Access Control Register (FMAC) Field Descriptions
Bit
31-16
2-0
Field
Value
Reserved
BANK
0
Description
Reads return 0. Writes have no effect.
Bank Enable.
These bits select which bank is enabled for operations such as local register access, OTP sector
access, and program/erase commands. These bits select only one bank at a time from up to eight
banks depending on the specific device being used. For example, a 000 selects bank 0; 011 selects
Bank 3.
Note: BANK[2:0] can identify up to 8 Flash banks. If BANK[2:0] is selected for an unimplemented
bank then the BANK[2:0] will set itself to the number of an implemented bank. To determine if a
bank is implemented, write the bank number to BANK[2:0] and read back the value to see if what
was written can be read back.
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5.7.21 Flash Module Status Register (FMSTAT)
Figure 5-27. Flash Module Status Register (FMSTAT) [offset = 54h]
31
24
Reserved
R-0
23
16
Reserved
R-0
15
14
13
12
11
10
9
8
Reserved
ILA
Reserved
PGV
Reserved
EV
Reserved
BUSY
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
7
6
5
4
3
2
1
0
ERS
PGM
INVDAT
CSTAT
VOLTSTAT
ESUSP
PSUSP
SLOCK
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 5-33. Flash Module Status Register (FMSTAT) Field Descriptions
Bit
31-15
14
Field
Reserved
Value
0
ILA
Description
Reads return 0. Writes have no effect.
Illegal Address
When set, indicates that an illegal address is detected. Five conditions can set the illegal address
flag.
1.
2.
3.
4.
5.
13
Reserved
12
PGV
0
Writing to a hole (unimplemented logical address space) within a Flash bank.
Writing to an address location to an unimplemented Flash space.
Input address for write is decoded to select a different bank from the bank ID register.
The address range does not match the type of FSM command. For example, the erase_sector
command must match the address regions.
TI-OTP address selected but CMD_EN in FSM_ST_MACHINE is not set.
Reads return 0. Writes have no effect.
Program Verify
When set, indicates that a word is not successfully programmed after the maximum allowed
number of program pulses are given for program operation.
11
Reserved
10
EV
0
Reads return 0. Writes have no effect.
Erase Verify
When set, indicates that a sector is not successfully erased after the maximum allowed number of
erase pulses are given for erase operation. During Erase verify command, this flag is set
immediately if a bit is found to be 0.
9
Reserved
8
BUSY
7
ERS
0
Reads return 0. Writes have no effect.
Busy
When set, this bit indicates that a program, erase, or suspend operation is being processed.
Erase Active
When set, this bit indicates that the Flash module is actively performing an erase operation. This bit
is set when erasing starts and is cleared when erasing is complete. It is also cleared when the
erase is suspended and set when the erase resumes.
6
PGM
Program Active
When set, this bit indicates that the Flash module is currently performing a program operation. This
bit is set when programming starts and is cleared when programming is complete. It is also cleared
when programming is suspended and set when programming is resumes.
5
INVDAT
Invalid Data
When set, this bit indicates that the user attempted to program a 1 where a 0 was already present.
This bit is cleared by the Clear Status command.
288
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Table 5-33. Flash Module Status Register (FMSTAT) Field Descriptions (continued)
Bit
4
Field
Value
CSTAT
Description
Command Status
Once the FSM starts any failure will set this bit. When set, this bit informs the host that the
program, erase, or validate sector command failed and the command was stopped. This bit is
cleared by the Clear Status command. For some errors, this will be the only indication of an FSM
error because the cause does not fall within the other error bit types.
3
VOLTSTAT
Core Voltage Status
When set, this bit indicates that the core voltage generator of the pump power supply dipped below
the lower limit allowable during a program or erase operation. This bit is cleared by the Clear Status
command.
2
ESUSP
Erase Suspended
When set, this bit indicates that the Flash module has received and processed an erase suspend
operation. This bit remains set until the erase resume command has been issued or until the
Clear_More command is run.
1
PSUSP
Program Suspended
When set, this bit indicates that the Flash module has received and processed a program suspend
operation. This bit remains set until the program resume command has been issued or until the
Clear_More command is run.
0
SLOCK
Sector Lock Status
When set, this bit indicates that the operation was halted because the target sector was locked for
erasing and programming either by the sector protect bit or by OTP write protection disable bits.
(Bits BSE in FBSE register or OTPPROTDIS in register FBAC). This bit is cleared by the Clear
Status command.
No SLOCK FSM error will occur if all sectors in a bank erase operation are set to 1. All the sectors
will be checked but no SLOCK will be set if no operation occurs due to the SECT_ERASED bits
being set to all 1s. A SLOCK error will occur if attempting to do a sector erase with either BSE is
cleared or SECT_ERASED is set.
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5.7.22 EEPROM Emulation Data MSW Register (FEMU_DMSW)
The Flash module controller includes hardware support computing the check bits for ECC, based on the
data and address being programmed into the EEPROM emulation array. To utilize this capability, the
address to be programmed is written to the FEMU_ADDR register and the data to be programmed is
written to the FEMU_DMSW and FEMU_DLSW registers. The write to FEMU_DLSW triggers an ECC
calculation and the resulting check bits are available in the FEMU_ECC register. The value from
FEMU_ECC can then be used to program the check bits into the EEPROM emulation array for the
particular data word over which they were calculated.
Figure 5-28. EEPROM Emulation Data MSW Register (FEMU_DMSW) [offset = 58h]
31
0
EMU_DMSW[63:32]
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in Privilege mode; -n = value after reset
Table 5-34. EEPROM Emulation Data MSW Register (FEMU_DMSW) Field Descriptions
Bit
31-0
Field
Description
EMU_DMSW
EEPROM Emulation Most-Significant Data Word.
The most-significant data word of the 64-bits of data for which the ECC check bits are to be calculated
should be programmed into this register.
This register is also used in diagnostic modes 1 and 2 where it supplies the upper data for checking the
SECDED hardware.
5.7.23 EEPROM Emulation Data LSW Register (FEMU_DLSW)
The Flash module controller includes hardware support computing the check bits for ECC, based on the
data and address being programmed into the EEPROM emulation array. To utilize this capability, the
address to be programmed is written to the FEMU_ADDR register and the data to be programmed is
written to the FEMU_DMSW and FEMU_DLSW registers. The write to FEMU_DLSW triggers an ECC
calculation and the resulting check bits are available in the FEMU_ECC register. The value from
FEMU_ECC can then be used to program the check bits into the EEPROM emulation array for the
particular data word over which they were calculated.
Figure 5-29. EEPROM Emulation Data LSW Register (FEMU_DLSW) [offset = 5Ch]
31
0
EMU_DLSW[31:0]
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in Privilege mode; -n = value after reset
Table 5-35. EEPROM Emulation Data LSW Register (FEMU_DLSW) Field Descriptions
Bit
31-0
Field
Description
EMU_DLSW
EEPROM Emulation Least-Significant Data Word.
The least-significant data word of the 64-bits of data for which the ECC check bits are to be calculated
should be programmed into this register.
This register is also used in diagnostic modes 1 and 2 where it supplies the lower data for checking the
SECDED hardware.
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5.7.24 EEPROM Emulation ECC Register (FEMU_ECC)
The Flash module controller includes hardware support computing the check bits for ECC, based on the
data and address being programmed into the EEPROM emulation array. To utilize this capability, the
address to be programmed is written to the FEMU_ADDR register and the data to be programmed is
written to the FEMU_DMSW and FEMU_DLSW registers. The write to FEMU_DLSW triggers an ECC
calculation and the resulting check bits are available in the FEMU_ECC register. The value from
FEMU_ECC can then be used to program the check bits into the EEPROM emulation array for the
particular data word over which they were calculated.
Figure 5-30. EEPROM Emulation ECC Register (FEMU_ECC) [offset = 60h]
31
16
Reserved
R-0
15
8
7
0
Reserved
EMU_ECC[7:0]
R-0
R/WP-3h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privilege mode; -n = value after reset
Table 5-36. EEPROM Emulation ECC Register (FEMU_ECC) Field Descriptions
Bit
Field
31-8
Reserved
7-0
EMU_ECC[7:0]
Value
0
Description
Reserved
EEPROM Emulation ECC Check Bit Value.
This register contains the ECC check bits calculated by the FMC controller based on the address
written to FEMU_ADDR and the 64-bits of data written to FEMU_DMSW and FEMU_DLSW.
This register is also used in the diagnostic modes 1 and 2. In these modes, this register supplies
the ECC data for checking the SECDED. In mode 1, this register is filled with the desired ECC and
after the DIAG_TRIG is set this register is set to the ECC value returned from the SECDED
selected by DIAG_ECC_SEL. DIAG_EN_KEY and DIAG_TRIG must be set to fill this register in the
diagnostic modes. Writes to FEMU_DxSW will not affect this register in diagnostic modes 1 or 2.
In mode 2, this register is filled with the desired ECC and after the DIAG_TRIG is set this register is
set to the syndrome value returned from the SECDED selected by DIAG_ECC_SEL.
This register is only available when the module is configured to use the ECC logic; otherwise, it is a
reserved register.
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5.7.25 EEPROM Emulation Address Register (FEMU_ADDR)
The Flash module controller includes hardware support computing the check bits for ECC, based on the
data and address being programmed into the EEPROM emulation array. To utilize this capability, the
address to be programmed is written to the FEMU_ADDR register and the data to be programmed is
written to the FEMU_DMSW and FEMU_DLSW registers. The write to FEMU_DLSW triggers an ECC
calculation and the resulting check bits are available in the FEMU_ECC register. The value from
FEMU_ECC can then be used to program the check bits into the EEPROM emulation array for the
particular data word over which they were calculated.
Figure 5-31. EEPROM Emulation Address Register (FEMU_ADDR) [offset = 68h]
31
22
21
16
Reserved
EMU_ADDR[21:16]
R-0
R/WP-0
15
3
2
0
EMU_ADDR[15:3]
Reserved
R/WP-0
R-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privilege mode; -n = value after reset
Table 5-37. EEPROM Emulation Address Register (FEMU_ADDR) Field Descriptions
Bit
Field
31-22
Reserved
21-3
EMU_ADDR
Value
0
0-7 FFFFh
Description
Reserved. Writes have no effect. It is not necessary to mask these upper ten bits when
writing the address of bank 7 locations (0xF002xxxx); however, these bits are not used in
calculating the ECC value and will read back as 0.
EEPROM Emulation Address.
The address of the 64-bit data word over which ECC is to be calculated is written to this
field. Note that only bits 21:3 are actually written and used for the calculation. The other bits
(31:22 and 2:0) are ignored, but do not need to be masked off before being written to this
register.
This register is also used in diagnostic modes 1 and 2 where it supplies the address bits for
checking the SECDED hardware.
2-0
292
Reserved
0
Reserved. Writes have no effect. The lower three bits of the CPU address are not used in
the ECC calculation to align the data on a 64-bit boundary. These bits will read back as 0.
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5.7.26 Diagnostic Control Register (FDIAGCTRL)
Set the DIAG_MODE and the DIAG_EN_KEY first before setting up the other registers to block the other
registers from causing a false error. The final write should set the DIAG_TRIG register to activate the test.
Running out of ram will prevent problems with the diagnostic test corrupting the Flash access in some of
the modes.
Figure 5-32. Diagnostic Control Register (FDIAGCTRL) [offset = 6Ch]
31
15
25
24
23
20
19
16
Reserved
DIAG_TRIG
Reserved
DIAG_EN_KEY
R-0
R/WP-0
R-0
R/WP-Ah
14
12
11
10
9
8
7
3
2
0
Rsvd
DIAG_ECC_
SEL
Reserved
DIAG_BUF_
SEL
Reserved
DIAG_MODE
R-0
R/WP-0
R-0
R/WP-0
R-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privilege mode; -n = value after reset
Table 5-38. Diagnostic Control Register (FDIAGCTRL) Field Descriptions
Bit
Field
31-25 Reserved
24
Value
0
DIAG_TRIG
Description
Reserved
Diagnostic Trigger
Diagnostic trigger is the final qualifier for the diagnostic result. After setting all the
other diagnostic register values, the DIAG_TRIG is set to 1. This will activate the
diagnostic logic for one access and then automatically clear the DIAG_TRIG value.
DIAG_EN_KEY and DIAG_MODE must be set at least one cycle before setting
DIAG_TRIG.
This bit always reads as 0.
23-20 Reserved
0
19-16 DIAG_EN_KEY
Reserved
Diagnostic Enable Key
5h
Diagnostic mode is enabled.
All other values Diagnostic mode is disabled.
15
Reserved
0
14-12 DIAG_ECC_SEL
11-10 Reserved
Reserved
Diagnostic SECDED Select
0
Select SECDED0 for diagnostic testing.
1h
Select SECDED1 for diagnostic testing.
2h
Select SECDED2 for diagnostic testing (256 bit wide words only).
3h
Select SECDED3 for diagnostic testing (256 bit wide words only).
4h
Select BUS2 SECDED for diagnostic testing.
5h
Select FEE SECDED for diagnostic testing (Same ECC logic as BUS2 but sets FEE
registers).
6h-7h
Reserved
0
Reserved
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Table 5-38. Diagnostic Control Register (FDIAGCTRL) Field Descriptions (continued)
Bit
Field
9-8
DIAG_BUF_ SEL
Value
Description
Diagnostic Buffer Select
0
The DIAG_BUF_SEL selects the Instruction or Data buffer to read or write when
accessing the FPRIM_ADD_TAG and FDUP_ADD_TAG registers. The address tags
consists of matching primary and duplicate address tag registers. All the primary
address tag registers are memory mapped to a common address (see Section 5.7.10 )
and are selected by DIAG_BUF_SEL. The same occurs for the duplicate address.
(see Section 5.7.11 ). Bit 0 selects a data buffer if high and an instruction buffer if low.
Bits 1 indicate the buffer number.
DIAG_BUF_SEL ENCODING:
7-4
Reserved
2-0
DIAG_MODE
294
0
Buffer
Number
Bits 1
Inst=0
Data=1
Bit0
0
0
Instruction Buffer 0
0
1
Data Buffer 0
1
0
Instruction Buffer 1
1
1
Data Buffer 1
Buffer
Reserved
Diagnostic Mode
0
Diagnostic mode is disabled. This is the same as DIAG_EN_KEY is not equal to 5h.
1h
Diagnostic ECC Data Correction test mode (see Section 5.6.2.1 ).
2h
Diagnostic ECC Syndrome Reporting test mode (see Section 5.6.2.2 ).
3h
ECC Malfunction test mode 1 (same data) (see Section 5.6.2.3 ).
4h
ECC Malfunction test mode 2 (inverted data) (see Section 5.6.2.4 ).
5h
Address Tag Register test mode (see Section 5.6.2.5 ).
6h
Reserved
7h
ECC Data Correction Diagnostic test mode (see Section 5.6.2.6 ).
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5.7.27 Uncorrected Raw Data High Register (FRAW_DATAH)
Figure 5-33. Uncorrected Raw Data High Register (FRAW_DATAH) [offset = 70h]
31
0
RAW_DATA[63:32]
R/WP-u
LEGEND: R/W = Read/Write; WP = Write in Privilege mode; -n = value after reset; -u = unchanged value on internal reset, cleared on
power up
Table 5-39. Uncorrected Raw Data High Register (FRAW_DATAH) Field Descriptions
Bit
31-0
Field
Description
RAW_DATA [63:32]
Uncorrected Raw Data
This register contains the upper 32 bits of the 64-bit raw data used in diagnostic testing of the ECC
logic.
NOTE: Raw Data and Raw ECC registers can be loaded with diagnostic
values only in diagnostic modes 1 through 6 with
DIAG_EN_KEY=0101. These modes must be set for at least one
clock cycle before writing to any FRAW* register.
5.7.28 Uncorrected Raw Data Low Register (FRAW_DATAL)
Figure 5-34. Uncorrected Raw Data Low Register (FRAW_DATAL) [offset = 74h]
31
0
RAW_DATA[31:0]
R/WP-u
LEGEND: R/W = Read/Write; WP = Write in Privilege mode; -n = value after reset -u = unchanged value on internal reset, cleared on power
up
Table 5-40. Uncorrected Raw Data Low Register (FRAW_DATAL) Field Descriptions
Bit
31-0
Field
Description
RAW_DATA [31:0]
Uncorrected Raw Data.
This register contains the lower 32 bits of the 64-bit raw data used in diagnostic testing of the ECC
logic.
NOTE: Raw Data and Raw ECC registers can be loaded with diagnostic
values only in diagnostic modes 1 through 6 with
DIAG_EN_KEY=0101. These modes must be set for at least one
clock cycle before writing to any FRAW* register.
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5.7.29 Uncorrected Raw ECC Register (FRAW_ECC)
Figure 5-35. Uncorrected Raw ECC Register (FRAW_ECC) [offset = 78h]
31
16
Reserved
R-0
15
9
8
7
0
Reserved
PIPE BUF
RAW_ECC[7:0]
R-0
RC-0
R/WD-u
LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privilege mode; C = Clear by writing a 1; -n = value after reset -u = unchanged
value on internal reset, cleared on power up
Table 5-41. Uncorrected Raw ECC Register (FRAW_ECC) Field Descriptions
Bit
Field
31-9
Reserved
8
PIPE BUF
Value
0
Description
Reserved
Error came from pipeline buffer hit
When this bit is a 1, latest error came from a pipeline buffer hit and the FRAW_DATH,
FRAW_DATL, and RAW_ECC fields will not contain information that matches the error address nor
error status bits. This bit is cleared when the RAW_ECC field is updated with new valid information
or by writing a 1 to this bit.
7-0
RAW_ECC[7:0]
Uncorrected Raw ECC
This register contains the ECC data used in diagnostic testing of the ECC logic.
NOTE: Raw Data and Raw ECC registers can loaded with diagnostic
values only in a used diagnostic mode with
DIAG_EN_KEY=0101. This mode must be set for at least one
clock cycle before writing to any FRAW* register.
296
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5.7.30 Parity Override Register (FPAR_OVR)
Figure 5-36. Parity Override Register (FPAR_OVR) [offset = 7Ch]
31
17
15
12
11
16
Reserved
BNK_INV_
PAR
R-0
R/WP-0
9
8
7
0
BUS_PAR_DIS
PAR_OVR_KEY
ADD_INV_
PAR
DAT_INV_PAR
R/WP-5h
R/WP-2h
R/WP-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privilege Mode; -n = value after reset
Table 5-42. Parity Override Register (FPAR_OVR) Field Descriptions
Bit
31-17
16
Field
Value
Reserved
BNK_INV_PAR
0
Description
Reserved
Buffer Invert Parity
When this value is 1 and PAR_OVR_KEY is 101 then the current system parity signal
SYS_ODD_PARITY is inverted when doing bank parity calculations. This will generate parity errors
and cause interrupt signals to be generated. When 0, the SYS_ODD_PARITY value is used. This
bit is only implemented for parity configurations and is reserved for ECC devices.
15-12
BUS_PAR_DIS
Disable Bus Parity
When this value is 1010, the address bus parity error and buffer parity error are disabled and no
checking is done and no events are generated. Any other value will enable the parity checking on
the Address bus and read data bus. The read data parity is never disabled from this module.
11-9
PAR_OVR_KEY
When this value is 101, the selected ADD_INV_PAR and DAT_INV_PAR fields will become active.
Any other value will cause the module to use the global system parity bit in the system register
DEVCR1.
8
ADD_INV_PAR
Address Odd Parity
This bit is active only when PAR_OVR_KEY = 101. When ADD_INV_PAR is 1, the incoming
address bus will invert the system signal SYS_ODD_PARITY for parity calculations. This will cause
parity errors and generate interrupt error signals. When 0, it will use the SYS_ODD_PARITY value.
This bit is set to the SYS_ODD_PAR signal value on reset.
7-0
DAT_INV_PAR
Data Odd Parity
This byte is active only when PAR_OVR_KEY = 101. When a DATA_INV_PAR bit is 1, the output
read data will invert the system signal SYS_ODD_PARITY for parity calculations. This will cause
parity errors and generate interrupt signals. When 0, it will use the SYS_ODD_PARITY value. This
byte can support up to a 64 bit data bus but when the device has a 32 bit bus, bits 7:4 are
reserved.
Bit 0 affects read bus bits 7:0, Bit 1 affects read bus bits 15:8 and so on. Each active bit of this field
is set to the SYS_ODD_PAR signal value on reset.
The DAT_INV_PAR is used in the parity for the pipeline buffer logic and for the read data bus to the
CPU.
When the ECC logic is in the CPU (CONF_TYPE = 5) and SIL3 is active, this field becomes the
ECC corrupting value for SIL3 diagnostic mode 7. (Starting with version 1.0.0.0)
In diagnostic mode 7 the FPAR_OVR should be set to 00005Axxh to allow writes to the
DAT_INV_PAR field. This field should be written before entering diagnostic mode 7.
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5.7.31 Flash Error Detection and Correction Sector Disable Register (FEDACSDIS2)
This register is used to disable the SECDED function for one or two sectors from the EEPROM Emulation
Flash (bank 7). An additional two sectors can have SECDED disabled by the use of the FEDACSDIS
register. see Section 5.7.9.
Figure 5-37. Flash Error Detection and Correction Sector Disable Register (FEDACSDIS2)
[offset = C0h]
31
29
28
27
24
23
21
20
19
16
BankID3_Inverse
Rsvd
SectorID3_inverse
BankID3
Rsvd
SectorID3
R/WP-0
R-0
R/WP-0
R/WP-0
R-0
R/WP-0
15
13
12
11
8
7
5
4
3
0
BankID2_Inverse
Rsvd
SectorID2_inverse
BankID2
Rsvd
SectorID2
R/WP-0
R-0
R/WP-0
R/WP-0
R-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privilege Mode; -n = value after reset
Table 5-43. Flash Error Detection and Correction Sector Disable Register (FEDACSDIS2)
Field Descriptions
Bit
31-29
Field
Value
BankID3_Inverse
The bank ID inverse bits are used with the bank ID bits to select the bank for which a sector
is disabled. The only bank that supports sector disable is bank 7.
0
28
Reserved
Description
If BankID3 = 7h and BankID3_inverse = 0, then if a valid sector is selected by SectorID3
and SectorID3_inverse that sector will have ECC checking disabled.
other
No sector is disabled by disable ID 3.
0
Reads return 0. Writes have no effect.
27-24
SectorID3_inverse
The sector ID inverse bits are used with the sector ID bits to determine which sector is
disabled. If the sector ID bits are not pointing to a valid sector (0-3) or the sector ID inverse
bits are not an inverse of the sector ID bits, then no sector is disabled by disable ID 3.
23-21
BankID3
The bank ID bits are used with the bank ID inverse bits to select the bank for which a sector
is disabled. The only bank that supports sector disable is bank 7.
7h
If BankID3 = 7h and BankID3_inverse = 0, then if a valid sector is selected by SectorID3
and SectorID3_inverse that sector will have ECC checking disabled.
other
No sector is disabled by disable ID 3.
0
Reads return 0. Writes have no effect.
20
Reserved
19-16
SectorID3
The sector ID bits are used with the sector ID inverse bits to determine which sector is
disabled. If the sector ID bits are not pointing to a valid sector (0-3) or the sector ID inverse
bits are not an inverse of the sector ID bits, then no sector is disabled by disable ID 3.
15-13
BankID2_Inverse
The bank ID inverse bits are used with the bank ID bits to select the bank for which a sector
is disabled. The only bank that supports sector disable is bank 7.
0
12
Reserved
If BankID2 = 7h and BankID2_inverse = 0, then if a valid sector is selected by SectorID2
and SectorID2_inverse that sector will have ECC checking disabled.
other
No sector is disabled by disable ID 2.
0
Reads return 0. Writes have no effect.
11-8
SectorID2_inverse
The sector ID inverse bits are used with the sector ID bits to determine which sector is
disabled. If the sector ID bits are not pointing to a valid sector (0-3) or the sector ID inverse
bits are not an inverse of the sector ID bits, then no sector is disabled by disable ID 2.
7-5
BankID2
The bank ID bits are used with the bank ID inverse bits to select the bank for which a sector
is disabled. The only bank that supports sector disable is bank 7.
7h
If BankID2 = 7h and BankID2_inverse = 0, then if a valid sector is selected by SectorID2
and SectorID2_inverse that sector will have ECC checking disabled.
other
No sector is disabled by disable ID 2.
4
Reserved
0
Reads return 0. Writes have no effect.
3-0
SectorID2
0-Fh
298
The sector ID bits are used with the sector ID inverse bits to determine which sector is
disabled. If the sector ID bits are not pointing to a valid sector (0-3) or the sector ID inverse
bits are not an inverse of the sector ID bits, then no sector is disabled by disable ID 2.
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5.7.32 FSM Register Write Enable (FSM_WR_ENA)
Figure 5-38. FSM Register Write Enable (FSM_WR_ENA) [offset = 288h]
31
16
Reserved
R-0
15
3
2
0
Reserved
WR_ENA
R-0
R/WP-2h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privilege Mode; -n = value after reset
Table 5-44. FSM Register Write Enable (FSM_WR_ENA) Field Descriptions
Bit
Field
31-16
Reserved
2-0
WR_ENA
Value
Description
0
Reads return 0. Writes have no effect.
Flash State Machine Write Enable
5h
This register must contain 101 in order to write to any other register in the range FFF8 7200h
to FFF8 72FFh. This is the first register to be written when setting up the FSM.
All other values
For all other values, the FSM registers cannot be written.
5.7.33 FSM Sector Register (FSM_SECTOR)
This is a banked register. A separate register is implemented for each bank, but they all occupy the same
address. The correct bank must be selected in the FMAC register before reading or writing this register.
See Section 5.7.20.
Figure 5-39. FSM Sector Register (FSM_SECTOR) [offset = 2A4h]
31
16
SECT_ERASED[16:0]
R/WP-0
15
0
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privilege Mode; -n = value after reset
Table 5-45. FSM Sector Register (FSM_SECTOR) Field Descriptions
Bit
31-16
Field
Value
SECT_ERASED[16:0]
Description
Sectors Erased
There is one bit for each sector. Bit 16 corresponds to sector 0, bit 17 corresponds to sector 1,
and so on. After bank erase, the bit corresponding to each sector which is erased will be
changed from 0 to 1.
15-0
Reserved
0
During bank erase, each sector will be erased.
1
Each sector will not be erased.
0
These bits are used by the state machine during bank erase. Do not write to these bits.
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5.7.34 EEPROM Emulation Configuration Register (EEPROM_CONFIG)
Figure 5-40. EEPROM Emulation Configuration Register (EEPROM_CONFIG) [offset = 2B8h]
31
20
15
16
EWAIT
R-0
R/WP-1h
9
Reserved
19
Reserved
8
7
AUTOSUSP_EN
R-0
0
AUTOSTART_GRACE
R/WP-0
R/WP-2h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privilege Mode; -n = value after reset
Table 5-46. EPROM Emulation Configuration Register (EEPROM_CONFIG) Field Descriptions
Bit
Field
31-20
Reserved
19-16
EWAIT
Value
0
Description
Reads return 0. Writes have no effect.
EEPROM Wait State Counter
This register will replace the RWAIT count in the EEPROM register. The same formulas that
apply to RWAIT will apply to EWAIT in the EEPROM bank.
15-9
8
Reserved
0
AUTOSUSP_EN
Reads return 0. Writes have no effect.
Auto Suspend Enable
0
Auto Suspend is disabled.
1
Auto Suspend is enabled.
The auto-suspend will begin when the CPU or Bus 2 attempts to access a bank with an
active and suspendable FSM operation. If this happens the FSM will automatically be
issued a suspend command and exit from the FSM. It will then do the access. After the
access, the FMC will wait for a time determined by the Autostart_grace field before issuing
the FSM resume command.
7-0
300
AUTOSTART_GRACE
Auto-suspend Startup Grace Period
1
The value in this register determines how many cycles the FMC will wait after the last CPU
or Bus 2 access before issuing the FSM resume command.
0
The FMC will wait 16 HCLK periods for each count in the AUTOSTART_GRACE field. A
value of 2 will wait for 32 periods after the last access. Each access will reset the counter to
the AUTOSTART_GRACE value × 16.
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5.7.35 EEPROM Emulation Error Detection and Correction Control Register 1 (EE_CTRL1)
This register controls ECC event detection for the EEPROM Emulation Flash bank (bank 7). For the
equivalent register that controls ECC event detection for the main Flash banks, see Section 5.7.2.
Figure 5-41. EEPROM Emulation Error Detection and Correction Control Register 1 (EE_CTRL1)
[offset = 308h]
31
24
Reserved
R-05h
23
20
19
16
Reserved
EE_EDACMODE
R-0
R/WP-Ah
15
7
10
9
8
Reserved
EE_EOFEN
EE_EZFEN
EE_EPEN
R-0
R/WP-0
R/WP-0
R/WP-0
5
4
Reserved
6
EE_ALL1_OK
EE_ALL0_OK
3
EE_EDACEN
0
R-0
R/WP-0
R/WP-0
R/WP-5h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privilege Mode; -n = value after reset
Table 5-47. EEPROM Emulation Error Detection and Correction Control Register 1 (EE_CTRL1)
Field Descriptions
Field
Value
Description
31-20
Bit
Reserved
050h
Reads return 050h. Writes have no effect.
19-16
EE_
EDACMODE
Error Correction Mode for the EEPROM Emulation Flash bank (bank 7). For the main
Flash banks, see Section 5.7.2.
5h
Detection only mode.
Note: In detection only mode single-bit errors will not be corrected, but will be treated as
uncorrectable errors. The single-bit error flags and profiling mode are disabled. Detection
only mode has the advantage that a triple bit error will be detected and not mistaken for a
single-bit error and mis-corrected.
All Other Values
Single-bit errors are corrected and multi-bit or address errors are detected.
Note: It is recommended to leave the EE_EDACMODE field as 1010 to guard against
soft errors from flipping EE_EDACMODE to a detection only.
15-11
10
9
8
Reserved
0
EE_EOFEN
Reads return 0. Writes have no effect.
EEPROM Emulation Event on a correctable One's Fail Enable bit
0
No ESM event will be generated on a single-bit error when a 1 reads as a 0 and is
corrected.
1
An ESM group 1 channel 35 event will be generated on a single-bit error when a 1 reads
as a 0 and is corrected.
EE_EZFEN
EEPROM Emulation Event on a correctable Zero's Fail Enable bit
0
No ESM event will be generated on a single-bit error when a 0 reads as a 1 and is
corrected.
1
An ESM group 1 channel 35 event will be generated on a single-bit error when a 0 reads
as a 1 and is corrected.
EE_EPEN
EEPROM Emulation Error Profiling Enable
0
Error profiling is disabled.
1
Error profiling is enabled.
An ESM group 1 channel 35 event will be generated when number of correctable bit
errors detected and corrected has reached the threshold value defined in the EE_CTRL2
register.
7-6
Reserved
0
Reads return 0. Writes have no effect.
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Table 5-47. EEPROM Emulation Error Detection and Correction Control Register 1 (EE_CTRL1)
Field Descriptions (continued)
Bit
5
Field
Value
EE_ALL1_OK
Description
EEPROM Emulation All One Condition Valid
0
One condition valid is disabled.
Reading of an erased location (64 data bits and the corresponding 8 ECC bits are all 1s)
will generate ECC errors. The error counter for profiling will increment if all 1s are
detected.
1
One condition valid is enabled.
Reading of an erased location (64 data bits and the corresponding 8 ECC bits are all 1s)
will NOT generate ECC errors. The error counter for profiling will NOT increment if all 1s
are detected.
4
EE_ALL0_OK
EEPROM Emulation All Zero Condition Valid
0
Zero condition valid is disabled.
Reading of all 0s (64 data bits and the corresponding 8 ECC bits are all 0s) will generate
ECC errors. The error counter for profiling will increment if all 0s are detected.
1
Zero condition valid is enabled.
Reading of all 0s (64 data bits and the corresponding 8 ECC bits are all 0s) will NOT
generate ECC errors. The error counter for profiling will NOT increment if all 0s are
detected.
3-0
EE_EDACEN
EEPROM Emulation Error Detection and Correction Enable
5h
Error Detection and Correction is disabled.
All Other Values
Error Detection and Correction is enabled.
Note: It is recommended to leave the EE_EDACEN field as 1010 to guard against soft
errors from flipping the EE_EDACEN to a disabled state.
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5.7.36 EEPROM Emulation Error Correction and Correction Control Register 2 (EE_CTRL2)
Figure 5-42. EEPROM Emulation Error Correction and Correction Control Register 2 (EE_CTRL2)
[offset = 30Ch]
31
16
Reserved
R-0
15
0
EE_SEC_THRESHOLD
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privilege Mode; -n = value after reset
Table 5-48. EEPROM Emulation Error Correction Control Register 2 (EE_CTRL2) Field Descriptions
Bit
Field
Value
31-16
Reserved
15-0
EE_SEC_THRESHOLD
0
Description
Reads return 0. Writes have no effect.
0-FFFFh
EEPROM Emulation Single Error Correction Threshold
This register contains the threshold value for the SEC (single error correction)
occurrences before a single interrupt request is generated. A threshold of zero
disables the threshold so that it never triggers the profile interrupt.
5.7.37 EEPROM Emulation Correctable Error Count Register (EE_COR_ERR_CNT)
Figure 5-43. EEPROM Emulation Error Correctable Error Count Register (EE_COR_ERR_CNT)
[offset = 310h]
31
16
Reserved
R-0
15
0
EE_ERRCNT
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privilege Mode; -n = value after reset
Table 5-49. EEPROM Emulation Correctable Error Count Register (EE_COR_ERR_CNT)
Field Descriptions
Bit
Field
31-16
Reserved
15-0
EE_ERRCNT
Value
0
Description
Reads return 0. Writes have no effect.
0-FFFFh
Single Error Correction Count
This register contains the number of SEC (single error correction) occurrences.
Writing any value to this register resets the count value to 0. The counter resets to 0
when it increments to be equal to the single error correction threshold. This register
only increments when profiling mode is enabled. This register is not affected by the
EE_ZERO_EN or EE_ONE_EN error control bits in the EE_CTRL1 register.
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5.7.38 EEPROM Emulation Correctable Error Address Register (EE_COR_ERR_ADD)
During emulation mode, this address is frozen even when read. By setting the SUSP_IGNR bit,
(seeTable 5-14) this register can be unfrozen in emulation mode.
This register is not changed with the reset signal and contains unknown data at power-up.
Figure 5-44. EEPROM Emulation Correctable Error Address Register (EE_COR_ERR_ADD)
[offset = 314h]
31
16
COR_ERR_ADD
R-u
15
3
2
0
COR_ERR_ADD
B_OFF
R-u
R-u
LEGEND: R = Read only; -n = value after reset; -u = unchanged value on internal reset, cleared on power up
Table 5-50. EEPROM Emulation Correctable Error Address Register (EE_COR_ERR_ADD)
Field Descriptions
Bit
31-3
Field
COR_ERR_ADD
Value
Description
0-1FFF FFFFh
Correctable Error Address
COR_ERR_ADD records the CPU logical address of which a correctable error is
detected by the ECC logic. This error address is frozen from begin updated until it is
read by the CPU. Additional error are blocked until this register is read.
2-0
B_OFF
0-7h
Byte offset
Since ECC is checked on 64 bit data, when checking main memory or OTP, the
address captured is aligned to a 64-bit boundary with address bits[2:0] equal to 0.
When reading from the ECC bytes, these bits will indicate the failing address of the
ECC location associated with the failure. When reading an ECC byte, the ECC is
checked against the 64 data bits they protect.
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5.7.39 EEPROM Emulation Correctable Error Position Register (EE_COR_ERR_POS)
The bit position is captured during errors when either EE_EOFEN or EE_EZFEN enable bit is set. During
error profiling mode when only EE_EPEN is set, the bit position is not captured if a correctable error is
detected. This register is frozen while either the EE_ERR_ZERO_FLG or the EE_ERR_ONE_FLG bit is
set in the EE_EDACSTATUS register.
During emulation mode, this address is frozen even when read. By setting the SUSP_IGNR bit, this
register can be unfrozen in emulation mode.
This register is not changed with the reset signal and contains unknown data at power-up.
Figure 5-45. EEPROM Emulation Correctable Error Position Register (EE_COR_ERR_POS)
[offset = 318h]
31
16
Reserved
R-0
15
8
7
0
Reserved
TYPE
EE_ERR_POS
R-0
R-u
R-u
LEGEND: R = Read only; -n = value after reset; -u = unchanged value on internal reset, cleared on power up
Table 5-51. EEPROM Emulation Correctable Error Position Register (EE_COR_ERR_POS)
Field Descriptions
Bit
31-9
8
7-0
Field
Reserved
Value
0
TYPE
EE_ERR_POS
Description
Reads return 0. Writes have no effect.
Error Type
0
The error was one of the 64 data bits.
1
The error was one of the 8 check bits.
0-FFh
The bit address of the single-bit error.
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5.7.40 EEPROM Emulation Error Status Register (EE_STATUS)
During emulation mode, this address is frozen even when read. By setting the SUSP_IGNR bit in
FEDACCTRL1 register, (see Table 5-14) this register can be unfrozen in emulation mode.
This register is not changed with the reset signal and contains unknown data at power-up.
All these error status bits can be deactivated by writing a 1 to the bit. Writing a 0 has no effect.
Bits 0 to 3 show correctable errors while bits 4 to 12 show uncorrectable errors. When the uncorrectable
errors are triggered, the current address is stored in the EE_UNC_ERR_ADD register.
These error bits are not set while the FMC is in the suspend mode but they can be cleared in suspend by
writing 1s to the bits. By setting the SUSP_IGNR bit to 1, these error bits can be set in suspend mode
(see Table 5-14).
Figure 5-46. EEPROM Emulation Error Status Register (EE_STATUS) [offset = 31Ch]
31
24
Reserved
R-0
23
16
Reserved
R-0
15
13
12
11
9
8
Reserved
EE_D_UNC_
ERR
Reserved
EE_UNC_
ERR
R-0
RCP-u
R-0
RCP-u
7
6
5
4
3
2
1
0
Reserved
EE_CMG
Reserved
EE_CME
EE_D_COR_
ERR
EE_ERR_
ONE_FLG
EE_ERR_
ZERO_FLG
EE_ERR_
PRF_FLG
R-0
R-0
R-0
R-0
RCP-u
RCP-u
RCP-u
RCP-u
LEGEND: R = Read only; RCP = Read and Clear in Privilege Mode; -n = value after reset; -u = unchanged value on internal reset, cleared
on power up
Table 5-52. EEPROM Emulation Error Status Register (EE_STATUS) Field Descriptions
Bit
31-13
12
11-9
8
306
Field
Reserved
Value
0
EE_D_UNC_ERR
Reserved
Reserved
6
EE_CMG
5
Reserved
4
EE_CME
Reads return 0. Writes have no effect.
Diagnostic Mode Uncorrectable Error Status Flag
0
No uncorrectable error was detected in diagnostic mode 1.
1
An uncorrectable error was detected in diagnostic mode 1. This means two or more bits in
the data or ECC field have been found in error, or one or more bits in the address have
been found in error.
0
Reads return 0. Writes have no effect.
EE_UNC_ERR
7
Description
EEPROM Emulation Uncorrectable Error Flag
0
No uncorrectable errors were detected in bank 7.
1
An uncorrectable error was detected in bank 7.
0
Reads return 0. Writes have no effect.
EEPROM Emulation Compare Malfunction Good
0
Compare malfunction was detected on the Bus2 SECDED logic.
1
Compare malfunction was not detected on the Bus2 SECDED logic.
0
Reads return 0. Writes have no effect.
EEPROM Emulation Compare Malfunction Error
0
Compare malfunction was not detected on the Bus2 SECDED logic.
1
Compare malfunction was detected on the Bus2 SECDED logic.
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Table 5-52. EEPROM Emulation Error Status Register (EE_STATUS) Field Descriptions (continued)
Bit
3
2
1
0
Field
Value
EE_D_COR_ERR
Description
Diagnostic Correctable Error Flag
0
No correctable error was detected.
1
A correctable error was detected.
EE_ERR_ONE_FLG
Error on One Fail Error Flag
0
No correctable error was detected.
1
A correctable error was detected.
EE_ERR_ZERO_FLG
Error on Zero Fail Error Flag
0
No correctable error was detected.
1
A correctable error was detected.
EE_ERR_PRF_FLG
Error Profiling Error Flag
0
No correctable error was detected.
1
A correctable error was detected.
5.7.41 EEPROM Emulation Uncorrectable Error Address Register (EE_UNC_ERR_ADD)
During emulation mode, this address is frozen even when read. By setting the SUSP_IGNR bit, (see
Table 5-14) this register can be unfrozen in emulation mode.
This register is not changed with the reset signal and contains unknown data at power-up.
Figure 5-47. EEPROM Emulation Uncorrectable Error Address Register (EE_UNC_ERR_ADD)
[offset = 320h]
31
16
UNC_ERR_ADD
R-u
15
3
2
0
UNC_ERR_ADD
B_OFF
R-u
R-u
LEGEND: R = Read only; -n = value after reset; -u = unchanged value on internal reset, cleared on power up
Table 5-53. EEPROM Emulation Uncorrectable Error Address Register (EE_UNC_ERR_ADD)
Field Descriptions
Bit
31-3
Field
UNC_ERR_ADD
Value
Description
0-1FFF FFFFh
Uncorrectable Error Address
UNC_ERR_ADD records the CPU logical address of which an uncorrectable error is
detected by the ECC logic. This error address is frozen from begin updated until it is
read by the CPU. Additional error are blocked until this register is read.
2-0
B_OFF
0-7h
Byte offset
Since ECC is checked on 64-bit data, when checking main memory or OTP, the
address captured is aligned to a 64-bit boundary with address bits[2:0] equal to
0.When reading from the ECC bytes, these bits will indicate the failing address of the
ECC location associated with the failure. When reading an ECC byte, the ECC is
checked against the 64 data bits they protect.
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5.7.42 Flash Bank Configuration Register (FCFG_BANK)
Figure 5-48. Flash Bank Configuration Register (FCFG_BANK) [offset = 400h]
31
20
19
16
EE_BANK_WIDTH
Reserved
R-90h
R-1
15
4
3
0
MAIN_BANK_WIDTH
Reserved
R-90h
R-2h
LEGEND: R = Read only; -n = value after reset
Table 5-54. Flash Bank Configuration Register (FCFG_BANK) Field Descriptions
Bit
31-20
Field
EE_BANK_WIDTH
Value
90h
Description
Bank 7 width (144-bits wide)
This read-only value indicates the maximum number of bits that can be programmed in the
bank in one operation. The 144 bits includes 128 data bits and 16 ECC bits.
19-16
Reserved
15-4
MAIN_BANK_WIDTH
1
90h
Writes have no effect.
Width of main Flash banks (144-bits wide)
This read-only value indicates the maximum number of bits that can be programmed in the
bank in one operation. The 144 bits includes 128 data bits and 16 ECC bits.
3-0
308
Reserved
2h
Writes have no effect.
F021 Flash Module Controller (FMC)
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Chapter 6
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Tightly-Coupled RAM (TCRAM) Module
This chapter describes the tightly-coupled RAM (TCRAM) module.
Topic
...........................................................................................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
Overview .........................................................................................................
RAM Memory Map ............................................................................................
Safety Features ................................................................................................
TCRAM Auto-Initialization ..................................................................................
Trace Module Support .......................................................................................
Emulation / Debug Mode Behavior ......................................................................
Control and Status Registers .............................................................................
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310
311
312
313
314
314
314
309
Overview
6.1
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Overview
The Hercules family of microcontrollers are based on the ARM Cortex-R4F processor. This CPU has two
tightly-coupled memory interfaces – ATCM and BTCM, which are used to interface to the program and
data memories, respectively. The Hercules MCUs use the ATCM interface for the main flash memory and
the BTCM interface for the CPU data RAM.
6.1.1 B0TCM and B1TCM Connection Diagram
The BTCM interface is further divided into two parts – B0TCM and B1TCM, which are both used to
interface to actual RAM banks as shown in Figure 6-1.
Figure 6-1. TCRAM Module Connections
36 Bit
36 Bit
Upper 32 bits data
and 4 ECC bits
Cortex-R4F
EVEN Address
TCM BUS
B0
TCM
36 bit
RAM
Wide
RAM
TCRAMW 1
36 Bit
64 Bit data
and 8 ECC bits
Lower 32 bits data
and 4 ECC bits
36 Bit
36 bit
RAM
Wide
RAM
36 Bit
B1
TCM
Upper 32 bits data
and 4 ECC bits
ODD Address
TCM BUS
36 Bit
36 bit
RAM
Wide
RAM
TCR AMW 2
36 Bit
64 Bit data
and 8 ECC bits
Lower 32 bits data
and 4 ECC bits
36 Bit
36 bit
RAM
Wide
RAM
6.1.2 Main Features
The main features of the tightly-coupled RAM interface module are:
• Controls read/write accesses to the data RAM
• Decodes addresses within the memory region allocated for the RAM
• Supports read and write accesses in 64-bit, 32-bit, 16-bit or 8-bit access sizes
– Does not support bit-wise operations
• Safety Features:
– Support for Cortex-R4F CPU's Built-In Single-Error-Correction Double-Error-Detection (SECDED)
Logic
• Uses the CPU's Event bus and maintains the SECDED status in memory-mapped registers
• Captures the number of occurrences of single-bit or multi-bit errors as well as the RAM address
that has the fault
• Generates signals for indicating single-bit and multi-bit errors to the Error Signaling Module
(ESM)
– Support for Cortex-R4F CPU's Parity Protection Logic for BTCM Address Bus and Control Signals
• Uses the CPU's TCM Address Parity Scheme and indicates an address bus parity error to the
ESM
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•
•
6.2
– Redundant Address Decode Scheme
• Checks the decoding of CPU address lines and generation of correct memory selects for the
RAM banks
• Also supports checking of the redundant address decode comparators themselves
Supports auto-initialization of the CPU data RAM banks
Supports the RAM Trace Port (RTP) Interface
– Traces out all RAM read and write accesses to the RTP module
RAM Memory Map
The ARM Cortex-R4F CPU allows up to 8MB to be accessed through the BTCM interface. The Hercules
family of microcontrollers support up to 256KB RAM on the BTCM interface. Check the specific part's
datasheet to identify the actual amount of TCRAM supported on the part. This RAM is protected by ECC
allowing the CPU to correct any single-bit errors and detect double-bit errors within a 64-bit value. The
error correction codes (ECC) are stored in the RAM memory space as well. The memory map for the
TCRAM and the corresponding ECC space is shown in Figure 6-2. Any access to an unimplemented
TCRAM location results in an error response from the TCRAM module.
Figure 6-2. RAM Memory Map
8 MB
Illegal address
4MB + 256KB
Implemented ECC space
4MB
Illegal address
256KB
Implemented data space
0x0
Each RAM data word is 64 bits wide. These 64 bits are divided into two 32 bits per RAM bank as shown in
Figure 6-1. The 8 bits of ECC are also divided into 4 bits per RAM bank.
For every 64-bit read from the RAM, an 8-bit ECC is also read by the CPU on its ECC bus. Similarly, for
every 64-bit write to the RAM, the CPU also writes an 8-bit ECC using the same ECC bus.
NOTE: Read-Modify-Write Requirement for Writes to RAM: The TCRAM interface module
supports 64-bit, 32-bit, 16-bit or 8-bit writes to the RAM. However the ECC is calculated by
the CPU for 64-bit values only. For any write access smaller than 64 bits, it is necessary to
force the CPU to perform a 64-bit read-modify-write operation in order to ensure that the
correct ECC is also written. This can be done by setting the bit 1: BTCMRMW of c15, the
Secondary Auxiliary Control Register of the CPU. This bit is already set by default.
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The ECC memory can also be directly accessed via memory-mapped offset addresses starting from 4MB,
as shown in Figure 6-2. A read from the ECC space results in the 8-bit ECC value appearing on each byte
of the 64-bit CPU data. The ECC memory can only be written to as a 64-bit access. The write to the ECC
space must also first be enabled via the RAM Control Register (RAMCTRL).
Accesses to the ECC space are not traced out to the RAM Trace Port (RTP).
NOTE: No ECC Error Generated for Accesses to ECC Memory: A read from the ECC space
send the ECC value on both the 64-bit TCM read data bus as well as the 8-bit ECC bus.
This could result in the detection of a multi-bit error by the SECDED logic inside the CPU.
The TCRAM interface module ignores the ECC error indicated by the CPU for the access to
the ECC space.
6.3
Safety Features
The TCRAM interface module incorporates some features that are designed specifically with safety
considerations. These are described in the following sections.
6.3.1 Support for Cortex-R4F CPU's Single-Error-Correction Double-Error-Detection (SECDED)
The TCRAM interface module monitors the CPU's event bus. The CPU's event bus signals single-bit or
multi-bit errors for B0TCM as well as B1TCM separately. These signals are monitored by the TCRAM
modules for each of these interfaces.
TCRAM Interface Module Features dedicated for SECDED Support:
• Dedicated single-bit error counter
– This counter is stored in a memory-mapped register called RAMOCCUR
– RAMOCCUR is used to count the single-bit errors corrected by the CPU's SECDED logic
– The TCRAM interface module allows the application to generate an interrupt via the RAMINTCTRL
register when the number of single-bit errors corrected by the CPU exceeds a programmable
threshold, RAMTHRESHOLD
• RAM Error Status Register
– The errors detected by the TCRAM interface module as well as those indicated by the CPU are
flagged in the RAMERRSTATUS register
– There are separate bits to indicate single-bit error, double-bit error, address decode failure, address
compare logic failure, read-address parity failure, and write-address parity failure
• ECC Error Address Capture
– Separate registers to hold the address on which a single-bit error is detected (RAMSERRADDR) or
a double-bit error is detected (RAMUERRADDR)
– The RAMSERRADDR register is only updated when the RAMTHRESHOLD value is set to 1
– Both the RAMSERRADDR and RAMUERRADDR capture the 64-bit-aligned address for the access
to the TCRAM as an offset from the base address of the TCRAM (0x08000000 by default)
NOTE: Cortex-R4F CPU Event Bus Signaling Not Enabled By Default: Upon power-up and after
a CPU reset, the event signaling mechanism inside the Cortex-R4F CPU is disabled. This
feature must be enabled by setting the Export (X-bit) of the Performance Monitoring and
Control Register (PMNC) in the CPU. The TCRAM interface module can only capture the
single-bit or double-bit ECC error occurrences once the CPU's event signaling mechanism is
enabled.
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6.3.2 Support for Cortex-R4F CPU's Address and Control Bus Parity Checking
The Cortex-R4F CPU calculates a single parity-bit for the TCRAM address and control signals. The
TCRAM interface module also computes this parity bit based on the CPU's address bus and control
signals. The computed parity bit is compared against the parity bit received from the CPU. A mismatch is
signaled as an Address Parity Failure to the Error Signaling Module (ESM) group2 channel 10 or 12.
There is a separate address parity failure error channel for B0TCM and B1TCM.
The 64-bit TCRAM address which fails the parity check is captured in the RAMPERRADDR register as an
offset from the base address of the TCRAM (0x08000000 by default). The TCRAM interface module also
indicates the type of access, read or write, that failed the parity check. This is indicated by the
RADDR_PAR_FAIL or the WADDR_PAR_FAIL status flags in the RAMERRSTATUS register.
The RAMERRSTATUS and RAMPERRADDR registers must be cleared by the application in order for the
TCRAM interface module to continue capturing subsequent errors and error addresses.
The parity scheme used for the described parity checking mechanism is defined by the global system
parity selection. This can be configured using the DEVPARSEL field of the DEVCR1 control register in the
system module. This device-wide parity scheme can be overridden inside the TCRAM interface module by
configuring the Address Parity Override field in the RAMCTRL register.
NOTE: No Change Of Parity Scheme On-The-Fly: The TCRAM interface module does not support
on-the-fly change to the parity scheme being used for checking the CPU address bus and
control bus. The application must ensure that the parity polarity (odd or even) is not changed
while there is an ongoing access to the TCRAM.
6.3.3 Redundant Address Decode
The TCRAM interface module generates the memory selects for each of the TCRAM banks as well as the
ECC memory based on the CPU address. The logic to generate these memory selects is duplicated and
the outputs compared to detect any address decode errors. A mismatch is indciated as an Address Error
to the Error Signaling Module (ESM), one signal for B0TCM and one for B1TCM. The TCRAM or ECC
address that caused the fault is captured in the RAMUERRADDR register. This 64-bit-aligned address is
stored as an offset from the base of the TCRAM or ECC memory.
As described earlier, each individual physical RAM bank is 36 bits wide. Each RAM bank contributes 32
bits of data and 4 bits of ECC when the bus master performs a 64-bit read from the TCRAM. Each
TCRAM bank receives a memory select and the address from the TCRAM interface module. Any
difference between the address and the memory selects results in wrong data and ECC pair being sent to
the CPU. The CPU's SECDED block will detect this data error.
The TCRAM interface module also supports a mechanism to test the operation of the redundant address
decode logic and the compare logic. This testing is supported by providing a test stimulus, and can be
triggered by the application by configuring the RAMTEST register. The address of any error identified
during testing of the redundant address decode and compare logic is not captured in the
RAMUERRADDR register.
NOTE: Address decode checking when in compare logic test mode: When the address decode
and compare logic test mode is enabled, the redundant address decode and compare logic
is not available for checking the proper generation of the memory selects for the TCRAM and
ECC memory.
6.4
TCRAM Auto-Initialization
The RAM memory can be initialized by using the dedicated auto-initialization hardware. The TCRAM
Module initializes the entire memory when the auto-initialization is enabled by the INIT_DOMAIN register
upon receiving a MMI_INIT pulse from the system module. All enabled RAM data memory locations are
initialized to zeros and the ECC memory is initialized to the correct ECC value for zeros, that is, 0Ch.
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Trace Module Support
The TCRAM Module traces out the following signals to the RAM Trace Port (RTP) module, thereby
providing RAM dataport trace capability.
• 18-bit address line
• 64-bit data bus
• Byte strobe information
• Current access master identification number
• Access type: Opcode or data fetch
• Read or Write access
No data is traced for an access to ECC memory.
6.6
Emulation / Debug Mode Behavior
The following describes the behavior of the TCRAM Module when in debug mode:
• The RAMOCCUR register continues to count the single-bit error corrections performed by the CortexR4F CPU's SECDED logic.
• No single-bit error interrupt is generated nor is any single-bit error address captured even when the
RAMOCCUR counter reaches the programmed single-bit error correction threshold.
• No uncorrectable error interrupt is generated nor is any double-bit error address captured.
• No address parity error interrupt is generated nor is any parity error address captured.
• The RAMUERRADDR register is not cleared by a read in debug mode.
– That is, if a double-bit error address is captured and is not read by the CPU before entering debug
mode, then it remains frozen during debug mode even if it is read.
• The RAMPERRADDR register is not cleared by a read in debug mode.
6.7
Control and Status Registers
The TCRAM Module registers are accessed through the system module registers' space in the CortexR4F CPU's memory map. All registers are 32-bit wide and are located on a 32-bit boundary. Reads and
writes to registers are supported in 8-, 16-, and 32-bit accesses. The base address for the control registers
is FFFF F800h for even RAM ECC and FFFF F900h for odd RAM ECC.
Table 6-1. TCRAM Module Control and Status Registers
314
Offset
Acronym
Register Description
00h
RAMCTRL
TCRAM Module Control Register
Section 6.7.1
Section
04h
RAMTHRESHOLD
TCRAM Module Single-Bit Error Correction Threshold Register
Section 6.7.2
08h
RAMOCCUR
TCRAM Module Single-Bit Error Occurrences Control Register
Section 6.7.3
0Ch
RAMINTCTRL
TCRAM Module Interrupt Control Register
Section 6.7.4
10h
RAMERRSTATUS
TCRAM Module Error Status Register
Section 6.7.5
14h
RAMSERRADDR
TCRAM Module Single-Bit Error Address Register
Section 6.7.6
1Ch
RAMUERRADDR
TCRAM Module Uncorrectable Error Address Register
Section 6.7.7
30h
RAMTEST
TCRAM Module Test Mode Control Register
Section 6.7.8
38h
RAMADDRDECVECT
TCRAM Module Test Mode Vector Register
Section 6.7.9
3Ch
RAMPERADDR
TCRAM Module Parity Error Address Register
Section 6.7.10
40h
INIT_DOMAIN
Auto-Memory Initialization Enable Register
Section 6.7.11
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6.7.1 TCRAM Module Control Register (RAMCTRL)
The RAMCTRL register, shown in Figure 6-3 and described in Table 6-2, controls the safety features
supported by the TCRAM Module.
Figure 6-3. TCRAM Module Control Register (RAMCTRL) [offset = 00h]
31
30
Reserved
EMU_TRACE_DIS
29
Reserved
28
ADDR_PARITY_OVERRIDE
R-0
R/WP-0
R-0
R/WP-0
23
20
27
24
19
16
Reserved
ADDR_PARITY_DISABLE
R-0
R/WP-5h
15
9
7
8
Reserved
ECC_WR_EN
R-0
R/WP-0
4
3
0
Reserved
ECC_DETECT_EN
R-0
R/WP-Ah
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 6-2. TCRAM Module Control Register (RAMCTRL) Field Descriptions
Bit
Field
31
Reserved
30
EMU_TRACE_DIS
29-28 Reserved
Value
0
Read returns 0. Writes have no effect.
Emulation Mode Trace Disable. This bit, when set, disables the tracing of read data to
RAM Trace Port (RTP) module during emulation mode access.
0
Data is allowed to be traced out to the trace modules during emulation mode accesses.
1
Data is blocked from being traced out to the trace modules during emulation mode
accesses.
0
Read returns 0. Writes have no effect.
27-24 ADDR_PARITY_OVERRIDE
23-20 Reserved
Description
Address Parity Override. This field, when set to Dh, will invert the parity scheme
selected by the device global parity selection. The address parity checker would then
work on the inverted parity scheme. By default, the parity scheme is the same as the
global device parity scheme.
Dh
Parity scheme is opposite to the device global parity scheme.
All Others
Parity scheme is the same as the device global parity scheme.
0
Read returns 0. Writes have no effect.
19-16 ADDR_PARITY_DISABLE
Address Parity Detect Disable. This field, when set to Ah, disables the parity checking
for the address bus. The parity checking is enabled when this field is set to any other
value.
Note: The application must ensure that the WADDR_PAR_FAIL and
RADDR_PAR_FAIL bits in RAMERRSTATUS register are cleared before enabling
address parity checking.
15-9
8
Reserved
Ah
Address parity checking is disabled
All Others
Address parity checking is enabled
0
ECC_WR_EN
Read returns 0. Writes have no effect.
ECC Memory Write Enable. This bit is provided to prevent accidental writes to the ECC
memory. A write access to the ECC memory is allowed only when the ECC_WR_EN
bit is set to 1. If this bit is cleared, then any writes to ECC memory are ignored.
Note: Reads are allowed from the ECC memory regardless of the state of the
ECC_WR_EN bit.
7-4
Reserved
0
ECC memory writes are disabled.
1
ECC memory writes are enabled.
0
Read returns 0. Writes have no effect.
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Table 6-2. TCRAM Module Control Register (RAMCTRL) Field Descriptions (continued)
Bit
Field
3-0
ECC_DETECT_EN
Value
Description
ECC Detect Enable. This is a 4-bit key to enable the ECC detection feature in the
TCRAM Module. If this field is set to any value other than 5h, then the TCRAM Module
starts monitoring the TCM event bus and generates the corresponding error status
flags. The error status updates are done only when the ECC_DETECT_EN field is not
5h. The ECC detection is enabled by default, as the ECC_DETECT_EN field default
value is Ah.
5h
ECC detection is disabled.
All Others
ECC detection is enabled.
6.7.2 TCRAM Module Single-Bit Error Correction Threshold Register (RAMTHRESHOLD)
The RAMTHRESHOLD register, shown in Figure 6-4 and described in Table 6-3, allows the application to
configure the number of single-bit error corrections by the SECDED logic inside the Cortex-R4F CPU
before generating a single-bit error interrupt.
Figure 6-4. TCRAM Module Single-Bit Error Correction Threshold Register (RAMTHRESHOLD)
[offset = 04h]
31
16
Reserved
R-0
15
0
THRESHOLD
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 6-3. TCRAM Module Single-Bit Error Correction Threshold Register (RAMTHRESHOLD)
Field Descriptions
Bit
Field
31-16
Reserved
15-0
THRESHOLD
316
Value
0
Description
Read returns 0. Writes have no effect.
Single-bit Error Threshold Count. This field contains the threshold value for the Single-bit Error
Correction (SEC) occurrences before the single-bit error interrupt is generated. If this threshold is
set to 1 then all single-bit error addresses are captured. To enable the error occurrence detection,
the threshold must be set to a non-zero value.
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6.7.3 TCRAM Module Single-Bit Error Occurrences Counter Register (RAMOCCUR)
The RAMOCCUR register, shown in Figure 6-5 and described in Table 6-4, indicates the number of
single-bit error corrections performed by the SEC logic inside the Cortex-R4F CPU.
Figure 6-5. TCRAM Module Single-Bit Error Occurrences Counter Register (RAMOCCUR)
[offset = 08h]
31
16
Reserved
R-0
15
0
SINGLE_ERROR_OCCURRENCES
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 6-4. TCRAM Module Single-Bit Error Occurrences Counter Register (RAMOCCUR)
Field Descriptions
Bit
Field
Value
31-16
Reserved
15-0
SINGLE_ERROR_
OCCURRENCES
0
Description
Read returns 0. Writes have no effect.
Single-bit Error Correction Occurrences. This 16-bit counter contains the number of singlebit error occurrences. RAMOCCUR is reset to zero when it becomes equal to the
THRESHOLD value set in the RAMTHRESHOLD register. The application must clear the
RAMOCCUR register by writing 0x0 before setting the THRESHOLD value. If the
RAMOCCUR value is already higher than the programmed THRESHOLD value then the
counter increments and wraps around (overflow) to zero.
Note: If the application tries to clear the RAMOCCUR register at the same time as the
TCRAM Module tried to update it, then the TCRAM Module takes priority.
Note: When the RAMTHRESHOLD register is set to 1, then the RAMOCCUR register
must be cleared whenever a single-bit error correction occurs in order to count
subsequent single-bit error corrections.
6.7.4 TCRAM Module Interrupt Control Register (RAMINTCTRL)
The RAMINTCTRL register, shown in Figure 6-6 and described in Table 6-5, enables the generation of an
interrupt to the CPU whenever the number of single-bit error corrections (RAMOCCUR) reaches the
programmed threshold (RAMTHRESHOLD).
Figure 6-6. TCRAM Module Interrupt Control Register (RAMINTCTRL) [offset = 0Ch]
31
16
Reserved
R-0
15
1
0
Reserved
SERR_EN
R-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 6-5. TCRAM Module Interrupt Control Register (RAMINTCTRL) Field Descriptions
Bit
Field
31-1
Reserved
0
SERR_EN
Value
0
Description
Read returns 0. Writes have no effect.
Single-bit Error Correction Interrupt Enable. This bit, when set to 1, enables the generation of the
single-bit error interrupt when the RAMOCCUR count reaches the programmed RAMTHRESHOLD.
If the interrupt is not enabled, the single-bit error counter continues to count by resetting back to
zero without generating any error interrupt. The SERR status flag in the RAMERRSTATUS register
gets set regardless of whether the SERR interrupt is enabled or not.
0
Single-bit error generation is disabled.
1
Single-bit error generation is enabled.
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6.7.5 TCRAM Module Error Status Register (RAMERRSTATUS)
The RAMERRSTATUS register, shown in Figure 6-7 and described in Table 6-6, indicates the status of
the various error conditions monitored by the TCRAM Module.
Figure 6-7. TCRAM Module Error Status Register (RAMERRSTATUS) [offset = 10h]
31
16
Reserved
R-0
15
10
7
6
9
8
Reserved
WADDR_
PAR_ FAIL
RADDR_
PAR_ FAIL
R-0
R/W1CP-0
R/W1CP-0
5
4
3
2
1
0
Reserved
DERR
ADDR_COMP_
LOGIC_FAIL
Reserved
ADDR_DEC_
FAIL
Reserved
SERR
R-0
R/W1CP-0
R/W1CP-0
R-0
R/W1CP-0
R-0
R/W1CP-0
LEGEND: R/W = Read/Write; R = Read only; W1CP = Write 1 to clear in privilege mode only; -n = value after reset
Table 6-6. TCRAM Module Error Status Register (RAMERRSTATUS) Field Descriptions
Bit
Field
31-10 Reserved
Value Description
0
Read returns 0. Writes have no effect.
9
WADDR_PAR_FAIL
This bit indicates a Write Address Parity Failure. This bit must be cleared by writing 1 to it
in order to enable the capture of parity error address for subsequent failures. This bit must
be in a cleared state for generation of any new parity error interrupt.
8
RADDR_PAR_FAIL
This bit indicates a Read Address Parity Failure. This bit must be cleared by writing 1 to it
in order to enable the capture of parity error address for subsequent failures. This bit must
be in a cleared state for generation of any new parity error interrupt.
7-6
Reserved
0
Read returns 0. Writes have no effect.
5
DERR
This bit indicates a multi-bit error detected by the Cortex-R4F SECDED logic.
4
ADDR_COMP_LOGIC_FAIL
Address decode logic element failed. This bit indicates that the redundant address decode
logic test scheme has detected that a compare element has malfunctioned during the
testing of the logic. This bit has to be cleared by writing 1 to it in order to enable the
capture of uncorrectable error address for subsequent failures. This bit has to be in a
cleared state for generation of a new uncorrectable error interrupt. This bit only gets set in
the test mode, and has no relevance in functional mode.
3
Reserved
2
ADDR_DEC_FAIL
1
Reserved
0
SERR
318
0
Read returns 0. Writes have no effect.
Address decode failed. This bit indicates that an address error interrupt was generated by
the redundant address decode and compare logic due to a functional failure. This bit must
be cleared by writing 1 to it in order to enable the capture of uncorrectable error address
for subsequent failures. This bit has to be in a cleared state for generation of a new
address error interrupt.
0
Read returns 0. Writes have no effect.
Single Error Status. This bit indicates that the single-bit error threshold has been reached.
This bit is set even if the single-bit error threshold interrupt is disabled. This bit must be
cleared by writing 1 to it in order to clear the interrupt request and to enable subsequent
single-bit error interrupt generation.
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NOTE: For equality test:
•
•
If the comparator matches (no true silicon fail), there is no status bit set for
ADDR_COMP_LOGIC_FAIL or ADDR_DEC_FAIL.
If there is true silicon malfunction, ADDR_COMP_LOGIC_FAIL and
ADDR_DEC_FAIL will be set, no UERRADDRESS is captured.
For inequality test, the compare vector will not match since non-inverted and inverted values
of the same test vector are fed to the comparator:
•
•
If there is no silicon malfunction on any of the comparator bits, then only
ADDR_DEC_FAIL will be set. This is chosen so that we can ensure the
functional ADDR_DEC_FAIL status bit data path can be tested.
If there is a silicon malfunction on any of the comparator bits, then,
ADDR_COMP_LOGIC_FAIL and ADDR_DEC_FAIL will be set, no
UERRADDRESS is captured.
6.7.6 TCRAM Module Single-Bit Error Address Register (RAMSERRADDR)
The RAMSERRADDR register, shown in Figure 6-8 and described in Table 6-7, captures the address for
which the Cortex-R4F CPU detected a single-bit error.
NOTE: The SERR bit in the RAMERRSTATUS register must be cleared, by writing 1 to the bit, in
order to enable the RAMSERRADDR register to capture a subsequent new error address.
Figure 6-8. TCRAM Module Single-Bit Error Address Register (RAMSERRADDR)
[offset = 14h]
31
18
Reserved
R-0
17
3
2
0
SINGLE_ERROR_ADDRESS
Reserved
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 6-7. TCRAM Module Single-Bit Error Address Register (RAMSERRADDR)
Field Descriptions
Bit
Field
31-18 Reserved
17-3
Value Description
0
SINGLE_ERROR_ADDRESS
Read returns 0. Writes have no effect.
This register captures bits 17-3 of the address for which the Cortex-R4F CPU detects a
single-bit error when the RAMTHRESHOLD register is set to 1. The lower 3 bits are
always tied to zero so that the address captured is a double-word (64-bit) address. This is
a 64-bit-aligned address is stored as an offset from the base of the TCRAM or ECC
memory.
This register can only be reset by asserting power-on reset, and holds the last error
address even after a system reset.
2-0
Reserved
0
Read returns 0. Writes have no effect.
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6.7.7 TCRAM Module Uncorrectable Error Address Register (RAMUERRADDR)
The RAMUERRADDR register, shown in Figure 6-9 and described in Table 6-8, captures the address for
which the Cortex-R4F CPU detected a multi-bit error.
Figure 6-9. TCRAM Module Uncorrectable Error Address Register (RAMUERRADDR)
[offset = 1Ch]
31
23
22
16
Reserved
UNCORRECTABLE_ERROR_ADDRESS
R-0
R-0
15
3
2
0
UNCORRECTABLE_ERROR_ADDRESS
Reserved
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 6-8. TCRAM Module Uncorrectable Error Address Register (RAMUERRADDR)
Field Descriptions
Bit
Field
31-23
Reserved
22-3
UNCORRECTABLE_
ERROR_ADDRESS
Value
0
Description
Read returns 0. Writes have no effect.
This register captures the address for which there was an uncorrectable error. The
uncorrectable error is indicated by the Cortex-R4F CPU's SECDED logic.
For the SECDED multi-bit or double-bit uncorrectable error this register stores bits 17-3 of
the TCM access address. The lower 3 bits 2-0 are always read as zeros to indicate that the
latched address is a double-word address. The address bits 31-18 are read as zeros. This
is a 64-bit-aligned address is stored as an offset from the base of the TCRAM or ECC
memory.
For a redundant address decode and compare logic error this register stores the complete
TCM access address rounded to a double-word boundary (bits 22-3). This error is also
indicated by the ADDR_DEC_FAIL flag in the RAMERRSTATUS register. No error address
is stored as a result of a redundant address logic test.
The register has to be read-cleared to enable further error address captures. Reading the
register does not clear its contents but enables the register to be updated with an
uncorrectable error address.
This register can only be reset by asserting power-on reset, and holds the last error address
even after a system reset.
2-0
320
Reserved
0
Read returns 0. Writes have no effect.
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6.7.8 TCRAM Module Test Mode Control Register (RAMTEST)
The RAMTEST register, shown in Figure 6-10 and described in Table 6-9, controls the test mode of the
TCRAM Module.
Figure 6-10. TCRAM Module Test Mode Control Register (RAMTEST) [offset = 30h]
31
16
Reserved
R-0
15
9
8
Reserved
TRIGGER
R-0
R/WP-0
7
6
5
TEST_MODE
R/WP-0
4
Reserved
3
0
TEST_ENABLE
R-0
R/WP-5h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 6-9. TCRAM Module Test Mode Control Register (RAMTEST) Field Descriptions
Bit
Field
31-9
Reserved
8
TRIGGER
7-6
Value
0
Description
Read returns 0. Writes have no effect.
Test Trigger. This is an auto reset test trigger used to test the redundant address decode
and compare logic. A redundant address decode test is executed when test mode is
enabled and the test trigger is applied by writing a 1 to this bit. The trigger is valid only if
test is enabled and the correct mode is configured in the TEST_MODE field, and the
ADDR_DEC_FAIL, ADDR_COMP_LOGIC_FAIL, and DERR flags are cleared in the
RAMERRSTATUS register and the RAMUERRADDR register is read-cleared.
TEST_MODE
5-4
Reserved
3-0
TEST_ENABLE
Test Mode. This field selects either equality or inequality testing schemes.
1h
If TEST_MODE is set to 1h, inequality check is done. The test stimulus stored in
ADDRTEST_VECT register is inverted and fed into one channel and the non-inverted
vector is fed into the other channel. If the XOR of these inputs is zero then the UERR
interrupt is generated and ADDR_COMP_LOGIC_FAIL flag is set in RAMERRSTATUS
register.
2h
If TEST_MODE is set to 2h, equality check is done. The test stimulus stored in
ADDRTEST_VECT register is fed directly to both the channels of the comparator. If the
XOR of these two inputs is not zero then UERR interrupt is generated and
ADDR_COMP_LOGIC_FAIL flag is set in RAMERRSTATUS register.
0
Read returns 0. Writes have no effect.
Test Enable. This is a 4-bit key to enable the redundant address decode and compare
logic test scheme. If the test scheme is enabled then the compare logic uses the test
vector inputs from the ADDRTEST_VECT register. The functional path comparison is
disabled when test mode is enabled.
Ah
Test mode is enabled.
All Others
Test mode is disabled.
NOTE: For equality test:
•
•
If the comparator matches (no true silicon fail), there is no status bit set for
ADDR_COMP_LOGIC_FAIL or ADDR_DEC_FAIL.
If there is true silicon malfunction, ADDR_COMP_LOGIC_FAIL and
ADDR_DEC_FAIL will be set, no UERRADDRESS is captured.
For inequality test, the compare vector will not match since non-inverted and inverted values
of the same test vector are fed to the comparator:
•
•
If there is no silicon malfunction on any of the comparator bits, then only
ADDR_DEC_FAIL will be set. This is chosen so that we can ensure the
functional ADDR_DEC_FAIL status bit data path can be tested.
If there is a silicon malfunction on any of the comparator bits, then,
ADDR_COMP_LOGIC_FAIL and ADDR_DEC_FAIL will be set, no
UERRADDRESS is captured.
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6.7.9 TCRAM Module Test Mode Vector Register (RAMADDRDECVECT)
The RAMADDRDECVECT register, shown in Figure 6-11 and described in Table 6-10, is used for testing
the redundant address decode and compare logic of the TCRAM Module.
Figure 6-11. TCRAM Module Test Mode Vector Register (RAMADDRDECVECT) [offset = 38h]
31
27
26
25
16
Reserved
ECC_SELECT
Reserved
R-0
R/WP-0
R-0
15
0
RAM_CHIP_SELECT
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 6-10. TCRAM Module Test Mode Vector Register (RAMADDRDEVECT)
Field Descriptions
Bit
31-27
26
Field
Value
Reserved
0
ECC_SELECT
25-16
Reserved
15-0
RAM_CHIP_SELECT
Description
Read returns 0. Writes have no effect.
ECC Select. This bit is used to store the ECC select value for the redundant address
decode and compare logic. The stored value is passed as test stimulus for the built-in test
scheme.
0
Read returns 0. Writes have no effect.
RAM Chip Select. This field is used to store the RAM chip select value for the redundant
address decode and compare logic. The stored value is passed as test stimulus for the
built-in test scheme.
6.7.10 TCRAM Module Parity Error Address Register (RAMPERRADDR)
The RAMPERRADDR register, shown in Figure 6-12 and described in Table 6-11, stores the address for
which an address-parity error was detected.
Figure 6-12. TCRAM Module Parity Error Address Register (RAMPERRADDR) [offset = 3Ch]
31
23
22
16
Reserved
ADDRESS_PARITY_ERROR_ADDRESS
R-0
R-U
15
3
2
0
ADDRESS_PARITY_ERROR_ADDRESS
Reserved
R-U
R-0
LEGEND: R = Read only; U = Undefined; -n = value after reset
Table 6-11. TCRAM Module Parity Error Address Register (RAMPERRADDR)
Field Descriptions
Bit
Field
31-23
Reserved
22-3
ADDRESS_PARITY_
ERROR_ADDRESS
2-0
Reserved
322
Value
0
Description
Read returns 0. Writes have no effect.
Parity Error Address. This register stores the double-word boundary (bits 22-3) of the TCM
access address for which there was an address parity error. This register must be readcleared to enable further error address captures. Reading the register does not clear the
register contents but enables the register to be updated with a new parity error address.
This is a 64-bit-aligned address is stored as an offset from the base of the TCRAM or ECC
memory.
0
Read returns 0. Writes have no effect.
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6.7.11 Auto-Memory Initialization Enable Register (INIT_DOMAIN)
The INIT_DOMAIN register is shown in Figure 6-13 and described in Table 6-12. The INIT_DOMAIN
register should not be written into when a memory initialization is proceeding. In other words, the
INIT_DOMAIN register should be programmed prior to the generation of the SYS_TCRAMW_MMI_INIT_I
pulse from the system module. You should disable the initialization of any implemented memory domain
that has been powered down by software before auto-memory initialization.
Figure 6-13. Auto-Memory Initialization Enable Register (INIT_DOMAIN) [offset = 40h]
31
16
Reserved
R-0
15
8
7
0
Reserved
AUTO_MEM_INIT_ENABLE
R-0
R/WP-FFh
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 6-12. Auto-Memory Initialization Enable Register (INIT_DOMAIN)
Field Descriptions
Bit
Field
31-8
Reserved
7-0
AUTO_MEM_INIT_ENABLE
Value Description
0
Read returns 0. Writes have no effect.
0-FFh These bits are used to enable auto-memory initialization per power domain. These bits
are all 1 by default and need to be written to 0 to prevent a certain power domain from
getting initialized. Note that these bits are only enable bits for their respective power
domains and the indication for the start of Memory Initialization would still come from the
system module through the pulsed input signal SYS_TCRAMW_MMI_INIT_I.
bit[0] represents the enable bit for power domain 0.
bit[1] represents the enable bit for power domain 1.
bit[2] represents the enable bit for power domain 2.
bit[3] represents the enable bit for power domain 3.
bit[4] represents the enable bit for power domain 4.
bit[5] represents the enable bit for power domain 5.
bit[6] represents the enable bit for power domain 6.
bit[7] represents the enable bit for power domain 7.
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Chapter 7
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Programmable Built-In Self-Test (PBIST) Module
This chapter describes the programmable built-in self-test (PBIST) controller module used for testing the
on-chip memories on the Hercules microcontrollers.
324
Topic
...........................................................................................................................
7.1
7.2
7.3
7.4
7.5
7.6
Overview ........................................................................................................
RAM Grouping and Algorithm ...........................................................................
PBIST Flow .....................................................................................................
Memory Test Algorithms on the On-chip ROM ....................................................
PBIST Control Registers ...................................................................................
PBIST Configuration Example ...........................................................................
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7.1
Overview
The PBIST (Programmable Built-In Self-Test) controller architecture provides a run-time-programmable
memory BIST engine for varying levels of coverage across many embedded memory instances.
7.1.1 Features of PBIST
•
•
•
•
•
Information regarding on-chip memories, memory groupings, memory background patterns and test
algorithms stored in dedicated on-chip PBIST ROM
Host processor interface to configure and start BIST of memories
Supports testing of PBIST ROM itself as well
Supports testing of each memory at its maximum access speed in application
Implements intelligent clock gating to conserve power
NOTE: Refer to the device datasheet for the maximum PBIST ROM clock frequency supported.
7.1.2 PBIST vs. Application Software-Based Testing
The PBIST architecture consists of a small coprocessor with a dedicated instruction set targeted
specifically toward testing memories. This coprocessor executes test routines stored in the PBIST ROM
and runs them on multiple on-chip memory instances. The on-chip memory configuration information is
also stored in the PBIST ROM. The testing is done in parallel for each of the CPU data RAMs, while it is
done sequentially for the rest of the memories.
The PBIST Controller architecture offers significant advantages over tests running on the main CortexR4F processor (application software-based testing):
• Embedded CPUs have a long access path to memories outside the tightly-couple memory sub-system,
while the PBIST controller has a dedicated path to the memories specifically for the self-test
• Embedded CPUs are designed for their targeted use and are often not easily programmed for memory
test algorithms.
• The memory test algorithm code on embedded CPUs is typically significantly larger than that needed
for PBIST.
• The embedded CPU is significantly larger than the PBIST controller.
7.1.3 PBIST Block Diagram
Figure 7-1 illustrates the basic PBIST blocks and its wrapper logic for the device.
Figure 7-1. PBIST Block Diagram
Host CPU
Control Interface
PBIST
ROM
Memory
Configurations,
Algorithms,
Backgrouns
PBIST
Controller
Memory
Data
Path
System
and
Peripheral
Memories
Data Logger
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RAM Grouping and Algorithm
7.1.3.1
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On-chip ROM
The on-chip ROM contains the information regarding the algorithms and memories to be tested.
7.1.3.2
Host Processor Interface to the PBIST Controller Registers
The Cortex-R4F CPU can select the algorithm and RAM groups for the memories' self-test from the onchip ROM based on the application requirements. Once the self-test has executed, the CPU can query the
PBIST controller registers to identify any memories that failed the self-test and to then take appropriate
next steps as required by the application's author.
7.1.3.3
Memory Data Path
This is the read and write data path logic between different system and peripheral memories tightly
coupled to the PBIST memory interface. The PBIST controller executes each selected algorithm on each
valid memory group sequentially until all the algorithms are executed.
NOTE: Not all algorithms are designed to run on all RAM groups. If an algorithm is selected to run
on an incompatible memory, this will result in a failure. Refer to Table 2-5 and Table 2-6 for
RAM grouping and algorithm information.
7.2
RAM Grouping and Algorithm
Table 2-5 gives the list of RAM groups and their types supported on the device. Table 2-6 maps the
different algorithms supported in application mode for the RAM groups with the background patterns used
for the particular algorithm.
NOTE: March13 is the most recommended algorithm for the memory self-test.
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7.3
PBIST Flow
Figure 7-2 illustrates the memory self-test flow.
Figure 7-2. PBIST Memory Self-Test Flow Diagram
Yes
Is system in
reset = 1?
No
Setup memories, peripheral and clock tree like
HCLK, VCLK peripheral and ROMCLK as required
for the PBIST test.
Enable PBIST controller by
by writing MSIENA = 0x01
Reset the PBIST controller by
writing MSTGCR = 0x0A
Wait for approximately N
vbus clocks.
Enable pbist clocks and ROM
clock by writing PACT = 0x03
Select the RAM group and
algorithm using RINFO and
ALGO registers
Program OVER = 0 for self test without Override
or OVER = 1 for RINFO Override
Write ROM = 0x03 to enable the
microcode load of the algorithm
and RAM info groups from the
on Chip ROM
Write 0x14 to DLR register to
configure PBIST in ROM mode
and start the Test
Resume PBIST self test by writing
0x02 to the STR register
No
Is (MSTDONE = 1) ?
Read FSRD and FSRA datalog
reg. for Fail data and address values
Yes
Is FSRF0 = 1 ?
Yes
Read RAMT reg for
RGS/RDS info
No
Disable pbist clocks and ROM
clock by writing PACT = 0
Disable PBIST Test
by writing MSTGCR = 0x05
PBIST Selftest Done
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7.3.1 PBIST Sequence
1. Configure the device clock sources and domains so that they are running at their target frequencies.
2. Program the HCLK to PBIST ROM clock ratio by configuring the ROM_DIV field (bits 9:8) of the
MSTGCR register of the system module. Check the device datasheet for the maximum supported
PBIST ROM clock frequency.
3. Enable PBIST Controller by setting bit 1 of MSIENA register in system module.
4. Enable the PBIST self-test by writing a value of 0x0A to bits 3:0 of the MSTGCR in the system module.
5. Wait for N VBUS clock cycles based on the HCLK to PBIST ROM clock ratio:
N = 16 when HCLK:PBIST ROM clock is 1:1
N = 32 when HCLK:PBIST ROM clock is 1:2
N = 64 when HCLK:PBIST ROM clock is 1:4
N = 64 when HCLK:PBIST ROM clock is 1:8
6. Write 1h to PACT register to enable the PBIST internal clocks.
7. Program the ALGO register to decide which algorithm from the instruction ROM must be selected (the
default value of ALGO register is all 1’s, meaning all algorithms are selected). Similarly, program the
RINFOL and RINFOU registers to indicate whether a particular RAM group in the instruction ROM
would get executed or not.
NOTE: In case of RAM Override (Override Register (OVER) = 00), the user should make sure that
only the algorithms that run on similar RAMs are selected. If a single port algorithm is
selected in ROM Algorithm Mask Register (ALGO), the RAM Info Mask Lower Register
(RINFOL) and RAM Info Mask Upper Register (RINFOU) must select only the single port
RAM’s. The same applies for two port RAM’s. Check Architecture chapter for information on
the memory types.
8. Program OVER = 1h to run PBIST self-test without RAM override. Program OVER = 0 to run PBIST
self-test with RAM Override.
9. Write a value of 3h to the ROM mask register should the microcode for the Algorithms as well as the
RAM groups loaded from the on-chip PBIST ROM.
10. Write DLR (Data Logger register) with 14h to configure the PBIST run in ROM mode and to enable the
configuration access. This starts the memory self-tests.
11. Wait for the PBIST self-test done by polling MSTDONE bit of MSTCGSTAT register in System
Module.
12. Once self-test is completed, check the Fail Status register FSRF0.
In case there is a failure (FSRF0 = 1h):
a. Read RAMT register that indicates the RGS and RDS values of the failure RAM
b. Read FSRC0 and FSRC1 registers that contains the failure count
c. Read FSRA0 and FSRA1 registers that contains the address of first failure
d. Read FSRDL0 and FSRDL1 registers that contains the failure data.
e. Write a value of 2h to the STR register to resume the test.
In case there is no failure (FSRF0 = 0) the memory self-test is completed.
a. Disable the PBIST internal clocks by writing a 0 to the PACT register.
b. Disable the PBIST self-test by writing a value of 5h to bits 3:0 of the MSTGCR in the system
module.
13. Repeat steps 2 through 9 for subsequent runs with different RAM group and algorithm configurations.
14. After required Memory tests are completed, Resume or Start the Normal Application software.
NOTE: The contents of the selected memory before the test will be completely lost. User software
must take care of data backup if required. Typically the PBIST tests are carried out at the
beginning of Application software.
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NOTE: Memory test fail information is reported in terms of RGS:RDS and not RAM GROUP. Check
Table 2-5 for information on the RGS:RDS information applicable to each memory being
tested.
7.4
Memory Test Algorithms on the On-chip ROM
This section provides a brief description for some of the test algorithms used for memory self-test.
1. March13N:
• March13N is the baseline test algorithm for SRAM testing. It provides the highest overall coverage.
The other algorithms provide additional coverage of otherwise missed boundary conditions of the
SRAM operation.
• The concept behind the general march algorithm is to indicate:
– The bit cell can be written and read as both a 1 and a 0.
– The bits around the bit cell do not affect the bit cell.
• The basic operation of the march is to initialize the array to a know pattern, then march a different
pattern through the memory.
• Type of faults detected by this algorithm:
– Address decoder faults
– Stuck-At faults
– Coupled faults
– State coupling faults
– Parametric faults
– Write recovery faults
– Read/write logic faults
2. Map Column:
• The MAP COLUMN algorithm is used to identify bit line sensitivities in the memory array. The
memory array is loaded with a row stripe pattern of all 1s in the first row followed by all 0s in the
second row and repeated throughout the array. Then the values are read down each column on
consecutive cycles. The pattern in memory is inverted and run the column reads again.
• This particular pattern is looking for the following SRAM failure mechanisms:
– Leakage due to a low resist path in a bit
– An Open in the bit cell
– Leakage on a BIT or BITN line
– Miss-balance in the sense amp
– Leakage in the sense
– High resist in the sense amp
– Failure of the pre-charge circuits after read operations
3. Pre-Charge:
• The Pre-Charge algorithm exercises the pre-charge capability within the SRAM array. It is
important to specifically target this issue as it is the only part of the analog portion of the SRAM
that is frequency sensitive.
• Similar to the MAP COLUMN algorithm, this algorithm works its way down the columns of the
SRAM. However, unlike the MAP COLUMN, this algorithm sandwiches a write between two reads
to force the worst-case conditions for the pre-charge circuits in the array.
• This test will fail when an increase in system frequency nears the minimum access time of the
array, at this boundary:
– High voltage should operate better than low voltage.
– Likewise, low temperature should operate better than high temperature.
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4. DOWN1a:
• The Down1 pattern forces the switching of all data bits and most address bits on consecutive read
cycles. This is primarily a read/write test of the CPU/memory subsystem.
• The aggressive writes target at-speed write failures.
• It also targets row/column decode in the memory array.
• Targets the sense amps and sense amp multiplexors.
• Memory array output buffers.
• This algorithm operates as follows:
– Load 1st half of the memory under test with one pattern.
– Load 2nd half of the memory under test with the bit-wise inverse of the pattern.
– Alternate sequential reads sequences between one sequence starting at the beginning of the
array and a second sequence starting at the end of the array.
– Upon completion of the read back, invert the patterns in both halves of the array and repeat the
above step.
– Perform an aggressive write sequence by alternating writes between the bottom half of the
memory upwards with a data pattern and the top half of the memory downwards with the
inverse data pattern.
– Invert the data pattern for the above two steps to perform another sequence of aggressive
writes.
5. DTXN2a:
This algorithm is used to target the global column decode Logic.
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7.5
PBIST Control Registers
PBIST controller uses configuration registers for programming the algorithm and its execution. All the
configuration registers are memory mapped for access by the CPU through the Peripheral Bus interface.
The base address for the control registers is FFFF E400h.
NOTE: There is no watchdog functionality implemented in the PBIST controller. If a bad code is
executed, the PBIST runs forever. The PBIST controller does not guard against this
situation.
Registers are accessible only when the clock to the PBIST controller is active. The clock is
activated by first writing 1h to the PACT register.
Table 7-1. PBIST Registers
Offset
Acronym
Register Description
000h - 15Ch
Reserved
Reserved locations. Do not write to these locations.
160h
RAMT
RAM Configuration Register
Section 7.5.1
164h
DLR
Datalogger Register
Section 7.5.2
168h - 17Ch
Section
Reserved
Reserved locations. Do not write to these locations.
180h
PACT
PBIST Activate/Clock Enable Register
Section 7.5.3
184h
PBISTID
PBIST ID Register
Section 7.5.4
188h
OVER
Override Register
Section 7.5.5
190h
FSRF0
Fail Status Fail Register 0
Section 7.5.6
198h
FSRC0
Fail Status Count Register 0
Section 7.5.7
19Ch
FSRC1
Fail Status Count Register 1
Section 7.5.7
1A0h
FSRA0
Fail Status Address 0 Register
Section 7.5.8
1A4h
FSRA1
Fail Status Address 1 Register
Section 7.5.8
1A8h
FSRDL0
Fail Status Data Register 0
Section 7.5.9
1B0h
FSRDL1
Fail Status Data Register 1
Section 7.5.9
1C0h
ROM
ROM Mask Register
Section 7.5.10
1C4h
ALGO
ROM Algorithm Mask Register
Section 7.5.11
1C8h
RINFOL
RAM Info Mask Lower Register
Section 7.5.12
1CCh
RINFOU
RAM Info Mask Upper Register
Section 7.5.13
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7.5.1 RAM Configuration Register (RAMT)
This register is divided into the following internal registers, none of which have a default value after reset.
Figure 7-3 and Table 7-2 illustrate this register.
This register provides the information regarding the memory being currently tested. In case of a PBIST
failure, the application can read this register to identify the RGS:RDS values for the memory that failed the
self-test.
Figure 7-3. RAM Configuration Register (RAMT) [offset = 0160h]
31
24
23
16
RGS
RDS
R/W-X
R/W-X
15
8
7
6
5
2
1
0
DWR
SMS
PLS
RLS
R/W-X
R/W-X
R/W-X
R/W-X
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-2. RAM Configuration Register (RAMT) Field Descriptions
Bit
Field
Description
31-24
RGS
Ram Group Select. Refer to Table 2-5 for information on the RGS value for each memory.
23-16
RDS
Return Data Select. Refer to Table 2-5 for information on the RDS values for each memory.
15-8
DWR
Data Width Register
7-6
SMS
Sense Margin Select Register
5-2
PLS
Pipeline Latency Select
1-0
RLS
RAM Latency Select
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7.5.2 Datalogger Register (DLR)
This register puts the PBIST controller into the appropriate comparison modes for data logging. Figure 7-4
and Table 7-3 illustrate this register.
Figure 7-4. Datalogger Register (DLR) [offset = 0164h]
31
16
Reserved
R-0
15
4
3
2
Reserved
5
DLR4
Rsvd
DLR2
1
Reserved
0
R-0
R/W-0
R/W-1
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-3. Datalogger Register (DLR) Field Descriptions
Bit
Field
31-5
Reserved
4
DLR4
3
Reserved
2
DLR2
1-0
Reserved
•
Value
0
Description
Reads return 0. Do not change these bits from their default value.
Config access: setting this bit allows the host processor to configure the PBIST controller registers.
1
Do not change this bit from its default value of 1.
ROM-based testing: setting this bit enables the PBIST controller to execute test algorithms that are
stored in the PBIST ROM.
00
Do not change these bits from their default value of 00.
DLR2: ROM-based testing mode
Writing a 1 to this register starts the ROM-based testing. This register is used to initiate ROM-based
testing from Config and ATE interfaces. Also, since a 1 in this bit position means the instruction ROM is
used for memory testing, all the intermediate interrupts and PBIST done signal after each memory test are
masked until all the selected algorithms in the ROM are executed for all RAM groups. However, a failure
would stop the test and report the status immediately.
• DLR4: Config access mode
This mode, when set, indicates the CPU is being used to access PBIST.
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7.5.3 PBIST Activate/Clock Enable Register (PACT)
This is the first register that needs to be programmed to activate the PBIST controller. Bit [0] is used for
static clock gating, and unless a 1 is written to this bit, all the internal PBIST clocks are shut off. Figure 7-5
and Table 7-4 illustrate this register.
NOTE: This register must be programmed to 1h during application self-test.
Figure 7-5. PBIST Activate/ROM Clock Enable Register (PACT) [offset = 0180h]
31
16
Reserved
R-0
15
1
0
Reserved
PACT0
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-4. PBIST Activate/ROM Clock Enable Register (PACT) Field Descriptions
Bit
Field
31-1
Reserved
0
Value
0
PACT0
•
Description
Reads return 0. Writes have no effect.
PBIST internal clocks enable.
0
Disable PBIST internal clocks.
1
Enable PBIST internal clocks.
PACT0
This bit must be set to 1 to turn on the PBIST internal clocks. Setting this bit asserts an internal signal that
is used as the clock gate enable. As long as this bit is 0, any access to the PBIST will not go through and
the PBIST will remain in an almost zero-power mode.
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7.5.4 PBIST ID Register
Functionality of this register is described in Figure 7-6 and Table 7-5.
Figure 7-6. PBIST ID Register [offset = 184h]
31
16
Reserved
R-0
15
8
7
0
Reserved
PBIST ID
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-5. PBIST ID Register Field Descriptions
Bit
Field
31-8
Reserved
7-0
PBIST ID
Value
0
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Description
Reads return 0. Writes have no effect.
This is a unique ID assigned to each PBIST controller in a device with multiple PBIST controllers.
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7.5.5 Override Register (OVER)
Functionality of the register is described in Figure 7-7 and Table 7-6.
Figure 7-7. Override Register (OVER) [offset = 0188h]
31
16
Reserved
R-0
15
3
2
Reserved
1
Reserved
R-0
R-0
0
OVER0
R-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-6. Override Register (OVER) Field Descriptions
Bit
Field
Value
Description
31-3
Reserved
0
Reads return 0. Writes have no effect.
2
Reserved
0
Reserved. This bit must not be changed from its default value of 0.
1
Reserved
0
Reserved. This bit must not be changed from its default value of 0.
0
OVER0
•
RINFO Override Bit
0
The RAM info registers RINFOL and RINFOU are used to select the memories for test.
1
The memory information available from ROM will override the RAM selection from the RAM info
registers RINFOL and RINFOU.
OVER0
While doing ROM-based testing, each algorithm downloaded from the ROM has a memory mask
associated with it that defines the applicable memory groups the algorithm will be run on. By default, this
bit is set to 1, which means the memory mask that is downloaded from the ROM will overwrite the RAM
info registers. The override bit can be reset by writing a 0 to it. In this case, the application can select the
RAM groups to be tested by configuring the RAM info registers.
NOTE: When this override bit = 0, each algorithm selected in ALGO register will run on each RAM
selected in RINFOL and RINFOU register. It must be ensured that:
1. Only the same type of memories (single port or two port) are selected, and
2. Only memories that are valid for all algorithms enabled via the ALGO register
are selected.
If the above two requirements are not met, the memory self-test will fail.
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7.5.6 Fail Status Fail Register (FSRF0)
This register indicates if a Port0 failure occurred during a memory self-test. Bit [0] gets set whenever a
failure occurs. Functionality of the register is described in Figure 7-8 and Table 7-7.
Figure 7-8. Fail Status Fail Register 0 (FSRF0) [offset = 0190h]
31
16
Reserved
R-0
15
1
0
Reserved
FSRF0
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-7. Fail Status Fail Register 0 (FSRF0) Field Descriptions
Bit
31-1
0
Field
Reserved
Value
0
FSRF0
Description
Reads return 0. Writes have no effect.
Fail Status 0. This bit would be cleared by reset of the module using MSTGCR register in system
module.
0
No failure occurred.
1
Failure occurred on port 0.
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7.5.7 Fail Status Count Registers (FSRC0 and FSRC1)
These registers keep count of the number of failures observed during the memory self-test. The PBIST
controller stops executing the memory self-test whenever a failure occurs in any memory instance for any
of the test algorithms. The value in FSRC0 / FSRC1 gets incremented by one whenever a failure occurs
and gets decremented by one when the failure is processed. FSRC0 is for Port 0 and FSRC1 is for Port 1.
Figure 7-9 and Table 7-8 illustrate the FSRC0 register, while Figure 7-10 and Table 7-9 illustrate the
FSRC1 register.
Figure 7-9. Fail Status Count 0 Register (FSRC0) [offset = 0198h]
31
16
Reserved
R-0
15
8
7
0
Reserved
FSRC0
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-8. Fail Status Count 0 Register (FSRC0) Field Descriptions
Bit
Field
31-8
Reserved
7-0
FSRC0
Value
0
Description
Reads return 0. Writes have no effect.
Fail Status Count 0. Indicates the number of failures on port 0.
Figure 7-10. Fail Status Count Register 1 (FSRC1) [offset = 019Ch]
31
16
Reserved
R-0
15
8
7
0
Reserved
FSRC1
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-9. Fail Status Count Register 1 (FSRC1) Field Descriptions
Bit
Field
31-8
Reserved
7-0
FSRC1
338
Value
0
Description
Reads return 0. Writes have no effect.
Fail Status Count 1. Indicates the number of failures on port 1.
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7.5.8 Fail Status Address Registers (FSRA0 and FSRA1)
These registers capture the memory address of the first failure on port 0 and port 1, respectively. Figure 711 and Table 7-10 illustrate the FSRA0 register, while Figure 7-12 and Table 7-11 illustrate the FSRA1
register.
Figure 7-11. Fail Status Address 0 Register (FSRA0) [offset = 01A0h]
31
16
Reserved
R-0
15
0
FSRA0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-10. Fail Status Address 0 Register (FSRA0) Field Descriptions
Bit
Field
31-16
Reserved
15-0
FSRA0
Value
0
Description
Reads return 0. Writes have no effect.
Fail Status Address 0. Contains the address of the first failure.
Figure 7-12. Fail Status Address 1 Register (FSRA1) [offset = 01A4h]
31
16
Reserved
R-0
15
0
FSRA1
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-11. Fail Status Address 1 Register (FSRA1) Field Descriptions
Bit
Field
31-16
Reserved
15-0
FSRA1
Value
0
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Description
Reads return 0. Writes have no effect.
Fail Status Address 1. Contains the address of the first failure.
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7.5.9 Fail Status Data Registers (FSRDL0 and FSRDL1)
These registers are used to capture the failure data in case of a memory self-test failure. FSRDL0
corresponds to Port 0, while FSRDL1 corresponds to Port 1. Figure 7-13 and Table 7-12 illustrate the
FSRDL0 register, while Figure 7-14 and Table 7-13 illustrate the FSRDL1 register.
Figure 7-13. Fail Status Data Register 0 (FSRDL0) [offset = 01A8h]
31
16
FSRDL0
R-AAAAh
15
0
FSRDL0
R-AAAAh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-12. Fail Status Data Register 0 (FSRDL0) Field Descriptions
Bit
31-0
Field
Description
FSRDL0
Failure data on port 0
Figure 7-14. Fail Status Data Register 1 (FSRDL1) [offset = 01B0h]
31
16
FSRDL1
R-AAAAh
15
0
FSRDL1
R-AAAAh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-13. Fail Status Data Register 1 (FSRDL1) Field Descriptions
Bit
31-0
340
Field
Description
FSRDL1
Failure data on port 1
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7.5.10 ROM Mask Register (ROM)
This two-bit register sets appropriate ROM access modes for the PBIST controller. The default value is
11b. This register is illustrated in Figure 7-15. It can be programmed according to Table 7-14.
Figure 7-15. ROM Mask Register (ROM) [offset = 01C0h]
31
16
Reserved
R-0
15
2
1
0
Reserved
ROM
R-0
R/W-3h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-14. ROM Mask Register (ROM) Field Descriptions
Bit
Field
31-2
Reserved
1-0
ROM
Value
0
Description
Reads return 0. Writes have no effect.
ROM Mask
0
No information is used from ROM.
1h
Only RAM Group information from ROM.
2h
Only Algorithm information from ROM.
3h
Both Algorithm and RAM Group information from ROM. This option should be selected for application
self-test.
7.5.11 ROM Algorithm Mask Register (ALGO)
This register is used to indicate the algorithm(s) to be used for the memory self-test routine. Each bit
corresponds to a specific algorithm. For example, bit [0] controls whether algorithm 1 is enabled or not.
Figure 7-16 and Table 7-15 illustrate this register.
Figure 7-16. ROM Algorithm Mask Register (ALGO) [offset = 01C4h]
31
24
23
16
ALGO3
ALGO2
R/W-FFh
R/W-FFh
15
8
7
0
ALGO1
ALGO0
R/W-FFh
R/W-FFh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-15. Algorithm Mask Register (ALGO) Field Descriptions
Bit
31
30
Field
Value
Description
0
Algorithm 32 is not selected.
1
Selects algorithm 32 for PBIST run.
0
Algorithm 31 is not selected.
1
Selects algorithm 31 for PBIST run.
0
Algorithm 1 is not selected.
1
Selects algorithm 1 for PBIST run.
0
None of the algorithms are selected.
:
0
31-0
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NOTE: Please refer to Table 2-6 for available algorithms and the memories on which each algorithm
can be run.
7.5.12 RAM Info Mask Lower Register (RINFOL)
This register is to select RAM groups to run the algorithms selected in the ALGO register. For an algorithm
to be executed on a particular RAM group, the corresponding bit in this register must be set to 1. The
default value of this register is all 1s, which means all the RAM Groups are selected. Figure 7-17 and
Table 7-16 illustrate this register.
The information from this register is used only when bit 0 in OVER register is not set.
Figure 7-17. RAM Info Mask Lower Register (RINFOL) [offset = 01C8h]
31
24
23
16
RINFOL3
RINFOL2
R/W-FFh
R/W-FFh
15
8
7
0
RINFOL1
RINFOL0
R/W-FFh
R/W-FFh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-16. RAM Info Mask Lower Register (RINFOL) Field Descriptions
Bit
31
30
Field
Value
Description
0
RAM Group 32 is not selected.
1
Selects group 32 for PBIST run.
0
RAM Group 31 is not selected.
1
Selects RAM group 31 for PBIST run.
0
RAM Group 1 is not selected.
1
Selects RAM Group 1 for PBIST run.
0
None of the RAM Groups 1 to 32 are selected.
:
0
31-0
NOTE: Please refer to Table 2-5 for RAM info groups.
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7.5.13 RAM Info Mask Upper Register (RINFOU)
This register is to select RAM groups to run the algorithms selected in the ALGO register. For an algorithm
to be executed on a particular RAM group, the corresponding bit in this register should be set to 1. The
default value of this register is all 1s, which means all the RAM Info Groups would be selected. Figure 718 and Table 7-17 illustrate this register.
Figure 7-18. RAM Info Mask Upper Register (RINFOU) [offset = 01CCh]
31
24
23
16
RINFOU3
RINFOU2
R/W-FFh
R/W-FFh
15
8
7
0
RINFOU1
RINFOU0
R/W-FFh
R/W-FFh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-17. RAM Info Mask Upper Register (RINFOU) Field Descriptions
Bit
31
30
Field
Value
Description
0
RAM Group 64 is not selected.
1
Selects group 64 for PBIST run.
0
RAM Group 63 is not selected.
1
Selects RAM group 63 for PBIST run.
0
RAM Group 33 is not selected.
1
Selects RAM Group 33 for PBIST run.
0
None of RAM Groups 33 to 64 are selected.
:
0
31-0
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PBIST Configuration Example
The following examples assume that the PLL is locked and selected as clock source with
HCLK = 160 MHz and VCLK = 80 MHz.
7.6.1 Example 1 : Configuration of PBIST Controller to Run Self-Test on RAM Group 3
This example explains the configurations for running March13, Down1A and Map Column algorithms on
RAM Group 3 (see device datasheet for RAM Group information).
1. Program the HCLK to PBIST ROM clock ratio to 1:2 in System Module.
MSTGCR[9:8] = 1
2. Enable PBIST Controller in System Module.
MSIENA[31:0] = 0x00000001
3. Enable the PBIST self-test in System Module.
MSTGCR[3:0] = 0xA
4. Wait for at least 32 VCLK cycles in a software loop.
5. Enable the PBIST internal clocks.
PACT = 0x1
6. Disable RAM Override. This will make the PBIST controller use the information provided by the
application in the RINFOx and ALGO registers for the memory self-test.
OVER = 0x0
7. Select the Algorithm (refer to Table 2-6).
ALGO = 0x00000054 (Algo 3 = March13N, Algo 5 = down1A_red, Algo 7 = Map column for two-port
RAM Group 3)
8. Program the RAM group Info to select RAM Group 3 (refer to Table 2-5).
RINFOL = 0x00000004 (select RAM Group 3)
RINFOU = 0x00000000 (since this device supports only 28 RAM Groups)
9. Select both Algorithm and RAM information from on-chip PBIST ROM.
ROM = 0x3
10. Configure PBIST to run in ROM Mode and start PBIST run.
DLR = 0x14
11. Wait for PBIST test to complete by polling MSTDONE bit in System Module.
while (MSTDONE !=1)
12. Once self-test is completed, check the Fail Status register FSRF0.
a. In case there is a failure (FSRF0 = 0x01):
i. Read RAMT register that indicates the RGS and RDS values of the failure RAM.
ii. Read FSRC0 and FSRC1 registers that contains the failure count.
iii. Read FSRA0 and FSRA1 registers that contains the address of first failure.
iv. Read FSRDL0 and FSRDL1 registers that contains the failure data.
v. Resume the Test if required using Program Control register (offset = 0x16C) STR = 2.
b. In case there is no failure (FSRF0 = 0x00), the memory self-test is completed:
i. Disable the PBIST internal clocks.
PACT = 0
ii. Disable the PBIST self-test.
MSTGCR[3:0] = 0x5
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7.6.2 Example 2 : Configuration of PBIST Controller to Run Self-Test on ALL RAM Groups
This example explains the configurations for running March13, Down1A and Mapcolumn algorithms on all
RAM groups defined in the PBIST ROM.
1. Program the HCLK to PBIST ROM clock ratio to 1:2 in System Module.
MSTGCR[9:8] = 1
2. Enable PBIST Controller in System Module.
MSIENA[31:0] = 0x00000001
3. Enable the PBIST self-test in System Module.
MSTGCR[3:0] = 0xA
4. Wait for at least 32 VCLK cycles in a software loop.
5. Enable the PBIST internal clocks.
PACT = 0x1
6. Enable RAM Override.
OVER = 0x1
7. Select the Algorithms to be run (refer to Table 2-6).
ALGO = 0x000000FC (select March13N, Down1A and Map Column algorithms for single-port and twoport RAMs)
8. Select both Algorithm and RAM information from on-chip PBIST ROM.
ROM = 0x3
9. Configure PBIST to run in ROM Mode and kickoff PBIST test.
DLR = 0x14
10. Wait for PBIST test to complete by polling MSTDONE bit in System Module.
while (MSTDONE !=1)
11. Once self-test is completed, check the Fail Status register FSRF0:
a. In case there is a failure (FSRF0 = 0x01):
i. Read RAMT register that indicates the RGS and RDS values of the failure RAM.
ii. Read FSRC0 and FSRC1 registers that contains the failure count.
iii. Read FSRA0 and FSRA1 registers that contains the address of first failure.
iv. Read FSRDL0 and FSRDL1 registers that contains the failure data.
v. Resume the Test if required using Program Control register (offset = 0x16C) STR = 2.
b. In case there is no failure (FSRF0 = 0x00), the memory self-test is completed:
i. Disable the PBIST internal clocks.
PACT = 0
ii. Disable the PBIST self-test.
MSTGCR[3:0] = 0x5
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CPU Self-Test Controller (STC) Module
This chapter describes the basics and configuration of the CPU self-test controller present in the device.
346
Topic
...........................................................................................................................
8.1
8.2
8.3
8.4
8.5
General Description ..........................................................................................
Application Self-Test Flow .................................................................................
STC Test Coverage and Duration........................................................................
STC Control Registers ......................................................................................
STC Configuration Example ..............................................................................
CPU Self-Test Controller (STC) Module
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8.1
General Description
The CPU self-test controller (STC) is used to test the ARM-CPU core using the Deterministic Logic Built-in
Self-Test (LBIST) Controller as the test engine. To achieve better coverage for the self-test of complex
cores like Cortex-R4, on-chip logic BIST is the preferred solution.
8.1.1 CPU Self-Test Controller Features
The CPU self-test controller has the following features:
• Capable of running the complete test as well as running a few intervals at a time
– Ability to continue from the last executed interval (test set) as well as the ability to restart from the
beginning (first test set)
– Total of 24 intervals supported in this device
• Complete isolation of the self-tested CPU core from the rest of the system during the self-test run
– The self-tested CPU core master bus transaction signals are configured to be in idle mode during
the self-test run
– Any master access to the CPU core under self-test (example: DMA access to CPU TCM) will be
held until the completion of the self-test
• Ability to capture the failure interval number
• Timeout counter for the CPU self-test run as a fail-safe feature
• Able to read the MISR data (shifted from LBIST controller) of the last executed interval of the self-test
run for debugging purposes
• STCCLK determines the self-test execution speed, STC clock divider (STCCLKDIV) register in the
system module is used to divide HCLK (system clock) to generate STCCLK
8.1.2 STC Block Diagram
STC module provides an interface to the LBIST controller implemented on the core.
The CPU STC is composed of following blocks of logic:
• ROM Interface
• FSM and Sequence Control
• Register Block
• Peripheral Bus Interface (VBUSP Interface)
• STC Bypass/ATE Interface
8.1.2.1
ROM Interface
This block handles the ROM address and control signal generation to read the self-test microcode from
the ROM. The test microcode and golden signature value for each interval are stored in ROM.
8.1.2.1.1 FSM and Sequence Control
This block generates the signals and data to the LBIST controller based on the seed, test_type and scan
chain depth.
8.1.2.1.2 Clock Control
The CLOCK CNTRL sub-block handles the internal clock selection and clock generation for the ROM and
LBIST controller.
8.1.2.2
Register Block
This block handles the control of the self-test controller. This block contains various configuration and
status registers that provide the result of a self-test run. These registers are memory-mapped and
accessible through the Peripheral Bus (VBUSP) Interface. This block controls the reseeding (reloading the
existing seed of the PRPG) in the LBIST controller.
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STC Bypass / ATE Interface
This is a production test interface. Only for TI internal use.
8.1.2.4
Peripheral Bus (VBUSP) Interface
STC control registers are accessed through Peripheral Bus (VBUSP) Interface. During application
programming, configuration registers are programmed through the Peripheral Bus Interface to enable and
run the self-test controller.
Figure 8-1. STC Block Diagram
Global Clock
Controller
Clock Controller
ESM
ROM
FSM
and
Sequence COMP
Controller BLK1
ROM
Interface
COMP
BLK1
Cpu_Reset
misr_out
misr_out
STC
CPU1
(BIST’ed core)
DBIST
CNTRL
STC REG
STC_BYPASS /
BLOCK
ATE Interface
CCM
DBIST
CNTRL
CPU2
(BIST’ed
core)
VBUSP
Interface
PCR
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8.2
Application Self-Test Flow
This section describes the STC module configuration and the application self-test flow that the user should
follow for successful execution. The following two configurations must be part of the STC initialization
code:
• STC clock rate configuration, STC clock divider (STCCLKDIV) register in system module is used to
divide HCLK (system clock) to generate STCCLK
• Clear SYSESR register before triggering an STC test
8.2.1 STC Module Configuration
•
•
•
Configure the test interval count using STCGCR0[31:16] register. A maximum of 24 intervals are
supported in the device. You can run 24 intervals together or in slices. If the tests are run in slices, the
user software can specify to the self-test controller whether to continue the run from the next interval
onwards or to restart from interval 0 using bit STCGCR0[0]. This bit gets reset after the completion of
the self-test run.
Configure self-test run timeout counter preload register STCTPR. This register contains the total
number of VBUS clock cycles it will take before a self-test timeout error (TO_ERR) will be triggered
after the initiation of the self-test run.
Enable CPU self-test by writing the enable key to STCGCR1 register.
8.2.2 Context Saving
STC generates a CPU reset after completion of the test regardless of pass or fail. You can run the STC
test during startup or can divide STC into 24 or fewer intervals and run them during normal operation.
If STC is ran only on startup, the user software need not save the CPU contents since the reset caused
will go through all startup configurations. You should check the STCGSTAT register for the self-test status
before going to the application software.
If STC is divided into intervals and ran, user software must save the CPU contents and reload them after
the CPU reset caused by the completion of the STC test interval. The check for STC status should bypass
STC run if the reset is caused by an STC run to prevent a cyclic reset, that is, if reset is caused by STC
the second time through, then it should not be ran again. You should also check the STCGSTAT register
for the self-test status before restoring the application software.
Following are some of the registers that are required to be backed up before and restored after self-test:
1. CPU core registers (all modes R0-R15, PC, CPSR)
2. CP15 System Control Coprocessor registers - MPU control and configuration registers, Auxiliary
Control Register used to Enable ECC, Fault Status Register etc.
3. CP13 Coprocessor Registers - FPU configuration registers, General Purpose Registers
4. Hardware Break Point and watch point registers like BVR, BSR, WVR, WSR etc.
For more information on the CPU reset, refer to the ARM® Cortex®-R4F Technical Reference Manual.
NOTE: Check all reset source flags in the SYSESR register after a CPU BIST execution. If a flag, in
addition to CPU reset, is set, clear the CPU reset flag and service the other reset sources
accordingly.
8.2.3 Entering CPU Idle Mode
After enabling the STC test by writing the STC enable key, the test is triggered only after the CPU is taken
to idle mode by executing the CPU Idle Instruction asm(“ WFI”).
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8.2.4 Self-Test Completion and Error Generation
At the end of each interval, the 128 bit MISR value (reflected in registers CPUx_CURMISR[3:0]) from the
DBIST controller is shifted into the STC. This is compared with the golden MISR value stored in the ROM.
At the end of a CPU self-test, the STC controller updates the status flags in the Global Status Register
(STCGSTAT) and resets the CPU. In case of a MISR mismatch or a test timeout, an error is generated
through the ESM module. TEST_ERR signal is asserted when an MISR miss-compare occurs during the
self-test. A TO_ERR is asserted when a timeout occurs during the self-test, meaning the test could not
complete within the time specified in the timeout counter preload register STCTPR. However, at the
device level, these two errors are combined and mapped to a single ESM channel. To identify which error
occurred, user software must check the global status register (STCGSTAT) and fail status register
STCFSTAT in the ESM interrupt service routine.
Figure 8-2 illustrates the application self-test test flow chart, drawn based on the assumption that the
device has gone through startup, necessary clocks initialized and SYSESR register bits cleared.
Figure 8-2. Application Self-Test Flow Chart
Configure STCCLK rate using STCCLKDIV
register in SYS2 register frame.
Program the STCGCR0 registers to
specify the number of intervals(N), timeout
counter etc for a selftest run.
Configure STC_ENA Key to
enable SelfTest
NO
StartUp selftest?
Store CPU state and Registers in Memory
before starting STC Test
YES
Configure CPU in WFI mode
(IDLE mode)
NO
WFI executed?
YES
CPU SelfTest execution.
CPU configured into safe mode
YES
SelfTest Done?
NO
350
CPU reset asserted
Read the SelfTest and system status
registers.
Retrieve state of CPU and Registers
and continue Application Software.
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8.3
STC Test Coverage and Duration
The test coverage and number of test execution cycles (STCCLK) for each test interval when the device is
running at HCLK = 180 MHz, VCLK = 90 MHz, and STCCLK = 90 MHz are shown in Table 8-1.
Table 8-1. STC Test Coverage and Duration
Intervals
Test Coverage (%)
Test Time (Cycles)
0
0
0
Test Time (µs)
0
1
62.13
1365
15.17
2
70.09
2730
30.33
3
74.49
4095
45.50
4
77.28
5460
60.67
5
79.28
6825
75.83
6
80.90
8190
91.00
7
82.02
9555
106.17
8
83.10
10920
121.33
9
84.08
12285
136.50
10
84.87
13650
151.67
11
85.59
15015
166.83
12
86.11
16380
182.00
13
86.67
17745
197.17
14
87.16
19110
212.33
15
87.61
20475
227.50
16
87.98
21840
242.67
17
88.38
23205
257.83
18
88.69
24570
273.00
19
88.98
25935
288.17
20
89.28
27300
303.33
21
89.50
28665
318.50
22
89.76
30030
333.67
23
90.01
31395
348.83
24
90.21
32760
364.00
Table 8-2 gives the typical STC execution times for 24 intervals at different clock rates.
Table 8-2. Typical STC Execution Times
Number of Intervals
@ HCLK = 180 MHz
VCLK = 90 MHz
STCCLK = 90 MHz
@ HCLK = 100 MHz
VCLK = 100 MHz
STCCLK = 50MHz
@ HCLK = 160 MHz
VCLK = 80 MHz
STCCLK = 80 MHz
24
364 µs
655.20 µs
409.50 µs
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STC Control Registers
STC control registers are accessed through Peripheral Bus (VBUSP) interface. Read and write access in
8, 16, and 32 bit are supported. The base address for the control registers is FFFF E600h.
NOTE: In suspend mode, all registers can be written irrespective of user or privilege mode.
Table 8-3. STC Control Registers
352
Offset
Acronym
Register Description
00h
STCGCR0
STC Global Control Register 0
Section 8.4.1
Section
04h
STCGCR1
STC Global Control Register 1
Section 8.4.2
08h
STCTPR
Self-Test Run Timeout Counter Preload Register
Section 8.4.3
0Ch
STC_CADDR
STC Current ROM Address Register
Section 8.4.4
10h
STCCICR
STC Current Interval Count Register
Section 8.4.5
14h
STCGSTAT
Self-Test Global Status Register
Section 8.4.6
18h
STCFSTAT
Self-Test Fail Status Register
Section 8.4.7
1Ch
CPU1_CURMISR3
CPU1 Current MISR Register
Section 8.4.8
20h
CPU1_CURMISR2
CPU1 Current MISR Register
Section 8.4.8
24h
CPU1_CURMISR1
CPU1 Current MISR Register
Section 8.4.8
28h
CPU1_CURMISR0
CPU1 Current MISR Register
Section 8.4.8
2Ch
CPU2_CURMISR3
CPU2 Current MISR Register
Section 8.4.9
30h
CPU2_CURMISR2
CPU2 Current MISR Register
Section 8.4.9
34h
CPU2_CURMISR1
CPU2 Current MISR Register
Section 8.4.9
38h
CPU2_CURMISR0
CPU2 Current MISR Register
Section 8.4.9
3Ch
STCSCSCR
Signature Compare Self-Check Register
Section 8.4.10
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8.4.1 STC Global Control Register 0 (STCGCR0)
This register is described in Figure 8-3 and Table 8-4.
Figure 8-3. STC Global Control Register 0 (STCGCR0) [offset = 00]
31
16
INTCOUNT
R/W-1
15
1
0
Reserved
RS_CNT
R-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 8-4. STC Global Control Register 0 (STCGCR0) Field Descriptions
Bit
31-16
Field
Value
INTCOUNT
Description
Number of intervals of self-test run
This register specifies the number of intervals to run for the self-test run. This corresponds to the
number of intervals to be ran from the value reflected in the current interval counter.
15-1
Reserved
0
RS_CNT
0
Read returns 0. Writes have no effect.
Restart or Continue
This bit specifies whether to continue the run from next interval onwards or to restart from interval
0. This bit gets reset after the completion of a self-test run.
0
Continue STC run from the previous interval.
1
Restart STC run from interval 0.
NOTE: On a power-on reset or system reset, this register gets reset to its default values.
8.4.2 STC Global Control Register 1 (STCGCR1)
This register is described in Figure 8-4 and Table 8-5.
Figure 8-4. STC Global Control Register 1 (STCGCR1) [offset = 04h]
31
16
Reserved
R-0
15
4
3
0
Reserved
STC_ENA
R-0
R/WP-5h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after nPORST (power-on reset) or System reset
Table 8-5. STC Global Control Register 1 (STCGCR1) Field Descriptions
Bit
Field
31-4
Reserved
3-0
STC_ENA
Value
0
Description
Read returns 0. Writes have no effect.
Self-test run enable key
Ah
Self-test run is enabled.
All Others
Self-test run is disabled.
NOTE: On a power-on reset or system reset, this register resets to its default values. Also, this
register automatically resets to its default values at the completion of a self-test run.
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8.4.3 Self-Test Run Timeout Counter Preload Register (STCTPR)
This register is described in Figure 8-5 and Table 8-6.
Figure 8-5. Self-Test Run Timeout Counter Preload Register (STCTPR) [offset = 08h]
31
16
RTOD
R/WP-FFFFh
15
0
RTOD
R/WP-FFFFh
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after nPORST (power-on reset) or System reset
Table 8-6. Self-Test Run Timeout Counter Preload Register (STCTPR)
Bit
Field
Description
31-0
RTOD
Self-test timeout count preload
This register contains the total number of VBUS clock cycles it will take before an self-test timeout error
(TO_ERR) will be triggered after the initiation of the self-test run. This is a fail safe feature to prevent the
device from hanging up due to a run away test during the self-test.
The preload count value gets loaded into the self-test time out down counter whenever a self-test run is
initiated (STC_KEY is enabled) and gets disabled on completion of a self-test run.
NOTE: On a power-on reset or system reset, this register gets reset to its default values.
8.4.4 STC Current ROM Address Register (STC_CADDR)
This register is described in Figure 8-6 and Table 8-7.
Figure 8-6. STC Current ROM Address Register (STC_CADDR) [offset = 0Ch]
31
16
ADDR
R-0
15
0
ADDR
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after nPORST (power-on reset) or System reset
Table 8-7. STC Current ROM Address Register (STC_CADDR) Field Descriptions
Bit
Field
Description
31-0
ADDR
Current ROM Address
This register reflects the current ROM address (for micro code load) which is the current value of the STC
program counter.
NOTE: When the RS_CNT bit in STCGCR0 is set to a 1 on the start of a self-test run, or on a
power-on reset or system reset, this register resets to all zeroes.
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8.4.5 STC Current Interval Count Register (STCCICR)
This register is described in Figure 8-7 and Table 8-8.
Figure 8-7. STC Current Interval Count Register (STCCICR) [offset = 10h]
31
16
Reserved
R-0
15
0
N
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-8. STC Current Interval Count Register (STCCICR) Field Descriptions
Bit
Field
31-16
Reserved
15-0
N
Value
0
Description
Read returns 0. Writes have no effect.
Interval Number
This specifies the last executed interval number.
NOTE: When the RS_CNT bit in STCGCR0 is set to a 1 or on a power-on reset, the current interval
counter resets to the default value.
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8.4.6 Self-Test Global Status Register (STCGSTAT)
This register is described in Figure 8-8 and Table 8-9.
Figure 8-8. Self-Test Global Status Register (STCGSTAT) [offset = 14h]
31
8
Reserved
R-0
1
0
Reserved
2
TEST_FAIL
TEST_DONE
R-0
R/WP-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 8-9. Self-Test Global Status Register (STCGSTAT) Field Descriptions
Bit
31-2
1
0
Field
Reserved
Value
0
TEST_FAIL
Description
Read returns 0. Writes have no effect.
Test Fail
0
Self-test run has not failed.
1
Self-test run has failed.
TEST_DONE
Test Done
0
Not completed.
1
Self-test run completed.
The test done flag is set to a 1 for any of the following conditions:
1.
2.
3.
When the STC run is complete without any failure
When a failure occurs on a STC run
When a timeout failure occurs
Reset is generated to the CPU on which the STC run is being performed when TEST_DONE goes
high (the test is completed).
NOTE: The two status bits can be cleared to their default values on a write of 1 to the bits.
Additionally when the STC_ENA key is written from a disabled state to enabled state, the two
status flags get cleared to their default values. This register gets reset to its default value
with power-on reset assertion.
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8.4.7 Self-Test Fail Status Register (STCFSTAT)
This register is described in Figure 8-9 and Table 8-10.
Figure 8-9. Self-Test Fail Status Register (STCFSTAT) [offset = 18h]
31
8
Reserved
R-0
2
1
0
Reserved
3
TO_ERR
CPU2_FAIL
CPU1_FAIL
R-0
R/WP-0
R/WP-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after nPORST (power-on reset) or System reset
Table 8-10. Self-Test Fail Status Register (STCFSTAT) Field Descriptions
Bit
Field
31-3
Reserved
2
TO_ERR
1
0
Value
0
Description
Read returns 0. Writes have no effect.
Timeout Error
0
No time out error occurred.
1
Self-test run failed due to a timeout error.
CPU2_FAIL
CPU2 failure info
0
No MISR mismatch for CPU2.
1
Self-test run failed due to MISR mismatch for CPU2.
CPU1_FAIL
CPU1 failure info
0
No MISR mismatch for CPU1.
1
Self-test run failed due to MISR mismatch for CPU1.
NOTE: The three status bits can be cleared to their default values on a write of 1 to the bits.
Additionally when the STC_ENA key in STCGCR1 is written from a disabled state to an
enabled state, the three status bits get cleared to their default values. This register gets reset
to its default value with power-on reset assertion.
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8.4.8 CPU1 Current MISR Register (CPU1_CURMISR[3:0])
This register is described in Figure 8-10 through Figure 8-13 and Table 8-11.
Figure 8-10. CPU1 Current MISR Register (CPU1_CURMISR3) [offset = 1Ch]
31
16
MISR[31:16]
R-0
15
0
MISR[15:0]
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 8-11. CPU1 Current MISR Register (CPU1_CURMISR2) [offset = 20h]
31
16
MISR[63:48]
R-0
15
0
MISR[47:32]
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 8-12. CPU1 Current MISR Register (CPU1_CURMISR1) [offset = 24h]
31
16
MISR[95:80]
R-0
15
0
MISR[79:64]
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 8-13. CPU1 Current MISR Register (CPU1_CURMISR0) [offset = 28h]
31
16
MISR[127:112]
R-0
15
0
MISR[111:96]
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-11. CPU1 Current MISR Register (CPU1_CURMISR[3:0]) Field Descriptions
Bit
Field
Description
127-0
MISR
MISR data from CPU1
This register contains the MISR data from the CPU1 for the most recent interval. This value is compared
with the GOLDEN MISR value copied from ROM.
NOTE: This register gets reset to its default value with power-on or system reset assertion.
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8.4.9 CPU2_CURMISR[3:0] (CPU2 Current MISR Register)
This register is described in Figure 8-14 through Figure 8-17 and Table 8-12.
Figure 8-14. CPU2 Current MISR Register (CPU2_CURMISR3) [offset = 2Ch]
31
16
MISR[31:16]
R-0
15
0
MISR[15:0]
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 8-15. CPU2 Current MISR Register (CPU2_CURMISR2) [offset = 30h]
31
16
MISR[63:48]
R-0
15
0
MISR[47:32]
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 8-16. CPU2 Current MISR Register (CPU2_CURMISR1) [offset = 34h]
31
16
MISR[95:80]
R-0
15
0
MISR[79:64]
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 8-17. CPU2 Current MISR Register (CPU2_CURMISR0) [offset = 38h]
31
16
MISR[127:112]
R-0
15
0
MISR[111:96]
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-12. CPU2 Current MISR Register (CPU2_CURMISR[3:0]) Field Descriptions
Bit
Field
Description
127-0
MISR
MISR data from CPU2
This register contains the MISR data from the CPU2 for the most recent interval. This value is compared
with the GOLDEN MISR value copied from ROM.
NOTE: This register gets reset to its default value with power-on or system reset assertion.
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8.4.10 STCSCSCR (Signature Compare Self-Check Register)
This register is described in Figure 8-18. This register is used to enable the self-check feature of the CPU
Self-Test Controller's (STC) signature compare logic. Self-check can only be done for the STC interval 0
by setting the RS_CNT bit in STCGCR0 to 1 to restart the self-test. The STC run will fail for signature
miss-compare, provided the signature compare logic is operating correctly. To proceed with regular CPU
self-test, STCSCSCR should be programmed to disable the self-check feature and clear the RS_CNT bit
in STCGCR0 to 0. This register gets reset to its default value with any system reset assertion.
Figure 8-18. Signature Compare Self-Check Register (STCSCSCR) [offset = 3Ch]
31
16
Reserved
R-0
15
5
4
3
0
Reserved
FAULT_INS
SELF_CHECK_KEY
R-0
R/WP-0
R/WP-5h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after nPORST (power-on reset) or System reset
Table 8-13. Signature Compare Self-Check Regsiter (STCSCSCR) Field Descriptions
Bit
31-5
4
3-0
Field
Value
Reserved
Reads return zeros, writes have no effect
FAULT_INS
Enable / Disable fault insertion.
0
No fault is inserted.
1
Insert stuck-at-fault inside CPU so that STC signature compare will fail.
SELF_CHECK_KEY
Signature compare logic self-check enable key
Ah
Any other
value
360
Description
Signature compare logic self-check is enabled. This allows a fault to be inserted using
the FAULT_INS field.
Signature compare logic self-check is disabled The FAULT_INS field has no effect in this
case.
CPU Self-Test Controller (STC) Module
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8.5
STC Configuration Example
The following examples assume that the PLL is locked and selected as the system clock source with
HCLK = 180 MHz and VCLK = 90 MHz.
8.5.1 Example 1: Self-Test Run for 24 Interval
This example explains the configurations for running STC Test for maximum Test Intervals 24.
1. Maximum STC clock rate support at 180 MHz HCLK is 90 MHz. Divide HCLK by 2 to achieve this
clock rate. STCCLKDIV[26:24] register in the secondary system module frame at location
0xFFFF E108 is used.
STCCLKDIV[26:24] = 1
2. Clear CPU_RST status bit in the System Exception Status Register in the system module.
SYSESR[5] = 1
3. Configure the test interval count in STC module.
STCGCR0[31:16] = 24
4. Configure self-test run time out counter preload register.
STCTPR[31:0] = 0xFFFFFFFF
5. Enable CPU self-test.
STCGCR1[3:0]= 0xA
6. Perform a context save of CPU state and configuration registers that get reset on CPU reset.
7. Put the CPU in idle mode by executing the CPU idle instruction.
asm(“ WFI”)
8. Upon CPU reset, verify the CPU_RST status bit in the System Exception Status Register is set. This
also verifies that no other resets occurred during the self-test.
SYSESR[5] == 1
9. Check the STCGSTAT register for the self-test status.
Check TEST_DONE bit before evaluating TEST_FAIL bit.
If TEST_DONE = 0 the self-test is not completed. restart the STC test by going to Step 5.
If (TEST_DONE = 1 and TEST_FAIL = 1) the self-test is completed and Failed.
• Read STC Fail Status Register STCFSTAT[2:0] to identify the type of Failure (Timeout, CPU1 fail,
CPU2 fail).
In case there is no failure (TEST_DONE = 1 and TEST_FAIL = 0), the CPU self-test is completed
successfully.
• Recover the CPU status, configuration registers and continue the application software.
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CPU Compare Module for Cortex-R4F (CCM-R4F)
This chapter describes the CPU compare module for Cortex-R4F (CCM-R4F). This device implements two
instances of the Cortex-R4F CPU which are running in lock step to detect faults which may result in
unsafe operating conditions. The CCM-R4F detects faults and signals them to an error signaling module
(ESM).
NOTE: In general, R4F is used when referencing the Cortex CPU used in the Hercules family of
devices; however, the floating-point functionality is a device-specific option and may not be
included in some devices. Consult your device-specific datasheet to determine which core is
included on your specific device being used.
362
Topic
...........................................................................................................................
9.1
9.2
9.3
9.4
Main Features ..................................................................................................
Block Diagram..................................................................................................
Module Operation .............................................................................................
CCM-R4F Control Registers ...............................................................................
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9.1
Main Features
Safety-critical applications require run-time detection of faults in the Central Processing Unit (CPU). For
this purpose, the CPU Compare Module for Cortex-R4F (CCM-R4F) compares the core compare bus
outputs of two Cortex-R4F CPUs running in a 1oo1D (one-out-of-one, with diagnostics) lockstep
configuration. Any difference in the core compare bus outputs of the CPUs is flagged as an error. For
diagnostic purposes, the CCM-R4F also incorporates a self-test capability to allow for boot time checking
of hardware faults within the CCM-R4F itself.
The main features of the CCM-R4F are:
• run-time detection of faults
• self-test capability
• error forcing capability
9.2
Block Diagram
Figure 9-1 shows the interconnection diagram of the CCM-R4F with the two Cortex-R4F CPUs. The core
compare bus outputs of the CPUs are compared in the CCM-R4F. To avoid common mode impacts, the
signals of the CPUs to be compared are temporally diverse. The output signals of the master CPU are
delayed 2 cycles while the input signals of checker CPU are delayed 2 cycles. The CCM-R4F is constantly
comparing about 900 signals from each of the two CPUs. These signals include the address, data and
control signals from the flash and RAM TCMs and from the AXI peripheral bus. An internal register or ALU
error will be flagged as a mis-compare when the faulty value is stored, used as an index, or causes a
change in program execution.
Figure 9-1. Block Diagram
CCM-R4F
2 cycles delay
CCM-R4F
compare
CPU1CLK
CPU 1
Master CPU
compare
error
ESM
(Error
Signaling
Module)
CPU 2
Checker CPU
2 cycles delay
CPU2CLK
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Module Operation
The CCM-R4F compares the core compare bus outputs of the master and checker Cortex-R4F CPUs on
the microcontroller and signals an error on any mismatch. This comparison is started 6 CPU clock cycles
after the CPU comes out of reset to ensure that CPU output signals have propagated to a known value
after reset. Once comparison is started, the CCM module continues to monitor the outputs of two CPUs
without any software intervention. Upon an error software needs to handle it.
The CCM-R4F can run in one of the following four operating modes:
1. 1oo1D lock step
2. self-test
3. error forcing
4. self-test error forcing
The operating mode can be selected by writing a dedicated key to the key register (MKEY).
9.3.1 1oo1D Lock Step Mode
This is the default mode on start-up.
In lock step mode, the compare bus output signals of both CPUs are compared. A difference in the CPU
compare bus outputs is indicated by signaling an error to the ESM which sets the error flag “CCM-R4F compare”.
NOTE: The CPU compare error asserts “CCM-R4F self-test error” flag as well. By doing this, the
CPU compare error has two paths (“CCM-R4F - compare” and “CCM-R4F self-test error”
flag) to the ESM, so that even if one of the paths fails, the error is still propagated to the
ESM.
Not all internal registers of the Cortex-R4F CPU have fixed values upon reset. To avoid an erroneous
CCMR4F compare error, the application software needs to ensure that the CPU registers of both CPUs
are initialized with the same values before the registers are used, including function calls where the
register values are pushed onto the stack.
9.3.2 Self-Test Mode
In self-test mode, the CCM-R4F checks itself for faults. During self-test, the compare error module output
signal is deactivated. Any fault detected inside the CCM-R4F will be flagged by ESM error “CCM-R4F self-test”.
In self-test mode, the CCM-R4F automatically generates test patterns to look for any hardware faults. If a
fault is detected, then a self-test error flag is set, a self-test error signal is asserted and sent to the ESM,
and the self-test is terminated immediately. If no fault is found during self-test, the self-test complete flag is
set. In both cases, the CCM-R4F remains in self-test mode after the test has been terminated or
completed, and the application needs to switch the CCM-R4F mode by writing another key to the mode
key register (MKEY). During the self-test operation, the compare error signal output to the ESM is inactive
irrespective of the compare result.
There are two types of patterns generated by CCM-R4F during self-test mode:
i. Compare Match Test
ii. Compare Mismatch Test
CCM-R4F first generates Compare Match Test patterns, followed by Compare Mismatch Test patterns.
Each test pattern is applied on both CPU signal inputs of the CCM-R4F’s compare block and clocked for
one cycle. The duration of self-test is 3615 CPU clock cycles (GCLK).
NOTE: During self-test, both CPUs can execute normally, but the compare logic will not be checking
any CPU signals. Also during self-test, only the compare unit logic is tested and not the
memory mapped register controls for the CCM-R4F. The self-test is not interruptible.
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9.3.2.1
Compare Match Test
During the Compare Match Test, there are four different test patterns generated to stimulate the CCMR4F. An identical vector is applied to both input ports at the same time expecting a compare match. These
patterns cause the self-test logic to exercise every CPU compare bus output signal in parallel. If the
compare unit produces a compare mismatch then the self-test error flag is set, the self-test error signal is
generated, and the Compare Match Test is terminated.
The four test patterns used for the Compare Match Test are:
• All 1s on both CPU signal ports
• All 0s on both CPU signal ports
• 0xAs on both CPU signal ports
• 0x5s on both CPU signal ports
These four test patterns will take four clock cycles to complete. illustrates the sequence of Compare Match
Test.
Table 9-1. Compare Match Test Sequence
CPU 1 Signal Position
9.3.2.2
CPU 2 Signal Position
Cycle
n:8
7
6
5
4
3
2
1
0
n:8
7
6
5
4
3
2
1
0
1s
1
1
1
1
1
1
1
1
1s
1
1
1
1
1
1
1
1
0
0s
0
0
0
0
0
0
0
0
0s
0
0
0
0
0
0
0
0
1
0xA
1
0
1
0
1
0
1
0
0xA
1
0
1
0
1
0
1
0
2
0x5
0
1
0
1
0
1
0
1
0x5
0
1
0
1
0
1
0
1
3
Compare Mismatch Test
During the Compare Mismatch Test, the number of test patterns is equal to twice the number of CPU
output signals to compare in lock step mode. An all 1s vector is applied to the CCM-R4F’s CPU1 input
port and the same pattern is also applied to the CCM-R4F’s CPU2 input port but with one bit flipped
starting from signal position 0. The un-equal vector will cause the CCM-R4F to expect a compare
mismatch at signal position 0, if the CCM-R4F logic is working correctly. If, however, the CCM-R4F logic
reports a compare match, the self-test error flag is set, the self-test error signal is asserted, and the
Compare Mismatch Test is terminated.
This Compare Mismatch Test algorithm repeats in a domino fashion with the next signal position flipped
while forcing all other signals to logic level 1. This sequence is repeated until every single signal position
is verified on both CPU signal ports.
The Compare Mismatch Test is terminated if the CCM-R4F reports a compare match versus the expected
compare mismatch. This test ensures that the compare unit is able to detect a mismatch on every CPU
signal being compared. Table 9-2 illustrates the sequence of Compare Mismatch Test. There is no error
signal is sent to ESM if the expected errors are seen with each pattern.
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Table 9-2. Compare Mismatch Test Sequence
CPU 1 Signal Position
n
n-1:8
CPU 2 Signal Position
7
6
5
4
3
2
1
0
n
n-1:8
7
6
5
4
3
2
1
0
Cycle
1
1
1s
1
1
1
1
1
1
1
1
1
1
1s
1
1
1
1
1
1
1
0
0
1
1
1s
1
1
1
1
1
1
1
1
1
1
1s
1
1
1
1
1
1
0
1
1
1
1
1s
1
1
1
1
1
1
1
1
1
1
1s
1
1
1
1
1
0
1
1
2
1
1
1s
1
1
1
1
1
1
1
1
1
1
1s
1
1
1
1
0
1
1
1
3
1
1
1s
1
1
1
1
1
1
1
1
1
0
1s
1
1
1
1
1
1
1
1
n-1
1
1
1s
1
1
1
1
1
1
1
1
0
1
1s
1
1
1
1
1
1
1
1
n
1
1
1s
1
1
1
1
1
1
1
0
1
1
1s
1
1
1
1
1
1
1
1
n+1
1
1
1s
1
1
1
1
1
1
0
1
1
1
1s
1
1
1
1
1
1
1
1
n+2
1
1
1s
1
1
1
1
1
0
1
1
1
1
1s
1
1
1
1
1
1
1
1
n+3
1
1
1s
1
1
1
1
0
1
1
1
1
1
1s
1
1
1
1
1
1
1
1
n+4
1
0
1s
1
1
1
1
1
1
1
1
1
1
1s
1
1
1
1
1
1
1
1
2n-1
0
1
1s
1
1
1
1
1
1
1
1
1
1
1s
1
1
1
1
1
1
1
1
2n
::
::
9.3.3 Error Forcing Mode
In error forcing mode, a test pattern is applied to the CPU related inputs of the CCM-R4F compare logic to
force an error in the compare error output signal of the compare unit. The ESM error flag “CCM-R4F compare” is expected after the error forcing mode completes. As a side effect, the “CCM-R4F self-test
error” flag is also asserted whenever the CPU compare error is asserted.
Error forcing mode is similar to the Compare Mismatch Test operation of self-test mode in which an unequal vector is applied to the CCM-R4F CPU signal ports. The error forcing mode forces the compare
mismatch to actually assert the compare error output signal. This ensures that faults in the path between
CCM-R4F and ESM is detected.
Only one hardcoded test pattern is applied into CCM-R4F during error forcing mode. A repeated 0x5
pattern is applied to CPU1 signal port of CCM-R4F input while a repeated 0xA pattern is applied to the
CPU2 signal port of CCM-R4F input. The error forcing mode takes one cycle to complete. Hence, the
failing signature is presented for one clock cycle. After that, the mode is automatically switched to lock
step mode. The key register (MKEY) will indicate the lock step key mode once it is switched to lock step
mode. During the one cycle required by the error forcing test, the CPU output signals are not compared.
User should expect the ESM to trigger a response (report the CCM-R4F fail). If no error is detected by
ESM, then a hardware fault is present.
9.3.4 Self-Test Error Forcing Mode
In self-test error forcing mode, an error is forced at the self-test error signal. The compare unit is still
running in lockstep mode and the key is switched to lockstep after one clock cycle. The ESM error flag
“CCM-R4F - self-test” is expected after the self-test error forcing mode completes. Once the expected
errors are seen, the application can clean the error through ESM module.
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9.3.5 Operation During CPU Debug Mode
Certain debug operations place the CPU in a halting debug state where the code execution is halted.
Because halting debug events are asynchronous, there is a possibility for the debug requests to cause
loss of lockstep. CCM-R4F will disable upon detection of halting debug requests. Core compare error will
not be generated and flags will not update. A CPU reset is needed to ensure the CPUs are again in
lockstep and will also re-enable the CCM-R4F.
9.4
CCM-R4F Control Registers
Table 9-3 lists the CCM-R4F registers. Each register begins on a 32-bit word boundary. The registers
support 32-bit, 16-bit and 8-bit accesses. The base address for the control registers is FFFF F600h.
Table 9-3. CCM-R4F Control Registers
Offset
Acronym
Register Description
00h
CCMSR
CCM-R4F Status Register
Section 9.4.1
04h
CCMKEYR
CCM-R4F Key Register
Section 9.4.2
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9.4.1 CCM-R4F Status Register (CCMSR)
Figure 9-2. CCM-R4F Status Register (CCMSR) (Address = FFFF F600h)
31
17
15
16
Reserved
CPME
R-0
R/WPC-0
9
8
7
2
1
0
Reserved
STC
Reserved
STET
STE
R-0
R-0
R-0
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; C = Clear; WP = Write in Privileged mode only; -n = value after reset
Table 9-4. CCM-R4F Status Register (CCMSR) Field Descriptions
Bit
31-17
16
Field
Reserved
Value
0
CMPE
(1)
Description
Reads return zeros and writes have no effect.
Compare Error
Read in User and Privileged mode. Write in Privileged mode only.
0
Read: CPU signals are identical.
Write: Leaves the bit unchanged.
1
Read: CPU signal compare mismatch.
Write: Clears the bit.
15-9
8
Reserved
0
STC
Reads return zeros and writes have no effect.
Self-test Complete
Note: This bit is always 0 when not in self-test mode. Once set, switching from self-test mode to
other modes will clear this bit.
Read/Write in User and Privileged mode.
0
Read: Self-test on-going if self-test mode is entered.
Write: Writes have no effect.
1
Read: Self-test is complete.
Write: Writes have no effect.
7-2
1
Reserved
0
STET
Reads return zeros and writes have no effect.
Self-test Error Type
Read/Write in User and Privileged mode.
0
Read: Self-test failed during Compare Match Test if STE = 1.
Write: Writes have no effect.
1
Read: Self-test failed during Compare Mismatch Test if STE = 1.
Write: Writes have no effect.
0
STE
Self-test Error
Note: This bit gets updated when the self-test is complete or an error is detected.
Read/Write in User and Privileged mode.
0
Read: Self-test passed.
Write: Writes have no effect.
1
Read: Self-test failed.
Write: Writes have no effect.
(1)
368
The contents of this register should be interpreted in context of what test was selected. That is what mode is CCM operating in.
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9.4.2 CCM-R4F Key Register (CCMKEYR)
Figure 9-3. CCM-R4F Key Register (CCMKEYR) (Address = FFFF F604h)
31
16
Reserved
R-0
15
4
3
0
Reserved
MKEY
R-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privileged mode only; -n = value after reset
Table 9-5. CCM-R4F Key Register (CCMKEYR) Field Descriptions
Bit
Field
31-4
Reserved
3-0
MKEY
Value
0
Description
Reads return to zeros and writes have no effect.
Mode Key
Read in User and Privileged mode. Write in Privileged mode only.
0
Read: Returns current value of the MKEY.
Write: Lockstep mode.
6h
Read: Returns current value of the MKEY.
Write: Self-test mode.
9h
Read: Returns current value of the MKEY.
Write: Error Forcing mode.
Fh
Read: Returns current value of the MKEY.
Write: Self-test Error Forcing mode.
Other
values
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Note: It is recommended to not write any other key combinations. Invalid keys will result in
switching operation to lockstep mode.
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Chapter 10
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Oscillator and PLL
This chapter describes the oscillator and PLL clock source paths for the device.
Topic
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
370
...........................................................................................................................
Introduction .....................................................................................................
Quick Start.......................................................................................................
Oscillator .........................................................................................................
Low-Power Oscillator and Clock Detect (LPOCLKDET) .........................................
PLL .................................................................................................................
PLL Control Registers .......................................................................................
Phase-Locked Loop Theory of Operation ............................................................
Programming Example ......................................................................................
Oscillator and PLL
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373
375
378
388
392
394
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10.1 Introduction
This chapter provides an overview of the oscillator and PLL clock source paths for the device.
The oscillator macro will pass a signal driven into the OSCIN pin to clock source 0 that is the device
default clock source on reset. When a crystal or resonator with appropriate load circuitry is connected to
OSCIN and OSCOUT, the oscillator macro drives the crystal/resonator to generate the input waveform. In
addition to being directly usable as clock source 0, the oscillator clock is the input to the PLL.
The oscillator frequency is continuously monitored by a dedicated clock detect circuit. If the frequency falls
out of a fixed range, the clock detect switches the clock from the oscillator to an internally generated, freerunning frequency (generated by the low-power oscillator (LPO)).
The phase lock loop (PLL), a circuit in the microcontroller, is used to multiply the input frequency to some
higher (device operation) frequency. This frequency synthesis is useful for generating higher frequencies
than can be conveniently achieved with an external crystal or resonator. Additionally, the PLL allows the
flexibility to be able to synthesize one of multiple frequency options from a given crystal or resonator.
Frequency modulation can be superimposed on the synthesized frequency. The modulation provides a
means to reduce the impact of electromagnetic radiation from the device; this reduction in measured
radiation can be useful in sensitive applications.
10.1.1 Features
The main features of the source clock path are:
• The oscillator may drive a crystal/resonator or be driven from an external source
• The clock detect provides continuous monitoring of the oscillator frequency and provides an automatic
switch over to a free-running clock in case of oscillator failure.
• The FM-PLL module can be operated in either modulation or non-modulation mode.
• The phase-frequency detector assures lock to the fundamental reference frequency.
•
•
•
f PLL =
f O S C IN
NF
´
NR
OD ´ R
(1)
– Configurable prescale divider (NR) for the input clock
– Configurable multiplier (NF)
– Configurable postscale dividers (OD, R)
The PLL may be used with modulation enabled.
– Configurable modulation frequency (NS)
– Configurable modulation depth (NV)
The slip control circuitry provides flexible response to a PLL failure (slip) including reset or automatic
switch over to oscillator.
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10.2 Quick Start
The purpose of this section is to provide an overview of how to configure the oscillator and PLL clock
paths on power-up. More detailed descriptions are presented in later sections. Figure 10-1 shows the
oscillator and PLL clock paths.
Figure 10-1. Clock Path From Oscillator Through PLL To Device
load
capacitors
osc
device pin
CLKDET
PLL1
OSCILLATOR
slip
PLL2
LPO
Clock source numbering can be
found in the device data sheet.
crystal
device pin
KELVIN_GND
While power-on reset is asserted (low), the oscillator and low-power oscillator (LPO) are enabled and
start-up by default. After power-on reset is released to a high level, the clock detect circuit (CLKDET)
begins to monitor the oscillator. If the oscillator is within a valid range, the oscillator becomes the default
clock for the device as it exits reset; if the oscillator is not within a valid range, the clock detect selects the
high-frequency low-power oscillator as the default clock for the device.
The low-power oscillator has a wide frequency range which also creates a large valid window for the clock
detect; in order to refine the clock detect window, the low-power oscillator can be trimmed. The initial trim
value is stored in one-time programmable section of the flash memory, address 0xF008_01B4. Bits 31:16
of this word contain a 16 bit value that may be programmed into LPOMONCTL(15:0) in order to initialize
the trim for both HF LPO and LF LPO. Software should read the initial trim values from flash and write
them to the control register.
The PLL is disabled by default on power-up. The PLL control registers (PLLCTL1 and PLLCTL2) must be
configured to set the desired output frequency. Then, the system PLL may be enabled (CSDISCLR.1).
Similarly, the second PLL must be configured in PLLCTL3 and enabled (CSDISCLR.6). Each PLL has a
valid bit that indicates the PLL is locked (CLKSRnV bit in the Clock Source Valid Status Register
(CSVSTAT) of the System and Peripheral Control Registers).
Prior to selecting the PLL clock as the source for a clock domain (for example, GCLK, HCLK, VCLKA1),
the domain and modules on the domain must be configured to accept the new frequency. An example of a
module that should be configured prior to selecting the PLL as clock source for GCLK and HCLK is the
memory wrapper to insure that access times are maintained correctly.
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10.3 Oscillator
The clock generation path through the PLL begins with the oscillator. The oscillator consists of three
separate pads -- OSCIN, OSCOUT, and Kelvin_GND (see Figure 10-2).
Figure 10-2. Clock Generation Path
load
capacitors
OSCIN
OSCILLATOR
crystal
OSCOUT
KELVIN_GND
The oscillator is responsible for two independent functions:
1. The oscillator is responsible for generating positive feedback in the external crystal/resonator with
appropriate load and tank circuitry. At start-up, the oscillator amplifies random noise. The external
circuitry acts like a band-pass and selects the crystal/resonator frequency to provide as positive
feedback into the amplifier. The positive feedback increases the amplitude of the output waveform into
the crystal/resonator (and the load circuitry), and the voltage waveform shows an envelope of
increasing amplitude. The oscillator can drive a crystal frequency that is within the data sheet range
tc(OSC).
Looking at the input waveform into OSCIN, the voltage waveform is an AC-coupled, filtered version of
the OSCOUT waveform. The band-pass functionality of the crystal/resonator removes distortion from
the OSCOUT waveform, leaving a sinusoidal input waveform.
NOTE: Vendor Validation of Resonators/Crystals
The crystal is a very tight bandpass filter while a resonator is a somewhat wider bandpass.
The load circuitry pulls the center frequency of the bandpass.
Texas Instruments strongly encourages each customer to submit samples of the device to
the resonator/crystal vendor for validation. The vendor is equipped to determine what load
capacitances will best tune their resonator/crystal to the microcontroller device for optimum
start-up and operation over temperature and voltage extremes. The vendor also factors in
margins for variations in the microcontroller process.
2. The oscillator is also responsible for squaring-up the input waveform. This squaring-up converts the
sinusoid into a square wave at the core logic levels. The input path limits the input frequency range as
a low-pass filter with a cutoff frequency.
The oscillator has a frequency range that is determined by the driving capability of external
crystals/resonators (feedback path). If a clock is driven directly into the oscillator, then the feedback
path is not relevant and the frequency range is determined solely by the forward path (which typically
allows a higher frequency); the device can support inputs within the data sheet range tc(OSC_Sqr).
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10.3.1 Oscillator Implementation
The oscillator operates at 3.3V and uses a constant current source to drive current onto the OSCOUT
node. An internal transistor shunts the current (and current from the external circuitry) to GND. This
current steering drives the voltage waveform on OSCOUT.
Figure 10-3. Oscillator Implementation
R
OSCOUT
OSCIN
10.3.2 Oscillator Enable
The oscillator is enabled asynchronously when nPORRST is low.
The oscillator is enabled by clearing bit 0 in the Clock Source Disable Register (CSDIS) or setting bit 0 in
the Clock Source Disable Clear Register (CSDISCLR) of the System and Peripheral Control Registers.
The bit sends a start signal to the oscillator. Bit 0 of CSDIS is cleared to 0 by default on a system or
power-on reset so that the oscillator starts-up by default. After the oscillator swings at a high-enough
amplitude to pass an input clock into the core domain and nPORRST is released, 1024 oscillator periods
are counted before setting the CLKSR0V bit in the Clock Source Valid Status Register (CSVSTAT) of the
System and Peripheral Control Registers. The oscillator generates clock source 0 in the global clock
module (GCM).
10.3.3 Oscillator Disable
The clock sources (for example, OSC, PLL) are disabled by setting the appropriate bit in the Clock Source
Disable Register (CSDIS) or setting the appropriate bit in the Clock Source Disable Set Register
(CSDISSET) of the System and Peripheral Control Registers. These bits allow the clock source to disable
but do not force the behavior until the clock is no longer used as the source for a clock domain (for
example, GCLK, VCLK, VCLK2, RTICLK). The CLKSR0V bit in the Clock Source Valid Status Register
(CSVSTAT), of the System and Peripheral Control Registers, is cleared after clock disable is asserted
(which occurs after all clock domains are stopped).
The oscillator disable signal places the oscillator into a low-power state, disconnects the feedback (bias)
resistor between OSCIN and OSCOUT, and OSCIN is grounded.
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10.4 Low-Power Oscillator and Clock Detect (LPOCLKDET)
The low-power oscillator (LPO) is comprised of two oscillators -- HF LPO and LF LPO -- in a single macro.
The low-power oscillator and clock detect (LPOCLKDET) uses a relaxation oscillator to generate an
internal clock whose frequency is NOT tightly controlled. This frequency is used to monitor the oscillator
input frequency and is also available as an independent clock source in the GCM.
The LPO produces two frequencies:
• High-frequency low-power oscillator (HF LPO) with a nominal frequency of 9.6MHz and a range from
5.5MHz to 19.5MHz; the HF LPO generates clock source 5 in the GCM.
• Low-frequency low-power oscillator (LF LPO) with a nominal frequency of 85kHz; the LF LPO
generates clock source 4 in the GCM.
A single current source drives current onto a capacitor; when the voltage on the capacitor exceeds some
threshold, the clock toggles. The LPO uses a single current source and the two different comparators to
generate the HF LPO and LF LPO frequencies. The LPO is controlled by 4 different bit fields -CSDIS.(5:4), HFTRIM(4:0), LFTRIM(4:0), and BIASEN.
• CSDIS.5 enables/disables the comparator that generates HF LPO.
• CSDIS.4 enables/disables the comparator that generates LF LPO.
• The HF TRIM and LF TRIM bit fields vary the current into the comparator to independently trim the
HF LPO and LF LPO frequencies.
• BIAS ENABLE (LPOMONCTL.24) enables/disables the current source that drives the LPO.
10.4.1 Clock Detect
The LPO HF clock frequency is typically near 9.6MHz but ranges from 5.5MHz to 19.5MHz. The clock
detect establishes a window for the oscillator by:
OSCIN > HF LPOmin / 4
OSCIN / 4 < HF LPOmax
OSCIN > 5.5[MHz] / 4 = 1.375[MHz]
OSCIN < 4 × 19.5 = 78[MHz]
The clock detect circuit works by checking for a rising edge on one clock (oscillator or HF LPO) between
rising edges of the other clock. The result is that in addition to flagging incorrect, repeating frequencies,
the circuit also fails due to transient conditions.
The low end of the clock detect window ignores a transient low phase of at least 12 HF LPO cycles.
NOTE: Clock Detection of Oscillator MUST be Disabled Before Disabling HF LPO
The HF LPO frequency is the comparison frequency for the oscillator. The clock detection
must be disabled prior to disabling the HF LPO frequency.
If the clock detection is NOT disabled prior to disabling the HF LPO, the clock detect circuitry
will fail the oscillator as too fast (compared to the non-existent HF LPO). The clock detect
circuitry will switch to the non-existent clock, leaving the device without a valid clock.
10.4.2 Behavior on Oscillator Failure
If the oscillator frequency fails, the clock detects supplies:
• the HF LPO clock to GCM clock source 0 instead of the oscillator
• the HF LPO clock to GCM clock source 1 instead of the PLL
The HF LPO signal will be available as three different clock sources:
• GCM clock source 0 (replacing the oscillator)
• GCM clock source 1 (replacing the PLL)
• GCM clock source 5 as HF LPO
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The automatic switch-over from oscillator to HF LPO allows the application to execute at a reduced
frequency and respond to a problem with the external crystal/resonator. During and after an oscillator
failure, the oscillator CLKSRnV bit in the Clock Source Valid Status Register (CSVSTAT), of the System
and Peripheral Control Registers, is set along with the OSCFAIL flag in the Global Status Register
(GLBSTAT), of the System and Peripheral Control Registers.
It is useful to explicitly change the GHVSRC register, defining the current clock source for
GCLK/HCLK/VCLK domains, to the HF LPO after an oscillator failure.
When reset on oscillator failure is set, PLLCTL1.23 (ROF), the device responds to an oscillator failure by
generating a device reset.
10.4.3 Recovery from Oscillator Failure
If the oscillator fails, the clock detect switches the HF LPO frequency onto the oscillator source into the
GCM. The OSCFAIL flag in the Global Status Register (GLBSTAT), of the System and Peripheral Control
Registers, is also set.
The oscillator may be re-enabled (though if the failure was caused by a hard-fault, the re-enable will fail)
through the following procedure:
1. Switch all clock domains from the oscillator to the HF LPO (for example, GHVSRC uses HF LPO,
VCLKAn uses HF LPO or VCLK, and so on).
2. If the PLL is used, disable the PLL by setting the appropriate bit in the Clock Source Disable Set
Register (CSDISSET) of the System and Peripheral Control Registers.
3. Disable the oscillator by setting the appropriate bit in the Clock Source Disable Set Register
(CSDISSET). This action resets the clock detect and allows the oscillator to propagate through GCM
clock source 0.
4. Re-enable the oscillator by setting the appropriate bit in the Clock Source Disable Clear Register
(CSDISCLR) of the System and Peripheral Control Registers.
5. Clear the OSCFAIL flag in the Global Status Register (GLBSTAT) by writing a 1 to the bit. The PLL slip
bits may also be set on an oscillator failure. These can also be cleared.
6. Switch the clock domains back to the oscillator.
7. Re-enable the PLL by setting the appropriate bit in the Clock Source Disable Clear Register
(CSDISCLR).
NOTE: Clock Re-Enable Procedure Will Fail If Caused by a Hard Failure
Although it is possible to re-enable the oscillator after a failure, if the oscillator failure was
caused by a hard fault (for example, disconnected crystal/resonator terminal), the re-enable
process will fail.
10.4.4 LPOCLKDET Enable
The LPO is enabled by default while nPORRST is low. During this time, the current source initializes,
holding the relaxation oscillator in reset until initialized. After the current source releases the HF LPO and
the LF LPO, these clock frequencies slew to their final frequencies; the final frequency may be achieved
while nPORRST is active or after its release. After, nPORRST is released, the HF LPO Valid signal is set
32 HF LPO clock cycles later.
The clock detect is enabled once the oscillator and HF LPO are valid. Because an oscillator failure could
occur from reset, the clock detect logic must provide an override path. If the HF LPO is valid and the
oscillator is not valid, the clock detect circuitry will become active (overriding the oscillator invalid signal)
after 16K LF LPO cycles (about 200ms).
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10.4.5 LPOCLKDET Disable
10.4.5.1 Disable Clock Detect
It is possible to disable the clock detect circuitry. For protection, this clock detect disable employs a 2-bit
key:
• RANGE DET ENA SSET (CLKTEST.24) must be set to 1
• RANGE DET CTRL (CLKTEST.25) must be cleared to 0
In this case, the LPO HF and LF clocks are still active but the clock detect circuitry is disabled. The clock
detect unconditionally switches GCM_CLK_SRC(0) back to the oscillator so care should be taken to
insure that the oscillator is good before disabling the clock detect circuitry.
10.4.5.2 Disable LPO HF and LF Clocks
The LPO may be disabled by holding the relaxation oscillator clocks (HF and LF) in reset. The clock
detect must be disabled, and any clock domains using either HF or LF clocks must be switched to a
different clock source. The LPO HF clock is reset by setting CSDIS.5; CSDISSET.5 is an easy way to set
specific bits without disturbing the rest of the register. The HF LPO clock disables several HF LPO cycles
after CSDIS is set.
Similarly, the LPO LF clock is reset by setting CSDIS.4, and in a similar way CSDISSET.4 can set the
specific CSDIS register bit without using a read-modify-write construction. The LF LPO disables several
LF LPO cycles after CSDIS is set.
Restarting the LPO clocks from this condition is fast and is known as a warm re-start. The CSDISCLR
register allows the user to clear CSDIS bits without using a read-modify-write code-construct.
10.4.5.3 Disable LPO Current Bias
The LPO current source may be disabled after the clock detect is disabled and HF and LF clock sources
are disabled. Turning off this current source places the LPOCLKDET into its lowest power configuration.
The bias may be disabled by clearing the BIAS ENABLE bit (LPOMONCTL.24).
Restarting the LPO when the bias current has been disabled requires the current source to initialize first
and is, therefore slower than a warm re-start; re-enabling the LPO from this condition is known as a warm
re-start (similar to what happens during nPORRST active).
10.4.6 Trimming the HF LPO Oscillator
The HF LPO range varies considerably around 9.6MHz from device to device. In order to provide tighter
monitoring of the crystal/resonator, it is useful to trim the oscillator. During device test, a trim value is
written into the one-time programmable section of the flash memory (OTP), address 0xF008_01B4. Bits
31:16 of this OTP word contain a 16 bit value that may be programmed into LPOMONCTL(15:0) in order
to initialize the trim for both HF LPO and LF LPO.
When trimming the HF LPO, it is recommended to step the trim value so as not to make a large change to
any TRIM setting.
After the initial trim, further trimming may be done in LPOMONCTL, using the dual clock compare module
(see Chapter 11) in order to determine the resultant frequency. This module allows for comparison of two
clock frequencies. Once the HF LPO is determined to be in-range with the initial HFTRIM setting from the
OTP, the crystal oscillator may be used as a reference against which the HF LPO and LF LPO may be
further adjusted.
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10.5 PLL
The following bit fields from PLLCTL1 and PLLCTL2 configure the PLL:
• REFCLKDIV[5:0]
• PLLMUL[15:0]
• ODPLL[2:0]
• PLLDIV[4:0]
• SPR_AMOUNT[8:0]
• SPREADINGRATE[8:0]
• FMENA
The PLL is responsible for synthesizing an output frequency from the input clock (from the oscillator);
Figure 10-4 shows a simple block diagram of the PLL. The FM-PLL divides the reference input for a lower
frequency input into the PLL (fINTCLK = fCLKIN/NR). The PLL multiplies this internal frequency by NF to get the
VCO output clock frequency (fOutput CLK = fINTCLK × NF). The PLL output is subsequently divided by two
prescale values (OD and R). The value of OD is an integer from 1 to 8 and R is an integer from 1 to 32.
This output clock, PLL CLK, sources GCM clock source 1. Valid frequencies are shown in Table 10-1
while Table 10-2 shows how that encoding is generated from the PLL bit fields.
[f(post_ODCLK) and f(GCLK) are data sheet parameters.]
Table 10-1. Valid Frequency Ranges for PLL
Frequency Limit
fCLKIN
f(OSC_Sqr)
fINTCLK
1MHz - f(OSC_Sqr)
fOutput
150MHz - 550MHz
CLK
fpost-ODCLK
f(post_ODCLK)
fPLL
f(GCLK)
CLK
Figure 10-4. Operation of the FM-PLL Module
CLKIN
÷NR
÷1 - ÷64
Output CLK
INTCLK
PLL
÷OD
post-ODCLK
÷1 - ÷8
÷R
PLL CLK
÷1 - ÷32
÷NF
÷1 - ÷256
f CLKIN
1
1
f PLLCLK = ----------------- x NF x --------- x ---OD R
NR
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Table 10-2. PLL Value Encoding
PLL
NR
NR = REFCLKDIV [5...0] + 1
(2)
Non-modulated:
NF =
( P L L M U L [1 5 . . . 0 ] + 2 5 6 )
256
(3)
Modulated:
NF
NV
NF =
( P L L M U L [1 5 ... 0 ] + M U L M O D [ 8 ... 0 ] + 2 5 6 )
256
(4)
NV =
( S P R _ A M O U N T [ 8 ... 0 ] + 1)
2048
(5)
NS
NS = SPRRATE [8...0] + 1
(6)
OD
OD = ODPLL[2...0] + 1
(7)
NOTE: ODPLL change should occur prior to enabling asynchronous clock domains
Since changing the ODPLL bit-field causes the PLL CLK to be gated, these changes to
ODPLL should be completed before configuring a clock domain for an asynchronous clock
source. Some clock domains (for example, RTICLK, VCLK2) require a frequency relationship
to the VCLK.
fVCLK ³ 3 ´
f RTISRC
RTIDIV
If the PLL is clocking VCLK and it is stopped for some cycles, then the frequency relationship
is temporarily violated.
Many asynchronous domains require frequency relationships between VCLK and the
asynchronous domain. Therefore, if the PLL clock is the source for GCLK, HCLK, and VCLK,
then the gating produces a short-term change in the PLL clock frequency (and hence also
the VCLK frequency). As such, this frequency change could violate the requirements for an
asynchronous clock domain.
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10.5.1 Modulation
Optionally, the frequency can be modulated, that is, a controlled jitter is introduced onto the baseline
frequency of the PLL. This modulation mechanism is not shown in Figure 10-4. When the PLL is used in
the modulating mode, the programmable modulation block varies the PLL frequency from the baseline
frequency (fbaseline = (fCLKIN/NR) × NF/(OD × R)) to fbaseline × (1 - 2 × Depth) in a period defined by 1/fs; the
modulation waveform is triangular and should be enabled after lock.
Modulation Period (1/fs)
f0 - n%
Depth
Modulation
Frequency (MHz)
f0
f0-2n%
Time (Ps)
The modulation is digital and the spreading profile is triangular, down-spread which implies:
• the modulation waveform is composed of a series of frequency steps.
• the modulation frequency and modulation depth are both well controlled due to their digital character.
• the average frequency during modulation is lower than the average frequency prior to enabling
modulation. The depth of modulation, however, sets the new average frequency.
• the modulation frequency must be selected slower than the loop bandwidth. From a practical
perspective, NS should be near 20.
The modulation fields have a simple geometric meaning:
• the modulation step size is:
NV
´ f O u tp u tC L K
NF
•
•
the number of steps per modulation period is 2 × NS
the modulation depth is given by:
NS
NV
´
´ f O u tp u tC L K
2
NF
Df =
D e p th [% ] =
•
N S
N V
´
2
N F
(9)
the modulation frequency is:
Tmod =
•
(8)
f OSC
2 ´ NR ´ NS
(10)
MULMOD minimizes frequency offset when programmed as:
( S P R _ A M O U N T [ 8 ... 0 ] + 1)( S P R R AT E [ 8 ... 0 ] + 1)
16
(11)
NOTE: Modulation should be enabled after Lock
Enable modulation after the lock is completed.
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10.5.2 PLL Output Control
The outputs from the PLL are the output clock, slip signals, and VALID.
• RFSLIP -- the RFSLIP signal indicates that the Output CLK is running too fast relative to INTCLK and
sets a RFSLIP status flag in the Global Status Register (GLBSTAT), of the System and Peripheral
Control Registers, if the slip signal is active during normal PLL operation; the RFSLIP flag is masked
off while the PLL is not active and during the PLL’s lock period.
• FBSLIP -- the FBSLIP signal indicates that the Output CLK is running too slow relative to INTCLK and
sets a FBSLIP status flag in the Global Status Register (GLBSTAT), of the System and Peripheral
Control Registers, if the slip signal is active during normal PLL operation; the FBSLIP flag is masked
off while the PLL is not active and during the PLL’s lock period.
• PLL Slip -- Logical-OR of the two PLL slip signals. Typically this signal is used to generate a
consolidated slip signal to the device (for example, error logic or exception generation). Also used to
gate VALID.
NOTE: Clearing Slip Bits
In order to clear any of the slip bits, it is necessary to disable the PLL first.
•
•
VALID -- is driven based upon whether the output clock, PLL CLK, is gated or not. However, the
VALID signal is dependent upon the PLL Slip signals so that VALID cannot be set if either slip signal is
active.
PLL Clock -- The PLL output clock runs at the programmed frequency. When enabled, it takes some
time to acquire the programmed frequency (see Section 10.5.2.1). Similarly, the disable has some
timing/constraints (see Section 10.5.2.2).
10.5.2.1 PLL Enable
After setting the PLL control registers, the clock source is enabled by clearing the appropriate bit in the
Clock Source Disable Register (CSDIS) or setting the appropriate bit in the Clock Source Disable Clear
Register (CSDISCLR) of the System and Peripheral Control Registers. The bit sends a signal to the PLL
that starts the process of enabling the PLL.
1. The PLL checks to make sure that the oscillator is ON. If not, it turns the oscillator ON.
2. The PLL begins a locking process in which the PLL slews from a starting frequency point to the
programmed frequency. During this lock period, the PLL slip signals are typically active, and the PLL
masks off the signals during this phase. The lock phase takes the following length of time:
Parameter
Lock
Enable clocks after lock
Value
TLock = (512 × TOSCIN) + (1024 × NR × TOSCIN)
TEnable = 6 × TOSCIN
3. After the lock phase is complete (when lock counters expire), the PLL releases the slip signals to the
system.
4. Then, after the slip signals are released and a delay to enable the clocks, the clock is released to the
system and the appropriate CLKSRnV bit for the PLL is set in the Clock Source Valid Status Register
(CSVSTAT) of the System and Peripheral Control Registers.
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10.5.2.2 PLL Disable
The clock sources (for example, OSC, PLL) are disabled by setting the appropriate bit in the Clock Source
Disable Register (CSDIS) or setting the appropriate bit in the Clock Source Disable Set Register
(CSDISSET) of the System and Peripheral Control Registers. These bits allow the clock to disable but do
not force the behavior until the clock is no longer used as the source for a clock domain (for example,
GCLK, VCLK, VCLK2, RTICLK).
The PLL receives a signal to disable after the clock is no longer used by any clock domain. Within the
PLL, the clock is disabled and the appropriate CLKSRnV bit for the PLL in the Clock Source Valid Status
Register (CSVSTAT), of the System and Peripheral Control Registers, becomes inactive. Then the PLL is
placed into a low-power state after the following length of time: TEnable = 150 × TOSCIN
10.5.2.3 OD-divider Change
The PLL gates the clock if the ODPLL bit-field is changed while the PLL is active. The output clock from
the PLL is gated for 3 or 12 OSCIN clock cycles. As the post-ODCLK is gated in the low phase, the output
clock to the device -- PLL CLK -- may be gated in a high or low phase though the transition is always
glitchless: TODPLL = 3 × TOSCIN
NOTE: ODPLL change should occur prior to enabling asynchronous clock domains
Since changing the ODPLL bit-field causes the PLL CLK to be gated, these changes to
ODPLL should be completed before configuring a clock domain for an asynchronous clock
source. Some clock domains (for example, RTICLK, VCLK2) require a frequency relationship
to the VCLK.
fVCLK ³ 3 ´
f RTISRC
RTIDIV
If the PLL is clocking VCLK and it is stopped for some cycles, then the frequency relationship
is temporarily violated.
Many asynchronous domains require frequency relationships between VCLK and the
asynchronous domain. Therefore, if the PLL clock is the source for GCLK, HCLK, and VCLK,
then the gating produces a short-term change in the PLL clock frequency (and hence also
the VCLK frequency). As such, this frequency change could violate the requirements for an
asynchronous clock domain.
10.5.2.4 Changing the PLL Operating Point While the PLL is Active
Once the valid bit (CLKSRnV bit in the Clock Source Valid Status Register (CSVSTAT) of the System and
Peripheral Control Registers) is set, software may change values to the PLL. If the change of values
results in a small percentage change to the VCO frequency (∆fOutputCLK < 0.1 × fOutputCLK), then these
changes can be done on-the-fly. In this mode, the values are updated into the PLL synchronously, and the
PLL re-locks to the new value without gating the clocks or the slip bits. If the operating point change is too
large, then the slip bits will be set.
Conversely, if the changes to the VCO frequency are large, then the PLL should be disabled prior to
changing the values. Typically, any change to the REFCLKDIV field or large changes to the PLLMUL field
in the PLL Control Register 1 (PLLCTL1) of the System and Peripheral Control Registers requires a
complete disable-and-relock strategy.
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10.5.2.5 Summary of PLL Timings
In addition to controlling the lock period and disabling the clock during an ODPLL change, the PLL also
generates reset delays. When power-on reset is released (nPORRST 0 --> 1), that release is delayed by
1024 OSCIN cycles so that it is released at the same time that the oscillator valid is asserted. The system
reset release is delayed by an additional 8 oscillator clock cycles.
Table 10-3. Summary of PLL Timings
Parameter
nPORRST delay
nRST delay
OSC valid
Lock
Value
TnPORRST = 1024 × TOSCIN
TnRST = 1032 × TOSCIN
TOSCVALID = 1024 × TOSCIN
TLock = (512 × TOSCIN) + (1024 × NR × TOSCIN)
Enable clocks after lock
TEnable = 6 × TOSCIN
Disable clocks after lock
TEnable = 150 × TOSCIN
Change ODPLL
TODPLL = 3 × TOSCIN
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10.5.3 Behavior on PLL Fail
The PLL allows flexible response to a PLL failure (slip). Like the oscillator, the PLL clock is configured by
default to automatically switch-over to the oscillator in case of a PLL slip. (In this case, the oscillator
sources GCM clock source 1 as well as GCM clock source 0. Also, if the oscillator fails, LPO HF is
sourced to both GCM clock sources 0 and 1.)
The PLL slip outputs indicate that the PLL is running either too fast or too slow. These error output toggle
when the PLL is locking and when the PLL is disabling. The PLL blocks these slip outputs during these
times, leaving them active only while the PLL is active.
A slip after the PLL has locked and while it is active is an indication of a PLL failure. The PLL provides
slip-filtering which enhances the flexibility of the PLL’s response to failure. The slip-filtering circuit samples
the slip based on HF LPO. The filter defines the number of consecutive HF LPO cycles for which the slip
signal must be active before the slip is recognized. This slip is latched in the RFSLIP and FBSLIP status
flags in the Global Status Register (GLBSTAT) of the System and Peripheral Control Registers.
The PLL may enable/disable the automatic switch over as well as the error signaling; if the error signaling
is enabled, a PLL slip may be configured to generate a reset. The automatic switch-over and suppression
of the error signals are controlled by the bypass on slip bit field -- BPOS[1:0] (PLLCTL1.(30:29)). When
BPOS[1:0] is disabled (BPOS[1:0] = 10b):
• automatic response to the PLL slip is prevented
• ESM/exception is NOT generated
• reset on slip is not generated regardless of the state of the ROS bit
• status bits are set on a PLL slip independent of BPOS[1:0]
When BPOS[1:0] is enabled (BPOS[1:0] = 00b OR 01b OR 11b):
• PLL slip causes the clock source into GCM clock source 1 to shift from the PLL to the oscillator
• ESM/exception is generated
• reset on slip is generated if ROS is set
The effect of BPOS[1:0] on the system is shown in Figure 10-5.
Figure 10-5. PLL Slip Detection and Reset/Bypass Block Diagram
PLL Bypass CLK
Input from
Oscillator
CLK signal to
Clock Control Module
PLL CLK
FMzPLL
Bypass on Slip
BPOS
Slip Detector
BPOS
384
ROS
Reset on Slip
Oscillator and PLL
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10.5.4 Recovery from a PLL Failure
If PLL1 fails, the PLL’s slip causes the valid flag to be locked and causes the clock source into GCM clock
source 1 to shift from the PLL to the oscillator. The RFSLIP or FBSLIP status flags in the Global Status
Register (GLBSTAT) of the System and Peripheral Control Registers are also set. PLL1 may be reenabled (though if the failure was caused by a hard-fault, the re-enable will fail) through the following
procedure:
1. Switch all clock domains from PLL1 to the oscillator (for example, GHVSRC uses oscillator, VCLKAn
uses oscillator or VCLK, and so on).
2. Disable PLL1 with CSDISSET. This action disables the PLL and causes the slip signal to no longer be
driven. Valid is not released until the slip is cleared.
3. Clear the RFSLIP or FBSLIP status flags in the Global Status Register (GLBSTAT) of the System and
Peripheral Control Registers by writing a 1 to the bit. After this step, the valid flag is unlocked and
cleared if it was previously set.
4. Re-enable PLL1 with CSDISCLR.
5. Switch the clock domains back to PLL1.
If PLL2 fails, the PLL’s slip causes the valid flag to be locked. There is no autonomous change of clock
source for PLL2. Neither the RFSLIP or FBSLIP status flags in the Global Status Register (GLBSTAT) of
the System and Peripheral Control Registers are set. PLL2 may be re-enabled in a similar procedure to
re-enabling PLL1 (though if the failure was caused by a hard-fault, the re-enable will fail):
1. Switch all clock domains from PLL2 to the oscillator (for example, GHVSRC uses oscillator, VCLKAn
uses oscillator or VCLK, and so on).
2. Disable PLL2 with CSDISSET. This action disables the PLL and causes the slip signal to no longer be
driven. Valid is not released until the slip is cleared.
3. Reset PLL2 Valid by writing a 1 to both RFSLIP and FBSLIP status flags in the Global Status Register
(GLBSTAT) of the System and Peripheral Control Registers (even though they are not set by the slip).
After this step, the valid flag is unlocked and cleared if it was previously set.
4. Re-enable PLL2 with CSDISCLR.
5. Switch the clock domains back to PLL2.
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10.5.5 PLL Modulation Depth Measurement
The PLL contains a circuit for estimating the depth of the modulation. The circuit counts clock edges over
a fixed window of the modulation waveform (SSW_CAPTURE_COUNT in SSWPLL2) and clock edges
over the entire waveform (SSW_CLKOUT_COUNT in SSWPLL3). The capture ends after a predetermined number of clock edges in SSW_CLKOUT_COUNTER as set in TAP_COUNTER_DIS. There
are 2 × NR windows per modulation waveform. The procedure for estimating the modulation depth is:
1. While GCLK is sourced by the oscillator and the PLL is enabled with modulation, configure SSWPLL1
as follows:
a. CAPTURE_WINDOW_INDEX is set equal to NR.
b. COUNTER_RESET is set.
c. TAP_COUNTER_DIS is set to disable the measurement after SSW_CLKOUT_COUNT captures
this number of clocks. The measurement is disabled after the set tap is set AND the modulation
cycle ends.
d. Ensure that EXT_COUNTER_EN is cleared.
2. Ensure that both SSW_CAPTURE_COUNT and SSW_CLKOUT_COUNT are cleared (by the
COUNTER_RESET).
3. Set COUNTER_EN and clear COUNTER_RESET. This step releases the reset and enables the
counter to begin counting.
4. After a wait loop, poll for COUNTER_READ_READY to set. After the bit is set, read
SSW_CAPTURE_COUNT and SSW_CLKOUT_COUNT.
5. Compute the modulation depth as:
æ 2 ´ NR ´ SSW _ CAPTURE _ COUNT ö
÷÷
Depth = absçç1 SSW
_
CLKOUT
_
COUNT
ø
è
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10.5.6 PLL Frequency Measurement Circuit
The same circuit that is used to measure modulation depth is also available to measure the average
frequency of the PLL. In this mode, the PLL output (before the R-divider) is captured in
SSW_CLKOUT_COUNT while the oscillator is captured in SSW_CAPTURE_COUNT. The procedure for
using the PLL frequency measurement circuit is:
1. While the PLL is enabled, set EXT_COUNTER_EN.
2. Set COUNTER_EN. This bit clears both SSW_CAPTURE_COUNT and SSW_CLKOUT_COUNT and
then immediately enables for counting.
3. Wait for some software delay loop.
4. Clear COUNTER_EN. Wait for COUNTER_READ_READY to set. Read both
SSW_CAPTURE_COUNT and SSW_CLKOUT_COUNT and compute the ratio of PLL multiplication
as:
NF
SSW _ C LK O U T _ C O U N T
=
NR ´ OD
SSW _ C APTU RE _ C O U N T
(13)
5. Note that CAPTURE_WINDOW_INDEX, COUNTER_RESET, TAP_COUNTER_DIS are not used in
this procedure.
10.5.7 PLL2
PLL2 drives GCM clock source 6.
The PLL is identical to PLL1, except modulation is disabled on this instance of the PLL. Also, the PLL
typically does not clock the system, there is no automatic switch over feature. Any PLL error can be
handled by the CPU.
PLL2 is programmed through PLLCTL3.
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10.6 PLL Control Registers
The clock module has two registers (PLLCTL1 and PLLCTL2) located within the System and Peripheral
Control Registers, plus it has four bits located in other System and Peripheral Control Registers.
The FM-PLL is off at power-on. The clock source is enabled by clearing the appropriate bit in the Clock
Source Disable Register (CSDIS) or setting the appropriate bit in the Clock Source Disable Clear Register
(CSDISCLR) of the System and Peripheral Control Registers. [CSDISCLR and Clock Source Disable Set
Register (CSDISSET) also enable/disable the PLL and oscillator (and other clock sources).]
The LPOCLKDET module generates the OSCFAIL flag in the Global Status Register (GLBSTAT), of the
System and Peripheral Control Registers, if a problem with the reference oscillator is detected. The slip
signals are also registered in the RFSLIP and FBSLIP status flags in the Global Status Register
(GLBSTAT), of the System and Peripheral Control Registers, in order to indicate the source of a clock
failure.
The appropriate CLKSRnV bit for the PLL is set in the Clock Source Valid Status Register (CSVSTAT) of
the System and Peripheral Control Registers.
The following sections describe the PLL registers used in the system module. These registers support 8,
16, and 32-bit write accesses. The reset values for these registers are configured so that an input
frequency in the range from 5MHz to 20MHz generates a valid clock.
Table 10-4. PLL Module Registers
Offset
Acronym
Register Description
Section
FFFF FF30h
CSDIS
Clock Source Disable Register
Section 2.5.1.10
FFFF FF34h
CSDISSET
Clock Source Disable Set Register
Section 2.5.1.11
FFFF FF38h
CSDISCLR
Clock Source Disable Clear Register
Section 2.5.1.12
FFFF FF54h
CSVSTAT
Clock Source Valid Status Register
Section 2.5.1.19
FFFF FF70h
PLLCTL1
PLL Control 1 Register
Section 2.5.1.25
FFFF FF74h
PLLCTL2
PLL Control 2 Register
Section 2.5.1.26
FFFF E100h
PLLCTL3
PLL Control 3 Register
Section 2.5.2.1
FFFF FFA0h
GPREG1
General Purpose Register
Section 2.5.1.34
FFFF FFECh
GLBSTAT
Global Status Register
Section 2.5.1.50
FFFF E170h
CLKSLIP
PLL Clock Slip Control Register
Section 2.5.2.5
FFFF FF24h
SSWPLL1
PLL Modulation Depth Measurement Control Register
Section 10.6.1
FFFF FF28h
SSWPLL2
SSW PLL BIST Control Register 2
Section 10.6.2
FFFF FF2Ch
SSWPLL3
SSW PLL BIST Control Register 3
Section 10.6.3
Table 10-5. LPOCLKDET Module Registers
Offset
388
Acronym
Register Description
FFFF FF88h
LPOMONCTL
LPO/Clock Monitor Control Register
Section 2.5.1.30
FFFF FF8Ch
CLKTEST
Clock Test Register
Section 2.5.1.31
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10.6.1 PLL Modulation Depth Measurement Control Register (SSWPLL1)
Figure 10-6 illustrates this register and Table 10-6 provides the bit descriptions. This register applies to
PLL1, but does not apply to PLL2.
Figure 10-6. SSW PLL BIST Control Register 1 (SSWPLL1) [offset = FF24h]
31
16
Reserved
R-0
15
8
CAPTURE_WINDOW_INDEX
R/W-0
7
6
5
4
Reserved
COUNTER_READ_
READY
COUNTER_
RESET
COUNTER_EN
3
TAP_COUNTER_DIS
1
EXT_COUNTER_
EN
0
R-0
R-0
R/W-1
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-6. SSW PLL BIST Control Register 1 (SSWPLL1) Field Descriptions
Bit
Field
31-16
Reserved
15-8
CAPTURE_WINDOW_INDEX
7
Reserved
6
COUNTER_READ_READY
5
4
Value
0
0-FFh
0
Description
Read returns 0. Writes have no effect.
The capture counter present in the PLL wrapper will count the PLL clock edges when
the current modulation phase capture window value is equal to these bits. Should be
set equal to NR.
Read returns 0. Writes have no effect.
Counter read ready.
Indicates that SSW_CAPTURE_COUNT (SSWPLL2) and SSW_CLKOUT_COUNT
(SSWPLL3) can be read.
0
Counter registers in SSWPLL2 and SSWPLL3 are not ready to read.
1
Counter registers in SSWPLL2 and SSWPLL3 are ready to read.
COUNTER_RESET
Counter reset.
If EXT_COUNTER_EN = 0, COUNTER_RESET resets SSW_CAPTURE_COUNT
(SSWPLL2) and SSW_CLKOUT_COUNT (SSWPLL3).
If EXT_COUNTER_EN = 1, this bit is ignored.
0
No impact to counters
1
If the EXT_COUNTER_EN bit is 0, then counters SSW_CAPTURE_COUNT and
SSW_CLKOUT_COUNT will be held in the reset state.
If EXT_COUNTER_EN bit is 1, then this bit will be ignored by the PLL wrapper.
COUNTER_EN
Counter enable.
If EXT_COUNTER_EN = 0, COUNTER_EN initializes the modulation depth
measurement. (In this mode, the disable is set to occur automatically.)
If EXT_COUNTER_EN = 1, the counters are enabled/disabled with COUNTER_EN.
0
If EXT_COUNTER_EN = 0, COUNTER_EN = 0 indicates that the counters are
inactive.
If EXT_COUNTER_EN = 1, COUNTER_EN = 0 disables the counters.
1
If EXT_COUNTER_EN = 0, COUNTER_EN = 1 indicates that the counters are still
active.
If EXT_COUNTER_EN = 1, COUNTER_EN = 1 enables the counters.
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Table 10-6. SSW PLL BIST Control Register 1 (SSWPLL1) Field Descriptions (continued)
Bit
Field
3-1
TAP_COUNTER_DIS
0
Value
EXT_COUNTER_EN
Description
The value in this register is used to program a particular bit in CLKOUT counter.
When that particular bit in CLKOUT counter becomes 1, then both the CLKOUT
counter and the CAPTURE counter will stop counting when EXT_COUNTER_EN = 0.
When EXT_COUNTER_EN = 1, this bit field is not used.
0
Bit 16 of CLKOUT counter is selected. When this bit is set and the modulation period
finishes, the counters are disabled and READ_READY_FLAG is set.
1h
Bit 18 of CLKOUT counter is selected.
2h
Bit 20 of CLKOUT counter is selected.
3h
Bit 22 of CLKOUT counter is selected.
4h
Bit 24 of CLKOUT counter is selected.
5h
Bit 26 of CLKOUT counter is selected.
6h
Bit 28 of CLKOUT counter is selected.
7h
Bit 30 of CLKOUT counter is selected.
0
Modulation Depth Measurement mode
1
Frequency Measurement mode
10.6.2 SSW PLL BIST Control Register 2 (SSWPLL2)
This is an observation register used to log counter value for the capture counter inside the PLL wrapper.
This register applies to PLL1, but does not apply to PLL2. The SSWPLL2 register is shown in Figure 10-7
and described in Table 10-7.
Figure 10-7. SSW PLL BIST Control Register 2 (SSWPLL2) [offset = FF28h]
31
16
SSW_CAPTURE_COUNT
R-0
15
0
SSW_CAPTURE_COUNT
R-0
LEGEND: R = Read only; -n = value after reset
Table 10-7. SSW PLL BIST Control Register 2 (SSWPLL2) Field Descriptions
Bit
31-0
390
Field
SSW_CAPTURE_COUNT
Value
Description
0-FFFF FFFFh Capture count. This register returns the value of the capture count.
When EXT_COUNTER_EN = 0, this counter increments within a fixed
modulation window.
When EXT_COUNTER_EN = 1, this counter increments based upon the
oscillator.
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10.6.3 SSW PLL BIST Control Register 3 (SSWPLL3)
This is observation register used to log counter value for CLKOUT counter inside PLL wrapper. This
register applies to PLL1, but does not apply to PLL2. The SSWPLL3 register is shown in Figure 10-8 and
described in Table 10-8.
Figure 10-8. SSW PLL BIST Control Register 3 (SSWPLL3) [offset = FF2Ch]
31
16
SSW_CLKOUT_COUNT
R-0
15
0
SSW_CLKOUT_COUNT
R-0
LEGEND: R = Read only; -n = value after reset
Table 10-8. SSW PLL BIST Control Register 3 (SSWPLL3) Field Descriptions
Bit
31-0
Field
SSW_CAPTURE_COUNT
Value
Description
0-FFFF FFFFh Value of CLKout count register. This counter increments based upon the PLL
output (prior to the R-divider).
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10.7 Phase-Locked Loop Theory of Operation
The PLL block consists of six logical sub-blocks:
• Phase-Frequency Detector (PFD)
• Charge Pump (CP)
• Loop Filter (LF)
• Voltage-Controlled Oscillator (VCO)
• Frequency Modulation
• Slip Detector
Figure 10-9 illustrates the sub-blocks in a basic PLL circuit. The VCO adjusts its frequency until the two
signals into the PFD have the same phase and frequency. The feedback path (from VCO to PFD) divides
the frequency of the feedback signal by 2 × NF; this feedback divider requires the VCO to generate a
frequency 2 × NF times greater than the internal frequency (OSCIN/NR). In the forward path (from VCO to
PLL CLK), the /2 block creates a clean duty cycle.
Figure 10-9. Basic PLL Circuit
Output CLK
INTCLK
CLKIN
÷NR
PFD
CP
LF
÷2
÷NF
VCO
post-ODCLK
÷OD
÷2
÷R
PLL CLK
Feedback
CLK
10.7.1 Phase-Frequency Detector
The phase-frequency detector (PFD) compares the input reference phase/frequency to the
phase/frequency of the feedback divider and generates two signals: an up pulse and a down pulse that
drive a charge pump. The resulting charge, when integrated by the circuit at the LF pin, provides a VCO
control voltage, as shown in Figure 10-10.
Figure 10-10. PFD Timing
Input
reference
Feedback
divider output
Leading phase
Lagging phase
Up
Down
VCO control
Interpulse slope caused by filter time constant and leakage
voltage
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The width of the up pulse and the down pulse depends on the difference in phase between the two inputs.
For example, when the reference input leads the feedback input by 10 ns, then an up pulse of
approximately 10 ns is generated (see Figure 10-10). On the other hand, when the reference input lags
the feedback input by 10 ns, then a down pulse of approximately 10 ns is generated. When the two inputs
are exactly in phase, the up pulse and down pulse become essentially zero-width. These pulses are fed to
the charge pump block, which meters charge into the low-pass loop filter.
The advantage of a phase-frequency detector over a phase-only detector is that it cannot lock to a
harmonic or subharmonic of the reference. This important property also ensures that the output frequency
of the VCO is always exactly 2 × NF times the reference frequency.
The reference feedback frequency is based upon the VCO frequency and the feedback divider. Fractional
multiplication is achieved by changing the feedback divider real-time in order to create the fractional
multiplication. As an example, if a multiplier of 100.5 is selected, the feedback divider divides by 100 and
101 in equal proportions; in this case, the PLLMUL bit field would be programmed as 99.5 (0x6380). This
fractional multiplication is useful when trying to achieve final frequencies that are non-integer to the input
frequency (for example, a final frequency that is a prime number). The fractional portion of the divider
should be small compared to the multiplier and so it is recommended that the fractional portion relate to
parts in 16, implying that the last 4 bits should always be 0.
10.7.2 Charge Pump and Loop Filter
The charge pump (CP) add or remove charge from the loop filter based on the pulses coming from the
phase-frequency detector (PFD).
Two components of the filter output signal are summed together: an integral component and a
proportional component. The integral component maintains a DC level going to the VCO to set its
frequency, and the proportional component makes the VCO track changes in phase to minimize jitter. The
capacitors and resistors required for the filter are integrated in silicon.
10.7.3 Voltage-Controlled Oscillator
The output frequency of the VCO is proportional to its input control voltage, which is generated by the
charge pump via the integrated loop filter. If the VCO oscillates too slowly, the feedback phase begins to
lag the reference phase at the PFD, which increases the control voltage at the VCO. Conversely, if the
VCO oscillates too fast, the feedback phase begins to lead the reference phase at the PFD, which
decreases the control voltage at the VCO. These two actions keep the VCO running at the correct
frequency multiple of the reference.
Figure 10-11. PLL Modulation Block Diagram
CLKIN
÷NR
post-ODCLK
Output CLK
INTCLK
PFD
CP
LF
VCO
÷2
÷OD
÷R
PLL CLK
Feedback
CLK
NF
NV
NS
Divider
÷2
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10.7.4 Frequency Modulation
The output clock of the PLL changes frequency in a controlled way, centered around the unmodulated
output frequency. The modulation block directly modulates the VCO frequency at the loop filter, and
creates the triangular frequency modulation (see Figure 10-12).
Figure 10-12. Frequency vs. Time
Modulation Period (1/fs)
Depth
f0
Modulation
Frequency (MHz)
f0+n%
f0-n%
Time (Ps)
10.8 Programming Example
This section provides an example of how to program the PLL. For non-modulation settings, the PLLCTL1
and PLLCTL2 settings from 130nm process devices can be used without modification.
Suppose that, using a 20MHz crystal, the application requires:
• 180MHz GCLK (and HCLK) frequency
• 100 kHz spreading frequency
• 0.5% spreading depth
1. Choose an NR and NS such that:
•
•
•
•
•
f CLKIN
³ 40
NR ´ f s
(14)
f CLKIN
2 ´ NR ´ NS
f
2 ´ NS = CLKIN ³ 40
NR ´ f s
fs º
(15)
(16)
(NR,NS) = {(5,20), (4,25), (2,50), (1,100)}
Either NR = 5 and NS = 20 or NR = 4 and NS = 25 are reasonable. Another choice (NR = 3 and
NS = 33) is possible, if the modulation frequency can vary from 100KHz.
2. Choose Output CLK frequency as integer divider of output frequency near to 330MHz. Output CLK
frequency shall not exceed 550MHz or fall below 150MHz.
The integer values for 180MHz are 360MHz or 540MHz. 360MHz is close to the target frequency of
330MHz and we use this frequency.
3. In this case, either of the following equations are suitable choices for getting to 360MHz.
Choose NR = 5, NS = 20 and set NF = 90 or choose NR = 4, NS = 25 and set NF = 72.
f CLKIN 20[ MHz ]
f
20[ MHz ]
=
= 5[ MHz ] or CLKIN =
= 4[ MHz ]
NR
5
4
NR
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4. Select the output divider OD so that the post-ODCLK frequency does not exceed the maximum
frequency of output divider R (device specific frequency). In this case, choose OD = 2 and R = 1.
5. Compute the divider value NV:
D ep th =
0 .5
NV
NS
N V 20
=
´
=
´
100
NF
2
90
2
(18)
NV = 0.045
6. If it is important to maintain the same average frequency in modulation as in non-modulation, either NF
should be modified OR program the MULMOD bit field. The modulation fields create a multiplier offset
equal to:
DNF =
NV ´ NS
2
(19)
If using MULMOD[8:0], then:
MULMOD [8 ...0 ] NV ´ NS 0 .045 ´ 20
=
=
256
2
2
0 . 045 ´ 20
M U LM O D [8 ... 0 ] =
´ 256 = 115 . 2
2
D NF =
(20)
(21)
MULMOD will be set to 115.
7. Convert the PLL parameters into bit field values:
• NR = 5, implies that REFCLKDIV[5:0] = 4
• NS = 20, implies that SPRATE[8:0] = 19 = 0x13
• NF = 90, implies that PLLMUL[15:0] = 0x5900
• OD = 2, implies that ODPLL[2:0] = 1
• R = 1, implies that PLLDIV[4:0] = 0
• NV = 0.045, implies that SPR_AMOUNT[8:0] = 91 = 0x5B
• MULMOD[8:0] = 115 = 0x73
8. Setting only these fields (that is, not BPOS, ROF, or ROS) yields:
PLLCTL1 = 0x00045900
PLLCTL2 = 0x04C7325B
When FM ENA is turned on, PLLCTL2 = 0x84C7325B
The Output CLK is centered in the range from 150MHz to 550MHz at 360MHz.
NF = 90 falls within the multiplier range from 1 to 256.
OD is selected so that post-ODCLK meets the device specification.
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Chapter 11
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Dual-Clock Comparator (DCC) Module
This chapter describes the dual-clock comparator (DCC) module.
Topic
11.1
11.2
11.3
11.4
396
...........................................................................................................................
Introduction .....................................................................................................
Module Operation .............................................................................................
Clock Source Selection for Counter0 and Counter1 ..............................................
DCC Control Registers ......................................................................................
Dual-Clock Comparator (DCC) Module
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397
398
402
403
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11.1 Introduction
The primary purpose of a DCC module is to measure the frequency of a clock signal using a second
known clock signal as a reference. This capability can be used to ensure the correct frequency range for
several different device clock sources, thereby enhancing the system safety metrics.
11.1.1 Main Features
The main features of each of the DCC modules are:
• Allows application to ensure that a fixed ratio is maintained between frequencies of two clock signals
• Supports the definition of a programmable tolerance window in terms of number of reference clock
cycles
• Supports continuous monitoring without requiring application intervention
• Also supports a single-sequence mode for spot measurements
• Allows selection of clock source for each of the counters resulting in several specific use cases
11.1.2 Block Diagram
Figure 11-1 illustrates the main concept of the DCC module.
Figure 11-1. DCC Operation
Preload Count 0
Reload
Preload Valid 0
0
0
Reload
Clock 0
Down Counter 0
=
Valid 0 Down Counter
=
Error (to ESM)
Compare and Control
Logic
Done (to VIM)
Preload Count 1
Reload
Reload
Clock 1
Down Counter 1
Single
Sequence
Mode
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11.2 Module Operation
As shown in Figure 11-1, the DCC contains two counters – counter0 and counter1, which are driven by
two signals – clock0 and clock1. The application programs the seed values for both these counters. The
application also configures the tolerance window time by configuring the valid counter for clock0.
Counter0 and counter1 both start counting simultaneously once the DCC is enabled. When counter0
counts down to zero, this automatically triggers the count down of the tolerance window counter (valid0).
The DCC module can be used in two different operating modes:
11.2.1 Continuous Monitoring Mode
In this mode, the DCC is used by the application to ensure that two clock signals maintain the correct
frequency ratio. Suppose the application wants to ensure that the PLL output signal (clock source # 1)
always maintains a fixed frequency relationship with the main oscillator (clock source # 0).
• In this case, the application can use the main oscillator as the clock0 signal (for counter0 and valid0)
and the PLL output as the clock1 (for counter1).
• The seed values of counter0, valid0 and counter1 are selected such that if the actual frequencies of
clock0 and clock1 are equal to their expected frequencies, then the counter1 will reach zero either at
the same time as counter0 or during the count down of the valid0 counter.
• If the counter1 reaches zero during the count down of the valid0 counter, then all the counters
(counter0, valid0, counter1) are reloaded with their initial seed values once valid0 has also counted
down to zero.
• This sequence of counting down and checking then continues as long as there is no error, or until the
DCC module is disabled.
• The counters also all get reloaded if the application resets and restarts the DCC module.
Error Conditions:
An error condition is generated by any one of the following:
1. Counter1 counts down to 0 before Counter0 reaches 0. This means that clock1 is faster than
expected, or clock0 is slower than expected. It includes the case when clock0 is stuck at 1 or 0.
2. Counter1 does not reach 0 even when Counter0 and Valid0 have both reached 0. This means that
clock1 is slower than expected. It includes the case when clock1 is stuck at 1 or 0.
Any error freezes the counters from counting. An application may then read out the counter values
to help determine what caused the error.
11.2.1.1 Error Conditions
While operating in continuous mode, the counters get reloaded with the seed values and continue
counting down under the following conditions:
• The module is reset or restarted by the application, OR
• Counter0, Valid 0 and Counter1 all reach 0 without any error
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Figure 11-2. Counter Relationship
(no error)
Error
Count0
Count0
Valid0
Valid0
Count1
Count1
Clock0
0
Clock1
0
time
reload
Clock1 must expire
in this window, otherwise
signal an error
reload
Figure 11-3. Clock1 Slower Than Clock0 - Results in an Error and Stops Counting
Error
Count0
Clock0
Valid0
0
Count1
Clock1
0
time
reload
Counter1 does not reach 0
before VALID0 reaches 0
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Figure 11-4. Clock1 Faster Than Clock0 - Results in an Error and Stops Counting
Error
Count0
Clock0
Valid0
0
Count1
Clock1
0
time
reload
Counter1 reaches 0 before
Counter0 reaches 0
Figure 11-5. Clock1 Not Present - Results in an Error and Stops Counting
Error
Count0
Clock0
Valid0
0
Count1
Count1 does not count down
due to an inactive clock 1
Clock1
0
time
reload
An error signal is generated since Count1
does not reach 0 in the Valid0 window.
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Figure 11-6. Clock0 Not Present - Results in an Error and Stops Counting
Error
Count0
Count0 and Valid 0 do not
count down due to an
inactive clock 0
Clock0
Valid0
Count1
Clock1
reload
time
Counter1 reaches 0 at the
right time, but since Clock0 is not running,
Valid0 hasn’t started, thus an error is generated.
11.2.2 Single-Shot Measurement Mode
The DCC module can be programmed to count down one time by enabling the single-shot mode. In this
mode, the DCC stops operating when the down counter0 and the valid counter0 reach 0. Alternatively, the
DCC can be programmed to stop counting when the down counter1 reaches 0.
At the end of one sequence of counting down in this single-shot mode, the DCC gets disabled
automatically, which prevents further counting. This mode is typically used for spot measurements of the
frequency of a signal. This frequency could be an unknown for the application before the measurement.
Example Usage of Single-Shot Measurement Mode: Trimming the High-Frequency Low-Power
Oscillator
A practical example of the usage of the spot measurement mode is in trimming the HF LPO (clock
source # 5) using the main oscillator as a reference. This measurement sequence would proceed as
follows:
• The application sets up the seed values for counter0 and valid0 for the duration of the
measurement. Suppose the main oscillator frequency is 10MHz and the intended duration of the
measurement is 500µs. The application needs to configure a seed value of 5000.
• These 5000 counts need to be divided between the counter0 and the valid0 counters. The
minimum value for the valid0 seed is 4, so the application can configure counter0 seed value as
4996 and the valid0 seed value as 4.
• Suppose the HF LPO frequency is truly unknown. In this case the application can choose the
maximum allowed seed value for counter1. This increases the probability of counter0 and valid0
counting down while the counter1 has still not fully counted down to zero. The maximum allowed
seed value for counter1 is 1048575.
• Once the DCC is enabled, the counters counter0 and counter1 both start counting down from their
seed values.
• When counter0 reaches zero, it automatically triggers the valid0 counter.
• When valid0 reaches zero, if counter1 is not zero as well, an ERROR status flag is set and a "DCC
error" is sent to the ESM. Counter1 is also frozen so that it stops counting down any further. The
application can enable an interrupt to be generated from the ESM whenever this DCC error is
indicated. Refer the device datasheet to identify the ESM group and channel where the DCC error
is connected.
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•
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The DCC error interrupt service routine can then check the value of counter1 when the error was
generated. Suppose that the counter1 now reads 1044575. This means that counter1 has counted
1048575 - 1044575, or 4000 cycles within the 500µs measurement period. This means that the
average frequency of the HF LPO over this 500µs period was 4000 cycles / 500µs, or 8MHz.
The application then needs to clear the ERROR status flag and restart the DCC module so that it is
ready for the next spot measurement.
If there is no error generated at the end of the sequence, then the DONE status flag is set and a DONE
interrupt is generated. The application must clear the DONE flag before restarting the DCC.
The conditions that cause a DCC error are identical between the continuous monitoring mode and the
single-shot measurement mode.
Error Conditions:
An error condition is generated by any one of the following:
1. Counter1 counts down to 0 before Counter0 reaches 0. This means that clock1 is faster than
expected, or clock0 is slower than expected. It includes the case when clock0 is stuck at 1 or 0.
2. Counter1 does not reach 0 even when Counter0 and Valid0 have both reached 0. This means that
clock1 is slower than expected. It includes the case when clock1 is stuck at 1 or 0.
Any error freezes the counters from counting. An application may then read out the counter values
to help determine what caused the error.
Freezing Counters when Counter1 Reaches Zero:
The DCC module also allows the counters to be frozen when the counter1 reaches zero. This allows
one of the clock sources for counter1 to be used as a reference for measuring one of the clock sources
for counter0. The error conditions are the same as those where (counter0=0 and valid0=0) define the
condition when the DCC counters are frozen. That is, an error is indicated if coutner0 and valid0
become zero while counter1 is still non-zero. In this case, however, the application would typically set
up the seed values such that the counter1 will become zero before counter0. Essentially the
measurement period is defined by the seed value of the counter1. Note that this is also an error
condition, and the interrupt service routine can use the measurement period and the actual cycles
counted by counter1 to determine the frequency of the clock0 signal.
11.3 Clock Source Selection for Counter0 and Counter1
Refer to the device datasheet to identify the available options for selecting the clock sources for both
counters of the DCC module. Some microcontrollers may include multiple instances of the DCC module.
This will also be identified in the device datasheet.
The selection of the clock sources for counter0 and coutner1 is done by a combination of the KEY, CNT0
CLKSRC, and CNT1 CLKSRC control fields of the CNT0CLKSRC and CNT1CLKSRC registers.
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11.4 DCC Control Registers
This section describes the dual-clock comparator (DCC) module control and status registers. The registers
support 8-bit, 16-bit or 32-bit writes and are aligned on a word (32-bit) boundary. Table 11-1 shows
address offsets from the module base address. The base address for the control registers is FFFF EC00h
for DCC1 and FFFF F400h for DCC2.
Table 11-1. DCC Control Registers
Offset
Acronym
Register Description
00h
DCCGCTRL
DCC Global Control Register
Section 11.4.1
04h
DCCREV
DCC Revision Id Register
Section 11.4.2
08h
DCCCNT0SEED
DCC Counter0 Seed Register
Section 11.4.3
0Ch
DCCVALID0SEED
DCC Valid0 Seed Register
Section 11.4.4
10h
DCCCNT1SEED
DCC Counter1 Seed Register
Section 11.4.5
14h
DCCSTAT
DCC Status Register
Section 11.4.6
18h
DCCCNT0
DCC Counter0 Value Register
Section 11.4.7
1Ch
DCCVALID0
DCC Valid0 Value Register
Section 11.4.8
20h
DCCCNT1
DCC Counter1 Value Register
Section 11.4.9
24h
DCCCNT1CLKSRC
DCC Counter1 Clock Source Selection Register
Section 11.4.10
28h
DCCCNT0CLKSRC
DCC Counter0 Clock Source Selection Register
Section 11.4.11
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11.4.1 DCC Global Control Register (DCCGCTRL)
Figure 11-7 and Table 11-2 describe the DCC Global Control register.
Figure 11-7. DCC Global Control Register (DCCGCTRL) [offset = 00]
31
16
Reserved
R-0
15
12
11
8
7
4
3
0
DONE INT ENA
SINGLE SHOT
ERR ENA
DCC ENA
R/WP-5h
R/WP-5h
R/WP-5h
R/WP-5h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 11-2. DCC Global Control Register (DCCGCTRL) Field Descriptions
Bit
Field
31-16
Reserved
15-12
DONE INT ENA
Value
0
Description
Reads return 0. Writes have no effect.
Done Interrupt Enable.
Any operation mode read, privileged mode write:
5h
Others
11-8
SINGLE SHOT
No interrupt is generated when the DONE flag is set in the DCC Status (DCCSTAT)
register.
DONE interrupt is generated when the DONE flag is set in the DCC Status (DCCSTAT)
register.
Single-Shot Mode Enable.
Any operation mode read, privileged mode write:
Ah
DCC stops counting when counter0 and valid0 both reach zero.
Bh
DCC stops counting when counter1 reaches zero.
Others
7-4
ERR ENA
DCC counts continuously and only stops when an error occurs.
Error Interrupt Enable.
Any operation mode read, privileged mode write:
5h
Others
3-0
DCC ENA
No interrupt is generated when the ERR flag is set in the DCC Status (DCCSTAT) register.
ERROR interrupt is generated when the ERR flag is set in the DCC Status (DCCSTAT)
register.
DCC Enable.
Any operation mode read, privileged mode write:
5h
Others
All DCC counters are stopped and error-checking is disabled. When an error occurs, the
counters stop and this field is set to 5h automatically disabling the DCC counter in
hardware.
Read: Counters are enabled.
Write: Load counters with their seed values and begin counting. It is recommended to write
Ah to enable counters to protect against single-bit errors.
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11.4.2 DCC Revision Id Register (DCCREV)
Figure 11-8 and Table 11-3 describe the DCC Revision Id register.
Figure 11-8. DCC Revision Id Register (DCCREV) [offset = 4h]
31
30
29
28
27
16
SCHEME
Reserved
FUNC
R-01
R-0
R-0
15
11
10
8
7
6
5
0
RTL
MAJOR
CUSTOM
MINOR
R-0
R-2h
R-0
R-4h
LEGEND: R = Read only; -n = value after reset
Table 11-3. DCC Revision Id Register (DCCREV) Field Descriptions
Bit
Field
Value
Description
31-30
SCHEME
01
Reads return 01, writes have no effect.
29-28
Reserved
0
Reads return 0. Writes have no effect.
27-16
FUNC
0
Functional release number. Reads return 0x000, writes have no effect.
15-11
RTL
0
Design release number. Reads return 0x00, writes have no effect.
10-8
MAJOR
2h
Major revision number. Reads return 0x2, writes have no effect.
7-6
CUSTOM
0
Custom version number. Reads return 0x0, writes have no effect.
5-0
MINOR
4h
Minor revision number. Reads return 0x4, writes have no effect.
11.4.3 DCC Counter0 Seed Register (DCCCNT0SEED)
Figure 11-9 and Table 11-4 describe the DCC Counter0 Seed register.
Figure 11-9. DCC Counter0 Seed Register (DCCCNT0SEED) [offset = 8h]
31
20
19
16
Reserved
COUNT0 SEED
R-0
R/WP-0
15
0
COUNT0 SEED
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 11-4. DCC Counter0 Seed Register (DCCCNT0SEED) Field Descriptions
Bit
Field
Value
31-20
Reserved
19-0
COUNT0 SEED
0
Description
Reads return 0. Writes have no effect.
Seed value for DCC counter0.
Reads in any operating mode return the current value of counter0.
Writing in privileged mode only sets the current seed value for counter0.
NOTE: Seed for Counter0 must be non-zero
The DCC must only be enabled after programming a non-zero value in the COUNT0 SEED
register.
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11.4.4 DCC Valid0 Seed Register (DCCVALID0SEED)
Figure 11-10 and Table 11-5 describe the DCC Valid0 Seed register.
Figure 11-10. DCC Valid0 Seed Register (DCCVALID0SEED) [offset = Ch]
31
16
Reserved
R-0
15
0
VALID0 SEED
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 11-5. DCC Valid0 Seed Register (DCCVALID0SEED) Field Descriptions
Bit
Field
Value
31-16
Reserved
0
15-0
VALID0 SEED
Description
Reads return 0. Writes have no effect.
Seed value for DCC Valid0. This value defines the window within which the counter1 must
reach 0. This window needs to be at least 4 cycles wide.
Reads in any operating mode return the current value of seed for Valid0.
Writing in privileged mode only sets the current seed value for Valid0. Writes in user mode are
ignored.
NOTE: Seed for Valid0 must be at least 0x4
The DCC must only be enabled after programming a value greater than or equal to 0x4 in
the VALID0 SEED register.
11.4.5 DCC Counter1 Seed Register (DCCCNT1SEED)
Figure 11-11 and Table 11-6 describe the DCC Counter1 Seed register.
Figure 11-11. DCC Counter1 Seed Register (DCCCNT1SEED) [offset = 10h]
31
20
19
16
Reserved
COUNT1 SEED
R-0
R/WP-0
15
0
COUNT1 SEED
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 11-6. DCC Counter1 Seed Register (DCCCNT0SEED) Field Descriptions
Bit
Field
Value
31-20
Reserved
0
19-0
COUNT1 SEED
Description
Reads return 0. Writes have no effect.
Seed value for DCC counter1.
Reads in any operating mode return the current value of seed for counter1.
Writing in privileged mode only sets the current seed value for counter1. Writes in user mode
are ignored.
NOTE: Seed for Counter0 must be non-zero
The DCC must only be enabled after programming a non-zero value in the COUNT1 SEED
register.
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11.4.6 DCC Status Register (DCCSTAT)
Figure 11-7 and Table 11-2 describe the DCC Status register.
Figure 11-12. DCC Status Register (DCCSTAT) [offset = 14h]
31
16
Reserved
R-0
15
1
0
Reserved
2
DONE
ERR
R-0
R/W1CP-0
R/W1CP-0
LEGEND: R/W = Read/Write; R = Read only; W1CP = Write 1 to clear in privilege mode only; -n = value after reset
Table 11-7. DCC Status Register (DCCSTAT) Field Descriptions
Bit
31-2
1
Field
Value
Reserved
0
DONE
Description
Reads return 0. Writes have no effect.
Single-Shot Sequence Done flag. Indicates that a single-shot DCC sequence is done without any
error.
0
Read: Single-shot sequence is not done.
Write: Writing 0 has no effect.
1
Read: Single-shot sequence is done without any error.
Write: Writing 1 in privileged mode clears the DONE flag.
0
ERR
Error flag. Indicates that a DCC error has occurred.
0
Read: DCC error has not occurred.
Write: Writing 0 has no effect.
1
Read: An error has occurred.
Write: Writing 1 in privileged mode clears the ERR flag.
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11.4.7 DCC Counter0 Value Register (DCCCNT0)
Figure 11-13 and Table 11-8 describe the DCC Counter0 Value register.
Figure 11-13. DCC Counter0 Value Register (DCCCNT0) [offset = 18h]
31
20
19
16
Reserved
COUNT0
R-0
R-0
15
0
COUNT0
R-0
LEGEND: R = Read only; -n = value after reset
Table 11-8. DCC Counter0 Value Register (DCCCNT0) Field Descriptions
Bit
Field
31-20
Reserved
19-0
COUNT0
Value
0
Description
Reads return 0. Writes have no effect.
Current value of DCC counter0.
Reads in any operating mode return the current value of counter0.
Writes have no effect.
NOTE: Reads may not return exact current value of counter
Reading the counter0 value while counting is enabled may not return the exact value of the
counter0.
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11.4.8 DCC Valid0 Value Register (DCCVALID0)
Figure 11-14 and Table 11-9 describe the DCC Valid0 Value register.
Figure 11-14. DCC Valid0 Value Register (DCCVALID0) [offset = 1Ch]
31
16
Reserved
R-0
15
0
VALID0
R-0
LEGEND: R = Read only; -n = value after reset
Table 11-9. DCC Valid0 Value Register (DCCVALID0) Field Descriptions
Bit
Field
31-16
Reserved
15-0
VALID0
Value
0
Description
Reads return 0. Writes have no effect.
Current value for DCC Valid0.
Reads in any operating mode return the current value of Valid0.
Writes have no effect.
NOTE: Reads may not return exact current value of Valid0
Reading the Valid0 value while counting is enabled may not return the exact value of the
Valid0.
11.4.9 DCC Counter1 Value Register (DCCCNT1)
Figure 11-15 and Table 11-10 describe the DCC Counter1 Value register.
Figure 11-15. DCC Counter1 Value Register (DCCCNT1) [offset = 20h]
31
20
19
16
Reserved
COUNT1
R-0
R/WP-0
15
0
COUNT1
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 11-10. DCC Counter1 Value Register (DCCCNT1) Field Descriptions
Bit
Field
31-20
Reserved
19-0
COUNT1
Value
0
Description
Reads return 0. Writes have no effect.
Current value for DCC counter1.
Reads in any operating mode return the current value of counter1.
Writes have no effect.
NOTE: Reads may not return exact current value of counter
Reading the counter1 value while counting is enabled may not return the exact value of the
counter1.
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11.4.10 DCC Counter1 Clock Source Selection Register (DCCCNT1CLKSRC)
Figure 11-15 and Table 11-10 describe the DCC Counter1 Clock Source Selection register.
Figure 11-16. DCC Counter1 Clock Source Selection Register (DCCCNT1CLKSRC) [offset = 24h]
31
16
Reserved
R-0
15
12
11
4
3
0
KEY
Reserved
CNT1 CLKSRC
R/WP-5h
R-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 11-11. DCC Counter1 Clock Source Selection Register (DCCCNT1CLKSRC)
Field Descriptions
Bit
Field
31-16 Reserved
Value
0
15-12 KEY
Description
Reads return 0. Writes have no effect.
Key to enable clock source selection for counter1.
Reads in any operating mode return the current value of the key.
Writes in privileged mode set the key value.
Ah
Writing Ah as the key enables the CNT1 CLKSRC field to define the clock source for
counter1.
Any other value Writing any other value as the key disables the clock source selection for counter1. In this
case, the N2HET signal is used as the source for counter1.
Refer to the device datasheet for available clock source options and the KEY required to
enable these options for counter1.
11-4
Reserved
3-0
CNT1 CLKSRC
0
Reads return 0. Writes have no effect.
Clock source for counter1 when KEY is programmed to Ah.
Reads in any operating mode return the current value of CLKSRC.
Writes in privileged mode select the clock source for counter1.
Refer to the device datasheet for available clock source options and the KEY required to
enable these options for counter1.
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11.4.11 DCC Counter0 Clock Source Selection Register (DCCCNT0CLKSRC)
Figure 11-15 and Table 11-10 describe the DCC Counter0 Clock Source Selection register.
Figure 11-17. DCC Counter0 Clock Source Selection Register (DCCCNT0CLKSRC) [offset = 28h]
31
16
Reserved
R-0
15
4
3
0
Reserved
CNT0 CLKSRC
R-0
R/WP-5h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 11-12. DCC Counter0 Clock Source Selection Register (DCCCNT0CLKSRC)
Field Descriptions
Bit
Field
31-4
Reserved
3-0
CNT0 CLKSRC
Value
0
Description
Reads return 0. Writes have no effect.
Clock source for counter0 .
Reads in any operating mode return the current value of CLKSRC.
Writes in privileged mode select the clock source for counter0.
Refer to the device datasheet for available clock source options for counter0.
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Chapter 12
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Error Signaling Module (ESM)
This chapter provides the details of the error signaling module (ESM) that aggregates device errors and
provides the capability to define internal and external error response based on error severity.
Topic
12.1
12.2
12.3
12.4
412
...........................................................................................................................
Overview ........................................................................................................
Module Operation ............................................................................................
Recommended Programming Procedure ............................................................
Control Registers ............................................................................................
Error Signaling Module (ESM)
Page
413
415
419
420
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12.1 Overview
The Error Signaling Module (ESM) collects and reports the various error conditions on the microcontroller.
The error condition is categorized based on a severity level. Error response is then generated based on
the category of the error. Possible error responses include a low-priority interrupt, high-priority interrupt,
and an external pin action.
12.1.1 Features
•
•
•
•
Up to 128 error channels are supported, divided into 3 different groups:
– 64 Group1 (low-severity) channels with configurable interrupt generation and configurable ERROR
pin behavior
– 32 Group2 (high-severity) channels with predefined interrupt generation and predefined ERROR pin
behavior
– 32 Group3 (high-severity) channels with no interrupt generation and predefined ERROR pin
behavior. These channels have no interrupt response as they are reserved for CPU based
diagnostics that generate aborts directly to the CPU.
Dedicated device ERROR pin to signal an external observer
Configurable timebase for ERROR pin output
Error forcing capability for latent fault testing
12.1.2 Block Diagram
As shown in Figure 12-1, the ESM channels are divided into three groups. Group1 channels are
considered to be low-severity. Group1 errors have a configurable interrupt response and configurable
ERROR pin behavior. Note that the ESM Status Register 1 (ESMSR1) for error group1 gets updated,
regardless of whether an ESM interrupt for that Group1 channel is enabled or not. Group2 channels are
connected to higher-severity error signals. Group2 errors generate a non-maskable high-priority interrupt
to the CPU and assert the ERROR pin. Group3 channels indicate errors of the highest severity. Check the
specific part's datasheet for identifying group3 errors and their expected responses. Group3 errors always
generate an ERROR pin output.
The ESM interrupt and ERROR pin behavior are also summarized in Table 12-1.
Figure 12-1. Block Diagram
Low-Priority
Interrupt
High-Priority
Interrupt Handling
High-Priority
Interrupt
error_group1
Interrupt Enable
Interrupt Priority
from Hardware Diagnostics
error_group2
ERROR Pin Enable
error_group3
Error Signal
Handling
to VIM Interrupt Controller
Low-Priority
Interrupt Handling
Device
ERROR Output
PIN
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Table 12-1. ESM Interrupt and ERROR Pin Behavior
Error Group
Interrupt to CPU
Interrupt Priority
ERROR Pin Response
1
Can be enabled or disabled for each
channel
Can be selected as low/high-priority
for each channel
ERROR pin action can be selected
for each channel separately
2
Cannot be disabled
High priority
ERROR pin is asserted
3
No interrupt
NA
ERROR pin is asserted
Figure 12-2 and Figure 12-3 show the interrupt response handling and ERROR pin response handling
with register configuration. The total active time of the ERROR pin is controlled by the Low-Time Counter
Preload register (LTCP) and the key register (ESMEPSR) as shown in Figure 12-3. See Section 12.2.2 for
details.
Figure 12-2. Interrupt Response Handling
Low-Priority
Interrupt
High-Priority
Interrupt Handling
High-Priority
Interrupt
error_group1
Interrupt Enable
Controlled by:
ESMIESR1
ESMIECR1
ESMIESR4
ESMIECR4
error_group2
Interrupt Priority
Controlled by:
ESMILSR1
ESMILCR1
ESMILSR4
ESMILCR4
to VIM Interrupt Controller
Low-Priority
Interrupt Handling
Figure 12-3. ERROR Pin Response Handling
Peripheral clock (VCLK)
error_group1
ERROR Pin Enable
Controlled by:
ESMIEPSR1,
ESMIEPCR1
ESMIEPSR4,
ESMIEPCR4
Error Signal
Control
Low-Time
Counter Preload
(LTCP )
error_group2
Low-Time
Counter
(LTC)
error_group3
ERROR
Device
Output
PIN
ESMEPSR
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12.2 Module Operation
This device has 128 error channels, divided into 3 different error groups. Please refer to the device
datasheet for ESM channel assignment details.
The ESM module has error flags for each error channel. The error status registers ESMSR1, ESMSR4,
ESMSR2, ESMSR3 provide status information on a pending error of Group1 (Channel 0-31), Group1
(Channel 32-63), Group2, and Group3, respectively. The ESMEPSR register provides the current ERROR
status. The module also provides a status shadow register, ESMSSR2, which maintains the error flags of
Group2 until power-on reset (PORRST) is asserted. See Section 12.2.1 for details of their behavior during
power on reset and warm reset.
Once an error occurs, the ESM module will set the corresponding error flags. In addition, it can trigger an
interrupt, ERROR pin outputs low depending on the ESM settings. Once the ERROR pin outputs low, a
power on reset or a write of 5h to ESMEKR is required to release the ESM error pin back to normal state.
See Section 12.2.2 for details. The application can read the error status registers (ESMSR1, ESMSR4,
ESMSR2, and ESMSR3) to debug the error. If an RST is triggered or the error interrupt has been served,
the error flag of Group2 should be read from ESMSSR2 because the error flag in ESMSR2 will be cleared
by RST.
The user can also test the functionality of the ERROR pin by forcing an error. See Section 12.2.3 for
details.
12.2.1 Reset Behavior
Power on reset:
• ERROR pin behavior
When PORRST is active, the ERROR pin is in a high impedance state (output drivers disabled).
• Register behavior
After PORRST, all registers in ESM module will be re-initialized to the default value. All the error status
registers are cleared to zero.
Warm reset (RST):
• ERROR pin behavior
During RST, the ERROR pin is in “output active” state with pull-down disabled. The ERROR pin
remains unchanged after RST.
• Register behavior
After RST, ESMSR1, ESMSR4, ESMSSR2, ESMSR3 and ESMEPSR register values remains unchanged. Since RST does not clear the critical failure registers, the user can read those registers to
debug the failures after RST pin goes back to high.
After RST, if one of the flags in ESMSR1 and ESMSR4 is set, the interrupt service routine will be
called once the corresponding interrupt is enabled.
NOTE: ESMSR2 is cleared after RST. The flag in ESMSR2 gets cleared when reading the
appropriate vector in the ESMIOFFHR offset register. Reading ESMIOFFHR will not clear the
ESMSR1, ESMSR4, and the shadow register ESMSSR2. Reading ESMIOFFLR will also not
clear the ESMSR1 and ESMSR4.
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12.2.2 ERROR Pin Timing
The ERROR pin is an active-low function. The state of the pin is also readable from ERROR Pin Status
Register (ESMEPSR). The pin is in a high-impedance state during power-on reset. Once the ESM module
drives the ERROR pin low, it remains in this state for the time specified by the Low-Time Counter Preload
register (LTCPR). Based on the time period of the peripheral clock (VCLK), the total active time of the
ERROR pin can be calculated as:
t ERROR _ low = tVCLK ´ ( LTCP + 1)
(22)
Once this period expires, the ERROR pin is set to high in case the reset of the ERROR pin was
requested. This request is done by writing an appropriate key (5h) to the key register (ESMEKR) during
the ERROR pin low time. Here are a few examples:
Example 1: ESM detects a failure and drives the ERROR pin low. No ERROR pin reset is requested. The
ERROR pin continues outputting low until power on reset occurs.
Figure 12-4. ERROR Pin Timing - Example 1
failure
ERROR
tERROR_low
Example 2: ESM detects a failure and drives the ERROR pin low. An ERROR pin reset request is
received before tERROR_low expires. In this case, the ERROR pin is set to high immediately after tERROR_low
expires.
Figure 12-5. ERROR Pin Timing - Example 2
failure
ERROR
ERROR pin reset request
tERROR_low
Example 3: ESM detects a failure and drives the ERROR pin low. An ERROR pin reset request is
received after tERROR_low expires. In this case, the ERROR pin is set to high immediately after ERROR pin
reset request is received.
Figure 12-6. ERROR Pin Timing - Example 3
failure
ERROR
416
ERROR pin reset request
tERROR_low
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Example 4: ESM detects a failure and drives the ERROR pin low. Another failure occurs within the time
the pin stays low. In this case, the low-time counter will be reset when the other failure occurs. In other
words, tERROR_low should be counted from whenever the most recent failure occurs.
Figure 12-7. ERROR Pin Timing - Example 4
ERROR pin reset request
failure failure
ERROR
tERROR_low
tERROR_low
Example 5: The reset of the ERROR pin was requested by the software even before the failure occurs. In
this case, the ERROR pin is set to high immediately after tERROR_low expires. This case is not recommended
and should be avoided by the application.
Figure 12-8. ERROR Pin Timing - Example 5
ERROR pin reset request
ERROR
failure
tERROR_low
Example 6: Failure1, then ERROR pin reset request, then Failure2 occurs before ERROR pin gets reset.
In this case, the ERROR pin low-time is just extended (restarted) when the failure2 occurs and goes high
when this count-down expires. There now is a scenario where the ERROR pin is high and the group2/3
status flag is set. To avoid this scenario, the application must write 5h followed by 0 to the ESM Error Key
Register (ESMEKR). In this case, the ERROR pin will go high and then go low again to indicate the
second failure.
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12.2.3 Forcing an Error Condition
The error response generation mechanism is testable by software by forcing an error condition. This
allows testing the ERROR pin functionality. By writing a dedicated key to the ESM Error Key Register
(ESMEKR), the ERROR pin is set to low for the specified time. The following steps describe how to force
an error condition:
1. Check ERROR Pin Status Register (ESMEPSR). This register must be 1 to switch into the error forcing
mode.
The ESM module cannot be switched into the error forcing mode if a failure has already been detected
in functional mode. The application command to switch to error forcing mode is ignored.
2. Write 5h to the ESM Error Key Register (ESMEKR). After that, the ERROR pin should output low (error
force mode).
Once the application puts the ESM module in the error forcing mode, the ERROR pin cannot indicate
the normal error functionality. If a failure occurs during this time, it gets still latched and the LTC is
reset and stopped. The error output pin is already driven low on account of the error forcing mode.
When the ESM is forced back to normal functional mode, the LTC becomes active and forces the
ERROR pin low until the expiration of the LTC (see Figure 12-9).
3. Write 0 to the ESM Error Key Register (ESMEKR) back to the active normal mode.
If there are no errors detected while the ESM module is in the error forcing mode, the ERROR pin
goes high immediately after exiting the error forcing mode.
Figure 12-9. ERROR Pin Timing - Example 7
failure
Write “1010” to ESMEKR
Write “0101” to ESMEKR
Write “0” to ESMEKR
ERROR
418
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12.3 Recommended Programming Procedure
During the initialization stage, the application code should follow the recommendations in Figure 12-10 to
initialize the ESM.
Figure 12-10. ESM Initialization
Power up or PORRST
Force error on ERROR pin to check the functionality of ERROR pin and external monitoring
device connected to ERROR pin (ESMEKR).
Initialize VIM RAM. Map the ESM low priority interrupt service routine and high priority interrupt
service routine to pre-defined device specific interrupt channel. (Refer to device specific datasheet.)
Enable the interrupt in VIM and CPU.
Map ESM interrupt to high/low (ESM Group1 only, see register
ESMILSR1,ESMILCR1, ESMILSR4, and ESMILCR4).
Enable ESM interrupt and influence on ERROR pin (ESM Group1 only, see register ESMIEPSR1,
ESMIEPCR1, ESMIESR1,ESMIECR1, ESMIEPSR4, ESMIEPCR4, ESMIESR4, and ESMIECR4).
Define ESM Low-Time Counter Preload Register ESMLTCPR to determine the ERROR pin
low time in case an error occurs.
Once an error occurs, it can trigger an interrupt, ERROR pin outputs low depending on the ESM settings.
Once the ERROR pin outputs low, a power on reset or a write of 5h to ESMEKR is required to release the
ESM back to normal state. The application can read the error status registers (ESMSR1, ESMSR4,
ESMSR2, and ESMSR3) to debug the error. If an RST is triggered or the error interrupt has been served,
the error flag of Group2 should be read from ESMSSR2 because the error flag in ESMSR2 will be cleared
by RST.
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12.4 Control Registers
This section describes the ESM registers. Each register begins on a 32-bit word boundary. The registers
support 32-bit, 16-bit, and 8-bit accesses. The base address for the registers is FFFF F500h.
Table 12-2. ESM Module Registers
Address
420
Acronym
Register Description
FFFF F500h
ESMEEPAPR1
ESM Enable ERROR Pin Action/Response Register 1
Section 12.4.1
Section
FFFF F504h
ESMDEPAPR1
ESM Disable ERROR Pin Action/Response Register 1
Section 12.4.2
FFFF F508h
ESMIESR1
ESM Interrupt Enable Set Register 1
Section 12.4.3
FFFF F50Ch
ESMIECR1
ESM Interrupt Enable Clear Register 1
Section 12.4.4
FFFF F510h
ESMILSR1
Interrupt Level Set Register 1
Section 12.4.5
FFFF F514h
ESMILCR1
Interrupt Level Clear Register 1
Section 12.4.6
FFFF F518h
ESMSR1
ESM Status Register 1
Section 12.4.7
FFFF F51Ch
ESMSR2
ESM Status Register 2
Section 12.4.8
FFFF F520h
ESMSR3
ESM Status Register 3
Section 12.4.9
FFFF F524h
ESMEPSR
ESM ERROR Pin Status Register
Section 12.4.10
FFFF F528h
ESMIOFFHR
ESM Interrupt Offset High Register
Section 12.4.11
FFFF F52Ch
ESMIOFFLR
ESM Interrupt Offset Low Register
Section 12.4.12
FFFF F530h
ESMLTCR
ESM Low-Time Counter Register
Section 12.4.13
FFFF F534h
ESMLTCPR
ESM Low-Time Counter Preload Register
Section 12.4.14
FFFF F538h
ESMEKR
ESM Error Key Register
Section 12.4.15
FFFF F53Ch
ESMSSR2
ESM Status Shadow Register 2
Section 12.4.16
FFFF F540h
ESMIEPSR4
ESM Influence ERROR Pin Set Register 4
Section 12.4.17
FFFF F544h
ESMIEPCR4
ESM Influence ERROR Pin Clear Register 4
Section 12.4.18
FFFF F548h
ESMIESR4
ESM Interrupt Enable Set Register 4
Section 12.4.19
FFFF F54Ch
ESMIECR4
ESM Interrupt Enable Clear Register 4
Section 12.4.20
FFFF F550h
ESMILSR4
Interrupt Level Set Register 4
Section 12.4.21
FFFF F554h
ESMILCR4
Interrupt Level Clear Register 4
Section 12.4.22
FFFF F558h
ESMSR4
ESM Status Register 4
Section 12.4.23
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12.4.1 ESM Enable ERROR Pin Action/Response Register 1 (ESMEEPAPR1)
This register is dedicated for Group1.
Figure 12-11. ESM Enable ERROR Pin Action/Response Register 1 (ESMEEPAPR1)
[address = FFFF F500h]
31
16
IEPSET
R/WP-0
15
0
IEPSET
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 12-3. ESM Enable ERROR Pin Action/Response Register 1 (ESMEEPAPR1)
Field Descriptions
Bit
31-0
Field
Value
IEPSET
Description
Enable ERROR Pin Action/Response on Group 1.
Read in User and Privileged mode. Write in Privileged mode only.
0
Read: Failure on channel x has no influence on ERROR pin.
Write: Leaves the bit and the corresponding clear bit in the ESMIEPCR1 register unchanged.
1
Read: Failure on channel x has influence on ERROR pin.
Write: Enables failure influence on ERROR pin and sets the corresponding clear bit in the
ESMIEPCR1 register.
12.4.2 ESM Disable ERROR Pin Action/Response Register 1 (ESMDEPAPR1)
This register is dedicated for Group1.
Figure 12-12. ESM Disable ERROR Pin Action/Response Register 1 (ESMDEPAPR1)
[address = FFFF F504h]
31
16
IEPCLR
R/WP-0
15
0
IEPCLR
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 12-4. ESM Disable ERROR Pin Action/Response Register 1 (ESMDEPAPR1)
Field Descriptions
Bit
31-0
Field
Value
IEPCLR
Description
Disable ERROR Pin Action/Response on Group 1.
Read in User and Privileged mode. Write in Privileged mode only.
0
Read: Failure on channel x has no influence on ERROR pin.
Write: Leaves the bit and the corresponding set bit in the ESMIEPSR1 register unchanged.
1
Read: Failure on channel x has influence on ERROR pin.
Write: Disables failure influence on ERROR pin and clears the corresponding set bit in the
ESMIEPSR1 register.
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12.4.3 ESM Interrupt Enable Set Register 1 (ESMIESR1)
This register is dedicated for Group1.
Figure 12-13. ESM Interrupt Enable Set Register 1 (ESMIESR1)
[address = FFFF F508h]
31
16
INTENSET
R/WP-0
15
0
INTENSET
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 12-5. ESM Interrupt Enable Set Register 1 (ESMIESR1) Field Descriptions
Bit
31-0
Field
Value
INTENSET
Description
Set interrupt enable.
Read in User and Privileged mode. Write in Privileged mode only.
0
Read: Interrupt is disabled.
Write: Leaves the bit and the corresponding clear bit in the ESMIECR1 register unchanged.
1
Read: Interrupt is enabled.
Write: Enables interrupt and sets the corresponding clear bit in the ESMIECR1 register.
12.4.4 ESM Interrupt Enable Clear Register 1 (ESMIECR1)
This register is dedicated for Group1.
Figure 12-14. ESM Interrupt Enable Clear Register 1 (ESMIECR1)
[address = FFFF F50Ch]
31
16
INTENCLR
R/WP-0
15
0
INTENCLR
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 12-6. ESM Interrupt Enable Clear Register 1 (ESMIECR1) Field Descriptions
Bit
31-0
Field
Value
INTENCLR
Description
Clear interrupt enable.
Read in User and Privileged mode. Write in Privileged mode only.
0
Read: Interrupt is disabled.
Write: Leaves the bit and the corresponding set bit in the ESMIESR1 register unchanged.
1
Read: Interrupt is enabled.
Write: Disables interrupt and clears the corresponding set bit in the ESMIESR1 register.
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12.4.5 ESM Interrupt Level Set Register 1 (ESMILSR1)
This register is dedicated for Group1.
Figure 12-15. ESM Interrupt Level Set Register 1 (ESMILSR1)
[address = FFFF F510h]
31
16
INTLVLSET
R/WP-0
15
0
INTLVLSET
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 12-7. ESM Interrupt Level Set Register 1 (ESMILSR1) Field Descriptions
Bit
31-0
Field
Value
INTLVLSET
Description
Set interrupt priority.
Read in User and Privileged mode. Write in Privileged mode only.
0
Read: Interrupt of channel x is mapped to low-level interrupt line.
Write: Leaves the bit and the corresponding clear bit in the ESMILCR1 register unchanged.
1
Read: Interrupt of channel x is mapped to high-level interrupt line.
Write: Maps interrupt of channel x to high-level interrupt line and sets the corresponding clear bit in
the ESMILCR1 register.
12.4.6 ESM Interrupt Level Clear Register 1 (ESMILCR1)
This register is dedicated for Group1.
Figure 12-16. ESM Interrupt Level Clear Register 1 (ESMILCR1)
[address = FFFF F514h]
31
16
INTLVLCLR
R/WP-0
15
0
INTLVLCLR
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 12-8. ESM Interrupt Level Clear Register 1 (ESMILCR1) Field Descriptions
Bit
31-0
Field
Value
INTLVLCLR
Description
Clear interrupt priority.
Read in User and Privileged mode. Write in Privileged mode only.
0
Read: Interrupt of channel x is mapped to low-level interrupt line.
Write: Leaves the bit and the corresponding set bit in the ESMILSR1 register unchanged.
1
Read: Interrupt of channel x is mapped to high-level interrupt line.
Write: Maps interrupt of channel x to low-level interrupt line and clears the corresponding set bit in
the ESMILSR1 register.
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12.4.7 ESM Status Register 1 (ESMSR1)
This register is dedicated for Group1. Note that the ESMSR1 status register will get updated if an error
condition occurs, regardless if the corresponding interrupt enable flag is set or not.
Figure 12-17. ESM Status Register 1 (ESMSR1)
[address = FFFF F518h]
31
16
ESF
R/W1CP-X/0
15
0
ESF
R/W1CP-X/0
LEGEND: R/W = Read/Write; W1CP = Write 1 to clear in privilege mode only; -n = value after reset/PORRST; X = Value unchanged
Table 12-9. ESM Status Register 1 (ESMSR1) Field Descriptions
Bit
Field
31-0
ESF
Value
Description
Error Status Flag. Provides status information on a pending error.
Read in User and Privileged mode. Write in Privileged mode only.
0
Read: No error occurred; no interrupt is pending.
Write: Leaves the bit unchanged.
1
Read: Error occurred; interrupt is pending.
Write: Clears the bit.
Note: After RST, if one of these flags are set and the corresponding interrupt are enabled, the
interrupt service routine will be called.
12.4.8 ESM Status Register 2 (ESMSR2)
This register is dedicated for Group2.
Figure 12-18. ESM Status Register 2 (ESMSR2)
[address = FFFF F51Ch]
31
16
ESF
R/W1CP-0
15
0
ESF
R/W1CP-0
LEGEND: R/W = Read/Write; W1CP = Write 1 to clear in privilege mode only; -n = value after reset
Table 12-10. ESM Status Register 2 (ESMSR2) Field Descriptions
Bit
Field
31-0
ESF
Value
Description
Error Status Flag. Provides status information on a pending error.
Read in User and Privileged mode. Write in Privileged mode only.
0
Read: No error occurred; no interrupt is pending.
Write: Leaves the bit unchanged.
1
Read: Error occurred; interrupt is pending.
Write: Clears the bit. ESMSSR2 is not impacted by this action.
Note: In normal operation, the flag gets cleared when reading the appropriate vector in the
ESMIOFFHR offset register. Reading ESMIOFFHR will not clear the ESMSR1 and the shadow
register ESMSSR2.
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12.4.9 ESM Status Register 3 (ESMSR3)
This register is dedicated for Group3.
Figure 12-19. ESM Status Register 3 (ESMSR3)
[address = FFFF F520h]
31
16
ESF
R/W1CP-X/0
15
0
ESF
R/W1CP-X/0
LEGEND: R/W = Read/Write; W1CP = Write 1 to clear in privilege mode only; -n = value after reset/PORRST; X = Value unchanged
Table 12-11. ESM Status Register 3 (ESMSR3) Field Descriptions
Bit
Field
31-0
ESF
Value
Description
Error Status Flag. Provides status information on a pending error.
Read in User and Privileged mode. Write in Privileged mode only.
0
Read: No error occurred.
Write: Leaves the bit unchanged.
1
Read: Error occurred.
Write: Clears the bit.
12.4.10 ESM ERROR Pin Status Register (ESMEPSR)
Figure 12-20. ESM ERROR Pin Status Register (ESMEPSR)
[address = FFFF F524h]
31
16
Reserved
R-0
15
1
0
Reserved
EPSF
R-0
R-X/1
LEGEND: R = Read only; -n = value after reset/PORRST; X = Value unchanged
Table 12-12. ESM ERROR Pin Status Register (ESMEPSR) Field Descriptions
Bit
31-1
0
Field
Value
Reserved
0
EPSF
Description
Reads return 0. Writes have no effect.
ERROR Pin Status Flag. Provides status information for the ERROR pin.
Read/Write in User and Privileged mode.
0
Read: ERROR pin is low (active) if any error has occurred.
Write: Writes have no effect.
1
Read: ERROR pin is high if no error has occurred.
Write: Writes have no effect.
Note: This flag will be set to 1 after PORRST. The value will be unchanged after RST. The ERROR
pin status remains unchanged after RST.
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12.4.11 ESM Interrupt Offset High Register (ESMIOFFHR)
Figure 12-21. ESM Interrupt Offset High Register (ESMIOFFHR)
[address = FFFF F528h]
31
16
Reserved
R-0
15
7
6
0
Reserved
INTOFFH
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 12-13. ESM Interrupt Offset High Register (ESMIOFFHR) Field Descriptions
Bit
Field
31-7
Reserved
6-0
INTOFFH
Value
0
Description
Reads return 0. Writes have no effect.
Offset High-Level Interrupt. This vector gives the channel number of the highest-pending interrupt
request for the high-level interrupt line. Interrupts of error Group2 have higher priority than
interrupts of error Group1. Inside a group, channel 0 has highest priority and channel 31 has lowest
priority.
User and privileged mode (read):
Returns number of pending interrupt with the highest priority for the high-level interrupt line.
0
No pending interrupt.
1h
Interrupt pending for channel 0, error Group1.
:
:
20h
Interrupt pending for channel 31, error Group1.
21h
Interrupt pending for channel 0, error Group2.
:
:
40h
Interrupt pending for channel 31, error Group2.
41h
Interrupt pending for channel 32, error Group1.
:
60h
:
Interrupt pending for channel 63, error Group1.
Note: Reading the interrupt vector will clear the corresponding flag in the ESMSR2 register; will not
clear ESMSR1 and ESMSSR2 and the offset register gets updated.
User and privileged mode (write):
Writes have no effect.
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12.4.12 ESM Interrupt Offset Low Register (ESMIOFFLR)
Figure 12-22. ESM Interrupt Offset Low Register (ESMIOFFLR)
[address = FFFF F52Ch]
31
16
Reserved
R-0
15
7
6
0
Reserved
INTOFFL
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 12-14. ESM Interrupt Offset Low Register (ESMIOFFLR) Field Descriptions
Bit
Field
31-7
Reserved
6-0
INTOFFL
Value
0
Description
Reads return 0. Writes have no effect.
Offset Low-Level Interrupt. This vector gives the channel number of the highest-pending interrupt
request for the low-level interrupt line. Inside a group, channel 0 has highest priority and channel 31
has lowest priority.
User and privileged mode (read):
Returns number of pending interrupt with the highest priority for the low-level interrupt line.
0
No pending interrupt.
1h
Interrupt pending for channel 0, error Group1.
:
20h
:
Interrupt pending for channel 31, error Group1.
21h-40h Reserved
41h
:
60h
Interrupt pending for channel 32, error Group1.
:
Interrupt pending for channel 63, error Group1.
Note: Reading the interrupt vector will not clear the corresponding flag in the ESMSR1 register.
Group2 interrupts are fixed to the high-level interrupt line only.
User and privileged mode (write):
Writes have no effect.
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12.4.13 ESM Low-Time Counter Register (ESMLTCR)
Figure 12-23. ESM Low-Time Counter Register (ESMLTCR)
[address = FFFF F530h]
31
16
Reserved
R-0
15
0
LTC
R-3FFFh
LEGEND: R = Read only; -n = value after reset
Table 12-15. ESM Low-Time Counter Register (ESMLTCR) Field Descriptions
Bit
Field
Value
31-16
Reserved
15-0
LTC
0
Description
Reads return 0. Writes have no effect.
ERROR Pin Low-Time Counter
16-bit preloadable down-counter to control low-time of ERROR pin. The low-time counter is
triggered by the peripheral clock (VCLK).
Note: Low-time counter is set to the default preload value of the ESMLTCPR in the following cases:
1.
2.
3.
Reset (power on reset or warm reset)
An error occurs
User forces an error
12.4.14 ESM Low-Time Counter Preload Register (ESMLTCPR)
Figure 12-24. ESM Low-Time Counter Preload Register (ESMLTCPR)
[address = FFFF F534h]
31
16
Reserved
R-0
15
14
13
0
LTCP
LTCP
R/WP-0
R-3FFFh
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 12-16. ESM Low-Time Counter Preload Register (ESMLTCPR) Field Descriptions
Bit
Field
31-16
Reserved
15-0
LTCP
Value
0
0-FFFFh
Description
Reads return 0. Writes have no effect.
ERROR Pin Low-Time Counter Pre-load Value
16-bit preload value for the ERROR pin low-time counter. Defines the minimum period for which
the ERROR pin will be driven to 16384 VCLK cycles.
Note: Only LTCP[15] and LTCP[14] are configurable (privileged mode write).
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12.4.15 ESM Error Key Register (ESMEKR)
Figure 12-25. ESM Error Key Register (ESMEKR)
[address = FFFF F538h]
31
16
Reserved
R-0
15
4
3
0
Reserved
EKEY
R-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 12-17. ESM Error Key Register (ESMEKR) Field Descriptions
Bit
Field
31-4
Reserved
3-0
EKEY
Value
Description
0
Reads return 0. Writes have no effect.
Error Key. The key to reset the ERROR pin or to force an error on the ERROR pin.
User and privileged mode (read):
Returns current value of the EKEY.
Privileged mode (write):
0
Activates normal mode (recommended default mode).
5h
The ERROR pin set to high when the low-time counter (LTC) has completed; then the EKEY
bit will switch back to normal mode (EKEY = 0000).
Ah
Forces error on ERROR pin.
All other values
Activates normal mode.
12.4.16 ESM Status Shadow Register 2 (ESMSSR2)
This register is dedicated for Group2.
Figure 12-26. ESM Status Shadow Register 2 (ESMSSR2)
[address = FFFF F53Ch]
31
16
ESF
R/W1CP-X/0
15
0
ESF
R/W1CP-X/0
LEGEND: R/W = Read/Write; W1CP = Write 1 to clear in privilege mode only; -n = value after reset/PORRST; X = Value unchanged
Table 12-18. ESM Status Shadow Register 2 (ESMSSR2) Field Descriptions
Bit
Field
31-0
ESF
Value
Description
Error Status Flag. Shadow register for status information on pending error.
Read in User and Privileged mode. Write in Privileged mode only.
0
Read: No error occurred.
Write: Leaves the bit unchanged.
1
Read: Error occurred.
Write: Clears the bit. ESMSR2 is not impacted by this action.
Note: Errors are stored until they are cleared by the software or at power-on reset (PORRST).
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12.4.17 ESM Influence ERROR Pin Set Register 4 (ESMIEPSR4)
This register is dedicated for Group1.
Figure 12-27. ESM Influence ERROR Pin Set Register 4 (ESMIEPSR4)
[address = FFFF F540h]
31
16
IEPSET[63:48]
R/WP-0
15
0
IEPSET[47:32]
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 12-19. ESM Influence ERROR Pin Set Register 4 (ESMIEPSR4) Field Descriptions
Bit
63-32
Field
Value
IEPSET
Description
Set influence on ERROR pin.
Read in User and Privileged mode. Write in Privileged mode only.
0
Read: Failure on channel x has no influence on ERROR pin.
Write: Leaves the bit and the corresponding clear bit in the ESMIEPCR4 register unchanged.
1
Read: Failure on channel x has influence on ERROR pin.
Write: Enables failure influence on ERROR pin and sets the corresponding clear bit in the
ESMIEPCR4 register.
12.4.18 ESM Influence ERROR Pin Clear Register 4 (ESMIEPCR4)
This register is dedicated for Group1.
Figure 12-28. ESM Influence ERROR Pin Clear Register 4 (ESMIEPCR4)
[address = FFFF F544h]
31
16
IEPCLR[63:48]
R/WP-0
15
0
IEPCLR[47:32]
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 12-20. ESM Influence ERROR Pin Clear Register 4 (ESMIEPCR4) Field Descriptions
Bit
63-32
Field
Value
IEPCLR
Description
Clear influence on ERROR pin.
Read in User and Privileged mode. Write in Privileged mode only.
0
Read: Failure on channel x has no influence on ERROR pin.
Write: Leaves the bit and the corresponding set bit in the ESMIEPSR4 register unchanged.
1
Read: Failure on channel x has influence on ERROR pin.
Write: Disables failure influence on ERROR pin and clears the corresponding set bit in the
ESMIEPSR4 register.
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12.4.19 ESM Interrupt Enable Set Register 4 (ESMIESR4)
This register is dedicated for Group1.
Figure 12-29. ESM Interrupt Enable Set Register 4 (ESMIESR4)
[address = FFFF F548h]
31
16
INTENSET[63:48]
R/WP-0
15
0
INTENSET[47:32]
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 12-21. ESM Interrupt Enable Set Register 4 (ESMIESR4) Field Descriptions
Bit
63-32
Field
Value
INTENSET
Description
Set interrupt enable.
Read in User and Privileged mode. Write in Privileged mode only.
0
Read: Interrupt is disabled.
Write: Leaves the bit and the corresponding clear bit in the ESMIECR4 register unchanged.
1
Read: Interrupt is enabled.
Write: Enables interrupt and sets the corresponding clear bit in the ESMIECR4 register.
12.4.20 ESM Interrupt Enable Clear Register 4 (ESMIECR4)
This register is dedicated for Group1.
Figure 12-30. ESM Interrupt Enable Clear Register 4 (ESMIECR4)
[address = FFFF F54Ch]
31
16
INTENCLR[63:48]
R/WP-0
15
0
INTENCLR[47:32]
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 12-22. ESM Interrupt Enable Clear Register 4 (ESMIECR4) Field Descriptions
Bit
63-32
Field
Value
INTENCLR
Description
Clear interrupt enable.
Read in User and Privileged mode. Write in Privileged mode only.
0
Read: Interrupt is disabled.
Write: Leaves the bit and the corresponding set bit in the ESMIESR4 register unchanged.
1
Read: Interrupt is enabled.
Write: Disables interrupt and clears the corresponding set bit in the ESMIESR4 register.
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12.4.21 ESM Interrupt Level Set Register 4 (ESMILSR4)
This register is dedicated for Group1.
Figure 12-31. ESM Interrupt Level Set Register 4 (ESMILSR4)
[address = FFFF F550h]
31
16
INTLVLSET[63:48]
R/WP-0
15
0
INTLVLSET[47:32]
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 12-23. ESM Interrupt Level Set Register 4 (ESMILSR4) Field Descriptions
Bit
63-32
Field
Value
INTLVLSET
Description
Set interrupt level.
Read in User and Privileged mode. Write in Privileged mode only.
0
Read: Read: Interrupt of channel x is mapped to low-level interrupt line.
Write: Leaves the bit and the corresponding clear bit in the ESMILCR4 register unchanged.
1
Read: Interrupt of channel x is mapped to high-level interrupt line.
Write: Maps interrupt of channel x to high-level interrupt line and sets the corresponding clear bit in
the ESMILCR4 register.
12.4.22 ESM Interrupt Level Clear Register 4 (ESMILCR4)
This register is dedicated for Group1.
Figure 12-32. ESM Interrupt Level Clear Register 4 (ESMILCR4)
[address = FFFF F554h]
31
16
INTLVLCLR[63:48]
R/WP-0
15
0
INTLVLCLR[47:32]
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 12-24. ESM Interrupt Level Clear Register 4 (ESMILCR4) Field Descriptions
Bit
63-32
Field
Value
INTLVLCLR
Description
Clear interrupt level.
Read in User and Privileged mode. Write in Privileged mode only.
0
Read: Interrupt of channel x is mapped to low-level interrupt line.
Write: Leaves the bit and the corresponding set bit in the ESMILSR4 register unchanged.
1
Read: Interrupt of channel x is mapped to high-level interrupt line.
Write: Maps interrupt of channel x to low-level interrupt line and clears the corresponding set bit in
the ESMILSR4 register.
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12.4.23 ESM Status Register 4 (ESMSR4)
This register is dedicated for Group1.
Figure 12-33. ESM Status Register 4 (ESMSR4)
[address = FFFF F558h]
31
16
ESF[63:48]
R/W1CP-X/0
15
0
ESF[47:32]
R/W1CP-X/0
LEGEND: R/W = Read/Write; W1CP = Write 1 to clear in privilege mode only; -n = value after reset/PORRST; X = Value unchanged
Table 12-25. ESM Status Register 4 (ESMSR4) Field Descriptions
Bit
Field
63-32
ESF
Value
Description
Error Status Flag. Provides status information on a pending error.
Read in User and Privileged mode. Write in Privileged mode only.
0
Read: No error occurred; no interrupt is pending.
Write: Leaves the bit unchanged.
1
Read: Error occurred; interrupt is pending.
Write: Clears the bit.
Note: After RST, if one of these flags are set and the corresponding interrupt are enabled, the
interrupt service routine will be called.
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Chapter 13
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Real-Time Interrupt (RTI) Module
This chapter describes the functionality of the real-time interrupt (RTI) module. The RTI is designed as an
operating system timer to support a real time operating system (RTOS).
NOTE: This chapter describes a superset implementation of the RTI module that includes features
and functionality related to DMA, FlexRay, and Timbase control. These features are
dependent on the device-specific feature content. Consult your device-specific datasheet to
determine the applicability of these features to your device being used.
Topic
13.1
13.2
13.3
434
...........................................................................................................................
Page
Overview ......................................................................................................... 435
Module Operation ............................................................................................. 436
RTI Control Registers ........................................................................................ 446
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13.1 Overview
The real-time interrupt (RTI) module provides timer functionality for operating systems and for
benchmarking code. The RTI module can incorporate several counters that define the timebases needed
for scheduling in the operating system.
The timers also allow you to benchmark certain areas of code by reading the values of the counters at the
beginning and the end of the desired code range and calculating the difference between the values.
In addition the RTI provides a mechanism to synchronize the operating system to the FlexRay
communication cycle. Clock supervision allows for detection of issues on the FlexRay bus with an
automatic switch to an internally generated timebase when a failure with the FlexRay timebase is
detected.
13.1.1 Features
The RTI module has the following features:
• Two independent 64 bit counter blocks
• Four configurable compares for generating operating system ticks or DMA requests. Each event can
be driven by either counter block 0 or counter block 1.
• One counter block usable for application synchronization to FlexRay network including clock
supervision
• Fast enabling/disabling of events
• Two time stamp (capture) functions for system or peripheral interrupts, one for each counter block
• Digital windowed watchdog
13.1.2 Industry Standard Compliance Statement
This module is specifically designed to fulfill the requirements for OSEK (Offene Systeme und deren
Schnittstellen für die Elektronik im Kraftfahrzeug, or Open Systems and the Corresponding Interfaces for
Automotive Electronics) as well as OSEK/time-compliant operating systems, but is not limited to it.
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13.2 Module Operation
Figure 13-1 illustrates the high level block diagram of the RTI module.
The RTI module has two independent counter blocks for generating different timebases: counter block 0
and counter block 1. The two counter blocks provide the same basic functionality, but counter block 0 has
the additional functionality of being able to work with the FlexRay Macrotick (NTU0) or Start of Cycle
(NTU1) and perform clock supervision to detect a missing signal.
A compare unit compares the counters with programmable values and generates four independent
interrupt or DMA requests on compare matches. Each of the compare registers can be programmed to be
compared to either counter block 0 or counter block 1.
The following sections describe the individual functions in more detail.
Figure 13-1. RTI Block Diagram
Compare Unit
32
RTICLK
FlexRay Macrotick (NTU0)
FlexRay Start of Cycle (NTU1)
NTU2
NTU3
Counter Block 0
64-bit
incl. FlexRay Feature
Capture Feature
Counter Block 1
64-bit
Capture Feature
RTICLK
Event0
VIM REQ[2]
DMA REQ[12]
Event1
VIM REQ[3]
DMA REQ[13]
Event2
VIM REQ[4]
DMA REQ[18]
Event3
VIM REQ[5]
DMA REQ[19]
32
32
32
32
32
13.2.1 Counter Operation
Each counter block consists of the following (see Figure 13-2):
• One 32-bit prescale counter (RTIUC0 or RTIUC1)
• One 32-bit free running counter (RTIFRC0 or RTIFRC1)
The RTIUC0/1 is driven by the RTICLK and counts up until the compare value in the compare up counter
register (RTICPUC0 or RTICPUC1) is reached. When the compare matches, RTIFRC0/1 is incremented
and RTIUC0/1 is reset to 0. If RTIFRC0/1 overflows, an interrupt is generated to the vectored interrupt
manager (VIM). The overflow interrupt is not intended to generate the timebase for the operating system.
See Section 13.2.2 for the timebase generation. The up counter together with the compare up counter
value prescale the RTI clock. The resulting formula for the frequency of the free running counter
(RTIFRC0/1) is:
f RTIFRCx =
{
f RTICLK
--------------------------------------RTICPUCx + 1
f RTICLK
-------------------32
2 +1
when RTICPUCx ≠ 0
when RTICPUCx = 0
(23)
NOTE: Setting RTICPUCx equal to zero is not recommended. Doing so will hold the Up Counter at
zero for two RTICLK cycles after it overflows from 0xFFFFFFFF to zero.
The counter values can be determined by reading the respective counter registers or by generating a
hardware event which captures the counter value into the respective capture register. Both functions are
described in the following sections.
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Figure 13-2. Counter Block Diagram
31
0
Counter Block 0
Compare Up
Counter
RTICPUC0
RTICLK
0
Up Counter
31
OVLINT0
32
32
=
31
1
32
RTIFRC0
Up Counter
Register
To Compare
Unit
Timebase
Control
RTIUC0
32
31
0
Free Running Counter
0
NTU0
NTU1
NTU2
NTU3
1
31
0
32
31
Capture Up
Counter
0
Capture Free Running
Counter
RTICAUC0
RTICAFRC0
1
Control
CAP event source 0 from VIM
CAP event source 1 from VIM
RTICAPCTRL
31
0
Counter Block 1
1
Compare Up
Counter
OVLINT1
RTICPUC1
RTICLK
0
Up Counter
31
32
1
31
32
=
31
1
0
Free Running Counter
RTIFRC1
32
To Compare
Unit
0
Up Counter
Register
RTIUC1
32
31
0
Capture Up
Counter
RTICAUC1
32
31
0
Capture Free Running
Counter
RTICAFRC1
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13.2.1.1 Counter and Capture Read Consistency
Portions of the device internal databus are 32-bits wide. If the application wants to read the 64-bit counters
or the 64-bit capture values, a certain order of 32-bit read operations needs to be followed. This is to
prevent one counter incrementing in between the two separate read operations to both counters.
Reading the Counters
The free running counter (RTIFRCx) must be read first. This priority will ensure that in the cycle when the
CPU reads RTIFRCx, the up counter value is stored in its counter register (RTIUCx). The second read has
to access the up counter register (RTIUCx), which then holds the value which corresponds to the number
of RTICLK cycles that have elapsed at the time reading the free running counter register (RTIFRCx).
NOTE: The up counters are implemented as shadow registers. Reading RTIUCx without having
read RTIFRCx first will return always the same value. RTIUCx will only be updated when
RTIFRCx is read.
Reading the Capture Values
The free running counter capture register (RTICAFRCx) must be read first. This priority will ensure that in
the cycle when the CPU reads RTICAFRCx, the up counter value is stored in its counter register
(RTICAUCx). The second read has to access the up counter register (RTICAUCx), which then holds the
value captured at the time when reading the capture free running counter register (RTICAFRCx).
NOTE: The capture up counter registers are implemented as shadow registers. Reading RTICAUCx
without having read RTICAFRCx first will return always the same value. RTICAUCx will only
be updated when RTICAFRCx is read.
13.2.1.2 Capture Feature
Both counter blocks also provide a capture feature on external events. Two capture sources can trigger
the capture event. The source triggering the block is configurable (RTICAPCTRL). The sources originate
from the Vectored Interrupt Manager (VIM) and allow the generation of capture events when a peripheral
modules has generated an interrupt. Any of the peripheral interrupts can be selected as the capture event
in the VIM.
When an event is detected, RTIUCx and RTIFRCx are stored in the capture up counter (RTICAUCx) and
capture free running counter (RTICAFRCx) registers. The read order of the captured values must be the
same as the read order of the actual counters (see Section 13.2.1.1).
13.2.2 Interrupt/DMA Requests
There are four compare registers (RTICOMPy) to generate interrupt requests to the VIM or DMA requests
to the DMA controller. The interrupts can be used to generate different timebases for the operating
system. Each of the compare registers can be configured to be compared to either RTIFRC0 or RTIFRC1.
When the counter value matches the compare value, an interrupt is generated. To allow periodic
interrupts, a certain value can be added to the compare value in RTICOMPy automatically. This value is
stored in the update compare register (RTIUDCPy) and will be added after a compare is matched. The
period of the generated interrupt/DMA request can be calculated with:
t COMPx = t RTICLK x (RTICPUCy + 1) x RTIUDCPy
if RTICPUCy ≠ 0,
32
t COMPx = t RTICLK x (2 +1) x RTIUDCPy
if RTIUDCPy = 0,
32
t COMPx = t RTICLK x (RTICPUCy + 1) x 2
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Figure 13-3. Compare Unit Block Diagram (shows only 1 of 4 blocks for simplification)
31
0
Update Compare
RTIUDCP0 / RTIUDCP1
RTIUDCP2 / RTIUDCP3
32
DMA REQy
+
31
0
Enable/Disable
Compare
RTICOMP0 / RTICOMP1
RTICOMP2 / RTICOMP3
From counter
block 0
RTISETINTENA[11:8]
RTICLEARINTENA[11:8]
32
=
32
1
From counter
block 1
INT REQn
Enable/Disable
Control
RTICOMPCTRL
RTISETINTENA[3:0]
RTICLEARINTENA[3:0]
Another interrupt that can be generated is the overflow interrupt (OVLINTx) in case the RTIFRCx counter
overflows.
The interrupts/DMA requests can be enabled in the RTISETINTENA register and disabled in the
RTICLEARINTENA register. The RTIINTFLAG register shows the pending interrupts.
13.2.3 RTI Clocking
The counter blocks are clocked with RTICLK (for definition see Section 2.4.2). Counter block 0 can be
clocked in addition by either the FlexRay Macrotick (NTU0) or the FlexRay Start of Cycle (NTU1).
A clock supervision for the NTUx clocking scheme is implemented to avoid missing operating system ticks.
13.2.4 Synchronizing Timer Events to Network Time (NTU)
For applications which are participating on a time-triggered communication bus, it is often beneficial to
synchronize the application or operating system to the network time. The RTI provides a feature to
increment Free Running Counter 0 (RTIFRC0) by a periodic clock provided by the communication module.
In this case two different clocks can be chosen. One is the FlexRay module Macrotick (NTU0) and the
other is the Start of Cycle (NTU1) information of the same module.
The application has control over which clock (RTICLK, NTU0, NTU1) should be used for clocking
RTIFRC0. If NTUx is used, a clock supervision circuit allows to monitor this clock and provides a fallback
solution, should the clock be non-functional (missing). A too fast running NTUx cannot be detected.
RTIUC0 is utilized to monitor the NTUx signal. A detection window can be programmed in which a valid
NTU clock pulse needs to occur. If no pulse is detected, the RTI automatically switches back to clock the
Free Running Counter 0 with RTIUC0. In order to avoid a big jitter in the operating ticks, in case a switch
back to RTIUC0 happens, RTICPUC0 should be set to a value so the clock frequency RTIUC0 outputs is
approximately the same as the NTUx frequency.
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Figure 13-4. Timebase Control
RTIUC0
RTIFRC0
Control
RTIGCTRL
31
Increment by 1
NTU0
NTU1
Control
RTITBCTRL
0
Timebase Low Compare
RTITBLCOMP
NTU
edge detect
≥
31
0
Control
Timebase High Compare
RTITBCTRL
RTITBHCOMP
≤
Control
Timebase
Interrupt
TBINT
RTITBCTRL
13.2.4.1 Detecting Clock Edges
To detect clock edges on the NTUx signal, the timebase low compare has to be set lower or equal than
the value stored in the RTICPUC0 register and the timebase high compare has to be set higher than 0
and lower than the timebase low compare value. This effectively opens a window in which an edge of the
NTUx signal is expected (see Figure 13-5). Outside this window, no edges will be detected. If no edge will
occur inside the detection window, the multiplexer is switched to internal timebase. The application can
select to generate a timebase interrupt (TBINT) and if the INC bit is set, also will automatically increment
RTIFRC0 by one to compensate for the missed clock cycle of NTUx. If an edge occurs inside the window,
RTIUC0 will be reset to synchronize the two timebases.
In order to make the edge detection work properly, the value in RTICPUC0 needs to be adapted so that
RTIUC0 has a similar period as NTUx.
NOTE: To ensure the NTUx signal is properly detected, the NTUx period must be at least twice as
long as the RTICLK period.
Figure 13-5. Clock Detection Scheme
RTIUC0
RTICPUC0
RTITBLCOMP
RTITBHCOMP
Active Edge
time
Detection
NTUx
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13.2.4.2 Switching from Internal Source to External Source
If the application switches from an internal source to an external source, the two signals must be
synchronized (see Figure 13-6). The synchronization will occur when the TBEXT bit is set. RTIUC0 will be
reset and the edge detection circuit will be active for one (RTICPUC0 + RTITBHCOMP) period or until an
edge is detected. If there is no pulse during this period, the source will be reset from an external clock
source to an internal clock source. If an edge is detected, the windowed edge detection behavior will take
place. Setting the TBEXT bit will not increment free running counter 0.
NOTE: If an external timebase is used, then the software must ensure that timebase low compare
and timebase high compare are programmed to a valid state before switching TBEXT to an
external source. This state is necessary to allow the timebase control circuit to operate
correctly. The following condition must be met:
•
RTITBHCOMP < RTITBLCOMP + RTICPUC0
RTITBHCOMP must be lower than RTICPUC0 because RTIUC0 will be reset if RTICPUC0 is
reached. RTITBHCOMP will represent the number of RTICLK cycles from RTICPUC0 until
the circuit switches to the internal timebase when no NTU edge is detected.
If an external timebase is used, RTIGCTRL[0] must be set to 1 (enable RTIUC0) to ensure
that the timebase control circuit does not wait indefinitely for an incoming signal.
Figure 13-6 shows a timing example for the synchronization phase when the TBEXT bit is set.
Figure 13-6. Switch to NTUx
RTIUC0
CPUC0 might not be matched
depending on the NTU period
RTICPUC0
Write TBEXT = 1
to switch to ext. timbase
time
Active edge detection for
one RTICPUC0 + RTITBHCOMP
NTUx
13.2.4.3 Switching from External Source to Internal Source
When the edge detection is active (TBEXT = 1) and no clock edge of NTUx is detected inside the
programmed detection window, the RTI will automatically switch the timebase to RTIUC0. Figure 13-7
shows a timing example for a missing NTU signal. In the case where the INC bit is set, RTIFRC0 will
automatically be incremented by one to compensate for the missed NTU pulse.
Setting TBEXT = 0 will also switch the clock source for RTIFRC0 to RTIUC0.
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Figure 13-7. Missing NTUx Signal Example
RTIUC0
RTICPUC0
UC0 reset
by NTU edge
time
switch to internal
timebase
UC0 reset
by CPUC0
compare match
missing NTU pulse
NTUx
13.2.5 Digital Watchdog (DWD)
The digital watchdog (DWD) is an optional safety diagnostic which can detect a runaway CPU and
generate either a reset or NMI (non-maskable interrupt) response. It generates resets or NMIs after a
programmable period, or if no correct key sequence was written to the RTIWDKEY register. Figure 13-8
illustrates the DWD.
Figure 13-8. Digital Watchdog
To RESET
logic
15
0
RTIWDKEY
Reset
WD Finite State Machine
=0
Discharge
24
15
0
Compare
16 bit out to 2
KEY [1:0]
0
DWD down counter
RTIDWDCNTR
RTICLK
Suspend
nTRST
11
0
DWD preload
RTIDWDPRLD
442
31
31
0
DWD ctrl
RTIDWDCTRL
=
Real-Time Interrupt (RTI) Module
0
DWD hardwired
code
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13.2.5.1 Digital Watchdog (DWD)
The DWD is disabled by default. If it should be used, it must be enabled by writing a 32-bit value to the
RTIDWDCTRL register.
NOTE:
Once the DWD is enabled, it cannot be disabled except by system reset or power on reset.
If the correct key sequence is written to the RTIWDKEY register (0xE51A followed by 0xA35C), the 25-bit
DWD down counter is reloaded with the left justified 12-bit preload value stored in RTIDWDPRLD. If an
incorrect value is written, a watchdog reset or NMI will occur immediately. A reset or NMI will also be
generated when the DWD down counter is decremented to 0.
While the device is in suspend mode (halting debug mode), the DWD down counter keeps the value it had
when entering suspend mode.
The DWD down counter will be decremented with the RTICLK frequency.
Figure 13-9. DWD Operation
0x1FFFFFF
Preload
Register
Value left
shifted 13bits
DWD
Down
Counter
0
time
CPU
access
to DWD
Reset/NMI
set DWD
Preload
enable
DWD
write E51A
to WDKEY
write A35C write E51A write A35C
to WDKEY to WDKEY to WDKEY
The expiration time of the DWD down counter can be determined with the following equation:
texp = (DWDPRLD + 1) × 213/RTICLK
where
DWDPRLD = 0...4095
NOTE: Care should be taken to ensure that the CPU write to the watchdog register is made allowing
time for the write to propagate to the RTI.
13.2.5.2 Digital Windowed Watchdog (DWWD)
In addition to the time-out boundary configurable via the digital watchdog discussed in Section 13.2.5.1,
for enhanced safety metrics it is desirable to check for a watchdog "pet" within a time window rather than
using a single time threshold. This is enabled by the digital windowed watchdog (DWWD) feature.
• Functional Behavior
The DWWD opens a configurable time window in which the watchdog must be serviced. Any attempt to
service the watchdog outside this time window, or a failure to service the watchdog in this time window,
will cause the watchdog to generate either a reset or a NMI to the CPU. This is controlled by configuring
the RTIWWDRXNCTRL register. As with the DWD, the DWWD is disabled after power on reset. When the
DWWD is configured to generate a non-maskable interrupt on a window violation, the watchdog counter
continues to count down. The NMI handler needs to clear the watchdog violation status flag(s) and then
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service the watchdog by writing the correct sequence in the watchdog key register. This service will cause
the watchdog counter to get reloaded from the preload value and start counting down. If the NMI handler
does not service the watchdog in time, it could count down all the way to zero and wrap around. If the NMI
Handler does not service the watchdog in time, the NMI gets generated continuously, each time the
counter counts to '0'.
The DWWD uses the Digital Watchdog (DWD) preload register (RTIDWDPRLD) setting to define the endtime of the window. The start-time of the window is defined by a window size configuration
register(RTIWWDSIZECTRL).
The default window size is set to 100%, which corresponds to the DWD functionality of a time-out-only
watchdog. The window size can be selected (through register RTIWWDSIZECTRL) from among 100%,
50%, 25%, 12.5%, 6.25% and 3.125% as shown in Figure 13-10. The window with the respective size will
be opened before the end of the DWD expiration. The user has to serve the watchdog in the window.
Otherwise, a reset or NMI will generate. Figure 13-11 shows an DWWD operation example (25% window).
• Configuration of DWWD
The DWWD preload value (same as DWD preload) can only be configured when the DWWD counter is
disabled. The window size and watchdog reaction to a violation can be configured even after the
watchdog has been enabled. Any changes to the window size and watchdog reaction configurations will
only take effect after the next servicing of the DWWD. This feature can be utilized to dynamically set
windows of different sizes based on task execution time, adding a program sequence element to the
diagnostic which can improve fault coverage.
Figure 13-10. Digital Windowed Watchdog Timing Example
DWD Down
Counter
open window
100% window
open window
open window
50% window
open window
open window
open
window
25% window
open window
open
window
open
window
12.5% window
open
window
open
window
open
window
6.25% window
op.
win
op.
win
op.
win
3.125% window
o
w
o
w
o
w
Figure 13-11. Digital Windowed Watchdog Operation Example (25% Window)
0x1FFFFFF
Preload Register Value
left shifted 13bits
Open
Window
DWD
Down
Counter
Preload Register
Value left shifted
11bits
DWD can NOT be
served in this period
0
time
CPU
access
to DWD
444
set DWD
Preload
Config
25%
DWD
Window
Reset/NMI
enable
DWD
Write
WD
Keys
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13.2.6 Low Power Modes
Low power modes allow the trade off of the current used during low power versus functionality and fast
wakeup response. All low power modes have the following characteristics:
• CPU and system clocks are disabled.
• Flash banks and pump are in sleep mode.
• All peripheral modules are in low power modes and the clocks are disabled (exceptions to this may
occur and would be documented in the specific device data sheet).
Flexibility in enabling and disabling clocks allows for many different low-power modes (see Section 2.4.3).
The operation of the RTI Module is guaranteed in Run, Doze and Snooze modes. In Sleep mode, all
clocks will be switched off and the RTI will not work.
In Doze and Snooze modes, the RTI is active and is able to wake up the device with compare, timebase
and overflow interrupts. The compare interrupts can be used to periodically wake up the device. The
overflow interrupt can be used to notify the operating system that a counter overflow has occurred.
Capturing events generated by the Vectored Interrupt Module (VIM) is also possible since, in both of these
low power modes, the peripheral modules are able to generate interrupts that can trigger capture events.
Capturing events while in Sleep mode is not supported as the clock to the RTI is not active.
When the device is put into low power mode, the peripheral which is generating the external clock NTU is
no longer active, and the timebase control circuitry has to switch to an internal clocking scheme when it
detects a missing clock on NTU. The timebase interrupt will wake up the device and the application
software has to adapt the periodic interrupt generation to the internal clock source.
DMA transfers will be disabled, and DMA requests will not be generated after device wakeup since the
DMA controller will be powered down.
NOTE: RTICLK in Doze Mode
In the special case of Doze Mode with PLL off, RTICLK might have a different period than
with PLL enabled since RTICLK will be derived from the oscillator output. It has to be
ensured that the VCLK to RTICLK ratio is at least 3:1.
13.2.7 Halting Debug Mode Behaviour
Once the system enters halting debug mode, the behavior of the RTI depends on the COS (continue on
suspend) bit. If the bit is cleared and halting debug mode is active, all counters will stop operation. If the
bit is set to one, all counters will be clocked normally and the RTI will work like in normal mode. However,
if the external timebase (NTU) is used and the system is in halting debug mode, the timebase control
circuit will switch to internal timebase once it detects the missing NTU signal of the suspended
communication controller. This will be signaled with an TBINT interrupt so that software can resynchronize
after the device exits halting debug mode.
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13.3 RTI Control Registers
Table 13-1 provides a summary of the registers. The registers support 8-bit, 16-bit, and 32-bit writes. The
offset is relative to the associated peripheral select. See the following sections for detailed descriptions of
the registers. The base address for the control registers is FFFF FC00h. The address locations not listed
are reserved.
Table 13-1. RTI Registers
Offset
446
Acronym
Register Description
Section
00h
RTIGCTRL
RTI Global Control Register
Section 13.3.1
04h
RTITBCTRL
RTI Timebase Control Register
Section 13.3.2
08h
RTICAPCTRL
RTI Capture Control Register
Section 13.3.3
0Ch
RTICOMPCTRL
RTI Compare Control Register
Section 13.3.4
10h
RTIFRC0
RTI Free Running Counter 0 Register
Section 13.3.5
14h
RTIUC0
RTI Up Counter 0 Register
Section 13.3.6
18h
RTICPUC0
RTI Compare Up Counter 0 Register
Section 13.3.7
20h
RTICAFRC0
RTI Capture Free Running Counter 0 Register
Section 13.3.8
24h
RTICAUC0
RTI Capture Up Counter 0 Register
Section 13.3.9
30h
RTIFRC1
RTI Free Running Counter 1 Register
Section 13.3.10
34h
RTIUC1
RTI Up Counter 1 Register
Section 13.3.11
38h
RTICPUC1
RTI Compare Up Counter 1 Register
Section 13.3.12
40h
RTICAFRC1
RTI Capture Free Running Counter 1 Register
Section 13.3.13
44h
RTICAUC1
RTI Capture Up Counter 1 Register
Section 13.3.14
50h
RTICOMP0
RTI Compare 0 Register
Section 13.3.15
54h
RTIUDCP0
RTI Update Compare 0 Register
Section 13.3.16
58h
RTICOMP1
RTI Compare 1 Register
Section 13.3.17
5Ch
RTIUDCP1
RTI Update Compare 1 Register
Section 13.3.18
60h
RTICOMP2
RTI Compare 2 Register
Section 13.3.19
64h
RTIUDCP2
RTI Update Compare 2 Register
Section 13.3.20
68h
RTICOMP3
RTI Compare 3 Register
Section 13.3.21
6Ch
RTIUDCP3
RTI Update Compare 3 Register
Section 13.3.22
70h
RTITBLCOMP
RTI Timebase Low Compare Register
Section 13.3.23
74h
RTITBHCOMP
RTI Timebase High Compare Register
Section 13.3.24
80h
RTISETINTENA
RTI Set Interrupt Enable Register
Section 13.3.25
84h
RTICLEARINTENA
RTI Clear Interrupt Enable Register
Section 13.3.26
88h
RTIINTFLAG
RTI Interrupt Flag Register
Section 13.3.27
90h
RTIDWDCTRL
Digital Watchdog Control Register
Section 13.3.28
94h
RTIDWDPRLD
Digital Watchdog Preload Register
Section 13.3.29
98h
RTIWDSTATUS
Watchdog Status Register
Section 13.3.30
9Ch
RTIWDKEY
RTI Watchdog Key Register
Section 13.3.31
A0h
RTIDWDCNTR
RTI Digital Watchdog Down Counter Register
Section 13.3.32
A4h
RTIWWDRXNCTRL
Digital Windowed Watchdog Reaction Control Register
Section 13.3.33
A8h
RTIWWDSIZECTRL
Digital Windowed Watchdog Window Size Control Register
Section 13.3.34
ACh
RTIINTCLRENABLE
RTI Compare Interrupt Clear Enable Register
Section 13.3.35
B0h
RTICOMP0CLR
RTI Compare 0 Clear Register
Section 13.3.36
B4h
RTICOMP1CLR
RTI Compare 1 Clear Register
Section 13.3.37
B8h
RTICOMP2CLR
RTI Compare 2 Clear Register
Section 13.3.38
BCh
RTICOMP3CLR
RTI Compare 3 Clear Register
Section 13.3.39
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NOTE: Writes to Reserved registers may clear the pending RTI interrupt.
13.3.1 RTI Global Control Register (RTIGCTRL)
The global control register starts/stops the counters and selects the signal compared with the timebase
control circuit. This register is shown in Figure 13-12 and described in Table 13-2.
Figure 13-12. RTI Global Control Register (RTIGCTRL) [offset = 00]
31
15
20
19
16
Reserved
NTUSEL
R-0
R/WP-0
14
2
1
0
COS
Reserved
CNT1EN
CNT0EN
R/WP-0
R-0
R/WP-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 13-2. RTI Global Control Register (RTIGCTRL) Field Descriptions
Bit
Field
31-20
Reserved
19-16
NTUSEL
Value
0
Select NTU signal. These bits determine which NTU input signal is used as external timebase
NTU0
5h
NTU1
Ah
NTU2
Fh
NTU3
COS
14-2
Reserved
1
CNT1EN
0
Reads return 0. Writes have no effect.
0h
All other
values
15
Description
Tied to 0
Continue on suspend. This bit determines if both counters are stopped when the device goes into
halting debug mode or if they continue counting.
0
Counters are stopped while in halting debug mode.
1
Counters are running while in halting debug mode.
0
Reads return 0. Writes have no effect.
Counter 1 enable. This bit starts and stops counter block 1 (RTIUC1 and RTIFRC1).
0
Counter block 1 is stopped.
1
Counter block 1 is running.
CNT0EN
Counter 0 enable. This bit starts and stops counter block 0 (RTIUC0 and RTIFRC0).
0
Counter block 0 is stopped.
1
Counter block 0 is running.
NOTE: If the application uses the timebase circuit for synchronization between the communications
controller and the operating system and the device enters halting debug mode, the
synchronization may be lost depending on the COS setting in the RTI module and the halting
debug mode behavior of the communications controller.
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13.3.2 RTI Timebase Control Register (RTITBCTRL)
The timebase control register selects if the free running counter 0 is incremented by RTICLK or NTU. This
register is shown in Figure 13-13 and described in Table 13-3.
Figure 13-13. RTI Timebase Control Register (RTITBCTRL) [offset = 04h]
31
8
Reserved
R-0
7
1
0
Reserved
2
INC
TBEXT
R-0
R/WP-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 13-3. RTI Timebase Control Register (RTITBCTRL) Field Descriptions
Bit
31-2
1
0
Field
Reserved
Value
0
INC
Description
Reads return 0. Writes have no effect.
Increment free running counter 0. This bit determines whether the free running counter 0 (RTIFRC0) is
automatically incremented if a failing clock on the NTU signal is detected.
0
RTIFRC0 will not be incremented on a failing external clock.
1
RTIFRC0 will be incremented on a failing external clock.
TBEXT
Timebase external. This bit selects whether the free running counter 0 (RTIFRC0) is clocked by the
internal up counter 0 (RTIUC0) or from the external signal NTU. Setting the TBEXT bit from 0 to 1 will
not increment RTIFRC0, since RTIUC0 is reset.
When the timebase supervisor circuit detects a missing clock edge, then the TBEXT bit is reset.
Only the software can select whether the external signal should be used.
448
0
RTIUC0 clocks RTIFRC0.
1
NTU clocks RTIFRC0.
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13.3.3 RTI Capture Control Register (RTICAPCTRL)
The capture control register controls the capture source for the counters. This register is shown in
Figure 13-14 and described in Table 13-4.
Figure 13-14. RTI Capture Control Register (RTICAPCTRL) [offset = 08h]
31
8
Reserved
R-0
7
1
0
Reserved
2
CAPCNTR1
CAPCNTR0
R-0
R/WP-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 13-4. RTI Capture Control Register (RTICAPCTRL) Field Descriptions
Bit
31-2
1
0
Field
Reserved
Value
0
CAPCNTR1
Description
Reads return 0. Writes have no effect.
Capture counter 1. This bit determines which external interrupt source triggers a capture event of
RTIUC1 and RTIFRC1.
0
Capture of RTIUC1/ RTIFRC1 is triggered by capture event source 0.
1
Capture of RTIUC1/ RTIFRC1 is triggered by capture event source 1.
CAPCNTR0
Capture counter 0. This bit determines which external interrupt source triggers a capture event of
RTIUC0 and RTIFRC0.
0
Capture of RTIUC0/ RTIFRC0 is triggered by capture event source 0.
1
Capture of RTIUC0/ RTIFRC0 is triggered by capture event source 1.
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13.3.4 RTI Compare Control Register (RTICOMPCTRL)
The compare control register controls the source for the compare registers. This register is shown in
Figure 13-15 and described in Table 13-5.
Figure 13-15. RTI Compare Control Register (RTICOMPCTRL) [offset = 0Ch]
31
16
Reserved
R-0
15
13
12
11
9
8
Reserved
COMPSEL3
Reserved
COMPSEL2
R-0
R/WP-0
R-0
R/WP-0
7
5
4
3
1
0
Reserved
COMPSEL1
Reserved
COMPSEL0
R-0
R/WP-0
R-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 13-5. RTI Compare Control Register (RTICOMPCTRL) Field Descriptions
Bit
31-13
12
11-9
8
7-5
4
3-1
0
450
Field
Reserved
Value
0
COMPSEL3
Reserved
0
Value will be compared with RTIFRC0.
1
Value will be compared with RTIFRC1.
0
Reads return 0. Writes have no effect.
Compare select 2. This bit determines the counter with which the compare value held in compare
register 2 (RTICOMP2) is compared.
0
Value will be compared with RTIFRC0.
1
Value will be compared with RTIFRC1.
0
Reads return 0. Writes have no effect.
COMPSEL1
Reserved
Reads return 0. Writes have no effect.
Compare select 3. This bit determines the counter with which the compare value held in compare
register 3 (RTICOMP3) is compared.
COMPSEL2
Reserved
Description
Compare select 1. This bit determines the counter with which the compare value held in compare
register 1 (RTICOMP1) is compared.
0
Value will be compared with RTIFRC0.
1
Value will be compared with RTIFRC1.
0
Reads return 0. Writes have no effect.
COMPSEL0
Compare select 0. This bit determines the counter with which the compare value held in compare
register 0 (RTICOMP0) is compared.
0
Value will be compared with RTIFRC0.
1
Value will be compared with RTIFRC1.
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13.3.5 RTI Free Running Counter 0 Register (RTIFRC0)
The free running counter 0 register holds the current value of free running counter 0. This register is
shown in Figure 13-16 and described in Table 13-6.
Figure 13-16. RTI Free Running Counter 0 Register (RTIFRC0) [offset = 10h]
31
16
FRC0
R/WP-0
15
0
FRC0
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 13-6. RTI Free Running Counter 0 Register (RTIFRC0) Field Descriptions
Bit
Field
Value
31-0
FRC0
0-FFFF FFFFh
Description
Free running counter 0. This registers holds the current value of the free running counter 0.
A read of this counter returns the current value of the counter.
The counter can be preset by writing (in privileged mode only) to this register. The counter
increments then from this written value upwards.
Note: If counters must be preset, they must be disabled in the RTIGCTRL register to
ensure consistency between RTIUC0 and RTIFRC0.
13.3.6 RTI Up Counter 0 Register (RTIUC0)
The up counter 0 register holds the current value of prescale counter. This register is shown in Figure 1317 and described in Table 13-7.
Figure 13-17. RTI Up Counter 0 Register (RTIUC0) [offset = 14h]
31
16
UC0
R/WP-0
15
0
UC0
R/WP-0
LLEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 13-7. RTI Up Counter 0 Register (RTIUC0) Field Descriptions
Bit
Field
Value
31-0
UC0
0-FFFF FFFFh
Description
Up counter 0. This register holds the current value of the up counter 0 and prescales the RTI
clock. It will be only updated by a previous read of free running counter 0 (RTIFRC0). This
method of updating effectively gives a 64-bit read of both counters, without having the problem
of a counter being updated between two consecutive reads on up counter 0 (RTIUC0) and free
running counter 0 (RTIFRC0).
A read of this counter returns the value of the counter at the time RTIFRC0 was read.
A write to this counter presets it with a value. The counter then increments from this written
value upwards.
Note: If counters must be preset, they must be disabled in the RTIGCTRL register to ensure
consistency between RTIUC0 and RTIFRC0.
Note: If the preset value is bigger than the compare value stored in register RTICPUC0,
then it can take a long time until a compare matches, since RTIUC0 has to count up until
it overflows.
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13.3.7 RTI Compare Up Counter 0 Register (RTICPUC0)
The compare up counter 0 register holds the value to be compared with prescale counter 0 (RTIUC0).
This register is shown in Figure 13-18 and described in Table 13-8.
Figure 13-18. RTI Compare Up Counter 0 Register (RTICPUC0) [offset = 18h]
31
16
CPUC0
R/WP-0
15
0
CPUC0
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 13-8. RTI Compare Up Counter 0 Register (RTICPUC0) Field Descriptions
Bit
31-0
Field
Value
CPUC0
0-FFFF FFFFh
Description
Compare up counter 0. This register holds the value that is compared with the up counter 0.
When the compare shows a match, the free running counter 0 (RTIFRC0) is incremented.
RTIUC0 is set to 0 when the counter value matches the RTICPUC0 value. The value set in this
register prescales the RTI clock.
If CPUC0 = 0, then
fFRC0 = RTICLK/(232+1) (Setting CPUC0 equal to 0 is not recommended. Doing so will hold the
Up Counter at 0 for 2 RTICLK cycles after it overflows from FFFF FFFFh to 0.)
If CPUC0 ≠ 0, then
fFRC0 = RTICLK/(RTICPUC0+1)
A read of this register returns the current compare value.
A write to this register:
• If TBEXT = 0, the compare value is updated.
• If TBEXT = 1, the compare value is unchanged.
13.3.8 RTI Capture Free Running Counter 0 Register (RTICAFRC0)
The capture free running counter 0 register holds the free running counter 0 on external events. This
register is shown in Figure 13-19 and described in Table 13-9.
Figure 13-19. RTI Capture Free Running Counter 0 Register (RTICAFRC0) [offset = 20h]
31
16
CAFRC0
R-0
15
0
CAFRC0
R-0
LEGEND: R = Read only; -n = value after reset
Table 13-9. RTI Capture Free Running Counter 0 Register (RTICAFRC0) Field Descriptions
Bit
31-0
Field
CAFRC0
Value
0-FFFF FFFFh
Description
Capture free running counter 0. This register captures the current value of the free running
counter 0 (RTIFRC0) when an event occurs, controlled by the external capture control block.
A read of this register returns the value of RTIFRC0 on a capture event.
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13.3.9 RTI Capture Up Counter 0 Register (RTICAUC0)
The capture up counter 0 register holds the current value of prescale counter 0 on external events. This
register is shown in Figure 13-20 and described in Table 13-10.
Figure 13-20. RTI Capture Up Counter 0 Register (RTICAUC0) [offset = 24h]
31
16
CAUC0
R-0
15
0
CAUC0
R-0
LEGEND: R = Read only; -n = value after reset
Table 13-10. RTI Capture Up Counter 0 Register (RTICAUC0) Field Descriptions
Bit
31-0
Field
CAUC0
Value
0-FFFF FFFFh
Description
Capture up counter 0. This register captures the current value of the up counter 0 (RTIUC0)
when an event occurs, controlled by the external capture control block.
Note: The read sequence must be the same as with RTIUC0 and RTIFRC0. Therefore, the
RTICAFRC0 register must be read before the RTICAUC0 register is read. This sequence
ensures that the value of the RTICAUC0 register is the corresponding value to the
RTICAFRC0 register, even if another capture event happens in between the two reads.
A read of this register returns the value of RTIUC0 on a capture event.
13.3.10 RTI Free Running Counter 1 Register (RTIFRC1)
The free running counter 1 register holds the current value of the free running counter 1. This register is
shown in Figure 13-21 and described in Table 13-11.
Figure 13-21. RTI Free Running Counter 1 Register (RTIFRC1) [offset = 30h]
31
16
FRC1
R/WP-0
15
0
FRC1
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 13-11. RTI Free Running Counter 1 Register (RTIFRC1) Field Descriptions
Bit
Field
Value
31-0
FRC1
0-FFFF FFFFh
Description
Free running counter 1. This register holds the current value of the free running counter 1 and
will be updated continuously.
A read of this register returns the current value of the counter.
A write to this register presets the counter. The counter increments then from this written value
upwards.
Note: If counters must be preset, they must be disabled in the RTIGCTRL register to
ensure consistency between RTIUC1 and RTIFRC1.
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13.3.11 RTI Up Counter 1 Register (RTIUC1)
The up counter 1 register holds the current value of the prescale counter 1. This register is shown in
Figure 13-22 and described in Table 13-12.
Figure 13-22. RTI Up Counter 1 Register (RTIUC1) [offset = 34h]
31
16
UC1
R/WP-0
15
0
UC1
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 13-12. RTI Up Counter 1 Register (RTIUC1) Field Descriptions
Bit
Field
Value
31-0
UC1
0-FFFF FFFFh
Description
Up counter 1. This register holds the current value of the up counter 1 and prescales the RTI
clock. It will be only updated by a previous read of free running counter 1 (RTIFRC1). This
method of updating effectively gives a 64-bit read of both counters, without having the problem
of a counter being updated between two consecutive reads on RTIUC1 and RTIFRC1.
A read of this register will return the value of the counter when the RTIFRC1 was read.
A write to this register presets the counter. The counter then increments from this written value
upwards.
Note: If counters must be preset, they must be disabled in the RTIGCTRL register to
ensure consistency between RTIUC1 and RTIFRC1.
Note: If the preset value is bigger than the compare value stored in register RTICPUC1,
then it can take a long time until a compare matches, since RTIUC1 has to count up until
it overflows.
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13.3.12 RTI Compare Up Counter 1 Register (RTICPUC1)
The compare up counter 1 register holds the value compared with prescale counter 1. This register is
shown in Figure 13-23 and described in Table 13-13.
Figure 13-23. RTI Compare Up Counter 1 Register (RTICPUC1) [offset = 38h]
31
16
CPUC1
R/WP-0
15
0
CPUC1
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 13-13. RTI Compare Up Counter 1 Register (RTICPUC1) Field Descriptions
Bit
31-0
Field
CPUC1
Value
0-FFFF FFFFh
Description
Compare up counter 1. This register holds the compare value, which is compared with the up
counter 1. When the compare matches, the free running counter 1 (RTIFRC1) is incremented.
The up counter is cleared to 0 when the counter value matches the CPUC1 value. The value
set in this prescales the RTI clock according to the following formula:
If CPUC1 = 0, then
fFRC1 = RTICLK/(232+1) (Setting CPUC1 equal to 0 is not recommended. Doing so will hold the
Up Counter at 0 for 2 RTICLK cycles after it overflows from FFFF FFFFh to 0.)
If CPUC1 ≠ 0, then
fFRC1 = RTICLK/(RTICPUC1+1)
A read of this register returns the current compare value.
A write to this register updates the compare value.
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13.3.13 RTI Capture Free Running Counter 1 Register (RTICAFRC1)
The capture free running counter 1 register holds the current value of free running counter 1 on external
events. This register is shown in Figure 13-24 and described in Table 13-14.
Figure 13-24. RTI Capture Free Running Counter 1 Register (RTICAFRC1) [offset = 40h]
31
16
CAFRC1
R-0
15
0
CAFRC1
R-0
LEGEND: R = Read only; -n = value after reset
Table 13-14. RTI Capture Free Running Counter 1 Register (RTICAFRC1) Field Descriptions
Bit
31-0
Field
CAFRC1
Value
0-FFFF FFFFh
Description
Capture free running counter 1. This register captures the current value of the free running
counter 1 (RTIFRC1) when an event occurs, controlled by the external capture control block.
A read of this register returns the value of RTIFRC1 on a capture event.
13.3.14 RTI Capture Up Counter 1 Register (RTICAUC1)
The capture up counter 1 register holds the current value of prescale counter 1 on external events. This
register is shown in Figure 13-25 and described in Table 13-15.
Figure 13-25. RTI Capture Up Counter 1 Register (RTICAUC1) [offset = 44h]
31
16
CAUC1
R-0
15
0
CAUC1
R-0
LEGEND: R = Read only; -n = value after reset
Table 13-15. RTI Capture Up Counter 1 Register (RTICAUC1) Field Descriptions
Bit
31-0
Field
CAUC1
Value
0-FFFF FFFFh
Description
Capture up counter 1. This register captures the current value of the up counter 1 (RTIUC1)
when an event occurs, controlled by the external capture control block.
Note: The RTICAFRC1 register must be read before the RTICAUC1 register is read. This
sequence ensures that the value of the RTICAUC1 register is the corresponding value to
the RTICAFRC1 register, even if another capture event happens in between the two
reads.
A read of this register returns the value of RTIUC1 on a capture event.
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13.3.15 RTI Compare 0 Register (RTICOMP0)
The compare 0 register holds the value to be compared with the counters. This register is shown in
Figure 13-26 and described in Table 13-16.
Figure 13-26. RTI Compare 0 Register (RTICOMP0) [offset = 50h]
31
16
COMP0
R/WP-0
15
0
COMP0
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 13-16. RTI Compare 0 Register (RTICOMP0) Field Descriptions
Bit
31-0
Field
COMP0
Value
0-FFFF FFFFh
Description
Compare 0. This registers holds a value that is compared with the counter selected in the
compare control logic. If RTIFRC0 or RTIFRC1, depending on the counter selected, matches
the compare value, an interrupt is flagged. With this register it is also possible to initiate a DMA
request.
A read of this register will return the current compare value.
A write to this register (in privileged mode only) will update the compare register with a new
compare value.
13.3.16 RTI Update Compare 0 Register (RTIUDCP0)
The update compare 0 register holds the value to be added to the compare register 0 value on a compare
match. This register is shown in Figure 13-27 and described in Table 13-17.
Figure 13-27. RTI Update Compare 0 Register (RTIUDCP0) [offset = 54h]
31
16
UDCP0
R/WP-0
15
0
UDCP0
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 13-17. RTI Update Compare 0 Register (RTIUDCP0) Field Descriptions
Bit
31-0
Field
UDCP0
Value
0-FFFF FFFFh
Description
Update compare 0. This register holds a value that is added to the value in the compare 0
(RTICOMP0) register each time a compare matches. This function allows periodic interrupts to
be generated without software intervention.
A read of this register will return the value to be added to the RTICOMP0 register on the next
compare match.
A write to this register will provide a new update value.
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13.3.17 RTI Compare 1 Register (RTICOMP1)
The compare 1 register holds the value to be compared to the counters. This register is shown in
Figure 13-28 and described in Table 13-18.
Figure 13-28. RTI Compare 1 Register (RTICOMP1) [offset = 58h]
31
16
COMP1
R/WP-0
15
0
COMP1
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 13-18. RTI Compare 1 Register (RTICOMP1) Field Descriptions
Bit
31-0
Field
COMP1
Value
0-FFFF FFFFh
Description
Compare 1. This register holds a value that is compared with the counter selected in the
compare control logic. If RTIFRC0 or RTIFRC1, depending on the counter selected, matches
this compare value, an interrupt is flagged. With this register, it is possible to initiate a DMA
request.
A read of this register will return the current compare value.
A write to this register will update the compare register with a new compare value.
13.3.18 RTI Update Compare 1 Register (RTIUDCP1)
The update compare 1 register holds the value to be added to the compare register 1 value on a compare
match. This register is shown in Figure 13-29 and described in Table 13-19.
Figure 13-29. RTI Update Compare 1 Register (RTIUDCP1) [offset = 5Ch]
31
16
UDCP1
R/WP-0
15
0
UDCP1
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 13-19. RTI Update Compare 1 Register (RTIUDCP1) Field Descriptions
Bit
31-0
Field
UDCP1
Value
0-FFFF FFFFh
Description
Update compare 1. This register holds a value that is added to the value in the RTICOMP1
register each time a compare matches. This process allows periodic interrupts to be generated
without software intervention.
A read of this register will return the value to be added to the RTICOMP1 register on the next
compare match.
A write to this register will provide a new update value.
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13.3.19 RTI Compare 2 Register (RTICOMP2)
The compare 2 register holds the value to be compared to the counters. This register is shown in
Figure 13-30 and described in Table 13-20.
Figure 13-30. RTI Compare 2 Register (RTICOMP2) [offset = 60h]
31
16
COMP2
R/WP-0
15
0
COMP2
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 13-20. RTI Compare 2 Register (RTICOMP2) Field Descriptions
Bit
31-0
Field
COMP2
Value
0-FFFF FFFFh
Description
Compare 2. This register holds a value that is compared with the counter selected in the
compare control logic. If RTIFRC0 or RTIFRC1, depending on the counter selected, matches
this compare value, an interrupt is flagged. With this register, it is possible to initiate a DMA
request.
A read of this register will return the current compare value.
A write to this register (in privileged mode only) will provide a new compare value.
13.3.20 RTI Update Compare 2 Register (RTIUDCP2)
The update compare 2 register holds the value to be added to the compare register 2 value on a compare
match. This register is shown in Figure 13-31 and described in Table 13-21.
Figure 13-31. RTI Update Compare 2 Register (RTIUDCP2) [offset = 64h]
31
16
UDCP2
R/WP-0
15
0
UDCP2
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 13-21. RTI Update Compare 2 Register (RTIUDCP2) Field Descriptions
Bit
31-0
Field
UDCP2
Value
0-FFFF FFFFh
Description
Update compare 2. This register holds a value that is added to the value in the RTICOMP2
register each time a compare matches. This process makes it possible to generate periodic
interrupts without software intervention.
A read of this register will return the value to be added to the RTICOMP2 register on the next
compare match.
A write to this register will provide a new update value.
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13.3.21 RTI Compare 3 Register (RTICOMP3)
The compare 3 register holds the value to be compared to the counters. This register is shown in
Figure 13-32 and described in Table 13-22.
Figure 13-32. RTI Compare 3 Register (RTICOMP3) [offset = 68h]
31
16
COMP3
R/WP-0
15
0
COMP3
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 13-22. RTI Compare 3 Register (RTICOMP3) Field Descriptions
Bit
31-0
Field
COMP3
Value
0-FFFF FFFFh
Description
Compare 3. This register holds a value that is compared with the counter selected in the
compare control logic. If RTIFRC0 or RTIFRC1, depending on the counter selected, matches
this compare value, an interrupt is flagged. With this register, it is possible to initiate a DMA
request.
A read of this register will return the current compare value.
A write to this register will provide a new compare value.
13.3.22 RTI Update Compare 3 Register (RTIUDCP3)
The update compare 3 register holds the value to be added to the compare register 3 value on a compare
match. This register is shown in Figure 13-33 and described in Table 13-23.
Figure 13-33. RTI Update Compare 3 Register (RTIUDCP3) [offset = 6Ch]
31
16
UDCP3
R/WP-0
15
0
UDCP3
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 13-23. RTI Update Compare 3 Register (RTIUDCP3) Field Descriptions
Bit
31-0
Field
UDCP3
Value
0-FFFF FFFFh
Description
Update compare 3. This register holds a value that is added to the value in the RTICOMP3
register each time a compare matches. This process makes it possible to generate periodic
interrupts without software intervention.
A read of this register will return the value to be added to the RTICOMP3 register on the next
compare match.
A write to this register will provide a new update value.
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13.3.23 RTI Timebase Low Compare Register (RTITBLCOMP)
The timebase low compare register holds the value to activate the edge detection circuit. This register is
shown in Figure 13-34 and described in Table 13-24.
Figure 13-34. RTI Timebase Low Compare Register (RTITBLCOMP) [offset = 70h]
31
16
TBLCOMP
R/WP-0
15
0
TBLCOMP
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 13-24. RTI Timebase Low Compare Register (RTITBLCOMP) Field Descriptions
Bit
31-0
Field
Value
TBLCOMP
0-FFFF FFFFh
Description
Timebase low compare value. This value determines when the edge detection circuit starts
monitoring the NTU signal. It will be compared with RTIUC0.
A read of this register will return the current compare value.
A write to this register has the following effects:
If TBEXT = 0: The compare value is updated.
If TBEXT = 1: The compare value is not changed.
13.3.24 RTI Timebase High Compare Register (RTITBHCOMP)
The timebase high compare register holds the value to deactivate the edge detection circuit. This register
is shown in Figure 13-35 and described in Table 13-25.
Figure 13-35. RTI Timebase High Compare Register (RTITBHCOMP) [offset = 74h]
31
16
TBHCOMP
R/WP-0
15
0
TBHCOMP
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 13-25. RTI Timebase High Compare Register (RTITBHCOMP) Field Descriptions
Bit
31-0
Field
TBHCOMP
Value
0-FFFF FFFFh
Description
Timebase high compare value. This value determines when the edge detection circuit will stop
monitoring the NTU signal. It will be compared with RTIUC0.
RTITBHCOMP must be less than RTICPUC0 because RTIUC0 will be reset when RTICPUC0
is reached.
Example: The NTU edge detection circuit should be active ± 10 RTICLK cycles around
RTICPUC0.
• RTICPUC0 = 0050h
• RTITBLCOMP = 0046h
• RTITBHCOMP = 0009h
A read of this register will return the current compare value.
A write to this register has the following effects:
If TBEXT = 0: The compare value is updated.
If TBEXT = 1: The compare value is not changed.
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13.3.25 RTI Set Interrupt Enable Register (RTISETINTENA)
This register prevents the necessity of a read-modify-write operation if a particular interrupt should be
enabled. This register is shown in Figure 13-36 and described in Table 13-26.
Figure 13-36. RTI Set Interrupt Control Register (RTISETINTENA) [offset = 80h]
31
24
Reserved
R-0
23
18
17
16
Reserved
19
SETOVL1INT
SETOVL0INT
SETTBINT
R-0
R/WP-0
R/WP-0
R/WP-0
15
11
10
9
8
Reserved
12
SETDMA3
SETDMA2
SETDMA1
SETDMA0
R-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
7
3
2
1
0
Reserved
4
SETINT3
SETINT2
SETINT1
SETINT0
R-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 13-26. RTI Set Interrupt Control Register (RTISETINTENA) Field Descriptions
Bit
31-19
18
Field
Reserved
Value
0
SETOVL1INT
Description
Reads return 0. Writes have no effect.
Set free running counter 1 overflow interrupt.
0
Read: Interrupt is disabled.
Write: Corresponding bit is unchanged.
1
17
SETOVL0INT
Read or Write: Interrupt is enabled.
Set free running counter 0 overflow interrupt.
0
Read: Interrupt is disabled.
Write: Corresponding bit is unchanged.
1
16
SETTBINT
Read or Write: Interrupt is enabled.
Set timebase interrupt.
0
Read: Interrupt is disabled.
Write: Corresponding bit is unchanged.
15-12
Reserved
11
SETDMA3
1
Read or Write: Interrupt is enabled.
0
Reads return 0. Writes have no effect.
Set compare DMA request 3.
0
Read: DMA request is disabled.
Write: DMA request is unchanged.
1
10
SETDMA2
Read or Write: DMA request is enabled.
Set compare DMA request 2.
0
Read: DMA request is disabled.
Write: DMA request is unchanged.
1
9
SETDMA1
Read or Write: DMA request is enabled.
Set compare DMA request 1.
0
Read: DMA request is disabled.
Write: DMA request is unchanged.
1
462
Read or Write: DMA request is enabled.
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Table 13-26. RTI Set Interrupt Control Register (RTISETINTENA) Field Descriptions (continued)
Bit
8
Field
Value
SETDMA0
Description
Set compare DMA request 0.
0
Read: DMA request is disabled.
Write: DMA request is unchanged.
7-4
Reserved
3
SETINT3
1
Read or Write: DMA request is enabled.
0
Reads return 0. Writes have no effect.
Set compare interrupt 3.
0
Read: Interrupt is disabled.
Write: Corresponding bit is unchanged.
1
2
SETINT2
Read or Write: Interrupt is enabled.
Set compare interrupt 2.
0
Read: Interrupt is disabled.
Write: Corresponding bit is unchanged.
1
1
SETINT1
Read or Write: Interrupt is enabled.
Set compare interrupt 1.
0
Read: Interrupt is disabled.
Write: Corresponding bit is unchanged.
1
0
SETINT0
Read or Write: Interrupt is enabled.
Set compare interrupt 0.
0
Read: Interrupt is disabled.
Write: Corresponding bit is unchanged.
1
Read or Write: Interrupt is enabled.
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13.3.26 RTI Clear Interrupt Enable Register (RTICLEARINTENA)
This register prevents the necessity of a read-modify-write operation if a particular interrupt should be
disabled. This register is shown in Figure 13-37 and described in Table 13-27.
Figure 13-37. RTI Clear Interrupt Control Register (RTICLEARINTENA) [offset = 84h]
31
24
Reserved
R-0
23
19
18
Reserved
17
CLEAROVL1INT
R-0
R/WP-0
15
12
16
CLEAROVL0INT
R/WP-0
CLEARTBINT
R/WP-0
11
10
9
8
Reserved
CLEARDMA3
CLEARDMA2
CLEARDMA1
CLEARDMA0
R-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
7
3
2
1
0
Reserved
4
CLEARINT3
CLEARINT2
CLEARINT1
CLEARINT0
R-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 13-27. RTI Clear Interrupt Control Register (RTICLEARINTENA) Field Descriptions
Bit
31-19
18
Field
Reserved
Value
0
CLEAROVL1INT
Description
Reads return 0. Writes have no effect.
Clear free running counter 1 overflow interrupt.
0
Read: Interrupt is disabled.
Write: Corresponding bit is unchanged.
1
Read: Interrupt is enabled.
Write: Interrupt is disabled.
17
CLEAROVL0INT
Clear free running counter 0 overflow interrupt.
0
Read: Interrupt is disabled.
Write: Corresponding bit is unchanged.
1
Read: Interrupt is enabled.
Write: Interrupt is disabled.
16
CLEARTBINT
Clear timebase interrupt.
0
Read: Interrupt is disabled.
Write: Corresponding bit is unchanged.
1
Read: Interrupt is enabled.
Write: Interrupt is disabled.
15-12
11
Reserved
0
CLEARDMA3
Reads return 0. Writes have no effect.
Clear compare DMA request 3.
0
Read: DMA request is disabled.
Write: Corresponding bit is unchanged.
1
Read: DMA request is enabled.
Write: DMA request is disabled.
10
CLEARDMA2
Clear compare DMA request 2.
0
Read: DMA request is disabled.
Write: Corresponding bit is unchanged.
1
Read: DMA request is enabled.
Write: DMA request is disabled.
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Table 13-27. RTI Clear Interrupt Control Register (RTICLEARINTENA) Field Descriptions (continued)
Bit
9
Field
Value
CLEARDMA1
Description
Clear compare DMA request 1.
0
Read: DMA request is disabled.
Write: Corresponding bit is unchanged.
1
Read: DMA request is enabled.
Write: DMA request is disabled.
8
CLEARDMA0
Clear compare DMA request 0.
0
Read: DMA request is disabled.
Write: Corresponding bit is unchanged.
1
Read: DMA request is enabled.
Write: DMA request is disabled.
7-4
3
Reserved
0
CLEARINT3
Reads return 0. Writes have no effect.
Clear compare interrupt 3.
0
Read: Interrupt is disabled.
Write: Corresponding bit is unchanged.
1
Read: Interrupt is enabled.
Write: Interrupt is disabled.
2
CLEARINT2
Clear compare interrupt 2.
0
Read: Interrupt is disabled.
Write: Corresponding bit is unchanged.
1
Read: Interrupt is enabled.
Write: Interrupt is disabled.
1
CLEARINT1
Clear compare interrupt 1.
0
Read: Interrupt is disabled.
Write: Corresponding bit is unchanged.
1
Read: Interrupt is enabled.
Write: Interrupt is disabled.
0
CLEARINT0
Clear compare interrupt 0.
0
Read: Interrupt is disabled.
Write: Corresponding bit is unchanged.
1
Read: Interrupt is enabled.
Write: Interrupt is disabled.
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13.3.27 RTI Interrupt Flag Register (RTIINTFLAG)
The corresponding flags are set at every compare match of the RTIFRCx and RTICOMPx values, whether
the interrupt is enabled or not. This register is shown in Figure 13-38 and described in Table 13-28.
Figure 13-38. RTI Interrupt Flag Register (RTIINTFLAG) [offset = 88h]
31
19
Reserved
R-0
15
4
18
17
16
OVL1INT
OVL0INT
TBINT
R/W1CP- R/W1CP0
0
R/W1C
P-0
3
2
1
0
Reserved
INT3
INT2
INT1
INT0
R-0
R/W1C
P-0
R/W1C
P-0
R/W1C
P-0
R/W1C
P-0
LEGEND: R/W = Read/Write; R = Read only; W1CP = Write 1 to clear in privilege mode only; -n = value after reset
Table 13-28. RTI Interrupt Flag Register (RTIINTFLAG) Field Descriptions
Bit
Field
31-19
Reserved
18
OVL1INT
Value
0
Description
Reads return 0. Writes have no effect.
Free running counter 1 overflow interrupt flag. This bit determines if an interrupt is pending.
0
Read: No interrupt is pending.
Write: Bit is unchanged.
1
Read: Interrupt is pending.
Write: Bit is cleared to 0.
17
OVL0INT
Free running counter 0 overflow interrupt flag. This bit determines if an interrupt is pending.
0
Read: No interrupt is pending.
Write: Bit is unchanged.
1
Read: Interrupt is pending.
Write: Bit is cleared to 0.
16
TBINT
Timebase interrupt flag. This flag is set when the TBEXT bit is cleared by detection of a missing
external clock edge. It will not be set by clearing TBEXT by software. It determines if an interrupt is
pending.
0
Read: No interrupt is pending.
Write: Bit is unchanged.
1
Read: Interrupt is pending.
Write: Bit is cleared to 0.
15-4
3
Reserved
0
INT3
Reads return 0. Writes have no effect.
Interrupt flag 3. These bits determine if an interrupt due to a Compare 3 match is pending.
0
Read: No interrupt is pending.
Write: Bit is unchanged.
1
Read: Interrupt is pending.
Write: Bit is cleared to 0.
2
INT2
Interrupt flag 2. These bits determine if an interrupt due to a Compare 2 match is pending.
0
Read: No interrupt is pending.
Write: Bit is unchanged.
1
Read: Interrupt is pending.
Write: Bit is cleared to 0.
1
INT1
Interrupt flag 1. These bits determine if an interrupt due to a Compare 1 match is pending.
0
Read: No interrupt is pending.
Write: Bit is unchanged.
1
Read: Interrupt is pending.
Write: Bit is cleared to 0.
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Table 13-28. RTI Interrupt Flag Register (RTIINTFLAG) Field Descriptions (continued)
Bit
Field
0
INT0
Value
Description
Interrupt flag 0. These bits determine if an interrupt due to a Compare 0 match is pending.
0
Read: No interrupt is pending.
Write: Bit is unchanged.
1
Read: Interrupt is pending.
Write: Bit is cleared to 0.
13.3.28 Digital Watchdog Control Register (RTIDWDCTRL)
The software has to write to the DWDCTRL field in order to enable the DWD, as described below. Once
enabled, the watchdog can only be disabled by a system reset. The application cannot disable the
watchdog. However should the RTICLK source be changed to a source that is unimplemented it will have
the same effect as disabling the watchdog. This register is shown in Figure 13-38 and described in
Table 13-28.
Figure 13-39. Digital Watchdog Control Register (RTIDWDCTRL) [offset = 90h]
31
16
DWDCTRL
R/WP-5312h
15
0
DWDCTRL
R/WP-ACEDh
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 13-29. Digital Watchdog Control Register (RTIDWDCTRL) Field Descriptions
Bit
31-0
Field
Value
DWDCTRL
Description
Digital Watchdog Control.
5312 ACEDh
Read: DWD counter is disabled.
Write: State of DWD counter is unchanged (stays enabled or disabled).
A985 59DAh
Read: DWD counter is enabled.
Write: DWD counter is enabled.
All other values
Read: DWD counter state is unchanged (enabled or disabled).
Write: State of DWD counter is unchanged (stays enabled or disabled).
Note: Once the enable value is written, all other future writes are blocked. In other words, once
DWD is enabled, it can only be disabled by system reset or power on reset. However should
the RTICLK source be changed to a source that is unimplemented it will have the same effect
as disabling the watchdog.
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13.3.29 Digital Watchdog Preload Register (RTIDWDPRLD)
This register sets the expiration time of the DWD. This register is shown in Figure 13-38 and described in
Table 13-28.
Figure 13-40. Digital Watchdog Preload Register (RTIDWDPRLD) [offset = 94h]
31
16
Reserved
R-0
15
12
11
0
Reserved
DWDPRLD
R-0
R/WP-FFFh
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 13-30. Digital Watchdog Preload Register (RTIDWDPRLD) Field Descriptions
Bit
Field
31-12
Reserved
11-0
DWDPRLD
Value
0
0-FFFh
Description
Reads return 0 and writes have no effect.
Digital Watchdog Preload Value.
Read: The current preload value
Write: Set the preload value. The DWD preload register can be configured only when the DWD is
disabled. Therefore, the application can only configure the DWD preload register before it enables
the DWD down counter.
The expiration time of the DWD Down Counter can be determined with following equation:
texp = (DWDPRLD+1) x 213 / RTICLK1
where: DWDPRLD = 0...4095
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13.3.30 Watchdog Status Register (RTIWDSTATUS)
This register records the status of the DWD. The values of the following status bits will not be affected by
a soft reset. These bits are cleared by a power-on reset, or by a write of 1. These bits can be used for
debug purposes. This register is shown in Figure 13-38 and described in Table 13-28.
Figure 13-41. Watchdog Status Register (RTIWDSTATUS) [offset = 98h]
31
8
Reserved
R-0
7
5
4
3
2
1
0
Reserved
6
DWWD ST
END TIME VIOL
START TIME VIOL
KEY ST
DWD ST
Reserved
R-0
R/W1CP-x
R/W1CP-x
R/W1CP-x
R/W1CP-x
R/W1CP-x
R-0
LEGEND: R/W = Read/Write; R = Read only; W1CP = Write 1 to clear in privilege mode only; -n = value after reset
Table 13-31. Watchdog Status Register (RTIWDSTATUS) Field Descriptions
Bit
31-6
5
Field
Reserved
Value
0
DWWD ST
Description
Reads return 0. Writes have no effect.
Windowed Watchdog Status
0
Read: No time-window violation has occurred.
Write: Leaves the current value unchanged.
1
Read: Time-window violation has occurred. The watchdog has generated either a system reset
or a non-maskable interrupt to the CPU in this case.
Write: Bit is cleared to 0. This will also clear all other status flags in the RTIWDSTATUS
register. Clearing of the status flags will deassert the non-maskable interrupt generated due to
violation of the DWWD.
4
END TIME VIOL
Windowed Watchdog End Time Violation Status.
This bit indicates whether the Watchdog counter expired.
0
Read: No end-time window violation has occurred.
Write: Leaves the current value unchanged.
1
Read: End-time defined by the windowed watchdog configuration has been violated.
Write: Bit is cleared to 0.
3
START TIME VIOL
Windowed Watchdog Start Time Violation Status.
This bit indicates whether the key is written before the watchdog window opened up.
0
Read: No start-time window violation has occurred.
Write: Leaves the current value unchanged.
1
Read: Start-time defined by the windowed watchdog configuration has been violated.
Write: Bit is cleared to 0.
2
KEY ST
Watchdog key status. This bit indicates a reset or NMI generated by a wrong key or key
sequence written to the RTIWDKEY register.
0
Read: No wrong key or key-sequence written.
Write: Bit is unchanged.
1
Read: Wrong key or key-sequence written to RTIWDKEY register.
Write: Bit is cleared to 0.
1
DWD ST
DWD status.
This bit is equivalent to bit END TIME VIOL.
0
Read: No reset or NMI was generated.
Write: Bit is unchanged.
1
Read: Reset or NMI was generated.
Write: Bit is cleared to 0.
0
Reserved
0
Reads return 0. Writes have no effect.
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13.3.31 RTI Watchdog Key Register (RTIWDKEY)
This register must be written with the correct written key values to serve the watchdog. This register is
shown in Figure 13-42 and described in Table 13-32.
NOTE: It has to be taken into account that the write to the RTIWDKEY register takes 3 VCLK cycles.
Figure 13-42. RTI Watchdog Key Register (RTIDWDKEY) [offset = 9Ch]
31
16
Reserved
R-0
15
0
WDKEY
R/WP-A35Ch
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 13-32. RTI Watchdog Key Register (RTIDWDKEY) Field Descriptions
Bit
Field
31-16
Reserved
15-0
WDKEY
Value
0
0-FFFFh
Description
Reads return 0 and writes have no effect.
Watchdog key. These bits provide the key sequence location.
Reads returns the current WDKEY value.
A write of E51Ah followed by A35Ch in two separate write operations defines the key sequence
and reloads the DWD. Writing any other value causes a reset or NMI, as shown in Table 13-33.
Writing any other value will cause the WDKEY to reset to A35Ch.
Table 13-33. Example of a WDKEY Sequence
470
Step
Value Written to WDKEY
1
A35Ch
Result
No action
2
A35Ch
No action
3
E51Ah
WDKEY is enabled for reset or NMI by next A35Ch.
4
E51Ah
WDKEY is enabled for reset or NMI by next A35Ch.
5
E51Ah
WDKEY is enabled for reset or NMI by next A35Ch.
6
A35Ch
Watchdog is reset.
7
A35Ch
No action
8
E51Ah
WDKEY is enabled for reset or NMI by next A35Ch.
9
A35Ch
Watchdog is reset.
10
E51Ah
WDKEY is enabled for reset or NMI by next A35Ch.
11
2345h
System reset or NMI; incorrect value written to WDKEY.
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13.3.32 RTI Digital Watchdog Down Counter (RTIDWDCNTR)
This register provides the current value of the DWD down counter. This register is shown in Figure 13-43
and described in Table 13-34.
Figure 13-43. RTI Watchdog Down Counter Register (RTIDWDCNTR) [offset = A0h]
31
25
24
16
Reserved
DWDCNTR
R-0
R-1FFh
15
0
DWDCNTR
R-FFFFh
LEGEND: R = Read only; -n = value after reset
Table 13-34. RTI Watchdog Down Counter Register (RTIDWDCNTR) Field Descriptions
Bit
Field
31-25
Reserved
24-0
DWDCNTR
Value
0
0-1FF FFFFh
Description
Reads return 0 and writes have no effect.
DWD down counter.
Reads return the current counter value.
13.3.33 Digital Windowed Watchdog Reaction Control (RTIWWDRXNCTRL)
This register selects the DWWD reaction if the watchdog is serviced outside the time window. This register
is shown in Figure 13-44 and described in Table 13-35.
Figure 13-44. Digital Windowed Watchdog Reaction Control (RTIWWDRXNCTRL) [offset = A4h]
31
16
Reserved
R-0
15
4
3
0
Reserved
WWDRXN
R-0
R/WP-5h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 13-35. Digital Windowed Watchdog Reaction Control (RTIWWDRXNCTRL) Field Descriptions
Bit
Field
31-4
Reserved
3-0
WWDRXN
Value
0
Description
Reads return 0 and writes have no effect.
The DWWD reaction
5h
The windowed watchdog will cause a reset if the watchdog is serviced outside the time window
defined by the configuration, or if the watchdog is not serviced at all.
Ah
The windowed watchdog will generate a non-maskable interrupt to the CPU if the watchdog is
serviced outside the time window defined by the configuration, or if the watchdog is not serviced
at all.
All other values
The windowed watchdog will cause a reset if the watchdog is serviced outside the time window
defined by the configuration, or if the watchdog is not serviced at all.
Note: The DWWD reaction can be selected by the application even when the DWWD counter is
already enabled. If a change to the WWDRXN is made before the watchdog service window is
opened, then the change in the configuration takes effect immediately. If a change to the
WWDRXN is made when the watchdog service window is already open, then the change in
configuration takes effect only after the watchdog is serviced.
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13.3.34 Digital Windowed Watchdog Window Size Control (RTIWWDSIZECTRL)
This register selects the DWWD window size. This register is shown in Figure 13-45 and described in
Table 13-36.
Figure 13-45. Digital Windowed Watchdog Window Size Control (RTIWWDSIZECTRL) [offset = A8h]
31
16
WWDSIZE
R/WP-0000
15
0
WWDSIZE
R/WP-0005h
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 13-36. Digital Windowed Watchdog Window Size Control (RTIWWDSIZECTRL)
Field Descriptions
Bit
31-0
Field
WWDSIZE
Value
0
Description
The DWWD window size
0000 0005h
100% (The functionality is the same as the standard time-out digital watchdog.)
0000 0050h
50%
0000 0500h
25%
0000 5000h
12.5%
0005 0000h
6.25%
All other values
3.125%
Note: The DWWD window size can be selected by the application even when the DWWD
counter is already enabled. If a change to the WWDSIZE is made before the watchdog service
window is opened, then the change in the configuration takes effect immediately. If a change to
the WWDSIZE is made when the watchdog service window is already open, then the change in
configuration takes effect only after the watchdog is serviced.
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13.3.35 RTI Compare Interrupt Clear Enable Register (RTIINTCLRENABLE)
When the RTI compare event is configured to generate a DMA request or triggers (all triggered by RTI
compare interrupt request flag) to other peripherals, it is often desirable to clear the RTI compare flag
automatically so that the requests can be generated repeatedly without any CPU intervention. This
register works with the RTI compare clear registers to enable an "auto-clear" of the compare interrupt
enable bit after a compare equal event. This register is shown in Figure 13-46 and described in Table 1337.
Figure 13-46. RTI Compare Interrupt Clear Enable Register (RTIINTCLRENABLE) [offset = ACh]
31
28
27
24
23
20
19
16
Reserved
INTCLRENABLE3
Reserved
INTCLRENABLE2
R-0
R/WP-5h
R-0
R/WP-5h
15
12
11
8
7
4
3
0
Reserved
INTCLRENABLE1
Reserved
INTCLRENABLE0
R-0
R/WP-5h
R-0
R/WP-5h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 13-37. RTI Compare Interrupt Clear Enable Register (RTIINTCLRENABLE) Field Descriptions
Bit
Field
Value
31-28 Reserved
0
27-24 INTCLRENABLE3
Description
Reads return 0. Writes have no effect.
Enables the auto-clear functionality on the compare 3 interrupt.
5h
Read: Auto-clear for compare 3 interrupt is disabled.
Privileged Write: Auto-clear for compare 3 interrupt becomes disabled.
All other values
Read: Auto-clear for compare 3 interrupt is enabled.
Privileged Write: Auto-clear for compare 3 interrupt becomes enabled.
23-20 Reserved
0
19-16 INTCLRENABLE2
Reads return 0. Writes have no effect.
Enables the auto-clear functionality on the compare 2 interrupt.
5h
Read: Auto-clear for compare 2interrupt is disabled.
Privileged Write: Auto-clear for compare 2 interrupt becomes disabled.
All other values
Read: Auto-clear for compare 2 interrupt is enabled.
Privileged Write: Auto-clear for compare 2 interrupt becomes enabled.
15-12 Reserved
11-8
0
INTCLRENABLE1
Reads return 0. Writes have no effect.
Enables the auto-clear functionality on the compare 1 interrupt.
5h
Read: Auto-clear for compare 1 interrupt is disabled.
Privileged Write: Auto-clear for compare 1 interrupt becomes disabled.
All other values
Read: Auto-clear for compare 1 interrupt is enabled.
Privileged Write: Auto-clear for compare 1 interrupt becomes enabled.
7-4
Reserved
3-0
INTCLRENABLE0
0
Reads return 0. Writes have no effect.
Enables the auto-clear functionality on the compare 0 interrupt.
5h
Read: Auto-clear for compare 0 interrupt is disabled.
Privileged Write: Auto-clear for compare 0 interrupt becomes disabled.
All other values
Read: Auto-clear for compare 0 interrupt is enabled.
Privileged Write: Auto-clear for compare 0 interrupt becomes enabled.
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13.3.36 RTI Compare 0 Clear Register (RTICMP0CLR)
This registers holds an initial value which is larger than the value in the RTI Compare 0 register
Section 13.3.4. The user needs to choose the value such that the compare clear 0 event occurs before
next compare 0 event. If the Free Running Counter matches the compare value, the compare 0 interrupt
request flag is cleared and the value in the RTIUDCP0 register Section 13.3.16 is added to this register.
This register is shown in Figure 13-47 and described in Table 13-38.
Figure 13-47. RTI Compare 0 Clear Register (RTICMP0CLR) [offset = B0h]
31
16
CMP0CLR
R/WP-0
15
0
CMP0CLR
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 13-38. RTI Compare 0 Clear Register (RTICMP0CLR) Field Descriptions
Bit
31-0
Field
CMP0CLR
Value
0-FFFF FFFFh
Description
Compare 0 clear. This registers holds a compare value. If the Free Running Counter matches
the compare value, the compare 0 interrupt request flag is cleared and the value in the
RTIUDCP0 register Section 13.3.16 is added to this register.
Reads return the current compare clear value.
A privileged write to this register updates the compare clear value.
13.3.37 RTI Compare 1 Clear Register (RTICMP1CLR)
This registers holds an initial value which is larger than the value in the RTI Compare 1 register
Section 13.3.4. The user needs to choose the value such that the compare clear 1 event occurs before
next compare 1 event. If the Free Running Counter matches the compare value, the compare 1 interrupt
request flag is cleared and the value in the RTIUDCP1 register Section 13.3.18 is added to this register.
This register is shown in Figure 13-48 and described in Table 13-39.
Figure 13-48. RTI Compare 1 Clear Register (RTICMP1CLR) [offset = B4h]
31
16
CMP1CLR
R/WP-0
15
0
CMP1CLR
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 13-39. RTI Compare 1 Clear Register (RTICMP1CLR) Field Descriptions
Bit
31-0
Field
CMP0CLR
Value
0-FFFF FFFFh
Description
Compare 1 clear. This registers holds a compare value. If the Free Running Counter matches
the compare value, the compare 1 interrupt request flag is cleared and the value in the
RTIUDCP1 register Section 13.3.18 is added to this register.
Reads return the current compare clear value.
A privileged write to this register updates the compare clear value.
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13.3.38 RTI Compare 2 Clear Register (RTICMP2CLR)
This registers holds an initial value which is larger than the value in the RTI Compare 2 register
Section 13.3.4. The user needs to choose the value such that the compare clear 2 event occurs before
next compare 2 event. If the Free Running Counter matches the compare value, the compare 2 interrupt
request flag is cleared and the value in the RTIUDCP2 register Section 13.3.20 is added to this register.
This register is shown in Figure 13-49 and described in Table 13-40.
Figure 13-49. RTI Compare 2 Clear Register (RTICMP2CLR) [offset = B8h]
31
16
CMP2CLR
R/WP-0
15
0
CMP2CLR
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 13-40. RTI Compare 2 Clear Register (RTICMP2CLR) Field Descriptions
Bit
31-0
Field
CMP2CLR
Value
0-FFFF FFFFh
Description
Compare 2 clear. This registers holds a compare value. If the Free Running Counter matches
the compare value, the compare 2 interrupt request flag is cleared and the value in the
RTIUDCP2 register Section 13.3.20 is added to this register.
Reads return the current compare clear value.
A privileged write to this register updates the compare clear value.
13.3.39 RTI Compare 3 Clear Register (RTICMP3CLR)
This registers holds an initial value which is larger than the value in the RTI Compare 3 register
Section 13.3.4. The user needs to choose the value such that the compare clear 3 event occurs before
next compare 3 event. If the Free Running Counter matches the compare value, the compare 3 interrupt
request flag is cleared and the value in the RTIUDCP3 register Section 13.3.22 is added to this register.
This register is shown in Figure 13-50 and described in Table 13-41.
Figure 13-50. RTI Compare 3 Clear Register (RTICMP3CLR) [offset = BCh]
31
16
CMP3CLR
R/WP-0
15
0
CMP3CLR
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 13-41. RTI Compare 3 Clear Register (RTICMP3CLR) Field Descriptions
Bit
31-0
Field
CMP3CLR
Value
0-FFFF FFFFh
Description
Compare 3 clear. This registers holds a compare value. If the Free Running Counter matches
the compare value, the compare 3 interrupt request flag is cleared and the value in the
RTIUDCP3 register Section 13.3.22 is added to this register.
Reads return the current compare clear value.
A privileged write to this register updates the compare clear value.
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Chapter 14
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Cyclic Redundancy Check (CRC) Controller Module
This chapter describes the cyclic redundancy check (CRC) controller module.
NOTE: This chapter describes a superset implementation of the CRC module that includes features
and functionality that require DMA. Since not all devices have DMA capability, consult your
device-specific datasheet to determine applicability of these features and functions to your
device being used.
Topic
14.1
14.2
14.3
14.4
476
...........................................................................................................................
Overview ........................................................................................................
Module Operation ............................................................................................
Example .........................................................................................................
CRC Control Registers ......................................................................................
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14.1 Overview
The CRC controller is a module that is used to perform CRC (Cyclic Redundancy Check) to verify the
integrity of memory system. A signature representing the contents of the memory is obtained when the
contents of the memory are read into CRC controller. The responsibility of CRC controller is to calculate
the signature for a set of data and then compare the calculated signature value against a pre-determined
good signature value. CRC controller supports two channels to perform CRC calculation on multiple
memories in parallel and can be used on any memory system.
14.1.1 Features
The CRC controller offers:
• Two channels to perform background signature verification on any memory sub-system.
• Data compression on 8, 16, 32, and 64 bit data size.
• Maximum-length PSA (Parallel Signature Analysis) register constructed based on 64 bit primitive
polynomial.
• Each channel has a CRC Value Register that contains the pre-determined CRC value.
• Use timed base event trigger from timer to initiate DMA data transfer.
• Programmable 20-bit pattern counter per channel to count the number of data patterns for
compression.
• Three modes of operation: Auto, Semi-CPU, and Full-CPU.
• For each channel, CRC can be performed either by CRC Controller or by CPU.
• Automatically perform signature verification without CPU intervention in AUTO mode.
• Generate interrupt to CPU in Semi-CPU mode to allow CPU to perform signature verification itself.
• Generate CRC fail interrupt in AUTO mode if signature verification fails.
• Generate Timeout interrupt if CRC is not performed within the time limit.
• Generate DMA request per channel to initiate CRC value transfer.
• Data trace capability on Peripheral Bus Master, Flash and System RAM data buses.
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14.1.2 Block Diagram
Figure 14-1 shows a block diagram of the CRC controller.
NOTE: Only Channel 1 can support data trace. See Section 14.2.11.
Figure 14-1. CRC Controller Block Diagram For One Channel
Read Data Bus(Peripheral, Flash,
System RAM)
Mux
Bus Matrix Module
64
Write Data
Data Synchronization
Register File
64
FSM & Control
Raw Data Register
PSA Signature Register
Trace Enable
HBSTRB[7:0]
CRC Value Register
PSA Sector Signature
Register
64
64
20 Bit
Pattern
Count
Preload
20 Bit
Pattern
Counter
=
DMA
Request
Logic
Mode Reg
DMA Request
CRC
Status Bit
24 Bit
Timeout
Preload
Register
16 Bit
Sector
Count
Preload
478
24 Bit
Time
Out
Counter
CRC Interrupt
Generation
Logic
CRC Fail Interrupt
CRC Overrun Interrupt
CRC Underrun Interrupt
CRC Timeout Interrupt
CH1_INT
CH2_INT
CH3_INT
CH4_INT
16 Bit
Sector
Counter
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14.2 Module Operation
14.2.1 General Operation
There are two channels in CRC controller and for each channel there is a memory-mapped PSA (Parallel
Signature Analysis) Signature Register and a memory-mapped CRC (Cyclic Redundancy Check) Value
register. A memory can be organized into multiple sectors with each sector consisting of multiple data
patterns. A data pattern can be a 8, 16, 32, or 64 bit data. CRC module performs the signature calculation
and compares the signature to a pre-determined value. The PSA Signature Register compresses an
incoming data pattern into a signature when it is written. When one sector of data patterns are written into
PSA Signature Register, a final signature corresponding to the sector is obtained. CRC Value Register
stores the pre-determined signature corresponding to one sector of data patterns. The calculated
signature and the pre-determined signature are then compared to each other for signature verification. To
minimize CPU’s involvement, data patterns transfer can be carried out at the background of CPU using
DMA controller. DMA is setup to transfer data from memory from which the contents to be verified to the
memory-mapped PSA Signature Register. When DMA transfers data to the memory-mapped PSA
Signature Register, a signature is generated. A programmable 20-bit data pattern counter is used for each
channel to define the number of data patterns to calculate for each sector. Signature verification can be
performed automatically by CRC controller in AUTO mode or by CPU itself in Semi-CPU or Full-CPU
mode. In AUTO mode, a self sustained CRC signature calculation can be achieved without any CPU
intervention. CRC Controller also provides data trace capability. Channel 1 can perform data trace on
CPU data bus. During data trace, channel 1 monitors any data being read on CPU data bus and
compresses it. When data trace is enabled for channel 1, all circuits related to DMA request and interrupt
generation and counters are disabled.
14.2.2 CRC Modes of Operation
CRC Controller can operate in AUTO, Semi-CPU, and Full-CPU modes.
14.2.2.1 AUTO Mode
In AUTO mode, CRC Controller in conjunction with DMA controller can perform CRC totally without CPU
intervention. A sustained transfer of data to both the PSA Signature Register and CRC Value Register are
performed in the background of CPU. When a mismatch is detected, an interrupt is generated to CPU. A
16 bit current sector ID register is provided to identify which sector causes a CRC failure.
14.2.2.2 Semi-CPU Mode
In Semi-CPU mode, DMA controller is also utilized to perform data patterns transfer to PSA Signature
Register. Instead of performing signature verification automatically, the CRC controller generates an
compression complete interrupt to CPU after each sector is compressed. Upon responding to the interrupt
the CPU performs the signature verification by reading the calculated signature stored at the PSA Sector
Signature Register and compare it to a pre-determined CRC value.
14.2.2.3 Full CPU Mode
In Full-CPU mode, the CPU does the data patterns transfer and signature verification all by itself. When
CPU has enough throughput, it can perform data patterns transfer by reading data from the memory
system to the PSA Signature Register. After certain number of data patterns are compressed, the CPU
can read from the PSA Signature Register and compare the calculated signature to the pre-determined
CRC signature value. In Full-CPU mode, neither interrupt nor DMA request is generated. All counters are
also disabled.
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14.2.3 PSA Signature Register
The 64-bit PSA Signature Register is based on the primitive polynomial (as in the following equation) to
produce the maximum length LFSR (Linear Feedback Shift Register), as shown in Figure 14-2.
64
4
3
f(x) = x + x + x + x + 1
(25)
Figure 14-2. LFSR
Data
D Q
D Q
D Q
D Q
D Q
D Q
X0
X1
X2
X3
X4
X63
The serial implementation of LFSF has a limitation that, it requires ‘n’ clock cycles to calculate the CRC
values for an ‘n’ bit data stream. The idea is to produce the same CRC value operating on a multi-bit data
stream, as would occur if the CRC were computed one bit at a time over the whole data stream. The
algorithm involves looping to simulate the shifting, and concatenating strings to build the equations after ‘n’
shift.
The parallel CRC calculation based on the polynomial can be illustrated in the following HDL code:
for i in 63 to 0 loop
NEXT_CRC_VAL(0) := CRC_VAL(63) xor DATA(i);
for j in 1 to 63 loop
case j is
when 1|3|4 =>
NEXT_CRC_VAL(j) :=
CRC_VAL(j - 1) xor CRC_VAL(63) xor DATA(i);
when others =>
NEXT_CRC_VAL(j) := CRC_VAL(j - 1);
end case;
end loop;
CRC_VAL := NEXT_CRC_VAL;
end loop;
NOTE: 1) The inner loop is to calculate the next value of each shift register bit after one cycle
2) The outer loop is to simulate 64 cycles of shifting. The equation for each shift register bit
is thus built before it is compressed into the shift register.
3) MSB of the DATA is shifted in first
There is one PSA Signature Register per CRC channel. PSA Signature Register can be both read and
written. When it is written, it can either compress the data or just capture the data depending on the state
of CHx_MODE bits. If CHx_MODE=Data Capture, a seed value can be planted in the PSA Signature
Register without compression. Other modes other than Data Capture will result with the data compressed
by PSA Signature Register when it is written. Each channel can be planted with different seed value
before compression starts. When PSA Signature Register is read, it gives the calculated signature.
CRC Controller should be used in conjunction with the on chip DMA controller to produce optimal system
performance. The incoming data pattern to PSA Signature Register is typically initiated by the DMA
master. When DMA is properly setup, it would read data from the pre-determined memory system and
write them to the memory-mapped PSA Signature Register. Each time PSA Signature Register is written a
signature is generated. CPU itself can also perform data transfer by reading from the memory system and
perform write operation to PSA Signature Register if CPU has enough throughput to handle data patterns
transfer.
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After system reset and when AUTO mode is enabled, CRC Controller automatically generates a DMA
request to request the pre-determined CRC value corresponding to the first sector of memory to be
checked.
In AUTO mode, when one sector of data patterns is compressed, the signature stored at the PSA
Signature Register is first copied to the PSA Sector Signature Register and PSA Signature Register is
then cleared out to all zeros. An automatic signature verification is then performed by comparing the
signature stored at the PSA Sector Signature Register to the CRC Value Register. After the comparison
the CRC Controller can generate a DMA request. Upon receiving the DMA request the DMA controller will
update the CRC Value Register by transferring the next pre-determined signature value associated with
the next sector of memory system. If the signature verification fails then CRC Controller can generate a
CRC fail interrupt.
In Full-CPU mode, no DMA request and interrupt are generated at all. The number of data patterns to be
compressed is determined by CPU itself. Full-CPU mode is useful when DMA controller is not available to
perform background data patterns transfer. The OS can periodically generate a software interrupt to CPU
and use CPU to accomplish data transfer and signature verification.
CRC Controller supports doubleword, word, half word and byte access to the PSA Signature Register.
During a non-doubleword write access, all unwritten byte lanes are padded with zero’s before
compression. Note that comparison between PSA Sector Signature Register and CRC Value Register is
always in 64 bit because a compressed value is always expressed in 64 bit.
There is a software reset per channel for PSA Signature Register. When set, the PSA Signature Register
is reset to all zeros.
PSA Signature Register is reset to zero under the following conditions:
• System reset
• PSA Software reset
• One sector of data patterns are compressed
14.2.4 PSA Sector Signature Register
After one sector of data is compressed, the final resulting signature calculated by PSA Signature Register
is transferred to the PSA Sector Signature Register. PSA Signature Register is a read only register.
During Semi-CPU mode, the host CPU should read from the PSA Sector Signature Register instead of
reading from PSA Signature Register for signature verification to avoid data coherency issue. The PSA
Signature Register can be updated with new signature before the host CPU is able to retrieve it.
In Semi-CPU mode, no DMA request is generated. When one sector of data patterns is compressed, CRC
controller first generates a compression complete interrupt. Responding to the interrupt, CPU will in the
ISR read the PSA Sector Signature Register and compare it to the known good signature or write the
signature value to another memory location to build a signature file. In Semi-CPU mode, CPU must
perform the signature verification in a manner to prevent any overrun condition. The overrun condition
occurs when the compression complete interrupt is generated after one sector of data patterns is
compressed and CPU has not read from the PSA Sector Signature Register to perform necessary
signature verification before PSA Sector Signature Register is overridden with a new value. An overrun
interrupt can be enable to generate when overrun condition occurs. During Semi-CPU mode, the host
CPU should read from the PSA Sector Signature Register instead of reading from PSA Signature Register
for signature verification to avoid data coherency issue. The PSA Signature Register can be updated with
new signature before the host CPU is able to retrieve it.
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14.2.5 CRC Value Register
Associated with each channel there is a CRC Value Register. The CRC Value Register stores the predetermined CRC value. After one sector of data patterns is compressed by PSA Signature Register, CRC
Controller can automatically compare the resulting signature stored at the PSA Sector Signature Register
with the pre-determined value stored at the CRC Value Register if AUTO mode is enabled. If the signature
verification fails, CRC Controller can be enabled to generate an CRC fail interrupt. When the channel is
set up for Semi-CPU mode, CRC controller first generates a compression complete interrupt to CPU.
Upon servicing the interrupt, CPU will then read the PSA Sector Signature Register and then read the
corresponding CRC value stored at another location and compare them. CPU should not read from the
CRC Value Register during Semi-CPU or Full-CPU mode because the CRC Value Register is not updated
during these two modes.
In AUTO mode, for first sector’s signature, DMA request is generated when mode is programmed to
AUTO. For subsequent sectors, DMA request is generated after each sector is compressed. Responding
to the DMA request, DMA controller reloads the CRC Value Register for the next sector of memory system
to be checked.
When CRC Value Register is updated with a new CRC value, an internal flag is set to indicate that CRC
Value Register contains the most current value. This flag is cleared when CRC comparison is performed.
Each time at the end of the final data pattern compression of a sector, CRC Controller first checks to see
if the corresponding CRC Value Register has the most current CRC value stored in it by polling the flag. If
the flag is set then the CRC comparison can be performed. If the flag is not set then it means the CRC
Value Register contains stale information. A CRC underrun interrupt is generated. When an underrun
condition is detected, signature verification is not performed.
CRC Controller supports doubleword, word, half word and byte access to the CRC Value Register. As
noted before comparison between PSA Sector Signature Register and CRC Value Register during AUTO
mode is carried out in 64 bit.
14.2.6 Raw Data Register
The raw or un-compressed data written to the PSA Signature Register is also saved in the Raw Data
Register. This register is read only.
14.2.7 Example DMA Controller Setup
DMA controller needs to be setup properly in either AUTO or Semi-CPU mode as DMA controller is used
to transfer data patterns. Hardware or a combination of hardware and software DMA triggering are
supported.
14.2.7.1 AUTO Mode Using Hardware Timer Trigger
There are two DMA channels associated with each CRC channel when in AUTO mode. One DMA channel
is setup to transfer data patterns from the source memory to the PSA Signature Register. The second
DMA channel is setup to transfer the pre-determined signature to the CRC Value Register. The trigger
source for the first DMA channel can be either by hardware or by software. As illustrated in Figure 14-3 a
timer can be used to trigger a DMA request to initiate transfer from the source memory system to PSA
Signature Register. In AUTO mode, CRC Controller also generates DMA request after one sector of data
patterns is compressed to initiate transfer of the next CRC value corresponding to the next sector of
memory. Thus a new CRC value is always updated in the CRC Value Register by DMA synchronized to
each sector of memory.
A block of memory system is usually divided into many sectors. All sectors are the same size. The sector
size is programmed in the CRC_PCOUNT_REGx and the number of sectors in one block is programmed
in the CRC_SCOUNT_REGx of the respective channel. CRC_PCOUNT_REGx multiplies
CRC_SCOUNT_REGx and multiplies transfer size of each data pattern should give the total block size in
number of bytes.
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The total size of the memory system to be examined is also programmed in the respective transfer count
register inside DMA module. The DMA transfer count register is divided into two parts. They are element
count and frame count. Note that an HW DMA request can be programmed to trigger either one frame or
one entire block transfer. In Figure 14-3, an HW DMA request from a timer is used as a trigger source to
initiate DMA transfer. If all four CRC channels are active in AUTO mode then a total of four DMA requests
would be generated by CRC Controller.
Figure 14-3. AUTO Mode Using Hardware Timer Trigger
Timer
DMA Controller
Memory System
HW DMA Req
HW DMA Req
Sector 1
Sector 2
.DMA Request Event Sync.
DMA channel 0
CRC
Controller
one
block
PSA Sig Reg
Ch1
DMA channel p
DMA channel q
CRC Value Reg
Sector n
Sector 1 CRC value
Sector 2 CRC value
PSA Sig Reg
Ch4
CRC Value Reg
DMA channel 15
Sector n CRC value
14.2.7.2 AUTO Mode Using Software Trigger
The data patterns transfer can also be initiated by software. CPU can generate a software DMA request to
activate the DMA channel to transfer data patterns from source memory system to the PSA Signature
Register. To generate a software DMA request CPU needs to set the corresponding DMA channel in the
DMA software trigger register. Note that just one software DMA request from CPU is enough to complete
the entire data patterns transfer for all sectors. See Figure 14-4 for an illustration.
Figure 14-4. AUTO Mode With Software CPU Trigger
CPU
DMA Controller
Memory System
SW DMA Req
HW DMA Req
CRC
Controller
Sector 1
Sector 2
.DMA Request Event Sync.
DMA channel 0
one
block
PSA Sig Reg
Ch1
CRC Value Reg
DMA channel p
DMA channel q
Sector n
Sector 1 CRC value
Sector 2 CRC value
PSA Sig Reg
Ch4
CRC Value Reg
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14.2.7.3 Semi-CPU Mode Using Hardware Timer Trigger
During semi-CPU mode, no DMA request is generated by CRC controller. Therefore, no DMA channel is
allocated to update CRC Value Register. CPU should not read from CRC Value Register in semi-CPU
mode as it contains stale value. Note that no signature verification is performed at all during this mode.
Similar to AUTO mode, either by hardware or by software DMA request can be used as a trigger for data
patterns transfer. Figure 14-5 illustrates the DMA setup using semi-CPU mode with hardware timer trigger.
Figure 14-5. Semi-CPU Mode With Hardware Timer Trigger
Timer
DMA Controller
Memory System
HW DMA Req
.DMA Request Event Sync.
Sector 1
Sector 2
DMA channel 0
CRC
Controller
one
block
PSA Reg
Ch1
DMA channel p
DMA channel q
CRC Reg
Sector n
PSA Reg
Ch4
CRC Reg
DMA channel 31
Table 14-1. CRC Modes in Which DMA Request and Counter Logic are Active or Inactive
Mode
DMA Request
Pattern Counter
Sector Counter
Timeout Counter
AUTO
Active
Active
Active
Active
Semi-CPU
Inactive
Active
Active
Active
Full-CPU
Inactive
Inactive
Inactive
Inactive
14.2.8 Pattern Count Register
There is a 20-bit data pattern counter for every CRC channel. The data pattern counter is a down counter
and can be pre-loaded with a programmable value stored in the Pattern Count Register. When the data
pattern counter reaches zero, a compression complete interrupt is generated in Semi-CPU mode and an
automatic signature verification is performed in AUTO mode. In AUTO only, DMA request is generated to
trigger the DMA controller to update the CRC Value Register.
NOTE: The data pattern count should be divisible by the total transfer count as programmed in DMA
controller. The total transfer count is the product of element count and frame count.
14.2.9 Sector Count Register/Current Sector Register
Each channel contains a 16 bit sector counter. The sector count register stores the number of sectors.
Sector counter is a free running counter and is incremented by one each time when one sector of data
patterns is compressed. When the signature verification fails, the current value stored in the sector
counter is saved into current sector register. If signature verification fails, CPU can read from the current
sector register to identify the sector which causes the CRC mismatch. To aid and facilitate the CPU in
determining the cause of a CRC failure, it is advisable to use the following equation during CRC and DMA
setup:
CRC Pattern Count × CRC Sector Count = DMA Element Count × DMA Frame Count
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The current sector register is frozen from being updated until both the current sector register is read and
CRC fail status bit is cleared by CPU. If CPU does not respond to the CRC failure in a timely manner
before another sector produces a signature verification failure, the current sector register is not updated
with the new sector number. An overrun interrupt is generate instead. If current sector register is already
frozen with an erroneous sector and emulation is entered with SUSPEND signal goes to high then the
register still remains frozen even it is read.
In Semi-CPU mode, the current sector register is used to indicate the sector for which the compression
complete has last happened.
The current sector register is reset when the PSA software reset is enabled.
NOTE: Both data pattern count and sector count registers must be greater than or equal to one for
the counters to count. After reset, pattern count and sector count registers default to zero
and the associated counters are inactive.
14.2.10 Interrupt
The CRC controller generates several types of interrupts per channel. Associated with each interrupt,
there is an interrupt enable bit. No interrupt is generated in Full-CPU mode.
• Compression complete interrupt
• CRC fail interrupt
• Overrun interrupt
• Underrun interrupt
• Timeout interrupt
Table 14-2. Modes in Which Interrupt Condition Can Occur
AUTO
Semi-CPU
Full-CPU
Compression Complete
no
yes
no
CRC Fail
yes
no
no
Overrun
yes
yes
no
Underrun
yes
no
no
Timeout
yes
yes
no
14.2.10.1 Compression Complete Interrupt
Compression complete interrupt is generated in Semi-CPU mode only. When the data pattern counter
reaches zero, the compression complete flag is set and the interrupt is generated.
14.2.10.2 CRC Fail Interrupt
CRC fail interrupt is generated in AUTO mode only. When the signature verification fails, the CRC fail flag
is set,. CPU should take action to address the fail condition and clear the CRC fail flag after it resolves the
CRC mismatch.
14.2.10.3 Overrun Interrupt
Overrun interrupt is generated in either AUTO or Semi-CPU mode. During AUTO mode, if a CRC fail is
detected, then the current sector number is recorded in the current sector register. If CRC fail status bit is
not cleared and current sector register is not read by the host CPU before another CRC fail is detected for
another sector, then an overrun interrupt is generated. During Semi-CPU mode, when the data pattern
counter finishes counting, it generates a compression complete interrupt. At the same time, the signature
is copied into the PSA Sector Signature Register. If the host CPU does not read the signature from PSA
Sector Signature Register before it is updated again with a new signature value, then an overrun interrupt
is generated.
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14.2.10.4 Underrun Interrupt
Underrun interrupt only occurs in AUTO mode. The interrupt is generated when the CRC Value Register is
not updated with the corresponding signature when the data pattern counter finishes counting. During
AUTO mode, CRC Controller generates DMA request to update CRC Value Register in synchronization to
the corresponding sector of the memory. Signature verification is also performed if underrun condition is
detected. And CRC fail interrupt is generated at the same time as the underrun interrupt.
14.2.10.5 Timeout Interrupt
To ensure that the memory system is examined within a pre-defined time frame and no loss of incoming
data there is a 24 bit timeout counter per CRC channel. The 24 bit timeout down counter can be preloaded with two different pre-load values, watchdog timeout pre-load value (CRC_WDTOPLDx) and block
complete timeout pre-load value (CRC_BCTOPLDx). The timeout counter is clocked by a prescaler clock
which is permanently running at division 64 of HCLK clock.
First pattern of data must be transferred by the DMA before the timeout counter expires, Watchdog
timeout pre-load register (CRC_WDTOPLDx) is used as timeout counter. Block complete timeout pre-load
register (CRC_BCTOPLDx) is used to check if one complete block of data patterns are compressed within
a specific time frame. The timeout counter is first pre-loaded with CRC_WDTOPLDx after either AUTO or
Semi-CPU mode is selected and starts to down count. If the timeout counter expires before DMA transfers
any data pattern to PSA Signature Register then a timeout interrupt is generated. An incoming data
pattern before the timeout counter expires will automatically pre-load the timeout counter with
CRC_BCTOPLDx the block complete timeout pre-load value.
Block complete timeout pre-load value is used to check it one block of data patterns are compressed
within a given time limit. If the timeout counter pre-loaded with CRC_BCTOPLDx value expires before one
block of data patterns are compressed a timeout interrupt is generated. When one block (pattern count x
sector count) of data patterns are compressed before the counter has expired, the counter is pre-loaded
with CRC_WDTOPLDx value again. If the timeout counter is pre-loaded with zero then the counter is
disable and no timeout interrupt is generated.
In Figure 14-6, a timer generates DMA request every 10ms to trigger one block (pattern count x sector
count) transfer. Since we want to make sure that DMA does start to transfer a block every 10 ms we
would set the first pre-load value to 10ms in CRC_WDTOPLDx. We also want to make sure that one block
of data patterns are compressed within 4ms. With such a requirement, we would set the second pre-load
value to 4ms in CRC_BCTOPLDx register.
Figure 14-6. Timeout Example 1
Timer
HW DMA req every 10 ms
0 ms
10 ms
20 ms
30 ms
Time scale
3 ms
13 ms
23 ms
Data
Timeout
Counter
WD
pre-load
10 9 8 7 6 5 4 3 4 3 2 10 9 8 7 6 5 4 4 3 2 10 9 8 7 6 5 4 4 3 2 10 9 8 7 6 5 4
BC
WD
pre-load pre-load
BC
WD
pre-load pre-load
BC
WD
pre-load pre-load
WD pre-load = watchdog timeout pre-load (CRC_WDTOPLDx)
BC pre-load = block complete timeout pre-load (CRC_BCTOPLDx)
Note: No timeout interrupt is generated in this example since each block of data patterns are compressed in 3 ms and DMA does
initiate a block transfer every 10 ms.
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Figure 14-7. Timeout Example 2
Timer
HW DMA req every 10 ms
0 ms
10 ms
20 ms
30 ms
Time scale
6 ms
16 ms
26 ms
Data
Timeout
Counter
10 9 8 7 6 5 4 3 4 3 2 1 0 10 9 8 7 6 4 3 2 1 0 10 9 8 7 6 4 3 2 1 0 10 9 8 7 6
BC
pre-load
WD
pre-load
WD
pre-load
BC
pre-load
WD
pre-load
time out
interrup
BC
pre-load
WD
pre-load
time out
interrup
time out
interrup
WD pre-load = watchdog timeout pre-load (CRC_WDTOPLDx)
BC pre-load = block complete timeout pre-load (CRC_BCTOPLDx)
Note: Timeout interrupt is generated in this example since each block of data patterns are compressed in 6 ms and this is
out of the 4ms time frame.
Figure 14-8. Timeout Example 3
Timer
HW DMA req every 10 ms
0 ms
10 ms
20 ms
30 ms
Time scale
3 ms
15 ms
25 ms
Data
Timeout
Counter
10 9 8 7 6 5 4 3 4 3 2 10 9 8 7 6 5 4 3 2 1 0 4 4 3 2 10 9 8 7 6 5 4 4 3 2 10 9
WD
pre-load
BC
WD
pre-load pre-load
BC
pre-load
WD
pre-load
BC
WD
pre-load pre-load
timeout
interrupt
WD pre-load = watchdog timeout pre-load (CRC_WDTOPLDx)
BC pre-load = block complete timeout pre-load (CRC_BCTOPLDx)
Note: Timeout interrupt is generated in this example since DMA can not transfer the second block of data within 10ms time
limit and the reason may be that DMA is set up in fixed priority scheme and DMA is serving other higher priority channels
at the time before it can service the timer request.
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14.2.10.6 Interrupt Offset Register
CRC Controller only generates one interrupt request to interrupt manager. A interrupt offset register is
provided to indicate the source of the pending interrupt with highest priority. Table 14-3 shows the offset
interrupt vector address of each interrupt condition in an ascending order of priority.
Table 14-3. Interrupt Offset Mapping
Offset Value
14.2.10.7
Interrupt Condition
0
Phantom
1h
Ch1 CRC Fail
2h
Ch2 CRC Fail
3h-8h
Reserved
9h
Ch1 Compression Complete
Ah
Ch2 Compression Complete
Bh-10h
Reserved
11h
Ch1 Overrun
12h
Ch2 Overrun
13h-18h
Reserved
19h
Ch1 Underrun
1Ah
Ch2 Underrun
1Bh-20h
Reserved
21h
Ch1 Timeout
22h
Ch2 Timeout
23h-24h
Reserved
Error Handling
When an interrupt is generated, host CPU should take appropriate actions to identify the source of error
and restart the respective channel in DMA and CRC module. To restart a CRC channel, the user should
perform the following steps in the ISR:
1. Write to software reset bit in CRC_CTRL register to reset the respective PSA Signature Register.
2. Reset the CHx_MODE bits to 00 in CRC_CTRL register as Data capture mode.
3. Set the CHx_MODE bits in CRC_CTRL register to desired new mode again.
4. Release software reset.
The host CPU should use byte write to restart each individual channel.
14.2.11 CPU Data Trace
CRC channel 1 can be used to snoop Flash, System RAM and Peripheral Bus Master Data buses.
However, at any one point only one bus is snooped. It is possible to disable the snooping of any of the
buses by programming CRC_BUS_SEL register. While snooping the data, there is a priority scheme
implemented between the buses. Peripheral Bus Master has the highest priority followed by Flash, Even
System RAM and Odd System RAM. For each data read by CPU on its data bus the same data is
compressed in the PSA Signature Register. A write to PSA Signature Register does not get compressed.
Therefore, it is possible to write a seed value into PSA Signature Register before the bus snooping takes
place. During data trace mode, all interrupts and DMA request logic are inactive. For non double word
read on the data bus, all un-selected byte lanes are padded with zero during compression.
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14.2.11.1 Data Capture Mode used in Conjunction with Data Trace
Data capture mode is especially useful when it is used in conjunction when data trace for channel 1 is
enabled (CRC_CTRL2.CH1_TRACEEN = 1). The seed value can be planted in PSA Signature Register
during data capture mode by writing a seed value into PSA Signature Register. The data trace enable bit
is then set to snoop and compress any read transaction on DAHB bus. When trace enable bit is set,
CRC_CTRL2.CH1_MODE is automatically reset to 0 (data capture mode). To change from one mode to
another mode in the middle of an on-going mode, perform the following steps:
1. Assert software reset for the respective channel.
2. Change from the current active mode to Data Capture mode (CRC_CTRL2.CH1_MODE = 0).
3. Change from Data Capture mode to the new mode.
4. Release software reset.
14.2.12 Power Down Mode
CRC module can be put into power down mode when the power down control bit PWDN is set. The
module wakes up when the PWDN bit is cleared. When CRC controller is in power down mode, no data
tracing alone will happen. However, if CRC registers are accessed then data trace happens from channel
1.
14.2.13 Emulation
A read access from a register in functional mode can sometimes trigger a certain internal event to follow.
For example, reading an interrupt offset register triggers an event to clear the corresponding interrupt
status flag. During emulation when SUSPEND signal is high, a read access from any register should only
return the register contents to the bus and should not trigger or mask any event as it would have in
functional mode. This is to prevent debugger from reading the interrupt offset register during refreshing
screen and cause the corresponding interrupt status flag to get cleared. Timeout counters are stopped to
generate timeout interrupts in emulation mode. No Peripheral Master bus error should be generated if
reading from the unimplemented locations. When channel 1 is placed under data trace, the PSA Signature
Register does not compress any data read on CPU data bus when suspend is active.
14.2.14 Peripheral Bus Interface
CRC is a Peripheral slave module. The register interface is similar to other peripheral modules. CRC
supports following features:
• Different sizes of burst operation.
• Aligned and unaligned accesses.
• Abort is generated for any illegal address accesses.
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Example
This section illustrates several of the ways in which the CRC Controller can be utilized to perform CRC.
14.3.1 Example: Auto Mode Using Time Based Event Triggering
A large memory area with 2Mbyte (256k doubleword) is to be checked in the background of CPU. CRC is
to be performed every 1K byte (128 doubleword). Therefore there should be 2048 pre-recorded CRC
values. For illustration purpose, we map channel 1 CRC Value Register to DMA channel 1 and channel 1
PSA Signature Register to DMA channel 2. Assume all DMA transfers are carried out in 64-bit transfer
size.
14.3.1.1 DMA Setup
• Set up DMA channel 1 with the starting address from which the pre-determined CRC values are
stored. Set up the destination address to the memory-mapped channel 1 CRC Value Register. Put the
source address at post increment addressing mode and put the destination address at constant
addressing mode. Use hardware DMA request for channel 1 to trigger a frame transfer.
• Set up DMA channel 2 with the source address from which the contents of memory to be verified. Set
up the destination address to the memory-mapped channel 1 PSA Signature Register. Program the
element transfer count to 128 and the frame transfer count to 2048. Put the source address at post
increment addressing mode and put the destination address at constant address mode. Use hardware
DMA request for channel 2 to trigger an entire block transfer.
14.3.1.2 Timer Setup
The timer can be any general-purpose timer that is capable of generating a time-based DMA request.
• Set up timer to generate DMA request associated with DMA channel 2. For example, an OS can set up
the timer to generate a DMA request every 10ms.
14.3.1.3
•
•
•
•
CRC Setup
Program the pattern count to 128.
Program the sector count to 2048.
For example, we want the entire 2Mbytes to be compressed within 5ms. We can program the block
complete timeout pre-load (CRC_BCTOPLDx) value to 15625 (5 ms / (1 HCLK period × 64)) if CRC is
operating at 200 MHz.
Enable AUTO mode and all interrupts.
After AUTO mode is selected, CRC Controller automatically generates a DMA request on channel 1.
Around the same time the timer module also generates a DMA request on DMA channel 2. When the first
incoming data pattern arrives at the PSA Signature Register, the CRC Controller will compress it. After
some time, the DMA controller would update the CRC Value Register with a pre-determined value
matching the calculated signature for the first sector of 128 64 bit data patterns. After one sector of data
patterns are compressed, the CRC Controller generate a CRC fail interrupt if signature stored at the PSA
Sector Signature Register does not match the CRC Value Register. CRC Controller generates a DMA
request on DMA channel 1 when one sector of data patterns are compressed. This routine will continue
until the entire 2Mbyte are consumed. If the timeout counter reached zero before the entire 2Mbytes are
compressed a timeout interrupt is generated. After 2MBytes are transferred, the DMA can generate an
interrupt to CPU. The entire operation will continue again when DMA responds to the DMA request from
both the timer and CRC Controller. The CRC is performed totally without any CPU intervention.
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14.3.2 Example: Auto Mode Without Using Time Based Triggering
A small but highly secured memory area with 1kbytes is to be checked in the background of CPU. CRC is
to be performed every 1Kbytes. Therefore there is only one pre-recorded CRC value. For illustration
purpose, we map channel 1 CRC Value Register to DMA channel 1 and channel 1 PSA Signature
Register to DMA channel 2. Assume all transfers carried out by DMA are in 64 bit transfer size.
14.3.2.1 DMA Setup
• Set up DMA channel 1 with the source address from which the pre-determined CRC value is stored.
Set up the destination address to the memory-mapped channel 1 CRC Value Register. Put the source
address at constant addressing mode and put the destination address at constant addressing mode.
Use hardware DMA request for channel 1.
• Set up DMA channel 2 with the source address from which the memory area to be verified. Set up the
destination address to the memory-mapped channel 1 PSA Signature Register. Program the element
transfer count to 128 and the frame transfer count to 1. Put the source address at post increment
addressing mode and put the destination address at constant address mode. Generate a software
DMA request on channel 2 after CRC has completed its setup. Enable autoinitiation for DMA channel
2.
14.3.2.2
•
•
•
•
CRC Setup
Program the pattern count to 128.
Program the sector count to 1.
Leaving the timeout count register with the reset value of zero means no timeout interrupt is generated.
Enable AUTO mode and all interrupts.
After AUTO mode is selected, the CRC Controller automatically generates a DMA request on channel 1.
At the same time the CPU generates a software DMA request on DMA channel 2. When the first
incoming data pattern arrives at the PSA Signature Register, the CRC Controller will compress it. After
some time, the DMA controller would update the CRC Value Register with a pre-determined value
matching the calculated signature for the first sector of 128 64 bit data patterns. After one sector of data
patterns are compressed, the CRC Controller generates a CRC fail interrupt if signature stored at the PSA
Sector Signature Register does not match the CRC Value Register. CRC Controller generates a DMA
request on DMA channel 1 again after one sector is compressed. After 1kbytes are transferred, the DMA
can generate an interrupt to CPU. Responding to the DMA interrupt CPU can restart the CRC routine by
generating a software DMA request onto channel 2 again.
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14.3.3 Example: Semi-CPU Mode
If DMA controller is available in a system, the CRC module can also operate in semi-CPU mode. This
means that CPU can still make use of the DMA to perform data patterns transfer to CRC controller in the
background. The difference between semi-CPU mode and AUTO mode is that CRC controller does not
automatically perform the signature verification. CRC controllers generates a compression complete
interrupt to CPU when the one sector of data patterns are compressed. CPU needs to perform the
signature verification itself.
A memory area with 2Mbyte is to be verified with the help of the CPU. CRC operation is to be performed
every 1K byte. Since there are 2Mbyte (256k doublewords) of memory to be check and we want to
perform a CRC every 1Kbyte (128 doublewords) and therefore there should be 2048 pre-recorded CRC
values. In Semi-CPU mode, the CRC Value Register is not updated and contains indeterminate data.
14.3.3.1 DMA Setup
Set up DMA channel 1 with the source address from which the memory area to be verified are mapped.
Set up the destination address to the memory-mapped channel 1 PSA Signature Register. Put the starting
address at post increment addressing mode and put the destination address at constant address mode.
Use hardware DMA request to trigger an entire block transfer for channel 1. Disable autoinitiation for DMA
channel 1.
14.3.3.2 Timer Setup
The timer can be any general-purpose timer that is capable of generating a time-based DMA request.
Set up timer to generate DMA request associated with DMA channel 1. For example, an OS can set up
the timer to generate a DMA request every 10ms.
14.3.3.3
•
•
•
•
CRC Setup
Program the pattern count to 128.
Program the sector count to 2048.
For example, we want the entire 2Mbytes to be compressed within 5ms. We can program the block
complete timeout pre-load value to 15625 (5 ms / (1 HCLK period × 64)) if CRC is operating at 200
MHz.
Enable Semi-CPU mode and enable all interrupts.
The timer module first generates a DMA request on DMA channel 1 when it is enabled. When the first
incoming data pattern arrives at the PSA Signature Register, the CRC controller will compress it. After one
sector of data patterns are compressed, the CRC controller generate a compression complete interrupt.
Upon responding to the interrupt the CPU would read from the PSA Sector Signature Register. It is up to
the CPU on how to deal with the PSA value just read. It can compare it to a known signature value or it
can write it to another memory location to build a signature file or even transfer the signature out of the
device via SCI or SPI. This routine will continue until the entire 2Mbyte are consumed. The latency of the
interrupt response from CPU can cause overrun condition. If CPU does not read from PSA Sector
Signature Register before the PSA value is overridden with the signature of the next sector of memory, an
overrun interrupt will be generated by CRC controller.
14.3.4 Example: Full-CPU Mode
In a system without the availability of DMA controller, the CRC routine can be operated by CPU provided
the CPU has enough throughput. CPU needs to read from the memory area from which CRC is to be
performed.
A memory area with 2Mbyte is to be checked with the help of the CPU. CRC verification is to be
performed every 1K byte. In CPU mode, the CRC Value Register is not updated and contains
indeterminate data.
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14.3.4.1 CRC Setup
• All control registers can be left in their reset state. Only enable Full-CPU mode.
CPU itself reads from the memory and write the data to the PSA Signature Register inside CRC
Controller. When the first incoming data pattern arrives at the PSA Signature Register, the CRC Controller
will compress it. After 2MBytes data patterns are compressed, CPU can read from the PSA Signature
Register. It is up to the CPU on how to deal with the PSA signature value just read. It can compare it to a
known signature value stored at another memory location.
14.4 CRC Control Registers
All registers are in word boundary. 64-, 32-, 16-, and 8-bit write accesses are supported to all registers.
The base address for the control registers is FE00 0000h.
Table 14-4. CRC Control Registers
Offset
Acronym
Register Description
0h
CRC_CTRL0
CRC Global Control Register
Section 14.4.1
Section
8h
CRC_CTRL1
CRC Global Control Register 1
Section 14.4.2
10h
CRC_CTRL2
CRC Global Control Register 2
Section 14.4.3
18h
CRC_INTS
CRC Interrupt Enable Set Register
Section 14.4.4
20h
CRC_INTR
CRC Interrupt Enable Reset Register
Section 14.4.5
28h
CRC_STATUS
CRC Interrupt Status Register
Section 14.4.6
30h
CRC_INT_OFFS_ET_REG
CRC Interrupt Offset Register
Section 14.4.7
38h
CRC_BUSY
CRC Busy Register
Section 14.4.8
40h
CRC_PCOUNT_REG1
CRC Channel 1 Pattern Counter Preload Register
Section 14.4.9
44h
CRC_SCOUNT_REG1
CRC Channel 1 Sector Counter Preload Register
Section 14.4.10
48h
CRC_CURSEC_REG1
CRC Channel 1 Current Sector Register
Section 14.4.11
4Ch
CRC_WDTOPLD1
CRC Channel 1 Watchdog Timeout Preload Register
Section 14.4.12
50h
CRC_BCTOPLD1
CRC Channel 1 Block Complete Timeout Preload Register
Section 14.4.13
60h
PSA_SIGREGL1
Channel 1 PSA Signature Low Register
Section 14.4.14
64h
PSA_SIGREGH1
Channel 1 PSA Signature High Register
Section 14.4.15
68h
CRC_REGL1
Channel 1 CRC Value Low Register
Section 14.4.16
6Ch
CRC_REGH1
Channel 1 CRC Value High Register
Section 14.4.17
70h
PSA_SECSIGREGL1
Channel 1 PSA Sector Signature Low Register
Section 14.4.18
74h
PSA_SECSIGREGH1
Channel 1 PSA Sector Signature High Register
Section 14.4.19
78h
RAW_DATAREGL1
Channel 1 Raw Data Low Register
Section 14.4.20
7Ch
RAW_DATAREGH1
Channel 1 Raw Data High Register
Section 14.4.21
80h
CRC_PCOUNT_REG2
CRC Channel 2 Pattern Counter Preload Register
Section 14.4.22
84h
CRC_SCOUNT_REG2
CRC Channel 2 Sector Counter Preload Register
Section 14.4.23
88h
CRC_CURSEC_REG2
CRC Current Sector Register 2
Section 14.4.24
8Ch
CRC_WDTOPLD2
CRC Channel 2 Watchdog Timeout Preload Register A
Section 14.4.25
90h
CRC_BCTOPLD2
CRC Channel 2 Block Complete Timeout Preload Register B
Section 14.4.26
A0h
PSA_SIGREGL2
Channel 2 PSA Signature Low Register
Section 14.4.27
A4h
PSA_SIGREGH2
Channel 2 PSA Signature High Register
Section 14.4.28
A8h
CRC_REGL2
Channel 2 CRC Value Low Register
Section 14.4.29
ACh
CRC_REGH2
Channel 2 CRC Value High Register
Section 14.4.30
B0h
PSA_SECSIGREGL2
Channel 2 PSA Sector Signature Low Register
Section 14.4.31
B4h
PSA_SECSIGREGH2
Channel 2 PSA Sector Signature High Register
Section 14.4.32
B8h
RAW_DATAREGL2
Channel 2 Raw Data Low Register
Section 14.4.33
BCh
RAW_DATAREGH2
Channel 2 Raw Data High Register
Section 14.4.34
140h
CRC_BUS_SEL
Data Bus Selection Register
Section 14.4.35
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14.4.1 CRC Global Control Register 0 (CRC_CTRL0)
Figure 14-9. CRC Global Control Register 0 (CRC_CTRL0) [offset = 00h]
31
16
Reserved
R-0
15
9
8
Reserved
CH2_PSA_SWREST
R-0
R/W-0
7
1
0
Reserved
CH1_PSA_SWREST
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-5. CRC Global Control Register 0 (CRC_CTRL0) Field Descriptions
Bit
31-9
8
7-1
0
Field
Value
Reserved
0
CH2_PSA_SWREST
Description
Reads return 0. Writes have no effect.
Channel 2 PSA Software Reset. When set, the PSA Signature Register is reset to all zero.
Software reset does not reset software reset bit itself. Therefore, CPU is required to clear
this bit by writing a 0.
Reserved
0
PSA Signature Register is not reset.
1
PSA Signature Register is reset.
0
Reads return 0. Writes have no effect.
CH1_PSA_SWREST
Channel 1 PSA Software Reset. When set, the PSA Signature Register is reset to all zero.
Software reset does not reset software reset bit itself. Therefore, CPU is required to clear
this bit by writing a 0.
0
PSA Signature Register is not reset.
1
PSA Signature Register is reset.
14.4.2 CRC Global Control Register (CRC_CTRL1)
Figure 14-10. CRC Global Control Register 1 (CRC_CTRL1) [offset = 08h]
31
16
Reserved
R-0
15
1
0
Reserved
PWDN
R-0
RW-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-6. CRC Global Control Register 1 (CRC_CTRL1) Field Descriptions
Bit
31-1
0
494
Field
Reserved
Value
0
PWDN
Description
Reads return 0. Writes have no effect.
Power Down. When set, CRC module is put in power-down mode
0
CRC is not in power-down mode.
1
CRC is in power-down mode.
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14.4.3 CRC Global Control Register 2 (CRC_CTRL2)
Figure 14-11. CRC Global Control Register 2 (CRC_CTRL2) [offset = 10h]
31
16
Reserved
R-0
15
10
7
CH2_MODE
R-0
R/WP-0
4
3
2
CH1_TRACEEN
R-0
8
Reserved
5
Reserved
9
Reserved
R/WP-0
R-0
1
0
CH1_MODE
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 14-7. CRC Global Control Register 2 (CRC_CTRL2) Field Descriptions
Bit
31-10
9-8
7-5
4
Field
Reserved
Value
0
CH2_MODE
Reserved
Reserved
1-0
CH1_MODE
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Reads return 0. Writes have no effect.
Channel 2 Mode Selection
0
Data Capture mode. In this mode, the PSA Signature Register does not compress data when it
is written. Any data written to PSA Signature Register is simply captured by PSA Signature
Register without any compression. This mode can be used to plant seed value into the PSA
register.
1h
AUTO Mode
2h
Semi-CPU Mode
3h
Full-CPU Mode
0
Reads return 0. Writes have no effect.
CH1_TRACEEN
3-2
Description
Channel 1 Data Trace Enable. When set, the channel is put into data trace mode. The channel
snoops on the CPU Peripheral Bus Master, Flash, System RAM buses for any read transaction.
Any read data on these buses is compressed by the PSA Signature Register. When suspend is
on, the PSA Signature Register does not compress any read data on these buses. When trace
enable bit is set, the CH1_MODE bit is automatically reset to 0 (Data Capture mode).
0
Data Trace is disabled.
1
Data Trace is enabled.
0
Reads return 0. Writes have no effect.
Channel 1 Mode Selection
0
Data Capture mode. In this mode, the PSA Signature Register does not compress data when it
is written. Any data written to PSA Signature Register is simply captured by PSA Signature
Register without any compression. This mode can be used to plant seed value into the PSA
register.
1h
AUTO mode
2h
Semi-CPU mode
3h
Full-CPU mode
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14.4.4 CRC Interrupt Enable Set Register (CRC_INTS)
Figure 14-12. CRC Interrupt Enable Set Register (CRC_INTS) [offset = 18h]
31
16
Reserved
R-0
15
13
12
11
10
9
8
Reserved
CH2_
TIMEOUTENS
CH2_
UNDERENS
CH2_
OVERENS
CH2_
CRCFAILENS
CH2_
CCITENS
R-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
7
4
3
2
1
0
Reserved
5
CH1_
TIMEOUTENS
CH1_
UNDERENS
CH1_
OVERENS
CH1_
CRCFAILENS
CH1_
CCITENS
R-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 14-8. CRC Interrupt Enable Set Register (CRC_INTS) Field Descriptions
Bit
31-13
12
Field
Reserved
Value
0
CH2_TIMEOUTENS
Description
Reads return 0. Writes have no effect.
Channel 2 Timeout Interrupt Enable Bit.
User and Privileged mode (read):
0
Timeout Interrupt is disabled.
1
Timeout Interrupt is enabled.
Privileged mode (write):
11
0
Has no effect.
1
Timeout Interrupt is enabled.
CH2_UNDERENS
Channel 2 Underrun Interrupt Enable Bit.
User and Privileged mode (read):
0
Underrun Interrupt is disabled.
1
Underrun Interrupt is enabled.
Privileged mode (write):
10
0
Has no effect.
1
Underrun Interrupt is enabled.
CH2_OVERENS
Channel 2 Overrun Interrupt Enable Bit.
User and Privileged mode (read):
0
Overrun Interrupt is disabled.
1
Overrun Interrupt is enabled.
Privileged mode (write):
9
0
Has no effect.
1
Overrun Interrupt is enabled.
CH2_CRCFAILENS
Channel 2 CRC Fail Interrupt Enable Bit.
User and Privileged mode (read):
0
CRC Fail Interrupt is disabled.
1
CRC Fail Interrupt is enabled.
Privileged mode (write):
496
0
Has no effect.
1
CRC Fail Interrupt is enabled.
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Table 14-8. CRC Interrupt Enable Set Register (CRC_INTS) Field Descriptions (continued)
Bit
8
Field
Value
CH2_CCITENS
Description
Channel 2 Compression Complete Interrupt Enable Bit.
User and Privileged mode (read):
0
Compression Complete Interrupt is disabled.
1
Compression Complete Interrupt is enabled.
Privileged mode (write):
7-5
4
Reserved
0
Has no effect.
1
Compression Complete Interrupt is enabled.
0
Reads return 0. Writes have no effect.
CH1_TIMEOUTENS
Channel 1 Timeout Interrupt Enable Bit.
User and Privileged mode (read):
0
Timeout Interrupt is disabled.
1
Timeout Interrupt is enabled.
Privileged mode (write):
3
0
Has no effect.
1
Timeout Interrupt is enabled.
CH1_UNDERENS
Channel 1 Underrun Interrupt Enable Bit.
User and Privileged mode (read):
0
Underrun Interrupt is disabled.
1
Underrun Interrupt is enabled.
Privileged mode (write):
2
0
Has no effect.
1
Underrun Interrupt is enabled.
CH1_OVERENS
Channel 1 Overrun Interrupt Enable Bit.
User and Privileged mode (read):
0
Overrun Interrupt is disabled.
1
Overrun Interrupt is enabled.
Privileged mode (write):
1
0
Has no effect.
1
Overrun Interrupt is enabled.
CH1_CRCFAILENS
Channel 1 CRC Fail Interrupt Enable Bit.
User and Privileged mode (read):
0
CRC Fail Interrupt is disabled.
1
CRC Fail Interrupt is enabled.
Privileged mode (write):
0
0
Has no effect.
1
CRC Fail Interrupt is enabled.
CH1_CCITENS
Channel 1 Compression Complete Interrupt Enable Bit.
User and Privileged mode (read):
0
Compression Complete Interrupt is disabled.
1
Compression Complete Interrupt is enabled.
Privileged mode (write):
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0
Has no effect.
1
Compression Complete Interrupt is enabled.
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14.4.5 CRC Interrupt Enable Reset Register (CRC_INTR)
Figure 14-13. CRC Interrupt Enable Reset Register (CRC_INTR) [offset = 20h]
31
16
Reserved
R-0
15
13
12
11
10
9
8
Reserved
CH2_
TIMEOUTENR
CH2_
UNDERENR
CH2_
OVERENR
CH2_
CRCFAILENR
CH2_
CCITENR
R-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
7
4
3
2
1
0
Reserved
5
CH1_
TIMEOUTENR
CH1_
UNDERENR
CH1_
OVERENR
CH1_
CRCFAILENR
CH1_
CCITENR
R-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 14-9. CRC Interrupt Enable Reset Register (CRC_INTR) Field Descriptions
Bit
31-13
12
Field
Reserved
Value
0
CH2_TIMEOUTENR
Description
Reads return 0. Writes have no effect.
Channel 2 Timeout Interrupt Enable Reset Bit.
User and Privileged mode (read):
0
Timeout Interrupt is disabled.
1
Timeout Interrupt is enabled.
Privileged mode (write):
11
0
Has no effect.
1
Timeout Interrupt is disabled.
CH2_UNDERENR
Channel 2 Underrun Interrupt Enable Reset Bit.
User and Privileged mode (read):
0
Underrun Interrupt is disabled.
1
Underrun Interrupt is enabled.
Privileged mode (write):
10
0
Has no effect.
1
Underrun Interrupt is disabled.
CH2_OVERENR
Channel 2 Overrun Interrupt Enable Reset Bit.
User and Privileged mode (read):
0
Overrun Interrupt is disabled
1
Overrun Interrupt is enabled
Privileged mode (write):
9
0
Has no effect
1
Overrun Interrupt disable
CH2_CRCFAILENR
Channel 2 CRC Fail Interrupt Enable Reset Bit.
User and Privileged mode (read):
0
CRC Fail Interrupt is disabled.
1
CRC Fail Interrupt is enabled.
Privileged mode (write):
498
0
Has no effect.
1
CRC Fail Interrupt is disabled.
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Table 14-9. CRC Interrupt Enable Reset Register (CRC_INTR) Field Descriptions (continued)
Bit
8
Field
Value
CH2_CCITENR
Description
Channel 2 Compression Complete Interrupt Enable Reset Bit.
User and Privileged mode (read):
0
Compression Complete Interrupt is disabled.
1
Compression Complete Interrupt is enabled.
Privileged mode (write):
7-5
4
Reserved
0
Has no effect.
1
Compression Complete Interrupt is disabled.
0
Reads return 0. Writes have no effect.
CH1_TIMEOUTENR
Channel 1 Timeout Interrupt Enable Reset Bit.
User and Privileged mode (read):
0
Timeout Interrupt is disabled.
1
Timeout Interrupt is enabled.
Privileged mode (write):
3
0
Has no effect.
1
Timeout Interrupt is disabled.
CH1_UNDERENR
Channel 1 Underrun Interrupt Enable Reset Bit.
User and Privileged mode (read):
0
Underrun Interrupt is disabled.
1
Underrun Interrupt is enabled.
Privileged mode (write):
2
0
Has no effect.
1
Underrun Interrupt is disabled.
CH1_OVERENR
Channel 1 Overrun Interrupt Enable Reset Bit.
User and Privileged mode (read):
0
Overrun Interrupt is disabled.
1
Overrun Interrupt is enabled.
Privileged mode (write):
1
0
Has no effect.
1
Overrun Interrupt is disabled.
CH1_CRCFAILENR
Channel 1 CRC Fail Interrupt Enable Reset Bit.
User and Privileged mode (read):
0
CRC Fail Interrupt is disabled.
1
CRC Fail Interrupt is enabled.
Privileged mode (write):
0
0
Has no effect.
1
CRC Fail Interrupt is disabled.
CH1_CCITENR
Channel 1 Compression Complete Interrupt Enable Reset Bit.
User and Privileged mode (read):
0
Compression Complete Interrupt is disabled.
1
Compression Complete Interrupt is enabled.
Privileged mode (write):
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0
Has no effect.
1
Compression Complete Interrupt is disabled.
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14.4.6 CRC Interrupt Status Register (CRC_STATUS)
Figure 14-14. CRC Interrupt Status Register (CRC_STATUS) [offset = 28h]
31
16
Reserved
R-0
15
13
12
11
10
9
8
Reserved
CH2_TIMEOUT
CH2_UNDER
CH2_OVER
CH2_CRCFAIL
CH2_CCIT
R-0
R/W1CP-0
R/W1CP-0
R/W1CP-0
R/W1CP-0
R/W1CP-0
7
4
3
2
1
0
Reserved
5
CH1_TIMEOUT
CH1_UNDER
CH1_OVER
CH1_CRCFAIL
CH1_CCIT
R-0
R/W1CP-0
R/W1CP-0
R/W1CP-0
R/W1CP-0
R/W1CP-0
LEGEND: R/W = Read/Write; R = Read only; W1CP = Write 1 to clear in privilege mode only; -n = value after reset
Table 14-10. CRC Interrupt Status Register (CRC_STATUS) Field Descriptions
Bit
31-13
12
Field
Reserved
Value
0
CH2_TIMEOUT
Description
Reads return 0. Writes have no effect.
Channel 2 CRC Timeout Interrupt Status Flag. This bit is set in both AUTO and Semi-CPU
mode.
User and Privileged mode (read):
0
No timeout interrupt is active.
1
Timeout interrupt is active.
Privileged mode (write):
11
0
Has no effect.
1
Bit is cleared.
CH2_UNDER
Channel 2 CRC Underrun Interrupt Status Flag. This bit is set in AUTO mode only.
User and Privileged mode (read):
0
No Underrun Interrupt is active.
1
Underrun Interrupt is active.
Privileged mode (write):
10
0
Has no effect.
1
Bit is cleared.
CH2_OVER
Channel 2 CRC Overrun Interrupt Status Flag. This bit is set in either AUTO or Semi-CPU
mode.
User and Privileged mode (read):
0
No Overrun Interrupt is active.
1
Overrun Interrupt is active.
Privileged mode (write):
9
0
Has no effect.
1
Bit is cleared.
CH2_CRCFAIL
Channel 2 CRC Compare Fail Interrupt Status Flag. This bit is set in AUTO mode only.
User and Privileged mode (read):
0
No CRC Fail Interrupt is active.
1
CRC Fail Interrupt is active.
Privileged mode (write):
500
0
Has no effect.
1
Bit is cleared.
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Table 14-10. CRC Interrupt Status Register (CRC_STATUS) Field Descriptions (continued)
Bit
8
Field
Value
CH2_CCIT
Description
Channel 2 CRC Pattern Compression Complete Interrupt Status Flag. This bit is only set in
Semi-CPU mode.
User and Privileged mode (read):
0
No Compression Complete Interrupt is active.
1
Compression Complete Interrupt is active.
Privileged mode (write):
7-5
4
Reserved
0
Has no effect.
1
Bit is cleared.
0
Reads return 0. Writes have no effect.
CH1_TIMEOUT
Channel 1 CRC Timeout Interrupt Status Flag.
User and Privileged mode (read):
0
No timeout interrupt is active.
1
Timeout interrupt is active.
Privileged mode (write):
3
0
Has no effect.
1
Bit is cleared.
CH1_UNDER
Channel 1 Underrun Interrupt Status Flag.
User and Privileged mode (read):
0
No Underrun Interrupt is active.
1
Underrun Interrupt is active.
Privileged mode (write):
2
0
Has no effect.
1
Bit is cleared.
CH1_OVER
Channel 1 Overrun Interrupt Status Flag.
User and Privileged mode (read):
0
No Overrun Interrupt is active.
1
Overrun Interrupt is active.
Privileged mode (write):
1
0
Has no effect.
1
Bit is cleared.
CH1_CRCFAIL
Channel 1 CRC Compare Fail Interrupt Status Flag.
User and Privileged mode (read):
0
No CRC Fail Interrupt is active.
1
CRC Fail Interrupt is active.
Privileged mode (write):
0
0
Has no effect.
1
Bit is cleared.
CH1_CCIT
Channel 1 CRC Pattern Compression Complete Interrupt Status Flag.
User and Privileged mode (read):
0
No Compression Complete Interrupt is active.
1
Compression Complete Interrupt is active.
Privileged mode (write):
0
Has no effect.
1
Bit is cleared.
14.4.7 CRC Interrupt Offset (CRC_INT_OFFSET_REG)
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Figure 14-15. CRC Interrupt Offset (CRC_INT_OFFSET_REG) [offset = 30h]
31
16
Reserved
R-0
15
8
7
0
Reserved
OFSTREG
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-11. CRC Interrupt Offset (CRC_INT_OFFSET_REG) Field Descriptions
Bit
Field
31-8
Reserved
7-0
OFSTREG
Value
0
Reads return 0. Writes have no effect.
CRC Interrupt Offset. This register indicates the highest priority pending interrupt vector address.
Reading the offset register automatically clears the respective interrupt flag.
0
Phantom
1h
Ch1 CRC Fail
2h
Ch2 CRC Fail
3h-8h
Reserved
9h
Ch1 Compression Complete
Ah
Ch2 Compression Complete
Bh-10h
Reserved
11h
Ch1 Overrun
12h
Ch2 Overrun
13h-18h
Reserved
19h
Ch1 Underrun
1Ah
Ch2 Underrun
1Bh-20h
Reserved
21h
Ch1 Timeout
22h
Ch2 Timeout
23h-FFh
502
Description
Reserved
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14.4.8 CRC Busy Register (CRC_BUSY)
Figure 14-16. CRC Busy Register (CRC_BUSY) [offset = 38h]
31
16
Reserved
R-0
15
9
8
7
1
0
Reserved
CH2_BUSY
Reserved
CH1_BUSY
R-0
R-0
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-12. CRC Busy Register (CRC_BUSY) Field Descriptions
Bit
31-9
8
7-1
0
Field
Value
Reserved
0
CH2_BUSY
Reserved
CH1_BUSY
Description
Reads return 0. Writes have no effect.
CH2_BUSY. During AUTO or Semi-CPU mode, the busy flag is set when the first data pattern of
the block is compressed and remains set until the last data pattern of the block is compressed. The
flag is cleared when the last data pattern of the block is compressed.
0
Reads return 0. Writes have no effect.
CH1_BUSY. During AUTO or Semi-CPU mode, the busy flag is set when the first data pattern of
the block is compressed and remains set until the last data pattern of the block is compressed. The
flag is cleared when the last data pattern of the block is compressed.
14.4.9 CRC Pattern Counter Preload Register 1 (CRC_PCOUNT_REG1)
Figure 14-17. CRC Pattern Counter Preload Register 1 (CRC_PCOUNT_REG1) [offset = 40h]
31
20
19
16
Reserved
CRC_PAT_COUNT1
R-0
R/W-0
15
0
CRC_PAT_COUNT1
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-13. CRC Pattern Counter Preload Register 1 (CRC_PCOUNT_REG1) Field Descriptions
Bit
Field
31-20
Reserved
19-0
CRC_PAT_COUNT1
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Value
0
Description
Reads return 0. Writes have no effect.
Channel 1 Pattern Counter Preload Register. This register contains the number of data
patterns in one sector to be compressed before a CRC is performed.
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14.4.10 CRC Sector Counter Preload Register 1 (CRC_SCOUNT_REG1)
Figure 14-18. CRC Sector Counter Preload Register 1 (CRC_SCOUNT_REG1) [offset = 44h]
31
16
Reserved
R-0
15
0
CRC_SEC_COUNT1
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-14. CRC Sector Counter Preload Register 1 (CRC_SCOUNT_REG1) Field Descriptions
Bit
Field
Value
31-16
Reserved
15-0
CRC_SEC_COUNT1
0
Description
Reads return 0. Writes have no effect.
Channel 1 Sector Counter Preload Register. This register contains the number of sectors
in one block of memory.
14.4.11 CRC Current Sector Register 1 (CRC_CURSEC_REG1)
Figure 14-19. CRC Current Sector Preload Register 1 (CRC_CURSEC_REG1) [offset = 48h]
31
16
Reserved
R-0
15
0
CRC_CURSEC1
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-15. CRC Current Sector Register 1 (CRC_CURSEC_REG1) Field Descriptions
Bit
Field
31-16
Reserved
15-0
CRC_CURSEC1
504
Value
0
Description
Reads return 0. Writes have no effect.
Channel 1 Current Sector ID Register. In AUTO mode, this register contains the current
sector number of which the signature verification fails. The sector counter is a free running up
counter. When a sector fails, the erroneous sector number is logged into current sector ID
register and the CRC fail interrupt is generated The sector ID register is frozen until it is read
and the CRC fail status bit is cleared by CPU. While it is frozen, it does not capture another
erroneous sector number. When this condition happens, an overrun interrupt is generated
instead. Once the register is read and the CRC fail interrupt flag is cleared it can capture new
erroneous sector number. In Semi-CPU mode, this register is used to indicate the sector
number for which the compression complete has last happened.
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14.4.12 CRC Channel 1 Watchdog Timeout Preload Register A (CRC_WDTOPLD1)
Figure 14-20. CRC Channel 1 Watchdog Timeout Preload Register A (CRC_WDTOPLD1)
[offset = 4Ch]
31
24
23
16
Reserved
CRC_WDTOPLD1
R-0
R/W-0
15
0
CRC_WDTOPLD1
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-16. CRC Channel 1 Watchdog Timeout Preload Register A (CRC_WDTOPLD1)
Field Descriptions
Bit
Field
31-24
Reserved
23-0
CRC_WDTOPLD1
Value
0
Description
Reads return 0. Writes have no effect.
Channel 1 Watchdog Timeout Counter Preload Register. This register contains the number
of clock cycles within which the DMA must transfer the next block of data patterns. In SemiCPU mode, this register is used to indicate the sector number for which the compression
complete has last happened.
14.4.13 CRC Channel 1 Block Complete Timeout Preload Register B (CRC_BCTOPLD1)
Figure 14-21. CRC Channel 1 Block Complete Timeout Preload Register B (CRC_BCTOPLD1)
[offset = 50h]
31
24
23
16
Reserved
CRC_BCTOPLD1
R-0
R/W-0
15
0
CRC_BCTOPLD1
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-17. CRC Channel 1 Block Complete Timeout Preload Register B (CRC_BCTOPLD1)
Field Descriptions
Bit
Field
31-24
Reserved
23-0
CRC_BCTOPLD1
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Value
0
Description
Reads return 0. Writes have no effect.
Channel 1 Block Complete Timeout Counter Preload Register. This register contains the
number of clock cycles within which the CRC for an entire block needs to complete before a
timeout interrupt is generated.
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14.4.14 Channel 1 PSA Signature Low Register (PSA_SIGREGL1)
Figure 14-22. Channel 1 PSA Signature Low Register (PSA_SIGREGL1) [offset = 60h]
31
0
PSASIG1
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-18. Channel 1 PSA Signature Low Register (PSA_SIGREGL1) Field Descriptions
Bit
31-0
Field
Description
PSASIG1
Channel 1 PSA Signature Low Register. This register contains the value stored at PSASIG1[31:0]
register.
14.4.15 Channel 1 PSA Signature High Register (PSA_SIGREGH1)
Figure 14-23. Channel 1 PSA Signature High Register (PSA_SIGREGH1) [offset = 64h]
31
0
PSASIG1
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-19. Channel 1 PSA Signature High Register (PSA_SIGREGH1) Field Descriptions
Bit
31-0
Field
Description
PSASIG1
Channel 1 PSA Signature High Register. This register contains the value stored at PSASIG1[63:32]
register.
14.4.16 Channel 1 CRC Value Low Register (CRC_REGL1)
Figure 14-24. Channel 1 CRC Value Low Register (CRC_REGL1) [offset = 68h]
31
0
CRC1
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-20. Channel 1 CRC Value Low Register (CRC_REGL1) Field Descriptions
Bit
Field
Description
31-0
CRC1
Channel 1 CRC Value Low Register. This register contains the current known good signature value
stored at CRC1[31:0] register.
506
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14.4.17 Channel 1 CRC Value High Register (CRC_REGH1)
Figure 14-25. Channel 1 CRC Value High Register (CRC_REGH1) [offset = 6Ch]
31
0
CRC1
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-21. Channel 1 CRC Value High Register (CRC_REGH1) Field Descriptions
Bit
Field
Description
31-0
CRC1
Channel 1 CRC Value High Register. This register contains the current known good signature value
stored at CRC1[63:32] register.
14.4.18 Channel 1 PSA Sector Signature Low Register (PSA_SECSIGREGL1)
Figure 14-26. Channel 1 PSA Sector Signature Low Register (PSA_SECSIGREGL1) [offset = 70h]
31
0
PSASECSIG1
R-0
LEGEND: R = Read only; -n = value after reset
Table 14-22. Channel 1 PSA Sector Signature Low Register (PSA_SECSIGREGL1)
Field Descriptions
Bit
31-0
Field
Description
PSASECSIG1
Channel 1 PSA Sector Signature Low Register. This register contains the value stored at
PSASECSIG1[31:0] register.
14.4.19 Channel 1 PSA Sector Signature High Register (PSA_SECSIGREGH1)
Figure 14-27. Channel 1 PSA Sector Signature High Register (PSA_SECSIGREGH1) [offset = 74h]
31
0
PSASECSIG1
R-0
LEGEND: R = Read only; -n = value after reset
Table 14-23. Channel 1 PSA Sector Signature High Register (PSA_SECSIGREGH1)
Field Descriptions
Bit
31-0
Field
Description
PSASECSIG1
Channel 1 PSA Sector Signature High Register. This register contains the value stored at
PSASECSIG1[63:32] register.
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14.4.20 Channel 1 Raw Data Low Register (RAW_DATAREGL1)
Figure 14-28. Channel 1 Raw Data Low Register (RAW_DATAREGL1) [offset = 78h]
31
0
RAW_DATA1
R-0
LEGEND: R = Read only; -n = value after reset
Table 14-24. Channel 1 Raw Data Low Register (RAW_DATAREGL1) Field Descriptions
Bit
31-0
Field
Description
RAW_DATA1
Channel 1 Raw Data Low Register. This register contains bits 31:0 of the uncompressed raw data.
14.4.21 Channel 1 Raw Data High Register (RAW_DATAREGH1)
Figure 14-29. Channel 1 Raw Data High Register (RAW_DATAREGH1) [offset = 7Ch]
31
0
RAW_DATA1
R-0
LEGEND: R = Read only; -n = value after reset
Table 14-25. Channel 1 Raw Data High Register (RAW_DATAREGH1) Field Descriptions
Bit
31-0
Field
Description
RAW_DATA1
Channel 1 Raw Data High Register. This register contains bits 63:32 of the uncompressed raw data.
14.4.22 CRC Pattern Counter Preload Register 2 (CRC_PCOUNT_REG2)
Figure 14-30. CRC Pattern Counter Preload Register 2 (CRC_PCOUNT_REG2) [offset = 80h]
31
18
19
16
Reserved
CRC_PAT_COUNT2
R-0
R/W-0
15
0
CRC_PAT_COUNT2
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-26. CRC Pattern Counter Preload Register 2 (CRC_PCOUNT_REG2) Field Descriptions
Bit
Field
31-20
Reserved
19-0
CRC_PAT_COUNT2
508
Value
0
Description
Reads return 0. Writes have no effect.
Channel 2 Pattern Counter Preload Register. This register contains the number of data
patterns in one sector to be compressed before a CRC is performed.
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14.4.23 CRC Sector Counter Preload Register 2 (CRC_SCOUNT_REG2)
Figure 14-31. CRC Sector Counter Preload Register 2 (CRC_SCOUNT_REG2) [offset = 84h]
31
16
Reserved
R-0
15
0
CRC_SEC_COUNT2
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-27. CRC Sector Counter Preload Register 2 (CRC_SCOUNT_REG2) Field Descriptions
Bit
Field
Value
31-16
Reserved
15-0
CRC_SEC_COUNT2
0
Description
Reads return 0. Writes have no effect.
Channel 2 Sector Counter Preload Register. This register contains the number of sectors
in one block of memory.
14.4.24 CRC Current Sector Register 2 (CRC_CURSEC_REG2)
Figure 14-32. CRC Current Sector Register 2 (CRC_CURSEC_REG2) [offset = 88h]
31
16
Reserved
R-0
15
0
CRC_CURSEC2
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-28. CRC Current Sector Register 2 (CRC_CURSEC_REG2) Field Descriptions
Bit
Field
31-16
Reserved
15-0
CRC_CURSEC2
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Value
0
Description
Reads return 0. Writes have no effect.
Channel 2 Current Sector ID Register. In AUTO mode, this register contains the current
sector number of which the signature verification fails. The sector counter is a free running
up counter. When a sector fails, the erroneous sector number is logged into current sector
ID register and the CRC fail interrupt is generated The sector ID register is frozen until it is
read and the CRC fail status bit is cleared by CPU. While it is frozen, it does not capture
another erroneous sector number. When this condition happens, an overrun interrupt is
generated instead. Once the register is read and the CRC fail interrupt flag is cleared it can
capture new erroneous sector number. In Semi-CPU mode, this register is used to indicate
the sector number for which the compression complete has last happened.
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14.4.25 CRC Channel 2 Watchdog Timeout Preload Register A (CRC_WDTOPLD2)
Figure 14-33. CRC Channel 2 Watchdog Timeout Preload Register A (CRC_WDTOPLD2)
[offset = 8Ch]
31
24
23
16
Reserved
CRC_WDTOPLD2
R-0
R/W-0
15
0
CRC_WDTOPLD2
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-29. CRC Channel 2 Watchdog Timeout Preload Register A (CRC_WDTOPLD2)
Field Descriptions
Bit
Field
31-24
Reserved
23-0
CRC_WDTOPLD2
Value
0
Description
Reads return 0. Writes have no effect.
Channel 2 Watchdog Timeout Counter Preload Register. This register contains the number
of clock cycles within which the DMA must transfer the next block of data patterns. In SemiCPU mode, this register is used to indicate the sector number for which the compression
complete has last happened.
14.4.26 CRC Channel 2 Block Complete Timeout Preload Register B (CRC_BCTOPLD2)
Figure 14-34. CRC Channel 2 Block Complete Timeout Preload Register B (CRC_BCTOPLD2)
[offset = 90h]
31
24
23
16
Reserved
CRC_BCTOPLD2
R-0
R/W-0
15
0
CRC_BCTOPLD2
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-30. CRC Channel 2 Block Complete Timeout Preload Register B (CRC_BCTOPLD2)
Field Descriptions
Bit
Field
31-24
Reserved
23-0
CRC_BCTOPLD2
510
Value
0
Description
Reads return 0. Writes have no effect.
Channel 2 Block Complete Timeout Counter Preload Register. This register contains the
number of clock cycles within which the CRC for an entire block needs to complete before a
timeout interrupt is generated.
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14.4.27 Channel 2 PSA Signature Low Register (PSA_SIGREGL2)
Figure 14-35. Channel 2 PSA Signature Low Register (PSA_SIGREGL2) [offset = A0h]
31
0
PSASIG2
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-31. Channel 2 PSA Signature Low Register (PSA_SIGREGL2) Field Descriptions
Bit
31-0
Field
Description
PSASIG2
Channel 2 PSA Signature Low Register. This register contains the value stored at PSASIG2[31:0]
register.
14.4.28 Channel 2 PSA Signature High Register (PSA_SIGREGH2)
Figure 14-36. Channel 2 PSA Signature High Register (PSA_SIGREGH2) [offset = A4h]
31
0
PSASIG2
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-32. Channel 2 PSA Signature High Register (PSA_SIGREGH2) Field Descriptions
Bit
31-0
Field
Description
PSASIG2
Channel 2 PSA Signature High Register. This register contains the value stored at PSASIG2[63:32]
register.
14.4.29 Channel 2 CRC Value Low Register (CRC_REGL2)
Figure 14-37. Channel 2 CRC Value Low Register (CRC_REGL2) [offset = A8h]
31
0
CRC2
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-33. Channel 2 CRC Value Low Register (CRC_REGL2) Field Descriptions
Bit
Field
Description
31-0
CRC2
Channel 2 CRC Value Low Register. This register contains the current known good signature value
stored at CRC2[31:0] register.
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14.4.30 Channel 2 CRC Value High Register (CRC_REGH2)
Figure 14-38. Channel 2 CRC Value High Register (CRC_REGH2) [offset = ACh]
31
0
CRC2
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-34. Channel 2 CRC Value High Register (CRC_REGH2) Field Descriptions
Bit
Field
Description
31-0
CRC2
Channel 2 CRC Value High Register. This register contains the current known good signature value
stored at CRC2[63:32] register.
14.4.31 Channel 2 PSA Sector Signature Low Register (PSA_SECSIGREGL2)
Figure 14-39. Channel 2 PSA Sector Signature Low Register (PSA_SECSIGREGL2) [offset = B0h]
31
0
PSASECSIG2
R-0
LEGEND: R = Read only; -n = value after reset
Table 14-35. Channel 2 PSA Sector Signature Low Register (PSA_SECSIGREGL2)
Field Descriptions
Bit
31-0
Field
Description
PSASECSIG2
Channel 2 PSA Sector Signature Low Register. This register contains the value stored at
PSASECSIG2[31:0] register.
14.4.32 Channel 2 PSA Sector Signature High Register (PSA_SECSIGREGH2)
Figure 14-40. Channel 2 PSA Sector Signature High Register (PSA_SECSIGREGH2) [offset = B4h]
31
0
PSASECSIG2
R-0
LEGEND: R = Read only; -n = value after reset
Table 14-36. Channel 2 PSA Sector Signature High Register (PSA_SECSIGREGH2)
Field Descriptions
Bit
31-0
512
Field
Description
PSASECSIG2
Channel 2 PSA Sector Signature High Register. This register contains the value stored at
PSASECSIG2[63:32] register.
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14.4.33 Channel 2 Raw Data Low Register (RAW_DATAREGL2)
Figure 14-41. Channel 2 Raw Data Low Register (RAW_DATAREGL2) [offset = B8h]
31
0
RAW_DATA2
R-0
LEGEND: R = Read only; -n = value after reset
Table 14-37. Channel 2 Raw Data Low Register (RAW_DATAREGL2) Field Descriptions
Bit
31-0
Field
Description
RAW_DATA2
Channel 2 Raw Data Low Register. This register contains bits 31:0 of the uncompressed raw data..
14.4.34 Channel 2 Raw Data High Register (RAW_DATAREGH2)
Figure 14-42. Channel 2 Raw Data High Register (RAW_DATAREGH2) [offset = BCh]
31
0
RAW_DATA2
R-0
LEGEND: R = Read only; -n = value after reset
Table 14-38. Channel 2 Raw Data High Register (RAW_DATAREGH2) Field Descriptions
Bit
31-0
Field
Description
RAW_DATA2
Channel 2 Raw Data High Register. This register contains bits 63:32 of the uncompressed raw data..
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14.4.35 Data Bus Selection Register (CRC_TRACE_BUS_SEL)
Figure 14-43. Data Bus Selection Register (CRC_TRACE_BUS_SEL) [offset = 140h]
31
16
Reserved
R-0
15
3
Reserved
R-0
2
1
0
MEn
DTCMEn
ITCMEn
R/W-1
R/W-1
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-39. Data Bus Selection Register Field Descriptions
Bit
31-3
2
1
0
514
Field
Reserved
Value
0
MEn
Description
Reads return 0. Writes have no effect.
Enable/disables the tracing of Peripheral Bus Master
0
Tracing of Peripheral Bus Master has been disabled.
1
Tracing of Peripheral Bus Master has been enabled.
DTCMEn
Enable/disables the tracing of data TCM
0
Tracing of System Odd and Even RAM buses have been disabled.
1
Tracing of System Odd and Even RAM buses have been enabled.
ITCMEn
Enable/disables the tracing of instruction TCM
0
Tracing of Flash data bus has been disabled.
1
Tracing of Flash data bus has been enabled.
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Chapter 15
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Vectored Interrupt Manager (VIM) Module
This chapter describes the behavior of the vectored interrupt manager (VIM) module of the device family.
Topic
15.1
15.2
15.3
15.4
15.5
15.6
15.7
15.8
...........................................................................................................................
Overview .........................................................................................................
Device Level Interrupt Management ....................................................................
Interrupt Handling Inside VIM .............................................................................
Interrupt Vector Table (VIM RAM) .......................................................................
VIM Wakeup Interrupt ........................................................................................
Capture Event Sources .....................................................................................
Examples.........................................................................................................
VIM Control Registers .......................................................................................
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516
519
523
526
527
527
530
515
Overview
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15.1 Overview
The vectored interrupt manager (VIM) provides hardware assistance for prioritizing and controlling the
many interrupt sources present on a device. Interrupts are caused by events outside of the normal flow of
program execution. Normally, these events require a timely response from the central processing unit
(CPU); therefore, when an interrupt occurs, the CPU switches execution from the normal program flow to
an interrupt service routine (ISR).
The VIM module has the following features:
• Supports 95 interrupt channels, in both register vectored interrupt and hardware vectored interrupt
mode.
– Provides IRQ vector directly to the CPU VIC port
– Provides FIQ/IRQ vector through registers
– Provides programmable priority and enable for interrupt request lines
• Provides a direct hardware dispatch mechanism for fastest IRQ dispatch.
• Provides two software dispatch mechanisms for backward compatibility with earlier generation of TI
processors.
– Index interrupt
– Register vectored interrupt
• Parity protected vector interrupt table against soft errors.
15.2 Device Level Interrupt Management
A block diagram of device level interrupt handling is shown in Figure 15-1. When an event occurs within a
peripheral, the peripheral makes an interrupt request to the VIM. Then, VIM prioritizes the requests from
peripherals and provides the address of the highest interrupt service routine (ISR) to the CPU. Finally,
CPU starts executing the ISR instructions from that address in the ISR. Section 15.2.1 through
Section 15.2.3 provide additional details about these three steps.
Figure 15-1. Device Level Interrupt Block Diagram
Peripherals - Generate Interrupt Requests
ESM
ADC
LIN
SPI
DCAN
INT_REQ0 INT_REQ1
INT_REQ94
VIM
CPU Interrupts
Special Interrupts
NHET
- Interrupt Enable
- Interrupt Priority
- Interrupt Mapping
- Interrupt Generation
INT
IRQ
FIQ
IRQ
FIQ
FIQ
IRQ
IRQ
Table
Index
Index Vector
Vector
Request
Request
t
Vector
Configuration Register RegisterRegister Register
(Direct
CAPEVT[1:0] Wakeup_INT
Hardware
VBUSP
RTI
516
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15.2.1 Interrupt Generation at the Peripheral
Interrupt generation begins when an event occurs within a peripheral module. Some examples of interruptcapable events are expiration of a counter within a timer module, receipt of a character in a
communications module, and completion of a conversion in an analog-to-digital converter (ADC) module.
Some device peripherals are capable of requesting interrupts on more than one interrupt request line.
Interrupts are not always generated when an event occurs; the peripheral must make an interrupt request
to the VIM based on the event occurrence. Typically, the peripheral contains:
• An interrupt flag bit for each event to signify the event occurrence.
• An interrupt enable bit to control whether the event occurrence causes an interrupt request to the VIM.
15.2.2 Interrupt Handling at the CPU
The ARM CPU provides two vectors for interrupt requests—fast interrupt requests (FIQs) and normal
interrupt requests (IRQs). FIQs are higher priority than IRQs, and FIQ interrupts may interrupt IRQ
interrupts.
NOTE: The FIQ implemented in Cortex-R4F is Non-Maskable Fast Interrupts (NMFI). Once FIQ is
enabled (by clearing F bit in CPSR), it can NOT be disabled by setting F bit in CPSR. Only a
reset or an FIQ will be able to set the F bit in CPSR. By hardware, Non Maskable FIQ are
not reentrant.
After reset (power reset or warm reset), both FIQ and IRQ are disabled. The CPU may enable these
interrupt request channels individually within the CPSR (Current Program Status Register); CPSR bits 6
and 7 must be cleared to enable the FIQ (bit 6) and IRQ (bit 7) interrupt requests at the CPU. CPSR is
writable in privilege mode only. Example 15-2 shows how to enable the IRQ and FIQ through CPSR.
When the CPU receives an interrupt request, the CPSR mode field changes to either FIQ or IRQ mode.
When an IRQ interrupt is received, the CPU disables other IRQ interrupts by setting CPSR bit 7. When an
FIQ interrupt is received, the CPU disables both IRQ and FIQ interrupts by setting CPSR bits 6 and 7.
A write of 1 to CPSR bit 7 disables the IRQ from CPU. However, a write of 1 to CPSR bit 6 leaves it
unchanged. Example 15-2 also shows how to disable the IRQ through CPSR.
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15.2.3 Software Interrupt Handling Options
The device supports three different possibilities for software to handle interrupts
1. Index interrupts mode (compatible with TMS470R1x legacy code)
After the interrupt is received by the CPU, the CPU branches to 0x18 (IRQ) or 0x1C (FIQ) to execute
the main ISR. The main ISR routine reads the offset register (IRQINDEX, FIQINDEX) to determine the
source of the interrupt.
This mode is compatible with the TMS470R1x (CIM) module and provides the same interrupt registers.
This mode could be used if legacy code needs to be reused, porting it from the TMS470R1x family.
However, imported software will not benefit from the VIM improvements.
To port legacy software, the interrupt vector at 0x18 (IRQ) or 0x1C (FIQ) only needs to be a branch
statement to a software interrupt table. The software interrupt table reads the pending interrupt from a
vector offset register (FIQINDEX[7:0] for FIQ interrupts and IRQINDEX[7:0] for IRQ interrupts). All
pending interrupts can be viewed in the INTREQ register. Example 15-4 shows how to respond to FIQ
with short latency in this mode.
2. Register vectored interrupts (automatically provide vector address to application)
Before enabling interrupts, the application software also has to initiate the interrupt vector table (VIM
RAM).
Once the VIM receives an interrupt, it loads the address of ISR from interrupt vector table, and store it
into the interrupt vector register (IRQVECREG for IRQ interrupt, FIQVECREG for FIQ interrupt).
After the interrupt is received by the CPU, the CPU executes the instruction placed at 0x18 or 0x1C
(IRQ or FIQ vector) to load the address of ISR (interrupt vector) from the interrupt vector register.
Example 15-3 illustrates the configuration for the exception vectors using this mode.
3. Hardware vectored interrupts (automatically dispatch to ISR, IRQ only)
Before enabling interrupts, the application software must initiate the interrupt vector table (VIM RAM)
pointing to the ISR for each interrupt channel.
After the interrupt (IRQ) is received by the CPU, CPU reads the address of ISR directly from the
interface with VIM (VIC port) instead of branching to 0x18. The CPU will branch directly to the ISR.
The hardware vectored interrupt behavior must be explicitly enabled by setting the vector enable (VE)
bit in the CP15 R1 register. This bit resets to 0, so that the default state after reset is backward
compatible to earlier ARM CPU. Example 15-1 shows how to enable the hardware vectored interrupt.
NOTE: This mode is NOT available for FIQ.
4. Software-Based Priority Decoding Scheme
If the application uses a software-based interrupt priority decoding scheme instead of the hardware
vector capabilities, then there is an additional step which was not required on earlier devices. This
version of the VIM will hold an interrupt request generated by a peripheral. When the software clears
the interrupt condition in the source module (for example, RTI, GIO, and so on), then it must also
perform an additional clear of the interrupt request in the VIM. This can be done by reading the
IRQVECREG register ( Section 15.8.14) or FIQVECREG register (Section 15.8.15), or by writing a 1 to
the INTREQ(i) bit (Section 15.8.9) in the VIM. This is not necessary if any of the three previous
methods are used as the interrupt request bit in the VIM will be automatically cleared when the vector
is read.
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15.3 Interrupt Handling Inside VIM
A block diagram of the interrupt handling inside VIM is shown in Figure 15-2
Figure 15-2. VIM Interrupt Handling Block Diagram
INT_
REQ0
INT_
REQ1
INT_
REQ2
INT_
INT_
REQ93 REQ94
CHANNEL
MAPPING
CHAN0 CHAN1 CHAN2
CHAN93 CHAN94
INTERRUPT
ENABLE
INT_
INT_
INT_
CHAN0 CHAN1 CHAN2
INT_
INT_
CHAN93 CHAN94
IRQ / FIQ
LEVEL
FIQ_ FIQ_
CHAN93 CHAN94
FIQ_
FIQ_
FIQ_
CHAN0 CHAN1 CHAN2
IRQ_
CHAN2
FIQ
Register
FIQINDEX
FIQ INDEX
To CPU
IRQ LEVEL
PRIORITY ENCODER
IRQ INDEX
FIQ LEVEL
PRIORITY ENCODER
IRQ_
IRQ_
CHAN93 CHAN94
IRQ
PROGRAMMABLE INTERRUPT VECTOR TABLE
To CPU
Register
IRQINDEX
Phantom Vector
Channel 0 Vector
Channel 1 Vector
Register
FIQVECREG
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IRQ VECTOR
FIQ VECTOR
Channel 94 Vector
TO CPU
VIC Port
Register
IRQVECREG
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15.3.1 VIM Interrupt Channel Mapping
The VIM support 96 interrupt channels (including phantom interrupt). A block diagram of the VIM interrupt
requests arrangement from peripheral modules to the interrupt channels, is provided in Figure 15-3. Each
interrupt channel(CHANx) has a corresponding mapping register bit field (CHANMAPx[6:0]). This mapping
register determines which interrupt channel it maps each VIM interrupt request. With this scheme, the
same request can be mapped to multiple channels. A lower numbered channel in each FIQ and IRQ has
higher priority. The programmability of the VIM allows software to control the interrupt priority.
Figure 15-3. VIM Channel Mapping
INT_ INT_ INT_
REQ0 REQ1 REQ2
CHANMAP2[6:0]
INT_
REQ94
NOTE:
CHAN0 and CHAN1 are hard wired to
INT_REQ0 and INT_REQ1, can NOT
be remapped.
7
CHAN2
CHANNEL
MAPPING
INT_ INT_ INT_
REQ0 REQ1 REQ2
CHANMAP94[6:0]
95 Interrupt
Channels
INT_
REQ94
7
CHAN94
NOTE: CHAN95
CHAN95 has no dedicated interrupt vector table entry. Therefore, CHAN95 shall NOT be
remapped to other INT_REQ (INT_REQ95 is reserved at device level).
In the reset state, the VIM maps all of the interrupt requests in the system to their respective interrupt
channels. Figure 15-4 shows the default state following the reset.
Figure 15-5 shows the VIM INT2 is remapped to both Channel 2 and 4, and INT3 is mapped to channel 3.
NOTE: By mapping INT2 to channel 2 and channel 4, and mapping INT3 to channel 3, it is possible
for the software to change the priority dynamically by changing the ENABLE register
(REQENASET and REQENACLR). When channel 2 is enabled, the priority is:
1. INT0
2. INT1
3. INT2
4. INT3
Disabling channel 2, the priority becomes:
1.
2.
3.
4.
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INT1
INT3
INT2
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Figure 15-4. VIM in Default State
Phantom Vector
0xFFF82000
Peripheral 0
INT_REQ0
CHANMAP0
CHAN0
Channel 0 Vector
0xFFF82004
Peripheral 1
INT_REQ1
CHANMAP1
CHAN1
Channel 1 Vector
0xFFF82008
Peripheral 2
INT_REQ2
CHANMAP2
CHAN2
Channel 2 Vector
0xFFF8200C
Peripheral 3
INT_REQ3
CHANMAP3
CHAN3
Channel 3 Vector
0xFFF82010
Peripheral 4
INT_REQ4
CHANMAP4
CHAN4
Channel 4 Vector
0xFFF82014
Interrupt
requests
(from peripheral)
Interrupt
channels
Peripheral 93
INT_REQ93
CHANMAP93
CHAN93
Channel 93 Vector
0xFFF82178
Peripheral 94
INT_REQ94
CHANMAP94
CHAN94
Channel 94 Vector
0xFFF8217C
NOTE: CHAN0 and CHAN1 are hardwired to INT_REQ0 and INT_REQ1, so they cannot be
remapped.
Figure 15-5. VIM in a Programmed State
Phantom Vector
0xFFF82000
Peripheral 0
INT_REQ0
CHANMAP0
CHAN0
Channel 0 Vector
0xFFF82004
Peripheral 1
INT_REQ1
CHANMAP1
CHAN1
Channel 1 Vector
0xFFF82008
Peripheral 2
INT_REQ2
CHANMAP2
CHAN2
Channel 2 Vector
0xFFF8200C
Peripheral 3
INT_REQ3
CHANMAP3
CHAN3
Channel 3 Vector
0xFFF82010
Peripheral 4
INT_REQ4
CHANMAP4
CHAN4
Channel 4 Vector
0xFFF82014
Interrupt
requests
(from peripheral)
Interrupt
channels
Peripheral 93
INT_REQ93
CHANMAP93
CHAN93
Channel 93 Vector
0xFFF82178
Peripheral 94
INT_REQ94
CHANMAP94
CHAN94
Channel 94 Vector
0xFFF8217C
NOTE: CHAN0 and CHAN1 are hard wired to INT_REQ0 and INT_REQ1, so they cannot be
remapped.
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15.3.2 VIM Input Channel Management
As shown in Figure 15-6, the VIM enables channels on a channel-by-channel basis (in the REQENASET
and REQENACLR registers); unused channels may be masked to prevent spurious interrupts.
NOTE: The interrupt ENABLE register does not affect the value of INTREQ.
Figure 15-6. Interrupt Channel Management
INT FLAG
INTREQ.0
FIQ_CHAN[0]
CHAN0
INT_CHAN0
INT FLAG
INTREQ.1
FIQ_CHAN[1]
CHAN1
INT_CHAN1
INT FLAG
INTREQ.2
CHAN2
1
REQENA.2
INT_CHAN2
Controlled by:
REQENASET.2
REQENACLR.2
0
FIQ_CHAN[2]
IRQ_CHAN[2]
FIRQPR.2
INT FLAG
INTREQ.95
CHAN95
FIQ_CHAN[95]
1
REQENA.95
INT_CHAN95
Controlled by:
REQENASET.95
REQENACLR.95
0
IRQ_CHAN[95]
FIRQPR.95
By default, interrupt CHAN0 is mapped to ESM (Error Signal Module) high level interrupt and CHAN1 is
reserved for other NMI. For safety reasons, these two channels are mapped to FIQ only and can NOT be
disabled through ENABLE registers.
NOTE: NMI Channel
Channel 0 and channel 1 are not maskable by the REQENASET/REQENACLR bit and both
channels are routed exclusively to FIQ/NMI request line (FIRQPR0 and FIRQPR1 have no
effect).
The VIM prioritizes the received interrupts based upon a programmed prioritization scheme. The VIM can
send two interrupt requests to the CPU simultaneously—one IRQ and one FIQ. If both interrupt types are
enabled at the CPU level, then the FIQ has greater priority and is handled first. Each interrupt channel,
except channel 0 and 1, can be assigned to send either an FIQ or IRQ request to the CPU (in the
FIRQPR register).
The VIM provides a default prioritization scheme, which sends the lowest numbered active channel (in
each FIQ and IRQ classes) to the CPU. Within the FIQ and IRQ classes of interrupts, the lowest channel
has the highest priority interrupt. The channel number is programmable through register CHANMAPx.
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After the VIM has generated the vector corresponding to the highest active IRQ, it updates the FIQINDEX
or the IRQINDEX register, depending on the class of interrupt. Then, it accesses the interrupt vector table
using the vector value to fetch the address of the corresponding ISR. If the request is an FIQ class
interrupt, the address read from the interrupt vector table, is written to the FIQVECREG register. If the
request is an IRQ class interrupt, the address is written to the IRQVECREG register and put on the VIC
port of the CPU (in case of hardware vectored interrupt is enabled).
All of the interrupt registers are updated when a new high priority interrupt line becomes active.
15.4 Interrupt Vector Table (VIM RAM)
Interrupt vector table stores the address of ISRs. During register vectored interrupt and hardware vectored
interrupt, VIM accesses the interrupt vector table using the vector value to fetch the address of the
corresponding ISR.
For safety reasons, the interrupt vector table has protection by parity to indicate corruption due to soft
errors. The parity scheme is implemented as a continuous background check based on memory access.
Section 15.4.1 through Section 15.4.4 describe how parity works in the interrupt vector table.
NOTE: Writes to the interrupt vector table parity flag register (PARFLG) and the interrupt vector
table parity control register (PARCTL) are in privilege mode only.
15.4.1 Interrupt Vector Table Operation
The interrupt vector table is organized in 96 words of 32 bits. 32-bit, 16-bit, and 8-bit accesses are
supported (when parity is disabled). Figure 15-7 shows the interrupt memory mapping. The table base
address is FFF8 2000h.
Figure 15-7. VIM Interrupt Address Memory Map
Interrupt vector table address space
0xFFF82000
Phantom Vector
0xFFF82004
Channel 0 Vector
0xFFF82008
Channel 1 Vector
0xFFF82178
Channel 93 Vector
0xFFF8217C
Channel 94 Vector
NOTE: The interrupt vector table only has 96 entries, one phantom vector and 95 interrupt channels.
Channel 95 does not have a dedicated vector and shall not be used.
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There is one bit of parity per 32-bit ISR address. When a write is performed into the interrupt vector table,
the parity is calculated for the 32-bit word and a parity bit is written into the corresponding parity region of
interrupt vector table.
NOTE: Only 32-bit write/read access are allowed on interrupt vector table if parity is required. Non
32-bit access might result in parity errors.
When a read occurs from the CPU or VIM, the VIM calculates the parity from the data coming from the
interrupt vector table and compares it to the parity stored in the table. The access of the data and the
parity is performed in the same clock cycle.
If the parity bit does not match the calculated parity, a parity error is generated and the VIM stores the
address of the error in the ADDERR register. The parity flag error (PARFLG) is set.
NOTE: The PARFLG register is only for bypassing the interrupt vector table in case of a parity fault.
It should be used only to maintain the interrupt vector table bypassed. The checking of the
parity fault should be done in the error signaling module (ESM) module where all parity
errors are flagged.
Since the interrupt vector table may have an error, the FBPARERR register will provide to the VIC port,
IRQVECREG and FIQVECREG, a fall-back address to an ISR that can restore the interrupt vector table
content. The FBPARERR register should be set before initializing the interrupt in the interrupt vector table,
to avoid branching to an unpredictable location.
The normal operation is restored when the PARFLG is cleared by the CPU. It is recommended to restore
the content of the VIM before clearing the PARFLG.
The parity error signal is forwarded to the ESM.
15.4.2 Enabling and Controlling the VIM Parity
The polarity of VIM parity is controlled by the DEVCR1 register in the system module (address
FFFF FFDCh). The parity enable is controlled by the PARCTL register. After reset, the parity is disabled.
Parity checking can be enabled by writing 0xA (1010b) in the PARENA[3:0] bit field of the PARCTL
register. The default polarity is odd. The polarity can be changed to even by writing 5 (0101b) in the
DEVPARSEL[3:0] bit field of the DEVCR1 register.
15.4.3 Interrupt Vector Table Initialization
After reset, the interrupt vector table content including the parity bits is not initialized. Therefore, the CPU
needs to initialize all of the interrupt addresses into the table, before enabling the corresponding interrupt
channel. If parity is required, this initialization should be done after the parity functionality is enabled. In
this way, the corresponding parity bit will be automatically updated. This initialization is only required when
vectored interrupts are used, index interrupt management does not need the table to be initialized.
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15.4.4 Interrupt Vector Table Parity Testing
To test the parity checking mechanism, the parity RAM allows manual insertion of faults. This option is
implemented by the test bit in the PARCTL register. Once the bit is set, the parity bits are mapped to
0xFFF82400. After that, user can force faults into the parity bits. Finally, the parity error can be triggered
by reading interrupt vector table (not parity bit) from VIM or CPU.
The interrupt vector table parity can also be verified by inserting faults into interrupt vector table. Once the
VIM parity is disabled in system module, user can modify interrupt vector table without impacting the parity
bit. After user re-enable interrupt vector table parity, the parity error can be triggered by reading interrupt
vector table from VIM or CPU.
Figure 15-8. Parity Bit Mapping
32-bit only accessible
31
0xFFF82000
0
Word 0
Word 1
Word 2
Word 3
31
0xFFF82400
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1
0
Read 0
P0
Read 0
P1
Read 0
P2
Read 0
P3
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15.5 VIM Wakeup Interrupt
The wakeup interrupts are used to come out of low power mode (LPM). Any interrupt requests can be
used to wake up the device. After reset, all interrupt requests are set to wake up from LPM. However, the
VIM can mask unwanted interrupt lines for wake-up by using the WAKEENASET and WAKEENACLR
register. The value in REQENASET/REQENACLR does NOT impact the wakeup interrupt.
As shown in Figure 15-9, the WAKEENASET and WAKEENACLR registers will enable/disable an interrupt
for wake-up from low-power mode. All wake-up interrupts are “ORed” into a single signal WAKE_INT
connected to the Global Clock Module.
Figure 15-9. Detail of the IRQ Input
INT_REQ0
WAKEUP0
WAKEENA.0
Controlled by:
WAKEENASET.0
WAKEENACLR.0
INT_REQ1
WAKEUP1
WAKEENA.1
Controlled by:
WAKEENASET.1
WAKEENACLR.1
INT_REQ2
WAKEUP2
OR
WAKE_INT
WAKEENA.2
Controlled by:
WAKEENASET.2
WAKEENACLR.2
INT_REQ95
WAKEUP95
WAKEENA.95
Controlled by:
WAKEENASET.95
WAKEENACLR.95
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15.6 Capture Event Sources
The VIM can select any of the 96 interrupt requests to generate up to two capture events for the real-time
interrupt (RTI) module (see Figure 15-10). The value in REQENASET/REQENACLR does NOT impact the
capture event. Two registers (Section 15.8.16) are available, one for each capture event source.
Figure 15-10. Capture Event Sources
7
CAPEVTSRC0[6:0]
7
INT_REQ0
INT_REQ1
INT_REQ0
INT_REQ1
CAPEVT0
To RTI
CAPEVTSRC1[6:0]
CAPEVT1
To RTI
INT_REQ94
INT_REQ95
INT_REQ94
INT_REQ95
15.7 Examples
The following sections provide examples about the operation of the VIM.
15.7.1 Examples - Configure CPU To Receive Interrupts
Example 15-1 shows how to set the vector enable (VE) bit in the CP15 R1 register to enable the hardware
vector interrupt. Example 15-2 shows how to enable/disable the IRQ and FIQ through CPSR. As a
convention, the program who calls these subroutines shall preserve register R1 if needed. Example 15-2
can ONLY run in privileged mode. However, in USER mode, the application software can force the
program into software interrupt by instruction SWI. Then, in the software interrupt service routine, user can
write register SPSR, which is the copy of CPSR in this exception mode.
Example 15-1. Enable Hardware Vector Interrupt (IRQ Only)
_HW_Vec_Init
MRC p15 ,#0 ,R1 ,c1 ,c0 ,#0
ORR R1 ,R1 ,#0x01000000
MCR p15 ,#0 ,R1 ,c1 ,c0 ,#0
MOV PC, LR
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; Mask 0-31 bits except bit 24 in Sys
; Ctrl Reg of CORTEX-R4
; Enable bit 24
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Example 15-2. Enable/Disable IRQ/FIQ through CPSR
FIQENABLE .equ 0x40
IRQENABLE .equ 0x80
......
_Enable_Fiq
MRS R1, CPSR
BIC R1, R1, #FIQENABLE
MSR CPSR, R1
MOV PC, LR
......
_Disable_Irq
MRS R1, CPSR
ORR R1, R1, #IRQENABLE
MSR CPSR, R1
MOV PC, LR
......
_Enable_Irq
MRS R1, CPSR
BIC R1, R1, #IRQENABLE
MSR CPSR, R1
MOV PC, LR
15.7.2 Examples - Register Vector Interrupt and Index Interrupt Handling
Example 15-3 shows the configuration for the exception vectors in Register Vector Interrupt handling. After
the interrupt is received by the CPU, the CPU branches to 0x18 (IRQ) or 0x1C (FIQ). The instruction
placed here should be LDR PC, [PC,#-0x1B0]. The pending ISR address is written into the corresponding
vector register (IRQVECREG for IRQ, FIQVECREG for FIQ). The CPU reads the content of the register
and branches to the ISR.
Example 15-3. Exception Vector Configuration for VIM Vector
00000000h
00000004h
00000008h
0000000Ch
00000010h
00000014h
00000018h
0000001Ch
.sect ".intvecs"
b _RESET
b _UNDEF_INST_INT
b _SW_INT
b _ABORT_PREF_INT
b _ABORT_DATA_INT
b #-8
ldr pc,[pc,#-0x1B0]
ldr pc,[pc,#-0x1B0]
;
;
;
;
;
;
;
;
RESET interrupt
UNDEFINED INSTRUCTION interrupt
SOFTWARE interrupt
ABORT (PREFETCH) interrupt
ABORT (DATA) interrupt
Reserved
IRQ interrupt
FIQ interrupt
NOTE: Program Counter (PC) always pointers two instructions beyond the current executed
instruction. In this case, PC equals to ‘0x18 or 0x1C + 0x08’. The LDR instruction load the
memory at ‘PC - 0x1B0’, which is ‘0x18 or 0x1C + 0x08 - 0x1B0 = 0xFFFFFE70 or
0xFFFFFE74’. These are the address of IRQVECREG and FIQVECREG, which store the
pending ISR address.
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Example 15-4 shows a fast response to the FIQ interrupt in Index Interrupt and can be applied to a system
that has more than one channel assigned as a FIQ. It is built in Index Interrupt compatible with
TMS470R1x legacy code.
Example 15-4. How to Respond to FIQ With Short Latency
00000000h
00000004h
00000008h
0000000Ch
00000010h
00000014h
00000018h
.sect ".intvecs"
b _RESET
b _UNDEF_INST_INT
b _SW_INT
b _ABORT_PREF_INT
b _ABORT_DATA_INT
b #-8
b _IRQ_ENTRY_0
0000001Ch ldrb R8, [PC,#-0x21d]
00000020h ldr PC, [PC, R8, LSL#2]
00000024h nop
00000028h _INT_TABLE
0000002Ch .word _FIQ_TABLE
00000030h .word _ISR1
00000034h .word _ISR2
.
.
; Interrupt and exception vector sector
; RESET interrupt
; UNDEFINED INSTRUCTION interrupt
; SOFTWARE interrupt
; ABORT (PREFETCH) interrupt
; ABORT (DATA) interrupt
; Reserved
; IRQ interrupt
;*********************************
; INTERRUPT PROCESSING AREA
;*********************************
; FIQ INTERRUPT ENTRY
; R8 used to get the FIQ index
; with address pointer to the
; first FIQ banked register
; Branch to the indexed interrupt
; routine. The prefetch
; operation causes the PC to be 2
; words (8 bytes) ahead of the
; current instruction, so
; pointing to _INT_TABLE.
; Required due to pipeline.
;=================================
; FIQ INTERRUPT DISPATCH
;=================================
; beginning of FIQ Dispatch
; dispatch to interrupt routine 1
; dispatch to interrupt routine 2
Another way to improve the FIQ latency is to assign only one channel to the FIQ interrupt and to map the
ISR code corresponding to this channel directly starting at 0x1C.
NOTE: When the CPU is in vector-enabled mode, Example 15-3 and Example 15-4 are still valid.
The difference is that the CPU will not read from the 0x18 location during IRQ interrupt, but
will jump directly to the corresponding ISR routine.
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15.8 VIM Control Registers
This section details the VIM module registers, summarized in Table 15-1.
Each register begins on a word boundary. All registers are 32-bit, 16-bit, and 8-bit accessible for read and
write. Write is only possible in privilege mode. The base address of the control registers is FFFF FE00h.
The base address of the parity-related VIM registers is FFFF FD00h. The address locations not listed are
reserved.
Table 15-1. VIM Control Registers
Offset
Acronym
Register Description
Section
Parity-related Registers
ECh
PARFLG
Interrupt Vector Table Parity Flag Register
Section 15.8.1
F0h
PARCTL
Interrupt Vector Table Parity Control Register
Section 15.8.2
F4h
ADDERR
Address Parity Error Register
Section 15.8.3
F8h
FBPARERR
Fall-Back Address Parity Error Register
Section 15.8.4
Control Registers
00h
IRQINDEX
IRQ Index Offset Vector Register
Section 15.8.6
04h
FIQINDEX
FIQ Index Offset Vector Register
Section 15.8.7
10h
FIRQPR0
FIQ/IRQ Program Control Register 0
Section 15.8.8
14h
FIRQPR1
FIQ/IRQ Program Control Register 1
Section 15.8.8
18h
FIRQPR2
FIQ/IRQ Program Control Register 2
Section 15.8.8
20h
INTREQ0
Pending Interrupt Read Location Register 0
Section 15.8.9
24h
INTREQ1
Pending Interrupt Read Location Register 1
Section 15.8.9
28h
INTREQ2
Pending Interrupt Read Location Register 2
Section 15.8.9
30h
REQENASET0
Interrupt Enable Set Register 0
Section 15.8.10
34h
REQENASET1
Interrupt Enable Set Register 1
Section 15.8.10
38h
REQENASET2
Interrupt Enable Set Register 2
Section 15.8.10
40h
REQENACLR0
Interrupt Enable Clear Register 0
Section 15.8.11
44h
REQENACLR1
Interrupt Enable Clear Register 1
Section 15.8.11
48h
REQENACLR2
Interrupt Enable Clear Register 2
Section 15.8.11
50h
WAKEENASET0
Wake-up Enable Set Register 0
Section 15.8.12
54h
WAKEENASET1
Wake-up Enable Set Register 1
Section 15.8.12
58h
WAKEENASET2
Wake-up Enable Set Register 2
Section 15.8.12
60h
WAKEENACLR0
Wake-up Enable Clear Register 0
Section 15.8.13
64h
WAKEENACLR1
Wake-up Enable Clear Register 1
Section 15.8.13
68h
WAKEENACLR2
Wake-up Enable Clear Register 2
Section 15.8.13
70h
IRQVECREG
IRQ Interrupt Vector Register
Section 15.8.14
74h
FIQVECREG
FIQ Interrupt Vector Register
Section 15.8.15
78h
CAPEVT
Capture Event Register
Section 15.8.16
CHANCTRL
VIM Interrupt Control Register
Section 15.8.17
80h-DCh
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15.8.1
Interrupt Vector Table Parity Flag Register (PARFLG)
Figure 15-11 and Table 15-2 describe this register.
Figure 15-11. Interrupt Vector Table Parity Flag Register (PARFLG) [offset = ECh]
31
16
Reserved
R-0
15
1
0
Reserved
PARFLG
R-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 15-2. Interrupt Vector Table Parity Flag Register (PARFLG) Field Descriptions
Bit
Field
Value
31-1
Reserved
0
PARFLG
0
Description
Read returns 0. Writes have no effect.
The PARFLG indicates that a parity error has been found and that the Interrupt Vector Table is
bypassed. The resulting vector of any IRQ/FRQ interrupt is then the value contained in the
FBPARERR register until this bit has been cleared.
0
Read: No parity error has occurred.
Write: A write to this bit has no effect.
1
Read: A parity error has occurred and the Interrupt Vector Table is bypassed.
Write: The PARFLG is cleared and the interrupt vector can be read from the Interrupt Vector Table.
15.8.2 Interrupt Vector Table Parity Control Register (PARCTL)
Figure 15-12. Interrupt Vector Table Parity Control Register (PARCTL) [offset = F0h]
31
16
Reserved
R-0
15
9
Reserved
8
7
TEST
R-0
R/WP-0
4
Reserved
R-0
3
0
PARENA
R/WP-5h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 15-3. Interrupt Vector Table Parity Control Register (PARCTL) Field Descriptions
Bit
31-9
8
Field
Reserved
Value
0
TEST
7-4
Reserved
3-0
PARENA
Description
Read returns 0. Writes have no effect.
This bit maps the parity bits into the Interrupt Vector Table frame to make them accessible by the
CPU.
0
Parity bits are not memory mapped.
1
Parity bits are memory mapped.
0
Read returns 0. Writes have no effect.
VIM parity enable.
5h
The VIM parity is disabled.
All Others
The VIM parity is enabled.
Note: To avoid soft error to disable VIM parity checking, it is recommended to write Ah to
enable parity checking.
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15.8.3 Address Parity Error Register (ADDERR)
The address parity error register gives the address of the first parity error location.
NOTE: No computation is needed when reading the complete register to retrieve the address in the
Interrupt Vector Table.
This register will never be reset by a power-on reset nor any other reset source.
Figure 15-13. Address Parity Error Register (ADDERR) [offset = F4h]
31
16
Interrupt Vector Table offset
R-FFF8h
15
9
8
2
1
0
Interrupt Vector Table offset
ADDERR
Word offset
R-0010 000b
R-x
R-0
LEGEND: R = Read only; -n = value after reset
Table 15-4. Address Parity Error Register (ADDERR) Field Descriptions
Field
Description
31-9
Bit
Interrupt Vector Table
offset
Interrupt Vector Table offset. Reads are always FFF8 2xxxh; writes have no effect.
8-2
ADDERR
Address parity error register. This register gives the address of the first encountered parity error since
the flag has been clear. Subsequent parity errors will not update this register until the PARFLG register
has been cleared.
1-0
Word offset
Note: This register is valid only when PARFLG is set (see Section 15.8.1).
Word offset. Reads are always 0; writes have no effect.
15.8.4 Fall-Back Address Parity Error Register (FBPARERR)
This register provides a fall-back address to the VIM if a parity error has occurred in the Interrupt Vector
Table. Figure 15-14 and Table 15-5 describe this register.
NOTE: This register will never be reset by a power-on reset nor any other reset source.
Figure 15-14. Fall-Back Address Parity Error Register (FBPARERR) [offset = F8h]
31
16
FBPARERR
R/WP-x
15
0
FBPARERR
R/WP-x
LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset; x = Indeterminate
Table 15-5. Fall Back Address Parity Error Register (FBPARERR) Field Descriptions
Bit
31-0
Field
FBPARERR
Value
0-FFFF FFFFh
Description
Fall back address parity error. This register is used by the VIM if the Interrupt Vector Table
has been corrupted. The contents of the IRQVECREG and FIQVECREG registers will reflect
the value programmed in FBPARERR. The value provided to the VIC port will also reflect
FBPARERR until the PARFLG register has been cleared.
This register provides the address of the ISR that will restore the integrity of the Interrupt
Vector Table.
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15.8.5 VIM Offset Vector Registers
The VIM offset register provides the user with the numerical index value that represents the pending
interrupt with the highest precedence. The register IRQINDEX holds the index to the highest priority IRQ
interrupt; the register FIQINDEX holds the index to the highest priority FIQ interrupt. The index can be
used to locate the interrupt routine in a dispatch table, as shown in Table 15-6.
Table 15-6. Interrupt Dispatch
IRQINDEX / FIQINDEX Register Bit Field
Highest Priority Pending Interrupt Enabled
0x00
No interrupt
0x01
Channel 0
:
:
0x5F
Channel 94
0x60
Channel 95
NOTE: Channel 95 has no dedicated interrupt vector table entry. Therefore, Channel 95 shall NOT
be used in application.
The VIM offset registers are read only. They are updated continuously by the VIM. When an interrupt is
serviced, the offset vectors show the index for the next highest pending interrupt or 0x0 if no interrupt is
pending.
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15.8.6 IRQ Index Offset Vector Register (IRQINDEX)
The IRQ offset register provides the user with the numerical index value that represents the pending IRQ
interrupt with the highest priority. Figure 15-15 and Table 15-7 describe this register.
Figure 15-15. IRQ Index Offset Vector Register (IRQINDEX) [offset = 00h]
31
16
Reserved
R-0
15
8
7
0
Reserved
IRQINDEX
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 15-7. IRQ Index Offset Vector Register (IRQINDEX) Field Descriptions
Bit
Field
Value
31-8
Reserved
0
7-0
IRQINDEX
0-FFh
Description
Read returns 0. Writes have no effect.
IRQ index vector. The least-significant bits represent the index of the IRQ pending interrupt with
the highest precedence, as shown in Table 15-6. When no interrupts are pending, the leastsignificant byte of IRQINDEX is 0.
Note: A read of register IRQINDEX or IRQVECREG will cause IRQINDEX / IRQVECREG to
reflect the index/ISR address for the next highest-priority pending IRQ interrupt. In case there is
no other interrupt pending, the IRQINDEX will read 0x00 and the IRQVECREG register will read
the phantom interrupt address.
15.8.7 FIQ Index Offset Vector Registers (FIQINDEX)
The FIQINDEX register provides the user with a numerical index value that represents the pending FIQ
interrupt with the highest priority. Figure 15-16 and Table 15-8 describe this register.
Figure 15-16. FIQ Index Offset Vector Register (FIQINDEX) [offset = 04h]
31
16
Reserved
R-0
15
8
7
0
Reserved
FIQINDEX
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 15-8. FIQ Index Offset Vector Register (FIQINDEX) Field Descriptions
Bit
Field
Value
31-8
Reserved
0
7-0
FIQINDEX
0-FFh
534
Description
Read returns 0. Writes have no effect.
FIQ index offset vector. The least-significant bits represent the index of the FIQ pending
interrupt with the highest precedence, as shown in Table 15-6. When no interrupts are pending,
the least-significant byte of FIQINDEX is 0x00.
Note: A read of register FIQINDEX or FIQVECREG will cause FIQINDEX / FIQVECREG to
reflect the index/ISR address for the next highest-priority pending FIQ interrupt. In case there is
no other interrupt pending, the FIQINDEX will read 0x00 and the FIQVECREG register will read
the phantom interrupt address.
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15.8.8 FIQ/IRQ Program Control Registers (FIRQPR[0:2])
The FIQ/IRQ program control registers (FIRQPRx) determine whether a given interrupt request will be
either FIQ or IRQ. Figure 15-17, Figure 15-18, Figure 15-19 and Table 15-9 describe these registers.
NOTE: Channel 0 and 1 are FIQ only, not impacted by this register.
Figure 15-17. FIQ/IRQ Program Control Register 0 (FIRQPR0) [offset = 10h]
31
16
FIRQPR0[31:16]
R/WP-0
15
2
1
0
FIRQPR0[15:2]
Reserved
R/WP-0
R-3h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Figure 15-18. FIQ/IRQ Program Control Register 1 (FIRQPR1) [offset = 14h]
31
16
FIRQPR1[63:48]
R/WP-0
15
0
FIRQPR1[47:32]
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Figure 15-19. FIQ/IRQ Program Control Register 2 (FIRQPR2) [offset = 18h]
31
16
FIRQPR2[95:80]
R/WP-0
15
0
FIRQPR2[79:64]
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 15-9. FIQ/IRQ Program Control Registers (FIRQPRx) Field Descriptions
Bit
95-2
1-0
Field
Value
FIRQPRx[95:2]
Reserved
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Description
FIQ/IRQ program control bits. These bits determine whether an interrupt request from a peripheral
is of type FIQ or IRQ. Bit FIRQPRx[95:2] corresponds to request channel[95:2].
0
Interrupt request is of IRQ type.
1
Interrupt request is of FIQ type.
3h
Read only. Writes have no effect.
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15.8.9 Pending Interrupt Read Location Registers (INTREQ[0:2])
The pending interrupt registers (INTREQx) give the pending interrupt requests. The register is updated
every vbus clock cycle. Figure 15-20, Figure 15-21, Figure 15-22 and Table 15-10 describe this register.
Figure 15-20. Pending Interrupt Read Location Register 0 (INTREQ0) [offset = 20h]
31
16
INTREQ0[31:16]
R/W1CP-0
15
0
INTREQ0[15:0]
R/W1CP-0
LEGEND: R/W = Read/Write; W1CP = Write 1 to clear in privilege mode only; -n = value after reset
Figure 15-21. Pending Interrupt Read Location Register 1 (INTREQ1) Register [offset = 24h]
31
16
INTREQ1[63:48]
R/W1CP-0
15
0
INTREQ1[47:32]
R/W1CP-0
LEGEND: R/W = Read/Write; W1CP = Write 1 to clear in privilege mode only; -n = value after reset
Figure 15-22. Pending Interrupt Read Location Register 2 (INTREQ2) Register [offset = 28h]
31
16
INTREQ2[95:80]
R/W1CP-0
15
0
INTREQ2[79:64]
R/W1CP-0
LEGEND: R/W = Read/Write; W1CP = Write 1 to clear in privilege mode only; -n = value after reset
Table 15-10. Pending Interrupt Read Location Registers (INTREQx) Field Descriptions
Bit
95-0
Field
Value
INTREQx[95:0]
Description
Pending interrupt bits. These bits determine whether an interrupt request is pending for the request
channel between 0 and 95. The interrupt ENABLE register does not affect the value of the interrupt
pending bit. Bit INTREQx[95:0] corresponds to request channel[95:0].
User and Privilege Mode read:
0
No interrupt event has occurred.
1
An interrupt is pending.
Privilege Mode write only:
536
0
Writing 0 has no effect.
1
Clears the interrupt pending status flag. This write-clear functionality is intended to allow clearing
those interrupts which have been signaled to VIM before enabling the interrupt channel, if they are
undesired.
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15.8.10 Interrupt Enable Set Registers (REQENASET[0:2])
The interrupt enable set registers (REQENASETx) selectively enables individual request channels.
Figure 15-23, Figure 15-24, Figure 15-25 and Table 15-11 describe these registers.
NOTE: Channel 0 and 1 are always enabled, not impacted by this register.
Figure 15-23. Interrupt Enable Set Register 0 (REQENASET0) [offset = 30h]
31
16
REQENASET0[31:16]
R/WP-0
15
2
1
0
REQENASET0[15:2]
Reserved
R/WP-0
R-3h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Figure 15-24. Interrupt Enable Set Register 1 (REQENASET1) [offset = 34h]
31
16
REQENASET1[63:48]
R/WP-0
15
0
REQENASET1[47:32]
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Figure 15-25. Interrupt Enable Set Register 2 (REQENASET2) [offset = 38h]
31
16
REQENASET2[95:80]
R/WP-0
15
0
REQENASET2[79:64]
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 15-11. Interrupt Enable Set Registers (REQENASETx) Field Descriptions
Bit
95-2
Field
Value
REQENASETx[95:2]
Description
Request enable set bits. This vector determines whether the interrupt request channel is
enabled. Bit REQENASETx[95:2] corresponds to request channel[95:2].
0
Read: Interrupt request channel is disabled.
Write: A write of 0 has no effect.
1-0
Reserved
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1
Read or Write: The interrupt request channel is enabled.
3h
Read only. Writes have no effect.
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15.8.11 Interrupt Enable Clear Registers (REQENACLR[0:2])
The interrupt enable clear registers (REQENACLRx) selectively disables individual request channels.
Figure 15-26, Figure 15-27, Figure 15-28 and Table 15-12 describe these registers.
NOTE: Channel 0 and 1 are always enabled, not impacted by this register.
Figure 15-26. Interrupt Enable Clear Register 0 (REQENACLR0) [offset = 40h]
31
16
REQENACLR0[31:16]
R/WP-0
15
2
1
0
REQENACLR0[15:2]
Reserved
R/WP-0
R-3h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Figure 15-27. Interrupt Enable Clear Register 1 (REQENACLR1) [offset = 44h]
31
16
REQENACLR1[63:48]
R/WP-0
15
0
REQENACLR1[47:32]
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Figure 15-28. Interrupt Enable Clear Register 2 (REQENACLR2) [offset = 48h]
31
16
REQENACLR2[95:80]
R/WP-0
15
0
REQENACLR2[79:64]
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 15-12. Interrupt Enable Clear Registers (REQENACLRx) Field Descriptions
Bit
95-2
Field
Value
REQENACLRx[95:2]
Description
Request enable clear bits. This vector determines whether the interrupt request channel is
enabled. Bit REQENACLRx[95:2] corresponds to request channel[95:2].
0
Read: Interrupt request channel is disabled.
Write: A write of 0 has no effect.
1
Read: The interrupt request channel is enabled.
Write: The interrupt request channel is disabled.
1-0
538
Reserved
3h
Read only. Writes have no effect.
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15.8.12 Wake-Up Enable Set Registers (WAKEENASET[0:2])
The wake-up enable set registers (WAKEENASETx) selectively enables individual wake-up interrupt
request lines. Figure 15-29, Figure 15-30, Figure 15-31 and Table 15-13 describe these registers.
Figure 15-29. Wake-Up Enable Set Register 0 (WAKEENASET0) [offset = 50h]
31
16
WAKEENASET0[31:16]
R/WP-FFFFh
15
0
WAKEENASET0[15:0]
R/WP-FFFFh
LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset
Figure 15-30. Wake-Up Enable Set Register 1 (WAKEENASET1) [offset = 54h]
31
16
WAKEENASET1[63:48]
R/WP-FFFFh
15
0
WAKEENASET1[47:32]
R/WP-FFFFh
LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset
Figure 15-31. Wake-Up Enable Set Register 2 (WAKEENASET2) [offset = 58h]
31
16
WAKEENASET2[95:80]
R/WP-FFFFh
15
0
WAKEENASET2[79:64]
R/WP-FFFFh
LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset
Table 15-13. Wake-Up Enable Set Registers (WAKEENASETx) Field Descriptions
Bit
95-0
Field
Value
WAKEENASETx[95:0]
Description
Wake-up enable set bits. This vector determines whether the wake-up interrupt line is enabled.
Bit WAKEENASETx[95:0] corresponds to interrupt request channel[95:0].
0
Read: Interrupt request channel is disabled.
Write: A write of 0 has no effect.
1
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Read or Write: The interrupt request channel is enabled.
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15.8.13 Wake-Up Enable Clear Registers (WAKEENACLR[0:2])
The wake-up enable clear registers (WAKEENACLRx) selectively disables individual wake-up interrupt
request lines. Figure 15-32, Figure 15-33, Figure 15-34 and Table 15-14 describe these registers.
Figure 15-32. Wake-Up Enable Clear Register 0 (WAKEENACLR0) [offset = 60h]
31
16
WAKEENACLR0[31:16]
R/WP-FFFFh
15
0
WAKEENACLR0[15:0]
R/WP-FFFFh
LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset
Figure 15-33. Wake-Up Enable Clear Register 1 (WAKEENACLR1) [offset = 64h]
31
16
WAKEENACLR1[63:48]
R/WP-FFFFh
15
0
WAKEENACLR1[47:32]
R/WP-FFFFh
LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset
Figure 15-34. Wake-Up Enable Clear Register 2 (WAKEENACLR2) [offset = 68h]
31
16
WAKEENACLR2[95:80]
R/WP-FFFFh
15
0
WAKEENACLR2[79:64]
R/WP-FFFFh
LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset
Table 15-14. Wake-Up Enable Clear Registers (WAKEENACLRx) Field Descriptions
Bit
95-0
Field
Value
WAKEENACLRx[95:0
]
Description
Wake-up enable clear bits. This vector determines whether the wake-up interrupt line is
enabled. Bit WAKEENACLRx[95:0] corresponds to interrupt request channel[95:0].
0
Read: Wake-up interrupt channel is disabled.
Write: A write of 0 has no effect.
1
Read: The wake-up interrupt channel is enabled.
Write: The wake-up interrupt channel is disabled.
540
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15.8.14 IRQ Interrupt Vector Register (IRQVECREG)
The interrupt vector register gives the address of the enabled and active IRQ interrupt. Figure 15-35 and
Table 15-15 describe these registers.
Figure 15-35. IRQ Interrupt Vector Register (IRQVECREG) [offset = 70h]
31
16
IRQVECREG
R-0
15
0
IRQVECREG
R-0
LEGEND: R = Read only; -n = value after reset
Table 15-15. IRQ Interrupt Vector Register (IRQVECREG) Field Descriptions
Bit
31-0
Field
IRQVECREG
Value
From
Section 15.4
Description
IRQ interrupt vector register. This vector gives the address of the ISR with the highest
pending IRQ request. The CPU reads the address and branches to this location.
Note: A read of register IRQINDEX or IRQVECREG will cause IRQINDEX / IRQVECREG to
reflect the index/ISR address for the next highest-priority pending IRQ interrupt. In case there
is no other interrupt pending, the IRQINDEX will read 0x00 and the IRQVECREG register will
read the phantom interrupt address.
15.8.15 FIQ Interrupt Vector Register (FIQVECREG)
The interrupt vector register gives the address of the enabled and active FIQ interrupt. Figure 15-36 and
Table 15-16 describe these registers.
Figure 15-36. IRQ Interrupt Vector Register (FIQVECREG) [offset = 74h]
31
16
FIQVECREG
R-0
15
0
FIQVECREG
R-0
LEGEND: R = Read only; -n = value after reset; X = Unknown
Table 15-16. FIQ Interrupt Vector Register (FIQVECREG) Field Descriptions
Bit
31-0
Field
FIQVECREG
Value
From
Section 15.4
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Description
FIQ interrupt vector register. This vector gives the address of the ISR with the highest
pending FIQ request. The CPU reads the address and branches to this location.
Note: A read of register FIQINDEX or FIQVECREG will cause FIQINDEX / FIQVECREG to
reflect the index/ISR address for the next highest-priority pending FIQ interrupt. In case there
is no other interrupt pending, the FIQINDEX will read 0x00 and the FIQVECREG register will
read the phantom interrupt address.
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15.8.16 Capture Event Register (CAPEVT)
Figure 15-37 and Table 15-17 describe this register.
Figure 15-37. Capture Event Register (CAPEVT) [offset = 78h]
31
23
22
16
Reserved
CAPEVTSRC1
R-U
R/W-0
15
7
6
0
Reserved
CAPEVTSRC0
R-U
R/W-0
LEGEND: R/W = Read/Write; R = Read only; U = Undefined; -n = value after reset
Table 15-17. Capture Event Register (CAPEVT) Field Descriptions
Bit
Field
31-23
Reserved
22-16
CAPEVTSRC1
Value
0
0
Interrupt request 0.
1h
Interrupt request 1.
5Fh
Reserved
6-0
CAPEVTSRC0
0
:
Interrupt request 95.
Reads are indeterminate and writes have no effect.
Capture event source 0 mapping control. These bits determine which interrupt request maps to the
capture event source 0 of the RTI:
0
Interrupt request 0.
1h
Interrupt request 1.
:
5Fh
542
Reads are indeterminate and writes have no effect.
Capture event source 1 mapping control. These bits determine which interrupt request maps to the
capture event source 1 of the RTI:
:
15-7
Description
:
Interrupt request 95.
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15.8.17 VIM Interrupt Control Registers (CHANCTRL[0:23])
Twenty-four interrupt control registers control the 96 interrupt channels of the VIM. Each register controls
four interrupt channels: each of them is indexed from 0 to 95. Table 15-18 shows the organization of all
the registers and the reset value of each. Each four fields of the register has been named with a generic
index that refers to the detailed register organization. Figure 15-38 and Table 15-19 describe these
registers.
Table 15-18. Interrupt Control Registers Organization
Register Field
31:24
CHANMAPx0
Register Field
23:16
CHANMAPx1
Register Field
15:8
CHANMAPx2
Register Field
7:0
CHANMAPx3
Reset Value
Address
Register
Acronym
FFFF FE80h
CHANCTRL0
CHANMAP0
CHANMAP1
CHANMAP2
CHANMAP3
0001 0203h
FFFF FE84h
CHANCTRL1
CHANMAP4
CHANMAP5
CHANMAP6
CHANMAP7
0405 0607h
:
:
:
:
:
:
:
FFFF FED8h
CHANCTRL22
CHANMAP88
CHANMAP89
CHANMAP90
CHANMAP91
5859 5A5Bh
FFFF FEDCh
CHANCTRL23
CHANMAP92
CHANMAP93
CHANMAP94
CHANMAP95
5C5D 5E5Fh
NOTE: CHANMAP0 and CHANMAP1 are not programable. CHAN0 and CHAN1 are hard wired to
INT_REQ0 and INT_REQ1.
Do NOT write any value other than 0x5F to CHANMAP95. Channel 95 is reserved because
no interrupt vector table entry supports this channel.
Figure 15-38. Interrupt Control Registers (CHANCTRL[0:23])
[offset = 80h-DCh]
31
30
24
23
22
16
Rsvd
CHANMAPx0
Rsvd
CHANMAPx1
R-U
R/W-n
R-U
R/W-n
15
14
8
7
6
0
Rsvd
CHANMAPx2
Rsvd
CHANMAPx3
R-U
R/W-n
R-U
R/W-n
LEGEND: R/W = Read/Write; R = Read only; U = Undefined; -n = value after reset (see Table 15-18)
Table 15-19. Interrupt Control Registers (CHANCTRLx) Field Descriptions
Bit
Field
31
Reserved
30-24
Value
0
CHANMAPx0
Description
Reads are indeterminate and writes have no effect.
CHANMAPx0(6-0). Interrupt CHANx0 mapping control. These bits determine which interrupt request
the priority channel CHANx0 maps to:
0
Read: Interrupt request 0 maps to channel priority CHANx0.
Write: The default value of this bit after reset is given in Table 15-18 . The channel priority CHANx0
is set with the interrupt request.
1h
Read: Interrupt request 1 maps to channel priority CHANx0.
Write: The default value of this bit after reset is given in Table 15-18. The channel priority CHANx0
is set with the interrupt request.
:
5Fh
:
Read: Interrupt request 95 maps to channel priority CHANx0.
Write: The default value of this bit after reset is given in Table 15-18. The channel priority CHANx0
is set with the interrupt request.
23
Reserved
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Reads are indeterminate and writes have no effect.
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Table 15-19. Interrupt Control Registers (CHANCTRLx) Field Descriptions (continued)
Bit
22-16
Field
Value
CHANMAPx1
Description
CHANMAPx1(6-0). Interrupt CHANx1 mapping control. These bits determine which interrupt request
the priority channel CHANx1 maps to:
0
Read: Interrupt request 0 maps to channel priority CHANx1.
Write: The default value of this bit after reset is given in Table 15-18. The channel priority CHANx1
is set with the interrupt request.
1h
Read: Interrupt request 1 maps to channel priority CHANx1.
Write: The default value of this bit after reset is given in Table 15-18. The channel priority CHANx1
is set with the interrupt request.
:
5Fh
:
Read: Interrupt request 95 maps to channel priority CHANx1.
Write: The default value of this bit after reset is given in Table 15-18. The channel priority CHANx1
is set with the interrupt request.
15
14-8
Reserved
0
CHANMAPx2
Reads are indeterminate and writes have no effect.
CHANMAPx2(6-0). Interrupt CHANx2 mapping control. These bits determine which interrupt request
the priority channel CHANx2 maps to:
0
Read: Interrupt request 0 maps to channel priority CHANx2.
Write: The default value of this bit after reset is given in Table 15-18. The channel priority CHANx2
is set with the interrupt request.
1h
Read: Interrupt request 1 maps to channel priority CHANx2.
Write: The default value of this bit after reset is given in Table 15-18. The channel priority CHANx2
is set with the interrupt request.
:
5Fh
:
Read: Interrupt request 95 maps to channel priority CHANx2.
Write: The default value of this bit after reset is given in Table 15-18. The channel priority CHANx2
is set with the interrupt request.
7
6-0
Reserved
0
CHANMAPx3
Reads are indeterminate and writes have no effect.
CHANMAPx3(6-0). Interrupt CHANx3 mapping control. These bits determine which interrupt request
the priority channel CHANx3 maps to:
0
Read: Interrupt request 0 maps to channel priority CHANx3.
Write: The default value of this bit after reset is given in Table 15-18. The channel priority CHANx3
is set with the interrupt request.
1h
Read: Interrupt request 1 maps to channel priority CHANx3.
Write: The default value of this bit after reset is given in Table 15-18. The channel priority CHANx3
is set with the interrupt request.
:
5Fh
:
Read: Interrupt request 95 maps to channel priority CHANx3.
Write: The default value of this bit after reset is given in Table 15-18. The channel priority CHANx3
is set with the interrupt request.
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Chapter 16
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Direct Memory Access Controller (DMA) Module
This chapter describes the direct memory access (DMA) controller.
Topic
16.1
16.2
16.3
...........................................................................................................................
Page
Overview ......................................................................................................... 546
Module Operation ............................................................................................. 547
Control Registers and Control Packets ............................................................... 566
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16.1 Overview
The DMA controller is used to transfer data between two locations in the memory map in the background
of CPU operations. Typically, the DMA is used to:
• Transfer blocks of data between external and internal data memories
• Restructure portions of internal data memory
• Continually service a peripheral
• Page program sections to internal program memory
16.1.1 Main Features
•
•
•
•
•
•
•
•
•
•
•
•
•
CPU independent data transfer
One master port - PortB (64-bits wide) that interfaces microcontrollers Memory System.
FIFO buffer (4 entries deep and each 64-bits wide)
Channel control information is stored in RAM protected by parity
16 channels with individual enable
Channel chaining capability
32 peripheral DMA requests
Hardware and Software DMA requests
8-, 16-, 32-, or 64-bit transactions supported
Multiple addressing modes for source/destination (fixed, increment, offset)
Auto-initiation
Power-management mode
Memory Protection for the address range DMA can access with four configurable memory regions
16.1.1.1 Block Diagram
Figure 16-1 gives a detailed view of the DMA internal architecture. DMA data read and write access
happens through Port B. FIFO B is 4 levels deep and 64-bits wide. 32 DMA requests go into the DMA that
can trigger DMA transfers. Five interrupt request lines go out of the DMA to signal that a certain transfer
status is reached. Register banks hold the memory-mapped DMA configuration registers. Local RAM
consists of DMA control packets and is secured by parity. All the programming / configuration of the DMA
controller is done via the Peripheral bus.
Figure 16-1. DMA Block Diagram
Register Bank
FIFO B
Peripheral Bus
Local RAM (with parity)
32
DMAREQ
5
Port B
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READ Bus
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16.2 Module Operation
The DMA acts as an independent master in the platform architecture. All DMA memory and register
accesses are performed in user mode. If the DMA writes to registers that are only accessible in privileged
mode, the write will not be performed.
The DMA registers and its local RAM can only be accessed in privilege mode. Therefore, it is not possible
for the DMA to reprogram itself.
16.2.1 Memory Space
The DMA controller makes no distinction between program memory and data memory. The DMA
controller can transfer to and from any space within the 4 gigabyte physical address map, by programming
the absolute address for the source and destination in the control packet. Control packets store the
transfer information such as source address, destination address, transfer count and control attributes for
each channel.
16.2.2 DMA Data Access
The DMA controller refers to data in three levels of granularity:
• Element: Depending on the programmed data type, an 8-bit, 16-bit, 32-bit, or a 64-bit value. The type
can be individually selected for the source (read) and destination (write). See Figure 16-2 and
Figure 16-3 for an example of the use of elements. An element transfer cannot be interrupted.
• Frame: One or more elements to be transferred as a unit. A frame transfer can be interrupted between
element transfers. See Figure 16-2 for an example. Use a frame size of one and frame transfer trigger
source for transfers of one element per request.
• Block: One or more frames to be transferred as a unit. Each channel can transfer one block of data
(once or multiple times). See Figure 16-3 for an example.
Figure 16-2. Example of a DMA Transfer Using Frame Trigger Source
Trigger Source = frame transfer triggered by DMA request
Block
Frame 1
Frame 2
Element 1 Element 2
DMAREQ
Element 3 Element 4
DMAREQ
Element Count = 2
Frame count = 4
Frame 4
Frame 3
Element 5 Element 6
DMAREQ
Element 7 Element 8
DMAREQ
Figure 16-3. Example of a DMA Transfer Using Block Trigger Source
Block
Frame 1
Element 1 Element 2
Trigger Source = block transfer triggered by DMA request
Frame 2
Element 3 Element 4
Frame 3
Element Count = 2
Frame count = 4
Frame 4
Element 5 Element 6
Element 7 Element 8
DMAREQ
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16.2.3 Addressing Modes
There are three addressing modes supported by the DMA controller that can be setup independent for the
source and the destination address:
• Constant -- source and/or destination addresses do not change.
• Post incremented -- source and/or destination address are post-incremented by the element size.
• Indexed -- source and/or destination address is post-incremented as defined in the Element Index
Offset Register (Section 16.3.2.5) and the Frame Index Offset Register (Section 16.3.2.6).
An unaligned address with respect to the element size is not supported.
16.2.4 DMA Channel Control Packets
There are a total of 16 control packets. Each control packet is associated with a channel in a fixed order.
For example, control packet 0 stores channel information for channel 0. The DMA requests can be
mapped to the individual channels as described in Section 16.2.7. The mapping scheme between DMA
requests and channels is shown in Figure 16-4. Each control packet contains nine fields. The first six
fields compose the primary control packet and are programmable during DMA setup. The last three fields
compose working control packet and are only readable by the CPU. The working control packets are used
to support auto-initiation. The organization of control packets is shown in Figure 16-5.
The primary control packet contains channel information such as source address, destination address,
transfer count, element/frame offset value and channel configuration. Source address, destination address
and transfer count also have their respective working images. The three fields of working images compose
a working control packet and are not accessible to the CPU in write access.
The first time a DMA channel is selected for a transaction, the following process occurs:
1. The primary control packet is first read by the DMA state machine.
2. Once the channel is arbitrated, the current source address, destination address and transfer count are
then copied to their respective working images.
3. When the channel is serviced again by the DMA, the state machine will read both the primary control
packet and the working control packet to continue the DMA transaction until the end of an entire block
transfer.
When the same channel is requested again, the state machine will start again by reading only the primary
control packet and then continue the same process described above. The user software need not set up
control packets again because the contents of the primary control packet were never lost. The working
images of the control packets are reducing the software overhead and interaction with the DMA module to
a minimum.
NOTE: Changing the contents of a channel control packet will clear the corresponding pending bit
(Section 16.3.1.2) if the channel has a pending status. If the control packet of an active
channel (as indicated in Section 16.3.1.3) is changed, then the channel will stop immediately
at an arbitration boundary. When the same channel is triggered again, it will begin with the
new control packet information.
16.2.4.1 Initial Source Address
This field stores the absolute 32-bit source address of the DMA transfer.
16.2.4.2 Initial Destination Address
This field stores the absolute 32-bit destination address of the DMA transfer.
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Figure 16-4. DMA Request Mapping and Control Packet Organization
CH0ASI(5–0)
CH1ASI(5–0)
Channel Sel0
Control Packet 0
Channel Sel1
Control Packet 1
DMA_REQ[31:0]
CHnASI(5–0)
Channel Sel15
Control Packet 15
Figure 16-5. Control Packet Organization and Memory Map
Base + 0x00
0x10
0x20
0x30
Base + 0XXX0
Base + 0xXXX4
Base + 0xXXX8
Initial Source Address
Channel Configuration
Initial Source Address
Channel Configuration
Initial Destination Address
Element Offset Value
Initial Destination Address
Element Offset Value
Initial Transfer Count
Frame Offset Value
Initial Transfer Count
Frame Offset Value
Base + 0xXXXC
} Primary CP0
} Primary CP1
Reserved
0x1E0
0x1F0
Initial Source Address
Channel Configuration
Reserved
Reserved
Reserved
0x800
0x810
Current Source Address
Current Source Address
Current Destination Address
Current Destination Address
Current Transfer Count
Current Transfer Count
} Working CP0
} Working CP1
0x8F0
Current Source Address
Current Destination Address
Current Transfer Count
} Working CPnn
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Initial Destination Address
Element Offset Value
Initial Transfer Count
Frame Offset Value
} Primary CPnn
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16.2.4.3 Initial Transfer Count
The transfer count field is composed of two parts. The frame transfer count value and the element transfer
count value. Each count value is 13 bits wide. As a Single Block transfer maximum of 512 Mbytes of data
can be transferred. Element count and frame count are programmed according to the source data
structure.
The total transfer size is calculated as:
Tsz = Ersz • Etc • Ftc
(26)
where
Tsz = Total Transfer Size
Ersz = Read Element Size
Etc = Element Transfer Count
Ftc = Frame Transfer Count
NOTE: A zero element count with a non-zero frame count or a non-zero element count with a zero
frame count are all considered as zero total transfer count. No DMA transaction is initiated
with any of the counters set to 0.
16.2.4.4 Channel Configuration Word
The channel configuration defines the following individual parameters
• Read element size
• Write element size
• Trigger type (frame or block)
• Addressing mode for source
• Addressing mode for destination
• Auto-initiation mode
• Next control packet to be triggered at control packet finish (Channel Chaining)
16.2.4.5 Element/Frame Offset Value
There are 4 offset values that allow the creation of different types of buffers in RAM and address registers
in a structured manner: an element offset value for source and destination and a frame offset value for
source and destination.
The element offset value for source and/or destination defines the offset to be added after each element
transfer to the source and/or destination address. The frame offset value for source and/or destination
defines the offset to be added to the source and/or destination address after the element count reaches
zero. The element and frame offset values must be defined in terms of the number of bytes of offset. The
DMA controller does not adjust the element/frame index number according to the element size. An index
of 2 means increment the address by 2 and not by 16 when the element size is 64 bits.
16.2.4.6 Current Source Address
The current source address field contains the current working source address during a DMA transaction.
The current source address is incremented during post increment addressing mode or indexing mode.
16.2.4.7 Current Destination Address
The current destination address field contains the current working destination address during a DMA
transaction. The current destination address is incremented during post-increment addressing mode or
indexing mode.
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16.2.4.8 Current Transfer Count
The current transfer count stores the remaining number of elements to be transferred in a block. It is
decremented by one for each element read from the source location.
Figure 16-6, Figure 16-7, and Figure 16-8 show some examples of DMA transfers.
Figure 16-6. DMA Transfer Example 1
Source
0x00
Destination
f1
f2
f3
f4
E1
E3
E5
E7
0x04
0x0 E1/3/5/7 E2/4/6/8
Dest. Element Index = 1
0x4
Dest. Frame Index = 0
0x08
0x0C
E2
E4
E6
E8
0x0
E1/2
E3/4
E5/6
E7/8
Dest. Element Index = 0
Dest. Frame Index = 1
0x0
E1
E3
E5
E7
Dest. Element Index = 4
0x4
E2
E4
E6
E8
Dest. Frame Index = 1
0x0
E1
E2
E3
E4
Dest. Element Index = 1
0x4
E5
E6
E7
E8
Dest. Frame Index = 2
Source Element Index = 12
Source Frame Index = 1
The example assumes the following setup.
Read Element Size = 8 bit
Write Element Size = 8 bit
Element Count = 2
Frame Count = 4
Figure 16-7. DMA Indexing Example 1
f1
f2
f3
f4
0x0
E1
E5
E9
E13
0x10
E2
E6
E10
E14
0x20
E3
E7
E11
E15
0x30
E4
E8
E12
E16
Element Index = 16
Frame Index = 4
This example can be applied to either source or
destination indexing and assumes the following setup.
Element Size = 16 bit
Element Count = 4
Frame Count = 4
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Figure 16-8. DMA Indexing Example 2
0x0
E1
E4
E7
E10
E13
E16
E19
E22
E2
E5
E8
E11
E14
E17
E20
E23
E3
E6
E9
E12
E15
E18
E21
E23
0x20
0x40
0x60
0x80
Element Index = 64
Frame Index = 4
This example can be applied to either source or
destination indexing and assumes the following setup.
Element Size = 32 bit
Element Count = 3
Frame Count = 8
16.2.5 Priority Queue
User can assign channels in to priority queues to facilitate request handling during arbitration. The port
has two priority queues: a high and a low priority queue. The queue can be configured to follow a fixed or
rotating priority scheme. Fixed priority is such that the lower the channel number (Figure 16-9), the higher
its priority. Rotating priority is based on a round-robin scheme. Initially, the priority list is sorted according
to the fixed priority scheme. Channels assigned to the high priority queue are always serviced first
according to the selected priority scheme before channels in the low priority queue are serviced. Table 161 describes how arbitration is performed according to different priority schemes.
NOTE: Since the DMA controller provides the capability to map any one of the 32 hardware DMA
request lines to any channel, the numerical order of the hardware DMA request does not
imply any priority. The priority of each hardware DMA request is programmed and
determined by software.
Figure 16-9. Fixed Priority Scheme
Priority Queue
Ch0 Ch2 Ch3 Ch4...
Triggered Channels
Control Packet 0
Control Packet 1
Control Packet 2
Control Packet 3
Control Packet 4
Control Packet 5
Control Packet 6
Control Packet 7
Control Packet 8
Control Packet 9
Control Packet 10
Control Packet 11
Control Packet 12
Control Packet 13
Control Packet 14
Control Packet 15
High
ORDER
OF
PRIORITY
Low
The above figure illustrates that by default Lower the channel number, higher the Priority.
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Table 16-1. Arbitration According to Priority Queues and Priority Schemes
Queue
Priority Scheme
Remark
Fixed
Channels are serviced in an ascending order according to the channel number.
The lower the channel number, the higher the priority. A channel will be
arbitrated out whenever there is a higher pending channel. Otherwise a channel
is completely serviced until its transfer count reaches zero before the next
highest pending channel is serviced. When there is no pending channels left in
high queue then the DMA switches to service low queue channels.
Rotating
Channels are arbitrated by using the round-robin scheme. Arbitration is
performed when the FIFO is empty. When there are no pending channels left in
high queue then the DMA switches to service low queue channels.
High priority
Fixed
Low priority
Rotating
Channels are serviced in an ascending order according to the channel number.
The lower the channel number the higher the priority. A channel will be arbitrated
out whenever there is a higher-priority pending channel. Otherwise a channel is
completely serviced until its transfer count reaches zero, before the next highest
pending channel is serviced. If there is a pending channel in the high-priority
queue while DMA is servicing a low queue channel then DMA will switch back to
service high queue channel after an arbitration boundary.
Channels are arbitrated by using round-robin scheme. Arbitration is performed
when the FIFO is empty.
A Simple Priority Queues example in both Fixed and Rotation Scheme is shown in Figure 16-10.
Figure 16-10. Example of Priority Queues
CH1
CH1
in use
CH3
CH7
CH15
CH3
CH3
CH9
in queue
CH13
High
queue
Rotation
CH1
Fixed
CH6
CH6
CH6
CH4
CH8
CH14
CH4
CH4
CH5
CH5
CH10
ininqu
eue n u se
queue
CH2
CH2
i use
in
CH2
Low
queue
CH7
CH7
Pending triggere d
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For optimal system performance, the high priority channels should be put in fixed arbitration scheme and
low priority channels in the rotating priority scheme as illustrated in Figure 16-11.
Figure 16-11. Example Channel Assignments
Port B Priority Queue
high
Ch0 Ch2 Ch3 Ch4
low
Ch8, Ch12
fixed priority
rotational priority
Control Packet 0
Control Packet 1
Control Packet 2
Control Packet 3
Control Packet 4
Control Packet 5
Control Packet 6
Control Packet 7
Control Packet 8
Control Packet 9
Control Packet 10
Control Packet 11
Control Packet 12
Control Packet 13
Control Packet 14
Control Packet 15
1 The above figure illustrates the channel assignments in a system with 16 channels.
This approach can be scaled dependent on the total channels available.
16.2.6 Data Packing and Unpacking
The DMA controller automatically performs the necessary data packing and unpacking when the read
element size differs from the write element size. Data packing is required when the read element size is
smaller than the write element size; data unpacking is required when the read element size is larger than
the write element size. When the read element size is equal to the write element size, no packing is
performed during read, nor is any unpacking performed during write.
Figure 16-12 shows an example of data unpacking in which the DMA is used to transfer 128 transmit data
elements to the MibSPI FIFO buffer. In this example, data unpacking is required because the read
element size is 64 while the write element size is 16. The DMA first performs an 64-bit read from the
source into its FIFO buffer. After the 64-bit data is read into the DMA FIFO buffer, it must unpack the data
into four 16-bit data elements before writing out to the destination. Therefore the DMA would need to
perform four 16-bit write operations to the destination.
NOTE: In the example in Figure 16-12, to transmit data at the lower bits of the MibSPI, bits 15:0, the
destination address should be incremented by a factor of 2.
NOTE: 1) The element Count (Section 16.3.2.3) refers only to the read element.
2) Data unpacking does not require the DMA request. Once the DMA request is received,
data from Source is moved in to FIFO and unpacking happens until the FIFO is empty.
3) DMA assumes the destination is always ready and will perform write immediately. In case
of data unpacking and Constant Addressing Mode write (Section 16.3.2.4 (1 - 0) = 0) the
destination data will be overwritten by next data or next data might be skipped in case the
destination has overflow protection (eg., SCITD register). User should configure DMA to
avoid data unpacking if the Destination is configured as Constant Addressing Mode write to
avoid data loss.
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Figure 16-12. Example of DMA Data Unpacking
63
0
31
1615
0x0 Control 0
0x4
E124
E125
E126
Control 1
0
Transmit buf 0
E0
Transmit buf 1
E1
E127
Control 127
0x8
E4
E5
E6
E7
0x0
E0
E1
E2
E3
Transmit buf 127
E127
Status 0
Receive buf 0
Status 1
Receive buf 1
64-bit memory organization
0x400 Status 127
Receive buf 127
MIBSPI FIFO organization
In this example, initialization of the MIBSPI FIFO is illustrated and assumes the following setup:
Read Element Size = 64 bit
Write Element Size = 16 bit
Element Count = 32
Frame Count = 1
Source Element Index = n/a, use post increment addressing mode
Source Frame Index = n/a, use post increment addressing mode
Destination Element Index = 4
Destination Frame Index = 0
When the read element size is smaller than the write element size, the DMA controller needs to perform
data packing. The number of elements to pack is equal to the ratio between the write element size and
read element size. In the example in Figure 16-13, the read element size is 16 bits and the write element
size is 64 bits. The DMA controller would first pack the first four elements by performing four consecutive
16-bit read accesses of E0, E1, E2, and E3 into the first word of the DMA's internal FIFO. The DMA
controller would then perform one single 64-bit write operation to transfer the data to the 64-bit destination
memory.
Normally, the DMA controller carries out bus transactions on the bus according to the element size. For
example, the DMA controller would perform a 16-bit read transaction if the read element size is
programmed as 16 bits, or an 8-bit write transaction if the write element size is programmed as 8 bit. The
exception is when the total transfer size is as defined in Equation 26 is not a multiple of the write element
size.
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Figure 16-13. Example of DMA Data Packing
31
1615
0x0 Control 0
Transmit buf 0
Control 1
Transmit buf 1
0x4
0
63
0
E126
Control 127
Status 0
Status 1
E127
E124
E125
Transmit buf 127
Receive buf 0
E0
Receive buf 1
E1
0x8
E6
E7
E4
E5
0x0
E2
E3
E0
E1
64-bit memory organization
Receive buf 127
E127
MIBSPI FIFO organization
0x400 Status 127
In this example, a read of the MIBSPI FIFO is illustrated and assumes the following setup:
Read Element Size = 16 bit
Write Element Size = 64 bit
Element Count = 128
Frame Count = 1
Source Element Index = 4
Source Frame Index = 0
Destination Element Index = n/a, use post increment addressing mode
Destination Frame Index = n/a, use post increment addressing mode
For example, if the read element size is 8 bits, the element transfer count is equal to 9, and the write
element size is 64 bit. The DMA controller would first perform eight 8-bit read transactions from the
source. It would then perform a 64-bit write to the destination. When the same channel wins arbitration
again, the DMA controller would first perform one 8-bit read from the source, followed by one 8-bit write to
the destination, even though the write element size is 64 bit.
NOTE: Since peripherals are slower, it is advised to use data packing feature with caution for
reading data from peripherals. Improper use might delay servicing other pending DMA
channels.
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16.2.7 DMA Request
There are three ways to start a DMA transfer:
• Software request: The transfer will be triggered by writing to SW Channel Enable Set and Status
Register (Section 16.3.1.6). The software request can trigger either a block or a frame transfer
depending on the setting of the TTYPE bit in the Channel Control Register (Section 16.3.2.4).
• Hardware request: The DMA controller can handle up to 32 DMA Request lines. A hardware request
can trigger either a frame or a block transfer depending on the setting of the TTYPE bit in the Channel
Control Register (Section 16.3.2.4).
• Triggered by other control packet: When a control packet finishes the programmed number of
transfers it can trigger another channel to initiate its transfers.
Each time a DMA request is made, either one frame transfer or one block transfer can be chosen. An
active DMA request signal will trigger a DMA transaction.
The DMA controller has a two-level buffer to capture HW requests per channel. When a HW request is
generated and the channel is enabled, the corresponding bit in the DMA Status Register
(Section 16.3.1.3) is set. The pending register acts as a first-level buffer. Typically, a peripheral acting as a
source of a transfer would initiate another request after its data registers have been read out by DMA,
even though that data has not been completely transferred to the destination. If a second HW request is
generated by the peripheral, the DMA controller has an extra request buffer to capture this second request
and service it after the first request is complete.
NOTE: The DMA cannot capture more than three requests if its request buffers are already full. If
any request occur during this moment DMA will discard it.
The DMA controller also supports a mix of hardware and software requests on the same channel. Note
that such interchangeable usage may result into an out of sync for DMA channel and peripheral. The
application needs to be careful as the DMA does not have a built-in mechanism to protect against this loss
of synchronization.
If a software request is generated, the corresponding bit in the Channel Pending Register
(Section 16.3.1.2) is set accordingly. If the pending request is not completely serviced by the DMA and a
hardware request is generated by a peripheral onto the same channel, the DMA will capture and
recognize this hardware request into its request buffer.
NOTE: The DMA controller cannot recognize two software requests on the same channel if the first
software request is still pending. If such request occur DMA will discard it. Therefore the user
software should check the pending register before issuing a new software request.
The DMA module has 16 channels and up to 32 hardware DMA requests. The module contains
DREQASIx registers that are used to map the DMA requests to the DMA channels. By default, channel 0
is mapped to request 0, channel 1 to request 1, and so on.
Some DMA requests have multiple sources, as shown in Table 16-2. The application must ensure that
only one of these DMA request sources is enabled at any time.
Table 16-2. DMA Request Line Connection
(1)
(2)
Modules
DMA Request Sources
DMA Request
MIBSPI1
MIBSPI1[1] (1)
DMAREQ[0]
MIBSPI1
MIBSPI1[0] (2)
DMAREQ[1]
SPI2
SPI2 receive
DMAREQ[2]
SPI2
SPI2 transmit
DMAREQ[3]
MIBSPI1 / MIBSPI3 / DCAN2
MIBSPI1[2] / MIBSPI3[2] / DCAN2 IF3
DMAREQ[4]
MIBSPI1 / MIBSPI3 / DCAN2
MIBSPI1[3] / MIBSPI3[3] / DCAN2 IF2
DMAREQ[5]
DCAN1 / MIBSPI5
DCAN1 IF2 / MIBSPI5[2]
DMAREQ[6]
SPI1, SPI3, SPI5 receive in standard SPI mode
SPI1, SPI3, SPI5 transmit in standard SPI mode
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Table 16-2. DMA Request Line Connection (continued)
Modules
DMA Request Sources
DMA Request
MIBADC1 / MIBSPI5
MIBADC1 event / MIBSPI5[3]
DMAREQ[7]
MIBSPI1 / MIBSPI3 / DCAN1
MIBSPI1[4] / MIBSPI3[4] / DCAN1 IF1
DMAREQ[8]
MIBSPI1 / MIBSPI3 / DCAN2
MIBSPI1[5] / MIBSPI3[5] / DCAN2 IF1
DMAREQ[9]
MIBADC1 / I2C / MIBSPI5
MIBADC1 G1 / I2C receive / MIBSPI5[4]
DMAREQ[10]
MIBADC1 / I2C / MIBSPI5
MIBADC1 G2 / I2C transmit / MIBSPI5[5]
DMAREQ[11]
RTI / MIBSPI1 / MIBSPI3
RTI DMAREQ0 / MIBSPI1[6] / MIBSPI3[6]
DMAREQ[12]
RTI / MIBSPI1 / MIBSPI3
RTI DMAREQ1 / MIBSPI1[7] / MIBSPI3[7]
DMAREQ[13]
MIBSPI3 / MibADC2 / MIBSPI5
MIBSPI3[1] (1) / MibADC2 event / MIBSPI5[6]
DMAREQ[14]
MIBSPI3 / MIBSPI5
(3)
(4)
558
MIBSPI3[0]
(2)
/ MIBSPI5[7]
DMAREQ[15]
MIBSPI1 / MIBSPI3 / DCAN1 / MibADC2
MIBSPI1[8] / MIBSPI3[8] / DCAN1 IF3 / MibADC2
G1
DMAREQ[16]
MIBSPI1 / MIBSPI3 / DCAN3 / MibADC2
MIBSPI1[9] / MIBSPI3[9] / DCAN3 IF1 / MibADC2
G2
DMAREQ[17]
RTI / MIBSPI5
RTI DMAREQ2 / MIBSPI5[8]
DMAREQ[18]
RTI / MIBSPI5
RTI DMAREQ3 / MIBSPI5[9]
DMAREQ[19]
N2HET1 / N2HET2 / DCAN3
N2HET1 DMAREQ[4] / N2HET2 DMAREQ[4] /
DCAN3 IF2
DMAREQ[20]
N2HET1 / N2HET2 / DCAN3
N2HET1 DMAREQ[5] / N2HET2 DMAREQ[5] /
DCAN3 IF3
DMAREQ[21]
MIBSPI1 / MIBSPI3 / MIBSPI5
MIBSPI1[10] / MIBSPI3[10] / MIBSPI5[10]
DMAREQ[22]
MIBSPI1 / MIBSPI3 / MIBSPI5
MIBSPI1[11] / MIBSPI3[11] / MIBSPI5[11]
DMAREQ[23]
N2HET1 / N2HET2 / SPI4 / MIBSPI5
N2HET1 DMAREQ[6] / N2HET2 DMAREQ[6] /
SPI4 receive / MIBSPI5[12]
DMAREQ[24]
N2HET1 / N2HET2 / SPI4 / MIBSPI5
N2HET1 DMAREQ[7] / N2HET2 DMAREQ[7] /
SPI4 transmit / MIBSPI5[13]
DMAREQ[25]
CRC / MIBSPI1 / MIBSPI3
CRC DMAREQ[0] / MIBSPI1[12] / MIBSPI3[12]
DMAREQ[26]
CRC / MIBSPI1 / MIBSPI3
CRC DMAREQ[1] / MIBSPI1[13] / MIBSPI3[13]
DMAREQ[27]
LIN / MIBSPI5
LIN receive / MIBSPI5[14]
DMAREQ[28]
LIN / MIBSPI5
LIN transmit / MIBSPI5[15]
DMAREQ[29]
MIBSPI1 / MIBSPI3 / SCI / MIBSPI5
MIBSPI1[14] / MIBSPI3[14] / SCI receive /
MIBSPI5[1] (3)
DMAREQ[30]
MIBSPI1 / MIBSPI3 / SCI / MIBSPI5
MIBSPI1[15] / MIBSPI3[15] / SCI transmit /
MIBSPI5[0] (4)
DMAREQ[31]
SPI1, SPI3, SPI5 receive in standard SPI mode
SPI1, SPI3, SPI5 transmit in standard SPI mode
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16.2.8 Auto-Initiation
When Auto-initiation Mode (AIM) bit of Channel Control Register (Section 16.3.2.4) is enabled for a
channel and the channel is triggered by a software request for a block transfer, the channel will restart
again using the same channel information stored at the respective control packet after one block transfer
is completed. In the case of Hardware Request, the channel needs to be retriggered each time after a
block is complete even if auto-initiation is enabled.
16.2.9 Interrupts
Each channel can be configured to generate interrupts on several transfer conditions:
• Frame transfer complete (FTC) interrupt: an interrupt is issued after the last element of a frame has
been transferred.
• Last frame transfer started (LFS) interrupt: an interrupt is issued before the first element of the last
frame of a block transfer has started.
• First half of block complete (HBC) interrupt: an interrupt is issued if more than half of the block is
transferred.
– If the number of frames n is odd, then the HBC interrupt is generated at the end of the frame when
(n+1) / 2 number of frames are left in the block.
– If the number of frames n is even, then the HBC interrupt is generated at the end of the frame after
n/2 number of frames are left in the block.
• Block transfer complete (BTC) interrupt: an interrupt is issued after the last element of the last frame
has been transferred.
• External imprecise error on read: an interrupt can be issued when a bus error (Illegal transaction with
ok response) is detected. The imprecise read error is connected to the ESM module.
• External imprecise error on write: an interrupt can be issued when a bus error (Illegal transaction with
ok response) is detected. The imprecise write error is connected to the ESM module.
• Memory Protection Unit error (MPU): an interrupt is issued when the DMA detects that the access falls
outside of a memory region programmed in the MPU registers of the DMA. The MPU interrupt is
connected to the ESM module.
• Parity error (PAR): an interrupt is issued when the DMA detects a parity error when reading one of the
control packets. The PAR interrupt is connected to the ESM module.
The DMA outputs 5 interrupt lines for control packet handling, a parity interrupt and a memory protection
interrupt (Figure 16-14). Each type of transfer interrupt condition is grouped together. For example, all
block-transfer complete interrupts that are routed to a port are combined (ORed). The channel that caused
the interrupt is given in the corresponding interrupt channel offset register. Priority between interrupts
among the same interrupt type is resolved by a fixed priority scheme. Priority between different interrupt
types is resolved in the Vector Interrupt Manager. Figure 16-15 explains the Frame Transfer Complete
Interrupt structure in detail.
NOTE: Each Channel Specific interrupts in DMA module are routed towards Group A or B to
support two different CPUs individually. For devices with Single CPU or Dual CPU where
both CPUs are running same code in delayed lock-step as safety feature:
Group A - Interrupts (FTC, LFS, HBC, and BTC) are routed to the ARM CPU.
Group B - Interrupts (FTC, LFS, HBC, and BTC) are not routed out.
User software should configure only Group A interrupts.
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Figure 16-14. DMA Interrupts
DMA
FTCA
CHANNEL
SPECIFIC
INTERRUPT
G
R
O
U
P
LFSA
HBCA
BTCA
VECTOR
INTERRUPT
MODULE
(VIM)
A
S
C
R
CPU
High
PARITY
ERROR
PAR
MPU
ERROR
MPU
Low
ERROR
SIGNALING
MODULE
(ESM)
DMA/DMM imprecise read error Group 1.5
DMA/DMM imprecise write error Group 1.13
Figure 16-15. Detailed Interrupt Structure (Frame Transfer Complete Path)
Frame Transfer
Complete Ch0
•••
•••
•••
FTC0AB
FTCA
Frame Transfer
Complete Ch31
FTC31AB
This figure is applicable for the HBC, LFS, and BTC interrupt.
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16.2.10 Debugging
The DMA supports four different behaviors in suspend mode. These behaviors can be configured by the
user as per the application requirement.
• Immediate stop at a DMA channel arbitration boundary. Please refer to Table 16-3 and Table 16-4 for
arbitration boundary definition.
• Finish current frame transfer and continue after suspend ends.
• Finish current block transfer and continue after suspend ends.
• Ignore the suspend. The DMA continues to be operational as in functional mode when debug mode is
active.
When the DMA controller enters suspend mode, it continues to sample incoming hardware DMA requests,
but the Channel Pending Register (Section 16.3.1.2) is frozen from being updated. After the suspend
ends, all new requests that were received during suspend mode are reflected in the Channel Pending
Register (Section 16.3.1.2).
Except when the DMA controller is configured to ignore suspend mode, no channel arbitration is
performed during suspend mode. The current channel under which suspend mode was entered will finish
its entire frame or block-transfer after suspend mode ends, depending how the debug option was chosen.
To facilitate debugging, a Watch Point Register (Section 16.3.1.47) and a Watch Mask Register
(Section 16.3.1.48) are used. The watch point register together with the watch mask register can be
configured to watch for a unique address or a range of addresses. When the condition to watch is true, the
DMA freezes its state and generates a debug request signal to the host CPU so the state of the DMA can
be examined.
16.2.11 Power Management
The DMA offers two power-management modes: run and sleep. In run mode, the DMA is fully operational.
The sleep mode shuts down the DMA if no pending channels are waiting to be serviced. If a DMA request
is received or a software request is generated by the user software, then the DMA wakes up immediately.
The sleep mode may be used to optimize the DMA module power consumption.
When the system module issues a global low power mode request, the DMA will respond to the system
module with an acknowledge if no DMA requests are pending.
NOTE: When the DMA is in global low power mode, the clock is stopped and therefore it cannot
detect any DMA request. The device must be woken up before a peripheral can generate a
DMA request.
16.2.12 FIFO Buffer
DMA FIFO is 4 levels deep and 64-bit wide (can hold up to 4 x 64-bits of data). They are used for Data
packing and unpacking.
The DMA FIFO has two states:
• EMPTY : The FIFO contains no data.
• FULL : The FIFO is filled or the element count has reached zero; the read operation has to be stopped.
DMA channels can only be switched when the FIFO is empty. This also implies that arbitration between
channels is done when the FIFO is empty.
The FIFO buffer may be bypassed through the use of the bypass feature in the port control register; see
Port Control Register (Section 16.3.1.44) for register details. Writing 1 to this bit limits the FIFO depth to
the size of one element. That means if the read element size is equal to or larger than the write element
size, after one element is read the write out to the destination starts. Otherwise, the write out to the
destination starts after enough reads have completed to do one write of the write element size. This
feature is particularly useful to minimize switching latency in-between channels. When bypass mode is
enabled, the DMA performs minimal bus cycles on AHB bus. In addition, the bypass feature allows
arbitration between channels that can be carried out at a source element granularity.
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However, it has to be considered that while in bypass mode, the DMA controller does not make optimal
use of the bus bandwidth. Since the read and write element sizes can be different, then the number of
read and write transactions will be different. Table 16-3 and Table 16-4 show a comparison between the
number of read and write transactions performed by the DMA controller from one channel to another
before arbitration in non-bypass and bypass mode.
Table 16-3. Maximum Number of DMA Transactions per Channel in Non-Bypass Mode
Write
Element
Size
Read
Element
Size
8 bit
16 bit
32 bit
64 bit
8 bit
4 read
4 write
4 read
2 write
4 read
1 write
8 read
1 write
16 bit
2 read
4 write
4 read
4 write
4 read
2 write
4 read
1 write
32 bit
1 read
4 write
2 read
4 write
4 read
4 write
4 read
2 write
64 bit
1 read
8 write
1 read
4 write
2 read
4 write
4 read
4 write
Table 16-4. Maximum Number of DMA Transactions per Channel in Bypass Mode
Write
Element
Size
Read
Element
Size
8 bit
16 bit
32 bit
64 bit
8 bit
1 read
1 write
2 read
1 write
4 read
1 write
8 read
1 write
16 bit
1 read
2 write
1 read
1 write
2 read
1 write
4 read
1 write
32 bit
1 read
4 write
1 read
2 write
1 read
1 write
2 read
1 write
64 bit
1 read
8 write
1 read
4 write
1 read
2 write
1 read
1 write
16.2.13 Channel Chaining
Channel chaining is used to trigger a single or multiple channels with out an external DMA request. This is
possible by chaining one control packet to other. Chain[5:0] field of the Channel Control Register
(Section 16.3.2.4) is used to program the chaining control packet. Chained control packets follow
arbitration rules within the pending register. For example if CH1, CH2, CH4, CH5 are triggered together
and CH3 is chained with CH1. The order of channels serviced in spite of chaining will be CH1 -> CH2 ->
CH3 -> CH4 -> CH5.
In order to setup up channel chain feature, the Channel Control Register (Section 16.3.2.4) needs to be
enabled for all chained channels before triggering first DMA request.
Figure 16-16 illustrates how internally chained request is generated after completing the required transfers
and stored in pending register. In this example CH1 is Chained to CH0. When CH0 is triggered CH1 is
captured as pending in the Channel Pending Register (Section 16.3.1.2) even when it is not triggered.
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Figure 16-16. Example of Channel Chaining
Ch chain0
Pending
Register
CH1ASI[5:0]
Ch Sel0
0
Bit 0
0
Bit 1
Ch chain1
CH1ASI[5:0]
Ch Sel1
Bit 2
DMA_REQ[31:0]
Ch chain14
CH14ASI[5:0]
Ch Sel14
0
Bit 14
0
Bit 15
Ch chain15
CH15ASI[5:0]
Ch Sel15
16.2.14 Memory Protection
The DMA controller is capable of access to the full address range of the device. The protection
mechanism allows the protection of up to four memory regions to restrict accesses to those address
ranges. This will allow the application to protect critical application data from unintentionally being
accessed by the DMA controller.
16.2.14.1 Protection Mechanism
The memory protection mechanism consists of the access privilege for a given memory region, the start
and end address for the region, and notification of an access violation for the protected region.
Each region to be protected is configured by software by writing the start address and end address for
each region into the DMA Memory Protection Registers, DMAMPRxS and DMAMPRxE. The definition of
these registers can be found starting at Section 16.3.1.54. Any region in the valid address space can be
protected from inappropriate accesses.
The access privileges can be set to one of four permission settings:
• Full access
• Read only access
• Write only access
• No access
The permissions for a given region are selected by writing the appropriate values in the DMA Memory
Protection Control Register (Section 16.3.1.54).
NOTE: If the regions defined by the start and end addresses overlap, the region defined first in the
register space determines the access privilege. For example, if region 0 and region 1
overlap, the access permissions defined for region 0 will take precedence since region 0
registers are before region 1.
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In a case where a memory protection violation occurs, a flag will be set and an interrupt will be generated,
if interrupts are enabled. The DMA Memory Protection Status Register (Section 16.3.1.55) contains the
status flags for the memory protection mechanism, and the DMA Memory Protection Control Register
(Section 16.3.1.54) contains the interrupt enable bits. Upon detection of the memory protection violation,
the DMA Channel that caused the violation will be stopped and the next available DMA channel will be
serviced.
Figure 16-17 Illustrates a protection mechanism.
Figure 16-17. Example of Protection Mechanism
0xFFFFFFFF
Region3
System + peripherals
Region2
0xFFF78000
No access restrictions
Access restrictions
0x08003FFF
Region1
RAM
Region0
0x08000000
0x00000000
16.2.15 Parity Checking
Parity checking is implemented using parity on a per-byte basis for DMA Control Packets in the RAM.
Checking for even or odd parity can be programmed by a 4-bit key located in the system module that
controls the parity configuration on a global basis. This ensures that all modules using parity are acting in
the same manner. The default setup after reset is odd parity.
In addition, parity checking can be enabled and disabled within the module by a 4-bit key. The key is
located in the Parity Control Register (Section 16.3.1.52).
During a read access, regardless if it was read by the DMA state machine or another master (CPU), the
parity is calculated based on the data read from the RAM and compared with the good parity value stored
in the parity bits. If any word fails the parity check, then a parity error interrupt is generated. The address
that generated the error is detected and is captured for host system debugging in the DMA Parity Error
Address Register (Section 16.3.1.53). The address is frozen from being updated until it is read by the bus
master.
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Additional error handling is dependent on the requestor.
• DMA reading from a control packet RAM: The transmission requested by DMA request will not take
place.
• CPU reading from the control packet RAM: The data will be retrieved by the CPU and a parity error
interrupt will be generated.
In both cases, the control packet will be left active or the DMA will be switched off dependent on the
ERRA bit in the Parity Control Register (Section 16.3.1.52).
16.2.16 Parity Testing
The parity RAM is accessible to allow manually inserting faults so that the parity checking feature can be
tested. Test mode is entered by asserting the TEST bit in the Parity Control Register (Section 16.3.1.52).
Once the bit is set, the parity bits are mapped to the control packet RAM starting address A00h.
NOTE: When in test mode, no parity checking will be done when reading from parity memory, but
parity checking will be performed on the normal memory.
Each byte in Control Packet RAM has its own parity bit in the Control Packet Parity RAM as shown in
Table 16-5, Table 16-6, and Table 16-7. P0 is the parity bit for byte 0, P1 is the parity bit for byte 1 and so
on.
Each byte in the control packet RAM has its own parity bit in the control packet parity RAM as shown in
Table 16-5 and Table 16-6.
Table 16-5. Control Packet RAM
Bit
31
24
23
16
15
8
7
0
Word0
Byte 0
Byte 1
Byte 2
Byte 3
Word1
Byte 4
Byte 5
Byte 6
Byte 7
Word2
Byte 8
Byte 9
Byte 10
Byte 11
Word3
Byte 12
Byte 13
Byte 14
Byte 15
Table 16-6. Control Packet RAM
Bit
127
96
95
Word 3
64
63
32
Word 2
31
Word 1
0
Word 0
Table 16-7. Parity RAM
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
P15
P14
P13
P12
P11
P10
P9
P8
P7
P6
P5
P4
P3
P2
P1
P0
16.2.17 Initializing RAM with Parity
After power up, the RAM content including the parity bit cannot be guaranteed. To avoid parity failures
when reading RAM, the RAM has to be initialized. The RAM can be initialized by writing known values into
it. When the known value is written, the corresponding parity bit will be automatically calculated and
updated.
Another possibility to initialize the memory is to follow the Auto-Initialization of On-Chip SRAM Modules
subsection in the Architecture chapter. The RAM will be initialized to 0. Depending on the even/odd parity
selection, the parity bit will be calculated accordingly.
To allow for parity calculation during initialization, the parity functionality has to be enabled as discussed in
Section 16.2.15.
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16.3 Control Registers and Control Packets
The DMA control registers are summarized in Table 16-8. The base address for the control registers is
FFFF F000h. The control packets are summarized in Table 16-9. The base address for the control
packets is FFF8 0000h. Each register begins on a word boundary. All registers and control packets are
accessible in 8, 16, and 32 bit.
NOTE: The register definitions are given for a full DMA module configuration (32 channels,
64 requests, 2 Ports, Dual CPU support). Writes and Reads of bits pertaining to features not
included in the DMA implementation as defined in the device-specific data manual are
possible without error; however, they will have no affect on device operation.
Table 16-8. DMA Control Registers
Offset
Acronym
Register Description
Section
00h
GCTRL
Global Control Register
Section 16.3.1.1
04h
PEND
Channel Pending Register
Section 16.3.1.2
0Ch
DMASTAT
DMA Status Register
Section 16.3.1.3
14h
HWCHENAS
HW Channel Enable Set and Status Register
Section 16.3.1.4
1Ch
HWCHENAR
HW Channel Enable Reset and Status Register
Section 16.3.1.5
24h
SWCHENAS
SW Channel Enable Set and Status Register
Section 16.3.1.6
2Ch
SWCHENAR
SW Channel Enable Reset and Status Register
Section 16.3.1.7
Section 16.3.1.8
34h
CHPRIOS
Channel Priority Set Register
3Ch
CHPRIOR
Channel Priority Reset Register
Section 16.3.1.9
44h
GCHIENAS
Global Channel Interrupt Enable Set Register
Section 16.3.1.10
4Ch
GCHIENAR
Global Channel Interrupt Enable Reset Register
Section 16.3.1.11
54h
DREQASI0
DMA Request Assignment Register 0
Section 16.3.1.12
58h
DREQASI1
DMA Request Assignment Register 1
Section 16.3.1.13
5Ch
DREQASI2
DMA Request Assignment Register 2
Section 16.3.1.14
60h
DREQASI3
DMA Request Assignment Register 3
Section 16.3.1.15
94h
PAR0
Port Assignment Register 0
Section 16.3.1.16
98h
PAR1
Port Assignment Register 1
Section 16.3.1.17
B4h
FTCMAP
FTC Interrupt Mapping Register
Section 16.3.1.18
BCh
LFSMAP
LFS Interrupt Mapping Register
Section 16.3.1.19
C4h
HBCMAP
HBC Interrupt Mapping Register
Section 16.3.1.20
CCh
BTCMAP
BTC Interrupt Mapping Register
Section 16.3.1.21
DCh
FTCINTENAS
FTC Interrupt Enable Set Register
Section 16.3.1.22
E4h
FTCINTENAR
FTC Interrupt Enable Reset Register
Section 16.3.1.23
ECh
LFSINTENAS
LFS Interrupt Enable Set Register
Section 16.3.1.24
F4h
LFSINTENAR
LFS Interrupt Enable Reset Register
Section 16.3.1.25
FCh
HBCINTENAS
HBC Interrupt Enable Set Register
Section 16.3.1.26
104h
HBCINTENAR
HBC Interrupt Enable Reset Register
Section 16.3.1.27
10Ch
BTCINTENAS
BTC Interrupt Enable Set Register
Section 16.3.1.28
114h
BTCINTENAR
BTC Interrupt Enable Reset Register
Section 16.3.1.29
11Ch
GINTFLAG
Global Interrupt Flag Register
Section 16.3.1.30
124h
FTCFLAG
FTC Interrupt Flag Register
Section 16.3.1.31
12Ch
LFSFLAG
LFS Interrupt Flag Register
Section 16.3.1.32
134h
HBCFLAG
HBC Interrupt Flag Register
Section 16.3.1.33
13Ch
BTCFLAG
BTC Interrupt Flag Register
Section 16.3.1.34
144h
BERFLAG
BER Interrupt Flag Register
Section 16.3.1.35
14Ch
FTCAOFFSET
FTCA Interrupt Channel Offset Register
Section 16.3.1.36
150h
LFSAOFFSET
LFSA Interrupt Channel Offset Register
Section 16.3.1.37
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Table 16-8. DMA Control Registers (continued)
Offset
Acronym
Register Description
154h
HBCAOFFSET
HBCA Interrupt Channel Offset Register
Section 16.3.1.38
Section
158h
BTCAOFFSET
BTCA Interrupt Channel Offset Register
Section 16.3.1.39
160h
FTCBOFFSET
FTCB Interrupt Channel Offset Register
Section 16.3.1.40
164h
LFSBOFFSET
LFSB Interrupt Channel Offset Register
Section 16.3.1.41
168h
HBCBOFFSET
HBCB Interrupt Channel Offset Register
Section 16.3.1.42
16Ch
BTCBOFFSET
BTCB Interrupt Channel Offset Register
Section 16.3.1.43
178h
PTCRL
Port Control Register
Section 16.3.1.44
17Ch
RTCTRL
RAM Test Control Register
Section 16.3.1.45
180h
DCTRL
Debug Control Register
Section 16.3.1.46
184h
WPR
Watch Point Register
Section 16.3.1.47
188h
WMR
Watch Mask Register
Section 16.3.1.48
198h
PBACSADDR
Port B Active Channel Source Address Register
Section 16.3.1.49
19Ch
PBACDADDR
Port B Active Channel Destination Address Register
Section 16.3.1.50
1A0h
PBACTC
Port B Active Channel Transfer Count Register
Section 16.3.1.51
1A8h
DMAPCR
Parity Control Register
Section 16.3.1.52
1ACh
DMAPAR
DMA Parity Error Address Register
Section 16.3.1.53
1B0h
DMAMPCTRL
DMA Memory Protection Control Register
Section 16.3.1.54
1B4h
DMAMPST
DMA Memory Protection Status Register
Section 16.3.1.55
1B8h
DMAMPR0S
DMA Memory Protection Region 0 Start Address Register
Section 16.3.1.56
1BCh
DMAMPR0E
DMA Memory Protection Region 0 End Address Register
Section 16.3.1.57
1C0h
DMAMPR1S
DMA Memory Protection Region 1 Start Address Register
Section 16.3.1.58
1C4h
DMAMPR1E
DMA Memory Protection Region 1 End Address Register
Section 16.3.1.59
1C8h
DMAMPR2S
DMA Memory Protection Region 2 Start Address Register
Section 16.3.1.60
1CCh
DMAMPR2E
DMA Memory Protection Region 2 End Address Register
Section 16.3.1.61
1D0h
DMAMPR3S
DMA Memory Protection Region 3 Start Address Register
Section 16.3.1.62
1D4h
DMAMPR3E
DMA Memory Protection Region 3 End Address Register
Section 16.3.1.63
Table 16-9. Control Packet Memory Map
Offset
Acronym
Register Description
Section
Primary Control Packet 0
00h
ISADDR
Initial Source Address Register
Section 16.3.2.1
04h
IDADDR
Initial Destination Address Register
Section 16.3.2.2
08h
ITCOUNT
Initial Transfer Count Register
Section 16.3.2.3
10h
CHCTRL
Channel Control Register
Section 16.3.2.4
14h
EIOFF
Element Index Offset Register
Section 16.3.2.5
18h
FIOFF
Frame Index Offset Register
Section 16.3.2.6
Working Control Packet 0
800h
CSADDR
Current Source Address Register
Section 16.3.2.7
804h
CDADDR
Current Destination Address Register
Section 16.3.2.8
808h
CTCOUNT
Current Transfer Count Register
Section 16.3.2.9
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16.3.1 Global Configuration Registers
These registers control the overall behavior of the DMA controller.
16.3.1.1 Global Control Register (GCTRL)
Figure 16-18. Global Control Register (GCTRL) [offset = 00]
31
17
16
Reserved
DMA_EN
R-0
R/WP-0
15
14
Reserved
BUS_BUSY
13
Reserved
10
DEBUG_MODE
R-0
R-0
R-0
R/WP-0
7
9
8
1
0
Reserved
DMA_RES
R-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 16-10. Global Control Register (GCTRL) Field Descriptions
Bit
Field
31-17
Reserved
16
DMA_EN
15
Reserved
14
BUS_BUSY
13-10
9-8
Reserved
Value
0
Reserved
0
DMA_RES
Reads return 0. Writes have no effect.
DMA enable bit. The configuration registers and channel control packets should be setup first
before DMA_EN bit is set to 1 to prevent state machines from carrying out bus transactions. If
DMA_EN bit is cleared in the middle of an bus transaction, the state machine will stop at an
arbitration boundary.
0
The DMA is disabled.
1
The DMA is enabled.
0
Reads return 0. Writes have no effect.
This bit indicates status of DMA external AHB bus status.
0
DMAs external bus is not busy in data transfers.
1
DMAs external bus is busy in data transfers.
0
Reads return 0. Writes have no effect.
DEBUG_MODE
7-1
Description
Debug Mode.
0
Ignore suspend.
1h
Finish current block transfer.
2h
Finish current frame transfer.
3h
Immediately stop at an DMA arbitration boundary and continue after suspend.
0
Reads return 0. Writes have no effect.
DMA software reset
Note: In the event a DMA slave does not respond, the DMA module will respond to the
software reset upon reaching an arbitration boundary.
0
Read: Software reset is disabled.
Write: No effect.
1
568
Read and write: The DMA state machine and all control registers are in software reset. Control
packets are not reset when DMA software reset is active.
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16.3.1.2 Channel Pending Register (PEND)
Figure 16-19. Channel Pending Register (PEND) [offset = 04h]
31
16
Reserved
R-0
15
0
PEND[15:0]
R-0
LEGEND: R = Read only; -n = value after reset
Table 16-11. Channel Pending Register (PEND) Field Descriptions
Bit
Field
31-16
Reserved
15-0
PEND[n]
Value
0
Description
Reads return 0. Writes have no effect.
Channel pending register. Bit 0 corresponds to channel 0, bit 1 corresponds to channel 1, and so on.
Reading from PEND gives the channel pending information if the channel was initiated by SW or HW.
Once set, it remains set even if the corresponding channel is disabled via HWCHENA or SWCHENA.
The pending bit is automatically cleared for the following conditions:
• At the end of a frame or a block transfer depending on how the channel is triggered as programmed
in the TTYPE bit field of CHCTRL.
• The control packet is modified after the pending bit is set.
• An AHB bus error occurs.
0
The corresponding channel is inactive.
1
The corresponding channel is pending and is waiting for service.
16.3.1.3 DMA Status Register (DMASTAT)
Figure 16-20. DMA Status Register (DMASTAT) [offset = 0Ch]
31
16
Reserved
R-0
15
0
STCH[15:0]
R-0
LEGEND: R = Read only; -n = value after reset
Table 16-12. DMA Status Register (DMASTAT) Field Descriptions
Bit
Field
31-16
Reserved
15-0
STCH[n]
Value
0
Description
Reads return 0. Writes have no effect.
Status of DMA channels. Bit 0 corresponds to channel 0, bit 1 corresponds to channel 1, and so on.
0
The channel is inactive.
1
The channel is active; that is, the channel is currently in the DMA's execution queue.
Note: The status of a channel currently in DMA's execution queue remains active even if
emulation mode is entered or DMA is disabled via DMA_EN bit.
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16.3.1.4 HW Channel Enable Set and Status Register (HWCHENAS)
Figure 16-21. HW Channel Enable Set and Status Register (HWCHENAS) [offset = 14h]
31
16
Reserved
R-0
15
0
HWCHENA[15:0]
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 16-13. HW Channel Enable Set and Status Register (HWCHENAS) Field Descriptions
Bit
Field
31-16
Reserved
15-0
HWCHENA[n]
Value
0
Description
Reads return 0. Writes have no effect.
Hardware channel enable bit. Bit 0 corresponds to channel 0, bit 1 corresponds to channel 1, and
so on. An active hardware DMA request cannot initiate a DMA transfer unless the corresponding
hardware enable bit is set.
The corresponding hardware enable bit is cleared automatically for the following conditions:
• At the end of a block transfer if the auto-initiation bit AIM (see CHCTRL) is not active.
• If an AHB bus error is detected for an active channel.
Reading from HWCHENAS gives the status (enabled/disabled) of channels 0 through 15.
0
The corresponding channel is disabled for hardware triggering.
1
The corresponding channel is enabled for hardware triggering.
16.3.1.5 HW Channel Enable Reset and Status Register (HWCHENAR)
Figure 16-22. HW Channel Enable Reset and Status Register (HWCHENAR) [offset = 1Ch]
31
16
Reserved
R-0
15
0
HWCHDIS[15:0]
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 16-14. HW Channel Enable Reset and Status Register (HWCHENAR) Field Descriptions
Bit
Field
31-16
Reserved
15-0
HWCHDIS[n]
Value
0
Description
Reads return 0. Writes have no effect.
HW channel disable bit. Bit 0 corresponds to channel 0, bit 1 corresponds to channel 1, and so on.
0
Read: The corresponding channel is disabled for HW triggering.
Write: No effect.
1
Read: The corresponding channel is enabled for HW triggering.
Write: The corresponding channel is disabled.
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16.3.1.6 SW Channel Enable Set and Status Register (SWCHENAS)
Figure 16-23. SW Channel Enable Set and Status Register (SWCHENAS) [offset = 24h]
31
16
Reserved
R-0
15
0
SWCHENA[15:0]
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 16-15. SW Channel Enable Set and Status Register (SWCHENAS) Field Descriptions
Bit
Field
31-16
Reserved
15-0
SWCHENA[n]
Value
0
Description
Reads return 0. Writes have no effect.
SW channel enable bit. Bit 0 corresponds to channel 0, bit 1 corresponds to channel 1, and so on.
Writing a 1 to a bit triggers a SW request on the corresponding channel to start a DMA transaction.
The corresponding bit is automatically cleared by the following conditions.
• The corresponding bit is cleared after one frame transfer if the TTYPE bit in Channel Control
Register (CHCTRL) is programmed for frame transfer.
• The corresponding bit is cleared after one block transfer if the corresponding TTYPE bit is
programmed for block transfer and the auto-initiation bit is not enabled.
• The control packet is modified after the pending bit is set.
• The corresponding bit is cleared after one block transfer when TTYPE bit is programmed for
blocks transfer and if the corresponding bit in HW channel enable register (HWCHENAS) is
enabled. When a channel is enabled for both HW and SW, the state machine will initiate
transfers based on the SW first. After one block transfer is complete, the corresponding bit in the
SWCHENA register is then cleared. The same channel is serviced again by a HW DMA request.
• The corresponding bit is cleared if an AHB bus error is detected.
Reading from SWCHENAS gives the status (enabled/disabled) of channels 0 through 15.
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0
The corresponding channel is not triggered by SW request.
1
The corresponding channel is triggered by SW request.
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16.3.1.7 SW Channel Enable Reset and Status Register (SWCHENAR)
Figure 16-24. SW Channel Enable Reset and Status Register (SWCHENAR) [offset = 2Ch]
31
16
Reserved
R-0
15
0
SWCHDIS[15:0]
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 16-16. SW Channel Enable Reset and Status Register (SWCHENAR) Field Descriptions
Bit
Field
31-16
Reserved
15-0
SWCHDIS[n]
Value
0
Description
Reads return 0. Writes have no effect.
SW channel disable bit. Bit 0 corresponds to channel 0, bit 1 corresponds to channel 1, and so on.
0
Read: The corresponding channel was not triggered by SW.
Write: No effect.
1
Read: The corresponding channel was triggered by SW.
Write: The corresponding channel is disabled.
16.3.1.8 Channel Priority Set Register (CHPRIOS)
Figure 16-25. Channel Priority Set Register (CHPRIOS) [offset = 34h]
31
16
Reserved
R-0
15
0
CPS[15:0]
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 16-17. Channel Priority Set Register (CHPRIOS) Field Descriptions
Bit
Field
31-16
Reserved
15-0
CPS[n]
Value
0
Description
Reads return 0. Writes have no effect.
Channel priority set bit. Bit 0 corresponds to channel 0, bit 1 corresponds to channel 1, and so on.
Writing a 1 to a bit assigns the corresponding channel to the high-priority queue.
0
Read: The corresponding channel is assigned to the low-priority queue.
Write: No effect.
1
572
Read and write: The corresponding channel is assigned to high-priority queue.
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16.3.1.9 Channel Priority Reset Register (CHPRIOR)
Figure 16-26. Channel Priority Reset Register (CHPRIOR) [offset = 3Ch]
31
16
Reserved
R-0
15
0
CPR[15:0]
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 16-18. Channel Priority Reset Register (CHPRIOR) Field Descriptions
Bit
Field
Value
31-16
Reserved
15-0
CPR[n]
0
Description
Reads return 0. Writes have no effect.
Channel priority reset bit. Bit 0 corresponds to channel 0, bit 1 corresponds to channel 1, and so on.
Writing a 1 to a bit assigns the according channel to the low-priority queue.
0
Read: The corresponding channel is assigned to the low-priority queue.
Write: No effect.
1
Read: The corresponding channel is assigned to the high-priority queue.
Write: The corresponding channel is assigned to the low-priority queue.
16.3.1.10 Global Channel Interrupt Enable Set Register (GCHIENAS)
Figure 16-27. Global Channel Interrupt Enable Set Register (GCHIENAS) [offset = 44h]
31
16
Reserved
R-0
15
0
GCHIE[15:0]
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 16-19. Global Channel Interrupt Enable Set Register (GCHIENAS) Field Descriptions
Bit
Field
31-16
Reserved
15-0
GCHIE[n]
Value
0
Description
Reads return 0. Writes have no effect.
Global channel interrupt enable bit. Bit 0 corresponds to channel 0, bit 1 corresponds to channel 1, and
so on.
0
Read: The corresponding channel is disabled for interrupt.
Write: No effect.
1
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Read and write: The corresponding channel is enabled for interrupt.
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16.3.1.11 Global Channel Interrupt Enable Reset Register (GCHIENAR)
Figure 16-28. Global Channel Interrupt Enable Reset Register (GCHIENAR) [offset = 4Ch]
31
16
Reserved
R-0
15
0
GCHID[15:0]
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 16-20. Global Channel Interrupt Enable Reset Register (GCHIENAR) Field Descriptions
Bit
Field
31-16
Reserved
15-0
GCHID[n]
Value
0
Description
Reads return 0. Writes have no effect.
Global channel interrupt disable bit. Bit 0 corresponds to channel 0, bit 1 corresponds to channel 1, and
so on.
0
Read: The corresponding channel is disabled for interrupt.
Write: No effect.
1
Read: The corresponding channel is enabled for interrupt.
Write: The corresponding channel is disabled for interrupt.
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16.3.1.12 DMA Request Assignment Register 0 (DREQASI0)
Figure 16-29. DMA Request Assignment Register 0 (DREQASI0) [offset = 54h]
31
30
29
24
23
22
21
16
Reserved
CH0ASI
Reserved
CH1ASI
R-0
R/WP-0
R-0
R/WP-1h
15
14
13
8
7
6
5
0
Reserved
CH2ASI
Reserved
CH3ASI
R-0
R/WP-2h
R-0
R/WP-3h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 16-21. DMA Request Assignment Register 0 (DREQASI0) Field Descriptions
Bit
Field
31-30
Reserved
29-24
CH0ASI
23-22
Reserved
21-16
CH1ASI
15-14
Reserved
13-8
CH2ASI
7-6
Reserved
5-0
CH3ASI
Value
0
Description
Reads return 0. Writes have no effect.
Channel 0 assignment. This bit field chooses the DMA request assignment for channel 0.
0
DMA request line 0 triggers channel 0.
:
:
1Fh
DMA request line 31 triggers channel 0.
20h3Fh
Reserved
0
Reads return 0. Writes have no effect.
Channel 1 assignment. This bit field chooses the DMA request assignment for channel 1.
0
DMA request line 0 triggers channel 1.
:
:
1Fh
DMA request line 31 triggers channel 1.
20h3Fh
Reserved
0
Reads return 0. Writes have no effect.
Channel 2 assignment. This bit field chooses the DMA request assignment for channel 2.
0
DMA request line 0 triggers channel 2.
:
:
1Fh
DMA request line 31 triggers channel 2.
20h3Fh
Reserved
0
Reads return 0. Writes have no effect.
Channel 3 assignment. This bit field chooses the DMA request assignment for channel 3.
0
DMA request line 0 triggers channel 3.
:
:
1Fh
DMA request line 31 triggers channel 3.
20h3Fh
Reserved
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16.3.1.13 DMA Request Assignment Register 1 (DREQASI1)
Figure 16-30. DMA Request Assignment Register 1 (DREQASI1) [offset = 58h]
31
30
29
24
23
22
21
16
Reserved
CH4ASI
Reserved
CH5ASI
R-0
R/WP-4h
R-0
R/WP-5h
15
14
13
8
7
6
5
0
Reserved
CH6ASI
Reserved
CH7ASI
R-0
R/WP-6h
R-0
R/WP-7h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 16-22. DMA Request Assignment Register 1 (DREQASI1) Field Descriptions
Bit
Field
31-30
Reserved
29-24
CH4ASI
23-22
Reserved
21-26
CH5ASI
15-14
Reserved
13-8
CH6ASI
7-6
Reserved
5-0
CH7ASI
576
Value
0
Description
Reads return 0. Writes have no effect.
Channel 4 assignment. This bit field chooses the DMA request assignment for channel 4.
0
DMA request line 0 triggers channel 4.
:
:
1Fh
DMA request line 31 triggers channel 4.
20h3Fh
Reserved
0
Reads return 0. Writes have no effect.
Channel 5 assignment. This bit field chooses the DMA request assignment for channel 5.
0
DMA request line 0 triggers channel 5.
:
:
1Fh
DMA request line 31 triggers channel 5.
20h3Fh
Reserved
0
Reads return 0. Writes have no effect.
Channel 6 assignment. This bit field chooses the DMA request assignment for channel 6.
0
DMA request line 0 triggers channel 6.
:
:
1Fh
DMA request line 31 triggers channel 6.
20h3Fh
Reserved
0
Reads return 0. Writes have no effect.
Channel 7 assignment. This bit field chooses the DMA request assignment for channel 7.
0
DMA request line 0 triggers channel 7.
:
:
1Fh
DMA request line 31 triggers channel 7.
20h3Fh
Reserved
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16.3.1.14 DMA Request Assignment Register 2 (DREQASI2)
Figure 16-31. DMA Request Assignment Register 2 (DREQASI2) [offset = 5Ch]
31
30
29
24
23
22
21
16
Reserved
CH8ASI
Reserved
CH9ASI
R-0
R/WP-8h
R-0
R/WP-9h
15
14
13
8
7
6
5
0
Reserved
CH10ASI
Reserved
CH11ASI
R-0
R/WP-Ah
R-0
R/WP-Bh
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 16-23. DMA Request Assignment Register 2 (DREQASI2) Field Descriptions
Bit
Field
31-30
Reserved
29-24
CH8ASI
23-22
Reserved
21-16
CH9ASI
15-14
Reserved
13-8
CH10ASI
7-6
Reserved
5-0
CH11ASI
Value
0
Description
Reads return 0. Writes have no effect.
Channel 8 assignment. This bit field chooses the DMA request assignment for channel 8.
0
DMA request line 0 triggers channel 8.
:
:
1Fh
DMA request line 31 triggers channel 8.
20h3Fh
Reserved
0
Reads return 0. Writes have no effect.
Channel 9 assignment. This bit field chooses the DMA request assignment for channel 9.
0
DMA request line 0 triggers channel 9.
:
:
1Fh
DMA request line 31 triggers channel 9.
20h3Fh
Reserved
0
Reads return 0. Writes have no effect.
Channel 10 assignment. This bit field chooses the DMA request assignment for channel 10.
0
DMA request line 0 triggers channel 10.
:
:
1Fh
DMA request line 31 triggers channel 10.
20h3Fh
Reserved
0
Reads return 0. Writes have no effect.
Channel 11 assignment. This bit field chooses the DMA request assignment for channel 11.
0
DMA request line 0 triggers channel 11.
:
:
1Fh
DMA request line 31 triggers channel 11.
20h3Fh
Reserved
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16.3.1.15 DMA Request Assignment Register 3 (DREQASI3)
Figure 16-32. DMA Request Assignment Register 3 (DREQASI3) [offset = 60h]
31
30
29
24
23
22
21
16
Reserved
CH12ASI
Reserved
CH13ASI
R-0
R/WP-Ch
R-0
R/WP-Dh
15
14
13
8
7
6
5
0
Reserved
CH14ASI
Reserved
CH15ASI
R-0
R/WP-Eh
R-0
R/WP-Fh
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 16-24. DMA Request Assignment Register 3 (DREQASI3) Field Descriptions
Bit
Field
31-30
Reserved
29-24
CH12ASI
23-22
Reserved
21-16
CH13ASI
15-14
Reserved
13-8
CH14ASI
7-6
Reserved
5-0
CH15ASI
578
Value
0
Description
Reads return 0. Writes have no effect.
Channel 12 assignment. This bit field chooses the DMA request assignment for channel 12.
0
DMA request line 0 triggers channel 12.
:
:
1Fh
DMA request line 31 triggers channel 12.
20h3Fh
Reserved
0
Reads return 0. Writes have no effect.
Channel 13 assignment. This bit field chooses the DMA request assignment for channel 13.
0
DMA request line 0 triggers channel 13.
:
:
1Fh
DMA request line 31 triggers channel 13.
20h3Fh
Reserved
0
Reads return 0. Writes have no effect.
Channel 14 assignment. This bit field chooses the DMA request assignment for channel 14.
0
DMA request line 0 triggers channel 14.
:
:
1Fh
DMA request line 31 triggers channel 14.
20h3Fh
Reserved
0
Reads return 0. Writes have no effect.
Channel 15 assignment. This bit field chooses the DMA request assignment for channel 15.
0
DMA request line 0 triggers channel 15.
:
:
1Fh
DMA request line 31 triggers channel 15.
20h3Fh
Reserved
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16.3.1.16 Port Assignment Register 0 (PAR0)
Figure 16-33. Port Assignment Register 0 (PAR0) [offset = 94h]
31
30
28
27
26
24
23
22
20
19
18
16
Rsvd
CH0PA
Rsvd
CH1PA
Rsvd
CH2PA
Rsvd
CH3PA
R-0
R/WP-0
R-0
R/WP-0
R-0
R/WP-0
R-0
R/WP-0
15
14
12
11
10
8
7
6
4
3
2
0
Rsvd
CH4PA
Rsvd
CH5PA
Rsvd
CH6PA
Rsvd
CH7PA
R-0
R/WP-0
R-0
R/WP-0
R-0
R/WP-0
R-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 16-25. Port Assignment Register 0 (PAR0) Field Descriptions
Bit
Field
31
Reserved
30-28
27
26-24
23
22-20
19
18-16
15
14-12
11
10-8
7
6-4
3
2-0
Value
0
CH0PA
Reserved
These bit fields determine to which port channel 0 is assigned.
Port B
0xx
Reserved
0
These bit fields determine to which port channel 1 is assigned.
Port B
0xx
Reserved
0
1xx
Port B
0xx
Reserved
0
1xx
Port B
0xx
Reserved
0
These bit fields determine to which port channel 4 is assigned.
Port B
0xx
Reserved
0
Reads return 0. Writes have no effect.
These bit fields determine to which port channel 5 is assigned.
1xx
Port B
0xx
Reserved
0
CH6PA
Reserved
Reads return 0. Writes have no effect.
1xx
CH5PA
Reserved
Reads return 0. Writes have no effect.
These bit fields determine to which port channel 3 is assigned.
CH4PA
Reserved
Reads return 0. Writes have no effect.
These bit fields determine to which port channel 2 is assigned.
CH3PA
Reserved
Reads return 0. Writes have no effect.
1xx
CH2PA
Reserved
Reads return 0. Writes have no effect.
1xx
CH1PA
Reserved
Description
Reads return 0. Writes have no effect.
These bit fields determine to which port channel 6 is assigned.
1xx
Port B
0xx
Reserved
0
CH7PA
Reads return 0. Writes have no effect.
These bit fields determine to which port channel 7 is assigned.
1xx
Port B
0xx
Reserved
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16.3.1.17 Port Assignment Register 1 (PAR1)
Figure 16-34. Port Assignment Register 1 (PAR1) [offset = 98h]
31
30
28
27
26
24
23
22
20
19
18
16
Rsvd
CH8PA
Rsvd
CH9PA
Rsvd
CH10PA
Rsvd
CH11PA
R-0
R/WP-0
R-0
R/WP-0
R-0
R/WP-0
R-0
R/WP-0
15
14
12
11
10
8
7
6
4
3
2
0
Rsvd
CH12PA
Rsvd
CH13PA
Rsvd
CH14PA
Rsvd
CH15PA
R-0
R/WP-0
R-0
R/WP-0
R-0
R/WP-0
R-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 16-26. Port Assignment Register 1 (PAR1) Field Descriptions
Bit
Field
31
Reserved
30-28
27
26-24
0
CH8PA
Reserved
Reserved
22-20
CH10PA
19
Reserved
18-16
CH11PA
15
Reserved
14-12
CH12PA
11
Reserved
10-8
CH13PA
7
Reserved
6-4
CH14PA
3
Reserved
2-0
CH15PA
Description
Reads return 0. Writes have no effect.
These bit fields determine to which port channel 8 is assigned.
1xx
Port B
0xx
Reserved
0
CH9PA
23
580
Value
Reads return 0. Writes have no effect.
These bit fields determine to which port channel 9 is assigned.
1xx
Port B
0xx
Reserved
0
Reads return 0. Writes have no effect.
These bit fields determine to which port channel 10 is assigned.
1xx
Port B
0xx
Reserved
0
Reads return 0. Writes have no effect.
These bit fields determine to which port channel 11 is assigned.
1xx
Port B
0xx
Reserved
0
Reads return 0. Writes have no effect.
These bit fields determine to which port channel 12 is assigned.
1xx
Port B
0xx
Reserved
0
Reads return 0. Writes have no effect.
These bit fields determine to which port channel 13 is assigned.
1xx
Port B
0xx
Reserved
0
Reads return 0. Writes have no effect.
These bit fields determine to which port channel 14 is assigned.
1xx
Port B
0xx
Reserved
0
Reads return 0. Writes have no effect.
These bit fields determine to which port channel 15 is assigned.
1xx
Port B
0xx
Reserved
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16.3.1.18 FTC Interrupt Mapping Register (FTCMAP)
NOTE: On this device Group B interrupts are not implemented; hence, user software should
configure only Group A interrupts.
Figure 16-35. FTC Interrupt Mapping Register (FTCMAP) [offset = B4h]
31
16
Reserved
R-0
15
0
FTCAB[15:0]
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 16-27. FTC Interrupt Mapping Register (FTCMAP) Field Descriptions
Bit
Field
31-16
Reserved
15-0
FTCAB[n]
Value
0
Description
Reads return 0. Writes have no effect.
Frame transfer complete (FTC) interrupt to Group A or Group B. Bit 0 corresponds to channel 0, bit 1
corresponds to channel 1, and so on.
0
The FTC interrupt of the corresponding channel is routed to Group A.
1
The FTC interrupt of the corresponding channel is routed to Group B.
16.3.1.19 LFS Interrupt Mapping Register (LFSMAP)
NOTE: On this device Group B interrupts are not implemented; hence, user software should
configure only Group A interrupts.
Figure 16-36. LFS Interrupt Mapping Register (LFSMAP) [offset = BCh]
31
16
Reserved
R-0
15
0
LFSAB[15:0]
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 16-28. LFS Interrupt Mapping Register (LFSMAP) Field Descriptions
Bit
Field
31-16
Reserved
15-0
LFSAB[n]
Value
0
Description
Reads return 0. Writes have no effect.
Last frame started (LFS) interrupt to Group A or Group B. Bit 0 corresponds to channel 0, bit 1
corresponds to channel 1, and so on.
0
The LFS interrupt of the corresponding channel is routed to Group A.
1
The LFS interrupt of the corresponding channel is routed to Group B.
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16.3.1.20 HBC Interrupt Mapping Register (HBCMAP)
NOTE: On this device Group B interrupts are not implemented; hence, user software should
configure only Group A interrupts.
Figure 16-37. HBC Interrupt Mapping Register (HBCMAP) [offset = C4h]
31
16
Reserved
R-0
15
0
HBCAB[15:0]
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 16-29. HBC Interrupt Mapping Register (HBCMAP) Field Descriptions
Bit
Field
31-16
Reserved
15-0
HBCAB[n]
Value
0
Description
Reads return 0. Writes have no effect.
Half block complete (HBC) interrupt to Group A or Group B. Bit 0 corresponds to channel 0, bit 1
corresponds to channel 1, and so on.
0
The HBC interrupt of the corresponding channel is routed to Group A.
1
The HBC interrupt of the corresponding channel is routed to Group B.
16.3.1.21 BTC Interrupt Mapping Register (BTCMAP)
NOTE: On this device Group B interrupts are not implemented; hence, user software should
configure only Group A interrupts.
Figure 16-38. BTC Interrupt Mapping Register (BTCMAP) [offset = CCh]
31
16
Reserved
R-0
15
0
BTCAB[15:0]
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 16-30. BTC Interrupt Mapping Register (BTCMAP) Field Descriptions
Bit
Field
31-16
Reserved
15-0
BTCAB[n]
582
Value
0
Description
Reads return 0. Writes have no effect.
Block transfer complete (BTC) interrupt to Group A or Group B. Bit 0 corresponds to channel 0, bit 1
corresponds to channel 1, and so on.
0
The BTC interrupt of the corresponding channel is routed to Group A.
1
The BTC interrupt of the corresponding channel is routed to Group B.
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16.3.1.22 FTC Interrupt Enable Set (FTCINTENAS)
Figure 16-39. FTC Interrupt Enable Set (FTCINTENAS) [offset = DCh]
31
16
Reserved
R-0
15
0
FTCINTENA[15:0]
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 16-31. FTC Interrupt Enable Set (FTCINTENAS) Field Descriptions
Bit
Field
Value
31-16
Reserved
15-0
FTCINTENA[n]
0
Description
Reads return 0. Writes have no effect.
Frame transfer complete (FTC) interrupt enable. Bit 0 corresponds to channel 0, bit 1 corresponds
to channel 1, and so on.
0
Read: The corresponding FTC interrupt of a channel is disabled.
Write: No effect.
1
Read or write: The FTC interrupt of the corresponding channel is enabled.
16.3.1.23 FTC Interrupt Enable Reset (FTCINTENAR)
NOTE: On this device Group B interrupts are not implemented hence user software should configure
only Group A interrupts.
Figure 16-40. FTC Interrupt Enable Reset (FTCINTENAR) [offset = E4h]
31
16
Reserved
R-0
15
0
FTCINTDIS[15:0]
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 16-32. FTC Interrupt Enable Reset (FTCINTENAR) Field Descriptions
Bit
Field
31-16
Reserved
15-0
FTCINTDIS[n]
Value
0
Description
Reads return 0. Writes have no effect.
Frame transfer complete (FTC) interrupt disable. Bit 0 corresponds to channel 0, bit 1 corresponds
to channel 1, and so on.
0
Read: The corresponding FTC interrupt of a channel is disabled.
Write: No effect.
1
Read: The corresponding FTC interrupt of a channel is enabled.
Write: The corresponding FTC interrupt is disabled.
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16.3.1.24 LFS Interrupt Enable Set (LFSINTENAS)
Figure 16-41. LFS Interrupt Enable Set (LFSINTENAS) [offset = ECh]
31
16
Reserved
R-0
15
0
LFSINTENA[15:0]
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 16-33. LFS Interrupt Enable Set (LFSINTENAS) Field Descriptions
Bit
Field
Value
31-16
Reserved
15-0
LFSINTENA[n]
0
Description
Reads return 0. Writes have no effect.
Last frame started (LFS) interrupt enable. Bit 0 corresponds to channel 0, bit 1 corresponds to
channel 1, and so on.
0
Read: The corresponding LFS interrupt of a channel is disabled.
Write: No effect.
1
Read or write: The LFS interrupt of the corresponding channel is enabled.
16.3.1.25 LFS Interrupt Enable Reset (LFSINTENAR)
Figure 16-42. LFS Interrupt Enable Reset (LFSINTENAR) [offset = F4h]
31
16
Reserved
R-0
15
0
LFSINTDIS[15:0]
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 16-34. LFS Interrupt Enable Reset (LFSINTENAR) Field Descriptions
Bit
Field
31-16
Reserved
15-0
LFSINTDIS[n]
Value
0
Description
Reads return 0. Writes have no effect.
Last frame started (LFS) interrupt disable. Bit 0 corresponds to channel 0, bit 1 corresponds to
channel 1, and so on.
0
Read: The LFS interrupt of the corresponding channel is disabled.
Write: No effect.
1
Read: The LFS interrupt of the corresponding channel is enabled.
Write: The LFS interrupt of the corresponding channel is disabled.
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16.3.1.26 HBC Interrupt Enable Reset (HBCINTENAS)
Figure 16-43. HBC Interrupt Enable Set (HBCINTENAS) [offset = FCh]
31
16
Reserved
R-0
15
0
HBCINTENA[15:0]
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 16-35. HBC Interrupt Enable Set (HBCINTENAS) Field Descriptions
Bit
Field
Value
31-16
Reserved
15-0
HBCINTENA[n]
0
Description
Reads return 0. Writes have no effect.
Half block complete (HBC) interrupt enable. Bit 0 corresponds to channel 0, bit 1 corresponds to
channel 1, and so on.
0
Read: The HBC interrupt of the corresponding channel is disabled.
Write: No effect.
1
Read or write: The HBC interrupt of the corresponding channel is enabled.
16.3.1.27 HBC Interrupt Enable Reset (HBCINTENAR)
Figure 16-44. HBC Interrupt Enable Reset (HBCINTENAR) [offset = 104h]
31
16
Reserved
R-0
15
0
HBCINTDIS[15:0]
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 16-36. HBC Interrupt Enable Reset (HBCINTENAR) Field Descriptions
Bit
Field
31-16
Reserved
15-0
HBCINTDIS[n]
Value
0
Description
Reads return 0. Writes have no effect.
Half block complete (HBC) interrupt disable. Bit 0 corresponds to channel 0, bit 1 corresponds to
channel 1, and so on.
0
Read: The HBC interrupt of the corresponding channel is disabled.
Write: No effect.
1
Read: The HBC interrupt of the corresponding channel is enabled.
Write: The HBC interrupt of the corresponding channel is disabled.
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16.3.1.28 BTC Interrupt Enable Set (BTCINTENAS)
Figure 16-45. BTC Interrupt Enable Set (BTCINTENAS) [offset = 10Ch]
31
16
Reserved
R-0
15
0
BTCINTENA[15:0]
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 16-37. BTC Interrupt Enable Reset (BTCINTENAS) Field Descriptions
Bit
Field
Value
31-16
Reserved
15-0
BTCINTENA[n]
0
Description
Reads return 0. Writes have no effect.
Block transfer complete (BTC) interrupt enable. Bit 0 corresponds to channel 0, bit 1 corresponds to
channel 1, and so on.
0
Read: The BTC interrupt of the corresponding channel is disabled.
Write: No effect.
1
Read or write: The BTC interrupt of the corresponding channel is enabled.
16.3.1.29 BTC Interrupt Enable Reset (BTCINTENAR)
Figure 16-46. BTC Interrupt Enable Reset (BTCINTENAR) [offset = 114h]
31
16
Reserved
R-0
15
0
BTCINTDIS[15:0]
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 16-38. BTC Interrupt Enable Reset (BTCINTENAR) Field Descriptions
Bit
Field
31-16
Reserved
15-0
BTCINTDIS[n]
Value
0
Description
Reads return 0. Writes have no effect.
Block transfer complete (BTC) interrupt disable. Bit 0 corresponds to channel 0, bit 1 corresponds
to channel 1, and so on.
0
Read: The BTC interrupt of the corresponding channel is disabled.
Write: No effect.
1
Read: The BTC interrupt of the corresponding channel is enabled.
Write: The BTC interrupt of the corresponding channel is disabled.
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16.3.1.30 Global Interrupt Flag Register (GINTFLAG)
Figure 16-47. Global Interrupt Flag Register (GINTFLAG) [offset = 11Ch]
31
16
Reserved
R-0
15
0
GINT[15:0]
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 16-39. Global Interrupt Flag Register (GINTFLAG) Field Descriptions
Bit
Field
31-16
Reserved
15-0
GINT[n]
Value
0
Description
Reads return 0. Writes have no effect.
Global interrupt flags. Bit 0 corresponds to channel 0, bit 1 corresponds to channel 1, and so on. A
global interrupt flag bit is an OR function of FTC, LFS, HBC, and BTC interrupt flags.
0
No interrupt is pending on the corresponding channel.
1
One or more of the interrupt types (FTC, LFS, HBC, or BTC) is pending on the corresponding channel.
16.3.1.31 FTC Interrupt Flag Register (FTCFLAG)
Figure 16-48. FTC Interrupt Flag Register (FTCFLAG) [offset = 124h]
31
16
Reserved
R-0
15
0
FTCI[15:0]
R/W1CP-0
LEGEND: R/W = Read/Write; R = Read only; W1CP = Write 1 in privilege mode to clear the bit; -n = value after reset
Table 16-40. FTC Interrupt Flag Register (FTCFLAG) Field Descriptions
Bit
Field
31-16
Reserved
15-0
FTCI[n]
Value
0
Description
Reads return 0. Writes have no effect.
Frame transfer complete (FTC) flags. Bit 0 corresponds to channel 0, bit 1 corresponds to channel 1,
and so on.
Note: Reading from the respective interrupt channel offset register also clears the
corresponding flag (see Section 16.3.1.36 and Section 16.3.1.40).
Note: The state of the flag bit can be polled even if the corresponding interrupt enable bit is
cleared.
0
Read: An FTC interrupt of the corresponding channel is not pending.
Write: No effect.
1
Read: An FTC interrupt of the corresponding channel is pending.
Write: The flag is cleared.
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16.3.1.32 LFS Interrupt Flag Register (LFSFLAG)
Figure 16-49. LFS Interrupt Flag Register (LFSFLAG) [offset = 12Ch]
31
16
Reserved
R-0
15
0
LFSI[15:0]
R/W1CP-0
LEGEND: R/W = Read/Write; R = Read only; W1CP = Write 1 in privilege mode to clear the bit; -n = value after reset
Table 16-41. LFS Interrupt Flag Register (LFSFLAG) Field Descriptions
Bit
Field
31-16
Reserved
15-0
LFSI[n]
Value
0
Description
Reads return 0. Writes have no effect.
Last frame started (LFS) flags. Bit 0 corresponds to channel 0, bit 1 corresponds to channel 1, and so
on.
Note: Reading from the respective interrupt channel offset register also clears the
corresponding flag (see Section 16.3.1.37 and Section 16.3.1.41).
Note: The state of the flag bit can be polled even if the corresponding interrupt enable bit is
cleared.
0
Read: An LFS interrupt of the corresponding channel is not pending.
Write: No effect.
1
Read: An LFS interrupt of the corresponding channel is pending.
Write: The flag is cleared.
16.3.1.33 HBC Interrupt Flag Register (HBCFLAG)
Figure 16-50. HBC Interrupt Flag Register (HBCFLAG) [offset = 134h]
31
16
Reserved
R-0
15
0
HBCI[15:0]
R/W1CP-0
LEGEND: R/W = Read/Write; R = Read only; W1CP = Write 1 in privilege mode to clear the bit; -n = value after reset
Table 16-42. HBC Interrupt Flag (HBCFLAG) Field Descriptions
Bit
Field
31-16
Reserved
15-0
HBCI[n]
Value
0
Description
Reads return 0. Writes have no effect.
Half block transfer (HBC) complete flags. Bit 0 corresponds to channel 0, bit 1 corresponds to
channel 1, and so on.
Note: Reading from the respective interrupt channel offset register also clears the
corresponding flag (see Section 16.3.1.38 and Section 16.3.1.42).
Note: The state of the flag bit can be polled even if the corresponding interrupt enable bit is
cleared.
0
Read: An HBC interrupt of the corresponding channel is not pending.
Write: No effect.
1
Read: An HBC interrupt of the corresponding channel is pending.
Write: The flag is cleared.
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16.3.1.34 BTC Interrupt Flag Register (BTCFLAG)
Figure 16-51. BTC Interrupt Flag Register (BTCFLAG) [offset = 13Ch]
31
16
Reserved
R-0
15
0
BTCI[15:0]
R/W1CP-0
LEGEND: R/W = Read/Write; R = Read only; W1CP = Write 1 in privilege mode to clear the bit; -n = value after reset
Table 16-43. BTC Interrupt Flag Register (BTCFLAG) Field Descriptions
Bit
Field
31-16
Reserved
15-0
BTCI[n]
Value
0
Description
Reads return 0. Writes have no effect.
Block transfer complete (BTC) flags. Bit 0 corresponds to channel 0, bit 1 corresponds to channel 1,
and so on.
Note: Reading from the respective interrupt channel offset register also clears the
corresponding flag (see Section 16.3.1.39 and Section 16.3.1.43).
Note: The state of the flag bit can be polled even if the corresponding interrupt enable bit is
cleared.
0
Read: A BTC interrupt of the corresponding channel is not pending.
Write: No effect.
1
Read: A BTC interrupt of the corresponding channel is pending.
Write: The flag is cleared.
16.3.1.35 BER Interrupt Flag Register (BERFLAG)
The BERFLAG will never be set in this device. The bus error reporting is handled by the DMA Read
Imprecise Error and DMA Write Imprecise Error asserted to the ESM module directly, which are detected
at the device level. See the ESM error mapping for the DMA Read/Write Imprecise Error.
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16.3.1.36 FTCA Interrupt Channel Offset Register (FTCAOFFSET)
Figure 16-52. FTCA Interrupt Channel Offset Register (FTCAOFFSET) [offset = 14Ch]
31
16
Reserved
R-0
15
8
7
6
5
0
Reserved
sbz
sbz
FTCA
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 16-44. FTCA Interrupt Channel Offset Register (FTCAOFFSET) Field Descriptions
Bit
Field
Value
Description
31-8
Reserved
0
Reads return 0. Writes have no effect.
7-6
sbz
0
These bits should always be programmed as 0.
5-0
FTCA
Channel causing FTC interrupt Group A. These bits contain the channel number of the pending interrupt
for Group A if the corresponding interrupt enable is set.
Note: Reading this location clears the corresponding interrupt pending flag (see
Section 16.3.1.31) with the highest priority.
0
No interrupt is pending.
1h
Channel 0 is causing the pending interrupt Group A.
:
:
10h
Channel 15 is causing the pending interrupt Group A.
11h3Fh
Reserved
16.3.1.37 LFSA Interrupt Channel Offset Register (LFSAOFFSET)
Figure 16-53. LFSA Interrupt Channel Offset Register (LFSAOFFSET) [offset = 150h]
31
16
Reserved
R-0
15
7
6
Reserved
8
sbz
sbz
5
LFSA
0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 16-45. LFSA Interrupt Channel Offset Register (LFSAOFFSET) Field Descriptions
Bit
Field
Value
Description
31-8
Reserved
0
Reads return 0. Writes have no effect.
7-6
sbz
0
These bits should always be programmed as 0.
590
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Table 16-45. LFSA Interrupt Channel Offset Register (LFSAOFFSET) Field Descriptions (continued)
Bit
Field
5-0
LFSA
Value
Description
Channel causing LFS interrupt Group A. These bits contain the channel number of the pending interrupt
for Group A if the corresponding interrupt enable is set.
Note: Reading this location clears the corresponding interrupt pending flag (see
Section 16.3.1.32) with the highest priority.
0
No interrupt is pending.
1h
Channel 0 is causing the pending interrupt Group A.
:
:
10h
Channel 15 is causing the pending interrupt Group A.
11h3Fh
Reserved
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16.3.1.38 HBCA Interrupt Channel Offset Register (HBCAOFFSET)
Figure 16-54. HBCA Interrupt Channel Offset Register (HBCAOFFSET) [offset = 154h]
31
16
Reserved
R-0
15
8
7
6
5
0
Reserved
sbz
sbz
HBCA
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 16-46. HBCA Interrupt Channel Offset Register (HBCAOFFSET) Field Descriptions
Bit
Field
Value
Description
31-8
Reserved
0
Reads return 0. Writes have no effect.
7-6
sbz
0
These bits should always be programmed as 0.
5-0
HBCA
Channel causing HBC interrupt Group A. These bits contain the channel number of the pending
interrupt for Group A if the corresponding interrupt enable is set.
Note: Reading this location clears the corresponding interrupt pending flag (see
Section 16.3.1.33) with the highest priority.
0
No interrupt is pending.
1h
Channel 0 is causing the pending interrupt Group A.
:
:
10h
Channel 15 is causing the pending interrupt Group A.
11h3Fh
Reserved
16.3.1.39 BTCA Interrupt Channel Offset Register (BTCAOFFSET)
Figure 16-55. BTCA Interrupt Channel Offset Register (BTCAOFFSET) [offset = 158h]
31
16
Reserved
R-0
15
7
6
Reserved
8
sbz
sbz
5
BTCA
0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 16-47. BTCA Interrupt Channel Offset Register (BTCAOFFSET) Field Descriptions
Bit
Field
Value
Description
31-8
Reserved
0
Reads return 0. Writes have no effect.
7-6
sbz
0
These bits should always be programmed as 0.
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Table 16-47. BTCA Interrupt Channel Offset Register (BTCAOFFSET) Field Descriptions (continued)
Bit
Field
5-0
BTCA
Value
Description
Channel causing BTC interrupt Group A. These bits contain the channel number of the pending
interrupt for Group A if the corresponding interrupt enable is set.
Note: Reading this location clears the corresponding interrupt pending flag (see
Section 16.3.1.34) with the highest priority.
0
No interrupt is pending.
1h
Channel 0 is causing the pending interrupt Group A.
:
:
10h
Channel 15 is causing the pending interrupt Group A.
11h3Fh
Reserved
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16.3.1.40 FTCB Interrupt Channel Offset Register (FTCBOFFSET)
Figure 16-56. FTCB Interrupt Channel Offset Register (FTCBOFFSET) [offset = 160h]
31
16
Reserved
R-0
15
8
7
6
5
0
Reserved
sbz
sbz
FTCB
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 16-48. FTCB Interrupt Channel Offset Register (FTCBOFFSET) Field Descriptions
Bit
Field
Value
Description
31-8
Reserved
0
Reads return 0. Writes have no effect.
7-6
sbz
0
These bits should always be programmed as 0.
5-0
FTCB
Channel causing FTC interrupt Group B. These bits contain the channel number of the pending interrupt
for Group B if the corresponding interrupt enable is set.
Note: Reading this location clears the corresponding interrupt pending flag (see
Section 16.3.1.31) with the highest priority.
0
No interrupt is pending.
1h
Channel 0 is causing the pending interrupt Group B.
:
:
10h
Channel 15 is causing the pending interrupt Group B.
11h3Fh
Reserved
16.3.1.41 LFSB Interrupt Channel Offset Register (LFSBOFFSET)
Figure 16-57. LFSB Interrupt Channel Offset Register (LFSBOFFSET) [offset = 164h]
31
16
Reserved
R-0
15
7
6
Reserved
8
sbz
sbz
5
LFSB
0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 16-49. LFSB Interrupt Channel Offset Register (LFSBOFFSET) Field Descriptions
Bit
Field
Value
Description
31-8
Reserved
0
Reads return 0. Writes have no effect.
7-6
sbz
0
These bits should always be programmed as 0.
594
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Table 16-49. LFSB Interrupt Channel Offset Register (LFSBOFFSET) Field Descriptions (continued)
Bit
Field
5-0
LFSB
Value
Description
Channel causing LFS interrupt Group B. These bits contain the channel number of the pending interrupt
for Group B if the corresponding interrupt enable is set.
Note: Reading this location clears the corresponding interrupt pending flag (see
Section 16.3.1.32) with the highest priority.
0
No interrupt is pending.
1h
Channel 0 is causing the pending interrupt Group B.
:
:
10h
Channel 15 is causing the pending interrupt Group B.
11h3Fh
Reserved
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16.3.1.42 HBCB Interrupt Channel Offset Register (HBCBOFFSET)
Figure 16-58. HBCB Interrupt Channel Offset Register (HBCBOFFSET) [offset = 168h]
31
16
Reserved
R-0
15
8
7
6
5
0
Reserved
sbz
sbz
HBCB
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 16-50. HBCB Interrupt Channel Offset Register (HBCBOFFSET) Field Descriptions
Bit
Field
Value
Description
31-8
Reserved
0
Reads return 0. Writes have no effect.
7-6
sbz
0
These bits should always be programmed as 0.
5-0
HBCB
Channel causing HBC interrupt Group B. These bits contain the channel number of the pending
interrupt for Group B if the corresponding interrupt enable is set.
Note: Reading this location clears the corresponding interrupt pending flag (see
Section 16.3.1.33) with the highest priority.
0
No interrupt is pending.
1h
Channel 0 is causing the pending interrupt Group B.
:
:
10h
Channel 15 is causing the pending interrupt Group B.
11h3Fh
Reserved
16.3.1.43 BTCB Interrupt Channel Offset Register (BTCBOFFSET)
Figure 16-59. BTCB Interrupt Channel Offset Register (BTCBOFFSET) [offset = 16Ch]
31
16
Reserved
R-0
15
7
6
Reserved
8
sbz
sbz
5
BTCB
0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 16-51. BTCB Interrupt Channel Offset Register (BTCBOFFSET) Field Descriptions
Bit
Field
Value
Description
31-8
Reserved
0
Reads return 0. Writes have no effect.
7-6
sbz
0
These bits should always be programmed as 0.
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Table 16-51. BTCB Interrupt Channel Offset Register (BTCBOFFSET) Field Descriptions (continued)
Bit
Field
5-0
BTCB
Value
Description
Channel causing BTC interrupt Group B. These bits contain the channel number of the pending
interrupt for Group B if the corresponding interrupt enable is set.
Note: Reading this location clears the corresponding interrupt pending flag (see
Section 16.3.1.34) with the highest priority.
0
No interrupt is pending.
1h
Channel 0 is causing the pending interrupt Group B.
:
:
10h
Channel 15 is causing the pending interrupt Group B.
11h3Fh
Reserved
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16.3.1.44 Port Control Register (PTCRL)
Figure 16-60. Port Control Register (PTCRL) [offset = 178h]
31
25
24
Reserved
PENDB
R-0
R-0
23
19
18
17
16
Reserved
BYB
PSFRHQPB
PSFRLQPB
R-0
R/WP-0
R/WP-0
R/WP-0
15
0
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 16-52. Port Control Register (PTCRL) Field Descriptions
Bit
31-25
24
23-19
18
Field
Reserved
Value
0
PENDB
Reserved
Description
Reads return 0. Writes have no effect.
Transfers pending for Port B. This flag determines if transfers are ongoing on port B. The flag will
be cleared if no transfers are performed. It can be used to determine if there is still data transferred
while DMA_EN is set to 0 in GCTCRL. In this case, once all transfers are finished, the flag will be
set to 0.
0
No transfers are pending.
1
Transfers are pending.
0
Reads return 0. Writes have no effect.
BYB
Bypass FIFO B.
0
FIFO B is not bypassed.
1
FIFO B is bypassed. Writing 1 to this bit limits the FIFO depth to the size of one element. That
means that after one element is read, the write-out to the destination will begin. This feature is
particularly useful to minimize switching latency between channels.
Note: This feature does not make optimal use of bus bandwidth.
17
16
15-0
598
PSFRHQPB
Priority scheme fix or rotate for high priority queue of Port B.
0
Fixed priority is used.
1
Rotation priority is used.
PSFRLQPB
Reserved
Priority scheme fix or rotate for low priority queue of Port B.
0
The fixed priority scheme is used.
1
The rotation priority scheme is used.
0
Reads return 0. Writes have no effect.
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16.3.1.45 RAM Test Control (RTCTRL)
Figure 16-61. RAM Test Control (RTCTRL) [offset = 17Ch]
31
16
Reserved
R-0
15
1
0
Reserved
RTC
R-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 16-53. RAM Test Control (RTCTRL) Field Descriptions
Bit
31-1
0
Field
Reserved
Value
0
RTC
Description
Reads return 0. Writes have no effect.
RAM Test Control. Writing a 1 to this bit opens the write access to the reserved locations of control
packet RAM as defined in the memory map.
Note: This bit should be cleared to 0 during normal operation.
0
RAM Test Control is disabled.
1
RAM Test Control is enabled.
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16.3.1.46 Debug Control (DCTRL)
Figure 16-62. Debug Control (DCTRL) [offset = 180h]
31
29
28
24
23
17
16
Reserved
CHNUM
Reserved
DMADBGS
R-0
R-0
R-0
R/W1C-0
15
1
0
Reserved
DBGEN
R-0
R/WC-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear; -n = value after reset
Table 16-54. Debug Control (DCTRL) Field Descriptions
Bit
Field
Value
31-29
Reserved
0
28-24
CHNUM
0-1Fh
23-17
Reserved
0
16
DMADBGS
Description
Reads return 0. Writes have no effect.
Channel Number. This bit field indicates the channel number that causes the watch point to
match.
Reads return 0. Writes have no effect.
DMA debug status. When a watch point is set up to watch for a unique bus address or a range
of addresses is true on one of the three bus ports, then the DMA debug status bit is set to 1
and a debug request signal is asserted to the main CPU. The CPU must write a 1 to clear this
bit for the DMA controller to release the debug request signal.
0
Read: No watch point condition is detected.
Write: No effect.
1
Read: The watch point condition is detected.
Write: The bit is cleared.
15-1
0
Reserved
0
DBGEN
Reads return 0. Writes have no effect.
Debug Enable.
Note: This bit can only be set when using a debugger.
Note: This bit is reset when Test reset (nTRST) is low.
600
0
Debug is disabled.
1
The watch point checking logics is enabled.
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16.3.1.47 Watch Point Register (WPR)
Figure 16-63. Watch Point Register (WPR) [offset = 184h]
31
16
WP
R/W-0
15
0
WP
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16-55. Watch Point Register (WPR) Field Descriptions
Bit
31-0
Field
WP
Value
Description
0-FFFF FFFFh
Watch point.
Note: These bits can only be set when using a debugger.
Note: This register is only reset by a when Test reset (nTRST).
A 32-bit address can be programmed into this register as a watch point. This register is used
with the watch mask register (WMR).
When the DBGEN bit in the DCTRL register is set and a unique address or a range of
addresses are detected on the AHB address bus of Port B, a debug request signal is sent to
the ARM CPU. The state machine of the port in which the watch point condition is true is
frozen.
16.3.1.48 Watch Mask Register (WMR)
Figure 16-64. Watch Mask Register (WMR) [offset = 188h]
31
16
WM[31:16]
R/W-0
15
0
WM[15:0]
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16-56. Watch Mask Register (WMR) Field Descriptions
Bit
Field
31-0
WM[n]
Value
Description
Watch mask.
Note: These bits can only be set when using a debugger.
Note: This register is only reset by a when Test reset (nTRST).
0
Allows the corresponding bit in the WPR register to be used for address matching for a watch point.
1
Masks the corresponding bit in the WPR register and is disregarded in the comparison.
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16.3.1.49 Port B Active Channel Source Address Register (PBACSADDR)
Figure 16-65. Port B Active Channel Source Address Register (PBACDADDR) [offset = 198h]
31
16
PBACSA
R-0
15
0
PBACSA
R-0
LEGEND: R = Read only; -n = value after reset
Table 16-57. Port B Active Channel Source Address Register (PBACDADDR) Field Descriptions
Bit
31-0
Field
PBACSA
Value
0-FFFF FFFFh
Description
Port B Active Channel Source Address. This register contains the current source address of the
active channel as broadcasted in Section 16.3.1.3 for Port B.
16.3.1.50 Port B Active Channel Destination Address Register (PBACDADDR)
Figure 16-66. Port B Active Channel Destination Address Register (PBACDADDR) [offset = 19Ch]
31
16
PBACDA
R-0
15
0
PBACDA
R-0
LEGEND: R = Read only; -n = value after reset
Table 16-58. Port B Active Channel Destination Address Register (PBACDADDR) Field Descriptions
Bit
31-0
602
Field
PBACDA
Value
0-FFFF FFFFh
Description
Port B Active Channel Destination Address. This register contains the current destination
address of the active channel as broadcasted in Section 16.3.1.3 for Port B.
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16.3.1.51 Port B Active Channel Transfer Count Register (PBACTC)
Figure 16-67. Port B Active Channel Transfer Count Register (PBACTC) [offset = 1A0h]
31
29
28
16
Reserved
PBFTCOUNT
R-0
R-0
15
13
12
0
Reserved
PBETCOUNT
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 16-59. Port B Active Channel Transfer Count Register (PBACTC) Field Descriptions
Bit
Field
31-29
Reserved
28-16
PBFTCOUNT
15-13
Reserved
12-0
PBETCOUNT
Value
0
0-1FFFh
0
0-1FFFh
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Description
Reads return 0. Writes have no effect.
Port B active channel frame count. These bits contain the current frame count value of the
active channel as broadcasted in Section 16.3.1.3 for Port B.
Reads return 0. Writes have no effect.
Port B active channel element count. These bits contain the current element count value of
the active channel as broadcasted in Section 16.3.1.3 for Port B.
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16.3.1.52 Parity Control Register (DMAPCR)
Figure 16-68. Parity Control Register (DMAPCR) [offset = 1A8h]
31
15
15
9
16
Reserved
ERRA
R-0
R/WP-0
8
7
4
3
0
Reserved
TEST
Reserved
PARITY_ENA
R-0
R/WP-0
R-0
R/WP-5h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 16-60. Parity Control Register (DMAPCR) Field Descriptions
Bit
31-17
16
15-9
8
Field
Reserved
Value
0
ERRA
Reserved
Reserved
3-0
PARITY_ENA
Reads return 0. Writes have no effect.
Error action.
0
If a parity error is detected on control packet x (x = 0, 1, ... n), then the enable/disable state of
control packet x remains unchanged.
1
If a parity error is detected on control packet x (x = 0, 1, ...n), then the DMA controller is
disabled immediately. If a frame on control packet x is processed at the time the parity error is
detected, then remaining elements of this frame will not be transferred anymore. The DMA will
be disabled regardless of whether the error was detected during a read to the control packet
RAM performed by the DMA state machine or by a different master.
0
Reads return 0. Writes have no effect.
TEST
7-4
Description
When this bit is set, the parity bits are memory mapped to make them accessible by the CPU.
0
The parity bits are not memory mapped.
1
The parity bits are memory mapped.
0
Reads return 0. Writes have no effect.
Parity error detection enable. This bit field enables or disables the parity check on read
operations and the parity calculation on write operations. If parity checking is enabled and a
parity error is detected, the DMA_UERR signal is activated.
5h
The parity check is disabled.
All other
values
The parity check is enabled.
Note: It is recommended to write Ah to enable parity check, to guard against soft error
from flipping PARITY_ENA to a disable state.
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16.3.1.53 DMA Parity Error Address Register (DMAPAR)
Figure 16-69. DMA Parity Error Address Register (DMAPAR) [offset = 1ACh]
31
25
24
23
16
Reserved
EDFLAG
Reserved
R-0
R/W1C-0
R-0
15
12
11
0
Reserved
ERRORADDRESS
R-0
R-X
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear; X= Undefined; -n = value after reset
Table 16-61. DMA Parity Error Address Register (DMAPAR) Field Descriptions
Bit
Field
31-25
Reserved
24
EDFLAG
Value
0
Description
Reads return 0. Writes have no effect.
Parity Error Detection Flag. This flag indicates if a parity error occurred on reading DMA
Control packet RAM.
0
Read: No error occurred.
Write: No effect.
1
Read: Error detected and the address is captured in DMAPAR's ERROR_ADDRESS field
Write: Clears the bit.
23-12
Reserved
11-0
ERRORADDRESS
0
0-FFFh
Reads return 0. Writes have no effect.
Error address. These bits hold the address of the first parity error generated in the RAM.
This error address is frozen from being updated until it is read by the CPU. During
emulation mode when SUSPEND is high, this address is frozen even when read.
Note: The error address register will not be reset by PORRST nor by any other reset
source.
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16.3.1.54 DMA Memory Protection Control Register (DMAMPCTRL)
Figure 16-70. DMA Memory Protection Control Register (DMAMPCTRL) [offset = 1B0h]
31
28
27
Reserved
29
INT3AB
INT3ENA
REG3AP
REG3ENA
R-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
20
19
Reserved
INT2AB
INT2ENA
REG2AP
REG2ENA
R-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
23
21
15
13
26
25
18
17
12
11
INT1AB
INT1ENA
REG1AP
REG1ENA
R-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
5
9
16
Reserved
7
10
24
2
1
8
4
3
Reserved
INT0AB
INT0ENA
REG0AP
REG0ENA
0
R-0
R/WP-0
R/WP-0
R/WP-00
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 16-62. DMA Memory Protection Control Register (DMAMPCTRL) Field Descriptions
Bit
31-29
28
27
26-25
24
23-21
20
19
18-17
16
606
Field
Reserved
Value
0
INT3AB
Reads return 0. Writes have no effect.
Interrupt assignment of region 3 to Group A or Group B.
0
The interrupt is routed to the VIM (Group A).
1
The interrupt is routed to the second CPU (Group B).
INT3ENA
Interrupt enable of region 3.
0
The interrupt is disabled.
1
The interrupt is enabled.
REG3AP
Region 3 access permission. These bits determine the access permission for region 3.
0
All accesses are allowed.
1h
Read only accesses are allowed.
2h
Write only accesses are allowed.
3h
No accesses are allowed.
REG3ENA
Reserved
Description
Region 3 enable.
0
The region is disabled (no address checking done).
1
The region is enabled (address and access permission checking done).
0
Reads return 0. Writes have no effect.
INT2AB
Interrupt assignment of region 2 to Group A or Group B.
0
The interrupt is routed to the VIM (Group A).
1
The interrupt is routed to the second CPU (Group B).
INT2ENA
Interrupt enable of region 2.
0
The interrupt is disabled.
1
The interrupt is enabled.
REG2AP
Region 2 access permission. These bits determine the access permission for region 2.
0
All accesses are allowed.
1h
Read only accesses are allowed.
2h
Write only accesses are allowed.
3h
No accesses are allowed.
REG2ENA
Region 2 enable.
0
The region is disabled (no address checking done).
1
The region is enabled (address and access permission checking done).
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Table 16-62. DMA Memory Protection Control Register (DMAMPCTRL) Field Descriptions (continued)
Bit
15-13
12
11
10-9
8
7-5
4
3
2-1
0
Field
Reserved
Value
0
INT1AB
Reads return 0. Writes have no effect.
Interrupt assignment of region 1 to Group A or Group B.
0
The interrupt is routed to the VIM (Group A).
1
The interrupt is routed to the second CPU (Group B).
INT1ENA
Interrupt enable of region 1.
0
The interrupt is disabled.
1
The interrupt is enabled.
REG1AP
Region 1 access permission. These bits determine the access permission for region 1.
0
All accesses are allowed.
1h
Read only accesses are allowed.
2h
Write only accesses are allowed.
3h
No accesses are allowed.
REG1ENA
Reserved
Description
Region 1 enable.
0
The region is disabled (no address checking done).
1
The region is enabled (address and access permission checking done).
0
Reads return 0. Writes have no effect.
INT0AB
Interrupt assignment of region 0 to Group A or Group B.
0
The interrupt is routed to the VIM (Group A).
1
The interrupt is routed to the DSP CPU (Group B).
INT0ENA
Interrupt enable of region 0.
0
The interrupt is disabled.
1
The interrupt is enabled.
REG0AP
Region 0 access permission. These bits determine the access permission for region 0.
0
All accesses are allowed.
1h
Read only accesses are allowed.
2h
Write only accesses are allowed.
3h
No accesses are allowed.
REG0ENA
Region 0 enable.
0
The region is disabled (no address checking done).
1
The region is enabled (address and access permission checking done).
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16.3.1.55 DMA Memory Protection Status Register (DMAMPST)
Figure 16-71. DMA Memory Protection Status Register (DMAMPST) [offset = 1B4h]
31
25
24
23
17
16
Reserved
REG3FT
Reserved
REG2FT
R-0
R/W1C-0
R-0
R/W1C-0
15
9
8
7
1
0
Reserved
REG1FT
Reserved
REG0FT
R-0
R/W1C-0
R-0
R/W1C-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear; -n = value after reset
Table 16-63. DMA Memory Protection Status Register (DMAMPST) Field Descriptions
Bit
Field
31-25
Reserved
24
REG3FT
Value
0
Description
Reads return 0. Writes have no effect.
Region 3 fault. This bit determines whether an access permission violation was detected in this region.
0
Read: No fault was detected.
Write: No effect.
1
Read: A fault was detected.
Write: The bit was cleared.
23-17
Reserved
16
REG2FT
0
Reads return 0. Writes have no effect.
Region 2 fault. This bit determines whether an access permission violation was detected in this region.
0
Read: No fault was detected.
Write: No effect.
1
Read: A fault was detected.
Write: The bit was cleared.
15-9
Reserved
8
REG1FT
0
Reads return 0. Writes have no effect.
Region 1 fault. This bit determines whether an access permission violation was detected in this region.
0
Read: No fault was detected.
Write: No effect.
1
Read: A fault was detected.
Write: The bit was cleared.
7-1
Reserved
0
REG0FT
0
Reads return 0. Writes have no effect.
Region 0 fault. This bit determines whether an access permission violation was detected in this region.
0
Read: No fault was detected.
Write: No effect.
1
Read: A fault was detected.
Write: The bit was cleared.
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16.3.1.56 DMA Memory Protection Region 0 Start Address Register (DMAMPR0S)
Figure 16-72. DMA Memory Protection Region 0 Start Address Register (DMAMPR0S)
[offset = 1B8h]
31
16
STARTADDRESS
R/WP-0
15
0
STARTADDRESS
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 16-64. DMA Memory Protection Region 0 Start Address Register (DMAMPR0S)
Field Descriptions
Bit
31-0
Field
Value
STARTADDRESS
0-FFFF FFFFh
Description
Start Address defines the address at which the region begins. The effective start address
is truncated to the nearest word address, that is, 0x103 = 0x100.
16.3.1.57 DMA Memory Protection Region 0 End Address Register (DMAMPR0E)
Figure 16-73. DMA Memory Protection Region 0 End Address Register (DMAMPR0E)
[offset = 1BCh]
31
16
ENDADDRESS
R/WP-0
15
0
ENDADDRESS
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 16-65. DMA Memory Protection Region 0 End Address Register (DMAMPR0E)
Field Descriptions
Bit
31-0
Field
ENDADDRESS
Value
0-FFFF FFFFh
Description
End Address defines the address at which the region ends. The end address usually is
larger than the start address for this region; otherwise, the region will wrap around at the
end of the address space. The end address is the start address plus the region length
minus 1. The effective end address is rounded up to the nearest 32-bit word end address,
that is, 0x200 = 0x203.
Note: When using 64-bit transfers, the address is rounded up to the nearest 64-bit
word end address, that is, 0x200 = 0x207. All other transfers are rounded up to the
nearest 32-bit word end address.
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16.3.1.58 DMA Memory Protection Region 1 Start Address Register (DMAMPR1S)
Figure 16-74. DMA Memory Protection Region 1 Start Address Register (DMAMPR1S)
[offset = 1C0h]
31
16
STARTADDRESS
R/WP-0
15
0
STARTADDRESS
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 16-66. DMA Memory Protection Region 1 Start Address Register (DMAMPR1S)
Field Descriptions
Bit
31-0
Field
Value
STARTADDRESS
0-FFFF FFFFh
Description
Start Address defines the address at which the region begins. The effective start address
is truncated to the nearest word address, that is, 0x103 = 0x100.
16.3.1.59 DMA Memory Protection Region 1 End Address Register (DMAMPR1E)
Figure 16-75. DMA Memory Protection Region 1 End Address Register (DMAMPR1E)
[offset = 1C4h]
31
16
ENDADDRESS
R/WP-0
15
0
ENDADDRESS
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 16-67. DMA Memory Protection Region 1 End Address Register (DMAMPR1E)
Field Descriptions
Bit
31-0
Field
ENDADDRESS
Value
0-FFFF FFFFh
Description
End Address defines the address at which the region ends. The end address usually is
larger than the start address for this region; otherwise, the region will wrap around at the
end of the address space. The end address is the start address plus the region length
minus 1. The effective end address is rounded up to the nearest 32-bit word end address,
that is, 0x200 = 0x203.
Note: When using 64-bit transfers, the address is rounded up to the nearest 64-bit
word end address, that is, 0x200 = 0x207. All other transfers are rounded up to the
nearest 32-bit word end address.
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16.3.1.60 DMA Memory Protection Region 2 Start Address Register (DMAMPR2S)
Figure 16-76. DMA Memory Protection Region 2 Start Address Register (DMAMPR2S)
[offset = 1C8h]
31
16
STARTADDRESS
R/WP-0
15
0
STARTADDRESS
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 16-68. DMA Memory Protection Region 2 Start Address Register (DMAMPR2S)
Field Descriptions
Bit
31-0
Field
Value
STARTADDRESS
0-FFFF FFFFh
Description
Start Address defines the address at which the region begins. The effective start address
is truncated to the nearest word address, that is, 0x103 = 0x100.
16.3.1.61 DMA Memory Protection Region 2 End Address Register (DMAMPR2E)
Figure 16-77. DMA Memory Protection Region 2 End Address Register (DMAMPR2E)
[offset = 1CCh]
31
16
ENDADDRESS
R/WP-0
15
0
ENDADDRESS
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 16-69. DMA Memory Protection Region 2 End Address Register (DMAMPR2E)
Field Descriptions
Bit
31-0
Field
ENDADDRESS
Value
0-FFFF FFFFh
Description
End Address defines the address at which the region ends. The end address usually is
larger than the start address for this region; otherwise, the region will wrap around at the
end of the address space. The end address is the start address plus the region length
minus 1. The effective end address is rounded up to the nearest 32-bit word end address,
that is, 0x200 = 0x203.
Note: When using 64-bit transfers, the address is rounded up to the nearest 64-bit
word end address, that is, 0x200 = 0x207. All other transfers are rounded up to the
nearest 32-bit word end address.
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16.3.1.62 DMA Memory Protection Region 3 Start Address Register (DMAMPR3S)
Figure 16-78. DMA Memory Protection Region 3 Start Address Register (DMAMPR3S)
[offset = 1D0h]
31
16
STARTADDRESS
R/WP-0
15
0
STARTADDRESS
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 16-70. DMA Memory Protection Region 3 Start Address Register (DMAMPR3S)
Field Descriptions
Bit
31-0
Field
Value
STARTADDRESS
0-FFFF FFFFh
Description
Start Address defines the address at which the region begins. The effective start address
is truncated to the nearest word address, that is, 0x103 = 0x100.
16.3.1.63 DMA Memory Protection Region 3 End Address Register (DMAMPR3E)
Figure 16-79. DMA Memory Protection Region 3 End Address Register (DMAMPR3E)
[offset = 1D4h]
31
16
ENDADDRESS
R/WP-0
15
0
ENDADDRESS
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 16-71. DMA Memory Protection Region 3 End Address Register (DMAMPR3E)
Field Descriptions
Bit
31-0
Field
ENDADDRESS
Value
0-FFFF FFFFh
Description
End Address defines the address at which the region ends. The end address usually is
larger than the start address for this region; otherwise, the region will wrap around at the
end of the address space. The end address is the start address plus the region length
minus 1. The effective end address is rounded up to the nearest 32-bit word end address,
that is, 0x200 = 0x203.
Note: When using 64-bit transfers, the address is rounded up to the nearest 64-bit
word end address, that is, 0x200 = 0x207. All other transfers are rounded up to the
nearest 32-bit word end address.
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16.3.2 Channel Configuration
The channel configuration is defined by the channel control packet: channel control, transfer count, offset
values, source/destination address.
• It is stored in local RAM, which is protected by parity.
• Each control packet contains a total of nine fields.
• The first six fields are programmable, while the last three fields are read only.
• The RAM is accessible by queue A and queue B state machines as well as CPU.
• When there are simultaneous accesses, the priority is resolved in a fixed priority scheme with the CPU
having the highest priority.
All the control packets look the same. Following, there is the detailed layout of these registers shown for
control packet 0.
16.3.2.1 Initial Source Address (ISADDR)
Figure 16-80. Initial Source Address (ISADDR) [offset = 00]
31
16
ISADDR
R/WP-X
15
0
ISADDR
R/WP-X
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset; X = Unknown
Table 16-72. Initial Source Address (ISADDR) Field Descriptions
Bit
31-0
Field
ISADDR
Value
0-FFFF FFFFh
Description
Initial source address. These bits give the absolute 32-bit source address (physical).
16.3.2.2 Initial Destination Address Register (IDADDR)
Figure 16-81. Initial Destination Address Register (IDADDR) [offset = 04h]
31
16
IDADDR
R/WP-X
15
0
IDADDR
R/WP-X
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset; X = Unknown
Table 16-73. Initial Destination Address Register (IDADDR) Field Descriptions
Bit
31-0
Field
IDADDR
Value
0-FFFF FFFFh
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Description
Initial destination address. These bits give the absolute 32-bit destination address (physical).
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16.3.2.3 Initial Transfer Count Register (ITCOUNT)
Figure 16-82. Initial Transfer Count Register (ITCOUNT) [offset = 08h]
31
29
28
16
Reserved
IFTCOUNT
R-X
R/WP-X
15
13
12
0
Reserved
IETCOUNT
R-X
R/WP-X
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset; X = Unknown
Table 16-74. Initial Transfer Count Register (ITCOUNT) Field Descriptions
Bit
Field
Value
31-29
Reserved
28-16
IFTCOUNT
15-13
Reserved
12-0
IETCOUNT
Description
0
Reads are undefined. Writes have no effect.
0-1FFFh
Initial frame transfer count. These bits define the number of frame transfers.
0
Reads are undefined. Writes have no effect.
0-1FFFh
Initial element transfer count. These bits define the number of element transfers. The block
transfer size will be IETCOUNT x IFTCOUNT
16.3.2.4 Channel Control Register (CHCTRL)
Figure 16-83. Channel Control Register (CHCTRL) [offset = 10h]
31
22
15
14
13
12
21
16
Reserved
CHAIN
R-X
R/WP-X
11
9
8
7
5
4
3
2
1
0
RES
WES
Reserved
TTYPE
Reserved
ADDMR
ADDMW
AIM
R/WP-X
R/WP-X
R-X
R/WP-X
R-X
R/WP-X
R/WP-X
R/WP-X
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset; X = Unknown
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Table 16-75. Channel Control Register (CHCTRL) Field Descriptions
Bit
Field
31-22
Reserved
21-16
CHAIN
Value
0
Description
Reads are undefined. Writes have no effect.
Next channel to be triggered. At the end of the programmed number of frames, the specified
channel will be triggered. Programmed value x means channel (x-1) is chained.
Note: The programmer must program the CHAIN bits before initiating a DMA transfer.
0
No channel is selected.
1h
Channel 0 is selected.
:
10h
11h-3Fh
15-14
13-12
11-9
8
RES
Reserved
4-3
ADDMR
2-1
0
Reserved
Read element size.
The element is byte, 8-bit.
1h
The element is half-word, 16-bit.
2h
The element is word, 32-bit.
3h
The element is double-word, 64-bit.
Write element size.
0
The element is byte, 8-bit.
1h
The element is half-word, 16-bit.
2h
The element is word, 32-bit.
3h
The element is double-word, 64-bit.
0
Reads are undefined. Writes have no effect.
TTYPE
7-5
Channel 15 is selected.
0
WES
Reserved
:
Transfer type.
0
A request triggers one frame transfer.
1
A request triggers one block transfer.
0
Reads are undefined. Writes have no effect.
Addressing mode read.
0
Constant
1h
Post-increment
2h
Reserved
3h
Indexed
ADDMW
Addressing mode write.
0
Constant
1h
Post-increment
2h
Reserved
3h
Indexed
AIM
Auto-initiation mode.
0
Auto-initiation mode is disabled.
1
Auto-initiation mode is enabled.
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16.3.2.5 Element Index Offset Register (EIOFF)
Figure 16-84. Element Index Offset Register (EIOFF) [offset = 14h]
31
29
28
16
Reserved
EIDXD
R-X
R/WP-X
15
13
12
0
Reserved
EIDXS
R-X
R/WP-X
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset; X = Unknown
Table 16-76. Element Index Offset Register (EIOFF) Field Descriptions
Bit
Field
31-29
Reserved
28-16
EIDXD
15-13
Reserved
12-0
EIDXS
Value
0
0-1FFFh
0
0-1FFFh
Description
Reads are undefined. Writes have no effect.
Destination address element index. These bits define the offset to be added to the
destination address after each element transfer.
Reads are undefined. Writes have no effect.
Source address element index. These bits define the offset to be added to the source
address after each element transfer.
16.3.2.6 Frame Index Offset Register (FIOFF)
Figure 16-85. Frame Index Offset Register (FIOFF) [offset = 18h]
31
29
28
16
Reserved
FIDXD
R-X
R/WP-X
15
13
12
0
Reserved
FIDXS
R-X
R/WP-X
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset; X = Unknown
Table 16-77. Frame Index Offset Register (FIOFF) Field Descriptions
Bit
Field
31-29
Reserved
28-16
FIDXD
15-13
Reserved
12-0
FIDXS
616
Value
0
0-1FFFh
0
0-1FFFh
Description
Reads are undefined. Writes have no effect.
Destination address frame index. These bits define the offset to be added to the destination
address after element count reached 1.
Reads are undefined. Writes have no effect.
Source address frame index. These bits define the offset to be added to the source address
after element count reached 1.
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16.3.2.7 Current Source Address Register (CSADDR)
Figure 16-86. Current Source Address Register (CSADDR) [offset = 800h]
31
16
CSADDR
R-X
15
0
CSADDR
R-X
LEGEND: R = Read only; -n = value after reset; X = Unknown
Table 16-78. Current Source Address Register (CSADDR) Field Descriptions
Bit
31-0
Field
CSADDR
Value
0-FFFF FFFFh
Description
Current source address. These bits contain the current working absolute 32-bit source
address (physical). These bits are only updated after a channel is arbitrated out from the
priority queue.
16.3.2.8 Current Destination Address Register (CDADDR)
Figure 16-87. Current Destination Address Register (CDADDR) [offset = 804h]
31
16
CDADDR
R-X
15
0
CDADDR
R-X
LEGEND: R = Read only; -n = value after reset; X = Unknown
Table 16-79. Current Destination Address Register (CDADDR) Field Descriptions
Bit
31-0
Field
CDADDR
Value
0-FFFF FFFFh
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Description
Current destination address. These bits contain the current working absolute 32-bit
destination address (physical). These bits are only updated after a channel is arbitrated out
of the priority queue.
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16.3.2.9 Current Transfer Count Register (CTCOUNT)
Figure 16-88. Current Transfer Count Register (CTCOUNT) [offset = 808h]
31
29
28
16
Reserved
CFTCOUNT
R-X
R-X
15
13
12
0
Reserved
CETCOUNT
R-X
R-X
LEGEND: R = Read only; -n = value after reset; X = Unknown
Table 16-80. Current Transfer Count Register (CTCOUNT) Field Descriptions
Bit
Field
31-29
Reserved
28-16
CFTCOUNT
15-13
Reserved
12-0
CETCOUNT
618
Value
0
0-1FFFh
0
0-1FFFh
Description
Reads are undefined. Writes have no effect.
Current frame transfer count. Returned the current remaining frame counts.
Reads are undefined. Writes have no effect.
Current element transfer count. These bits return the current remaining element counts.
CTCOUNT register is only updated after a channel is arbitrated out of the priority queue.
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Chapter 17
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External Memory Interface (EMIF)
This chapter describes the external memory Interface (EMIF).
Topic
17.1
17.2
17.3
17.4
...........................................................................................................................
Introduction .....................................................................................................
EMIF Module Architecture .................................................................................
EMIF Registers .................................................................................................
Example Configuration ......................................................................................
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17.1 Introduction
17.1.1 Purpose of the Peripheral
This EMIF memory controller is compliant with the JESD21-C SDR SDRAM memories utilizing a 16-bit
data bus. The purpose of this EMIF is to provide a means for the CPU to connect to a variety of external
devices including:
• Single data rate (SDR) SDRAM
• Asynchronous devices including NOR Flash and SRAM
The most common use for the EMIF is to interface with both a flash device and an SDRAM device
simultaneously. Section 17.4 contains an example of operating the EMIF in this configuration.
17.1.2 Features
The EMIF includes many features to enhance the ease and flexibility of connecting to external SDR
SDRAM and asynchronous devices.
17.1.2.1 Asynchronous Memory Support
EMIF supports asynchronous:
• SRAM memories
• NOR Flash memories
The EMIF data bus width is up to 16 bits and there are up to 22 address lines. There is an external wait
input that allows slower asynchronous memories to extend the memory access. The EMIF module
supports up to 3 chip selects (EMIF_nCS[4:2]). Each chip select has the following individually
programmable attributes:
• Data Bus Width
• Read cycle timings: setup, hold, strobe
• Write cycle timings: setup, hold, strobe
• Bus turn-around time
• Extended Wait Option with Programmable Timeout
• Select Strobe option
17.1.2.2 Synchronous DRAM Memory Support
The EMIF module supports 16-bit SDRAM in addition to the asynchronous memories listed in
Section 17.1.2.1. It has a single SDRAM chip select (EMIF_nCS[0]). SDRAM configurations that are
supported are:
• One, Two and Four Bank SDRAM devices
• Devices with Eight, Nine, Ten, and Eleven Column Address
• CAS Latency of two or three clock cycles
• 16-bit Data Bus Width
• 3.3V LVCMOS Interface
Additionally, the EMIF supports placing the SDRAM in Self-Refresh and Powerdown modes. Self-refresh
mode allows the SDRAM to be put in a low-power state while still retaining memory contents; since the
SDRAM will continue to refresh itself even without clocks from the microcontroller. Powerdown mode
achieves even lower power, except the microcontroller must periodically wake up and issue refreshes if
data retention is required.
Note that the EMIF module does not support Mobile SDRAM devices.
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17.1.3 Functional Block Diagram
Figure 17-1 illustrates the connections between the EMIF and its internal requesters, along with the
external EMIF pins. Section 17.2.2 contains a description of the entities internal to the SoC that can send
requests to the EMIF, along with their prioritization. Section 17.2.3 describes the EMIF external pins and
summarizes their purpose when interfacing with SDRAM and asynchronous devices.
Figure 17-1. EMIF Functional Block Diagram
EMIF
CPU
EDMA
EMIF_nCS[0]
EMIF_nCAS
EMIF_nRAS
EMIF_CLK
EMIF_CKE
EMIF_nCS[4:2]
EMIF_nOE
SDRAM
interface
Asynchronous
interface
EMIF_nWAIT
Master
Peripherals
EMIF_nWE
EMIF_BA[1:0]
EMIF_nDQM[1:0]
EMIF_DATA[15:0]
EMIF_ADDR[21:0]
Shared SDRAM
and asynchronous
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17.2 EMIF Module Architecture
This section provides details about the architecture and operation of the EMIF. Both, SDRAM and
asynchronous Interface are covered, along with other system-related issues such as clock control.
17.2.1 EMIF Clock Control
The EMIF clock is output on the EMIF_CLK pin and should be used when interfacing to external SDRAM
devices. The EMIF module gets the VCLK3 clock domain as the input. This clock domain is running at half
the frequency of the main oscillator by default, that is, between 2.5MHz to 10MHz. The VCLK3 frequency
is divided down from the HCLK domain frequency by a programmable divider (/1 to /16). Refer the
Architecture chapter of the device technical reference manual for more information on configuring the
VCLK3 domain frequency.
17.2.2 EMIF Requests
Different sources within the SoC can make requests to the EMIF. These requests consist of accesses to
SDRAM memory, asynchronous memory, and EMIF registers. The EMIF can process only one request at
a time. Therefore a high performance crossbar switch exists within the SoC to provide prioritized requests
from the different sources to the EMIF. The sources are:
1. CPU
2. DMA
3. Other master peripherals
If a request is submitted from two or more sources simultaneously, the crossbar switch will forward the
highest priority request to the EMIF first. Upon completion of a request, the crossbar switch again
evaluates the pending requests and forwards the highest priority pending request to the EMIF.
When the EMIF receives a request, it may or may not be immediately processed. In some cases, the
EMIF will perform one or more auto refresh cycles before processing the request. For details on the
EMIF's internal arbitration between performing requests and performing auto refresh cycles, see
Section 17.2.13.
17.2.3 EMIF Signal Descriptions
This section describes the function of each of the EMIF signals.
Table 17-1. EMIF Pins Used to Access Both SDRAM and Asynchronous Memories
Pins(s)
I/O
Description
EMIF_DATA[15:0]
I/O
EMIF data bus.
EMIF_ADDR[21:0]
O
EMIF address bus.
When interfacing to an SDRAM device, these pins are primarily used to provide the row and
column address to the SDRAM. The mapping from the internal program address to the external
values placed on these pins can be found in Table 17-13. EMIF_A[10] is also used during the
PRE command to select which banks to deactivate.
When interfacing to an asynchronous device, these pins are used in conjunction with the
EMIF_BA pins to form the address that is sent to the device. The mapping from the internal
program address to the external values placed on these pins can be found in Section 17.2.6.1.
EMIF_BA[1:0]
O
EMIF bank address.
When interfacing to an SDRAM device, these pins are used to provide the bank address inputs to
the SDRAM. The mapping from the internal program address to the external values placed on
these pins can be found inTable 17-13.
When interfacing to an asynchronous device, these pins are used in conjunction with the EMIF_A
pins to form the address that is sent to the device. The mapping from the internal program
address to the external values placed on these pins can be found in Section 17.2.6.1.
EMIF_nDQM[1:0]
O
Active-low byte enables.
When interfacing to SDRAM, these pins are connected to the DQM pins of the SDRAM to
individually enable/disable each of the bytes in a data access.
When interfacing to an asynchronous device, these pins are connected to byte enables. See
Section 17.2.6 for details.
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Table 17-1. EMIF Pins Used to Access Both SDRAM and Asynchronous Memories (continued)
Pins(s)
I/O
Description
EMIF_nWE
O
Active-low write enable.
When interfacing to SDRAM, this pin is connected to the nWE pin of the SDRAM and is used to
send commands to the device.
When interfacing to an asynchronous device, this pin provides a signal which is active-low during
the strobe period of an asynchronous write access cycle.
Table 17-2. EMIF Pins Specific to SDRAM
Pin(s)
I/O
Description
EMIF_nCS[0]
O
Active-low chip enable pin for SDRAM devices.
This pin is connected to the chip-select pin of the attached SDRAM device and is used for
enabling/disabling commands. By default, the EMIF keeps this SDRAM chip select active, even if
the EMIF is not interfaced with an SDRAM device. This pin is deactivated when accessing the
asynchronous memory bank and is reactivated on completion of the asynchronous access.
EMIF_nRAS
O
Active-low row address strobe pin.
This pin is connected to the nRAS pin of the attached SDRAM device and is used for sending
commands to the device.
EMIF_nCAS
O
Active-low column address strobe pin.
This pin is connected to the nCAS pin of the attached SDRAM device and is used for sending
commands to the device.
EMIF_CKE
O
Clock enable pin.
This pin is connected to the CKE pin of the attached SDRAM device and is used for issuing the
SELF REFRESH command which places the device in self refresh mode. See Section 17.2.5.7
for details.
EMIF_CLK
O
SDRAM clock pin.
This pin is connected to the CLK pin of the attached SDRAM device. See Section 17.2.1 for
details on the clock signal.
Table 17-3. EMIF Pins Specific to Asynchronous Memory
Pin(s)
I/O
Description
EMIF_nCS[4:2]
O
Active-low chip enable pins for asynchronous devices.
These pins are meant to be connected to the chip-select pins of the attached asynchronous
device. These pins are active only during accesses to the asynchronous memory.
EMIF_nWAIT
I
Wait input with programmable polarity.
A connected asynchronous device can extend the strobe period of an access cycle by asserting
the EMIF_nWAIT input to the EMIF as described in Section 17.2.6.6. To enable this functionality,
the EW bit in the asynchronous 1 configuration register (CE2CFG) must be set to 1. In addition,
the WP0 bit in CE2CFG must be configured to define the polarity of the EMIF_nWAIT pin.
EMIF_nOE
O
Active-low pin enable for asynchronous devices.
This pin provides a signal which is active-low during the strobe period of an asynchronous read
access cycle.
17.2.4 EMIF Signal Multiplexing Control
Several EMIF signals are multiplexed with other functions on this microcontroller. Please refer to the I/O
Multiplexing Module chapter of the technical reference manual for more information on how to enable the
output of these EMIF signals.
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17.2.5 SDRAM Controller and Interface
The EMIF can gluelessly interface to most standard SDR SDRAM devices and supports such features as
self refresh mode and prioritized refresh. In addition, it provides flexibility through programmable
parameters such as the refresh rate, CAS latency, and many SDRAM timing parameters. The following
sections include details on how to Interface and properly configure the EMIF to perform read and write
operations to externally connected SDR SDRAM devices. Also, Section 17.4 provides a detailed example
of interfacing the EMIF to a common SDRAM device.
17.2.5.1 SDRAM Commands
The EMIF supports the SDRAM commands described in Table 17-4. Table 17-5 shows the truth table for
the SDRAM commands, and an example timing waveform of the PRE command is shown in Figure 17-2.
EMIF_A[10] is pulled low in this example to deactivate only the bank specified by the EMIF_BA pins.
Table 17-4. EMIF SDRAM Commands
Command
Function
PRE
Precharge. Depending on the value of EMIF_A[10], the PRE command either deactivates the open row in all
banks (EMIF_A[10] = 1) or only the bank specified by the EMIF_BA[1:0] pins (EMIF_A[10] = 0).
ACTV
Activate. The ACTV command activates the selected row in a particular bank for the current access.
READ
Read. The READ command outputs the starting column address and signals the SDRAM to begin the burst read
operation. Address EMIF_A[10] is always pulled low to avoid auto precharge. This allows for better bank
interleaving performance.
WRT
Write. The WRT command outputs the starting column address and signals the SDRAM to begin the burst write
operation. Address EMIF_A[10] is always pulled low to avoid auto precharge. This allows for better bank
interleaving performance.
BT
Burst terminate. The BT command is used to truncate the current read or write burst request.
LMR
Load mode register. The LMR command sets the mode register of the attached SDRAM devices and is only
issued during the SDRAM initialization sequence described in Section 17.2.5.4.
REFR
Auto refresh. The REFR command signals the SDRAM to perform an auto refresh according to its internal
address.
SLFR
Self refresh. The self refresh command places the SDRAM into self refresh mode, during which it provides its own
clock signal and auto refresh cycles.
NOP
No operation. The NOP command is issued during all cycles in which one of the above commands is not issued.
Table 17-5. Truth Table for SDRAM Commands
SDRAM Pins:
CKE
nCS
nRAS
nCAS
nWE
BA[1:0]
A[12:11]
A[10]
A[9:0]
EMIF_CKE
EMIF_nCS[0]
EMIF_nRAS
EMIF_nCAS
EMIF_nWE
EMIF_BA[1:0]
EMIF_A[12:11]
EMIF_A[10]
EMIF_A[9:0]
PRE
H
L
L
H
L
Bank/X
X
L/H
X
ACTV
H
L
L
H
H
Bank
Row
Row
Row
READ
H
L
H
L
H
Bank
Column
L
Column
WRT
H
L
H
L
L
Bank
Column
L
Column
BT
H
L
H
H
L
X
X
X
X
LMR
H
L
L
L
L
X
Mode
Mode
Mode
REFR
H
L
L
L
H
X
X
X
X
SLFR
L
L
L
L
H
X
X
X
X
NOP
H
L
H
H
H
X
X
X
X
EMIF Pins:
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Figure 17-2. Timing Waveform of SDRAM PRE Command
PRE
EMIF_CLK
EMIF_nCS[0]
EMIF_nDQM
Bank
EMIF_BA
EMIF_A[10]=0
EMIF_A
EMIF_nRAS
EMIF_nCAS
EMIF_nWE
17.2.5.2 Interfacing to SDRAM
The EMIF supports a glueless interface to SDRAM devices with the following characteristics:
• Pre-charge bit is A[10]
• The number of column address bits is 8, 9, 10, or 11.
• The number of row address bits is 13, 14, 15, or 16.
• The number of internal banks is 1, 2, or 4.
Figure 17-3 shows an interface between the EMIF and a 2M × 16 × 4 bank SDRAM device, and
Figure 17-4 shows an interface between the EMIF and a 512K × 16 × 2 bank SDRAM device. For devices
supporting 16-bit interface, refer to Table 17-6 for list of commonly-supported SDRAM devices and the
required connections for the address pins.
Figure 17-3. EMIF to 2M × 16 × 4 bank SDRAM Interface
EMIF
EMIF_nCS[0]
EMIF_nCAS
EMIF_nRAS
EMIF_nWE
EMIF_CLK
EMIF_CKE
EMIF_BA[1:0]
EMIF_A[11:0]
EMIF_nDQM[0]
EMIF_nDQM[1]
EMIF_D[15:0]
nCE
nCAS
nRAS
nWE
CLK
CKE
BA[1:0]
SDRAM
2M x 16
x 4 bank
A[11:0]
LDQM
UDQM
DQ[15:0]
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Figure 17-4. EMIF to 512K × 16 × 2 bank SDRAM Interface
EMIF
EMIF_nCS[0]
EMIF_nCAS
EMIF_nRAS
EMIF_nWE
EMIF_CLK
EMIF_CKE
EMIF_BA[0]
nCE
nCAS
nRAS
nWE
CLK
CKE
BA[0]
EMIF_A[10:0]
EMIF_nDQM[0]
EMIF_nDQM[1]
EMIF_D[15:0]
SDRAM
512 x 16
x 2 bank
A[10:0]
LDQM
UDQM
DQ[15:0]
Table 17-6. 16-bit EMIF Address Pin Connections
SDRAM Size
Width
Banks
Device
Address Pins
16M bits
×16
2
SDRAM
A[10:0]
EMIF
EMIF_A[10:0]
64M bits
×16
4
SDRAM
A[11:0]
EMIF
EMIF_A[11:0]
128M bits
×16
4
SDRAM
A[11:0]
EMIF
EMIF_A[11:0]
256M bits
x16
4
SDRAM
A[12:0]
EMIF
EMIF_A[12:0]
512M bits
626
x16
4
SDRAM
A[12:0]
EMIF
EMIF_A[12:0]
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17.2.5.3 SDRAM Configuration Registers
The operation of the EMIF's SDRAM interface is controlled by programming the appropriate configuration
registers. This section describes the purpose and function of each configuration register, but Section 17.3
should be referred for a more detailed description of each register, including the default registers values
and bit-field positions. The following tables list the four such configuration registers, along with a
description of each of their programmable fields.
NOTE: Writing to any of the fields: NM, CL, IBANK, and PAGESIZE in the SDRAM configuration
register (SDCR) causes the EMIF to abandon whatever it is currently doing and trigger the
SDRAM initialization procedure described in Section 17.2.5.4.
Table 17-7. Description of the SDRAM Configuration Register (SDCR)
Parameter
Description
SR
This bit controls entering and exiting of the Self-Refresh mode. The field should be written using a bytewrite to the upper byte of SDCR to avoid triggering the SDRAM initialization sequence.
PD
This bit controls entering and exiting of the Power down mode. The field should be written using a bytewrite to the upper byte of SDCR to avoid triggering the SDRAM initialization sequence. If both SR and
PD bits are set, the EMIF will go into Self Refresh.
PDWR
Perform refreshes during Power Down. Writing a 1 to this bit will cause the EMIF to exit the power down
state and issue an AUTO REFRESH command every time Refresh May level is set. The field should be
written using a byte-write to the upper byte of SDCR to avoid triggering the SDRAM initialization
sequence. This bit should be set along with PD when entering power-down mode.
NM
Narrow Mode. This bit defines the width of the data bus between the EMIF and the attached SDRAM
device. When set to 1, the data bus is set to 16-bits. When set to 0, the data bus is set to 32-bits. This
bit must always be set to 1.
CL
CAS latency. This field defines the number of clock cycles between when an SDRAM issues a READ
command and when the first piece of data appears on the bus. The value in this field is sent to the
attached SDRAM device via the LOAD MODE REGISTER command during the SDRAM initialization
procedure as described in Section 17.2.5.4. Only, values of 2h (CAS latency = 2) and 3h (CAS latency =
3) are supported and should be written to this field. A 1 must be simultaneously written to the
BIT11_9LOCK bit field of SDCR in order to write to the CL bit field.
IBANK
Number of Internal SDRAM Banks. This field defines the number of banks inside the attached SDRAM
devices in the following way:
• When IBANK = 0, 1 internal bank is used
• When IBANK = 1h, 2 internal banks are used
• When IBANK = 2h, 4 internal banks are used
This field value affects the mapping of logical addresses to SDRAM row, column, and bank addresses.
See Section 17.2.5.11 for details.
PAGESIZE
Page Size. This field defines the internal page size of the attached SDRAM devices in the following way:
• When PAGESIZE = 0, 256-word pages are used
• When PAGESIZE = 1h, 512-word pages are used
• When PAGESIZE = 2h, 1024-word pages are used
• When PAGESIZE = 3h, 2048-word pages are used
This field value affects the mapping of logical addresses to SDRAM row, column, and bank addresses.
See Section 17.2.5.11 for details.
Table 17-8. Description of the SDRAM Refresh Control Register (SDRCR)
Parameter
Description
RR
Refresh Rate. This field controls the rate at which attached SDRAM devices will be refreshed. The
following equation can be used to determine the required value of RR for an SDRAM device:
• RR = fEMIF_CLK / (Required SDRAM Refresh Rate)
More information about the operation of the SDRAM refresh controller can be found in Section 17.2.5.6.
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Table 17-9. Description of the SDRAM Timing Register (SDTIMR)
Parameter
Description
T_RFC
SDRAM Timing Parameters. These fields configure the EMIF to comply with the AC timing
requirements of the attached SDRAM devices. This allows the EMIF to avoid violating SDRAM timing
constraints and to more efficiently schedule its operations. More details about each of these parameters
can be found in the register description in Section 17.3.6. These parameters should be set to satisfy the
corresponding timing requirements found in the SDRAM's datasheet.
T_RP
T_RCD
T_WR
T_RAS
T_RC
T_RRD
Table 17-10. Description of the SDRAM Self Refresh Exit Timing Register (SDSRETR)
Parameter
Description
T_XS
Self Refresh Exit Parameter. The T_XS field of this register informs the EMIF about the minimum
number of EMIF_CLK cycles required between exiting Self Refresh and issuing any command. This
parameter should be set to satisfy the tXSR value for the attached SDRAM device.
17.2.5.4 SDRAM Auto-Initialization Sequence
The EMIF automatically performs an SDRAM initialization sequence, regardless of whether it is interfaced
to an SDRAM device, when either of the following two events occur:
• The EMIF comes out of reset. No memory accesses to the SDRAM and Asynchronous interfaces are
performed until this auto-initialization is complete.
• A write is performed to any of the three least significant bytes of the SDRAM configuration register
(SDCR)
An SDRAM initialization sequence consists of the following steps:
1. If the initialization sequence is activated by a write to SDCR, and if any of the SDRAM banks are open,
the EMIF issues a PRE command with EMIF_A[10] held high to indicate all banks. This is done so that
the maximum ACTV to PRE timing for an SDRAM is not violated.
2. The EMIF drives EMIF_CKE high and begins continuously issuing NOP commands until eight SDRAM
refresh intervals have elapsed. An SDRAM refresh interval is equal to the value of the RR field of
SDRAM refresh control register (SDRCR), divided by the frequency of EMIF_CLK (RR/fEMIF_CLK). This
step is used to avoid violating the Power-up constraint of most SDRAM devices that requires 200 μs
(sometimes 100 μs) between receiving stable Vdd and CLK and the issuing of a PRE command.
Depending on the frequency of EMIF_CLK, this step may or may not be sufficient to avoid violating the
SDRAM constraint. See Section 17.2.5.5 for more information.
3. After the refresh intervals have elapsed, the EMIF issues a PRE command with EMIF_A[10] held high
to indicate all banks.
4. The EMIF issues eight AUTO REFRESH commands.
5. The EMIF issues the LMR command with the EMIF_A[9:0] pins set as described in Table 17-11.
6. Finally, the EMIF performs a refresh cycle, which consists of the following steps:
a. Issuing a PRE command with EMIF_A[10] held high if any banks are open
b. Issuing an REF command
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Table 17-11. SDRAM LOAD MODE REGISTER Command
EMIF_A[9:7]
EMIF_A[6:4]
EMIF_A[3]
EMIF_A[2:0]
0 (Write bursts are of
the programmed burst
length in
EMIF_A[2:0])
These bits control the CAS latency of the
SDRAM and are set according to CL field in
the SDRAM configuration register (SDCR)
as follows:
• If CL = 2, EMIF_A[6:4] = 2h
(CAS latency = 2)
• If CL = 3, EMIF_A[6:4] = 3h
(CAS latency = 3)
0 (Sequential Burst
Type. Interleaved
Burst Type not
supported)
These bits control the burst length of the
SDRAM and are set according to the NM
field in the SDRAM configuration register
(SDCR) as follows:
• If NM = 0, EMIF_A[2:0] = 2h
(Burst Length = 4)
• If NM = 1, EMIF_A[2:0] = 3h
(Burst Length = 8)
17.2.5.5 SDRAM Configuration Procedure
There are two different SDRAM configuration procedures. Although EMIF automatically performs the
SDRAM initialization sequence described in Section 17.2.5.4 when coming out of reset, it is recommended
to follow one of the procedures listed below before performing any EMIF memory requests. Procedure A
should be followed if it is determined that the SDRAM Power-up constraint was not violated during the
SDRAM Auto-Initialization Sequence detailed in Section 17.2.5.4 on coming out of Reset. The SDRAM
Power-up constraint specifies that 200 μs (sometimes 100 μs) should exist between receiving stable Vdd
and CLK and the issuing of a PRE command. Procedure B should be followed if the SDRAM Power-up
constraint was violated. The 200 μs (100 μs) SDRAM Power-up constraint will be violated if the frequency
of EMIF_CLK is greater than 50 MHz (100 MHz for 100 μs SDRAM power-up constraint) during SDRAM
Auto-Initialization Sequence. Procedure B should be followed if there is any doubt that the Power-up
constraint was not met.
Procedure A — Following is the procedure to be followed if the SDRAM Power-up constraint was NOT
violated:
1. Place the SDRAM into Self-Refresh Mode by setting the SR bit of SDCR to 1. A byte-write to the upper
byte of SDCR should be used to avoid restarting the SDRAM Auto-Initialization Sequence described in
Section 17.2.5.4. The SDRAM should be placed into Self-Refresh mode when changing the frequency
of EMIF_CLK to avoid incurring the 200 μs Power-up constraint again.
2. Configure the desired EMIF_CLK clock frequency. The frequency of the memory clock must meet the
timing requirements in the SDRAM manufacturer's documentation and the timing limitations shown in
the electrical specifications of the device datasheet.
3. Remove the SDRAM from Self-Refresh Mode by clearing the SR bit of SDCR to 0. A byte-write to the
upper byte of SDCR should be used to avoid restarting the SDRAM Auto-Initialization Sequence
described in Section 17.2.5.4.
4. Program SDTIMR and SDSRETR to satisfy the timing requirements for the attached SDRAM device.
The timing parameters should be taken from the SDRAM datasheet.
5. Program the RR field of SDRCR to match that of the attached device's refresh interval. See
Section 17.2.5.6.1 details on determining the appropriate value.
6. Program SDCR to match the characteristics of the attached SDRAM device. This will cause the autoinitialization sequence in Section 17.2.5.4 to be re-run. This second initialization generally takes much
less time due to the increased frequency of EMIF_CLK.
Procedure B — Following is the procedure to be followed if the SDRAM Power-up constraint was
violated:
1. Configure the desired EMIF_CLK clock frequency. The frequency of the memory clock must meet the
timing requirements in the SDRAM manufacturer's documentation and the timing limitations shown in
the electrical specifications of the device datasheet.
2. Program SDTIMR and SDSRETR to satisfy the timing requirements for the attached SDRAM device.
The timing parameters should be taken from the SDRAM datasheet.
3. Program the RR field of SDRCR such that the following equation is satisfied: (RR × 8)/(fEMIF_CLK) >
200 μs (sometimes 100 μs). For example, an EMIF_CLK frequency of 100 MHz would require setting
RR to 2501 (9C5h) or higher to meet a 200 μs constraint.
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4. Program SDCR to match the characteristics of the attached SDRAM device. This will cause the autoinitialization sequence in Section 17.2.5.4 to be re-run with the new value of RR.
5. Perform a read from the SDRAM to assure that step 5 of this procedure will occur after the initialization
process has completed. Alternatively, wait for 200 μs instead of performing a read.
6. Finally, program the RR field to match that of the attached device's refresh interval. See
Section 17.2.5.6.1 details on determining the appropriate value.
After following the above procedure, the EMIF is ready to perform accesses to the attached SDRAM
device. See Section 17.4 for an example of configuring the SDRAM interface.
17.2.5.6 EMIF Refresh Controller
An SDRAM device requires that each of its rows be refreshed at a minimum required rate. The EMIF can
meet this constraint by performing auto refresh cycles at or above this required rate. An auto refresh cycle
consists of issuing a PRE command to all banks of the SDRAM device followed by issuing a REFR
command. To inform the EMIF of the required rate for performing auto refresh cycles, the RR field of the
SDRAM refresh control register (SDRCR) must be programmed. The EMIF will use this value along with
two internal counters to automatically perform auto refresh cycles at the required rate. The auto refresh
cycles cannot be disabled, even if the EMIF is not interfaced with an SDRAM. The remainder of this
section details the EMIF's refresh scheme and provides an example for determining the appropriate value
to place in the RR field of SDRCR.
The two counters used to perform auto-refresh cycles are a 13-bit refresh interval counter and a 4-bit
refresh backlog counter. At reset and upon writing to the RR field, the refresh interval counter is loaded
with the value from RR field and begins decrementing, by one, each EMIF clock cycle. When the refresh
interval counter reaches zero, the following actions occur:
• The refresh interval counter is reloaded with the value from the RR field and restarts decrementing.
• The 4-bit refresh backlog counter increments unless it has already reached its maximum value.
The refresh backlog counter records the number of auto refresh cycles that the EMIF currently has
outstanding. This counter is decremented by one each time an auto refresh cycle is performed and
incremented by one each time the refresh interval counter expires. The refresh backlog counter saturates
at the values of 0000b and 1111b. The EMIF uses the refresh backlog counter to determine the urgency
with which an auto refresh cycle should be performed. The four levels of urgency are described in
Table 17-12. This refresh scheme allows the required refreshes to be performed with minimal impact on
access requests.
Table 17-12. Refresh Urgency Levels
Urgency Level
630
Refresh Backlog
Counter Range
Action Taken
Refresh May
1-3
An auto-refresh cycle is performed only if the EMIF has no requests pending and none
of the SDRAM banks are open.
Refresh Release
4-7
An auto-refresh cycle is performed if the EMIF has no requests pending, regardless of
whether any SDRAM banks are open.
Refresh Need
8-11
An auto-refresh cycle is performed at the completion of the current access unless
there are read requests pending.
Refresh Must
12-15
Multiple auto-refresh cycles are performed at the completion of the current access
until the Refresh Release urgency level is reached. At that point, the EMIF can begin
servicing any new read or write requests.
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17.2.5.6.1 Determining the Appropriate Value for the RR Field
The value that should be programmed into the RR field of SDRCR can be calculated by using the
frequency of the EMIF_CLK signal (fEMIF_CLK) and the required refresh rate of the SDRAM (fRefresh). The
following formula can be used:
RR = fEMIF_CLK / fRefresh
The SDRAM datasheet often communicates the required SDRAM Refresh Rate in terms of the number of
REFR commands required in a given time interval. The required SDRAM Refresh Rate in the formula
above can therefore be calculated by dividing the number of required cycles per time interval (ncycles) by
the time interval given in the datasheet (tRefresh Period) :
fRefresh = ncycles / tRefresh Period
Combining these formulas, the value that should be programmed into the RR field can be computed as:
RR = fEMIF_CLK × tRefresh Period / ncycles
The following example illustrates calculating the value of RR. Given that:
• fEMIF_CLK = 100 MHz (frequency of the EMIF clock)
• tRefresh Period = 64 ms (required refresh interval of the SDRAM)
• ncycles = 8192 (number of cycles in a refresh interval for the SDRAM)
RR can be calculated as:
RR = 100 MHz × 64 ms/8192
RR = 781.25
RR = 782 cycles = 30Eh cycles
17.2.5.7 Self-Refresh Mode
The EMIF can be programmed to enter the self-refresh state by setting the SR bit of SDCR to 1. This will
cause the EMIF to issue the SLFR command after completing any outstanding SDRAM access requests
and clearing the refresh backlog counter by performing one or more auto refresh cycles. This places the
attached SDRAM device into self-refresh mode in which it consumes a minimal amount of power while
performing its own refresh cycles. The SR bit should be set and cleared using a byte-write to the upper
byte of the SDRAM configuration register (SDCR) to avoid triggering the SDRAM initialization sequence.
While in the self-refresh state, the EMIF continues to service asynchronous bank requests and register
accesses as normal, with one caveat. The EMIF will not park the data bus following a read to
asynchronous memory while in the self-refresh state. Instead, the EMIF tri-states the data bus. Therefore,
it is not recommended to perform asynchronous read operations while the EMIF is in the self-refresh state,
in order to prevent floating inputs on the data bus. More information about data bus parking can be found
in Section 17.2.7.
The EMIF will exit from the self-refresh state if either of the following events occur:
• The SR bit of SDCR is cleared to 0.
• An SDRAM accesses is requested.
The EMIF exits from the self-refresh state by driving EMIF_CKE high and performing an auto refresh
cycle.
The attached SDRAM device should also be placed into Self-Refresh Mode when changing the frequency
of EMIF_CLK. If the frequency of EMIF_CLK changes while the SDRAM is not in Self-Refresh Mode,
Procedure B in Section 17.2.5.5 should be followed to reinitialize the device.
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17.2.5.8 Power Down Mode
To support low-power modes, the EMIF can be requested to issue a POWER DOWN command to the
SDRAM by setting the PD bit in the SDRAM configuration register (SDCR). When this bit is set, the EMIF
will continue normal operation until all outstanding memory access requests have been serviced and the
SDRAM refresh backlog (if there is one) has been cleared. At this point the EMIF will enter the powerdown state. Upon entering this state, the EMIF will issue a POWER DOWN command (same as a NOP
command but driving EMIF_CKE low on the same cycle). The EMIF then maintains EMIF_CKE low until it
exits the power-down state.
Since the EMIF services the refresh backlog before it enters the power-down state, all internal banks of
the SDRAM are closed (precharged) prior to issuing the POWER DOWN command. Therefore, the EMIF
only supports Precharge Power Down. The EMIF does not support Active Power Down, where internal
banks of the SDRAM are open (active) before the POWER DOWN command is issued.
During the power-down state, the EMIF services the SDRAM, asynchronous memory, and register
accesses as normal, returning to the power-down state upon completion.
The PDWR bit in SDCR indicates whether the EMIF should perform refreshes in power-down state. If the
PDWR bit is set, the EMIF exits the power-down state every time the Refresh Must level is set, performs
AUTO REFRESH commands to the SDRAM, and returns back to the power-down state. This evenly
distributes the refreshes to the SDRAM in power-down state. If the PDWR bit is not set, the EMIF does
not perform any refreshes to the SDRAM. Therefore, the data integrity of the SDRAM is not assured upon
power down exit if the PDWR bit is not set.
If the PD bit is cleared while in the power-down state, the EMIF will come out of the power-down state.
The EMIF:
• Drives EMIF_CKE high.
• Enters its idle state.
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17.2.5.9 SDRAM Read Operation
When the EMIF receives a read request to SDRAM from one of the requesters listed in Section 17.2.2, it
performs one or more read access cycles. A read access cycle begins with the issuing of the ACTV
command to select the desired bank and row of the SDRAM device. After the row has been opened, the
EMIF proceeds to issue a READ command while specifying the desired bank and column address.
EMIF_A[10] is held low during the READ command to avoid auto-precharging. The READ command
signals the SDRAM device to start bursting data from the specified address while the EMIF issues NOP
commands. Following a READ command, the CL field of the SDRAM configuration register (SDCR)
defines how many delay cycles will be present before the read data appears on the data bus. This is
referred to as the CAS latency.
Figure 17-5 shows the signal waveforms for a basic SDRAM read operation in which a burst of data is
read from a single page. When the EMIF SDRAM interface is configured to 16 bit by setting the NM bit of
the SDRAM configuration register (SDCR) to 1, a burst size of eight is used. Figure 17-5 shows a burst
size of eight.
The EMIF will truncate a series of bursting data if the remaining addresses of the burst are not required to
complete the request. The EMIF can truncate the burst in three ways:
• By issuing another READ to the same page in the same bank.
• By issuing a PRE command in order to prepare for accessing a different page of the same bank.
• By issuing a BT command in order to prepare for accessing a page in a different bank.
Figure 17-5. Timing Waveform for Basic SDRAM Read Operation
CL=3
ACTV
READ
EMIF_CLK
EMIF_nCS[0]
EMIF_nDQM
Bank
EMIF_BA
EMIF_A
Row
EMIF_D
Col
D1
D2
D3
D4
D5
D6
D7
D8
EMIF_nRAS
EMIF_nCAS
EMIF_nWE
Several other pins are also active during a read access. The EMIF_nDQM[1:0] pins are driven low during
the READ commands and are kept low during the NOP commands that correspond to the burst request.
The state of the other EMIF pins during each command can be found in Table 17-5.
The EMIF schedules its commands based on the timing information that is provided to it in the SDRAM
timing register (SDTIMR). The values for the timing parameters in this register should be chosen to satisfy
the timing requirements listed in the SDRAM datasheet. The EMIF uses this timing information to avoid
violating any timing constraints related to issuing commands. This is commonly accomplished by inserting
NOP commands between various commands during an access. Refer to the register description of
SDTIMR in Section 17.3.6 for more details on the various timing parameters.
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17.2.5.10 SDRAM Write Operations
When the EMIF receives a write request to SDRAM from one of the requesters listed in Section 17.2.2, it
performs one or more write-access cycles. A write-access cycle begins with the issuing of the ACTV
command to select the desired bank and row of the SDRAM device. After the row has been opened, the
EMIF proceeds to issue a WRT command while specifying the desired bank and column address.
EMIF_A[10] is held low during the WRT command to avoid auto-precharging. The WRT command signals
the SDRAM device to start writing a burst of data to the specified address while the EMIF issues NOP
commands. The associated write data will be placed on the data bus in the cycle concurrent with the WRT
command and with subsequent burst continuation NOP commands.
Figure 17-6 shows the signal waveforms for a basic SDRAM write operation in which a burst of data is
read from a single page. When the EMIF SDRAM interface is configured to 16-bit by setting the NM bit of
the SDRAM configuration register (SDCR) to 1, a burst size of eight is used. Figure 17-6 shows a burst
size of eight.
Figure 17-6. Timing Waveform for Basic SDRAM Write Operation
ACTV
WRT
EMIF_CLK
EMIF_nCS[0]
EMIF_nDQM
EMIF_BA
EMIF_A
Bank
Row
EMIF_D
Column
D1
D2
D3
D4
D5
D6
D7
D8
EMIF_nRAS
EMIF_nCAS
EMIF_nWE
The EMIF will truncate a series of bursting data if the remaining addresses of the burst are not part of the
write request. The EMIF can truncate the burst in three ways:
• By issuing another WRT to the same page
• By issuing a PRE command in order to prepare for accessing a different page of the same bank
• By issuing a BT command in order to prepare for accessing a page in a different bank
Several other pins are also active during a write access. The EMIF_nDQM[1:0] pins are driven to select
which bytes of the data word will be written to the SDRAM device. They are also used to mask out entire
undesired data words during a burst access. The state of the other EMIF pins during each command can
be found in Table 17-5.
The EMIF schedules its commands based on the timing information that is provided to it in the SDRAM
timing register (SDTIMR). The values for the timing parameters in this register should be chosen to satisfy
the timing requirements listed in the SDRAM datasheet. The EMIF uses this timing information to avoid
violating any timing constraints related to issuing commands. This is commonly accomplished by inserting
NOP commands during various cycles of an access. Refer to the register description of SDTIMR in
Section 17.3.6 for more details on the various timing parameters.
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17.2.5.11 Mapping from Logical Address to EMIF Pins
When the EMIF receives an SDRAM access request, it must convert the address of the access into the
appropriate signals to send to the SDRAM device. The details of this address mapping are shown in
Table 17-13 for 16-bit operation. Using the settings of the IBANK and PAGESIZE fields of the SDRAM
configuration register (SDCR), the EMIF determines which bits of the logical address will be mapped to
the SDRAM row, column, and bank addresses.
As the logical address is incremented by one halfword (16-bit operation), the column address is likewise
incremented by one until a page boundary is reached. When the logical address increments across a
page boundary, the EMIF moves into the same page in the next bank of the attached device by
incrementing the bank address EMIF_BA and resetting the column address. The page in the previous
bank is left open until it is necessary to close it. This method of traversal through the SDRAM banks helps
maximize the number of open banks inside of the SDRAM and results in an efficient use of the device.
There is no limitation on the number of banks that can be open at one time, but only one page within a
bank can be open at a time.
The EMIF uses the EMIF_nDQM[1:0] pins during a WRT command to mask out selected bytes or entire
words. The EMIF_nDQM[1:0] pins are always low during a READ command.
Table 17-13. Mapping from Logical Address to EMIF Pins for 16-bit SDRAM
Logical Address
IBANK
PAGESIZE
0
0
1
0
2
0
0
1
1
1
2
1
0
2
1
2
2
2
0
3
1
3
2
3
31:27
26
25
24
23
22
21:14
13
12
-
EMIF_BA[1:0]
Row Address
-
EMIF_BA[0
]
Row Address
-
Row Address
-
EMIF_BA[1:0]
Row Address
-
EMIF_BA[0
]
Row Address
Row Address
-
-
9
EMIF_BA[0
]
Row Address
-
-
10
Row Address
-
-
11
Row Address
EMIF_BA[1:0]
Row Address
Row Address
Row Address
EMIF_BA[0
]
EMIF_BA[1:0]
8:1
0
Col Address
EMIF_nDQM[0]
Col Address
EMIF_nDQM[0]
Col Address
EMIF_nDQM[0]
Column Address
EMIF_nDQM[0]
Column Address
EMIF_nDQM[0]
Column Address
EMIF_nDQM[0]
Column Address
EMIF_nDQM[0]
Column Address
EMIF_nDQM[0]
Column Address
EMIF_nDQM[0]
Column Address
EMIF_nDQM[0]
Column Address
EMIF_nDQM[0]
Column Address
EMIF_nDQM[0]
NOTE: The upper bit of the Row Address is used only when addressing 256-Mbit and 512-Mbit
SDRAM memories.
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17.2.6 Asynchronous Controller and Interface
The EMIF easily interfaces to a variety of asynchronous devices including NOR Flash and SRAM. It can
be operated in two major modes (see Table 17-14):
• Normal Mode
• Select Strobe Mode
Table 17-14. Normal Mode vs. Select Strobe Mode
Mode
Function of EMIF_nDQM pins
Operation of EMIF_nCS[4:2]
Normal Mode
Byte enables
Active during the entire asynchronous access cycle
Select Strobe Mode
Byte enables
Active only during the strobe period of an access cycle
The first mode of operation is Normal Mode, in which the EMIF_nDQM pins of the EMIF function as byte
enables. In this mode, the EMIF_nCS[4:2] pins behaves as typical chip select signals, remaining active for
the duration of the asynchronous access. See Section 17.2.6.1 for an example interface with multiple 8-bit
devices.
The second mode of operation is Select Strobe Mode, in which the EMIF_nCS[4:2] pins act as a strobe,
active only during the strobe period of an access. In this mode, the EMIF_nDQM pins of the EMIF function
as standard byte enables for reads and writes. A summary of the differences between the two modes of
operation are shown in Table 17-14. Refer to Section 17.2.6.4 for the details of asynchronous operations
in Normal Mode, and to Section 17.2.6.5 for the details of asynchronous operations in Select Strobe
Mode. The EMIF hardware defaults to Normal Mode, but can be manually switched to Select Strobe Mode
by setting the SS bit in the asynchronous m (m = 1, 2, 3, or 4) configuration register (CEnCFG) (n = 2, 3,
or 4). Throughout the chapter, m can hold the values 1, 2, 3 or 4; and n can hold the values 2, 3, or 4.
The EMIF also provides configurable cycle timing parameters and an Extended Wait Mode that allows the
connected device to extend the strobe period of an access cycle. The following sections describe the
features related to interfacing with external asynchronous devices.
17.2.6.1 Interfacing to Asynchronous Memory
Figure 17-7 shows the EMIF's external pins used in interfacing with an asynchronous device. In
EMIF_nCS[n], n = 2, 3, or 4.
Figure 17-7. EMIF Asynchronous Interface
EMIF
EMIF_nCS[n]
EMIF_nWE
EMIF_nOE
EMIF_WAIT
EMIF_D[x:0]
EMIF_nDQM[x:0]
EMIF_A[x:0]
EMIF_BA[1:0]
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Of special note is the connection between the EMIF and the external device's address bus. The EMIF
address pin EMIF_A[0] always provides the least significant bit of a 32-bit word address. Therefore, when
interfacing to a 16-bit or 8-bit asynchronous device, the EMIF_BA[1] and EMIF_BA[0] pins provide the
least-significant bits of the halfword or byte address, respectively. Additionally, when the EMIF interfaces
to a 16-bit asynchronous device, the EMIF_BA[0] pin can serve as the upper address line EMIF_A[22].
Figure 17-8 and Figure 17-9 show the mapping between the EMIF and the connected device's data and
address pins for various programmed data bus widths. The data bus width may be configured in the
asynchronous n configuration register (CEnCFG).
Figure 17-9 shows a common interface between the EMIF and external asynchronous memory. Figure 179 shows an interface between the EMIF and an external memory with byte enables. The EMIF should be
operated in either Normal Mode or Select Strobe Mode when using this interface, so that the EMIF_nDQM
signals operate as byte enables.
Figure 17-8. EMIF to 8-bit/16-bit Memory Interface
EMIF
8−bit
asynchronous
memory
EMIF_D[7:0]
EMIF_A[x:0]
EMIF_BA[1:0]
DQ[7:0]
A[(x+2):2]
A[1:0]
a) EMIF to 8-bit memory interface
EMIF
16−bit asynchronous
memory
EMIF_D[15:0]
EMIF_A[x:0]
EMIF_BA[1]
DQ[15:0]
A[(x+1):1]
A[0]
b) EMIF to 16-bit memory interface
Figure 17-9. Common Asynchronous Interface
16−bit
asynchronous
device
EMIF
EMIF_nCS[n]
EMIF_nWE
EMIF_nDQM[1:0]
EMIF_D[15:0]
nCE
nWE
BE[1:0]
DQ[15:0]
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17.2.6.2 Accessing Larger Asynchronous Memories
The device has 22 dedicated EMIF address lines. If a device such as a large asynchronous flash needs to
be attached to the EMIF, then GPIO pins may be used to control the flash device’s upper address lines.
17.2.6.3 Configuring the EMIF for Asynchronous Accesses
The operation of the EMIF's asynchronous interface can be configured by programming the appropriate
register fields. The reset value and bit position for each register field can be found in Section 17.3. The
following tables list the register fields that can be programmed and describe the purpose of each field.
These registers can be programmed prior to accessing the external memory, and the transfer following a
write to these registers will use the new configuration.
Table 17-15. Description of the Asynchronous m Configuration Register (CEnCFG)
Parameter
Description
SS
Select Strobe mode. This bit selects the EMIF's mode of operation in the following way:
• SS = 0 selects Normal Mode
–
EMIF_nDQM pins function as byte enables
– EMIF_nCS[4:2] active for duration of access
• SS = 1 selects Select Strobe Mode
–
EMIF_nDQM pins function as byte enables
–
EMIF_nCS[4:2] acts as a strobe.
EW
Extended Wait Mode enable.
• EW = 0 disables Extended Wait Mode
• EW = 1 enables Extended Wait Mode
When set to 1, the EMIF enables its Extended Wait Mode in which the strobe width of an access
cycle can be extended in response to the assertion of the EMIF_nWAIT pin. The WPn bit in the
asynchronous wait cycle configuration register (AWCC) controls to polarity of EMIF_nWAIT pin.
See Section 17.2.6.6 for more details on this mode of operation.
W_SETUP/R_SETUP
Read/Write setup widths.
These fields define the number of EMIF clock cycles of setup time for the address pins (EMIF_A
and EMIF_BA), byte enables (EMIF_nDQM), and asynchronous chip enable (EMIF_nCS[4:2])
before the read strobe pin (EMIF_nOE) or write strobe pin (EMIF_nWE) falls, minus one cycle.
For writes, the W_SETUP field also defines the setup time for the data pins (EMIF_D). Refer to
the datasheet of the external asynchronous device to determine the appropriate setting for this
field.
W_STROBE/R_STROBE
Read/Write strobe widths.
These fields define the number of EMIF clock cycles between the falling and rising of the read
strobe pin (EMIF_nOE) or write strobe pin (EMIF_nWE), minus one cycle. If Extended Wait Mode
is enabled by setting the EW field in the asynchronous n configuration register (CEnCFG), these
fields must be set to a value greater than zero. Refer to the datasheet of the external
asynchronous device to determine the appropriate setting for this field.
W_HOLD/R_HOLD
Read/Write hold widths.
These fields define the number of EMIF clock cycles of hold time for the address pins (EMIF_A
and EMIF_BA), byte enables (EMIF_nDQM), and asynchronous chip enable (EMIF_nCS[4:2])
after the read strobe pin (EMIF_nOE) or write strobe pin (EMIF_nWE) rises, minus one cycle. For
writes, the W_HOLD field also defines the hold time for the data pins (EMIF_D). Refer to the
datasheet of the external asynchronous device to determine the appropriate setting for this field.
TA
Minimum turnaround time.
This field defines the minimum number of EMIF clock cycles between asynchronous reads and
writes, minus one cycle. The purpose of this feature is to avoid contention on the bus. The value
written to this field also determines the number of cycles that will be inserted between
asynchronous accesses and SDRAM accesses. Refer to the datasheet of the external
asynchronous device to determine the appropriate setting for this field.
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Table 17-15. Description of the Asynchronous m Configuration Register (CEnCFG) (continued)
Parameter
Description
ASIZE
Asynchronous Device Bus Width.
This field determines the data bus width of the asynchronous interface in the following way:
• ASIZE = 0 selects an 8-bit bus
• ASIZE = 1 selects a 16-bit bus
The configuration of ASIZE determines the function of the EMIF_A and EMIF_BA pins as
described in Section 17.2.6.1. This field also determines the number of external accesses
required to fulfill a request generated by one of the sources mentioned in Section 17.2.2. For
example, a request for a 32-bit word would require four external access when ASIZE = 0. Refer to
the datasheet of the external asynchronous device to determine the appropriate setting for this
field.
Table 17-16. Description of the Asynchronous Wait Cycle Configuration Register (AWCC)
Parameter
Description
WPn
EM_WAIT Polarity.
• WPn = 0 selects active-low polarity
• WPn = 1 selects active-high polarity
When set to 1, the EMIF will wait if the EMIF_nWAIT pin is high. When cleared to 0, the EMIF will
wait if the EMIF_nWAIT pin is low. The EMIF must have the Extended Wait Mode enabled for the
EMIF_nWAIT pin to affect the width of the strobe period.
MAX_EXT_WAIT
Maximum Extended Wait Cycles.
This field configures the number of EMIF clock cycles the EMIF will wait for the EMIF_nWAIT pin
to be deactivated during the strobe period of an access cycle. The maximum number of EMIF
clock cycles it will wait is determined by the following formula:
Maximum Extended Wait Cycles = (MAX_EXT_WAIT + 1) × 16
If the EMIF_nWAIT pin is not deactivated within the time specified by this field, the EMIF resumes
the access cycle, registering whatever data is on the bus and proceeding to the hold period of the
access cycle. This situation is referred to as an Asynchronous Timeout. An Asynchronous
Timeout generates an interrupt, if it has been enabled in the EMIF interrupt mask set register
(INTMSKSET). Refer to Section 17.2.9.1 for more information about the EMIF interrupts.
Table 17-17. Description of the EMIF Interrupt Mask Set Register (INTMSKSET)
Parameter
Description
WR_MASK_SET
Wait Rise Mask Set.
Writing a 1 enables an interrupt to be generated when a rising edge on EMIF_nWAIT occurs
AT_MASK_SET
Asynchronous Timeout Mask Set.
Writing a 1 to this bit enables an interrupt to be generated when an Asynchronous Timeout
occurs.
Table 17-18. Description of the EMIF Interrupt Mast Clear Register (INTMSKCLR)
Parameter
Description
WR_MASK_CLR
Wait Rise Mask Clear.
Writing a 1 to this bit disables the interrupt, clearing the WR_MASK_SET bit in the EMIF interrupt
mask set register (INTMSKSET).
AT_MASK_CLR
Asynchronous Timeout Mask Clear.
Writing a 1 to this bit prevents an interrupt from being generated when an Asynchronous Timeout
occurs.
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17.2.6.4 Read and Write Operations in Normal Mode
Normal Mode is the asynchronous interface's default mode of operation. It is selected when the SS bit in
the asynchronous n configuration register (CEnCFG) is cleared to 0. In this mode, the EMIF_nDQM pins
operate as byte enables. Section 17.2.6.4.1 and Section 17.2.6.4.2 explain the details of read and write
operations while in Normal Mode.
17.2.6.4.1 Asynchronous Read Operations (Normal Mode)
NOTE: During an entire asynchronous read operation, the EMIF_nWE pin is driven high.
An asynchronous read is performed when any of the requesters mentioned in Section 17.2.2 request a
read from the attached asynchronous memory. After the request is received, a read operation is initiated
once it becomes the EMIF's highest priority task, according to the priority scheme detailed in
Section 17.2.13. In the event that the read request cannot be serviced by a single access cycle to the
external device, multiple access cycles will be performed by the EMIF until the entire request is fulfilled.
The details of an asynchronous read operation in Normal Mode are described in Table 17-19. Also,
Figure 17-10 shows an example timing diagram of a basic read operation.
Table 17-19. Asynchronous Read Operation in Normal Mode
Time Interval
Pin Activity in Normal Mode
Turn-around
period
Once the read operation becomes the highest priority task for the EMIF, the EMIF waits for the programmed
number of turn-around cycles before proceeding to the setup period of the operation. The number of wait cycles is
taken directly from the TA field of the asynchronous n configuration register (CEnCFG). There are two exceptions
to this rule:
• If the current read operation was directly proceeded by another read operation, no turnaround cycles are
inserted.
• If the current read operation was directly proceeded by a write operation and the TA field has been cleared
to 0, one turn-around cycle will be inserted.
After the EMIF has waited for the turnaround cycles to complete, it again checks to make sure that the read
operation is still its highest priority task. If so, the EMIF proceeds to the setup period of the operation. If it is no
longer the highest priority task, the EMIF terminates the operation.
Start of the
setup period
The following actions occur at the start of the setup period:
• The setup, strobe, and hold values are set according to the R_SETUP, R_STROBE, and R_HOLD values in
CEnCFG.
• The address pins EMIF_A and EMIF_BA become valid and carry the values described in Section 17.2.6.1.
• EMIF_nCS[4:2] falls to enable the external device (if not already low from a previous operation)
Strobe period
The following actions occur during the strobe period of a read operation:
1.
2.
EMIF_nOE falls at the start of the strobe period
On the rising edge of the clock which is concurrent with the end of the strobe period:
•
EMIF_nOE rises
•
The data on the EMIF_D bus is sampled by the EMIF.
In Figure 17-10, EMIF_nWAIT is inactive. If EMIF_nWAIT is instead activated, the strobe period can be extended
by the external device to give it more time to provide the data. Section 17.2.6.6 contains more details on using the
EMIF_nWAIT pin.
End of the hold At the end of the hold period:
period
• The address pins EMIF_A and EMIF_BA become invalid
• EMIF_nCS[4:2] rises (if no more operations are required to complete the current request)
EMIF may be required to issue additional read operations to a device with a small data bus width in order to
complete an entire word access. In this case, the EMIF immediately re-enters the setup period to begin another
operation without incurring the turn-round cycle delay. The setup, strobe, and hold values are not updated in this
case. If the entire word access has been completed, the EMIF returns to its previous state unless another
asynchronous request has been submitted and is currently the highest priority task. If this is the case, the EMIF
instead enters directly into the turnaround period for the pending read or write operation.
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Figure 17-10. Timing Waveform of an Asynchronous Read Cycle in Normal Mode
Setup
2
Strobe
3
Hold
2
EMIF_CLK
EMIF_nCS[n]
EMIF_nDQM
EMIF_A/EMIF_BA
Byte enable
Address
EMIF_D
Data
EMIF_nOE
EMIF_nWE
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17.2.6.4.2 Asynchronous Write Operations (Normal Mode)
NOTE:
During an entire asynchronous write operation, the EMIF_nOE pin is driven high.
An asynchronous write is performed when any of the requesters mentioned in Section 17.2.2 request a
write to memory in the asynchronous bank of the EMIF. After the request is received, a write operation is
initiated once it becomes the EMIF's highest priority task, according to the priority scheme detailed in
Section 17.2.13. In the event that the write request cannot be serviced by a single access cycle to the
external device, multiple access cycles will be performed by the EMIF until the entire request is fulfilled.
The details of an asynchronous write operation in Normal Mode are described in Table 17-20. Also,
Figure 17-11 shows an example timing diagram of a basic write operation.
Table 17-20. Asynchronous Write Operation in Normal Mode
Time Interval
Pin Activity in Normal Mode
Turnaround
period
Once the write operation becomes the highest priority task for the EMIF, the EMIF waits for the programmed
number of turn-around cycles before proceeding to the setup period of the operation. The number of wait cycles is
taken directly from the TA field of the asynchronous n configuration register (CEnCFG). There are two exceptions
to this rule:
• If the current write operation was directly proceeded by another write operation, no turn-around cycles are
inserted.
• If the current write operation was directly proceeded by a read operation and the TA field has been cleared
to 0, one turnaround cycle will be inserted.
After the EMIF has waited for the turn-around cycles to complete, it again checks to make sure that the write
operation is still its highest priority task. If so, the EMIF proceeds to the setup period of the operation. If it is no
longer the highest priority task, the EMIF terminates the operation.
Start of the
setup period
The following actions occur at the start of the setup period:
• The setup, strobe, and hold values are set according to the W_SETUP, W_STROBE, and W_HOLD values
in CEnCFG.
• The address pins EMIF_A and EMIF_BA and the data pins EMIF_D become valid. The EMIF_A and
EMIF_BA pins carry the values described in Section 17.2.6.1.
• EMIF_nCS[4:2] falls to enable the external device (if not already low from a previous operation).
Strobe period
The following actions occur at the start of the strobe period of a write operation:
1. EMIF_nWE falls
2. The EMIF_nDQM pins become valid as byte enables.
The following actions occur on the rising edge of the clock which is concurrent with the end of the strobe period:
1. EMIF_nWE rises
2. The EMIF_nDQM pins deactivate
In Figure 17-11, EMIF_nWAIT is inactive. If EMIF_nWAIT is instead activated, the strobe period can be extended
by the external device to give it more time to accept the data. Section 17.2.6.6 contains more details on using the
EMIF_nWAIT pin.
End of the hold At the end of the hold period:
period
• The address pins EMIF_A and EMIF_BA become invalid
• The data pins become invalid
• EMIF_nCS[n] (n = 2, 3, or 4) rises (if no more operations are required to complete the current request)
The EMIF may be required to issue additional write operations to a device with a small data bus width in order to
complete an entire word access. In this case, the EMIF immediately re-enters the setup period to begin another
operation without incurring the turnaround cycle delay. The setup, strobe, and hold values are not updated in this
case. If the entire word access has been completed, the EMIF returns to its previous state unless another
asynchronous request has been submitted and is currently the highest priority task. If this is the case, the EMIF
instead enters directly into the turnaround period for the pending read or write operation.
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Figure 17-11. Timing Waveform of an Asynchronous Write Cycle in Normal Mode
Setup
2
Strobe
3
Hold
2
EMIF_CLK
EMIF_nCS[n]
EMIF_nDQM
EMIF_A/EMIF_BA
EMIF_D
Byte enable
Address
Data
EMIF_nOE
EMIF_nWE
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17.2.6.5 Read and Write Operation in Select Strobe Mode
Select Strobe Mode is the EMIF's second mode of operation. It is selected when the SS bit of the
asynchronous n configuration register (CEnCFG) is set to 1. In this mode, the EMIF_nDQM pins operate
as byte enables and the EMIF_nCS[n] (n = 2, 3, or 4) pin is only active during the strobe period of an
access cycle. Section 17.2.6.4.1 and Section 17.2.6.4.2 explain the details of read and write operations
while in Select Strobe Mode.
17.2.6.5.1 Asynchronous Read Operations (Select Strobe Mode)
NOTE:
During the entirety of an asynchronous read operation, the EMIF_nWE pin is driven high.
An asynchronous read is performed when any of the requesters mentioned in Section 17.2.2 request a
read from the attached asynchronous memory. After the request is received, a read operation is initiated
once it becomes the EMIF's highest priority task, according to the priority scheme detailed in
Section 17.2.13. In the event that the read request cannot be serviced by a single access cycle to the
external device, multiple access cycles will be performed by the EMIF until the entire request is fulfilled.
The details of an asynchronous read operation in Select Strobe Mode are described in Table 17-21. Also,
Figure 17-12 shows an example timing diagram of a basic read operation.
Table 17-21. Asynchronous Read Operation in Select Strobe Mode
Time Interval
Pin Activity in Select Strobe Mode
Turnaround
period
Once the read operation becomes the highest priority task for the EMIF, the EMIF waits for the programmed
number of turn-around cycles before proceeding to the setup period of the operation. The number of wait cycles is
taken directly from the TA field of the asynchronous n configuration register (CEnCFG). There are two exceptions
to this rule:
• If the current read operation was directly proceeded by another read operation, no turn-around cycles are
inserted.
• If the current read operation was directly proceeded by a write operation and the TA field has been cleared
to 0, one turn-around cycle will be inserted.
After the EMIF has waited for the turn-around cycles to complete, it again checks to make sure that the read
operation is still its highest priority task. If so, the EMIF proceeds to the setup period of the operation. If it is no
longer the highest priority task, the EMIF terminates the operation.
Start of the
setup period
The following actions occur at the start of the setup period:
• The setup, strobe, and hold values are set according to the R_SETUP, R_STROBE, and R_HOLD values in
CEnCFG.
• The address pins EMIF_A and EMIF_BA become valid and carry the values described in Section 17.2.6.1.
• The EMIF_nDQM pins become valid as byte enables.
Strobe period
The following actions occur during the strobe period of a read operation:
1.
2.
EMIF_nCS[n] (n = 2, 3, or 4) and EMIF_nOE fall at the start of the strobe period
On the rising edge of the clock which is concurrent with the end of the strobe period:
•
EMIF_nCS[n] (n = 2, 3, or 4) and EMIF_nOE rise
•
The data on the EMIF_D bus is sampled by the EMIF.
In Figure 17-12, EMIF_nWAIT is inactive. If EMIF_nWAIT is instead activated, the strobe period can be extended
by the external device to give it more time to provide the data. Section 17.2.6.6 contains more details on using the
EMIF_nWAIT pin.
End of the hold At the end of the hold period:
period
• The address pins EMIF_A and EMIF_BA become invalid
• The EMIF_nDQM pins become invalid
The EMIF may be required to issue additional read operations to a device with a small data bus width in order to
complete an entire word access. In this case, the EMIF immediately re-enters the setup period to begin another
operation without incurring the turnaround cycle delay. The setup, strobe, and hold values are not updated in this
case. If the entire word access has been completed, the EMIF returns to its previous state unless another
asynchronous request has been submitted and is currently the highest priority task. If this is the case, the EMIF
instead enters directly into the turnaround period for the pending read or write operation.
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Figure 17-12. Timing Waveform of an Asynchronous Read Cycle in Select Strobe Mode
Setup
2
Strobe
3
Hold
2
EMIF_CLK
EMIF_nCS[n]
EMIF_nDQM
EMIF_A/EMIF_BA
Byte enables
Address
Data
EMIF_D
EMIF_nOE
EMIF_nWE
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17.2.6.5.2 Asynchronous Write Operations (Select Strobe Mode)
NOTE: During the entirety of an asynchronous write operation, the EMIF_nOE pin is driven high.
An asynchronous write is performed when any of the requesters mentioned in Section 17.2.2 request a
write to memory in the asynchronous bank of the EMIF. After the request is received, a write operation is
initiated once it becomes the EMIF's highest priority task, according to the priority scheme detailed in
Section 17.2.13. In the event that the write request cannot be serviced by a single access cycle to the
external device, multiple access cycles will be performed by the EMIF until the entire request is fulfilled.
The details of an asynchronous write operation in Select Strobe Mode are described in Table 17-22. Also,
Figure 17-13 shows an example timing diagram of a basic write operation.
Table 17-22. Asynchronous Write Operation in Select Strobe Mode
Time Interval
Pin Activity in Select Strobe Mode
Turnaround
period
Once the write operation becomes the highest priority task for the EMIF, the EMIF waits for the programmed
number of turnaround cycles before proceeding to the setup period of the operation. The number of wait cycles is
taken directly from the TA field of the asynchronous n configuration register (CEnCFG). There are two exceptions
to this rule:
• If the current write operation was directly proceeded by another write operation, no turn-around cycles are
inserted.
• If the current write operation was directly proceeded by a read operation and the TA field has been cleared
to 0, one turnaround cycle will be inserted.
After the EMIF has waited for the turnaround cycles to complete, it again checks to make sure that the write
operation is still its highest priority task. If so, the EMIF proceeds to the setup period of the operation. If it is no
longer the highest priority task, the EMIF terminates the operation.
Start of the
setup period
The following actions occur at the start of the setup period:
• The setup, strobe, and hold values are set according to the W_SETUP, W_STROBE, and W_HOLD values
in CEnCFG.
• The address pins EMIF_A and EMIF_BA and the data pins EMIF_D become valid. The EMIF_A and
EMIF_BA pins carry the values described in Section 17.2.6.1.
• The EMIF_nDQM pins become active as byte enables.
Strobe period
The following actions occur at the start of the strobe period of a write operation:
• EMIF_nCS[n] (n = 2, 3, or 4) and EMIF_nWE fall
The following actions occur on the rising edge of the clock which is concurrent with the end of the strobe period:
• EMIF_nCS[n] (n = 2, 3, or 4) and EMIF_nWE rise
In Figure 17-13, EMIF_nWAIT is inactive. If EMIF_nWAIT is instead activated, the strobe period can be extended
by the external device to give it more time to accept the data. Section 17.2.6.6 contains more details on using the
EMIF_nWAIT pin.
End of the hold At the end of the hold period:
period
• The address pins EMIF_A and EMIF_BA become invalid
• The data pins become invalid
• The EMIF_nDQM pins become invalid
The EMIF may be required to issue additional write operations to a device with a small data bus width in order to
complete an entire word access. In this case, the EMIF immediately re-enters the setup period to begin another
operation without incurring the turnaround cycle delay. The setup, strobe, and hold values are not updated in this
case. If the entire word access has been completed, the EMIF returns to its previous state unless another
asynchronous request has been submitted and is currently the highest priority task. If this is the case, the EMIF
instead enters directly into the turn-around period for the pending read or write operation.
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Figure 17-13. Timing Waveform of an Asynchronous Write Cycle in Select Strobe Mode
Setup
2
Strobe
3
Hold
2
EMIF_CLK
EMIF_nCS[n]
EMIF_nDQM
Byte enables
EMIF_A/EMIF_BA
Address
Data
EMIF_D
EMIF_nOE
EMIF_nWE
17.2.6.6 Extended Wait Mode and the EMIF_nWAIT Pin
The EMIF supports the Extend Wait Mode. This is a mode in which the external asynchronous device may
assert control over the length of the strobe period. The Extended Wait Mode can be entered by setting the
EW bit in the asynchronous n configuration register (CEnCFG) (n = 2, 3, or 4). When this bit is set, the
EMIF monitors the EMIF_nWAIT pin to determine if the attached device wishes to extend the strobe
period of the current access cycle beyond the programmed number of clock cycles.
When the EMIF detects that the EMIF_nWAIT pin has been asserted, it will begin inserting extra strobe
cycles into the operation until the EMIF_nWAIT pin is deactivated by the external device. The EMIF will
then return to the last cycle of the programmed strobe period and the operation will proceed as usual from
this point. Please refer to the device data manual for details on the timing requirements of the
EMIF_nWAIT signal.
The EMIF_nWAIT pin cannot be used to extend the strobe period indefinitely. The programmable
MAX_EXT_WAIT field in the asynchronous wait cycle configuration register (AWCC) determines the
maximum number of EMIF_CLK cycles the strobe period may be extended beyond the programmed
length. When the counter expires, the EMIF proceeds to the hold period of the operation regardless of the
state of the EMIF_nWAIT pin. The EMIF can also generate an interrupt upon expiration of this counter.
See Section 17.2.9.1 for details on enabling this interrupt.
For the EMIF to function properly in the Extended Wait mode, the WPn bit of AWCC must be programmed
to match the polarity of the EMIF_nWAIT pin. In its reset state of 1, the EMIF will insert wait cycles when
the EMIF_nWAIT pin is sampled high. When set to 0, the EMIF will insert wait cycles only when
EMIF_nWAIT is sampled low. This programmability allows for a glueless connection to larger variety of
asynchronous devices.
Finally, a restriction is placed on the strobe period timing parameters when operating in Extended Wait
mode. Specifically, the sum of the W_SETUP and W_STROBE fields must be greater than 4, and the sum
of the R_SETUP and R_STROBE fields must be greater than 4 for the EMIF to recognize the
EMIF_nWAIT pin has been asserted. The W_SETUP, W_STROBE, R_SETUP, and R_STROBE fields are
in CEnCFG.
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17.2.6.7 NOR Flash Page Mode
EMIF supports Page mode reads for NOR Flash on its asynchronous memory chip selects. This mode can
be enabled by writing a 1 to the CSn_PG_MD_EN (n = 2, 3, or 4) field in the Page Mode Control register
for the chip select in consideration. Whenever Page Mode for reads is enabled for a particular chip select,
the page size for the device connected must also be programmed in the CSn_PG_SIZE field of the Page
Mode Control register. The address change to valid read data available timing must be programmed in the
CSn_PG_DEL field of the Page Control register. All other asynchronous memory timings must be
programmed in the asynchronous configuration register (CEnCFG). See Figure 17-14 for read in
asynchronous page mode.
NOTE: The Extended Wait mode and the Select Strobe mode must be disabled when using the
asynchronous interface in Page mode.
Figure 17-14. Asynchronous Read in Page Mode
Setup
Strobe
pg_delay
pg_delay
A1
A2
Hold
pg_delay
EMIF_CLK
EMIF_nCS[n]
EMIF_nDQM
EMIF_A/EMIF_BA
EMIF_D
A0
D0
D1
A3
D2
D3
EMIF_nOE
EMIF_nWE
17.2.7 Data Bus Parking
The EMIF always drives the data bus to the previous write data value when it is idle. This feature is called
data bus parking. Only when the EMIF issues a read command to the external memory does it stop
driving the data bus. After the EMIF latches the last read data, it immediately parks the data bus again.
The one exception to this behavior occurs after performing an asynchronous read operation while the
EMIF is in the self-refresh state. In this situation, the read operation is not followed by the EMIF parking
the data bus. Instead, the EMIF tri-states the data bus. Therefore, it is not recommended to perform
asynchronous read operations while the EMIF is in the self-refresh state, in order to prevent floating inputs
on the data bus. External pull-ups, such as 10kΩ resistors, should be placed on the 16 EMIF data bus
pins (which do not have internal pull-ups) if it is required to perform reads in this situation. The precise
resistor value should be chosen so that the worst case combined off-state leakage currents do not cause
the voltage levels on the associated pins to drop below the high-level input voltage requirement.
For information about the self-refresh state, see Section 17.2.5.7.
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17.2.8 Reset and Initialization Considerations
The EMIF memory controller has two active-low reset signals, CHIP_RST_n and MOD_G_RST_n. Both
these reset signals are driven by the device system reset signal. This device does not offer the flexibility to
reset just the EMIF state machine without also resetting the EMIF controller's memory-mapped registers.
As soon as the device system reset is released (driven High), the EMIF memory controller immediately
begins its initialization sequence. Command and data stored in the EMIF memory controller FIFOs are
lost. Refer the Architecture chapter of the tecnical reference manual (TRM) for more information on
conditions that can cause a device system reset to be asserted.
When system reset is released, the EMIF automatically begins running the SDRAM initialization sequence
described in Section 17.2.5.4. Even though the initialization procedure is automatic, a special procedure,
found in Section 17.2.5.5 must still be followed.
17.2.9 Interrupt Support
The EMIF supports a single interrupt to the CPU. Section 17.2.9.1 details the generation and internal
masking of EMIF interrupts.
17.2.9.1 Interrupt Events
There are three conditions that may cause the EMIF to generate an interrupt to the CPU. These conditions
are:
• A rising edge on the EMIF_nWAIT signal (wait rise interrupt)
• An asynchronous time out
• Usage of unsupported addressing mode (line trap interrupt)
The wait rise interrupt occurs when a rising edge is detected on EMIF_nWAIT signal. This interrupt
generation is not affected by the WPn bit in the asynchronous wait cycle configuration register (AWCC).
The asynchronous time out interrupt condition occurs when the attached asynchronous device fails to
deassert the EMIF_nWAIT pin within the number of cycles defined by the MAX_EXT_WAIT bit in AWCC
(this happens only in extended wait mode). EMIF supports only linear incrementing and cache line wrap
addressing modes . If an access request for an unsupported addressing mode is received, the EMIF will
set the LT bit in the EMIF interrupt raw register (INTRAW) and treat the request as a linear incrementing
request.
Only when the interrupt is enabled by setting the appropriate bit
(WR_MASK_SET/AT_MASK_SET/LT_MASK_SET) in the EMIF interrupt mask set register (INTMSKSET)
to 1, will the interrupt be sent to the CPU. Once enabled, the interrupt may be disabled by writing a 1 to
the corresponding bit in the EMIF interrupt mask clear register (INTMSKCLR). The bit fields in both the
INTMSKSET and INTMSKCLR may be used to indicate whether the interrupt is enabled. When the
interrupt is enabled, the corresponding bit field in both the INTMSKSET and INTMSKCLR will have a
value of 1; when the interrupt is disabled, the corresponding bit field will have a value of 0.
The EMIF interrupt raw register (INTRAW) and the EMIF interrupt mask register (INTMSK) indicate the
status of each interrupt. The appropriate bit (WR/AT/LT) in INTRAW is set when the interrupt condition
occurs, whether or not the interrupt has been enabled. However, the appropriate bit
(WR_MASKED/AT_MASKED/LT_MASKED) in INTMSK is set only when the interrupt condition occurs
and the interrupt is enabled. Writing a 1 to the bit in INTRAW clears the INTRAW bit as well as the
corresponding bit in INTMSK. Table 17-23 contains a brief summary of the interrupt status and control bit
fields. See Section 17.3 for complete details on the register fields.
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Table 17-23. Interrupt Monitor and Control Bit Fields
Register Name
Bit Name
EMIF interrupt raw register (INTRAW) WR
EMIF interrupt mask register
(INTMSK)
EMIF interrupt mask set register
(INTMSKSET)
EMIF interrupt mask clear register
(INTMSKCLR)
Description
This bit is set when an rising edge on the EMIF_nWAIT signal occurs. Writing
a 1 clears the WR bit as well as the WR_MASKED bit in INTMSK.
AT
This bit is set when an asynchronous timeout occurs. Writing a 1 clears the
AT bit as well as the AT_MASKED bit in INTMSK.
LT
This bit is set when an unsupported addressing mode is used. Writing a 1
clears LT bit as well as the LT_MASKED bit in INTMSK.
WR_MASKED
This bit is set only when a rising edge on the EMIF_nWAIT signal occurs and
the interrupt has been enabled by writing a 1 to the WR_MASK_SET bit in
INTMSKSET.
AT_MASKED
This bit is set only when an asynchronous timeout occurs and the interrupt
has been enabled by writing a 1 to the AT_MASK_SET bit in INTMSKSET.
LT_MASKED
This bit is set only when line trap interrupt occurs and the interrupt has been
enabled by writing a 1 to the LT_MASK_SET bit in INTMSKSET.
WR_MASK_SET
Writing a 1 to this bit enables the wait rise interrupt.
AT_MASK_SET
Writing a 1 to this bit enables the asynchronous timeout interrupt.
LT_MASK_SET
Writing a 1 to this bit enables the line trap interrupt.
WR_MASK_CLR
Writing a 1 to this bit disables the wait rise interrupt.
AT_MASK_CLR
Writing a 1 to this bit disables the asynchronous timeout interrupt.
LT_MASK_CLR
Writing a 1 to this bit disables the line trap interrupt.
17.2.10 DMA Event Support
EMIF memory controller is a DMA slave peripheral and therefore does not generate DMA events. Data
read and write requests may be made directly, by masters and the DMA.
17.2.11 EMIF Signal Multiplexing
For details on EMIF signal multiplexing, see the I/O Multiplexing Module chapter of the technical reference
manual.
17.2.12 Memory Map
For information describing the device memory-map, see your device-specific datasheet.
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17.2.13 Priority and Arbitration
Section 17.2.2 describes the external prioritization and arbitration among requests from different sources
within the microcontroller. The result of this external arbitration is that only one request is presented to the
EMIF at a time. Once the EMIF completes a request, the external arbiter then provides the EMIF with the
next pending request.
Internally, the EMIF undertakes memory device transactions according to a strict priority scheme. The
highest priority events are:
• A device reset.
• A write to any of the three least significant bytes of the SDRAM configuration register (SDCR).
Either of these events will cause the EMIF to immediately commence its initialization sequence as
described in Section 17.2.5.4.
Once the EMIF has completed its initialization sequence, it performs memory transactions according to the
following priority scheme (highest priority listed first):
1. If the EMIF's backlog refresh counter is at the Refresh Must urgency level, the EMIF performs multiple
SDRAM auto refresh cycles until the Refresh Release urgency level is reached.
2. If an SDRAM or asynchronous read has been requested, the EMIF performs a read operation.
3. If the EMIF's backlog refresh counter is at the Refresh Need urgency level, the EMIF performs an
SDRAM auto refresh cycle.
4. If an SDRAM or asynchronous write has been requested, the EMIF performs a write operation.
5. If the EMIF's backlog refresh counter is at the Refresh May or Refresh Release urgency level, the
EMIF performs an SDRAM auto refresh cycle.
6. If the value of the SR bit in SDCR has been set to 1, the EMIF will enter the self-refresh state as
described in Section 17.2.5.7.
After taking one of the actions listed above, the EMIF then returns to the top of the priority list to determine
its next action.
Because the EMIF does not issue auto-refresh cycles when in the self-refresh state, the above priority
scheme does not apply when in this state. See Section 17.2.5.7 for details on the operation of the EMIF
when in the self-refresh state.
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17.2.14 System Considerations
This section describes various system considerations to keep in mind when operating the EMIF.
17.2.14.1 Asynchronous Request Times
In a system that interfaces to both SDRAM and asynchronous memory, the asynchronous requests must
not take longer than the smaller of the following two values:
• tRAS (typically 120 μs) - to avoid violating the maximum time allowed between issuing an ACTV and
PRE command to the SDRAM.
• tRefresh Rate × 11 (typically 15.7 μs × 11 = 172.7 μs) - to avoid refresh violations on the SDRAM.
The length of an asynchronous request is controlled by multiple factors, the primary factor being the
number of access cycles required to complete the request. For example, an asynchronous request for
4 bytes will require four access cycles using an 8-bit data bus and only two access cycle using a 16-bit
data bus. The maximum request size that the EMIF can be sent is 16 words, therefore the maximum
number of access cycles per memory request is 64 when the EMIF is configured with an 8-bit data
bus. The length of the individual access cycles that make up the asynchronous request is determined
by the programmed setup, strobe, hold, and turnaround values, but can also be extended with the
assertion of the EMIF_nWAIT input signal up to a programmed maximum limit. It is up to the user to
make sure that an entire asynchronous request does not exceed the timing values listed above when
also interfacing to an SDRAM device. This can be done by limiting the asynchronous timing
parameters.
17.2.14.2 Interface to External Peripheral or FIFO Memory
If EMIF is used to interface to an external peripheral or FIFO logic (for example, UHPI), it is recommended
to use the host CPU's Memory Protection Unit (MPU) to define this external memory range as a region
that is either strongly-ordered or of device type.
17.2.14.3 Interface to External SDRAM
If EMIF is used to interface to an external SDRAM, it is recommended to burst as much as possible to
normal memory to improve the interface bandwidth.
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17.2.15 Power Management
Power dissipation from the EMIF memory controller may be managed by following methods:
• Self-refresh mode
• Power-down mode
• Gating input clocks to the module off
Gating input clocks off to the EMIF memory controller achieves higher power savings when compared to
the power savings of self-refresh or power down mode. The input clock VCLK3 can be turned off through
the use of the Global Clock Module (GCM). Before gating clocks off, the EMIF memory controller must
place the SDR SDRAM memory in self-refresh mode. If the external memory requires a continuous clock,
the VCLK3 clock domain must not be turned off because this may result in data corruption. See the
following subsections for the proper procedures to follow when stopping the EMIF memory controller
clocks.
17.2.15.1 Power Management Using Self-Refresh Mode
The EMIF can be placed into a self-refresh state in order to place the attached SDRAM devices into selfrefresh mode, which consumes less power for most SDRAM devices. In this state, the attached SDRAM
device uses an internal clock to perform its own auto refresh cycles. This maintains the validity of the data
in the SDRAM without the need for any external commands. Refer to Section 17.2.5.7 for more details on
placing the EMIF into the self-refresh state.
17.2.15.2 Power Management Using Power Down Mode
In the power down mode, EMIF drives EMIF_CKE low to lower the power consumption. EMIF_CKE goes
high when there is a need to send refresh (REFR) commands, after which EMIF_CKE is again driven low.
EMIF_CKE remains low until any request arrives. Refer to Section 17.2.5.8 for more details on placing
EMIF in power down mode.
17.2.16 Emulation Considerations
EMIF memory controller remains fully functional during emulation halts in order to allow emulation access
to external memory.
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17.3 EMIF Registers
The external memory interface (EMIF) is controlled by programming its internal memory-mapped registers
(MMRs). Table 17-24 lists the memory-mapped registers for the EMIF.
NOTE: All EMIF MMRs, except SDCR, support only word (32-bit) accesses. Performing a byte (8bit) or halfword (16-bit) write to these registers results in undefined behavior. The SDCR is
byte writable to allow the setting of the SR, PD, and PDWR bits without triggering the
SDRAM initialization sequence.
The EMIF registers must always be accessed using 32-bit accesses (unless otherwise specified in this
chapter). The base address of the EMIF memory-mapped registers is FCFF E800h.
Table 17-24. External Memory Interface (EMIF) Registers
Offset
Acronym
Register Description
00h
MIDR
Module ID Register
Section 17.3.1
Section
04h
AWCC
Asynchronous Wait Cycle Configuration Register
Section 17.3.2
08h
SDCR
SDRAM Configuration Register
Section 17.3.3
0Ch
SDRCR
SDRAM Refresh Control Register
Section 17.3.4
10h
CE2CFG
Asynchronous 1 Configuration Register
Section 17.3.5
14h
CE3CFG
Asynchronous 2 Configuration Register
Section 17.3.5
18h
CE4CFG
Asynchronous 3 Configuration Register
Section 17.3.5
1Ch
CE5CFG
Asynchronous 4 Configuration Register
Section 17.3.5
20h
SDTIMR
SDRAM Timing Register
Section 17.3.6
3Ch
SDSRETR
SDRAM Self Refresh Exit Timing Register
Section 17.3.7
40h
INTRAW
EMIF Interrupt Raw Register
Section 17.3.8
44h
INTMSK
EMIF Interrupt Mask Register
Section 17.3.9
48h
INTMSKSET
EMIF Interrupt Mask Set Register
Section 17.3.10
4Ch
INTMSKCLR
EMIF Interrupt Mask Clear Register
Section 17.3.11
68h
PMCR
Page Mode Control Register
Section 17.3.12
17.3.1 Module ID Register (MIDR)
This is a read-only register indicating the module ID of the EMIF. The MIDR is shown in Figure 17-15 and
described in Table 17-25.
Figure 17-15. Module ID Register (MIDR) [offset = 00]
31
0
REV
R-x
LEGEND: R = Read only; -n = value after reset
Table 17-25. Module ID Register (MIDR) Field Descriptions
Bit
Field
Value
31-0
REV
x
654
Description
Module ID of EMIF. See the device-specific data manual.
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17.3.2 Asynchronous Wait Cycle Configuration Register (AWCC)
The asynchronous wait cycle configuration register (AWCC) is used to configure the parameters for
extended wait cycles. Both the polarity of the EMIF_nWAIT pin(s) and the maximum allowable number of
extended wait cycles can be configured. The AWCC is shown in Figure 17-16 and described in Table 1726. Not all devices support both EMIF_nWAIT[1] and EMIF_nWAIT[0], see the device-specific data
manual to determine support on each device.
NOTE: The EW bit in the asynchronous n configuration register (CEnCFG) must be set to allow for
the insertion of extended wait cycles.
Figure 17-16. Asynchronous Wait Cycle Configuration Register (AWCCR) [offset = 04h]
31
30
29
28
Reserved
WP1
WP0
27
Reserved
24
CS5_WAIT
CS4_WAIT
CS3_WAIT
CS2_WAIT
R-3h
R/W-1
R/W-1
R-0
R/W-0
R/W-0
R/W-0
R/W-0
15
8
23
22
21
20
19
18
17
7
16
0
Reserved
MAX_EXT_WAIT
R-0
R/W-80h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 17-26. Asynchronous Wait Cycle Configuration Register (AWCCR) Field Descriptions
Bit
31-30
29
28
Field
Reserved
Value
3h
WP1
Reserved
23-22
CS5_WAIT
21-20
CS4_WAIT
EMIF_nWAIT[1] polarity bit. This bit defines the polarity of the EMIF_nWAIT[1] pin.
Insert wait cycles if EMIF_nWAIT[1] pin is low.
1
Insert wait cycles if EMIF_nWAIT[1] pin is high.
EMIF_nWAIT[0] polarity bit. This bit defines the polarity of the EMIF_nWAIT[0] pin.
0
Insert wait cycles if EMIF_nWAIT[0] pin is low.
1
Insert wait cycles if EMIF_nWAIT[0] pin is high.
0
Reserved
0-3h
0
EMIF_nWAIT[0] pin is used to control external wait states.
1h
EMIF_nWAIT[1] pin is used to control external wait states.
CS3_WAIT
0
EMIF_nWAIT[0] pin is used to control external wait states.
1h
EMIF_nWAIT[1] pin is used to control external wait states.
CS2_WAIT
15-8
Reserved
7-0
MAX_EXT_WAIT
Reserved
Chip Select 3 WAIT signal selection. This signal determines which EMIF_nWAIT[n] signal will
be used for memory accesses to chip select 3 memory space.
2h-3h
17-16
Chip Select 5 WAIT signal selection. This signal determines which EMIF_nWAIT[n] signal will
be used for memory accesses to chip select 5 memory space. This device does not support
chip select 5, so any value written to this field has no effect.
Chip Select 4 WAIT signal selection. This signal determines which EMIF_nWAIT[n] signal will
be used for memory accesses to chip select 4 memory space.
2h-3h
19-18
Reserved
0
WP0
27-24
Description
Reserved
Chip Select 2 WAIT signal selection. This signal determines which EMIF_nWAIT[n] signal will
be used for memory accesses to chip select 2 memory space.
0
EMIF_nWAIT[0] pin is used to control external wait states.
1h
EMIF_nWAIT[1] pin is used to control external wait states.
2h-3h
Reserved
0
Reserved
0-FFh
Maximum extended wait cycles. The EMIF will wait for a maximum of (MAX_EXT_WAIT + 1) ×
16 clock cycles before it stops inserting asynchronous wait cycles and proceeds to the hold
period of the access.
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17.3.3 SDRAM Configuration Register (SDCR)
The SDRAM configuration register (SDCR) is used to configure various parameters of the SDRAM
controller such as the number of internal banks, the internal page size, and the CAS latency to match
those of the attached SDRAM device. In addition, this register is used to put the attached SDRAM device
into Self-Refresh mode. The SDCR is shown in Figure 17-17 and described in Table 17-27.
NOTE: Writing to the lower three bytes of this register will cause the EMIF to start the SDRAM
initialization sequence described in Section 17.2.5.4.
Figure 17-17. SDRAM Configuration Register (SDCR) [offset = 08h]
31
30
29
SR
PD
PDWR
28
Reserved
24
R/W-0
R/W-0
R/W-0
R-0
23
16
Reserved
R-0
15
14
Reserved
NM(A)
13
Reserved
12
CL
BIT11_9LOCK
R-0
R/W-0
R-0
R/W-3h
R/W-0
7
6
4
11
3
9
2
8
0
Reserved
IBANK
Reserved
PAGESIZE
R-0
R/W-2h
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
A. The NM bit must be set to 1 if the EMIF on your device only has 16 data bus pins.
Table 17-27. SDRAM Configuration Register (SDCR) Field Descriptions
Bit
Field
31
SR
30
29
28-15
14
13-12
656
Value
Self-Refresh mode bit. This bit controls entering and exiting of the Self-Refresh mode described in
Section 17.2.5.7. The field should be written using a byte-write to the upper byte of SDCR to avoid
triggering the SDRAM initialization sequence.
0
Writing a 0 to this bit will cause connected SDRAM devices and the EMIF to exit the Self-Refresh
mode.
1
Writing a 1 to this bit will cause connected SDRAM devices and the EMIF to enter the Self-Refresh
mode.
PD
Power Down bit. This bit controls entering and exiting of the power-down mode. The field should be
written using a byte-write to the upper byte of SDCR to avoid triggering the SDRAM initialization
sequence. If both SR and PD bits are set, the EMIF will go into Self Refresh.
0
Writing a 0 to this bit will cause connected SDRAM devices and the EMIF to exit the power-down
mode.
1
Writing a 1 to this bit will cause connected SDRAM devices and the EMIF to enter the power-down
mode.
PDWR
Reserved
Perform refreshes during power down. Writing a 1 to this bit will cause EMIF to exit power-down
state and issue and AUTO REFRESH command every time Refresh May level is set.
0
NM
Reserved
Description
Reserved. The reserved bit location is always read as 0. If writing to this field, always write the
default value of 0.
Narrow mode bit. This bit defines whether a 16- or 32-bit-wide SDRAM is connected to the EMIF.
This bit field must always be set to 1. Writing to this field triggers the SDRAM initialization
sequence.
0
32-bit SDRAM data bus is used.
1
16-bit SDRAM data bus is used.
0
Reserved. The reserved bit location is always read as 0. If writing to this field, always write the
default value of 0.
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Table 17-27. SDRAM Configuration Register (SDCR) Field Descriptions (continued)
Bit
11-9
Field
Value
CL
CAS Latency. This field defines the CAS latency to be used when accessing connected SDRAM
devices. A 1 must be simultaneously written to the BIT11_9LOCK bit field of this register in order to
write to the CL bit field. Writing to this field triggers the SDRAM initialization sequence.
0-1h
7
6-4
CAS latency = 2 EMIF_CLK cycles
3h
CAS latency = 3 EMIF_CLK cycles
BIT11_9LOCK
2-0
Reserved
Bits 11 to 9 lock. CL can only be written if BIT11_9LOCK is simultaneously written with a 1.
BIT11_9LOCK is always read as 0. Writing to this field triggers the SDRAM initialization sequence.
Reserved
0
CL cannot be written.
1
CL can be written.
0
Reserved. The reserved bit location is always read as 0. If writing to this field, always write the
default value of 0.
IBANK
Internal SDRAM Bank size. This field defines number of banks inside the connected SDRAM
devices. Writing to this field triggers the SDRAM initialization sequence.
0
1 bank SDRAM devices.
1
2 bank SDRAM devices.
2
4 bank SDRAM devices.
3h-7h
3
Reserved
2h
4h-7h
8
Description
Reserved
0
PAGESIZE
Reserved.
Reserved. The reserved bit location is always read as 0. If writing to this field, always write the
default value of 0.
Page Size. This field defines the internal page size of connected SDRAM devices. Writing to this
field triggers the SDRAM initialization sequence.
0
8 column address bits (256 elements per row)
1h
9 column address bits (512 elements per row)
2h
10 column address bits (1024 elements per row)
3h
11 column address bits (2048 elements per row)
4h-7h
Reserved
17.3.4 SDRAM Refresh Control Register (SDRCR)
The SDRAM refresh control register (SDRCR) is used to configure the rate at which connected SDRAM
devices will be automatically refreshed by the EMIF. Refer to Section 17.2.5.6 on the refresh controller for
more details. The SDRCR is shown in Figure 17-18 and described in Table 17-28.
Figure 17-18. SDRAM Refresh Control Register (SDRCR) [offset = 0Ch]
31
16
Reserved
R-0
15
13
12
0
Reserved
RR
R-0
R/W-60h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 17-28. SDRAM Refresh Control Register (SDRCR) Field Descriptions
Bit
Field
31-13
Reserved
12-0
RR
Value
0
0-1FFFh
Description
Reserved. The reserved bit location is always read as 0. If writing to this field, always write the
default value of 0.
Refresh Rate. This field is used to define the SDRAM refresh period in terms of EMIF_CLK cycles.
Writing a value < 0x0020 to this field will cause it to be loaded with (2 × T_RFC) + 1 value from the
SDRAM timing register (SDTIMR).
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17.3.5 Asynchronous n Configuration Registers (CE2CFG-CE5CFG)
The asynchronous n configuration registers (CE2CFG, CE3CFG, CE4CFG, and CE5CFG) are used to
configure the shaping of the address and control signals during an access to asynchronous memory
connected to CS2, CS3, CS4, and CS5, respectively. CS5 is not available on this device. It is also used to
program the width of asynchronous interface and to select from various modes of operation. This register
can be written prior to any transfer, and any asynchronous transfer following the write will use the new
configuration. The CEnCFG is shown in Figure 17-19 and described in Table 17-29.
Figure 17-19. Asynchronous n Configuration Register (CEnCFG) [offset = 10h - 1Ch]
31
30
SS
EW(A)
29
W_SETUP
26
W_STROBE(B)
R/W-0
R/W-0
R/W-Fh
R/W-3Fh
23
20
15
13
25
19
24
17
16
W_STROBE(B)
W_HOLD
R_SETUP
R/W-3Fh
R/W-7h
R/W-Fh
12
7
6
4
3
2
1
0
R_SETUP
R_STROBE(B)
R_HOLD
TA
ASIZE
R/W-Fh
R/W-3Fh
R/W-7h
R/W-3h
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
A. The EW bit must be cleared to 0.
B. This bit field must be cleared to 0 if the EMIF on your device does not have an EMIF_nWAIT pin.
Table 17-29. Asynchronous n Configuration Register (CEnCFG) Field Descriptions
Bit
Field
31
SS
30
Value
Description
Select Strobe bit. This bit defines whether the asynchronous interface operates in Normal Mode or
Select Strobe Mode. See Section 17.2.6 for details on the two modes of operation.
0
Normal Mode is enabled.
1
Select Strobe Mode is enabled.
EW
Extend Wait bit. This bit defines whether extended wait cycles will be enabled. See Section 17.2.6.6 on
extended wait cycles for details. This bit field must be cleared to 0, if the EMIF on your device does not
have an EMIF_nWAIT pin.
0
Extended wait cycles are disabled.
1
Extended wait cycles are enabled.
29-26
W_SETUP
0-Fh
Write setup width in EMIF_CLK cycles, minus 1 cycle. See Section 17.2.6.3 for details.
25-20
W_STROBE
0-3Fh
Write strobe width in EMIF_CLK cycles, minus 1 cycle. See Section 17.2.6.3 for details.
19-17
W_HOLD
16-13
12-7
6-4
R_HOLD
0-7h
Read hold width in EMIF_CLK cycles, minus 1 cycle. See Section 17.2.6.3 for details.
3-2
TA
0-3h
Minimum Turn-Around time. This field defines the minimum number of EMIF_CLK cycles between reads
and writes, minus 1 cycle. See Section 17.2.6.3 for details.
1-0
ASIZE
0-7h
Write hold width in EMIF_CLK cycles, minus 1 cycle. See Section 17.2.6.3 for details.
R_SETUP
0-Fh
Read setup width in EMIF_CLK cycles, minus 1 cycle. See Section 17.2.6.3 for details.
R_STROBE
0-3Fh
Read strobe width in EMIF_CLK cycles, minus 1 cycle. See Section 17.2.6.3 for details.
Asynchronous Data Bus Width. This field defines the width of the asynchronous device data bus.
0
8-bit data bus
1h
16-bit data bus
2h-3h
658
Reserved
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17.3.6 SDRAM Timing Register (SDTIMR)
The SDRAM timing register (SDTIMR) is used to program many of the SDRAM timing parameters.
Consult the SDRAM datasheet for information on the appropriate values to program into each field. The
SDTIMR is shown in Figure 17-20 and described in Table 17-30.
Figure 17-20. SDRAM Timing Register (SDTIMR) [offset = 20h]
31
27
26
24
23
22
20
19
18
16
T_RFC
T_RP
Rsvd
T_RCD
Rsvd
T_WR
R/W-8h
R/W-2h
R-0
R/W-2h
R-0
R/W-1h
15
12
11
8
7
6
4
3
0
T_RAS
T_RC
Rsvd
T_RRD
Reserved
R/W-5h
R/W-8h
R-0
R/W-1h
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 17-30. SDRAM Timing Register (SDTIMR) Field Descriptions
Field
Value
Description
31-27
Bit
T_RFC
0-1Fh
Specifies the Trfc value of the SDRAM. This defines the minimum number of EMIF_CLK cycles from
Refresh (REFR) to Refresh (REFR), minus 1:
T_RFC = (Trfc/tEMIF_CLK) - 1
26-24
T_RP
0-7h
Specifies the Trp value of the SDRAM. This defines the minimum number of EMIF_CLK cycles from
Precharge (PRE) to Activate (ACTV) or Refresh (REFR) command, minus 1:
T_RP = (Trp/tEMIF_CLK) - 1
23
22-20
19
Reserved
T_RCD
Reserved
0
Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default
value of 0.
0-7h
Specifies the Trcd value of the SDRAM. This defines the minimum number of EMIF_CLK cycles from
Active (ACTV) to Read (READ) or Write (WRT), minus 1:
T_RCD = (Trcd/tEMIF_CLK) - 1
0
Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default
value of 0.
18-16
T_WR
0-7h
Specifies the Twr value of the SDRAM. This defines the minimum number of EMIF_CLK cycles from
last Write (WRT) to Precharge (PRE), minus 1:
T_WR = (Twr/tEMIF_CLK) - 1
15-12
T_RAS
0-Fh
Specifies the Tras value of the SDRAM. This defines the minimum number of EMIF_CLK clock cycles
from Activate (ACTV) to Precharge (PRE), minus 1:
T_RAS = (Tras/tEMIF_CLK) - 1
11-8
T_RC
0-Fh
Specifies the Trc value of the SDRAM. This defines the minimum number of EMIF_CLK clock cycles
from Activate (ACTV) to Activate (ACTV), minus 1:
T_RC = (Trc/tEMIF_CLK) - 1
7
Reserved
6-4
T_RRD
3-0
Reserved
0
Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default
value of 0.
0-7h
Specifies the Trrd value of the SDRAM. This defines the minimum number of EMIF_CLK clock cycles
from Activate (ACTV) to Activate (ACTV) for a different bank, minus 1:
T_RRD = (Trrd/tEMIF_CLK) - 1
0
Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default
value of 0.
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17.3.7 SDRAM Self Refresh Exit Timing Register (SDSRETR)
The SDRAM self refresh exit timing register (SDSRETR) is used to program the amount of time between
when the SDRAM exits Self-Refresh mode and when the EMIF issues another command. The SDSRETR
is shown in Figure 17-21 and described in Table 17-31.
Figure 17-21. SDRAM Self Refresh Exit Timing Register (SDSRETR) [offset = 3Ch]
31
16
Reserved
R-0
15
5
4
0
Reserved
T_XS
R-0
R/W-9h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 17-31. SDRAM Self Refresh Exit Timing Register (SDSRETR) Field Descriptions
Bit
Field
31-5
Reserved
4-0
T_XS
660
Value
0
0-1Fh
Description
Reserved. The reserved bit location is always read as 0.
This field specifies the minimum number of ECLKOUT cycles from Self-Refresh exit to any command,
minus 1.
T_XS = Txsr / tEMIF_CLK - 1
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17.3.8 EMIF Interrupt Raw Register (INTRAW)
The EMIF interrupt raw register (INTRAW) is used to monitor and clear the EMIF’s hardware-generated
Asynchronous Timeout Interrupt. The AT bit in this register will be set when an Asynchronous Timeout
occurs regardless of the status of the EMIF interrupt mask set register (INTMSKSET) and EMIF interrupt
mask clear register (INTMSKCLR). Writing a 1 to this bit will clear it. The EMIF on some devices does not
have the EMIF_nWAIT pin; therefore, these registers and fields are reserved on those devices. The
INTRAW is shown in Figure 17-22 and described in Table 17-32.
Figure 17-22. EMIF Interrupt Raw Register (INTRAW) [offset = 40h]
31
8
Reserved
R-0
7
2
1
0
Reserved
3
WR
LT
AT
R-0
R/W1C-0
R/W1C-0
R/W1C-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing 0 has no effect); -n = value after reset
Table 17-32. EMIF Interrupt Raw Register (INTRAW) Field Descriptions
Bit
31-3
2
1
0
Field
Reserved
Value
0
WR
Description
Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default
value of 0.
Wait Rise. This bit is set to 1 by hardware to indicate that a rising edge on the EMIF_nWAIT pin has
occurred.
0
Indicates that a rising edge has not occurred on the EMIF_nWAIT pin. Writing a 0 has no effect.
1
Indicates that a rising edge has occurred on the EMIF_nWAIT pin. Writing a 1 will clear this bit and the
WR_MASKED bit in the EMIF interrupt masked register (INTMSK).
LT
Line Trap. Set to 1 by hardware to indicate illegal memory access type or invalid cache line size.
0
Writing a 0 has no effect.
1
Indicates that a line trap has occurred. Writing a 1 will clear this bit as well as the LT_MASKED bit in
the EMIF interrupt masked register (INTMSK).
AT
Asynchronous Timeout. This bit is set to 1 by hardware to indicate that during an extended
asynchronous memory access cycle, the EMIF_nWAIT pin did not go inactive within the number of
cycles defined by the MAX_EXT_WAIT field in the asynchronous wait cycle configuration register
(AWCC).
0
Indicates that an Asynchronous Timeout has not occurred. Writing a 0 has no effect.
1
Indicates that an Asynchronous Timeout has occurred. Writing a 1 will clear this bit as well as the
AT_MASKED bit in the EMIF interrupt masked register (INTMSK).
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17.3.9 EMIF Interrupt Masked Register (INTMSK)
Like the EMIF interrupt raw register (INTRAW), the EMIF interrupt masked register (INTMSK) is used to
monitor and clear the status of the EMIF’s hardware-generated Asynchronous Timeout Interrupt. The main
difference between the two registers is that when the AT_MASKED bit in this register is set, an active-high
pulse will be sent to the CPU interrupt controller. Also, the AT_MASKED bit field in INTMSK is only set to
1 if the associated interrupt has been enabled in the EMIF interrupt mask set register (INTMSKSET). The
EMIF on some devices does not have the EMIF_nWAIT pin, therefore, these registers and fields are
reserved on those devices. The INTMSK is shown in Figure 17-23 and described in Table 17-33.
Figure 17-23. EMIF Interrupt Mask Register (INTMSK) [offset = 44h]
31
8
Reserved
R-0
7
2
1
0
Reserved
3
WR_MASKED
LT_MASKED
AT_MASKED
R-0
R/W1C-0
R/W1C-0
R/W1C-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing 0 has no effect); -n = value after reset
Table 17-33. EMIF Interrupt Mask Register (INTMSK) Field Descriptions
Bit
31-3
2
1
0
662
Field
Reserved
Value
0
WR_MASKED
Description
Reserved. The reserved bit location is always read as 0. If writing to this field, always write the
default value of 0.
Wait Rise Masked. This bit is set to 1 by hardware to indicate a rising edge has occurred on the
EMIF_nWAIT pin, provided that the WR_MASK_SET bit is set to 1 in the EMIF interrupt mask set
register (INTMSKSET).
0
Indicates that a wait rise interrupt has not been generated. Writing a 0 has no effect.
1
Indicates that a wait rise interrupt has been generated. Writing a 1 will clear this bit and the WR bit
in the EMIF interrupt raw register (INTRAW).
LT_MASKED
Masked Line Trap. Set to 1 by hardware to indicate illegal memory access type or invalid cache line
size, only if the LT_MASK_SET bit in the EMIF interrupt mask set register (INTMSKSET) is set to 1.
0
Writing a 0 has no effect.
1
Writing a 1 will clear this bit as well as the LT bit in the EMIF interrupt raw register (INTRAW).
AT_MASKED
Asynchronous Timeout Masked. This bit is set to 1 by hardware to indicate that during an extended
asynchronous memory access cycle, the EMIF_nWAIT pin did not go inactive within the number of
cycles defined by the MAX_EXT_WAIT field in the asynchronous wait cycle configuration register
(AWCC), provided that the AT_MASK_SET bit is set to 1 in the EMIF interrupt mask set register
(INTMSKSET).
0
Indicates that an Asynchronous Timeout Interrupt has not been generated. Writing a 0 has no
effect.
1
Indicates that an Asynchronous Timeout Interrupt has been generated. Writing a 1 will clear this bit
as well as the AT bit in the EMIF interrupt raw register (INTRAW).
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17.3.10 EMIF Interrupt Mask Set Register (INTMSKSET)
The EMIF interrupt mask set register (INTMSKSET) is used to enable the Asynchronous Timeout
Interrupt. If read as 1, the AT_MASKED bit in the EMIF interrupt masked register (INTMSK) will be set and
an interrupt will be generated when an Asynchronous Timeout occurs. If read as 0, the AT_MASKED bit
will always read 0 and no interrupt will be generated when an Asynchronous Timeout occurs. Writing a 1
to the AT_MASK_SET bit enables the Asynchronous Timeout Interrupt. The EMIF on some devices does
not have the EMIF_nWAIT pin; therefore, these registers and fields are reserved on those devices. The
INTMSKSET is shown in Figure 17-24 and described in Table 17-34.
Figure 17-24. EMIF Interrupt Mask Set Register (INTMSKSET) [offset = 48h]
31
16
Reserved
R-0
15
2
1
0
Reserved
3
WR_MASK_SET
LT_MASK_SET
AT_MASK_SET
R-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 17-34. EMIF Interrupt Mask Set Register (INTMSKSET) Field Descriptions
Bit
31-3
2
1
0
Field
Value
Reserved
0
WR_MASK_SET
Description
Reserved. The reserved bit location is always read as 0. If writing to this field, always write the
default value of 0.
Wait Rise Mask Set. This bit determines whether or not the wait rise Interrupt is enabled. Writing a
1 to this bit sets this bit, sets the WR_MASK_CLR bit in the EMIF interrupt mask clear register
(INTMSKCLR), and enables the wait rise interrupt. To clear this bit, a 1 must be written to the
WR_MASK_CLR bit in INTMSKCLR.
0
Indicates that the wait rise interrupt is disabled. Writing a 0 has no effect.
1
Indicates that the wait rise interrupt is enabled. Writing a 1 sets this bit and the WR_MASK_CLR bit
in the EMIF interrupt mask clear register (INTMSKCLR).
LT_MASK_SET
Mask set for LT_MASKED bit in the EMIF interrupt mask register (INTMSK).
0
Indicates that the line trap interrupt is disabled. Writing a 0 has no effect.
1
Indicates that the line trap interrupt is enabled. Writing a 1 sets this bit and the LT_MASK_CLR bit
in the EMIF interrupt mask clear register (INTMSKCLR).
AT_MASK_SET
Asynchronous Timeout Mask Set. This bit determines whether or not the Asynchronous Timeout
Interrupt is enabled. Writing a 1 to this bit sets this bit, sets the AT_MASK_CLR bit in the EMIF
interrupt mask clear register (INTMSKCLR), and enables the Asynchronous Timeout Interrupt. To
clear this bit, a 1 must be written to the AT_MASK_CLR bit of the EMIF interrupt mask clear
register (INTMSKCLR).
0
Indicates that the Asynchronous Timeout Interrupt is disabled. Writing a 0 has no effect.
1
Indicates that the Asynchronous Timeout Interrupt is enabled. Writing a 1 sets this bit and the
AT_MASK_CLR bit in the EMIF interrupt mask clear register (INTMSKCLR).
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17.3.11 EMIF Interrupt Mask Clear Register (INTMSKCLR)
The EMIF interrupt mask clear register (INTMSKCLR) is used to disable the Asynchronous Timeout
Interrupt. If read as 1, the AT_MASKED bit in the EMIF interrupt masked register (INTMSK) will be set and
an interrupt will be generated when an Asynchronous Timeout occurs. If read as 0, the AT_MASKED bit
will always read 0 and no interrupt will be generated when an Asynchronous Timeout occurs. Writing a 1
to the AT_MASK_CLR bit disables the Asynchronous Timeout Interrupt. The EMIF on some devices does
not have the EMIF_nWAIT pin, therefore, these registers and fields are reserved on those devices. The
INTMSKCLR is shown in Figure 17-25 and described in Table 17-35.
Figure 17-25. EMIF Interrupt Mask Clear Register (INTMSKCLR) [offset = 4Ch]
31
16
Reserved
R-0
15
2
1
0
Reserved
3
WR_MASK_CLR
LT_MASK_CLR
AT_MASK_CLR
R-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 17-35. EMIF Interrupt Mask Clear Register (INTMSKCLR) Field Descriptions
Bit
31-3
2
1
0
664
Field
Reserved
Value
0
WR_MASK_CLR
Description
Reserved. The reserved bit location is always read as 0. If writing to this field, always write the
default value of 0.
Wait Rise Mask Clear. This bit determines whether or not the wait rise interrupt is enabled. Writing
a 1 to this bit clears this bit, clears the WR_MASK_SET bit in the EMIF interrupt mask set register
(INTMSKSET), and disables the wait rise interrupt. To set this bit, a 1 must be written to the
WR_MASK_SET bit in INTMSKSET.
0
Indicates that the wait rise interrupt is disabled. Writing a 0 has no effect.
1
Indicates that the wait rise interrupt is enabled. Writing a 1 clears this bit and the WR_MASK_SET
bit in the EMIF interrupt mask set register (INTMSKSET).
LT_MASK_CLR
Line trap Mask Clear. This bit determines whether or not the line trap interrupt is enabled. Writing a
1 to this bit clears this bit, clears the LT_MASK_SET bit in the EMIF interrupt mask set register
(INTMSKSET), and disables the line trap interrupt. To set this bit, a 1 must be written to the
LT_MASK_SET bit in INTMSKSET.
0
Indicates that the line trap interrupt is disabled. Writing a 0 has no effect.
1
Indicates that the line trap interrupt is enabled. Writing a 1 clears this bit and the LT_MASK_SET bit
in the EMIF interrupt mask set register (INTMSKSET).
AT_MASK_CLR
Asynchronous Timeout Mask Clear. This bit determines whether or not the Asynchronous Timeout
Interrupt is enabled. Writing a 1 to this bit clears this bit, clears the AT_MASK_SET bit in the EMIF
interrupt mask set register (INTMSKSET), and disables the Asynchronous Timeout Interrupt. To set
this bit, a 1 must be written to the AT_MASK_SET bit of the EMIF interrupt mask set register
(INTMSKSET).
0
Indicates that the Asynchronous Timeout Interrupt is disabled. Writing a 0 has no effect.
1
Indicates that the Asynchronous Timeout Interrupt is enabled. Writing a 1 clears this bit and the
AT_MASK_SET bit in the EMIF interrupt mask set register (INTMSKSET).
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17.3.12 Page Mode Control Register (PMCR)
The page mode control register (PMCR) is shown in Figure 17-26 and described in Table 17-36. This
register is configured when using NOR Flash page mode.
Figure 17-26. Page Mode Control Register (PMCR) [offset = 68h]
31
25
24
CS5_PG_DEL
26
CS5_PG_SIZE
CS5_PG_MD_EN
R/W-3Fh
R/W-0
R/W-0
23
17
16
CS4_PG_DEL
18
CS4_PG_SIZE
CS4_PG_MD_EN
R/W-3Fh
R/W-0
R/W-0
15
9
8
CS3_PG_DEL
10
CS3_PG_SIZE
CS3_PG_MD_EN
R/W-3Fh
R/W-0
R/W-0
7
1
0
CS2_PG_DEL
2
CS2_PG_SIZE
CS2_PG_MD_EN
R/W-3Fh
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 17-36. Page Mode Control Register (PMCR) Field Descriptions
Field
Value
Description
31-26
Bit
CS5_PG_DEL
1-3Fh
Page access delay for NOR Flash connected on CS5. CS5 is not available on this device.
25
CS5_PG_SIZE
Page Size for NOR Flash connected on CS5. CS5 is not available on this device.
24
CS5_PG_MD_EN
Page Mode enable for NOR Flash connected on CS5. CS5 is not available on this device.
23-18
CS4_PG_DEL
17
CS4_PG_SIZE
16
CS3_PG_DEL
9
CS3_PG_SIZE
CS2_PG_DEL
1
CS2_PG_SIZE
0
0
Page size is 4 words.
1
Page size is 8 words.
Page Mode enable for NOR Flash connected on CS4.
0
Page mode is disabled for this chip select.
1
Page mode is enabled for this chip select.
1-3Fh
Page access delay for NOR Flash connected on CS3. Number of EMIF_CLK cycles required for
the page read data to be valid, minus 1 cycle. This value must not be cleared to 0.
Page Size for NOR Flash connected on CS3.
0
Page size is 4 words.
1
Page size is 8 words.
CS3_PG_MD_EN
7-2
Page access delay for NOR Flash connected on CS4. Number of EMIF_CLK cycles required for
the page read data to be valid, minus 1 cycle. This value must not be cleared to 0.
Page Size for NOR Flash connected on CS4.
CS4_PG_MD_EN
15-10
8
1-3Fh
Page Mode enable for NOR Flash connected on CS3.
0
Page mode is disabled for this chip select.
1
Page mode is enabled for this chip select.
1-3Fh
Page access delay for NOR Flash connected on CS2. Number of EMIF_CLK cycles required for
the page read data to be valid, minus 1 cycle. This value must not be cleared to 0.
Page Size for NOR Flash connected on CS2.
0
Page size is 4 words.
1
Page size is 8 words.
CS2_PG_MD_EN
Page Mode enable for NOR Flash connected on CS2.
0
Page mode is disabled for this chip select.
1
Page mode is enabled for this chip select.
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17.4 Example Configuration
This section presents an example of interfacing the EMIF to both an SDR SDRAM device and an
asynchronous flash device.
17.4.1 Hardware Interface
Figure 17-27 shows the hardware interface between the EMIF, a Samsung K4S641632H-TC(L)70 64Mb
SDRAM device, and two SHARP LH28F800BJE-PTTL90 8Mb Flash memory. The connection between
the EMIF and the SDRAM is straightforward, but the connection between the EMIF and the flash deserves
a detailed look.
The address inputs for the flash are provided by three sources. The A[18:0] address inputs are provided
by a combination of the EMIF_A and EMIF_BA pins according to Section 17.2.6.1. RD/nBY signal from
one flash is connected to EMIF_nWAIT pin of EMIF.
Finally, this example configuration connects the EMIF_nWE pin to the nWE input of the flash and operates
the EMIF in Select Strobe Mode.
17.4.2 Software Configuration
The following sections describe how to configure the EMIF registers and bit fields to interface the EMIF
with the Samsung K4S641632H-TC(L)70 SDRAM and the SHARP LH28F800BJE-PTTL90 8Mb Flash
memory.
17.4.2.1 Configuring the SDRAM Interface
This section describes how to configure the EMIF to interface with the Samsung K4S641632H-TC(L)70
SDRAM with a clock frequency of fEMIF_CLK = 100 MHz. Procedure A described in Section 17.2.5.5 is
followed which assumes that the SDRAM power-up timing constraint were met during the SDRAM AutoInitialization sequence after Reset.
17.4.2.1.1 PLL Programming for the EMIF to K4S641632H-TC(L)70 Interface
The device global clock module (GCM) should first be programmed to select the desired EMIF_CLK
frequency. Before doing this, the SDRAM should be placed in Self-Refresh Mode by setting the SR bit in
the SDRAM configuration register (SDCR). The SR bit should be set using a byte-write to the upper byte
of the SDCR to avoid triggering the SDRAM Initialization Sequence. The EMIF_CLK frequency can now
be configured to the desired value by selecting the appropriate clock source for the VCLK3 domain. Once
the VCLK3 domain frequency has been configured, remove the SDRAM from Self-Refresh by clearing the
SR bit in SDCR, again with a byte-write.
Table 17-37. SR Field Value For the EMIF to K4S641632H-TC(L)70 Interface
666
Field
Value
Purpose
SR
1 then 0
To place the EMIF into the self refresh state
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Figure 17-27. Example Configuration Interface
EMIF
EMIF_nCS[0]
EMIF_nCAS
EMIF_nRAS
EMIF_nWE
EMIF_CLK
EMIF_CKE
EMIF_BA[1]
EMIF_BA[0]
EMIF_ADDR[11:0]
EMIF_nDQM[0]
EMIF_nDQM[1]
EMIF_DATA[15:0]
EMIF_nCS[2]
EMIF_nCS[3]
EMIF_nOE
EMIF_nWAIT
nRESET
EMIF_ADDR
[18:13]
Reset
SDRAM
nCE
1M x 16
nCAS
x 4 bank
nRAS
nWE
CLK
CKE
BA[1]
BA[0]
A[11:0]
LDQM
UDQM
DQ[15:0]
FLASH
A[0]
A[12:1] 512k x 16
DQ[15:0]
nCE
nWE
nOE
nRESET
A[18:13]
RY/BY
nBYTE0
nBYTE1
FLASH
A[0]
A[12:1] 512k x 16
DQ[15:0]
nCE
nWE
nOE
nRESET
A[18:13]
RY/BY
nBYTE0
nBYTE1
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17.4.2.1.2 SDRAM Timing Register (SDTIMR) Settings for the EMIF to K4S641632H-TC(L)70 Interface
The fields of the SDRAM timing register (SDTIMR) should be programmed first as described in Table 1738 to satisfy the required timing parameters for the K4S641632H-TC(L)70. Based on these calculations, a
value of 6111 4610h should be written to SDTIMR. Figure 17-28 shows a graphical description of how
SDTIMR should be programmed.
Table 17-38. SDTIMR Field Calculations for the EMIF to K4S641632H-TC(L)70 Interface
Field Name
Formula
Value from K4S641632H-TC(L)70
Datasheet
Value Calculated for
Field
T_RFC
T_RFC >= (tRFC × fEMIF_CLK) - 1
tRC = 68 ns (min) (1)
6
T_RP
T_RP >= (tRP × fEMIF_CLK) - 1
tRP = 20 ns (min)
1
T_RCD
T_RCD >= (tRCD × fEMIF_CLK) - 1
tRCD = 20 ns (min)
1
(2)
T_WR
T_WR >= (tWR × fEMIF_CLK) - 1
tRDL = 2 CLK = 20 ns (min)
T_RAS
T_RAS >= (tRAS × fEMIF_CLK) - 1
tRAS = 49 ns (min)
4
T_RC
T_RC >= (tRC × fEMIF_CLK) - 1
tRC = 68 ns (min)
6
T_RRD
T_RRD >= (tRRD × fEMIF_CLK) - 1
tRRD = 14 ns (min)
1
(1)
(2)
1
The Samsung datasheet does not specify a tRFC value. Instead, Samsung specifies tRC as the minimum auto refresh period.
The Samsung datasheet does not specify a tWR value. Instead, Samsung specifies tRDL as last data in to row precharge minimum
delay.
Figure 17-28. SDRAM Timing Register (SDTIMR)
31
27
24
23
22
20
19
18
16
001
0
001
0
001
T_RFC
T_RP
Rsvd
T_RCD
Rsvd
T_WR
15
668
26
0 0110
12
11
8
7
6
4
3
0
0100
0110
0
001
0000
T_RAS
T_RC
Rsvd
T_RRD
Reserved
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17.4.2.1.3 SDRAM Self Refresh Exit Timing Register (SDSRETR) Settings for the EMIF to K4S641632HTC(L)70 Interface
The SDRAM self refresh exit timing register (SDSRETR) should be programmed second to satisfy the tXSR
timing requirement from the K4S641632H-TC(L)70 datasheet. Table 17-39 shows the calculation of the
proper value to program into the T_XS field of this register. Based on this calculation, a value of 6h should
be written to SDSRETR. Figure 17-29 shows how SDSRETR should be programmed.
Table 17-39. RR Calculation for the EMIF to K4S641632H-TC(L)70 Interface
Field Name
Formula
Value from K4S641632H-TC(L)70
Datasheet
Value Calculated for
Field
T_XS
T_XS >= (tXSR × fEMIF_CLK) - 1
tRC = 68 ns (min) (1)
6
(1)
The Samsung datasheet does not specify a tXSR value. Instead, Samsung specifies tRC as the minimum required time after CKE
going high to complete self refresh exit.
Figure 17-29. SDRAM Self Refresh Exit Timing Register (SDSRETR)
31
16
0000 0000 0000 0000
Reserved
15
5
4
0
000 0000 0000
0 0110
Reserved
T_XS
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17.4.2.1.4 SDRAM Refresh Control Register (SDRCR) Settings for the EMIF to K4S641632H-TC(L)70
Interface
The SDRAM refresh control register (SDRCR) should next be programmed to satisfy the required refresh
rate of the K4S641632H-TC(L)70. Table 17-40 shows the calculation of the proper value to program into
the RR field of this register. Based on this calculation, a value of 61Ah should be written to SDRCR.
Figure 17-30 shows how SDRCR should be programmed.
Table 17-40. RR Calculation for the EMIF to K4S641632H-TC(L)70 Interface
Field Name
Formula
RR
RR ≤ fEMIF_CLK × tRefresh Period From SDRAM datasheet: tRefresh Period
/ ncycles
= 64 ms; ncycles = 4096 EMIF clock
rate: fEMIF_CLK = 100 MHz
Values
Value Calculated for Field
RR = 1562 cycles = 61Ah cycles
Figure 17-30. SDRAM Refresh Control Register (SDRCR)
31
19
15
670
13
18
16
0 0000 0000 0000
000
Reserved
Reserved
12
0
000
0 0110 0001 1010 (61Ah)
Reserved
RR
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17.4.2.1.5 SDRAM Configuration Register (SDCR) Settings for the EMIF to K4S641632H-TC(L)70
Interface
Finally, the fields of the SDRAM configuration register (SDCR) should be programmed as described in
Table 17-37 to properly interface with the K4S641632H-TC(L)70 device. Based on these settings, a value
of 4720h should be written to SDCR. Figure 17-31 shows how SDCR should be programmed. The EMIF is
now ready to perform read and write accesses to the SDRAM.
Table 17-41. SDCR Field Values For the EMIF to K4S641632H-TC(L)70 Interface
Field
Value
Purpose
SR
0
To avoid placing the EMIF into the self refresh state
NM
1
To configure the EMIF for a 16-bit data bus
CL
011b
To select a CAS latency of 3
BIT11_9LOCK
1
To allow the CL field to be written
IBANK
010b
To select 4 internal SDRAM banks
PAGESIZE
0
To select a page size of 256 words
Figure 17-31. SDRAM Configuration Register (SDCR)
31
30
29
0
0
0
28
0 0000
24
SR
Reserved
Reserved
Reserved
23
17
16
00 0000
18
0
0
Reserved
Reserved
Reserved
9
8
15
14
13
12
0
1
0
0
011
1
Reserved
NM
Reserved
Reserved
CL
BIT11_9LOCK
7
6
4
11
3
2
0
0
010
0
000
Reserved
IBANK
Reserved
PAGESIZE
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17.4.2.2 Configuring the Flash Interface
This section describes how to configure the EMIF to interface with the two of SHARP LH28F800BJEPTTL90 8Mb Flash memory with a clock frequency of fEMIF_CLK = 100 MHz. The example assumes that one
flash is connected to EMIF_nCS2 and the other to EMIF_nCS3.
17.4.2.2.1 Asynchronous 1 Configuration Register (CE2CFG) Settings for the EMIF to LH28F800BJEPTTL90 Interface
The asynchronous 1 configuration register (CE2CFG) and asynchronous 2 configuration register
(CE3CFG) are the only registers that is necessary to program for this asynchronous interface (assuming
that one Flash is connected to EMIF_nCS[2] and the other to EMIF_nCS[3]. The SS bit (in both registers)
should be set to 1 to enable Select Strobe Mode and the ASIZE field (in both registers) should be set to 1
to select a 16-bit interface. The other fields in this register control the shaping of the EMIF signals, and the
proper values can be determined by referring to the AC Characteristics in the Flash datasheet and the
device datasheet. Based on the following calculations, a value of 8862 25BDh should be written to
CE2CFG. Table 17-42 and Table 17-43 show the pertinent AC Characteristics for reads and writes to the
Flash device, and Figure 17-32 and Figure 17-33 show the associated timing waveforms. Finally,
Figure 17-34 shows programming the CEnCFG (n = 2, 3) with the calculated values.
Table 17-42. AC Characteristics for a Read Access
AC Characteristic
Device
Definition
Min
tSU
EMIF
Setup time, read EMIF_D before EMIF_CLK
high
6.5
Max
Unit
ns
tH
EMIF
Data hold time, read EMIF_D after EMIF_CLK
high
1
ns
tD
EMIF
Output delay time, EMIF_CLK high to output
signal valid
7
ns
tELQV
Flash
nCE to Output Delay
90
ns
tEHQZ
Flash
nCE High to Output in High Impedance
55
ns
Max
Unit
Table 17-43. AC Characteristics for a Write Access
AC Characteristic
Device
Definition
Min
tAVAV
Flash
Write Cycle Time
90
ns
tELEH
Flash
nCE Pulse Width Low
50
ns
tEHEL
Flash
nCE Pulse Width High (not shown in
Figure 17-33)
30
ns
Figure 17-32. LH28F800BJE-PTTL90 to EMIF Read Timing Waveforms
Setup
Hold
Strobe
TA
EMIF_CLK
tD
tD
EMIF_nCS[n]
EMIF_A/
EMIF_BA
tEHQZ
tSU
tH
tELQV
EMIF_D
Data
EMIF_nOE
672
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Figure 17-33. LH28F800BJE-PTTL90 to EMIF Write Timing Waveforms
Hold
Setup
Strobe
tAVAV
EMIF_CLK
tELEH
EMIF_nCS[n]
EMIF_A/
EMIF_BA
Address
EMIF_D
Data
EMIF_nWE
The R_STROBE field should be set to meet the following equation:
R_STROBE >= (tD + tELQV + tSU) × fEMIF_CLK - 1
R_STROBE >= (7 ns + 90 ns + 6.5 ns) × 100 MHz - 1
R_STROBE >= 9.35
R_STROBE = 10
The R_HOLD field must be large enough to satisfy the EMIF Data hold time, tH:
R_HOLD > = tH × fEMIF_CLK - 1
R_HOLD >= 1 ns × 100 MHz - 1
R_HOLD >= -0.9
The R_HOLD field must also combine with the TA field to satisfy the Flash's nCE High to Output in High
Impedance time, tEHQZ:
R_HOLD + TA >= (tD + tEHQZ) × fEMIF_CLK - 2
R_HOLD + TA >= (7 ns + 55 ns) × 100 MHz - 2
R_HOLD + TA >= 4.2
The largest value that can be programmed into the TA field is 3h, therefore the following values can be
used:
R_HOLD = 2
TA = 3
For Writes, the W_STROBE field should be set to satisfy the Flash's nCE Pulse Width constraint, tELEH:
W_STROBE >= tELEH × fEMIF_CLK - 1
W_STROBE >= 50 ns × 100 MHz - 1
W_STROBE >= 4
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The W_SETUP and W_HOLD fields should combine to satisfy the Flash's nCE Pulse Width High
constraint, tEHEL, when performing back-to-back writes:
W_SETUP + W_HOLD > = tEHEL × fEMIF_CLK - 2
W_SETUP + W_HOLD > = 30 ns × 100 MHz - 2
W_SETUP + W_HOLD > = 1
In addition, the entire Write access length must satisfy the Flash's minimum Write Cycle Time, tAVAV:
W_SETUP + W_STROBE + W_HOLD >= tAVAV × fEMIF_CLK - 3
W_SETUP + W_STROBE + W_HOLD >= 90 ns × 100 MHz - 3
W_SETUP + W_STROBE + W_HOLD >= 6
Solving the above equations for the Write fields results in the following possible solution:
W_SETUP = 1
W_STROBE = 5
W_HOLD = 0
Adding a 10 ns (1 cycle) margin to each of the periods (excluding TA which is already at its maximum) in
this example produces the following recommended values:
W_SETUP = 2h
W_STROBE = 6h
W_HOLD = 1h
R_SETUP = 1h
R_STROBE = Bh
R_HOLD = 3h
TA = 3h
Figure 17-34. Asynchronous m Configuration Register (m = 1, 2) (CEnCFG (n = 2, 3))
31
30
1
0
29
0010
26
00
SS
EW
W_SETUP
W_STROBE
23
20
15
674
13
25
19
24
17
16
0110
001
0
W_STROBE
W_HOLD
R_SETUP
12
7
6
4
3
2
1
0
001
001011
011
11
01
R_SETUP
R_STROBE
R_HOLD
TA
ASIZE
External Memory Interface (EMIF)
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Chapter 18
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Parameter Overlay Module (POM)
This chapter describes the parameter overlay module (POM).
Topic
18.1
18.2
18.3
...........................................................................................................................
Page
Introduction ..................................................................................................... 676
Module Operation ............................................................................................. 677
POM Control Registers ...................................................................................... 679
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18.1 Introduction
In many applications it is important to be able to change certain parameters in the program without having
to re-flash the device and immediately test these changes either in a hardware-in-the-loop simulation or in
a real environment.
The POM provides a mechanism to redirect accesses to non-volatile memory into a volatile memory
internal or external to the device. The data requested by the CPU will be fetched from the overlay memory
instead of the main non-volatile memory.
18.1.1 Main Features
•
•
•
Redirects program memory accesses to internal or external memory (overlay memory)
Up to 8 MByte of external overlay memory
Provides up to 32 programmable memory regions to replace non-volatile memory
– Programmable region start address
– Programmable region size (64 Bytes up to 256 kBytes in power of 2 steps)
18.1.2 Parameter Overlay Module (POM) Considerations
•
•
•
•
676
The POM can map onto up to 8MB of the internal or external memory space. The starting address and
the size of the memory overlay are configurable through the POM control registers. Care must be
taken to ensure that the overlay is mapped on to available memory.
ECC must be disabled by software through CP15 in case POM overlay is enabled; otherwise ECC
errors will be generated.
POM overlay must not be enabled when the flash and internal RAM memories are swapped through
the MEM SWAP field of the Bus Matrix Module Control Register 1 (BMMCR1).
When POM is used to overlay the flash on to internal or external RAM, there is a bus contention
possibility when another master accesses the TCM flash. This results in a system hang.
– The POM implements a timeout feature to detect this exact scenario. The timeout needs to be
enabled whenever POM overlay is enabled.
– The timeout can be enabled by writing Ah to the enable timeout (ETO) field of the POM global
control register (POMGLBCTRL).
– In case a read request by the POM cannot be completed within 32 HCLK cycles, the timeout (TO)
flag is set in the POM status register (POMFLG). Also, an abort is generated to the CPU. This can
be a prefetch abort for an instruction fetch or a data abort for a data fetch.
– The prefetch-abort and data-abort handlers must be modified to check if the TO flag in the POM is
set. If so, then the application can assume that the timeout is caused by a bus contention between
the POM transaction and another master accessing the same memory region. The abort handlers
need to clear the TO flag, so that any further aborts are not misinterpreted as having been caused
due to a timeout from the POM.
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18.1.3 Block Diagram
Figure 18-1. System Overlay Block Diagram
ext.
Mem Bus
External
Memory
(overlay)
EMIF
Internal
RAM
SCR
POM
Data
Data
Program
Memory
Address
Wrapper
Address
18.2 Module Operation
The POM has up to 32 programmable regions. Whenever the CPU requests data from the non-volatile
memory which address falls into one of the programmed regions, the POM will request the data from the
overlay memory. Wait states will be automatically inserted until the data is available from the overlay
memory. This ensures that the overlay memory has the same (in the case that the latency from overlay
memory is less than the program memory latency) or slower access time than the program memory.
The POM does not provide a feature to write into the overlay memory. The write has to be performed
directly to the memory mapped address space of the overlay memory.
When the module is disabled, no redirection of access will be performed.
NOTE: The overlay feature is not available for any other bus masters other than the main CPU. Any
attempt to access overlaid memory via the POM by any other bus master would result in a
deadlock situation (system hang). Other bus masters need to access the target internal or
external memory directly.
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18.2.1 Decode Regions
There are 32 decode regions. Regions are defined by a start address and a region size. The start address
is 23 bits wide to cover the maximum 8 MByte address space defined for program memory. The region
size ranges from 64 Bytes to 256 kBytes with a step size of power of 2. If a region size of 0 is selected,
the region is disabled. To support overlay memory that is not the same size as the program memory, an
overlay start address that is 23-bits wide can be specified. The size of the overlay region is the same as
the program memory region. The start address of both program memory and overlay memory region have
to be a multiple of the programmed region size. When the address of the access falls into one of the
programmed regions, the POM will start requesting the data from the overlay memory address, based on
the overlay start address. If the address falls into multiple overlapping regions, the region with the lowest
number has highest priority and only one read request from overlay memory will be initiated. This avoids
that regions with the same program memory address, but different overlay memory addresses, request
different data.
Figure 18-2. Region Definition Example
Overlay Memory
Program Memory
0x00000000
0x00001000
1 kByte
64 Byte
0x00000400
64 Byte
0x00024400
1 kByte
18.2.2 Bus Errors on Accesses via POM
In case a read by the POM cannot be completed within 32 HCLK cycles due to other transactions ongoing
or due to other bus errors, a timeout mechanism is implemented. This timeout mechanism is disabled by
default and must be enabled by writing Ah to the enable timeout (ETO) field of the POM global control
register (POMGLBCTRL).
An abort is generated to the host CPU when this timeout occurs. The host CPU responds by either taking
the prefetch abort or the data abort exceptions depending on the nature of the access that caused the
timeout.
The abort handler can check if the TO flag is set in the POM module's flag register (POMFLG). If this flag
is set, then the application can assume that the timeout is caused by the POM access not completing.
This flag must be cleared so that any further aborts are not misinterpreted as having been caused by
timeout on a POM access.
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18.3 POM Control Registers
Table 18-1 lists the Parameter Overlay Module registers. The registers support only 32-bit writes. The
offset is relative to the associated peripheral select. The base address for the control packets is
FFA0 4000h.
Table 18-1. POM Registers
Offset
Acronym
Register Description
00h
POMGLBCTRL
POM Global Control Register
Section 18.3.1
Section
04h
POMREV
POM Revision ID
Section 18.3.2
08h
POMCLKCTRL
POM Clock Gate Control Register
Section 18.3.3
0Ch
POMFLG
POM Status Register
Section 18.3.4
200h, 210h, ...,
3F0h
POMPROGSTARTx
POM Program Region Start Address Register x
Section 18.3.5
204h, 214h, ...,
3F4h
POMOVLSTARTx
POM Overlay Region Start Address Register x
Section 18.3.6
208h, 218h, ...,
3F8h
POMREGSIZEx
POM Region Size Register x
Section 18.3.7
Section 18.3.8
F00h
POMITCTRL
POM Integration Control Register
FA0h
POMCLAIMSET
POM Claim Set Register
Section 18.3.9
FA4h
POMCLAIMCLR
POM Claim Clear Register
Section 18.3.10
FB0h
POMLOCKACCESS
POM Lock Access Register
Section 18.3.11
FB4h
POMLOCKSTATUS
POM Lock Status Register
Section 18.3.12
FB8h
POMAUTHSTATUS
POM Authentication Status Register
Section 18.3.13
FC8h
POMDEVID
POM Device ID Register
Section 18.3.14
FCCh
POMDEVTYPE
POM Device Type Register
Section 18.3.15
FD0h
POMPERIPHERALID4
POM Peripheral ID 4 Register
Section 18.3.16
FD4h
POMPERIPHERALID5
POM Peripheral ID 5 Register
Section 18.3.17
FD8h
POMPERIPHERALID6
POM Peripheral ID 6 Register
Section 18.3.18
FDCh
POMPERIPHERALID7
POM Peripheral ID 7 Register
Section 18.3.19
FE0h
POMPERIPHERALID0
POM Peripheral ID 0 Register
Section 18.3.20
FE4h
POMPERIPHERALID1
POM Peripheral ID 1 Register
Section 18.3.21
FE8h
POMPERIPHERALID2
POM Peripheral ID 2 Register
Section 18.3.22
FECh
POMPERIPHERALID3
POM Peripheral ID 3 Register
Section 18.3.23
FF0h
POMCOMPONENTID0
POM Component ID 0 Register
Section 18.3.24
FF4h
POMCOMPONENTID1
POM Component ID 1 Register
Section 18.3.25
FF8h
POMCOMPONENTID2
POM Component ID 2 Register
Section 18.3.26
FFCh
POMCOMPONENTID3
POM Component ID 3 Register
Section 18.3.27
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18.3.1 POM Global Control Register (POMGLBCTRL)
This register contains a key to enable the POM module. Logic remains reset until this key is set.
Figure 18-3. POM Global Control Register (POMGLBCTRL) [address = FFA0 4000h]
31
23
15
22
16
OTADDR
Reserved
R/WP-60h
R-0
12
11
8
7
4
3
0
Reserved
ETO
Reserved
ON/OFF
R-0
R/WP-5h
R-0
R/WP-5h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 18-2. POM Global Control Register (POMGLBCTRL) Field Descriptions
Bit
Field
Value
31-23
OTADDR
60h
22-12
Reserved
0
11-8
ETO
All other values
Reserved
3-0
ON/OFF
Overlay target Address.
These bits determine the upper address bits of the target overlay address. Writing a different
value to this field will steer the POM access to a different location in the 4GB address space.
The application must ensure that the overlay memory address points to a valid internal or
external memory location.
Reads return 0, writes have no effect.
Enable Timeout. Refer to Section 18.2.2 for more details on the timeout error.
Ah
7-4
Description
0
Timeout for bus transactions is enabled.
Timeout for bus transactions is disabled. The timeout is disabled by default.
Reads return zeros, writes have no effect.
Turn functionality of POM on or off.
Ah
All other values
POM is functional.
POM is held in reset.
NOTE: The key should be written to 5h, to avoid single bit flips inadvertently turning on the
module.
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18.3.2 POM Revision ID (POMREV)
This register contains the revision ID of the POM module.
Figure 18-4. POM Revision ID (POMREV) [address = FFA0 4004h]
31
30
29
28
27
16
SCHEME
Reserved
FUNC
R-1h
R-0
R-A03h
15
11
10
8
7
6
5
0
RTL
MAJOR
CUSTOM
MINOR
R-0
R-1h
R-0
R-8h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18-3. POM Revision ID (POMREV) Field Descriptions
Bit
Field
Value
Description
31-30
SCHEME
1h
Used to distinguish between different ID schemes.
29-28
Reserved
0
Reads return 0, writes have no effect.
27-16
FUNC
15-11
RTL
0
RTL version number.
10-8
MAJOR
1h
Major revision number.
7-6
CUSTOM
0
Indicates a device specific implementation.
5-0
MINOR
8h
Minor revision number.
A03h
Indicates the SW compatible module family.
18.3.3 POM Clock Gate Control Register (POMCLKCTRL)
This register is for TI internal use only.
Figure 18-5. POM Clock Gate Control Register [address = FFA0 4008h]
31
16
Reserved
R-0
15
0
Reserved
CLK GATE OFF
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18-4. POM Clock Gate Control Register (POMCLKCTRL) Field Descriptions
Bit
31-1
0
Field
Value
Description
Reserved
0
Reads return 0, writes have no effect.
CLK GATE OFF
0
Do not modify this bit. Leave it in its reset state. Modifying the bit while the POM module is
switched on can result in unexpected behavior.
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18.3.4 POM Status Register (POMFLG)
This register provides POM status information.
Figure 18-6. POM Status Register [address = FFA0 400Ch]
31
16
Reserved
R-0
15
0
Reserved
TO
R-0
R/W1CP-0
LEGEND: R/W = Read/Write; R = Read only; W1CP = Write 1 to clear in privilege mode only; -n = value after reset
Table 18-5. POM Status Register (POMFLG) Field Descriptions
Bit
31-1
0
Field
Reserved
Value
0
TO
Description
Reads return 0, writes have no effect.
Timeout.
This flag signals a timeout condition on the last CPU read access through the POM. This flag is only
updated when the POM module is enabled (ON/OFF = Ah).
0
Read: No timeout occurred.
Write: No effect.
1
Read: Timeout occurred.
Write: Bit is cleared.
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18.3.5 POM Program Region Start Address Register x (POMPROGSTARTx)
This register contains the start address of the region in program memory. x goes from 0 to 31, since up to
32 regions can be defined.
Figure 18-7. POM Program Region Start Register x (POMPROGSTARTx) [address = FFA0 4200h,
FFA0 4210h, ..., FFA0 43F0h]
31
23
22
16
Reserved
STARTADDRESS
R-0
R/WP-0
15
0
STARTADDRESS
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 18-6. POM Program Region Start Address Register x (POMPROGSTARTx) Field Descriptions
Bit
Field
31-23
Reserved
22-0
STARTADDRESS
Value
0
Description
Reads return 0, writes have no effect.
Defines the start address of the program memory region. The start address has to be a multiple of
the region size.
NOTE: If the region start address is programmed to a non-region size boundary, the region will
begin at the next lower region size boundary.
18.3.6 POM Overlay Region Start Address Register x (POMOVLSTARTx)
This register contains the start address of the region in overlay memory. x goes from 0 to 31, since up to
32 regions can be defined.
Figure 18-8. POM Overlay Region Start Register x (POMOVLSTARTx) [address = FFA0 4204h, FFA0
4214h, ..., FFA0 43F4h]
31
23
22
16
Reserved
STARTADDRESS
R-0
R/W-0
15
0
STARTADDRESS
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18-7. POM Overlay Region Start Address Register x (POMOVLSTARTx) Field Descriptions
Bit
Field
31-23
Reserved
22-0
STARTADDRESS
Value
0
Description
Reads return 0, writes have no effect.
Defines the start address of the overlay memory region. The start address has to be a multiple of
the region size.
NOTE: If the region start address is programmed to a non-region size boundary, the region will
begin at the next lower region size boundary.
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18.3.7 POM Region Size Register x (POMREGSIZEx)
This register contains the region size for both program memory and overlay memory. x goes from 0 to 31,
since up to 32 regions can be defined.
Figure 18-9. POM Region Size Register x (POMREGSIZEx) [address = FFA0 4208h, FFA0 4218h, ...,
FFA0 43F8h]
31
16
Reserved
R-0
15
4
3
0
Reserved
SIZE
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18-8. POM Region Size Register x (POMREGSIZEx) Field Descriptions
Bit
Field
Value
31-4
Reserved
3-0
SIZE
0
Description
Reads return 0, writes have no effect.
Region size
0
Region is disabled.
1h
64 Bytes
2h
128 Bytes
:
Dh
Eh-Fh
:
256 kBytes
Reserved
NOTE: If the region is enabled by writing a non-zero value to the SIZE bitfield, it will take some
number of VCLK cycles until the write takes effect. If during this time an access to the
programmed region is taking place and the POM is already enabled in the POMGLBCTRL
register, it either decodes the previous setting of the SIZE field or the access will be directed
to the program memory when the region was disabled.
18.3.8 POM Integration Control Register (POMITCTRL)
This is a CoreSight register and is for debug purpose only. The integration functionality is not
implemented. The register reads 00000000.
Figure 18-10. POM Integration Control Register (POMITCTRL) [address = FFA0 4F00h]
31
0
Reserved
R-0
LEGEND: R = Read only; -n = value after reset
Table 18-9. POM Integration Control Register (POMITCTRL) Field Descriptions
Bit
31-0
684
Field
Reserved
Value
0
Description
Reads return 0, writes have no effect.
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18.3.9 POM Claim Set Register (POMCLAIMSET)
This is a CoreSight register and is for debug purpose only. This register allows different masters to claim
the control for the POM module. There is no control functionality for POM register accesses implemented.
The only functionality of these bits is to indicate that another master is controlling the module.
Figure 18-11. POM Claim Set Register (POMCLAIMSET) [address = FFA0 4FA0h]
31
16
Reserved
R-0
15
1
0
Reserved
2
SET1
SET0
R-0
R/W-1
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18-10. POM Claim Set Register (POMCLAIMSET) Field Descriptions
Bit
31-2
1
Field
Reserved
Value
0
SET1
Description
Reads return 0, writes have no effect.
The module is claimed.
0
Read: This claim tag bit is not implemented.
Write: No effect.
1
Read: This claim tag is implemented.
Write: Set claim tag.
0
SET0
The module is claimed.
0
Read: This claim tag bit is not implemented.
Write: No effect.
1
Read: This claim tag is implemented.
Write: Set claim tag.
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18.3.10 POM Claim Clear Register (POMCLAIMCLR)
This is a CoreSight register and is for debug purpose only. This register allows different masters to claim
the control for the POM module. There is no control functionality for POM register accesses implemented.
The only functionality of these bits is to indicate that another master is controlling the module.
Figure 18-12. POM Claim Clear Register (POMCLAIMCLR) [address = FFA0 4FA4h]
31
16
Reserved
R-0
15
1
0
Reserved
2
CLR1
CLR0
R-0
R/W-1
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18-11. POM Claim Clear Register (POMCLAIMCLR) Field Descriptions
Bit
31-2
1
Field
Reserved
Value
0
CLR1
Description
Reads return 0, writes have no effect.
The module is claimed.
Read: Current claim tag value.
0
0
Write: No effect.
1
Write: Clear claim tag.
CLR0
The module is claimed.
Read: Current claim tag value.
686
0
Write: No effect.
1
Write: Clear claim tag.
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18.3.11 POM Lock Access Register (POMLOCKACCESS)
This is a CoreSight register and is for debug purpose only. The register reads 00000000.
Figure 18-13. POM Lock Access Register (POMLOCKACCESS) [address = FFA0 4FB0h]
31
0
Reserved
R-0
LEGEND: R = Read only; -n = value after reset
Table 18-12. POM Lock Access Register (POMLOCKACCESS) Field Descriptions
Bit
31-0
Field
Value
Reserved
0
Description
Reads return 0, writes have no effect.
18.3.12 POM Lock Status Register (POMLOCKSTATUS)
This is a CoreSight register and is for debug purpose only. The register reads 00000000.
Figure 18-14. POM Lock Status Register (POMLOCKSTATUS) [address = FFA0 4FB4h]
31
0
Reserved
R-0
LEGEND: R = Read only; -n = value after reset
Table 18-13. POM Lock Status Register (POMLOCKSTATUS) Field Descriptions
Bit
31-0
Field
Reserved
Value
0
Description
Reads return 0, writes have no effect.
18.3.13 POM Authentication Status Register (POMAUTHSTATUS)
This is a CoreSight register and is for debug purpose only. The register reads 00000000.
Figure 18-15. POM Authentication Status Register (POMAUTHSTATUS) [address = FFA0 4FB8h]
31
0
Reserved
R-0
LEGEND: R = Read only; -n = value after reset
Table 18-14. POM Authentication Status Register (POMAUTHSTATUS) Field Descriptions
Bit
31-0
Field
Reserved
Value
0
Description
Reads return 0, writes have no effect.
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18.3.14 POM Device ID Register (POMDEVID)
This is a CoreSight register and is for debug purpose only. The register reads 00000000.
Figure 18-16. POM Device ID Register (POMDEVID) [address = FFA0 4FC8h]
31
0
Reserved
R-0
LEGEND: R = Read only; -n = value after reset
Table 18-15. POM Device ID Register (POMDEVID) Field Descriptions
Bit
31-0
Field
Value
Reserved
0
Description
Reads return 0, writes have no effect.
18.3.15 POM Device Type Register (POMDEVTYPE)
This is a CoreSight register and is for debug purpose only. The device type register defines the CoreSight
module class.
Figure 18-17. POM Device Type Register (POMDEVTYPE) [address = FFA0 4FCCh]
31
16
Reserved
R-0
15
8
7
4
3
0
Reserved
Sub Type
Major Type
R-0
R-0
R-4h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18-16. POM Device Type Register (POMDEVTYPE) Field Descriptions
Bit
Field
31-8
Reserved
7-4
3-0
688
Value
Description
0
Reads return 0, writes have no effect.
Sub Type
0
Other
Major Type
4h
Debug Control
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18.3.16 POM Peripheral ID 4 Register (POMPERIPHERALID4)
This is a CoreSight register and is for debug purpose only. This register shows the peripheral identification
of the CoreSight component.
Figure 18-18. POM Peripheral ID 4 Register (POMPERIPHERALID4) [address = FFA0 4FD0h]
31
16
Reserved
R-0
15
8
7
4
3
0
Reserved
4KB Count
JEP106 Continuation Code
R-0
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18-17. POM Peripheral ID 4 Register (POMPERIPHERALID4) Field Descriptions
Bit
Field
Value
Description
31-8
Reserved
0
Reads return 0, writes have no effect.
7-4
4KB Count
0
Only 4KB is implemented.
3-0
JEP Continuation
Code
0
JEP106 Code
18.3.17 POM Peripheral ID 5 Register (POMPERIPHERALID5)
This is a CoreSight register and is for debug purpose only. This register reads 00000000.
Figure 18-19. POM Peripheral ID 5 Register (POMPERIPHERALID5) [address = FFA0 4FD4h]
31
0
Reserved
R-0
LEGEND: R = Read only; -n = value after reset
Table 18-18. POM Peripheral ID 5 Register (POMPERIPHERALID5) Field Descriptions
Bit
31-0
Field
Reserved
Value
0
Description
Reads return 0, writes have no effect.
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18.3.18 POM Peripheral ID 6 Register (POMPERIPHERALID6)
This is a CoreSight register and is for debug purpose only. This register reads 00000000.
Figure 18-20. POM Peripheral ID 6 Register (POMPERIPHERALID6) [address = FFA0 4FD8h]
31
0
Reserved
R-0
LEGEND: R = Read only; -n = value after reset
Table 18-19. POM Peripheral ID 6 Register (POMPERIPHERALID6) Field Descriptions
Bit
31-0
Field
Value
Reserved
0
Description
Reads return 0, writes have no effect.
18.3.19 POM Peripheral ID 7 Register (POMPERIPHERALID7)
This is a CoreSight register and is for debug purpose only. This register reads 00000000.
Figure 18-21. POM Peripheral ID 7 Register (POMPERIPHERALID7) [address = FFA0 4FDCh]
31
0
Reserved
R-0
LEGEND: R = Read only; -n = value after reset
Table 18-20. POM Peripheral ID 7 Register (POMPERIPHERALID7) Field Descriptions
Bit
31-0
690
Field
Reserved
Value
0
Description
Reads return 0, writes have no effect.
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18.3.20 POM Peripheral ID 0 Register (POMPERIPHERALID0)
This is a CoreSight register and is for debug purpose only. This register shows the peripheral identification
of the CoreSight component.
Figure 18-22. POM Peripheral ID 0 Register (POMPERIPHERALID0) [address = FFA0 4FE0h]
31
16
Reserved
R-0
15
8
7
0
Reserved
Part Number
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18-21. POM Peripheral ID 0 Register (POMPERIPHERALID0) Field Descriptions
Bit
Field
Value
Description
31-8
Reserved
0
Reads return 0, writes have no effect.
7-0
Part Number
0
Reads 0, since POMREV defines the module.
18.3.21 POM Peripheral ID 1 Register (POMPERIPHERALID1)
This is a CoreSight register and is for debug purpose only. This register shows the peripheral identification
of the CoreSight component.
Figure 18-23. POM Peripheral ID 1 Register (POMPERIPHERALID1) [address = FFA0 4FE4]
31
16
Reserved
R-0
15
8
7
4
3
0
Reserved
JEP106 Identity Code
Part Number
R-0
R-7h
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18-22. POM Peripheral ID 1 Register (POMPERIPHERALID1) Field Descriptions
Bit
Field
Value
Description
31-8
Reserved
0
Reads return 0, writes have no effect.
7-4
JEP106 Identity
Code
7h
Part of TI JEDEC number.
3-0
Part Number
0
Reads 0, since POMREV defines the module.
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18.3.22 POM Peripheral ID 2 Register (POMPERIPHERALID2)
This is a CoreSight register and is for debug purpose only. This register shows the peripheral identification
of the CoreSight component.
Figure 18-24. POM Peripheral ID 2 Register (POMPERIPHERALID2) [address = FFA0 4FE8h]
31
16
Reserved
R-0
15
8
7
4
3
2
0
Reserved
Revision
JEDEC
JEP106 Identity Code
R-0
R-0
R-1h
R-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18-23. POM Peripheral ID 2 Register (POMPERIPHERALID2) Field Descriptions
Bit
Field
Value
Description
31-8
Reserved
0
Reads return 0, writes have no effect.
7-4
Revision
0
Reads 0, since POMREV defines the module.
3
JEDEC
1h
Indicates JEDEC assigned value.
JEP106 Identity
Code
1h
JEDEC+JEP106 Identity Code (POMPERIPHERALID2)+JEP106 Identity Code
(POMPERIPHERALID1) form TI JEDEC ID of 97h.
2-0
18.3.23 POM Peripheral ID 3 Register (POMPERIPHERALID3)
This is a CoreSight register and is for debug purpose only. This register reads 00000000.
Figure 18-25. POM Peripheral ID 3 Register (POMPERIPHERALID3) [address = FFA0 4FECh]
31
0
Reserved
R-0
LEGEND: R = Read only; -n = value after reset
Table 18-24. POM Peripheral ID 3 Register (POMPERIPHERALID3) Field Descriptions
Bit
31-0
692
Field
Reserved
Value
0
Description
Reads return 0, writes have no effect.
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18.3.24 POM Component ID 0 Register (POMCOMPONENTID0)
This is a CoreSight register and is for debug purpose only.
Figure 18-26. POM Component ID 0 Register (POMCOMPONENTID0) [address = FFA0 4FF0h]
31
16
Reserved
R-0
15
8
7
0
Reserved
Preamble
R-0
R-Dh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18-25. POM Component ID 0 Register (POMCOMPONENTID0) Field Descriptions
Bit
Field
Value
31-8
Reserved
0
7-0
Preamble
Dh
Description
Reads return 0, writes have no effect.
Preamble
18.3.25 POM Component ID 1 Register (POMCOMPONENTID1)
This is a CoreSight register and is for debug purpose only.
Figure 18-27. POM Component ID 1 Register (POMCPOMPONENTID1) [address = FFA0 4FF4h]
31
16
Reserved
R-0
15
8
7
4
3
0
Reserved
Component Class
Preamble
R-0
R-9h
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18-26. POM Component ID 1 Register (POMCOMPONENTID1) Field Descriptions
Bit
Field
Value
Description
31-8
Reserved
0
Reads return 0, writes have no effect.
7-4
Component Class
9h
CoreSight Component
3-0
Preamble
0
Preamble
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18.3.26 POM Component ID 2 Register (POMCOMPONENTID2)
This is a CoreSight register and is for debug purpose only.
Figure 18-28. POM Component ID 2 Register (POMCPOMPONENTID2) [address = FFA0 4FF8h]
31
16
Reserved
R-0
15
8
7
0
Reserved
Preamble
R-0
R-5h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18-27. POM Component ID 2 Register (POMCOMPONENTID2) Field Descriptions
Bit
Field
Value
Description
31-8
Reserved
0
Reads return 0, writes have no effect.
7-0
Preamble
5h
Preamble
18.3.27 POM Component ID 3 Register (POMCOMPONENTID3)
This is a CoreSight register and is for debug purpose only.
Figure 18-29. POM Component ID 3 Register (POMCPOMPONENTID3) [address = FFA0 4FFCh]
31
16
Reserved
R-0
15
8
7
0
Reserved
Preamble
R-0
R-B1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18-28. POM Component ID 3 Register (POMCOMPONENTID3) Field Descriptions
Bit
Field
Value
31-8
Reserved
0
7-0
Preamble
B1h
694
Description
Reads return 0, writes have no effect.
Preamble
Parameter Overlay Module (POM)
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Chapter 19
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Analog To Digital Converter (ADC) Module
This chapter describes the analog to digital converter (ADC) module.
Topic
...........................................................................................................................
19.1
19.2
19.3
19.4
19.5
19.6
19.7
19.8
19.9
19.10
19.11
Overview .........................................................................................................
Introduction .....................................................................................................
Basic Features and Usage of the ADC.................................................................
Advanced Conversion Group Configuration Options ............................................
ADC Module Basic Interrupts .............................................................................
ADC Module DMA Requests...............................................................................
ADC Magnitude Threshold Interrupts ..................................................................
ADC Special Modes ..........................................................................................
ADC Results’ RAM Special Features ...................................................................
ADEVT Pin General Purpose I/O Functionality ....................................................
ADC Control Registers .....................................................................................
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19.1 Overview
The microcontroller includes two 12-bit ADC modules. The main features of each of the ADC modules are:
• Selectable 10-bit or 12-bit resolution, 10-bit mode is the default
• Successive-approximation-register architecture
• Three conversion groups – Group1, Group2 and Event Group
• All three conversion groups can be configured to be hardware-triggered; group1 and group2 can also
be triggered by software
• Conversion results are stored in a 64-word memory (SRAM)
– These 64 words are divided between the three conversion groups and are configurable by software
– Accesses to the conversion result RAM are protected by parity
• Flexible options for generating DMA requests for transferring conversion results
• Multichannel conversions performed in ascending order, one channel at a time
• Single or continuous conversion modes
• Embedded self-test logic for input channel failure mode (open / short) detection
• Embedded calibration logic for offset error correction
• Enhanced Power-down mode
• External event pin (ADEVT) to trigger conversions
– ADEVT is also programmable as general-purpose I/O
• Eight hardware events to trigger conversions
The two instances of the 12-bit ADC modules on the microcontroller share 16 analog input channels. The
connections are shown in Figure 19-1.
• ADC1 supports 24 channels
• ADC2 supports 16 channels, all of which are shared with ADC1
• When using both ADC1 and ADC2 on a shared channel, the sample windows must be identical such
that the sample windows completely match each other or non-overlapping with a minimum of 2 ADC
cycles buffer between the end of one ADC’s sample window and the start of the other ADC’s sample
window.
• The reference voltages, as well as operating supply and ground, are shared between the two ADC
cores.
Figure 19-1. Channel Assignments of Two ADC Cores
AD1IN[7:0]
AD1EVT
AD1IN[23:8]
ADC1
12 Bit
VCCAD
VSSAD
ADREFHI
ADREFLO
AD2EVT
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ADC2
12 Bit
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19.2 Introduction
This section presents a brief functional description of the analog-to-digital converter (ADC) module.
Figure 19-2 illustrates the components of the ADC module.
Figure 19-2. ADC Block Diagram
ADIN0
ADREFLO
ADREFHI
10/12-bit
AIN Successive Approximation
Analog-to-Digital
Converter
Control Signals
24 – 1 Input Multiplexor
ADIN23
VSSAD
VCCAD
Self-Test and
Calibration Cell
End Of
Conversion
Sequencer and
ADC Results’ Memory Interface
Controller
10/12-bit
Result
ADC Results’
Memory
VBUS Interface for Access to
ADC Registers
VBUSP
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19.2.1 Input Multiplexor
The input multiplexor (MUX) connects the selected input channel to the AIN input of the ADC core. The
ADC1 module supports up to 24 inputs as shown in Figure 19-2. The ADC2 module supports up to 16
inputs. The sequencer selects the channel to be converted.
19.2.2 Self-Test and Calibration Cell
The ADC includes specific hardware that allows a software algorithm to detect open/short on an ADC
analog input. It also allows the application program to calibrate the ADC. Also see Section 19.8.1 and
Section 19.8.2.
19.2.3 Analog-to-Digital Converter Core
The ADC core is a combination voltage scaling, charge redistribution Successive Approximation Register
(SAR) based analog-to-digital converter. The core can be configured for operation in 10-bit resolution
(default) or 12-bit resolution. This is controlled by the sequencer logic. This selection applies to all
conversions performed by the ADC module. It is not possible to convert some channels with a 12-bit
resolution and some with a 10-bit resolution.
A single conversion from an analog input to a digital conversion result occurs in two distinct periods:
• Sampling Period:
– The sequencer generates a START signal to the ADC core to signal the start of the sampling
period.
– The analog input signal is sampled directly on to the switched capacitor array during this period,
providing an inherent sample-and-hold function.
– The sampling period ends one full ADCLK after the falling edge of the START signal.
– The sequencer can control the sampling period duration by configuring the conversion group’s
sample time control register (ADEVSAMP, ADG1SAMP, ADG2SAMP). This register controls the
time for which the START signal stays high.
• Conversion Period:
– The conversion period starts one full ADCLK after the falling edge of START.
– One bit of the conversion result is output on each rising edge of ADCLK in the conversion period,
starting with the most-significant bit first.
– The conversion period is 12 ADCLK cycles in case of a 12-bit ADC, and is 10 ADCLK cycles in
case of a 10-bit ADC.
– The ADC core generates an End-Of-Conversion (EOC) signal to the sequencer at the end of the
conversion period. At this time the complete 12-, or 10-bit conversion result is available.
– The sequencer captures the ADC core conversion result output as soon as EOC is driven High.
The analog conversion range is determined by the reference voltages: ADREFHI and ADREFLO. ADREFHI is the
top reference voltage and is the maximum analog voltage that can be converted. An analog input voltage
equal to ADREFHI or higher results in an output code of 0x3FF for 10-bit resolution and 0xFFF for 12-bit
resolution. ADREFLO is the bottom reference voltage and is the minimum analog voltage that can be
converted. Applying an input voltage equal to ADREFLO or lower results in an output code of 0x000. Both
ADREFHI and ADREFLO must be chosen not to exceed the analog power supplies: VCCAD and VSSAD,
respectively. Input voltages between ADREFHI and ADREFLO produce a conversion result given by
Equation 27 for 10-bit resolution and by Equation 28 for 12-bit resolution.
698
1024 x (InputVoltage - AD REFLO)
DigitalResult = -------------------------------------------------------------------------------------- – 0.5
AD REFHI - AD REFLO
(27)
4096 x(InputVoltage - AD REFLO) – 0.5
DigitalResult = -------------------------------------------------------------------------------------(AD REFHI - AD REFLO)
(28)
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19.2.4 Sequencer
The sequencer coordinates the operations of the ADC, including the input multiplexor, the ADC core, and
the result memory. In addition, the logic of the sequencer sets the status register flags when the
conversion is ongoing, stopped, or finished.
All the features of the sequencer are discussed in detail in the following sections of this document.
19.2.5 Conversion Groups
Several applications require groups of channels to be converted using a single trigger source for example.
There could also be some groups of channels identified which require a specific setting of the acquisition
time. The ADC module supports three conversion groups for this purpose – Group1, Group2 and the
Event Group.
Any of the available analog input channels can be assigned to any of the conversion groups. This also
allows a particular channel to be repeatedly sampled by selecting it in multiple groups. There is an
inherent priority scheme used when multiple conversion groups are triggered at once. The Event Group is
the highest-priority, followed by the Group1 and then the Group2.
The Event Group is always hardware event-triggered. Group1 and Group2 are software-triggered by
default and can be configured to be hardware-, or event-triggered as well. The triggering of conversions in
each group is discussed in Section 19.3.6.
Each conversion group has a separate set of control registers to:
• Select the input channels to be converted
• Configure the mode of conversion: single conversion sequence or continuous conversions
• Configure the input channel sampling time
• Configure the interrupt and/or DMA request generation conditions
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19.3 Basic Features and Usage of the ADC
This section describes the usage of the basic features of the ADC module.
19.3.1 How to Select Between 12-bit and 10-bit Resolution
The 10_12_BIT field of the ADC Operating Mode Control Register (ADOPMODECR) configures the ADC
to be in 10-bit or 12-bit resolution mode.
• If 10_12_BIT = 0, the module is in 10-bit resolution mode. This is the default mode of operation.
• If 10_12_BIT = 1, the module is in 12-bit resolution mode.
19.3.2 How to Set Up the ADCLK Speed
The ADC sequencer generates the clock for the ADC core, ADCLK. The ADC core uses the ADCLK
signal for its timing. The ADCLK is generated by dividing down the input clock to the ADC module, which
is the VBUSP interface clock, VCLK. A 5-bit field (PS) in the ADC Clock Control Register (ADCLOCKCR)
is used to divide down the VCLK by 1 up to 32. The ADCLK valid frequency range is specified in the
device datasheet.
fADCLK = fVCLK / (PS + 1)
The maximum frequency for ADCLK is specified in the device datasheet.
19.3.3 How to Set Up the Input Channel Acquisition Time
The signal acquisition time for each group is separately configurable using the ADG1SAMP[11:0],
ADG2SAMP[11:0], and ADEVSAMP[11:0] registers.
The acquisition time is specified in terms of ADCLK cycles and ranges from a minimum of 2 ADCLK
cycles to a maximum of 4098 ADCLK cycles.
For example, Group1 acquisition time, tACQG1 = G1SAMP[11:0] + 2, in ADCLK cycles.
The minimum acquisition time is specified in the device datasheet. This time also depends on the
impedance of the circuit connected to the analog input channel being converted. See the ADC Source
Impedance for Hercules™ ARM® Safety MCUs Application Report (SPNA118).
19.3.4 How to Select an Input Channel for Conversion
The ADC module needs to be enabled first before selecting an input channel for conversion. The ADC
module can be enabled by setting the ADC EN bit in the ADC Operating Mode Control Register
(ADOPMODECR). Multiple input channels can be selected for conversion in each group. Only one input
channel is converted at a time. The channels to be converted are configured in one or more of the three
conversion groups’ channel selection registers. Channels to be converted in Group1 are configured in the
Group1 Channel-Select Register (ADG1SEL), those to be converted in Group2 are configured in the
Group2 Channel-Select Register (ADG2SEL), and those to be converted in the Event Group are
configured in the Event Group Channel-Select Register (ADEVSEL).
19.3.5 How to Select Between Single Conversion Sequence or Continuous Conversions
Each group has its own mode control register. The MODE field of these control registers allow the
application to select between a single conversion sequence or continuous conversion mode.
NOTE: Selecting continuous conversion mode for all three groups
All three conversion groups cannot be configured to be in a continuous conversion mode. If
the application configures the group mode control registers to enable continuous conversion
mode for all three groups, then the Group2 will be automatically be configured to be in a
single conversion sequence mode.
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With conversions ongoing in continuous conversion mode, if the MODE field of a group is cleared, then
that group switches to the single conversion sequence mode. Conversions for this group will stop once all
channels selected for that group have been converted.
19.3.6 How to Start a Conversion
The conversion groups Group1 and Group2 are software-triggered by default. A conversion in these
groups can be started just by writing the desired channels to the respective Channel-Select Registers. For
example, in order to convert channels 0, 1, 2, and 3 in Group1 and channels 8, 9, 10, and 11 in Group2,
the application just has to write 0x0000000F to ADG1SEL and 0x00000F00 to ADG2SEL. The ADC
module will start by servicing the group that was triggered first, Group1 in this example.
The conversions for all groups are performed in ascending order of the channel number. For the Group1
the conversions will be performed in the order: channel 0 first, followed by channel 1, then channel 2, and
then channel 3. The Group2 conversions will be performed in the order: channels 8, 9, 10, and 11.
The Event Group is only hardware-triggered. There are up to eight hardware event trigger sources defined
for the ADC module. Check the device datasheet for a complete listing of these eight hardware trigger
options.
The trigger source to be used needs to be configured in the ADEVSRC register. Similar registers also
exist for the Group1 and Group2 as these can also be configured to be event-triggered.
The polarity of the event trigger is also configurable, with a falling edge being the default.
An Event Group conversion starts when at least one channel is selected for conversion in this group, and
when the defined event trigger occurs.
If any conversion group is configured to be in a continuous conversion mode, then it needs to only be
triggered once. All the channels selected for conversion in that group will be converted repeatedly.
19.3.7 How to Know When the Group Conversion is Completed
Each conversion group has a status flag to indicate when its conversion has ended. See ADEVSR,
ADG1SR, and ADG2SR. This bit is set when a conversion sequence for a group ends. This bit does is
always set if a group is configured for continuous conversions.
19.3.8 How Results are Stored in the Results’ Memory
The ADC stores the conversion results in three separate memory regions in the ADC Results’ RAM, one
region for each group. Each memory region is a stack of buffers, with each buffer capable of holding one
conversion result. The number of buffers allocated for each group is programmed by configuring the ADC
module registers ADBNDCR and ADBNDEND.
ADBNDCR contains two 9-bit pointers BNDA and BNDB. BNDA, BNDB, and BNDEND are used to
partition the total memory available into three memory regions as shown in Figure 19-3. Both BNDA and
BNDB are pointers referenced from the start of the results’ memory. BNDA specifies the number of buffers
allocated for the Event Group conversion results in units of two buffers; BNDB specifies the number of
buffers allocated for the Event Group plus Group1 in units of two buffers. Please refer to Section 19.11.23
for more details on configuring the ADC results’ memory.
ADBNDEND contains a 3-bit field called BNDEND that configures the total memory available. The ADC
module can support up to 1024 buffers. The device supports a maximum of 64 buffers for both the ADC
modules.
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Figure 19-3. FIFO Implementation
0x00
Total Memory Depth
Event Memory Depth
BNDA
Group 1 Memory Depth
BNDB
Group 2 Memory Depth
BNDEND
•
•
•
Number of buffers for Event Group = 2 × BNDA
Number of buffers for Group1 = 2 × (BNDB – BNDA)
Number of buffers for Group2 = Total number of buffers – 2 × BNDB
19.3.9 How to Read the Results from the Results’ Memory
The CPU can read the conversion results in one of two ways:
1. By using the conversion results memory as a FIFO queue
2. By accessing the conversion results memory directly
19.3.9.1 Reading Conversion Results from a FIFO
The conversion results for each group can be accessed via a range of addresses provided to facilitate the
use of the ARM Cortex-R4 CPU’s Load-Multiple (LDM) instruction. A single read performed using the LDR
instruction can also be used to read out a single conversion result. The results are read out from the
group’s memory region as a FIFO queue by reading from any location inside this address range. The
conversion result that got stored first gets read first. A result that is read from the memory in this method
is removed from the memory. For example, a read from any address in the range ADEVBUFFER (offset
0x90 to 0xAF) pulls out one conversion result from the Event Group memory.
Figure 19-4. Format of Conversion Result Read from FIFO, 12-bit ADC
Offset Address
Register
0x90 to 0xAF
ADEVBUFFER
0xB0 to 0xCF
ADG1BUFFER
0xD0 to 0xEF
ADG2BUFFER
702
31
30
15
29
14
28
13
27
12
EV_
EMPTY
26
11
25
10
24
9
23
8
22
7
21
6
Reserved
Reserved
20
5
19
4
18
3
17
2
16
1
0
EV_CHID
EV_DR
G1_
EMPTY
Reserved
Reserved
G1_CHID
G1_DR
G2_
EMPTY
Reserved
Reserved
G2_CHID
G2_DR
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Figure 19-5. Format of Conversion Result Read from FIFO, 10-bit ADC
Offset Address
Register
0x90 to 0xAF
ADEVBUFFER
0xB0 to 0xCF
ADG1BUFFER
0xD0 to 0xEF
ADG2BUFFER
31
30
15
29
14
28
13
27
12
26
11
25
10
24
9
23
8
22
7
21
6
20
5
19
4
18
3
17
2
16
1
0
Reserved
EV_
EMPTY
EV_CHID
EV_DR
Reserved
G1_
EMPTY
G1_CHID
G1_DR
Reserved
G2_
EMPTY
G2_CHID
G2_DR
Option to read channel id along with conversion result:
The application has an option to read the channel id along with the conversion result. This is controlled by
the CHID field of the group’s mode control register. If the option to read the channel id is not selected, the
channel id field of the conversion result reads as zeros.
Protection against reading from empty FIFO:
There is also a hardware mechanism to protect the application from reading past the number of new
conversion results held in the FIFO. Once all available conversion results have been read out of the FIFO
by the application, a subsequent read from the FIFO causes the mechanism to indicate that the FIFO is
empty by setting the EMPTY field.
Debug / Emulation Support:
For debug purposes, each conversion group also provides an address that the application can read from
for extracting the group’s conversion results. However, no status flags for a conversion group are affected
by reading from these emulation buffer addresses. For example, reading from ADEVEMUBUFFER (offset
0xF0) returns the next result in the Event Group buffer but does not actually remove that result from the
buffer or change the amount of data held in the buffer.
19.3.9.2 Reading Conversion Results Directly from the Conversion Results’ Memory
The conversion result memory is part of the device’s memory map. The base address for the ADC1 result
memory is FF3E 0000h and for the ADC2 result memory is FF3A 0000h.
Figure 19-6. ADC Memory Mapping
ADC1
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0xFF3E0000 0xFF3A0000
Conversion word 0
0xFF3E0004 0xFF3A0004
Conversion word 1
0xFF3E0008 0xFF3A0008
Conversion word 2
0xFF3E01F8 0xFF3A01F8
Conversion word 62
0xFF3E00FC 0xFF3A00FC
Conversion word 63
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The application can identify the address ranges for each of the three memory regions for the three
conversion groups after performing the segmentation as described in Section 19.3.8. It is up to the
application to read the desired results from the three conversion groups. The formats of the conversion
results when reading from RAM directly are shown in the following figures.
Figure 19-7. Format of Conversion Result Directly Read from ADC RAM, 12-bit ADC
ADC
RAM
address
Reserved
channel id [3-0]
channel id [4]
12-bit conversion result
Figure 19-8. Format of Conversion Result Directly Read from ADC RAM, 10-bit ADC
ADC
RAM
address
Reserved
Rsvd
channel id [4-0]
10-bit conversion result
Note that there is no EMPTY field to protect the application from reading data that has been previously
read.
Each group does have a separate register which holds the address in the group’s result memory where
the ADC will write the next conversion result. These are the ADEVRAMWRADDR, ADG1RAMWRADDR,
and ADG2RAMWRADDR registers. The application can use this information to calculate how many valid
conversion results are available to be read.
Benefit of reading conversion results directly from ADC RAM:
The application does not have to read out conversion results sequentially as in the case of reading from a
FIFO. As a result, the application can selectively read the conversion results for any particular input
channel of interest without having to read other channels’ conversion results.
19.3.9.3 Example
Suppose that channels 0, 1, and 2 are selected for conversion in the Event Group, channels 4, 7, and 8
are selected for conversion in group 1, and channels 3, 5, and 6 are selected for conversion in group 2.
The conversion results will get stored in the three memory regions as shown in Figure 19-9.
Suppose that the CPU wants to read out the results for the Event Group from a FIFO queue. The CPU
needs to read from any address in the range ADEVBUFFER (offset 0x90 to 0xAF) multiple times, or do a
“load multiple” from this range of addresses. This will cause the ADC to return the results for channel 0,
then channel 1, then channel 2, then channel 0, and so on for each read access to this address range.
Now suppose that the application wants to read out the results for the group 1 from the RAM directly. The
conversion results for the group 1 are accessible starting from address ADC RAM Base Address + BNDA.
Also, it is known that the first result at this address is for the input channel 4, the next one is for input
channel 7, and so on. So the application can selectively read the conversion results for only one channel if
so desired.
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Figure 19-9. Conversion Results Storage
0x00
Channel 0
Channel 1
Channel 2
Channel 0
Channel 1
Event Group Memory
Channel 2
EV RAM ADDR
...
BNDA
Channel 4
Channel 7
Channel 8
Channel 4
Channel 7
Group 1 Memory
Channel 8
G1 RAM ADDR
...
BNDB
Channel 3
Channel 5
Channel 6
Channel 3
Channel 5
Group 2 Memory
Channel 6
G2 RAM ADDR
...
BNDEND
19.3.10 How to Stop a Conversion
A group’s conversion can be stopped by clearing the group’s channel select register.
19.3.11 Example Sequence for Basic Configuration of ADC Module
The following sequence is necessary to configure the ADC to convert channels 0, 2, 4, and 8 in singleconversion mode using Group1:
1. Write 0 to the Reset Control Register (ADRSTCR) to release the module from the reset state
2. Write 1 to the ADC_EN bit of the Operating Mode Control Register (ADOPMODECR) to enable the
ADC state machine
3. Configure the ADCLK frequency by programming the desired divider into the Clock Control Register
(ADCLOCKCR)
4. Configure the acquisition time for the group that is to be used. For example, configure the Group1
Sampling Time Control Register (ADG1SAMP) to set the acquisition time for Group1.
5. Select the channels that need to be converted in Group1 by writing to the Group1 Channel Select
Register (ADG1SEL). In this example, a value of 0x115 needs to be written to ADG1SEL in order to
select channels 0, 2, 4, and 8 for conversion in Group1.
• The ADC sequencer will start the Group1 conversions as soon as the write to the ADG1SEL
register is completed.
6. Wait for the G1_END bit to be set in the Group1 Conversion Status Register (ADG1SR). This bit gets
set when all the channels selected for conversion in Group1 are converted and the results are stored in
the Group1 memory.
7. Read the conversion results by reading from the Group1 FIFO access location (ADG1BUFFER) or by
reading directly from the Group1 results’ memory.
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19.4 Advanced Conversion Group Configuration Options
Figure 19-10 shows the operating mode control registers and the status registers for each of the three
conversion groups. The register addresses shown are offsets from the base address. The ADC1 register
frame base address is 0xFFF7C000 and the ADC2 register frame base address is 0xFFF7C200.
Figure 19-10. ADC Groups’ Operating Mode Control and Status Registers
Offset Address
Register
31
30
15
29
14
28
13
27
12
26
11
25
10
24
23
9
22
8
7
21
6
20
5
19
4
18
3
17
2
16
1
Reserved
0x010
ADEVMODECR
EV_
DATA_FMT
Reserved
Reserved
EV_
CHID
OVR_
EV_
RAM_
IGN
Rsvd
EV_
8BIT
EV_
MODE
0x014
ADG1MODECR
G1_
DATA_FMT
Reserved
G1_
CHID
OVR_
G1_
RAM_
IGN
Rsvd
G1_
8BIT
G1_
MODE
0x018
ADG2MODECR
G2_
DATA_FMT
Reserved
FRZ_
G1
No
Reset
On
ChnSel
Reserved
Reserved
FRZ_
EV
No
Reset
On
ChnSel
Reserved
Reserved
0
No
Reset
On
ChnSel
G2_
CHID
OVR_
G2_
RAM_
IGN
Rsvd
G2_
8BIT
G2_
MODE
FRZ_
G2
EV_
MEM_
EMPTY
EV_
BUSY
EV_
STOP
EV_
END
G1_
MEM_
EMPTY
G1_
BUSY
G1_
STOP
G1_
END
G2_
MEM_
EMPTY
G2_
BUSY
G2_
STOP
G2_
END
Reserved
0x06C
ADEVSR
Reserved
Reserved
0x070
ADG1SR
Reserved
Reserved
0x074
ADG2SR
Reserved
The following sections describe each of these group configuration options separately.
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19.4.1 Group Trigger Options
The Group1 and Group2 operating mode control registers have an extra control bit: HW TRIG. This bit
configures the group to be hardware event-triggered instead of software-triggered, which is the default.
When a group is configured to be event-triggered, the group conversion starts when at least one channel
is selected for conversion in this group, and when the defined event trigger occurs. The event trigger
source is defined for each group in the ADEVSRC, ADG1SRC, and the ADG2SRC registers. The actual
connections used as the event trigger sources are defined in the device datasheet for both the ADC
modules.
19.4.2 Single or Continuous Conversion Modes
The EV_MODE, G1_MODE, and G2_MODE bits are used to select between either single or continuous
conversion mode for each of the three groups.
19.4.2.1 Single Conversion Mode
A conversion group configured to be in single-conversion mode gets serviced only once by the ADC for
each group trigger. The trigger can be a software trigger as in the case of Group1 and Group2 by default,
or it could be a hardware event trigger as in the case of the Event Group or Group1 or Group2.
The entire conversion sequence, from the acceptance of the group conversion request to the end of the
last channel’s conversion, is flagged for each group by the corresponding BUSY bit in that group’s status
register. After single-conversion mode is started, the BUSY bit is read as 1 until the conversion of the last
channel is complete. The END bit for the group is set once all the channels in that group are converted.
For example, say channels 0, 2, 4, and 6 are selected for conversion in Group1 in single-conversion
mode. When the Group1 gets serviced, the ADC will start conversion for channel 0, then channel 2, then
channel 4, and then channel 6. It will then stop servicing the Group1, set the G1_END status bit, and look
to service the Event Group or the Group2, if required.
19.4.2.2 Continuous Conversion Mode
A conversion group configured to be in continuous-conversion mode gets serviced by the ADC
continuously. The group still needs to be triggered appropriately for the first conversion to start. The
conversions are performed continuously thereafter.
The entire conversion sequence, from the acceptance of the group conversion request to the end of the
last channel’s conversion, is flagged for each group by the corresponding BUSY bit in that group’s status
register. After continuous-conversion mode is started, the BUSY bit is read as 1 as long as the
continuous-conversion mode for this group is selected.
As an example, say the channels 0, 2, 4, and 6 are selected for conversion in Group1, now in continuousconversion mode. When the Group1 gets serviced, the ADC will complete conversions for channels 0, 2,
4, and 6, and then look to service the Event Group or the Group2. Once it is done servicing the Event
Group or the Group2, it will return to service the Group1 again. The Group1 does not need to be triggered
again for the repeated conversion.
NOTE: Configuring all conversion groups in continuous conversion mode
All the three groups cannot operate in continuous-conversion mode at the same time. If the
application program configures all three groups to be in continuous-conversion mode, the
Group2 is automatically reset to single-conversion mode, and the G2_MODE bit in the
ADG2MODECR register is cleared to reflect the single-conversion mode of Group2.
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19.4.3 Conversion Group Freeze Capability
The ADC module has an inherent priority order between the three conversion groups. This group priority
determines the order of conversion in case multiple groups are triggered. The priority of conversions
between the three groups in descending order is:
1. Event Group
2. Group1
3. Group2
Examples of conversion group priority:
• If an Event Group conversion is ongoing in single conversion sequence mode and Group2 and Group1
conversions are requested, then the ADC will finish conversion of channels selected in Event Group,
then switch over to converting channels selected in Group1, and then convert channels selected in
Group2.
• If Group1 conversions are ongoing in continuous conversion mode and Group2 conversion is
requested, then the ADC will complete converting the current channel for Group1 and switch over to
converting channels selected in Group2. The new conversion request for Group2 has a higher priority
than the pending continuous conversion request for Group1.
The conversion group freeze capability allows the application to override this default priority between the
conversion groups. Enabling the freeze capability allows the ADC to freeze a higher-priority conversion
group’s conversions whenever there is a request for conversion in another (lower-priority) group.
For example, setting the FRZ_EV bit in the ADEVMODECR register will allow the ADC to freeze ongoing
Event Group conversions whenever there is a pending request, or a new request for a Group1 or Group2
conversion. The conversions for the Event Group will be frozen as long as the Group1 or Group2
conversions are active. Once the Group1 or Group2 conversions are completed, the Event Group
conversions start from where they were frozen.
While a group’s conversions are frozen, the group’s STOP status bit is set. This bit is cleared once the
group’s conversions are restarted.
19.4.4 Conversion Group Memory Overrun Option
An overrun condition occurs when the ADC module tries to store more conversion results to a group’s
results’ memory which is already full. In this case, the ADC allows two options.
If the OVR_RAM_IGN bit in the group’s operating mode control register (ADEVMODECR,
ADG1MODECR, ADG1MODECR) is set, then the ADC module ignores the contents of the group’s results’
memory and wraps around to overwrite the memory with the results of new conversions.
If the OVR_RAM_IGN bit is not set, then the application program has to read out the group’s results’
memory upon an overrun condition; only then can the ADC continue to write new results to the memory.
19.4.5 Response on Writing Non-Zero Value to Conversion Group’s Channel Select Register
If the application writes a non-zero value to a group’s channel select register while that group’s
conversions are already being serviced, then that group’s conversions will be restarted with the new
configuration programmed in the channel select registers.
The following rules apply in terms of the effect on the ADC conversion sequence:
• If the new conversion request comes from the same group as the ongoing conversion, then the
ongoing conversion will be stopped in whichever stage it is in, and the new sequence of conversions
will be started.
• If the new conversion request comes from a separate group, then the ongoing channel’s conversion
will be completed before starting the new sequence of conversions.
The following rules apply in terms of the effect on the group’s results memory:
• If a group conversion is ongoing or is frozen, writing a non-zero value to the group’s channel select
register will also reset its results FIFO. This does not clear the contents of the results FIFO; only the
ADC module is allowed to overwrite the FIFO’s contents with new conversion results starting from the
first location.
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•
If the group conversion is completed (_END flag is set), or the group is not being used, then
writing a non-zero value to the group’s channel select register will either be reset or not depending on
the value of the NoResetOnChnSel bit for that group (ADEVMODECR, ADG1MODECR,
ADG1MODECR).
– If the NoResetOnChnSel bit is 0, then the group’s FIFO will be reset.
– If the NoResetOnChnSel bit is 1, then the group’s FIFO will not be reset.
19.4.6 Conversion Result Size on Reading: 8-bit, 10-bit or 12-bit
Some applications do not need the full 12-bit resolution of the ADC modules on the device and can work
with 8-bit or 10-bit conversion results.
19.4.6.1 ADC Configured in 12-bit Resolution
The mode control register for each conversion group contains a field called DATA_FMT, which defines the
format of the conversion result read out of the result RAM, when accessed as a FIFO.
The DATA_FMT field is encoded as follows:
• If DATA_FMT = 00, the complete 12-bit conversion result is read out of the FIFO.
• If DATA_FMT = 01, the 12-bit conversion result is right-shifted by 2 and the resulting 10-bit result is
read out of the FIFO.
• If DATA_FMT = 10, the 12-bit conversion result is right-shifted by 4 and the resulting 8-bit result is read
out of the FIFO.
This control field is not effective when the application chooses to access the conversion result memory
directly. In that case, the application can choose to mask off the number of bits as required.
19.4.6.2 ADC Configured in 10-bit Resolution
The DATA_FMT field is not effective in this mode and the application has the choice to read either the full
10-bit conversion result or an 8-bit conversion result. This is controlled by the 8BIT field of the group’s
operating mode control register.
• If 8BIT = 0, the complete 10-bit conversion result is read out of the FIFO.
• If 8BIT = 1, the 10-bit conversion result is right-shifted by 2 and the resulting 8-bit result is read out of
the FIFO.
19.4.7 Option to Read Group Channel ID Along with Conversion Result
The ADC module allows the application program to also read out the analog input channel number along
with its conversion result. This capability is enabled by setting the CHID bit in the group’s operating mode
control register.
• If CHID = 0, the bits [14-10] are forced to 00000 when the conversion results are read out from the
group’s results’ FIFO.
• If CHID = 1, the bits [14-10] in the group’s results’ memory contain the input channel number to which
the conversion result belongs.
NOTE: Actual Storage of Channel ID
Regardless of whether the CHID bit is set or not, the channel number is always stored in
the memory along with the conversion result. The CHID bit only affects whether the channel
number is available with the conversion result when the group’s memory is read.
Therefore, the CHID bit for a group can be changed dynamically without affecting that
group’s ongoing conversions.
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19.5 ADC Module Basic Interrupts
This section describes the basic interrupts generated by the ADC module.
19.5.1 Group Conversion End Interrupt
The ADC module sets the group’s conversion end flag (EV_END, G1_END, or G2_END) in that group’s
interrupt flag register (ADEVINTFLG, ADG1INTFLG, ADG2INTFLG) when all the channels selected for
conversion in that group are converted. This causes a group conversion end interrupt to be generated if
this interrupt is enabled by setting the group’s END_INT_EN control bit (EV_END_INT_EN,
G1_END_INT_EN, or G2_END_INT_EN).
This interrupt can be easily used for conversion groups configured to be in the single-conversion mode.
The application program can read out the conversion results, change the group’s configuration if
necessary, and restart the conversions by triggering the group from within the interrupt service routine.
For groups configured to be in continuous conversion mode, this interrupt condition is not practical as the
conversions are always in progress. In this case, the Group Memory Threshold Interrupt is more practical
as the application can allow a programmable number of conversion results to accumulate before
interrupting the CPU.
19.5.2 Group Memory Threshold Interrupt
The ADC module has the ability to generate an interrupt for a fixed number of conversions for each group.
A group memory threshold register determines how many conversion results must be in a group’s memory
region before the CPU is interrupted. This feature can be used to significantly reduce the CPU load when
using interrupts for reading the conversion results.
The group’s threshold register needs to be configured before the group conversions are triggered. This
threshold register value behaves like a down-counter, which decrements each time the ADC writes a
conversion result to this group’s memory. This counter is incremented each time the application program
reads a conversion result from the results’ memory by accessing the FIFO queue. Simultaneous read (by
application program) and write (by ADC module) operations from the group’s results’ memory leave the
threshold counter unchanged.
The threshold counter can decrement past 0 and become negative. It always increments back to its
original value when the memory region is emptied. To determine how many samples are in the memory
region at a given moment, the threshold counter can be subtracted from the originally configured threshold
count.
Whenever the threshold counter transitions from +1 to 0, it sets the group’s threshold interrupt flag, and
the CPU is interrupted if the group’s threshold interrupt is enabled. The CPU is expected to clear the
interrupt flag after reading the conversion results from the memory.
The interrupt flag is not set when the threshold counter stays at 0 or transitions from -1 to 0.
19.5.3 Group Memory Overrun Interrupt
An interrupt can be generated for each group if the number of ADC conversions for that group exceed the
number of buffers allocated for that conversion group. The application program can choose to read out all
the conversion results using the CPU or the DMA. Alternatively, the application program can set the
group’s OVR_RAM_IGN bit and allow the ADC module to overwrite the group’s results’ memory contents
with new conversion results.
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19.6 ADC Module DMA Requests
This section describes the capabilities of the ADC module to take advantage of the Platform DMA
controller module. The ADC module can generate a DMA request under two conditions:
19.6.1 DMA Request for Each Conversion Result Written to the Results’ Memory
In this mode, the ADC module will generate the first DMA request as soon as a conversion result gets
written to the group’s results’ memory. Subsequent writes to the results’ memory will cause DMA requests
to be generated. This mode allows a smaller amount of ADC results’ memory to suffice for an application.
This DMA request generation is enabled by setting the group’s DMA_EN bit in the group’s DMA control
register. The BLK_XFER bit in this register must be left cleared (default) if a DMA request is desired to be
generated for new results getting written to the results’ memory.
19.6.2 DMA Request for a Fixed Number of Conversion Results
This mode is enabled by setting both the group’s DMA_EN and the group’s BLK_XFER bits in the group’s
DMA control registers.
In this mode, a DMA request will be generated for a specified number of conversion results being
available in the group’s results’ memory. The number of conversion results desired are configured using
the group’s BLOCKS field in the control registers.
For example, if the BLOCK count is configured for 10, then ADC module will generate a DMA request at
the end of 10th conversion. DMA controller should complete reading out 10 data before next set of 10
conversions complete.
NOTE: Usage of Block DMA transfers with Threshold Interrupts
It is not recommended to enable the block DMA transfers for a group at the same time as the
group threshold interrupt. The group’s BLOCKS field is essentially the same as the group’s
THRESHOLD field in the group’s interrupt control register described in Section 19.5.2.
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19.7 ADC Magnitude Threshold Interrupts
The ADC allows up to three magnitude threshold interrupts to be generated. The comparison parameters
are programmed via the Magnitude Compare Interrupt x Control Register (ADMAGINTxCR).
19.7.1 Magnitude Threshold Interrupt Configuration
The following fields are configurable for each of the three available magnitude threshold interrupts:
1. CHN_THR_COMP: Specifies whether to compare two channels’ conversion results, or to compare a
channel’s conversion result to a programmable threshold value. A value of 0 will select the
programmable threshold to be compared, and a value of 1 will select the conversion result of the
channel identified by the COMP_CHID field to be compared.
2. MAG_CHID: Specifies the channel number from 0 to 23 whose conversion result needs to be
monitored.
3. COMP_CHID: Specifies the channel number from 0 to 23 whose last conversion result is used for the
comparison with the conversion result of the channel being monitored.
4. MAG_THR: Specifies the value for comparison with the conversion result of the channel identified by
the MAG_CHID field.
5. CMP_GE_LT: Specifies whether the conversion result of the channel identified by MAG_CHID is
compared to be “greater than or equal to”, or “less than” the reference value. The reference value can
be the conversion result of another channel identified by the COMP_CHID field, or it could be a
threshold value specified in the MAG_THR field. A value of 0 in the CMP_GE_LT field indicates a “less
than” comparison and a value of 1 indicates a “greater than or equal to” comparison.
19.7.2 Magnitude Threshold Interrupt Comparison Mask Configuration
There is also a separate comparison mask register (ADMAGINTxMASK) for each of the three magnitude
threshold interrupts. This register is used to specify the bits that are masked off for the sake of the
comparison. For example, the lower 4 bits of the conversion result can be masked off by writing 0xF to the
interrupt comparison mask register, allowing a gross comparison to be made. By default, the full 10/12-bit
conversion results are compared.
19.7.3 Magnitude Threshold Interrupt Enable / Disable Control
Each of the three magnitude interrupts also have separate interrupt enable set (ADMAGINTENASET) and
clear (ADMAGINTENACLR) registers. These are used to respectively enable and disable that particular
magnitude threshold interrupt from being generated. To enable a magnitude threshold interrupt, write a 1
to the corresponding bit of the interrupt enable set register. Conversely, to disable a magnitude threshold
interrupt, write a 1 to the corresponding bit of the interrupt enable clear register.
19.7.4 Magnitude Threshold Interrupt Flags
There is a separate Magnitude Interrupt Flag register (ADMAGINTFLG) that holds the flags for these three
interrupts. This flag gets set whenever the comparison condition for the corresponding interrupt is met. A
magnitude threshold interrupt is generated if the corresponding flag is set inside the flag register, and the
interrupt generation is enabled. This flag can be cleared by writing a 1 to the flag or by reading from the
interrupt offset register in case of this interrupt being the current highest-priority pending interrupt.
19.7.5 Magnitude Threshold Interrupt Offset Register
It is possible to have multiple magnitude threshold interrupts pending at the same time. The magnitude
threshold interrupt offset register (ADMAGINTOFF) holds the index of the currently pending highest
priority magnitude threshold interrupt. The magnitude threshold interrupt 1 has the highest priority while
the magnitude threshold interrupt 3 has the lowest priority. This is a read-only register and returns zeros if
none of the magnitude threshold interrupts are pending. Writes to this register have no effect.
A read from this register updates the register to the next highest-priority pending magnitude threshold
interrupt. This read also clears the corresponding flag from the magnitude threshold interrupt flag register.
However, a read from the magnitude threshold interrupt offset register in emulation mode does not affect
the interrupt flag register or the interrupt offset register.
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19.8 ADC Special Modes
The ADC module supports some special modes for diagnostics and power saving purposes.
19.8.1 ADC Error Calibration Mode
The application program can activate a calibration sequence any time self-test mode is disabled
(SELF_TEST = 0). This calibration sequence includes the conversion of an embedded calibration
reference voltage followed by the calculation of an offset error correction value.
NOTE: Disable Self-Test Mode Before Calibration
To avoid errors during the calibration operation, self-test mode must not be enabled during a
calibration sequence. In addition, to ensure accurate results, calibrate the ADC in an
environment with minimum noise.
Calibration mode is enabled by setting the CAL_EN bit (ADCALCR.0). The application needs to ensure
that no conversion group is being serviced when the calibration mode is enabled.
The input multiplexor gets disabled and only the reference voltage is connected to the ADC core input.
Switch S5 of Figure 19-11 is opened. In addition, the digital result issued from a conversion is output from
the ADC core to the calibration and offset error correction register, ADCALR. The ADC results’ memory is
not affected by the calibration conversion.
When calibration mode is disabled, the ADC can be configured for normal conversions.
Figure 19-11. Self-Test and Calibration Logic
ADREFHI
ADREFLO
Self-test and
calibration
R1 ~ 5K
R2 ~ 7K
S3 S4
S1 S2
R2
R1
ADIN0
MUX
Vin
ADC Core
S5
ADIN31
CALR
ADCALR.9:0
ADDRx.16,9:0
19.8.1.1 Calibration Conversion
The calibration conversion also needs to meet the minimum sampling time specification for the ADC. This
value is typically 1 us. The Event Group sample time register (ADEVSAMP) is used to specify the number
of ADCLK cycles for the calibration conversion.
The BRIDGE_EN and HILO bits (ADCALCR.9:8) control the voltage to the calibration reference device
shown in Figure 19-13. The positions of the switches in calibration mode are listed in Table 19-1.
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Table 19-1. Calibration Reference Voltages
(1)
CAL_EN
BRIDGE_EN
HILO
S1
S2
S3
S4
S5
Reference Voltage
1
0
0
1
0
1
0
0
(ADREFHI × R1 + ADREFLO × R2) / (R1 + R2)
1
0
1
0
1
0
1
0
(ADREFLO × R1 + ADREFHI × R2) / (R1 + R2)
1
1
0
0
1
1
0
0
ADREFLO
1
1
1
1
0
0
1
0
ADREFHI
0
X
X
0
0
0
0
1
Vin
(1)
The state of the switches in this table assumes that self-test mode is not enabled.
When CAL_ST (ADCALCR.16) is set, a calibration conversion is started. The voltage source selected via
the bits BRIDGE_EN and HILO is converted once (single conversion mode) and the digital result is
returned to the calibration and correction register, ADCALR, where it can be read by the CPU. The
CAL_ST bit acts as a flag and must be polled by the CPU. It is held set during the conversion process and
automatically clears to indicate the end of the reference voltage conversion.
NOTE: No Interrupt for end of calibration
The ADC does not generate an interrupt to signal the end of the calibration conversion. The
application must poll the CAL_ST bit to determine the end of the calibration conversion.
After the CAL_ST bit is set by the application program, it can only be reset by the end of the ongoing
conversion generated by the ADC core. If the calibration conversion is interrupted (CAL_EN bit is cleared),
the CAL_ST bit is held at 1 until a new calibration conversion has been set and completed. Setting the
CAL_ST bit while calibration is disabled (CAL_EN = 0) has no effect; however, in this situation, setting
CAL_EN immediately starts a calibration conversion. When the calibration conversion is interrupted by an
ADC enable (ADC_EN = 0, CAL_EN = 1, and CAL_ST = 1), a new conversion is automatically restarted
as soon as the ADC enable bit is released (ADC_EN = 1).
19.8.1.2 Calibration and Offset Error Correction Sequences
The number of measurements and the source to measure for an ADC calibration are application
dependent. The CAL_ST bit must be set for each calibration source to be measured. While calibration
mode is enabled, any available calibration sources can be converted according to the BRIDGE_EN and
HILO bits (see Table 19-1). The digital results of the calibration measurements should be read from
ADCALR by the application after each reference conversion so that a correction value can be computed
and written back into ADCALR.
When the application has the necessary calibration data, it should compute the offset error correction
value and load it into the calibration and correction register, ADCALR. After the CAL_EN bit is cleared,
normal conversion mode restarts, continuing from where it was frozen, but with the addition of selfcorrection data.
In normal mode, the self-correction system adds the correction value stored in ADCALR to each digital
result before it is written to the respective group’s FIFO.
The basic calibration routine is as follows:
1. Enable calibration via CAL_EN (ADCALCR.0).
2. Select the voltage source via BRIDGE_EN and HILO (ADCALCR.9:8).
3. Start the conversion with CAL_ST (ADCALCR.16).
4. Wait for CAL_ST to go to 0.
5. Get the results from ADCALR and save to memory.
6. Loop to step 2 until the calibration conversion data is collected for the desired reference voltages.
7. Compute the error correction value using calibration data saved in memory.
8. Load the ADCALR register with the 2s complement of the computed error correction value.
9. Disable calibration mode.
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At this point, the ADC can be configured for normal operation, and it corrects each digital result with the
error correction value loaded in ADCALR.
NOTE: Prevent ADC Calibration Data From Being Overwritten
In calibration mode, the conversion result is written to ADCALR which overwrites any
previous calibration data; therefore, the ADCALR register must be read before a new
conversion is started.
For no correction, a value of 0x0000 must be written to ADCALR. In noncalibration mode, the ADCALR
register can be read and written. Any value written to ADCALR in normal mode (CAL_EN = 0) is added to
each digital result from the ADC core.
19.8.1.3 Mid-Point Calibration
Because of its connections to the ADC’s reference voltage (VrefHi, VrefLo), the precision of the calibration
reference is voltage independent. On the other hand, the accuracy of the switched bridge resistor (R1 and
R2) relies on the manufacturing process deviation. Consequently, the mid-point voltage’s accuracy can be
affected due to the imperfections in the two resistors (expected mismatch error is around 1.5%).
The switched reference voltage device has been specially designed to support a differential measurement
of its mid-point voltage. This ensures the accuracy of the mid-point reference, and hence the efficiency of
the calibration.
The differential mid-point calibration is software controlled; the algorithm (voltage source measurements
and associated calculation) is inserted within the calibration software module included in the application
program.
The basic differential mid-point calibration flow is illustrated here after:
1. The application program connects the voltage VrefHi to R1 and VrefLo to R2, (BRIDGE_EN = 0,
HILO = 0), launches a conversion of the input voltage V(cal1), and stores the digital result D(cal1) into
the memory.
2. Then the application program switches the voltage VrefHi to R2 and VrefLo to R1 (BRIDGE_EN = 0,
HILO = 1), converts this new input voltage V(cal2) and again stores the issued digital result D(cal2)
into the memory.
3. The actual value of the real middle point is obtained by computing the average of these two results.
[D(cal1)+D(cal2)] /2; Figure 19-12 summarizes the mid-point calibration flow.
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Figure 19-12. Mid-point Value Calculation
Digital Code (hex)
FS
3FF
* The Real function shown is a straight
line between the ends points of the real
staircase characteristic.
10-bit ADC’s Theoretical
Transfer Function
The Theoretical transfer function is
for reference only.
*Real
straight line
Transfer Function
D(cal2)
D(cal)
R
D(cal1)
Vin
VrefLo
V(cal1)
V(cal2)
VrefHi
(VrefHi - VrefLo)/2
MEMORY
V(cal1) = [VREFHI*R1+VREFLO*R2] / (R1 + R2)
D(cal1)
V(cal2) = [VREFLO*R1+VREFHI*R2] / (R1 + R2)
D(cal2)
CPU
[V(cal1) + V(cal2)] / 2 = (VrefHi-VrefLo) / 2
716
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19.8.2 ADC Self-Test Mode
The ADC module supports a self-test mode which can be used to detect an open or a short on the ADC
input channels. Self-test mode is enabled by setting the SELF_TEST bit (ADCALCR.24). Any conversion
type (continuous or single conversion, freeze enabled or non-freeze enabled, interrupts enabled or
disabled) can be performed in this mode.
In normal mode, setting the self-test mode while a conversion sequence is in process can corrupt the
current channel conversion results. However, the next channel in the sequence is converted correctly
during the additional self-test cycle. The logic associated with both self-test and calibration is shown in
Figure 19-13.
Figure 19-13. Self-Test and Calibration Logic
ADREFHI
ADREFLO
Self-test and
calibration
R1 ~ 5K
R2 ~ 7K
S3 S4
S1 S2
R2
R1
ADIN0
MUX
Vin
ADC Core
S5
ADIN31
CALR
ADCALR.9:0
ADDRx.16,9:0
In self-test mode, a test voltage defined by the HILO bit (ADCALCR.8) is provided to the ADC core input
through a resistor (see Table 19-2). To change the test source, this bit can be toggled before any single
conversion mode request. Changing this bit while a conversion is in progress can corrupt the results if the
source switches during the acquisition period.
Please note that the switch S5 shown in Figure 19-13 is only for the purpose of explaining the self-test
sequence. There is no physical switch.
Table 19-2. Self-Test Reference Voltages (1)
(1)
SELF_TEST
HILO
S1
S2
S3
S4
S5
Reference Voltage
1
0
0
1
1
0
1
ADREFLO via R1 || R2 connected to Vin
1
1
1
0
0
1
1
ADREFHI via R1 || R2 connected to Vin
0
X
0
0
0
0
1
Vin
Switches refer to Figure 19-13.
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Conversions in self-test mode are started just as they are in the normal operating mode (see
Section 19.3.6). The conversion starts according to the configuration set in the three mode control
registers (ADEVMODECR, ADG1MODECR, ADG2MODECR) and the sampling time control registers
(ADEVSAMP, ADG1SAMP, ADG2SAMP). The acquisition time for each conversion in self-test mode is
extended to twice the normal configured acquisition time. The selected reference voltage and the input
voltage from the ADINx input channel are both connected to the ADC internal sampling capacitor
throughout this extended acquisition period. Figure 19-14 shows the self-test mode timing when the
ADREFLO is chosen as the reference voltage for the self-test mode conversion. It also assumes an
external capacitor connected to the ADC input channel.
Figure 19-14. Timing for Self-Test Mode
Sample time doubled in self-test mode
Sample time in normal operation mode
Tsamp1
ADREFLO + ADINx
Tsamp2
ADREFLO + ADINx
Conversion of last value sampled
Start
ADREFHI
Ext. Input
AD_Core _In
discharge of ext. cap
charging of ext. cap
ADREFLO
time
19.8.2.1 Use of Self-Test Mode to Determine Open/Short on ADC Input Channels
The following sequence needs to be used to deduce the ADC pin status:
• Convert the channel with self test enabled and with the reference voltage as Vreflo. Store the
conversion result, say Vd.
• Convert the channel with self test enabled and with the reference voltage as Vrefhi. Store the
conversion result, say Vu.
• Convert the channel with self test disabled. Store the conversion result, say Vn.
The results can be interpreted using Table 19-3.
Table 19-3. Determination of ADC Input Channel Condition
718
Normal Conversion
Result, Vn
Self-test Conversion
Result, Vu
Self-test Conversion
Result, Vd
Pin Condition
Vn
Vn < Vu < ADREFHI
ADREFLO < Vd < Vn
Good
ADREFHI
ADREFHI
approx. ADREFHI
Shorted to ADREFHI
ADREFLO
approx. ADREFLO
ADREFLO
Shorted to ADREFLO
Unknown
ADREFHI
ADREFLO
Open
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19.8.3 ADC Power-Down Mode
This is an inactive mode in which the clocks to the ADC module are stopped leaving the module in a static
state. The clock to the ADC core (ADCLK) is stopped whenever there are no ongoing conversions. This is
the clock-gating implementation requirement. Also, the ADC module places the ADC core into the power
down mode such that there is minimal current drawn from the ADC operating and reference supplies.
19.8.3.1 Powering Down Just The ADC Core
The ADC core can be individually powered down without stopping the clocks to the ADC module. This can
be done by setting the POWERDOWN bit of the ADC Operating Mode Control Register
(ADOPMODECR.3). Whenever a conversion is required the POWERDOWN bit must be cleared, and a
minimum time td(PU-ADV), (see the specific device data sheet for actual value) has to be allowed before
starting a new conversion. This wait must be implemented in the application software.
19.8.3.2 Enhanced Power-Down Mode
A bit in the ADC operating mode control register, IDLE_PWRDN (ADOPMODECR.4) enables the
enhanced power-down mode of the ADC.
Once this bit is set, the ADC module will power down the ADC core whenever there are no more ongoing
or pending ADC conversions. The ADC core will be powered down regardless of the state of the
POWERDOWN bit (ADOPMODECR.3).
The ADC module releases the ADC core from power down mode as soon as a new conversion is
requested. The ADC logic state machine then has to wait for at least td(PU-ADV) (see the device data sheet
for actual value) before starting a new conversion. The IDLE_PWRDN bit will remain set at all times. The
logic state machine can use this bit to determine that it needs to wait for a programmable number of VCLK
cycles before it allows the input channel to be sampled. This time is configured by the ADC Power Up
Delay Control register (ADPWRUPDLYCTRL).
If IDLE_PWRDN is not set, the ADC module does not wait for any additional delay before sampling the
input channel and the application software has to take account of this required delay.
19.8.3.3 Managing Clocks to the ADC Module
The clock to the ADC module can be turned off via the appropriate Peripheral Central Resource (PCR)
controller PSPWRDNSET register (check the specific device datasheet to identify the register and the bit
to be set). If a conversion is ongoing when this bit is set, the ADC module will wait until the current
conversion completes before allowing the ADC module clock to be stopped.
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19.8.4 ADC Sample Capacitor Discharge Mode
This mode allows the charge on the ADC core’s internal sampling capacitor to be discharged before
starting the sampling phase of the next channel.
The ADC Sample Cap Discharge Mode is enabled by setting the SAMP_DIS_EN bit of the group’s
ADSAMPDISEN register. A discharge period for the sampling capacitor is added before the sampling
period for each channel as shown in Figure 19-15. The duration of this discharge period is configurable via
the corresponding group’s SAMP_DIS_CYC field in the ADSAMPDISEN register. The discharge time is
specified in terms of number of ADCLK cycles.
During the sample capacitor discharge period, the VREFLO reference voltage is connected to the input
voltage terminal of the ADC core. This allows any charge collected on the sampling capacitor from the
previous conversion to be discharged to ground. The VREFLO reference voltage is usually connected to
ground.
Figure 19-15. Timing for Sample Capacitor Discharge Mode
Sample cap discharge time
Tdischarge
Vreflo
Sampling time
Tsamp
ADINx
Conversion of last value sampled
Start
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19.9 ADC Results’ RAM Special Features
The following sections describe some of the special features supported by the ADC module to enhance
the results’ RAM testability and integrity.
19.9.1 ADC Results’ RAM Auto-Initialization
The ADC module allows the application to auto-initialize the ADC results’ RAM to all zeros. The
application must ensure that the ADC module is not in any of the conversion modes before triggering off
the auto-initialization process.
The auto-initialization sequence is as follows:
1. Enable the global hardware memory initialization key by programming a value of Ah to the bits [3-0] of
the MINITGCR register of the System module.
2. Set the control bit for the ADC results’ RAM in the MSINENA System module register. The bit 8 of the
MSINENA register is used to control the initialization of the ADC1 results’ RAM, while bit 14 controls
the initialization of the ADC2 results’ RAM. This starts the initialization process. The
BUF_INIT_ACTIVE flag in the ADBNDEND register will get set to reflect that the initialization is
ongoing.
3. When the memory initialization is completed, the corresponding status bit in the MINISTAT register will
be set. Also, the BUF_INIT_ACTIVE flag will get cleared.
19.9.2 ADC Results’ RAM Test Mode
In the defined conversion modes of the ADC, the application can only read from the ADC results’ RAM.
Only the ADC module is allowed to write to the results’ RAM. A special test mode is defined to allow the
application to also write into the ADC results’ RAM - this mode is the ADC Results’ RAM Test Mode. Only
32-bit reads and writes are allowed to the ADC results’ RAM in this test mode.
NOTE: Contention on access to ADC Results’ RAM
The ADC module cannot handle a contention between the application write to the results’
RAM and the ADC writing a conversion result to the results’ RAM. The application must
ensure that the ADC is not likely to write a new conversion result to the results’ RAM when
the ADC Results’ RAM Test Mode is enabled.
The ADC Results’ RAM Test Mode is enabled by setting the RAM_TEST_EN bit in the ADOPMODECR.
19.9.3 ADC Results’ RAM Parity
The following shows the ADC Results’ RAM parity control registers.
Parity checking is implemented using parity on a per-half word basis for the ADC RAM. That is, there is
one parity bit for 16 bits of the ADC RAM. The polarity of the ADC RAM parity is controlled by the
DEVCR1 register in the system module (address = FFFF FFDCh). The parity checking is enabled by the
ADPARCR register. After reset, the parity checking is disabled and must be enabled if parity protection is
required.
During a read access, the parity is calculated based on the data read from the ADC RAM and compared
with the good parity value stored in the parity bits. If any word fails the parity check then the ADC
generates an error signal hooked up to the Error Signaling Module (ESM). The ADC RAM address which
generated the parity error is captured for host system debugging, and is frozen from being updated until it
is read by the application.
Testing the Parity Checking Mechanism:
To test the parity checking mechanism itself, the parity RAM is made writable by the CPU in a special test
mode. This is done by a control bit called TEST in the ADPARCR register. Once this bit is set, the parity
bits are mapped to an address starting at an address offset of 4KB from the base address of the ADC
RAM. See Figure 19-16. The CPU can now manually insert parity errors. Note that the ADC RAM only
supports 32-bit accesses.
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Figure 19-16. ADC Memory Map in Parity Test Mode
ADC1
BASE ADDRESS
ADC2
0xFF3E0000 0xFF3A0000
Conversion word 0
0xFF3E0004 0xFF3A0004
Conversion word 1
0xFF3E0008 0xFF3A0008
Conversion word 2
0xFF3E01F8 0xFF3A01F8
Conversion word 62
0xFF3E00FC 0xFF3A00FC
Conversion word 63
Reserved
0xFF3E1000
0xFF3A1000
Parity Bits
19.10 ADEVT Pin General Purpose I/O Functionality
The AD1EVT pin for ADC1 and AD2EVT pin for ADC2 can be configured as general-purpose I/O signals.
The following sections describe the different ways in which the application can configure the ADxEVT
pins.
19.10.1 GPIO Functionality
Figure 19-17 illustrates the GPIO functionality of the ADxEVT pin.
Figure 19-17. GPIO Functionality of ADxEVT
Output enable
ADxEVT
pin
Data out
Data in
Pull control disable
Pull control
logic
Pull select
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Once the device power-on reset is released, the ADC module controls the state of the ADxEVT pin.
• Pull control: The pull control can either be enabled or disabled by default (while system reset is active
and after it is released). The actual default state of the pull control is specified in the device datasheet.
The application can enable pull control by clearing the PDIS (pull control disable) bit in the
ADEVTPDIS register. In this case, if the PSEL (pull select) bit in the ADEVTPSEL register is set, the
pin will have a pull-up. If the PSEL bit is cleared, the pin will have a pull-down. If the PDIS bit is set in
the control register, there is no pull-up or pull-down on the pin.
NOTE: Pull Behavior when ADxEVT is configured as output
If the ADxEVT pin is configured as output, then the pulls are disabled automatically. If the pin
is configured as input, the pulls are enabled or disabled depending on bit PDIS in the pull
disable register ADEVTPDIS.
•
•
Output buffer: The ADxEVT pin can be driven as an output pin if the ADEVTDIR bit is set in the pin
direction control register.
Open-Drain feature: The open drain output capability is enabled via the ADEVTPDR control register.
The ADxEVT pin must be also configured to be an output pin for this mode.
– The output buffer is enabled if a low signal is being driven on to the pin.
– The output buffer is disabled if a high signal is being driven on to the pin.
19.10.2 Summary
The behavior of the output buffer and the pull control is summarized in Table 19-4. The input buffer for the
ADxEVT pins are enabled once the device power-on reset is released.
Table 19-4. Output Buffer and Pull Control Behavior for ADxEVT as GPIO Pins
(1)
(2)
(3)
(4)
System Reset
Active?
Pin Direction
(DIR) (1) (2)
Pull Disable
(PDIS) (1) (3)
Pull Select
(PSEL) (1) (4)
Yes
X
X
No
0
0
No
0
No
No
No
Pull Control
Output Buffer
X
Enabled
Disabled
0
Pull down
Disabled
0
1
Pull up
Disabled
0
1
0
Disabled
Disabled
0
1
1
Disabled
Disabled
1
X
X
Disabled
Enabled
X = Don’t care
DIR = 0 for input, 1 for output
PULDIS = 0 for enabling pull control, 1 for disabling pull control
PULSEL = 0 for pull-down functionality, 1 for pull-up functionality
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19.11 ADC Control Registers
All registers in the ADC module are 32-bit, word-aligned; 8-bit, 16-bit and 32-bit accesses are allowed.
The application must ensure that the reserved bits are always written as 0 to ensure software compatibility
to future revisions of the module. Table 19-5 shows register address offsets from the base address of the
ADC modules. The base address of the ADC1 registers is FFF7 C000h and the base address of the
ADC2 registers is FFF7 C200h.
Table 19-5. ADC Registers
Offset
Acronym
Register Description
00h
ADRSTCR
ADC Reset Control Register
Section 19.11.1
Section
04h
ADOPMODECR
ADC Operating Mode Control Register
Section 19.11.2
08h
ADCLOCKCR
ADC Clock Control Register
Section 19.11.3
0Ch
ADCALCR
ADC Calibration Mode Control Register
Section 19.11.4
10h
ADEVMODECR
ADC Event Group Operating Mode Control Register
Section 19.11.5
14h
ADG1MODECR
ADC Group1 Operating Mode Control Register
Section 19.11.6
18h
ADG2MODECR
ADC Group2 Operating Mode Control Register
Section 19.11.7
1Ch
ADEVSRC
ADC Trigger Source Select Register
Section 19.11.8
20h
ADG1SRC
ADC Group1 Trigger Source Select Register
Section 19.11.9
24h
ADG2SRC
ADC Group2 Trigger Source Select Register
Section 19.11.10
28h
ADEVINTENA
ADC Event Interrupt Enable Control Register
Section 19.11.11
2Ch
ADG1INTENA
ADC Group1 Interrupt Enable Control Register
Section 19.11.12
30h
ADG2INTENA
ADC Group2 Interrupt Enable Control Register
Section 19.11.13
34h
ADEVINTFLG
ADC Event Group Interrupt Flag Register
Section 19.11.14
38h
ADG1INTFLG
ADC Group1 Interrupt Flag Register
Section 19.11.15
3Ch
ADG2INTFLG
ADC Group2 Interrupt Flag Register
Section 19.11.16
40h
ADEVTHRINTCR
ADC Event Group Threshold Interrupt Control Register
Section 19.11.17
44h
ADG1THRINTCR
ADC Group1 Threshold Interrupt Control Register
Section 19.11.18
48h
ADG2THRINTCR
ADC Group2 Threshold Interrupt Control Register
Section 19.11.19
4Ch
ADEVDMACR
ADC Event Group DMA Control Register
Section 19.11.20
50h
ADG1DMACR
ADC Group1 DMA Control Register
Section 19.11.21
54h
ADG2DMACR
ADC Group2 DMA Control Register
Section 19.11.22
58h
ADBNDCR
ADC Results Memory Configuration Register
Section 19.11.23
5Ch
ADBNDEND
ADC Results Memory Size Configuration Register
Section 19.11.24
60h
ADEVSAMP
ADC Event Group Sampling Time Configuration Register
Section 19.11.25
64h
ADG1SAMP
ADC Group1 Sampling Time Configuration Register()
Section 19.11.26
68h
ADG2SAMP
ADC Group2 Sampling Time Configuration Register
Section 19.11.27
6Ch
ADEVSR
ADC Event Group Status Register
Section 19.11.28
70h
ADG1SR
ADC Group1 Status Register
Section 19.11.29
74h
ADG2SR
ADC Group2 Status Register
Section 19.11.30
78h
ADEVSEL
ADC Event Group Channel Select Register
Section 19.11.31
7Ch
ADG1SEL
ADC Group1 Channel Select Register
Section 19.11.32
80h
ADG2SEL
ADC Group2 Channel Select Register
Section 19.11.33
84h
ADCALR
ADC Calibration and Error Offset Correction Register
Section 19.11.34
88h
ADSMSTATE
ADC State Machine Status Register
Section 19.11.35
8Ch
ADLASTCONV
ADC Channel Last Conversion Value Register
Section 19.11.36
90h-AFh
ADEVBUFFER
ADC Event Group Results FIFO Register
Section 19.11.37
B0h-CFh
ADG1BUFFER
ADC Group1 Results FIFO Register
Section 19.11.38
D0h-EFh
ADG2BUFFER
ADC Group2 Results FIFO Register
Section 19.11.39
F0h
ADEVEMUBUFFER
ADC Event Group Results Emulation FIFO Register
Section 19.11.40
F4h
ADG1EMUBUFFER
ADC Group1 Results Emulation FIFO Register
Section 19.11.41
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Table 19-5. ADC Registers (continued)
Offset
Acronym
Register Description
F8h
ADG2EMUBUFFER
ADC Group2 Results Emulation FIFO Register
Section 19.11.42
Section
FCh
ADEVTDIR
ADC ADEVT Pin Direction Control Register
Section 19.11.43
100h
ADEVTOUT
ADC ADEVT Pin Output Value Control Register
Section 19.11.44
104h
ADEVTIN
ADC ADEVT Pin Input Value Register
Section 19.11.45
108h
ADEVTSET
ADC ADEVT Pin Set Register
Section 19.11.46
10Ch
ADEVTCLR
ADC ADEVT Pin Clear Register
Section 19.11.47
110h
ADEVTPDR
ADC ADEVT Pin Open Drain Enable Register
Section 19.11.48
114h
ADEVTPDIS
ADC ADEVT Pin Pull Control Disable Register
Section 19.11.49
118h
ADEVTPSEL
ADC ADEVT Pin Pull Control Select Register
Section 19.11.50
11Ch
ADEVSAMPDISEN
ADC Event Group Sample Cap Discharge Control Register
Section 19.11.51
120h
ADG1SAMPDISEN
ADC Group1 Sample Cap Discharge Control Register
Section 19.11.52
124h
ADG2SAMPDISEN
ADC Group2 Sample Cap Discharge Control Register
Section 19.11.53
128h-138h
ADMAGINTxCR
ADC Magnitude Compare Interrupt x Control Register
Section 19.11.54
12Ch-13Ch
ADMAGxMASK
ADC Magnitude Compare Interrupt x Mask Register
Section 19.11.55
158h
ADMAGINTENASET
ADC Magnitude Compare Interrupt Enable Set Register
Section 19.11.56
15Ch
ADMAGINTENACLR
ADC Magnitude Compare Interrupt Enable Clear Register
Section 19.11.57
160h
ADMAGINTFLG
ADC Magnitude Compare Interrupt Flag Register
Section 19.11.58
164h
ADMAGINTOFF
ADC Magnitude Compare Interrupt Offset Register
Section 19.11.59
168h
ADEVFIFORESETCR
ADC Event Group FIFO Reset Control Register
Section 19.11.60
16Ch
ADG1FIFORESETCR
ADC Group1 FIFO Reset Control Register
Section 19.11.61
170h
ADG2FIFORESETCR
ADC Group2 FIFO Reset Control Register
Section 19.11.62
174h
ADEVRAMWRADDR
ADC Event Group RAM Write Address Register
Section 19.11.63
178h
ADG1RAMWRADDR
ADC Group1 RAM Write Address Register
Section 19.11.64
17Ch
ADG2RAMWRADDR
ADC Group2 RAM Write Address Register
Section 19.11.65
180h
ADPARCR
ADC Parity Control Register
Section 19.11.66
184h
ADPARADDR
ADC Parity Error Address Register
Section 19.11.67
188h
ADPWRUPDLYCTRL
ADC Power-Up Delay Control Register
Section 19.11.68
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19.11.1 ADC Reset Control Register (ADRSTCR)
Figure 19-18 and Table 19-6 describe the ADRSTCR register.
Figure 19-18. ADC Reset Control Register (ADRSTCR) [offset = 00h]
31
1
0
Reserved
RESET
R-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 19-6. ADC Reset Control Register (ADRSTCR) Field Descriptions
Bit
Field
31-1
Value
Reserved
0
0
RESET
Description
Reads return zeros, writes have no effect.
This bit is used to reset the ADC internal state machines and control/status registers. This reset
state is held until this bit is cleared. Read in all modes, write in privileged mode.
0
Module is released from the reset state.
1
All the module's internal state machines and the control/status registers are reset.
19.11.2 ADC Operating Mode Control Register (ADOPMODECR)
Figure 19-19 and Table 19-7 describe the ADOPMODECR register.
Figure 19-19. ADC Operating Mode Control Register (ADOPMODECR) [offset = 04h]
31
30
25
24
10_12_BIT
Reserved
COS
R/W-0
R-0
RW-0
23
21
20
17
16
Reserved
CHN_TEST_EN
RAM_TEST_
EN
R-0
R/W-Ah
R/W-0
15
9
7
8
Reserved
POWERDOWN
R-0
RW-0
5
4
3
1
0
Reserved
IDLE_PWRDN
Reserved
ADC_EN
R-0
R/W-0
R-0
RW-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-7. ADC Operating Mode Control Register (ADOPMODECR) Field Descriptions
Bit
Field
31
10_12_BIT
Value
Description
This bit controls the resolution of the ADC core. It also affects the size of the conversion
results stored in the results’ RAM.
Any operation mode read/write:
30-25
726
Reserved
0
The ADC core and digital logic are configured to be in 10-bit resolution. This is the default
mode of operation.
1
The ADC core and digital logic are configured to be in 12-bit resolution.
0
Read returns 0. Writes have no effect.
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Table 19-7. ADC Operating Mode Control Register (ADOPMODECR) Field Descriptions (continued)
Bit
Field
24
COS
Value
Description
This bit affects emulation operation only. It defines whether the ADC core clock (ADCLK) is
immediately halted when the emulation system enters suspend mode or if it should continue
operating normally.
Note: If COS = 0 when the ADC module enters the emulation mode, then the accuracy of
the conversion results can be affected depending on how long the module stays in the
emulation mode.
Any operation mode read/write:
23-21
Reserved
20-17
CHN_TEST_EN
0
ADC module halts all ongoing conversions immediately after emulation mode is entered.
1
ADC module continues all ongoing conversions as per the configurations of the three
conversion groups.
0
Read returns 0. Writes have no effect.
Enable the input channels’ impedance measurement mode.
This mode is reserved for use by TI.
Any operation mode read/write:
16
5h
Input impedance measurement mode is enabled.
Ah
Input impedance measurement mode is disabled.
other
Input impedance measurement mode is disabled.
RAM_TEST_EN
Enable the ADC Results’ RAM Test Mode.
Please refer to Section 19.9.2 for more details.
Any operation mode read/write:
15-9
8
Reserved
0
ADC RAM Test Mode is disabled. The application cannot write to the ADC RAM by the CPU
or the DMA.
1
ADC RAM Test Mode is enabled. The application can directly write to the ADC RAM by the
CPU or the DMA.
0
Read returns 0. Writes have no effect.
POWERDOWN
ADC Power Down. This bit powers down only the ADC core; the digital logic in the
sequencer stays active. To release the core from power down mode, this bit must be
cleared. If a conversion is ongoing, the ADC module will wait until the current conversion is
completed before powering down the ADC core.
Also refer to Section 19.11.68, ADC Power-Up Delay Control Register
(ADPWRUPDLYCTRL).
Any operation mode read/write:
7-5
4
Reserved
0
The state of the ADC core is controlled by the IDLE_PWRDN bit, or by a global power down
mode entry.
1
ADC core is in the power-down state.
0
Read returns 0. Writes have no effect.
IDLE_PWRDN
ADC Power Down When Idle. When this bit is set, the ADC module will automatically power
down the ADC core whenever there are no conversions ongoing or pending. This is the
enhanced power down mode.
Also refer to Section 19.11.68, ADC Power-Up Delay Control Register
(ADPWRUPDLYCTRL).
Any operation mode read/write:
3-1
Reserved
0
ADC_EN
0
The ADC stays in the normal operating mode even if no conversions are ongoing or
pending. The power down state is entered only by configuring the POWERDOWN bit or via
a global power down mode entry.
1
Enhanced power down mode is enabled.
0
Read returns 0. Writes have no effect.
ADC Enable. This bit must be set to allow the ADC module to be configured to perform any
conversions.
Any operation mode read/write:
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0
No ADC conversions can occur. The input channel select registers: ADEVSEL, ADG1SEL,
and ADG2SEL are held at their reset values.
1
ADC conversions can now proceed as configured.
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19.11.3 ADC Clock Control Register (ADCLOCKCR)
Figure 19-20 and Table 19-8 describe the ADCLOCKCR register.
Figure 19-20. ADC Clock Control Register (ADCLOCKCR) [offset = 08h]
31
5
4
0
Reserved
PS
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-8. ADC Clock Control Register (ADCLOCKCR) Field Descriptions
Bit
Field
Value
31-5
Reserved
4-0
PS
0
0-1Fh
Description
Reads return zeros, writes have no effect.
ADC Clock Prescaler. These bits define the prescaler value for the ADC core clock (ADCLK). The
ADCLK is generated by dividing down the input bus clock (VCLK) to the ADC module.
Note: The supported range for the ADC clock frequency is specified in the device datasheet. The
ADC clock prescaler must be configured to meet this datasheet specification.
Any operation mode read/write:
t C(ADCLK) = t C(VCLK) × (PS[4:0] + 1),
where tC(ADCLK) is the period of the ADCLK, and t C(VCLK) is the period of the VCLK.
19.11.4 ADC Calibration Mode Control Register (ADCALCR)
Figure 19-21 and Table 19-9 describe the ADCALCR register.
Figure 19-21. ADC Calibration Mode Control Register (ADCALCR) [offset = 0Ch]
31
25
24
Reserved
SELF_TEST
R-0
RW-0
23
17
16
Reserved
CAL_ST
R-0
R/S-0
15
9
8
Reserved
10
BRIDGE_EN
HILO
R-0
RW-0
RW-0
7
1
0
Reserved
CAL_EN
R-0
RW-0
LEGEND: R/W = Read/Write; R = Read only; S = Set; -n = value after reset
Table 19-9. ADC Calibration Mode Control Register (ADCALCR) Field Descriptions
Bit
Field
31-25
24
Reserved
Value
0
SELF_TEST
Description
Read returns 0. Writes have no effect.
ADC Self Test Enable. When this bit is Set, either ADREFHI or ADREFLO is connected through a
resistor to the selected input channel. The desired conversion mode is configured in the group
mode control registers. For more details on the ADC Self Test Mode, please refer to
Section 19.8.2.
Any operation mode read/write:
728
0
ADC Self Test mode is disabled.
1
ADC Self Test mode is enabled.
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Table 19-9. ADC Calibration Mode Control Register (ADCALCR) Field Descriptions (continued)
Bit
Field
23-17
Reserved
16
CAL_ST
Value
0
Description
Read returns 0. Writes have no effect.
ADC Calibration Conversion Start. Setting the CAL_ST bit while the CAL_EN bit is set starts
conversion of the selected reference voltage. The ADC module uses the sample time configured in
the Event Group sample time configuration register (ADEVSAMP) for the calibration conversion.
Any operation mode:
1
Read: Calibration conversion is in progress.
Write: ADC module starts calibration conversion.
0
Read: Calibration conversion has completed, or has not yet been started.
Write: Writing 0 to this bit has no effect.
15-10
Reserved
0
Read returns 0. Writes have no effect.
9
BRIDGE_EN
Bridge Enable. When set with the HILO bit, BRIDGE_EN allows a reference voltage to be
converted in calibration mode. Table 19-1 defines the four different reference voltages that can be
selected.
8
HILO
ADC Self Test mode and Calibration Mode Reference Source Selection.
In the ADC Self Test mode, this bit defines the test voltage to be combined through a resistor with
the selected input pin voltage. Refer to Section 19.8.2 for details on the ADC Self Test Mode.
In the ADC Calibration Mode, this bit defines the reference source polarity. Refer to Section 19.8.1
for details on the ADC Calibration Mode.
In the ADC module’s normal operating mode, this bit has no effect.
7-1
Reserved
0
CAL_EN
0
Read returns 0. Writes have no effect.
ADC Calibration Enable. When this bit is Set, the input channel multiplexor is disconnected and the
calibration reference voltage is connected to the ADC core input. The calibration reference voltage
is selected by the combination of the BRIDGE_EN and HILO. The actual conversion of this
reference voltage starts when the CAL_ST bit is set. If the CAL_ST bit is already set when the
CAL_EN bit is set, then the calibration conversion is immediately started.
Please refer to Section 19.8.1 for more details on the ADC calibration mode.
Any operation mode read/write:
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0
Calibration mode is disabled.
1
Calibration mode is enabled.
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19.11.5 ADC Event Group Operating Mode Control Register (ADEVMODECR)
ADC Event Group Operating Mode Control Register (ADEVMODECR) is shown in Figure 19-22 and
Figure 19-23, and described in Table 19-10. As shown, the format of the ADEVMODECR is different
based on whether the ADC module is configured to be a 12-bit or a 10-bit ADC module.
Figure 19-22. 12-bit ADC Event Group Operating Mode Control Register (ADEVMODECR)
[offset = 10h]
31
24
Reserved
R-0
23
17
Reserved
R-0
R/W-0
15
10
7
6
16
No Reset on
ChnSel
9
8
Reserved
EV_DATA_FMT
R-0
R/W-0
5
4
1
0
Reserved
EV_CHID
OVR_EV_
RAM_IGN
3
Reserved
2
EV_MODE
FRZ_EV
R-0
R/W-0
R/W-0
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 19-23. 10-bit ADC Event Group Operating Mode Control Register (ADEVMODECR)
[offset = 10h]
31
24
Reserved
R-0
23
17
16
Reserved
No Reset on
ChnSel
R-0
R/W-0
15
8
Reserved
R-0
7
6
5
4
3
2
1
0
Reserved
EV_CHID
OVR_EV_
RAM_IGN
Reserved
EV_8BIT
EV_MODE
FRZ_EV
R-0
R/W-0
R/W-0
R-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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Table 19-10. ADC Event Group Operating Mode Control Register (ADEVMODECR)
Field Descriptions
Field
Reserved
Value
0
No Reset on ChnSel
Description
Reads return zeros, writes have no effect.
No Event Group Results Memory Reset on New Channel Select. This bit determines whether the event
group results’ RAM is reset whenever a non-zero value is written to the event group channel select
register.
Any operation mode read/write:
0
Event group results RAM is reset when a non-zero value is written to event group channel select
register, even if event group conversions are completed.
1
Event group results RAM is not reset when a non-zero value is written to event group channel select
register, and event group conversions are completed.
If the event group conversions are ongoing (active or frozen), then writing a non-zero value to the
event group channel select register will always reset the event group results RAM.
Reserved
0
EV_DATA_FMT
Reads return zeros, writes have no effect.
Event Group Read Data Format. This field is only applicable when the ADC module is configured to be
a 12-bit ADC module. This field determines the format in which the conversion results are read out of
the Event group results RAM when using the FIFO interface, that is, when reading from the
ADEVBUFFER or ADEVEMUBUFFER locations.
Any operation mode read/write:
Reserved
0
Conversion results are read out in full 12-bit format. This is the default mode.
1h
Conversion results are read out in 10-bit format. Bits 11-2 of the 12-bit conversion result are returned
as the 10-bit conversion result.
2h
Conversion results are read out in 8-bit format. Bits 11-4 of the 12-bit conversion result are returned as
the 8-bit conversion result.
3h
Reserved. The full 12-bit conversion result is returned if programmed.
0
Reads return zeros, writes have no effect.
EV_CHID
Enable Channel Id for the Event Group conversion results to be read. This bit only affects the “read
from FIFO” mode. The ADC always stores the channel id in the results RAM. Any 16-bit read
performed in the “read from RAM” mode will return the 5-bit channel id along with the 10-bit conversion
result.
Any operation mode read/write:
0
Bits 14-10, the channel id field, of the data read from the Event Group results’ FIFO is read as 00000b.
1
Bits 14-10, the channel id field, of the data read from the Event Group results’ FIFO contains the
number of the ADC analog input to which the conversion result belongs.
OVR_EV_RAM_IGN
This bit allows the ADC module to overwrite the contents of the Event Group results memory under an
overrun condition.
Any operation mode read/write:
Reserved
0
The ADC cannot overwrite the contents of the Event Group results memory. When an overrun of this
memory occurs, the software needs to read out all the contents of this memory before the ADC is able
to write a new conversion result for the Event Group.
1
When an overrun of the Event Group results memory occurs, the ADC proceeds to overwrite the
contents with any new conversion results for the Event Group, starting with the first location in this
memory.
0
Reads return zeros, writes have no effect.
EV_8BIT
Event Group 8-bit result mode. This bit is only applicable when the ADC module is configured to be a
10-bit ADC module. This bit allows the Event Group conversion results to be read out in an 8-bit
format. This bit only applies to the “read from FIFO” mode. The lower 2 bits of the 10-bit conversion
result are discarded and the upper 8 bits are shifted right two places to form the 8-bit conversion result.
Any operation mode read/write:
0
The Event Group conversion result is read out as a 10-bit value in the “read from Event Group FIFO”
mode.
1
The Event Group conversion result is read out as an 8-bit value in the “read from Event Group FIFO”
mode.
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Table 19-10. ADC Event Group Operating Mode Control Register (ADEVMODECR)
Field Descriptions (continued)
Field
Value
EV_MODE
Description
Event Group Conversion Mode. This bit defines whether the input channels selected for conversion in
the Event Group are converted only once per trigger, or are continuously converted.
Any operation mode read/write:
0
The channels selected for conversion in the Event Group are converted only once when the selected
event trigger condition occurs.
1
The channels selected for conversion in the Event Group are converted continuously when the
selected event trigger condition occurs.
FRZ_EV
Event Group Freeze Enable. This bit allows an Event Group conversion sequence to be frozen if a
Group1 or a Group2 conversion is requested. The Event Group conversion is kept frozen while the
Group1 or Group2 conversion is active, and continues from where it was frozen once the Group1 or
Group2 conversions are completed.
While the Event Group conversion is frozen, the EV_STOP status flag in the ADEVSR register
indicates that the Event Group conversions have stopped. This bit gets cleared when the Event Group
conversions resume.
Any operation mode read/write:
732
0
Event Group conversions cannot be frozen. All the channels selected for conversion in the Event
Group are converted before the ADC can switch over to servicing any other conversion group.
1
Event Group conversions are frozen whenever there is a request for conversion from Group1 or
Group2.
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19.11.6 ADC Group1 Operating Mode Control Register (ADG1MODECR)
ADC Group1 Operating Mode Control Register (ADG1MODECR) is shown in Figure 19-24 and Figure 1925, and described in Table 19-11. As shown, the format of the ADG1MODECR is different based on
whether the ADC module is configured to be a 12-bit or a 10-bit ADC module.
Figure 19-24. 12-bit ADC Group1 Operating Mode Control Register (ADG1MODECR)
[offset = 14h]
31
24
Reserved
R-0
23
17
Reserved
R-0
R/W-0
15
10
7
6
16
No Reset on
ChnSel
9
8
Reserved
G1_DATA_FMT
R-0
R/W-0
5
4
3
2
1
0
Reserved
G1_CHID
OVR_G1_
RAM_IGN
G1_HW_TRIG
Reserved
G1_MODE
FRZ_G1
R-0
R/W-0
R/W-0
R/W-0
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 19-25. 10-bit ADC Group1 Operating Mode Control Register (ADG1MODECR)
[offset = 14h]
31
24
Reserved
R-0
23
17
16
Reserved
No Reset on
ChnSel
R-0
R/W-0
15
8
Reserved
R-0
7
6
5
4
3
2
1
0
Reserved
G1_CHID
OVR_G1_
RAM_IGN
G1_HW_TRIG
G1_8BIT
G1_MODE
FRZ_G1
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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Table 19-11. ADC Group1 Operating Mode Control Register (ADG1MODECR)
Field Descriptions
Field
Value
Reserved
0
No Reset on ChnSel
Description
Reads return zeros, writes have no effect.
No Group1 Results Memory Reset on New Channel Select. This bit determines whether the group1
results’ RAM is reset whenever a non-zero value is written to the group1 channel select register.
Any operation mode read/write:
0
Group1 results RAM is reset when a non-zero value is written to group1 channel select register, even if
group1 conversions are completed.
1
Group1 results RAM is not reset when a non-zero value is written to group1 channel select register,
and group1 conversions are completed.
If the group1 conversions are ongoing (active or frozen), then writing a nonzero value to the group1
channel select register will always reset the group1 results RAM.
Reserved
0
G1_DATA_FMT
Reads return zeros, writes have no effect.
Group1 Read Data Format. This field is only applicable when the ADC module is configured to be a
12-bit ADC module. This field determines the format in which the conversion results are read out of the
group1 results RAM when using the FIFO interface, that is, when reading from the ADG1BUFFER or
ADG1EMUBUFFER locations.
Any operation mode read/write:
Reserved
0
Conversion results are read out in full 12-bit format. This is the default mode.
1h
Conversion results are read out in 10-bit format. Bits 11-2 of the 12-bit conversion result are returned
as the 10-bit conversion result.
2h
Conversion results are read out in 8-bit format. Bits 11-4 of the 12-bit conversion result are returned as
the 8-bit conversion result.
3h
Reserved. The full 12-bit conversion result is returned if programmed.
0
Reads return zeros, writes have no effect.
G1_CHID
Enable Channel Id for the Group1 conversion results to be read. This bit only affects the “read from
FIFO” mode. The ADC always stores the channel id in the results RAM. Any 16-bit read performed in
the “read from RAM” mode will return the 5-bit channel id along with the 10-bit conversion result.
Any operation mode read/write:
0
Bits 14-10, the channel id field, of the data read from the Group1 results’ FIFO is read as 00000b.
1
Bits 14-10, the channel id field, of the data read from the Group1 results’ FIFO contains the number of
the ADC analog input to which the conversion result belongs.
OVR_G1_RAM_IGN
This bit allows the ADC module to overwrite the contents of the Group1 results memory under an
overrun condition.
Any operation mode read/write:
0
The ADC cannot overwrite the contents of the Group1 results memory. When an overrun of this
memory occurs, the software needs to read out all the contents of this memory before the ADC is able
to write a new conversion result for the Group1.
1
When an overrun of the Group1 results memory occurs, the ADC proceeds to overwrite the contents
with any new conversion results for the Group1, starting with the first location in this memory.
G1_HW_TRIG
Group1 Hardware Triggered. This bit allows the Group1 to be hardware triggered. The Group1 is
software triggered by default. For more details on how to trigger a conversion group, please refer to
Section 19.3.6.
Any operation mode read/write:
0
The Group1 is software-triggered. A Group1 conversion starts whenever the Group1 channel select
register (ADG1SEL) is written with a non-zero value.
1
The Group1 is hardware-triggered. A Group1 conversion starts whenever the Group1 channel select
register has a non-zero value, and the specified hardware trigger occurs. The hardware trigger for the
Group1 is specified in the Group1 Trigger Source register (ADG1SRC).
G1_8BIT
Group1 8-bit result mode. This bit is only applicable when the ADC module is configured to be a 10-bit
ADC module. This bit allows the Group1 conversion results to be read out in an 8-bit format. This bit
only applies to the “read from FIFO” mode. The lower 2 bits of the 10-bit conversion result are
discarded and the upper 8 bits are shifted right two places to form the 8-bit conversion result.
Any operation mode read/write:
734
0
The Group1 conversion result is read out as a 10-bit value in the “read from Group1 FIFO” mode.
1
The Group1 conversion result is read out as an 8-bit value in the “read from Group1 FIFO” mode.
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Table 19-11. ADC Group1 Operating Mode Control Register (ADG1MODECR)
Field Descriptions (continued)
Field
Value
G1_MODE
Description
Group1 Conversion Mode. This bit defines whether the input channels selected for conversion in the
Group1 are converted only once, or are continuously converted.
Any operation mode read/write:
0
The channels selected for conversion in the Group1 are converted only once.
1
The channels selected for conversion in the Group1 are converted continuously.
FRZ_G1
Group1 Freeze Enable. This bit allows a Group1 conversion sequence to be frozen if an Event Group
or a Group2 conversion is requested. The Group1 conversion is kept frozen while the Event Group or
Group2 conversion is active, and continues from where it was frozen once the Event Group or Group2
conversions are completed.
While the Group1 conversion is frozen, the G1_STOP status flag in the ADG1SR register indicates that
the Group1 conversions have stopped. This bit gets cleared when the Group1 conversions resume.
Any operation mode read/write:
0
Group1 conversions cannot be frozen. All the channels selected for conversion in the Group1 are
converted before the ADC can switch over to servicing any other conversion group.
1
Group1 conversions are frozen whenever there is a request for conversion from Event Group or
Group2.
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19.11.7 ADC Group2 Operating Mode Control Register (ADG2MODECR)
ADC Group2 Operating Mode Control Register (ADG2MODECR) is shown in Figure 19-26 and Figure 1927, described in Table 19-12. As shown, the format of the ADG2MODECR is different based on whether
the ADC module is configured to be a 12-bit or a 10-bit ADC module.
Figure 19-26. 12-bit ADC Group2 Operating Mode Control Register (ADG2MODECR)
[offset = 18h]
31
24
Reserved
R-0
23
16
Reserved
No Reset on
ChnSel
R-0
R/W-0
15
10
7
6
9
8
Reserved
G2_DATA_FMT
R-0
R/W-0
5
4
3
2
1
0
Reserved
G2_CHID
OVR_G2_
RAM_IGN
G2_HW_TRIG
Reserved
G2_MODE
FRZ_G2
R-0
R/W-0
R/W-0
R/W-0
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 19-27. 10-bit ADC Group2 Operating Mode Control Register (ADG2MODECR)
[offset = 18h]
31
24
Reserved
R-0
23
16
Reserved
No Reset on
ChnSel
R-0
R/W-0
15
8
Reserved
R-0
7
6
5
4
3
2
1
0
Reserved
G2_CHID
OVR_G2_
RAM_IGN
G2_HW_TRIG
G2_8BIT
G2_MODE
FRZ_G2
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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Table 19-12. ADC Group 2 Operating Mode Control Register (ADG2MODECR)
Field Descriptions
Field
Reserved
Value
0
No Reset on ChnSel
Description
Reads return zeros, writes have no effect.
No Group2 Results Memory Reset on New Channel Select. This bit determines whether the group2
results’ RAM is reset whenever a non-zero value is written to the group2 channel select register.
Any operation mode read/write:
0
Group2 results RAM is reset when a non-zero value is written to group2 channel select register, even if
group2 conversions are completed.
1
Group2 results RAM is not reset when a non-zero value is written to group2 channel select register,
and group2 conversions are completed.
If the group2 conversions are ongoing (active or frozen), then writing a nonzero value to the group2
channel select register will always reset the group2 results RAM.
Reserved
0
G2_DATA_FMT
Reads return zeros, writes have no effect.
Group2 Read Data Format. This field is only applicable when the ADC module is configured to be a
12-bit ADC module. This field determines the format in which the conversion results are read out of the
group1 results RAM when using the FIFO interface, that is, when reading from the ADG2BUFFER or
ADG2EMUBUFFER locations.
Any operation mode read/write:
Reserved
0
Conversion results are read out in full 12-bit format. This is the default mode.
1h
Conversion results are read out in 10-bit format. Bits 11-2 of the 12-bit conversion result are returned
as the 10-bit conversion result.
2h
Conversion results are read out in 8-bit format. Bits 11-4 of the 12-bit conversion result are returned as
the 8-bit conversion result.
3h
Reserved. The full 12-bit conversion result is returned if programmed.
0
Reads return zeros, writes have no effect.
G2_CHID
Enable Channel Id for the Group2 conversion results to be read. This bit only affects the “read from
FIFO” mode. The ADC always stores the channel id in the results RAM. Any 16-bit read performed in
the “read from RAM” mode will return the 5-bit channel id along with the 10-bit conversion result.
Any operation mode read/write:
0
Bits 14-10, the channel id field, of the data read from the Group2 results’ FIFO is read as 00000b.
1
Bits 14-10, the channel id field, of the data read from the Group2 results’ FIFO contains the number of
the ADC analog input to which the conversion result belongs.
OVR_G2_RAM_IGN
This bit allows the ADC module to overwrite the contents of the Group2 results memory under an
overrun condition.
Any operation mode read/write:
0
The ADC cannot overwrite the contents of the Group2 results memory. When an overrun of this
memory occurs, the software needs to read out all the contents of this memory before the ADC is able
to write a new conversion result for the Group2.
1
When an overrun of the Group2 results memory occurs, the ADC proceeds to overwrite the contents
with any new conversion results for the Group2, starting with the first location in this memory.
G2_HW_TRIG
Group2 Hardware Triggered. This bit allows the Group2 to be hardware triggered. The Group2 is
software triggered by default. For more details on how to trigger a conversion group, please refer to
Section 19.3.6.
Any operation mode read/write:
0
The Group2 is software-triggered. A Group2 conversion starts whenever the Group2 channel select
register (ADG2SEL) is written with a non-zero value.
1
The Group2 is hardware-triggered. A Group2 conversion starts whenever the Group2 channel select
register has a non-zero value, and the specified hardware trigger occurs. The hardware trigger for the
Group2 is specified in the Group2 Trigger Source register (ADG2SRC).
G2_8BIT
Group2 8-bit result mode. This bit is only applicable when the ADC module is configured to be a 10-bit
ADC module. This bit allows the Group2 conversion results to be read out in an 8-bit format. This bit
only applies to the “read from FIFO” mode. The lower 2 bits of the 10-bit conversion result are
discarded and the upper 8 bits are shifted right two places to form the 8-bit conversion result.
Any operation mode read/write:
0
The Group2 conversion result is read out as a 10-bit value in the “read from Group2 FIFO” mode.
1
The Group2 conversion result is read out as an 8-bit value in the “read from Group2 FIFO” mode.
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Table 19-12. ADC Group 2 Operating Mode Control Register (ADG2MODECR)
Field Descriptions (continued)
Field
Value
G2_MODE
Description
Group2 Conversion Mode. This bit defines whether the input channels selected for conversion in the
Group2 are converted only once, or are continuously converted.
Any operation mode read/write:
0
The channels selected for conversion in the Group2 are converted only once.
1
The channels selected for conversion in the Group2 are converted continuously.
FRZ_G2
Group2 Freeze Enable. This bit allows a Group2 conversion sequence to be frozen if an Event Group
or a Group1 conversion is requested. The Group2 conversion is kept frozen while the Event Group or
Group1 conversion is active, and continues from where it was frozen once the Event Group or Group1
conversions are completed.
While the Group2 conversion is frozen, the G2_STOP status flag in the ADG2SR register indicates that
the Group2 conversions have stopped. This bit gets cleared when the Group2 conversions resume.
Any operation mode read/write:
738
0
Group2 conversions cannot be frozen. All the channels selected for conversion in the Group2 are
converted before the ADC can switch over to servicing any other conversion group.
1
Group2 conversions are frozen whenever there is a request for conversion from Event Group or
Group1.
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19.11.8 ADC Event Group Trigger Source Select Register (ADEVSRC)
ADC Event Group Trigger Source Select Register (ADEVSRC) is shown in Figure 19-28 and described in
Table 19-13.
Figure 19-28. ADC Event Group Trigger Source Select Register (ADEVSRC) [offset = 1Ch]
31
8
Reserved
R-0
7
4
3
Reserved
5
EV_EDG_BOTH
EV_EDG_SEL
2
EV_SRC
0
R-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-13. ADC Event Group Trigger Source Select Register (ADEVSRC) Field Descriptions
Bit
31-5
4
Field
Value
Reserved
0
EV_EDG_BOTH
Description
Reads return zeros, writes have no effect.
EV Group Trigger Edge Polarity Select. This bit configures the event group to be triggered on both
rising and falling edge detected on the selected trigger source.
Any operation mode read/write:
3
0
The conversion is triggered only upon detecting an edge defined by the EV_EDG_SEL bit.
1
The conversion is triggered upon detecting either a rising or falling edge.
EV_EDG_SEL
Event Group Trigger Edge Polarity Select. This bit determines the polarity of the transition on the
selected source that triggers the Event Group conversion.
Any operation mode read/write:
2-0
0
A high-to-low transition on the selected source will trigger the Event Group conversion.
1
A low-to-high transition on the selected source will trigger the Event Group conversion.
EV_SRC
Event Group Trigger Source.
Any operation mode read/write:
0-7h
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The ADC module allows a trigger source to be selected for the Event Group from up to eight
options. These options are device-specific and the device specification must be referred to identify
the actual trigger sources.
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19.11.9 ADC Group1 Trigger Source Select Register (ADG1SRC)
ADC Group1 Trigger Source Select Register (ADG1SRC) is shown in Figure 19-29 and described in
Table 19-14.
Figure 19-29. ADC Group1 Trigger Source Select Register (ADG1SRC) [offset = 20h]
31
8
Reserved
R-0
7
4
3
Reserved
5
G1_EDG_BOTH
G1_EDG_SEL
2
G1_SRC
0
R-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-14. ADC Group1 Trigger Source Select Register (ADG1SRC) Field Descriptions
Bit
31-5
4
Field
Reserved
Value
0
G1_EDG_BOTH
Description
Reads return zeros, writes have no effect.
Group1 Trigger Edge Polarity Select. This bit configures the group1 to be triggered on both rising
and falling edge detected on the selected trigger source.
Any operation mode read/write:
3
0
The conversion is triggered only upon detecting an edge defined by the G1_EDG_SEL bit.
1
The conversion is triggered upon detecting either a rising or falling edge.
G1_EDG_SEL
Group1 Trigger Edge Polarity Select. This bit determines the polarity of the transition on the
selected source that triggers the Group1 conversion.
Any operation mode read/write:
2-0
0
A high-to-low transition on the selected source will trigger the Group1 conversion.
1
A low-to-high transition on the selected source will trigger the Group1 conversion.
G1_SRC
Group1 Trigger Source.
Any operation mode read/write:
0-7h
740
The ADC module allows a trigger source to be selected for the Group1 from up to eight options.
These options are device-specific and the device specification must be referred to identify the
actual trigger sources.
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19.11.10 ADC Group2 Trigger Source Select Register (ADG2SRC)
ADC Group2 Trigger Source Select Register (ADG2SRC) is shown in Figure 19-30 and described in
Table 19-15.
Figure 19-30. ADC Group2 Trigger Source Select Register (ADG2SRC) [offset = 24h]
31
8
Reserved
R-0
7
4
3
Reserved
5
G2_EDG_BOTH
G2_EDG_SEL
2
G2_SRC
0
R-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-15. ADC Group2 Trigger Source Select Register (ADG2SRC) Field Descriptions
Bit
31-5
4
Field
Value
Reserved
0
G2_EDG_BOTH
Description
Reads return zeros, writes have no effect.
Group2 Trigger Edge Polarity Select. This bit configures the group2 to be triggered on both rising
and falling edge detected on the selected trigger source.
Any operation mode read/write:
3
0
The conversion is triggered only upon detecting an edge defined by the G2_EDG_SEL bit.
1
The conversion is triggered upon detecting either a rising or falling edge.
G2_EDG_SEL
Group2 Trigger Edge Polarity Select. This bit determines the polarity of the transition on the
selected source that triggers the Group2 conversion.
Any operation mode read/write:
2-0
0
A high-to-low transition on the selected source will trigger the Group2 conversion.
1
A low-to-high transition on the selected source will trigger the Group2 conversion.
G2_SRC
Group2 Trigger Source.
Any operation mode read/write:
0-7h
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The ADC module allows a trigger source to be selected for the Group2 from up to eight options.
These options are device-specific and the device specification must be referred to identify the
actual trigger sources.
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19.11.11 ADC Event Interrupt Enable Control Register (ADEVINTENA)
ADC Event Group Interrupt Enable Control Register (ADEVINTENA) is shown in Figure 19-31 and
described in Table 19-16.
Figure 19-31. ADC Event Group Interrupt Enable Control Register (ADEVINTENA) [offset = 28h]
31
8
Reserved
R-0
7
3
2
1
0
Reserved
4
EV_END_
INT_EN
Reserved
EV_OVR_
INT_EN
EV_THR_
INT_EN
R-0
R/W-0
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-16. ADC Event Group Interrupt Enable Control Register (ADEVINTENA) Field Descriptions
Bit
31-4
3
Field
Reserved
Value
0
EV_END_INT_EN
Description
Reads return zeros, writes have no effect.
Event Group Conversion End Interrupt Enable. Please refer to Section 19.5.1 for more details
on the conversion end interrupts.
Any operation mode read/write:
2
Reserved
1
EV_OVR_INT_EN
0
No interrupt is generated when conversion of all the channels selected for conversion in the
Event Group is done.
1
An Event Group conversion end interrupt is generated when conversion of all the channels
selected for conversion in the Event Group is done.
0
Reads return zeros, writes have no effect.
Event Group Memory Overrun Interrupt Enable. A memory overrun occurs when the ADC tries
to write a new conversion result to the Event Group results memory that is already full. For
more details on the overrun interrupts, please refer to Section 19.5.3.
Any operation mode read/write:
0
0
No interrupt is generated if an Event Group memory overrun occurs.
1
An Event Group memory overrun interrupt is generated if an Event Group memory overrun
condition occurs.
EV_THR_INT_EN
Event Group Threshold Interrupt Enable. An Event Group threshold interrupt occurs when the
programmed Event Group threshold counter counts down to zero. Please refer to
Section 19.5.2 for more details.
Any operation mode read/write:
742
0
No interrupt is generated if the Event Group threshold counter reaches zero.
1
An Event Group threshold interrupt is generated if the Event Group threshold counter reaches
zero.
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19.11.12 ADC Group1 Interrupt Enable Control Register (ADG1INTENA)
ADC Group1 Interrupt Enable Control Register (ADG1INTENA) is shown in Figure 19-32 and described in
Table 19-17.
Figure 19-32. ADC Group1 Interrupt Enable Control Register (ADG1INTENA) [offset = 2Ch]
31
8
Reserved
R-0
7
3
2
1
0
Reserved
4
G1_END_
INT_EN
Reserved
G1_OVR_
INT_EN
G1_THR_
INT_EN
R-0
R/W-0
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-17. ADC Group1 Interrupt Enable Control Register (ADG1INTENA) Field Descriptions
Bit
31-4
3
Field
Reserved
Value
0
G1_END_INT_EN
Description
Reads return zeros, writes have no effect.
Group1 Conversion End Interrupt Enable. Please refer to Section 19.5.1 for more details on the
conversion end interrupts.
Any operation mode read/write:
2
Reserved
1
G1_OVR_INT_EN
0
No interrupt is generated when conversion of all the channels selected for conversion in the
Group1 is done.
1
A Group1 conversion end interrupt is generated when conversion of all the channels selected
for conversion in the Group1 is done.
0
Reads return zeros, writes have no effect.
Group1 Memory Overrun Interrupt Enable. A memory overrun occurs when the ADC tries to
write a new conversion result to the Group1 results memory that is already full. For more details
on the overrun interrupts, please refer to Section 19.5.3.
Any operation mode read/write:
0
0
No interrupt is generated if a Group1 memory overrun occurs.
1
A Group1 memory overrun interrupt is generated if a Group1 memory overrun condition occurs.
G1_THR_INT_EN
Group1 Threshold Interrupt Enable. A Group1 threshold interrupt occurs when the programmed
Group1 threshold counter counts down to zero. Please refer to Section 19.5.2 for more details.
Any operation mode read/write:
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0
No interrupt is generated if the Group1 threshold counter reaches zero.
1
A Group1 threshold interrupt is generated if the Group1 threshold counter reaches zero.
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19.11.13 ADC Group2 Interrupt Enable Control Register (ADG2INTENA)
ADC Group2 Interrupt Enable Control Register (ADG2INTENA) is shown in Figure 19-33 and described in
Table 19-18.
Figure 19-33. ADC Group2 Interrupt Enable Control Register (ADG2INTENA) [offset = 30h]
31
8
Reserved
R-0
7
3
2
1
0
Reserved
4
G2_END_
INT_EN
Reserved
G2_OVR_
INT_EN
G2_THR_
INT_EN
R-0
R/W-0
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-18. ADC Group2 Interrupt Enable Control Register (ADG2INTENA) Field Descriptions
Bit
31-4
3
Field
Reserved
Value
0
G2_END_INT_EN
Description
Reads return zeros, writes have no effect.
Group2 Conversion End Interrupt Enable. Please refer to Section 19.5.1 for more details on the
conversion end interrupts.
Any operation mode read/write:
2
Reserved
1
G2_OVR_INT_EN
0
No interrupt is generated when conversion of all the channels selected for conversion in the
Group2 is done.
1
A Group2 conversion end interrupt is generated when conversion of all the channels selected
for conversion in the Group2 is done.
0
Reads return zeros, writes have no effect.
Group2 Memory Overrun Interrupt Enable. A memory overrun occurs when the ADC tries to
write a new conversion result to the Group2 results memory that is already full. For more details
on the overrun interrupts, please refer to Section 19.5.3.
Any operation mode read/write:
0
0
No interrupt is generated if a Group2 memory overrun occurs.
1
A Group2 memory overrun interrupt is generated if a Group2 memory overrun condition occurs.
G2_THR_INT_EN
Group2 Threshold Interrupt Enable. A Group2 threshold interrupt occurs when the programmed
Group2 threshold counter counts down to zero. Please refer to Section 19.5.2 for more details.
Any operation mode read/write:
744
0
No interrupt is generated if the Group2 threshold counter reaches zero.
1
A Group2 threshold interrupt is generated if the Group2 threshold counter reaches zero.
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19.11.14 ADC Event Group Interrupt Flag Register (ADEVINTFLG)
ADC Event Group Interrupt Enable Control Register (ADEVINTENA) is shown in Figure 19-34 and
described in Table 19-19.
Figure 19-34. ADC Event Group Interrupt Flag Register (ADEVINTFLG) [offset = 34h]
31
8
Reserved
R-0
7
3
2
1
0
Reserved
4
EV_END
EV_MEM_
EMPTY
EV_MEM_
OVERRUN
EV_THR_
INT_FLG
R-0
R/W1C-0
R-1
R-0
R/W1C-0
LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset
Table 19-19. ADC Event Group Interrupt Flag Register (ADEVINTFLG) Field Descriptions
Bit
Field
31-4
Reserved
3
EV_END
Value
0
Description
Reads return zeros, writes have no effect.
Event Group Conversion End. This bit will be set only if the Event Group conversions are
configured to be in the single-conversion mode.
Any operation mode read:
0
All the channels selected for conversion in the Event Group have not yet been converted.
1
All the channels selected for conversion in the Event Group have been converted. An Event
Group conversion end interrupt is generated, if enabled, when this bit gets set.
This bit can be cleared by any one of the following ways:
• By writing a 1 to this bit
• By writing a 1 to the Event Group status register (ADEVSR) bit 0 (EV_END)
• By reading one conversion result from the Event Group results’ memory in the “read from
FIFO” mode
• By writing a new set of channels to the Event Group channel select register
2
EV_MEM_EMPTY
Event Group Results Memory Empty. This is a read-only bit; writes have no effect. It is not a
source of an interrupt from the ADC module.
Any operation mode read:
1
0
The Event Group results memory is not empty.
1
The Event Group results memory is empty.
EV_MEM_OVERRUN
Event Group Memory Overrun. This is a read-only bit; writes have no effect.
Any operation mode read:
0
0
Event Group results memory has not overrun.
1
Event Group results memory has overrun.
EV_THR_INT_FLG
Event Group Threshold Interrupt Flag.
Any operation mode read:
0
The number of conversions completed for the Event Group is smaller than the threshold
programmed in the Event Group interrupt threshold register.
1
The number of conversions completed for the Event Group is equal to or greater than the
threshold programmed in the Event Group interrupt threshold register.
This bit can be cleared by writing a 1 ; writing a 0 has no effect.
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19.11.15 ADC Group1 Interrupt Flag Register (ADG1INTFLG)
ADC Group1 Interrupt Flag Register (ADG1INTFLG) is shown in Figure 19-35 and described in Table 1920.
Figure 19-35. ADC Group1 Interrupt Flag Register (ADG1INTFLG) [offset = 38h]
31
8
Reserved
R-0
7
3
2
1
0
Reserved
4
G1_END
G1_MEM_
EMPTY
G1_MEM_
OVERRUN
G1_THR_
INT_FLG
R-0
R/W1C-0
R-1
R-0
R/W1C-0
LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset
Table 19-20. ADC Group1 Interrupt Flag Register (ADG1INTFLG) Field Descriptions
Bit
Field
31-4
Reserved
3
G1_END
Value
0
Description
Reads return zeros, writes have no effect.
Group1 Conversion End. This bit will be set only if the Group1 conversions are configured to be
in the single-conversion mode.
Any operation mode read:
0
All the channels selected for conversion in the Group1 have not yet been converted.
1
All the channels selected for conversion in the Group1 have been converted. A Group1
conversion end interrupt is generated, if enabled, when this bit gets set.
This bit can be cleared by any one of the following ways:
• By writing a 1 to this bit
• By writing a 1 to the Group1 status register (ADG1SR) bit 0 (G1_END)
• By reading one conversion result from the Group1 results’ memory in the “read from FIFO”
mode
• By writing a new set of channels to the Group1 channel select register
2
G1_MEM_EMPTY
Group1 Results Memory Empty. This is a read-only bit; writes have no effect. It is not a source
of an interrupt from the ADC module.
Any operation mode read:
1
0
The Group1 results memory is not empty.
1
The Group1 results memory is empty.
G1_MEM_OVERRUN
Group1 Memory Overrun. This is a read-only bit; writes have no effect.
Any operation mode read:
0
0
Group1 results memory has not overrun.
1
Group1 results memory has overrun.
G1_THR_INT_FLG
Group1 Threshold Interrupt Flag.
Any operation mode read:
0
The number of conversions completed for the Group1 is smaller than the threshold
programmed in the Group1 interrupt threshold register.
1
The number of conversions completed for the Group1 is equal to or greater than the threshold
programmed in the Group1 interrupt threshold register.
This bit can be cleared by writing a 1 ; writing a 0 has no effect.
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19.11.16 ADC Group2 Interrupt Flag Register (ADG2INTFLG)
ADC Group2 Interrupt Flag Register (ADG2INTFLG) is shown in Figure 19-36 and described in Table 1921.
Figure 19-36. ADC Group2 Interrupt Flag Register (ADG2INTFLG) [offset = 3Ch]
31
8
Reserved
R-0
7
3
2
1
0
Reserved
4
G2_END
G2_MEM_
EMPTY
G2_MEM_
OVERRUN
G2_THR_
INT_FLG
R-0
R/W1C-0
R-1
R-0
R/W1C-0
LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset
Table 19-21. ADC Group2 Interrupt Flag Register (ADG2INTFLG) Field Descriptions
Bit
Field
31-4
Reserved
3
G2_END
Value
0
Description
Reads return zeros, writes have no effect.
Group2 Conversion End. This bit will be set only if the Group2 conversions are configured to be
in the single-conversion mode.
Any operation mode read:
0
All the channels selected for conversion in the Group2 have not yet been converted.
1
All the channels selected for conversion in the Group2 have been converted. A Group2
conversion end interrupt is generated, if enabled, when this bit gets set.
This bit can be cleared by any one of the following ways:
• By writing a 1 to this bit
• By writing a 1 to the Group2 status register (ADG2SR) bit 0 (G2_END)
• By reading one conversion result from the Group2 results’ memory in the “read from FIFO”
mode
• By writing a new set of channels to the Group2 channel select register
2
G2_MEM_EMPTY
Group2 Results Memory Empty. This is a read-only bit; writes have no effect. It is not a source
of an interrupt from the ADC module.
Any operation mode read:
1
0
The Group2 results memory is not empty.
1
The Group2 results memory is empty.
G2_MEM_OVERRUN
Group2 Memory Overrun. This is a read-only bit; writes have no effect.
Any operation mode read:
0
0
Group2 results memory has not overrun.
1
Group2 results memory has overrun.
G2_THR_INT_FLG
Group2 Threshold Interrupt Flag.
Any operation mode read:
0
The number of conversions completed for the Group2 is smaller than the threshold
programmed in the Group2 interrupt threshold register.
1
The number of conversions completed for the Group2 is equal to or greater than the threshold
programmed in the Group2 interrupt threshold register.
This bit can be cleared by writing a 1 ; writing a 0 has no effect.
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19.11.17 ADC Event Group Threshold Interrupt Control Register (ADEVTHRINTCR)
ADC Event Group Threshold Interrupt Control Register (ADEVTHRINTCR) is shown in Figure 19-37 and
described in Table 19-22.
Figure 19-37. ADC Event Group Threshold Interrupt Control Register (ADEVTHRINTCR)
[offset = 40h]
31
16
15
9
8
0
Reserved
Sign Extension
EV_THR
R-0
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-22. ADC Event Group Threshold Interrupt Control Register (ADEVTHRINTCR)
Field Descriptions
Bit
Field
Value
0
Description
31-16
Reserved
Reads return zeros, writes have no effect.
15-9
Sign Extension
These bits always read the same as the bit 8 of this register.
8-0
EV_THR
Event Group Threshold Counter.
Before ADC conversions begin on the Event Group, this field is initialized to the number of
conversion results that the Event Group memory should contain before interrupting the CPU. This
counter decrements when the ADC module writes a new conversion result to the Event Group
results’ memory. The counter increments for each read of a conversion result from the Event Group
results’ memory in the “read from FIFO” mode. The threshold counter is not affected for a direct
read from the Event Group results’ memory. Also, a simultaneous ADC write and a CPU/DMA read
from the Event Group FIFO will leave the threshold counter unchanged. In case of an Event Group
Results’ memory overrun condition, if new conversion results are not allowed to overwrite the
existing memory contents, then the Event Group threshold counter is not decremented.
Please refer to Section 19.5.2 for more details on the threshold interrupts.
19.11.18 ADC Group1 Threshold Interrupt Control Register (ADG1THRINTCR)
ADC Group1 Threshold Interrupt Control Register (ADG1THRINTCR) is shown in Figure 19-38 and
described in Table 19-23.
Figure 19-38. ADC Group1 Threshold Interrupt Control Register (ADG1THRINTCR) [offset = 44h]
31
16
15
9
8
0
Reserved
Sign Extension
G1_THR
R-0
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-23. ADC Group1 Threshold Interrupt Control Register (ADG1THRINTCR)
Field Descriptions
Bit
Field
Value
0
Description
31-16
Reserved
Reads return zeros, writes have no effect.
15-9
Sign Extension
These bits always read the same as the bit 8 of this register.
8-0
G1_THR
Group1 Threshold Counter.
Before ADC conversions begin on the Group1, this field is initialized to the number of conversion
results that the Group1 memory should contain before interrupting the CPU. This counter
decrements when the ADC module writes a new conversion result to the Group1 results’ memory.
The counter increments for each read of a conversion result from the Group1 results’ memory in the
“read from FIFO” mode. The threshold counter is not affected for a direct read from the group1
results’ memory. Also, a simultaneous ADC write and a CPU/DMA read from the Group1 FIFO will
leave the threshold counter unchanged. In case of an Group1 Results’ memory overrun condition, if
new conversion results are not allowed to overwrite the existing memory contents, then the Group1
threshold counter is not decremented.
Please refer to Section 19.5.2 for more details on the threshold interrupts.
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19.11.19 ADC Group2 Threshold Interrupt Control Register (ADG2THRINTCR)
The ADC Group2 Threshold Interrupt Control Register (ADG2THRINTCR) is shown in Figure 19-39 and
described in Table 19-24.
Figure 19-39. ADC Group2 Threshold Interrupt Control Register (ADG2THRINTCR) [offset = 48h]
31
16
15
9
8
0
Reserved
Sign Extension
G2_THR
R-0
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-24. ADC Group2 Threshold Interrupt Control Register (ADG2THRINTCR)
Field Descriptions
Bit
Field
Value
0
Description
31-16
Reserved
15-9
Sign Extension
Reads return zeros, writes have no effect.
These bits always read the same as the bit 8 of this register.
8-0
G2_THR
Group2 Threshold Counter.
Before ADC conversions begin on the Group2, this field is initialized to the number of conversion
results that the Group2 memory should contain before interrupting the CPU. This counter
decrements when the ADC module writes a new conversion result to the Group2 results’ memory.
The counter increments for each read of a conversion result from the Group2 results’ memory in the
“read from FIFO” mode. The threshold counter is not affected for a direct read from the group2
results’ memory. Also, a simultaneous ADC write and a CPU/DMA read from the Group2 FIFO will
leave the threshold counter unchanged. In case of an Group2 Results’ memory overrun condition, if
new conversion results are not allowed to overwrite the existing memory contents, then the Group2
threshold counter is not decremented.
Please refer to Section 19.5.2 for more details on the threshold interrupts.
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19.11.20 ADC Event Group DMA Control Register (ADEVDMACR)
ADC Event Group DMA Control Register (ADEVDMACR) is shown in Figure 19-40 and described in
Table 19-25.
Figure 19-40. ADC Event Group DMA Control Register (ADEVDMACR) [offset = 4Ch]
31
25
24
16
Reserved
EV_BLOCKS
R-0
R/W-0
15
8
Reserved
R-0
7
4
Reserved
3
2
DMA_EV_END EV_BLK_XFER
R-0
R/W-0
R/W-0
1
0
Reserved
EV_DMA_EN
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-25. ADC Event Group DMA Control Register (ADEVDMACR) Field Descriptions
Bit
Field
31-25
Reserved
24-16
EV_BLOCKS
Value
0
Description
Reads return zeros, writes have no effect.
Number of Event Group Result buffers to be transferred using DMA if the ADC module is
configured to generate a DMA request. If the Event Group is configured to use the block
transfer mode of the DMA module, then the ADC module generates a DMA request after the
Event Group results’ memory accumulates EV_BLOCKS number of conversion results.
This feature is designed to be used in place of the threshold interrupt for the Event Group. As a
result, the EV_THR field of the Event Group Interrupt Threshold Control Register and the
EV_BLOCKS field of the Event Group DMA Control Register are the same.
Any operation mode read/write:
0
1h-1FFh
15-4
3
Reserved
0
DMA_EV_END
No DMA transfer occurs even if EV_BLK_XFER is set to 1.
One DMA request is generated if the EV_BLK_XFER is set to ‘1’ and the specified number of
Event Group conversion results have been accumulated.
Reads return zeros, writes have no effect.
Event Group Conversion End DMA Transfer Enable.
Any operation mode read:
0
ADC module generates a DMA request for each write to the Event group results RAM if
EV_DMA_EN is set.
1
ADC module generates a DMA request when the ADC has completed the conversions for all
channels selected for conversion in the event group.
If DMA_EV_END bit is set to ‘1’, EV_DMA_EN bit is ignored and DMA requests will be
generated every time the DMA_EV_END flag in the event group status register is set. The
DMA_EV_END bit must be set before enabling conversions for the event group.
2
EV_BLK_XFER
Event Group Block DMA Transfer Enable.
Any operation mode read:
0
ADC module generates a DMA request for each write to the Event Group memory if
EV_DMA_EN is set.
1
ADC module generates a DMA request when the ADC has written EV_BLOCKS number of
buffers into the Event Group memory.
If EV_BLK_XFER bit is set to 1, EV_DMA_EN bit is ignored and DMA requests will be
generated every time the Threshold Counter reaches 0 from a count value of 1.
1
750
Reserved
0
Reads return zeros, writes have no effect.
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Table 19-25. ADC Event Group DMA Control Register (ADEVDMACR) Field Descriptions (continued)
Bit
0
Field
Value
EV_DMA_EN
Description
Event Group DMA Transfer Enable.
Any operation mode read:
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0
ADC module does not generate a DMA request when it writes the conversion result to the
Event Group memory.
1
ADC module generates a DMA transfer when the ADC has written to the Event Group memory.
The EV_BLK_XFER bit must be cleared to ‘0’ for this DMA request to be generated.
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19.11.21 ADC Group1 DMA Control Register (ADG1DMACR)
ADC Group1 DMA Control Register (ADG1DMACR) is shown in Figure 19-41 and described in Table 1926.
Figure 19-41. ADC Group1 DMA Control Register (ADG1DMACR) [offset = 50h]
31
25
24
16
Reserved
G1_BLOCKS
R-0
R/W-0
15
8
Reserved
R-0
7
4
Reserved
3
2
DMA_G1_END G1_BLK_XFER
R-0
R/W-0
R/W-0
1
0
Reserved
G1_DMA_EN
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-26. ADC Group1 DMA Control Register (ADG1DMACR) Field Descriptions
Bit
Field
31-25
Reserved
24-16
G1_BLOCKS
Value
0
Description
Reads return zeros, writes have no effect.
Number of Group1 Result buffers to be transferred using DMA if the ADC module is configured
to generate a DMA request. If the Group1 is configured to use the block transfer mode of the
DMA module, then the ADC module generates a DMA request after the Group1 results’
memory accumulates G1_BLOCKS number of conversion results.
This feature is designed to be used in place of the threshold interrupt for the Group1. As a
result, the G1_THR field of the Group1 Interrupt Threshold Control Register and the
G1_BLOCKS field of the Group1 DMA Control Register are the same.
Any operation mode read/write:
0
1h-1FFh
15-4
3
Reserved
0
DMA_G1_END
No DMA transfer occurs even if G1_BLK_XFER is set to 1.
One DMA request is generated if the G1_BLK_XFER is set to ‘1’ and the specified number of
Group1 conversion results have been accumulated.
Reads return zeros, writes have no effect.
Group1 Conversion End DMA Transfer Enable.
Any operation mode read:
0
ADC module generates a DMA request for each write to the group1 results RAM if
G1_DMA_EN is set.
1
ADC module generates a DMA request when the ADC has completed the conversions for all
channels selected for conversion in the group1.
If DMA_G1_END bit is set to ‘1’, G1_DMA_EN bit is ignored and DMA requests will be
generated every time the DMA_G1_END flag in the group 1 status register is set. The
DMA_G1_END bit must be set before enabling conversions for the group 1.
2
G1_BLK_XFER
Group1 Block DMA Transfer Enable.
Any operation mode read:
0
ADC module generates a DMA request for each write to the Group1 memory if G1_DMA_EN is
set.
1
ADC module generates a DMA request when the ADC has written G1_BLOCKS number of
buffers into the Group1 memory.
If G1_BLK_XFER bit is set to 1, G1_DMA_EN bit is ignored and DMA requests will be
generated every time the Threshold Counter reaches 0 from a count value of 1.
1
752
Reserved
0
Reads return zeros, writes have no effect.
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Table 19-26. ADC Group1 DMA Control Register (ADG1DMACR) Field Descriptions (continued)
Bit
0
Field
Value
G1_DMA_EN
Description
Group1 DMA Transfer Enable.
Any operation mode read:
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0
ADC module does not generate a DMA request when it writes the conversion result to the
Group1 memory.
1
ADC module generates a DMA transfer when the ADC has written to the Group1 memory. The
G1_BLK_XFER bit must be cleared to ‘0’ for this DMA request to be generated.
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19.11.22 ADC Group2 DMA Control Register (ADG2DMACR)
ADC Group2 DMA Control Register (ADG2DMACR) is shown in Figure 19-42 and described in Table 1927.
Figure 19-42. ADC Group2 DMA Control Register (ADG2DMACR) [offset = 54h]
31
25
24
16
Reserved
G2_BLOCKS
R-0
R/W-0
15
8
Reserved
R-0
7
4
Reserved
3
2
DMA_G2_END G2_BLK_XFER
R-0
R/W-0
R/W-0
1
0
Reserved
G2_DMA_EN
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-27. ADC Group2 DMA Control Register (ADG2DMACR) Field Descriptions
Bit
Field
31-25
Reserved
24-16
G2_BLOCKS
Value
0
Description
Reads return zeros, writes have no effect.
Number of Group2 Result buffers to be transferred using DMA if the ADC module is configured
to generate a DMA request. If the Group2 is configured to use the block transfer mode of the
DMA module, then the ADC module generates a DMA request after the Group2 results’
memory accumulates G2_BLOCKS number of conversion results.
This feature is designed to be used in place of the threshold interrupt for the Group2. As a
result, the G2_THR field of the Group2 Interrupt Threshold Control Register and the
G2_BLOCKS field of the Group2 DMA Control Register are the same.
Any operation mode read/write:
0
1h-1FFh
15-4
3
Reserved
0
DMA_G2_END
No DMA transfer occurs even if G2_BLK_XFER is set to 1.
One DMA request is generated if the G2_BLK_XFER is set to ‘1’ and the specified number of
Group2 conversion results have been accumulated.
Reads return zeros, writes have no effect.
Group2 Conversion End DMA Transfer Enable.
Any operation mode read:
0
ADC module generates a DMA request for each write to the group2 results RAM if
G2_DMA_EN is set.
1
ADC module generates a DMA request when the ADC has completed the conversions for all
channels selected for conversion in the group2.
If DMA_G2_END bit is set to ‘1’, G2_DMA_EN bit is ignored and DMA requests will be
generated every time the DMA_G2_END flag in the group 2 status register is set. The
DMA_G2_END bit must be set before enabling conversions for the group 2.
2
G2_BLK_XFER
Group2 Block DMA Transfer Enable.
Any operation mode read:
0
ADC module generates a DMA request for each write to the Group2 memory if G2_DMA_EN is
set.
1
ADC module generates a DMA request when the ADC has written G2_BLOCKS number of
buffers into the Group2 memory.
If G2_BLK_XFER bit is set to 1, G2_DMA_EN bit is ignored and DMA requests will be
generated every time the Threshold Counter reaches 0 from a count value of 1.
1
754
Reserved
0
Reads return zeros, writes have no effect.
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Table 19-27. ADC Group2 DMA Control Register (ADG2DMACR) Field Descriptions (continued)
Bit
0
Field
Value
G2_DMA_EN
Description
Group2 DMA Transfer Enable.
Any operation mode read:
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0
ADC module does not generate a DMA request when it writes the conversion result to the
Group2 memory.
1
ADC module generates a DMA transfer when the ADC has written to the Group2 memory. The
G2_BLK_XFER bit must be cleared to ‘0’ for this DMA request to be generated.
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19.11.23 ADC Results Memory Configuration Register (ADBNDCR)
ADC Results Memory Configuration Register (ADBNDCR) [offset = 0x58] is shown in Figure 19-43 and
described in Table 19-28.
Please refer to Section 19.3.8 for further details on how the conversion results are stored in the ADC
results’ RAM.
Figure 19-43. ADC Results Memory Configuration Register (ADBNDCR) [offset = 58h]
31
25
24
16
Reserved
BNDA
R-0
R/W-0
15
9
8
0
Reserved
BNDB
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-28. ADC Results Memory Configuration Register (ADBNDCR) Field Descriptions
Bit
Field
31-25
Reserved
24-16
BNDA
Value
0
Description
Reads return zeros, writes have no effect.
Buffer Boundary A. These bits determine the memory available for the Event Group conversion
results. The memory available is specified in terms of pairs of result buffers.
Any operation mode read/write:
0
0-1FFh
15-9
Reserved
8-0
BNDB
0
Event Group conversions are not required. If Event Group conversions are performed with the
BNDA value of zero, then the Event Group memory size will default to 1024 words. For proper
usage of the ADC results memory, configure the BNDA value to be non-zero and lower than the
BNDB value.
A total of (2 × BNDA) buffers are available in the ADC results memory for storing Event Group
conversion results.
Reads return zeros, writes have no effect.
Buffer Boundary B. These bits specify the number of buffers allocated for the Event Group plus
the number of buffers allocated for the Group1. The number of buffer pairs allocated for storing
Group1 conversion results can be determined by subtracting BNDA from BNDB. As a result,
BNDB must always be specified as greater than or equal to BNDA.
Any operation mode read/write:
0
0-1FFh
756
Event Group as well as Group1 conversions are not required.
A total of 2 × (BNDB - BNDA) buffers are available in the ADC results memory for storing
Group1 conversion results.
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19.11.24 ADC Results Memory Size Configuration Register (ADBNDEND)
ADC Results Memory Size Configuration Register (ADBNDEND) is shown in Figure 19-44 and described
in Table 19-29.
Figure 19-44. ADC Results Memory Size Configuration Register (ADBNDEND) [offset = 5Ch]
31
17
16
Reserved
BUF_INIT_ACTIVE
R-0
R-0
15
3
2
0
Reserved
BNDEND
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-29. ADC Results Memory Size Configuration Register (ADBNDEND) Field Descriptions
Bit
31-17
16
Field
Reserved
Value
0
BUF_INIT_ACTIVE
Description
Reads return zeros, writes have no effect.
ADC Results Memory Auto-initialization Status.
Any operation mode read/write:
15-3
Reserved
2-0
BNDEND
0
ADC Results Memory is currently not being initialized, and the ADC is available. If this bit is
read as 0 after triggering an auto-initialization of the ADC results memory, then the ADC
results memory has been completely initialized to zeros. For devices requiring parity
checking on the ADC results memory, the parity bit in the results memory will also be
initialized according to the parity polarity. The parity polarity as well as the auto-initialization
process is controlled by the System module. Please refer to Chapter 2 for more details.
1
ADC results memory is being initialized, and the ADC is not available for conversion.
0
Reads return zeros, writes have no effect.
Buffer Boundary End. These bits specify the total number of memory buffers available for
storing the ADC conversion results. These bits should be programmed to match the number
of ADC conversion result buffers required to be used for the application.
Any operation mode read/write:
0
16 words available for storing ADC conversion results.
1h
32 words available for storing ADC conversion results.
2h
64 words available for storing ADC conversion results. This is the maximum configuration
allowed since the device supports 64 buffers each for ADC1 as well as ADC2.
4h-7h
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Reserved. These combinations must not be used.
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19.11.25 ADC Event Group Sampling Time Configuration Register (ADEVSAMP)
ADC Event Group Sampling Time Configuration Register (ADEVSAMP) is shown in Figure 19-45 and
described in Table 19-30.
Figure 19-45. ADC Event Group Sampling Time Configuration Register (ADEVSAMP) [offset = 60h]
31
12
11
0
Reserved
EV_ACQ
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-30. ADC Event Group Sampling Time Configuration Register (ADEVSAMP)
Field Descriptions
Bit
Field
31-12
Reserved
11-0
EV_ACQ
Value
0
Description
Reads return zeros, writes have no effect.
Event Group Acquisition Time. These bits define the sampling window (SW) for the Event Group
conversions.
SW = EV_ACQ + 2 in terms of ADCLK cycles.
There are two factors that determine the minimum sampling window value required:
First, the ADC module design requires that SW >= 3 ADCLK cycles.
Second, the ADC input impedance necessitates a certain minimum sampling time. This needs to be
guaranteed by configuring the EV_ACQ value properly considering the frequency of the ADCLK
signal. Please refer to the device datasheet to determine the minimum sampling time for this
device.
19.11.26 ADC Group1 Sampling Time Configuration Register (ADG1SAMP)
ADC Group1 Sampling Time Configuration Register (ADG1SAMP) is shown in Figure 19-46 and
described in Table 19-31.
Figure 19-46. ADC Group1 Sampling Time Configuration Register (ADG1SAMP) [offset = 64h]
31
12
11
0
Reserved
G1_ACQ
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-31. ADC Group1 Sampling Time Configuration Register (ADG1SAMP)
Field Descriptions
Bit
Field
31-12
Reserved
11-0
G1_ACQ
Value
0
Description
Reads return zeros, writes have no effect.
Group1 Acquisition Time. These bits define the sampling window (SW) for the Group1 conversions.
SW = G1_ACQ + 2 in terms of ADCLK cycles.
There are two factors that determine the minimum sampling window value required:
First, the ADC module design requires that SW >= 3 ADCLK cycles.
Second, the ADC input impedance necessitates a certain minimum sampling time. This needs to be
guaranteed by configuring the G1_ACQ value properly considering the frequency of the ADCLK
signal. Please refer to the device datasheet to determine the minimum sampling time for this
device.
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19.11.27 ADC Group2 Sampling Time Configuration Register (ADG2SAMP)
ADC Group2 Sampling Time Configuration Register (ADG2SAMP) is shown in Figure 19-47 and
described in Table 19-32.
Figure 19-47. ADC Group2 Sampling Time Configuration Register (ADG2SAMP) [offset = 68h]
31
12
11
0
Reserved
G2_ACQ
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-32. ADC Group2 Sampling Time Configuration Register (ADG2SAMP)
Field Descriptions
Bit
Field
31-12
Reserved
11-0
G2_ACQ
Value
0
Description
Reads return zeros, writes have no effect.
Group2 Acquisition Time. These bits define the sampling window (SW) for the Group2 conversions.
SW = G2_ACQ + 2 in terms of ADCLK cycles.
There are two factors that determine the minimum sampling window value required:
First, the ADC module design requires that SW >= 3 ADCLK cycles.
Second, the ADC input impedance necessitates a certain minimum sampling time. This needs to be
guaranteed by configuring the G2_ACQ value properly considering the frequency of the ADCLK
signal. Please refer to the device datasheet to determine the minimum sampling time for this
device.
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19.11.28 ADC Event Group Status Register (ADEVSR)
ADC Event Group Status Register (ADEVSR) is shown in Figure 19-48 and described in Table 19-33.
Figure 19-48. ADC Event Group Status Register (ADEVSR) [offset = 6Ch]
31
8
Reserved
R-0
7
3
2
1
0
Reserved
4
EV_MEM_
EMPTY
EV_BUSY
EV_STOP
EV_END
R-0
R-1
R-0
R-0
R/W1C-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-33. ADC Event Group Status Register (ADEVSR) Field Descriptions
Bit
31-4
3
Field
Reserved
Value
0
EV_MEM_EMPTY
Description
Reads return zeros, writes have no effect.
Event Group Results Memory Empty. This bit can be effectively used only when the conversion
results are read out of the Event Group results memory in the "read from FIFO" mode.
Any operation mode read:
2
0
The Event Group results memory has valid conversion results.
1
The Event Group results memory is empty, or does not contain any unread conversion results.
EV_BUSY
Event Group Conversion Busy.
Any operation mode read:
1
0
Event Group conversions are neither in progress nor frozen.
1
Event Group conversions are either in progress, or are frozen for servicing some other group.
This bit will always be set when the Event Group is configured to be in the continuous
conversion mode.
EV_STOP
Event Group Conversion Stopped.
Any operation mode read:
0
0
Event Group conversions are not currently frozen.
1
Event Group conversions are currently frozen.
EV_END
Event Group Conversions Ended.
Any operation mode read:
0
Event Group conversions have either not been started or have not yet completed since the last
time this status bit was cleared.
1
The conversion for all the channels selected in the Event Group has completed. This bit can be
cleared under the following conditions:
• By reading a conversion result from the Event Group results memory in the "read from FIFO"
mode.
• By writing a new value to the Event Group channel select register (ADEVSEL).
• By writing a 1 to this bit.
• By disabling the ADC module by clearing the ADC_EN bit in the ADC operating mode control
register (ADOPMODECR).
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19.11.29 ADC Group1 Status Register (ADG1SR)
ADC Group1 Status Register (ADG1SR) is shown in Figure 19-49 and described in Table 19-34.
Figure 19-49. ADC Group1 Status Register (ADG1SR) [offset = 70h]
31
8
Reserved
R-0
7
3
2
1
0
Reserved
4
G1_MEM_
EMPTY
G1_BUSY
G1_STOP
G1_END
R-0
R-1
R-0
R-0
R/W1C-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-34. ADC Group1 Status Register (ADG1SR) Field Descriptions
Bit
31-4
3
Field
Reserved
Value
0
G1_MEM_EMPTY
Description
Reads return zeros, writes have no effect.
Group1 Results Memory Empty. This bit can be effectively used only when the conversion
results are read out of the Group1 results memory in the "read from FIFO" mode.
Any operation mode read:
2
0
The Group1 results memory has valid conversion results.
1
The Group1 results memory is empty, or does not contain any unread conversion results.
G1_BUSY
Group1 Conversion Busy.
Any operation mode read:
1
0
Group1 conversions are neither in progress nor frozen.
1
Group1 conversions are either in progress, or are frozen for servicing some other group. This
bit will always be set when the Group1 is configured to be in the continuous conversion mode.
G1_STOP
Group1 Conversion Stopped.
Any operation mode read:
0
0
Group1 conversions are not currently frozen.
1
Group1 conversions are currently frozen.
G1_END
Group1 Conversions Ended.
Any operation mode read:
0
Group1 conversions have either not been started or have not yet completed since the last time
this status bit was cleared.
1
The conversion for all the channels selected in the Group1 has completed. This bit can be
cleared under the following conditions:
• By reading a conversion result from the Group1 results memory in the "read from FIFO"
mode.
• By writing a new value to the Group1 channel select register (ADG1SEL).
• By writing a 1 to this bit.
• By disabling the ADC module by clearing the ADC_EN bit in the ADC operating mode control
register (ADOPMODECR).
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19.11.30 ADC Group2 Status Register (ADG2SR)
ADC Group2 Status Register (ADG2SR) is shown in Figure 19-50 and described in Table 19-35.
Figure 19-50. ADC Group2 Status Register (ADG2SR) [offset = 74h]
31
8
Reserved
R-0
7
3
2
1
0
Reserved
4
G2_MEM_
EMPTY
G2_BUSY
G2_STOP
G2_END
R-0
R-1
R-0
R-0
R/W1C-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-35. ADC Group2 Status Register (ADG2SR) Field Descriptions
Bit
31-4
3
Field
Reserved
Value
0
G2_MEM_EMPTY
Description
Reads return zeros, writes have no effect.
Group2 Results Memory Empty. This bit can be effectively used only when the conversion
results are read out of the Group2 results memory in the "read from FIFO" mode.
Any operation mode read:
2
0
The Group2 results memory has valid conversion results.
1
The Group2 results memory is empty, or does not contain any unread conversion results.
G2_BUSY
Group2 Conversion Busy.
Any operation mode read:
1
0
Group2 conversions are neither in progress nor frozen.
1
Group2 conversions are either in progress, or are frozen for servicing some other group. This
bit will always be set when the Group2 is configured to be in the continuous conversion mode.
G2_STOP
Group2 Conversion Stopped.
Any operation mode read:
0
0
Group2 conversions are not currently frozen.
1
Group2 conversions are currently frozen.
G2_END
Group2 Conversions Ended.
Any operation mode read:
0
Group2 conversions have either not been started or have not yet completed since the last time
this status bit was cleared.
1
The conversion for all the channels selected in the Group2 has completed. This bit can be
cleared under the following conditions:
• By reading a conversion result from the Group2 results memory in the "read from FIFO"
mode.
• By writing a new value to the Group2 channel select register (ADG2SEL).
• By writing a 1 to this bit.
• By disabling the ADC module by clearing the ADC_EN bit in the ADC operating mode control
register (ADOPMODECR).
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19.11.31 ADC Event Group Channel Select Register (ADEVSEL)
ADC Event Group Channel Select Register (ADEVSEL) is shown in Figure 19-51 and described in
Table 19-36.
NOTE: Clearing ADEVSEL During a Conversion
Writing 0x0000 to ADEVSEL stops the Event Group conversions. This does not cause the
ADC Event Group results Memory pointer or the Event Group Threshold Register to be
reset.
NOTE: Writing A Non-Zero Value To ADEVSEL During a Conversion
Writing a new value to ADEVSEL while a Channel in Event Group is being converted results
in a new conversion sequence starting immediately with the highest priority channel in the
new ADEVSEL selection. This also causes the ADC Event Group Results Memory pointer to
be reset so that the memory allocated for storing the Event Group conversion results gets
overwritten. Care should be taken to re-program the corresponding Interrupt Threshold
Counter or DMA Threshold Counter again so that correct number of conversions happen
before a Threshold interrupt or Block DMA request is generated.
ADC1 supports up to 24 channels and ADC2 supports up to 16 channels on the microcontroller.
Figure 19-51. ADC Event Group Channel Select Register (ADEVSEL) [offset = 78h]
31
24
23
0
Reserved
EV_SEL
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-36. ADC Event Group Channel Select Register (ADEVSEL) Field Descriptions
Bit
Field
31-24
Reserved
23-0
EV_SEL
Value
0
Description
Reads return zeros, writes have no effect.
Event Group channels selected.
Any operation mode read/write:
0
Non-zero
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No ADC input channel is selected for conversion in the Event Group.
The channels marked by the bit positions that are set to ‘1’ will be converted in ascending
order when the Event Group is triggered.
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19.11.32 ADC Group1 Channel Select Register (ADG1SEL)
ADC Group1 Channel Select Register (ADG1SEL) is shown in Figure 19-52 and described in Table 19-37.
NOTE: Clearing ADG1SEL During a Conversion
Writing 0x0000 to ADG1SEL stops the Group1 conversions. This does not cause the ADC
Group1 Results Memory pointer or the Group1 Threshold Register to be reset.
NOTE: Writing A Non-Zero Value To ADG1SEL During a Conversion
Writing a new value to ADG1SEL while a Channel in Group1 is being converted results in a
new conversion sequence starting immediately with the highest priority channel in the new
ADG1SEL selection. This also causes the ADC Group1 Results Memory pointer to be reset
so that the memory allocated for storing the Group1 conversion results gets overwritten.
Care should be taken to re-program the corresponding Interrupt Threshold Counter or DMA
Threshold Counter again so that correct number of conversions happen before a Threshold
interrupt or Block DMA request is generated.
ADC1 supports up to 24 channels and ADC2 supports up to 16 channels on the microcontroller.
Figure 19-52. ADC Group1 Channel Select Register (ADG1SEL) [offset = 7Ch]
31
24
23
0
Reserved
G1_SEL
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-37. ADC Group1 Channel Select Register (ADG1SEL) Field Descriptions
Bit
Field
31-24
Reserved
23-0
G1_SEL
Value
0
Description
Reads return zeros, writes have no effect.
Group1 channels selected.
Any operation mode read/write:
0
Non-zero
764
No ADC input channel is selected for conversion in the Group1.
The channels marked by the bit positions that are set to ‘1’ will be converted in ascending
order when the Group1 is triggered.
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19.11.33 ADC Group2 Channel Select Register (ADG2SEL)
ADC Group2 Channel Select Register (ADG2SEL) is shown in Figure 19-53 and described in Table 19-38.
NOTE: Clearing ADG2SEL During a Conversion
Writing 0x0000 to ADG2SEL stops the Group2 conversions. This does not cause the ADC
Group2 Results Memory pointer or the Group2 Threshold Register to be reset.
NOTE: Writing A Non-Zero Value To ADG2SEL During a Conversion
Writing a new value to ADG2SEL while a Channel in Group2 is being converted results in a
new conversion sequence starting immediately with the highest priority channel in the new
ADG2SEL selection. This also causes the ADC Group2 Results Memory pointer to be reset
so that the memory allocated for storing the Group2 conversion results gets overwritten.
Care should be taken to re-program the corresponding Interrupt Threshold Counter or DMA
Threshold Counter again so that correct number of conversions happen before a Threshold
interrupt or Block DMA request is generated.
ADC1 supports up to 24 channels and ADC2 supports up to 16 channels on the microcontroller.
Figure 19-53. ADC Group2 Channel Select Register (ADG2SEL) [offset = 80h]
31
24
23
0
Reserved
G2_SEL
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-38. ADC Group2 Channel Select Register (ADG2SEL) Field Descriptions
Bit
Field
31-24
Reserved
23-0
G2_SEL
Value
0
Description
Reads return zeros, writes have no effect.
Group2 channels selected.
Any operation mode read/write:
0
Non-zero
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No ADC input channel is selected for conversion in the Group2.
The channels marked by the bit positions that are set to ‘1’ will be converted in ascending
order when the Group2 is triggered.
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19.11.34 ADC Calibration and Error Offset Correction Register (ADCALR)
ADC Calibration and Error Offset Correction Register (ADCALR) is shown in Figure 19-54 and Figure 1955, and described in Table 19-39. As shown, the format of the ADCALR is different based on whether the
ADC module is configured to be a 12-bit or a 10-bit ADC module.
Figure 19-54. 12-bit ADC Calibration and Error Offset Correction Register (ADCALR) [offset = 84h]
31
12
11
0
Reserved
ADCALR
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 19-55. 10-bit ADC Calibration and Error Offset Correction Register (ADCALR) [offset = 84h]
31
10
9
0
Reserved
ADCALR
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-39. ADC Calibration and Error Offset Correction Register (ADCALR) Field Descriptions
Field
Value
Reserved
0
ADCALR
Description
Reads return zeros, writes have no effect.
ADC Calibration Result and Offset Error Correction Value.
The actual size of the ADCALR field is 12 bits or 10 bits depending on whether the ADC is configured to be
in 12-bit or 10-bit resolution mode, respectively. Bits 11-10 are reserved when the module is configured as
a 10- bit ADC module.
The ADC module writes the results of the calibration conversions to this register. The application is
required to use these conversion results and determine the ADC offset error. The application can then
compute the correction for the offset error and this correction value needs to be written back to the
ADCALR register in the 2's complement form.
During normal conversion (when calibration is disabled), the ADCALR register contents are automatically
added to each digital output from the ADC core before it is stored in the ADC results memory. For more
details on error calibration, please refer to Section 19.8.1.
19.11.35 ADC State Machine Status Register (ADSMSTATE)
Figure 19-56 and Table 19-40 describe the ADSMSTATE register.
Figure 19-56. ADC State Machine Status Register (ADSMSTATE) [offset = 88h]
31
4
3
0
Reserved
SMSTATE
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-40. ADC State Machine Status Register (ADSMSTATE) Field Descriptions
Bit
Field
31-4
Reserved
3-0
SMSTATE
Value
0
Description
Reads return zeros, writes have no effect.
ADC State Machine Current State.
These bits reflect the current state of the state machine and are reserved for use by TI for debug
purposes.
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19.11.36 ADC Channel Last Conversion Value Register (ADLASTCONV)
ADC Channel Last Conversion Value Register (ADLASTCONV) is shown in Figure 19-57 and described in
Table 19-41.
Figure 19-57. ADC Channel Last Conversion Value Register (ADLASTCONV) [offset = 8Ch]
31
24
23
0
Reserved
LAST_CONV
R-0
R-U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -U = value after reset is unknown
Table 19-41. ADC Channel Last Conversion Value Register (ADLASTCONV) Field Descriptions
Bit
Field
31-24
Reserved
23-0
LAST_CONV
Value
0
Description
Reads return zeros, writes have no effect.
ADC Input Channel's Last Converted Value.
This register indicates whether the last converted value for a particular input channel was lower or
higher than the mid-point of the reference voltage. In other words, this register acts as a digital
input register and can be read by the application to determine the digital level at the input pins.
This data is only valid for an input channel if it has been converted at least once.
Any operation mode read for each bit of this register:
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0
A level lower than the midpoint reference voltage was measured at the last conversion for this
channel.
1
A level higher than or equal to the midpoint reference voltage was measured at the last conversion
for this channel.
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19.11.37 ADC Event Group Results' FIFO Register (ADEVBUFFER)
ADC Event Group Results' FIFO Register (ADEVBUFFER) is shown in Figure 19-58 and Figure 19-59,
and described in Table 19-42. As shown, the format of the data read from the ADEVBUFFER locations is
different based on whether the ADC module is configured to be a 12-bit or a 10-bit ADC module.
Figure 19-58. 12-bit ADC Event Group Results' FIFO Register (ADEVBUFFER)
[offset = 90h-AFh]
31
30
21
20
16
EV_EMPTY
Reserved
EV_CHID
R-1
R-0
R-0
15
12
11
0
Reserved
EV_DR
R-0
R-U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -U = value after reset is unknown
Figure 19-59. 10-bit ADC Event Group Results' FIFO Register (ADEVBUFFER)
[offset = 90h-AFh]
31
16
Reserved
R-0
15
14
10
9
0
EV_EMPTY
EV_CHID
EV_DR
R-1
R-0
R-U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -U = value after reset is unknown
Table 19-42. ADC Event Group Results' FIFO Register (ADEVBUFFER) Field Descriptions
Field
Value
Reserved
0
EV_EMPTY
Description
Reads return zeros, writes have no effect.
Event Group FIFO Empty. This bit is applicable only when the "read from FIFO" mode is used for reading
the Event Group conversion results.
Any operation mode read:
0
The data in the EV_DR field of this buffer is valid.
1
The data in the EV_DR field of this buffer is not valid and there are no valid data in the Event Group results
memory.
EV_CHID
Event Group Channel Id. These bits are also applicable only when the "read from FIFO" mode is used for
reading the Event Group conversion results.
Any operation mode read:
EV_DR
0
The conversion result in the EV_DR field of this buffer is from the ADC input channel 0, or the channel id
mode is disabled in the Event Group operating mode control register (ADEVMODECR).
1h-1Fh
The conversion result in the EV_DR field of this buffer is from the ADC input channel number denoted by
the EV_CHID field.
Event Group Digital Conversion Result.
The Event Group results’ FIFO location is aliased eight times, so that any word-aligned read from the
address range 0x90 to 0xAF results in one conversion result to be read from the Event Group results’
memory. This allows the ARM LDMIA instruction to read out up to 8 conversion results from the Event
Group results’ memory with just one instruction.
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19.11.38 ADC Group1 Results FIFO Register (ADG1BUFFER)
ADC Group1 Results FIFO Register (ADG1BUFFER) is shown in Figure 19-60 and Figure 19-61,
described in Table 19-43. As shown, the format of the data read from the ADG1BUFFER locations is
different based on whether the ADC module is configured to be a 12-bit or a 10-bit ADC module.
Figure 19-60. 12-bit ADC Group1 Results FIFO Register (ADG1BUFFER)
[offset = B0h-CFh]
31
30
21
20
16
G1_EMPTY
Reserved
G1_CHID
R-1
R-0
R-0
15
12
11
0
Reserved
G1_DR
R-0
R-U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -U = value after reset is unknown
Figure 19-61. 10-bit ADC Group1 Results' FIFO Register (ADG1BUFFER)
[offset = B0h-CFh]
31
16
Reserved
R-0
15
14
10
9
0
G1_EMPTY
G1_CHID
G1_DR
R-1
R-0
R-U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -U = value after reset is unknown
Table 19-43. ADC Group1 Results FIFO Register (ADG1BUFFER) Field Descriptions
Field
Reserved
Value
0
G1_EMPTY
Description
Reads return zeros, writes have no effect.
Group1 FIFO Empty. This bit is applicable only when the "read from FIFO" mode is used for reading the
Group1 conversion results.
Any operation mode read:
0
The data in the G1_DR field of this buffer is valid.
1
The data in the G1_DR field of this buffer is not valid and there are no valid data in the Group1 results
memory.
G1_CHID
Group1 Channel Id. These bits are also applicable only when the "read from FIFO" mode is used for
reading the Group1 conversion results.
Any operation mode read:
0
The conversion result in the G1_DR field of this buffer is from the ADC input channel 0, or the channel id
mode is disabled in the Group1 operating mode control register (ADG1MODECR).
1h-1Fh
The conversion result in the G1_DR field of this buffer is from the ADC input channel number denoted by
the G1_CHID field.
G1_DR
Group1 Digital Conversion Result.
The Group1 results’ FIFO location is aliased eight times, so that any word-aligned read from the address
range 0xB0 to 0xCF results in one conversion result to be read from the Group1 results’ memory. This
allows the ARM LDMIA instruction to read out up to 8 conversion results from the Group1 results’ memory
with just one instruction.
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19.11.39 ADC Group2 Results FIFO Register (ADG2BUFFER)
ADC Group2 Results FIFO Register (ADG2BUFFER) is shown in Figure 19-62 and Figure 19-63,
described in Table 19-44. As shown, the format of the data read from the ADG2BUFFER locations is
different based on whether the ADC module is configured to be a 12-bit or a 10-bit ADC module.
Figure 19-62. 12-bit ADC Group2 Results FIFO Register (ADG2BUFFER)
[offset = D0h-EFh]
31
30
21
20
16
G2_EMPTY
Reserved
G2_CHID
R-1
R-0
R-0
15
12
11
0
Reserved
G2_DR
R-0
R-U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -U = value after reset is unknown
Figure 19-63. 10-bit ADC Group2 Results' FIFO Register (ADG2BUFFER)
[offset = D0h-EFh]
31
16
Reserved
R-0
15
14
10
9
0
G2_EMPTY
G2_CHID
G2_DR
R-1
R-0
R-U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -U = value after reset is unknown
Table 19-44. ADC Group2 Results FIFO Register (ADG2BUFFER) Field Descriptions
Field
Value
Reserved
0
G2_EMPTY
Description
Reads return zeros, writes have no effect.
Group2 FIFO Empty. This bit is applicable only when the "read from FIFO" mode is used for reading the
Group2 conversion results.
Any operation mode read:
0
The data in the G2_DR field of this buffer is valid.
1
The data in the G2_DR field of this buffer is not valid and there are no valid data in the Group2 results
memory.
G2_CHID
Group2 Channel Id. These bits are also applicable only when the "read from FIFO" mode is used for
reading the Group2 conversion results.
Any operation mode read:
G2_DR
0
The conversion result in the G2_DR field of this buffer is from the ADC input channel 0, or the channel id
mode is disabled in the Group2 operating mode control register (ADG2MODECR).
1h-1Fh
The conversion result in the G2_DR field of this buffer is from the ADC input channel number denoted by
the G2_CHID field.
Group2 Digital Conversion Result.
The Group2 results’ FIFO location is aliased eight times, so that any word-aligned read from the address
range 0xD0 to 0xEF results in one conversion result to be read from the Group2 results’ memory. This
allows the ARM LDMIA instruction to read out up to 8 conversion results from the Group2 results’ memory
with just one instruction.
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19.11.40 ADC Event Group Results Emulation FIFO Register (ADEVEMUBUFFER)
ADC Event Group Results Emulation FIFO Register (ADEVEMUBUFFER) is shown in Figure 19-64 and
Figure 19-65, and described in Table 19-45. As shown, the format of the data read from the
ADEVEMUBUFFER locations is different based on whether the ADC module is configured to be a 12-bit
or a 10-bit ADC module.
A read from this location also gives out one conversion result from the Event Group results’ memory along
with the EV_EMPTY status bit and the optional channel id. However, this read will not affect any of the
status flags in the Event Group interrupt flag register or the Event Group status register. This register is
useful for debuggers.
Figure 19-64. 12-bit ADC Event Group Results Emulation FIFO Register (ADEVEMUBUFFER)
[offset = F0h]
31
30
21
20
16
EV_EMPTY
Reserved
EV_CHID
R-1
R-0
R-0
15
12
11
0
Reserved
EV_DR
R-0
R-U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -U = value after reset is unknown
Figure 19-65. 10-bit ADC Event Group Results Emulation FIFO Register (ADEVEMUBUFFER)
[offset = F0h]
31
16
Reserved
R-0
15
14
10
9
0
EV_EMPTY
EV_CHID
EV_DR
R-1
R-0
R-U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -U = value after reset is unknown
Table 19-45. ADC Event Group Results Emulation FIFO Register (ADEVEMUBUFFER)
Field Descriptions
Field
Reserved
Value
0
EV_EMPTY
Description
Reads return zeros, writes have no effect.
Event Group FIFO Empty. This bit is applicable only when the "read from FIFO" mode is used for reading
the Event Group conversion results.
Any operation mode read:
0
The data in the EV_DR field of this buffer is valid.
1
The data in the EV_DR field of this buffer is not valid and there are no valid data in the Event Group results
memory.
EV_CHID
Event Group Channel Id. These bits are also applicable only when the "read from FIFO" mode is used for
reading the Event Group conversion results.
Any operation mode read:
0
The conversion result in the EV_DR field of this buffer is from the ADC input channel 0, or the channel id
mode is disabled in the Event Group operating mode control register (ADEVMODECR).
1h-1Fh
The conversion result in the EV_DR field of this buffer is from the ADC input channel number denoted by
the EV_CHID field.
EV_DR
Event Group Digital Conversion Result.
These bits contain the digital result output from the Event Group FIFO buffer. The result can be presented
in an 8-bit, 10-bit, or 12-bit format for a 12-bit ADC module, or in an 8-bit or 10-bit format for a 10-bit ADC
module. The conversion result data is automatically shifted right by the appropriate number of bits when
using a reduced-size data format with the upper bits reading as zeros.
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19.11.41 ADC Group1 Results Emulation FIFO Register (ADG1EMUBUFFER)
ADC Group1 Results Emulation FIFO Register (ADG1EMUBUFFER) is shown in Figure 19-66 and
Figure 19-67, described in Table 19-46. As shown, the format of the data read from the
ADG1EMUBUFFER locations is different based on whether the ADC module is configured to be a 12-bit
or a 10-bit ADC module.
A read from this location also gives out one conversion result from the Group1 results’ memory along with
the G1_EMPTY status bit and the optional channel id. However, this read will not affect any of the status
flags in the Group1 interrupt flag register or the Group1 status register. This register is useful for
debuggers.
Figure 19-66. 12-bit ADC Group1 Results Emulation FIFO Register (ADG1EMUBUFFER)
[offset = F4h]
31
30
21
20
16
G1_EMPTY
Reserved
G1_CHID
R-1
R-0
R-0
15
12
11
0
Reserved
G1_DR
R-0
R-U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -U = value after reset is unknown
Figure 19-67. 10-bit ADC Group1 Results Emulation FIFO Register (ADG1EMUBUFFER)
[offset = F4h]
31
16
Reserved
R-0
15
14
10
9
0
G1_EMPTY
G1_CHID
G1_DR
R-1
R-0
R-U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -U = value after reset is unknown
Table 19-46. ADC Group1 Results Emulation FIFO Register (ADG1EMUBUFFER) Field Descriptions
Field
Value
Reserved
0
G1_EMPTY
Description
Reads return zeros, writes have no effect.
Group1 FIFO Empty. This bit is applicable only when the "read from FIFO" mode is used for reading the
Group1 conversion results.
Any operation mode read:
0
The data in the G1_DR field of this buffer is valid.
1
The data in the G1_DR field of this buffer is not valid and there are no valid data in the Group1 results
memory.
G1_CHID
Group1 Channel Id. These bits are also applicable only when the "read from FIFO" mode is used for
reading the Group1 conversion results.
Any operation mode read:
G1_DR
0
The conversion result in the G1_DR field of this buffer is from the ADC input channel 0, or the channel id
mode is disabled in the Group1 operating mode control register (ADG1MODECR).
1h-1Fh
The conversion result in the G1_DR field of this buffer is from the ADC input channel number denoted by
the G1_CHID field.
Group1 Digital Conversion Result.
These bits contain the digital result output from the Group 1 FIFO buffer. The result can be presented in an
8-bit, 10-bit, or 12-bit format for a 12-bit ADC module, or in an 8-bit or 10-bit format for a 10-bit ADC
module. The conversion result data is automatically shifted right by the appropriate number of bits when
using a reduced-size data format with the upper bits reading as zeros.
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19.11.42 ADC Group2 Results Emulation FIFO Register (ADG2EMUBUFFER)
ADC Group2 Results Emulation FIFO Register (ADG2EMUBUFFER) is shown in Figure 19-68 and
Figure 19-69, described in Table 19-47. As shown, the format of the data read from the
ADG2EMUBUFFER locations is different based on whether the ADC module is configured to be a 12-bit
or a 10-bit ADC module.
A read from this location also gives out one conversion result from the Group2 results’ memory along with
the G2_EMPTY status bit and the optional channel id. However, this read will not affect any of the status
flags in the Group2 interrupt flag register or the Group2 status register. This register is useful for
debuggers.
Figure 19-68. 12-bit ADC Group2 Results Emulation FIFO Register (ADG2EMUBUFFER)
[offset = F8h]
31
30
21
20
16
G2_EMPTY
Reserved
G2_CHID
R-1
R-0
R-0
15
12
11
0
Reserved
G2_DR
R-0
R-U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -U = value after reset is unknown
Figure 19-69. 10-bit ADC Group2 Results Emulation FIFO Register (ADG2EMUBUFFER)
[offset = F8h]
31
16
Reserved
R-0
15
14
10
9
0
G2_EMPTY
G2_CHID
G2_DR
R-1
R-0
R-U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -U = value after reset is unknown
Table 19-47. ADC Group2 Results Emulation FIFO Register (ADG2EMUBUFFER) Field Descriptions
Field
Reserved
Value
0
G2_EMPTY
Description
Reads return zeros, writes have no effect.
Group2 FIFO Empty. This bit is applicable only when the "read from FIFO" mode is used for reading the
Group2 conversion results.
Any operation mode read:
0
The data in the G2_DR field of this buffer is valid.
1
The data in the G2_DR field of this buffer is not valid and there are no valid data in the Group2 results
memory.
G2_CHID
Group2 Channel Id. These bits are also applicable only when the "read from FIFO" mode is used for
reading the Group2 conversion results.
Any operation mode read:
0
The conversion result in the G2_DR field of this buffer is from the ADC input channel 0, or the channel id
mode is disabled in the Group2 operating mode control register (ADG2MODECR).
1h-1Fh
The conversion result in the G2_DR field of this buffer is from the ADC input channel number denoted by
the G2_CHID field.
G2_DR
Group2 Digital Conversion Result.
These bits contain the digital result output from the Group 2 FIFO buffer. The result can be presented in an
8-bit, 10-bit, or 12-bit format for a 12-bit ADC module, or in an 8-bit or 10-bit format for a 10-bit ADC
module. The conversion result data is automatically shifted right by the appropriate number of bits when
using a reduced-size data format with the upper bits reading as zeros.
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19.11.43 ADC ADEVT Pin Direction Control Register (ADEVTDIR)
ADC ADEVT Pin Direction Control Register (ADEVTDIR) is shown in Figure 19-70 and described in
Table 19-48.
Figure 19-70. ADC ADEVT Pin Direction Control Register (ADEVTDIR) [offset = FCh]
31
1
0
Reserved
ADEVT_DIR
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-48. ADC ADEVT Pin Direction Control Register (ADEVTDIR) Field Descriptions
Bit
31-1
0
Field
Reserved
Value
0
ADEVT_DIR
Description
Reads return zeros, writes have no effect.
ADEVT Pin Direction.
Any operating mode read/write:
774
0
ADEVT is an input pin; the output buffer is disabled.
1
ADEVT is an output pin; the output buffer is enabled.
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19.11.44 ADC ADEVT Pin Output Value Control Register (ADEVTOUT)
ADC ADEVT Pin Output Value Control Register (ADEVTOUT) is shown in Figure 19-71 and described in
Table 19-49.
Figure 19-71. ADC ADEVT Pin Output Value Control Register (ADEVTOUT) [offset = 100h]
31
1
0
Reserved
ADEVT_OUT
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-49. ADC ADEVT Pin Output Value Control Register (ADEVTOUT) Field Descriptions
Bit
31-1
0
Field
Value
Reserved
0
ADEVT_OUT
Description
Reads return zeros, writes have no effect.
ADEVT Pin Output Value. This bit determines the logic level to be output to the ADEVT pin when
the pin is configured to be an output pin.
Any operating mode read/write:
0
Output logic LOW on the ADEVT pin.
1
Output logic HIGH on the ADEVT pin.
19.11.45 ADC ADEVT Pin Input Value Register (ADEVTIN)
ADC ADEVT Pin Input Value Register (ADEVTIN) is shown in Figure 19-72 and described in Table 19-50.
Figure 19-72. ADC ADEVT Pin Input Value Register (ADEVTIN) [offset = 104h]
31
1
0
Reserved
ADEVT_IN
R-0
R-U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -U = value after reset is unknown
Table 19-50. ADC ADEVT Pin Input Value Register (ADEVTIN) Field Descriptions
Bit
31-1
0
Field
Value
Reserved
0
ADEVT_IN
Description
Reads return zeros, writes have no effect.
ADEVT Pin Input Value. This is a read-only bit which reflects the logic level on the ADEVT pin.
Any operating mode read:
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Logic LOW present on the ADEVT pin.
1
Logic HIGH present on the ADEVT pin.
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19.11.46 ADC ADEVT Pin Set Register (ADEVTSET)
ADC ADEVT Pin Set Register (ADEVTSET) is shown in Figure 19-73 and described in Table 19-51.
Figure 19-73. ADC ADEVT Pin Set Register (ADEVTSET) [offset = 108h]
31
1
0
Reserved
ADEVT_SET
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-51. ADC ADEVT Pin Set Register (ADEVTSET) Field Descriptions
Bit
31-1
0
Field
Value
Reserved
0
ADEVT_SET
Description
Reads return zeros, writes have no effect.
ADEVT Pin Set. This bit drives the output of the ADEVT pin high. A read from this bit always
returns the current state of the ADEVT pin.
Any operating mode read/write:
0
Output value on the ADEVT pin is unchanged.
1
Output logic HIGH on the ADEVT pin, if the pin is configured to be an output pin.
19.11.47 ADC ADEVT Pin Clear Register (ADEVTCLR)
ADC ADEVT Pin Clear Register (ADEVTCLR) is shown in Figure 19-74 and described in Table 19-52.
Figure 19-74. ADC ADEVT Pin Clear Register (ADEVTCLR) [offset = 10Ch]
31
1
0
Reserved
ADEVT_CLR
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-52. ADC ADEVT Pin Clear Register (ADEVTCLR) Field Descriptions
Bit
31-1
0
Field
Reserved
Value
0
ADEVT_CLR
Description
Reads return zeros, writes have no effect.
ADEVT Pin Clear. A read from this bit always returns the current state of the ADEVT pin.
Any operating mode read/write:
776
0
Output value on the ADEVT pin is unchanged.
1
Output logic LOW on the ADEVT pin, if the pin is configured to be an output pin.
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19.11.48 ADC ADEVT Pin Open Drain Enable Register (ADEVTPDR)
ADC ADEVT Pin Open Drain Enable Register (ADEVTPDR) is shown in Figure 19-75 and described in
Table 19-53.
Figure 19-75. ADC ADEVT Pin Open Drain Enable Register (ADEVTPDR) [offset = 110h]
31
1
0
Reserved
ADEVT_PDR
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-53. ADC ADEVT Pin Open Drain Enable Register (ADEVTPDR) Field Descriptions
Bit
31-1
0
Field
Value
Reserved
0
ADEVT_PDR
Description
Reads return zeros, writes have no effect.
ADEVT Pin Open Drain Enable. This bit enables the open-drain capability for the ADEVT pin if it is
configured to be an output and a logic HIGH is being driven on to the pin.
Any operating mode read/write:
0
Output value on the ADEVT pin is logic HIGH.
1
The ADEVT pin is tristated.
19.11.49 ADC ADEVT Pin Pull Control Disable Register (ADEVTPDIS)
ADC ADEVT Pin Pull Control Disable Register (ADEVTPDIS) is shown in Figure 19-76 and described in
Table 19-54.
Figure 19-76. ADC ADEVT Pin Pull Control Disable Register (ADEVTPDIS) [offset = 114h]
31
1
0
Reserved
ADEVT_PDIS
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-54. ADC ADEVT Pin Pull Control Disable Register (ADEVTPDIS) Field Descriptions
Bit
31-1
0
Field
Value
Reserved
0
ADEVT_PDIS
Description
Reads return zeros, writes have no effect.
ADEVT Pin Pull Control Disable. This bit enables or disables the pull control on the ADEVT pin if it
is configured to be an input pin.
Any operating mode read/write:
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0
Pull on ADEVT pin is enabled.
1
Pull on ADEVT pin is disabled.
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19.11.50 ADC ADEVT Pin Pull Control Select Register (ADEVTPSEL)
ADC ADEVT Pin Pull Control Select Register (ADEVTPSEL) is shown in Figure 19-77 and described in
Table 19-55.
Figure 19-77. ADC ADEVT Pin Pull Control Select Register (ADEVTPSEL) [offset = 118h]
31
1
0
Reserved
ADEVT_PSEL
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-55. ADC ADEVT Pin Pull Control Select Register (ADEVTPSEL) Field Descriptions
Bit
31-1
0
Field
Value
Reserved
Description
0
Reads return zeros, writes have no effect.
ADEVT_PSEL
ADEVT Pin Pull Control Select. This bit selects a pull-down or pull-up on the ADEVT pin if it is
configured to be an input pin.
Any operating mode read/write:
0
Pull down is selected on ADEVT pin.
1
Pull up is selected on ADEVT pin.
19.11.51 ADC Event Group Sample Cap Discharge Control Register (ADEVSAMPDISEN)
ADC Event Group Sample Cap Discharge Control Register (ADEVSAMPDISEN) is shown in Figure 19-78
and described in Table 19-56.
Figure 19-78. ADC Event Group Sample Cap Discharge Control Register (ADEVSAMPDISEN)
[offset = 11Ch]
31
16
Reserved
R-0
15
8
7
1
0
EV_SAMP_DIS_CYC
Reserved
EV_SAMP_
DIS_EN
R/W-0
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-56. ADC Event Group Sample Cap Discharge Control Register (ADEVSAMPDISEN)
Field Descriptions
Bit
Field
31-16
Reserved
15-8
EV_SAMP_DIS_CYC
7-1
Reserved
0
Value
0
Description
Reads return zeros, writes have no effect.
Event Group sample cap discharge cycles. These bits specify the duration in terms of ADCLK
cycles for which the ADC internal sampling capacitor is allowed to discharge before sampling
the input channel voltage.
0
EV_SAMP_DIS_EN
Reads return zeros, writes have no effect.
Event Group sample cap discharge enable.
Any operation mode read/write:
778
0
Event Group sample cap discharge mode is disabled.
1
Event Group sample cap discharge mode is enabled. The ADC internal sampling capacitor is
connected to the V REFLO reference voltage for a duration specified by the EV_SAMP_DIS_CYC
field. After this discharge time has expired the selected ADC input channel is sampled and
converted normally based on the Event Group settings.
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19.11.52 ADC Group1 Sample Cap Discharge Control Register (ADG1SAMPDISEN)
ADC Group1 Sample Cap Discharge Control Register (ADG1SAMPDISEN) is shown in Figure 19-79 and
described in Table 19-57.
Figure 19-79. ADC Group1 Sample Cap Discharge Control Register (ADG1SAMPDISEN)
[offset = 120h]
31
16
Reserved
R-0
15
8
7
1
0
G1_SAMP_DIS_CYC
Reserved
G1_SAMP_
DIS_EN
R/W-0
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-57. ADC Group1 Sample Cap Discharge Control Register (ADG1SAMPDISEN)
Field Descriptions
Bit
Field
31-16
Reserved
15-8
G1_SAMP_DIS_CYC
7-1
Reserved
0
Value
0
Description
Reads return zeros, writes have no effect.
Group1 sample cap discharge cycles. These bits specify the duration in terms of ADCLK cycles
for which the ADC internal sampling capacitor is allowed to discharge before sampling the input
channel voltage.
0
G1_SAMP_DIS_EN
Reads return zeros, writes have no effect.
Group1 sample cap discharge enable.
Any operation mode read/write:
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0
Group1 sample cap discharge mode is disabled.
1
Group1 sample cap discharge mode is enabled. The ADC internal sampling capacitor is
connected to the VREFLO reference voltage for a duration specified by the G1_SAMP_DIS_CYC
field. After this discharge time has expired the selected ADC input channel is sampled and
converted normally based on the Group1 settings.
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19.11.53 ADC Group2 Sample Cap Discharge Control Register (ADG2SAMPDISEN)
ADC Group2 Sample Cap Discharge Control Register (ADG2SAMPDISEN) is shown in Figure 19-80 and
described in Table 19-58.
Figure 19-80. ADC Group2 Sample Cap Discharge Control Register (ADG2SAMPDISEN)
[offset = 124h]
31
16
Reserved
R-0
15
8
7
1
0
G2_SAMP_DIS_CYC
Reserved
G2_SAMP_
DIS_EN
R/W-0
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-58. ADC Group2 Sample Cap Discharge Control Register (ADG2SAMPDISEN)
Field Descriptions
Bit
Field
31-16
Reserved
15-8
G2_SAMP_DIS_CYC
7-1
Reserved
0
Value
0
Description
Reads return zeros, writes have no effect.
Group2 sample cap discharge cycles. These bits specify the duration in terms of ADCLK cycles
for which the ADC internal sampling capacitor is allowed to discharge before sampling the input
channel voltage.
0
G2_SAMP_DIS_EN
Reads return zeros, writes have no effect.
Group2 sample cap discharge enable.
Any operation mode read/write:
780
0
Group2 sample cap discharge mode is disabled.
1
Group2 sample cap discharge mode is enabled. The ADC internal sampling capacitor is
connected to the VREFLO reference voltage for a duration specified by the G2_SAMP_DIS_CYC
field. After this discharge time has expired the selected ADC input channel is sampled and
converted normally based on the Group2 settings.
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19.11.54 ADC Magnitude Compare Interrupt x Control Registers (ADMAGINTxCR)
ADC Magnitude Compare Interrupt x Control Registers (ADMAGINTxCR) are shown in Figure 19-81 and
Figure 19-82, and described in Table 19-59. As shown, the format of the ADMAGINTxCR is different
based on whether the ADC module is configured to be a 12-bit or a 10-bit ADC module. The ADC module
supports up to three magnitude compare interrupts. These registers are at offset addresses 128h, 130h,
and 138h.
Figure 19-81. 12-bit ADC Magnitude Compare Interrupt x Control Registers (ADMAGINTxCR)
[offset = 128h-138h]
31
28
27
16
Reserved
MAG_THRx
R-0
R/W-0
15
14
13
CHN_THR_
COMPx
CMP_GE_LTx
Reserved
COMP_CHIDx
R/W-0
R/W-0
R-0
R/W-0
7
12
5
8
4
0
Reserved
MAG_CHIDx
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 19-82. 10-bit ADC Magnitude Compare Interrupt x Control Registers (ADMAGINTxCR)
[offset = 128h-138h]
31
30
26
25
16
Rsvd
MAG_CHIDx
MAG_THRx
R-0
R/W-0
R/W-0
15
13
12
8
Reserved
COMP_CHIDx
R-0
R/W-0
7
1
0
Reserved
2
CHN_THR_
COMPx
CMP_GE_LTx
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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Table 19-59. ADC Magnitude Compare Interrupt x Control Registers (ADMAGINTxCR)
Field Descriptions
Field
Value
Reserved
0
Description
Reads return zeros, writes have no effect.
MAG_CHIDx
These bits specify the channel number from 0 to 31 for which the conversion result needs to be
monitored by the ADC.
MAG_THRx
These bits specify the 12-bit or 10-bit compare value that the ADC will use for the comparison with the
MAG_CHIDx channel's conversion result.
Reserved
0
COMP_CHIDx
Reserved
Reads return zeros, writes have no effect.
These bits specify the channel number from 0 to 31 whose last conversion result is compared with the
MAG_CHIDx channel's conversion result.
0
CHN_THR_COMPx
Reads return zeros, writes have no effect.
Channel OR Threshold comparison.
Any operation mode read/write:
0
The ADC module will compare the MAG_CHIDx channel's conversion result with the fixed threshold
value specified by the MAG_THRx field
1
The ADC module will compare the MAG_CHIDx channel's conversion result with the last conversion
result for the COMP_CHIDx channel.
Both the MAG_CHIDx and the COMP_CHIDx channel must have been converted at least once for the
ADC to perform the comparison.
CMP_GE_LTx
"Greater than or equal to" OR "Less than" comparison operator.
Any operation mode read/write:
782
0
The ADC module will check if the conversion result is lower than the reference value (fixed threshold
or COMP_CHIDx conversion result).
1
The ADC module will check if the conversion result is greater than or equal to the reference value
(fixed threshold or COMP_CHIDx conversion result).
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19.11.55 ADC Magnitude Compare Interrupt x Mask Register (ADMAGxMASK)
ADC Magnitude Compare Interrupt x Mask Register (ADMAGxMASK) is shown in Figure 19-83and
Figure 19-84, and described in Table 19-60. As shown, the format of the ADMAGxMASK is different
based on whether the ADC module is configured to be a 12-bit or a 10-bit ADC module. There are three
mask registers for the three magnitude compare interrupts. These registers are at offset addresses 12Ch,
134h, and 13Ch.
Figure 19-83. 12-bit ADC Magnitude Compare Interrupt x Mask Register (ADMAGxMASK)
[offset = 12Ch-13Ch]
31
12
11
0
Reserved
MAG_INTx_MASK
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 19-84. 10-bit ADC Magnitude Compare Interrupt x Mask Register (ADMAGxMASK)
[offset = 12Ch-13Ch]
31
10
9
0
Reserved
MAG_INTx_MASK
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-60. ADC Magnitude Compare Interrupt x Mask Register (ADMAGxMASK)
Field Descriptions
Field
Reserved
Value
0
MAG_INTx_MASK
Description
Reads return zeros, writes have no effect.
These bits specify the mask for the comparison in order to generate the magnitude compare interrupt # x.
Any operation mode read/write:
0
The ADC module will not mask the corresponding bit for the comparison.
1
The ADC module will mask the corresponding bit for the comparison.
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19.11.56 ADC Magnitude Compare Interrupt Enable Set Register (ADMAGINTENASET)
ADC Magnitude Compare Interrupt Enable Set Register (ADMAGINTENASET) is shown in Figure 19-85
and described in Table 19-61.
Figure 19-85. ADC Magnitude Compare Interrupt Enable Set Register (ADMAGINTENASET)
[offset = 158h]
31
3
2
0
Reserved
MAG_INT_ENA_SET
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-61. ADC Magnitude Compare Interrupt Enable Set Register (ADMAGINTENASET)
Field Descriptions
Bit
Field
31-3
Reserved
2-0
MAG_INT_ENA_SET
Value
0
Description
Reads return zeros, writes have no effect.
Each of these three bits, when set, enable the corresponding magnitude compare interrupt.
Any operation mode read/write for each bit:
0
The enable status of the corresponding magnitude compare interrupt is left unchanged.
1
The corresponding magnitude compare interrupt is enabled.
19.11.57 ADC Magnitude Compare Interrupt Enable Clear Register (ADMAGINTENACLR)
ADC Magnitude Compare Interrupt Enable Clear Register (ADMAGINTENACLR) is shown in Figure 19-86
and described in Table 19-62.
Figure 19-86. ADC Magnitude Compare Interrupt Enable Clear Register (ADMAGINTENACLR)
[offset = 15Ch]
31
3
2
0
Reserved
MAG_INT_ENA_CLR
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-62. ADC Magnitude Compare Interrupt Enable Clear Register (ADMAGINTENACLR)
Field Descriptions
Bit
Field
31-3
Reserved
2-0
MAG_INT_ENA_CLR
Value
0
Description
Reads return zeros, writes have no effect.
Each of these three bits, when set, enable the corresponding magnitude compare interrupt.
Any operation mode read/write for each bit:
784
0
The enable status of the corresponding magnitude compare interrupt is left unchanged.
1
The corresponding magnitude compare interrupt is disabled.
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19.11.58 ADC Magnitude Compare Interrupt Flag Register (ADMAGINTFLG)
ADC Magnitude Compare Interrupt Flag Register (ADMAGINTFLG) is shown in Figure 19-87 and
described in Table 19-63.
Figure 19-87. ADC Magnitude Compare Interrupt Flag Register (ADMAGINTFLG)
[offset = 160h]
31
3
2
0
Reserved
MAG_INT_FLG
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-63. ADC Magnitude Compare Interrupt Flag Register (ADMAGINTFLG)
Field Descriptions
Bit
Field
31-3
Reserved
2-0
MAG_INT_FLG
Value
0
Description
Reads return zeros, writes have no effect.
Magnitude Compare Interrupt Flags. These bits can be polled by the application to determine if the
magnitude compares have been evaluated as true. When a magnitude compare interrupt flag is set,
the corresponding magnitude compare interrupt will be generated if enabled.
Any operation mode, for each bit:
0
Read: The condition for the corresponding magnitude threshold interrupt was false.
Write: The corresponding flag is left unchanged.
1
Read: The condition for the corresponding magnitude threshold interrupt was true.
Write: The corresponding flag is cleared. The flag can also be cleared by reading from the
magnitude compare interrupt offset register.
19.11.59 ADC Magnitude Compare Interrupt Offset Register (ADMAGINTOFF)
ADC Magnitude Compare Interrupt Offset Register (ADMAGINTOFF) is shown in Figure 19-88 and
described in Table 19-64.
Figure 19-88. ADC Magnitude Compare Interrupt Offset Register (ADMAGINTOFF) [offset = 164h]
31
4
3
0
Reserved
MAG_INT_OFF
R-0
R/C-0
LEGEND: R/W = Read/Write; R = Read only;C = Clear; -n = value after reset
Table 19-64. ADC Magnitude Compare Interrupt Offset Register (ADMAGINTOFF) Field Descriptions
Bit
Field
31-4
Reserved
3-0
MAG_INT_OFF
Value
0
Description
Reads return zeros, writes have no effect.
Magnitude Compare Interrupt Offset. This field indexes the currently highest-priority magnitude
compare interrupt. Interrupt 1 has the highest priority and interrupt 3 has the lowest priority among
the magnitude compare interrupts.
Writes to these bits have no effect. A read from this register clears this register as well as the
corresponding magnitude compare interrupt flag in the ADMAGINTFLG register. However, a read
from this register in emulation mode does not affect this register or the interrupt status flags.
Any operation mode read:
0
No magnitude compare interrupt is pending.
1h
Magnitude compare interrupt # 1 is pending.
2h
Magnitude compare interrupt # 2 is pending.
3h
Magnitude compare interrupt # 3 is pending.
4h-Fh
Reserved. These combinations do not occur.
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19.11.60 ADC Event Group FIFO Reset Control Register (ADEVFIFORESETCR)
ADC Event Group FIFO Reset Control Register (ADEVFIFORESETCR) is shown in Figure 19-89 and
described in Table 19-65.
Figure 19-89. ADC Event Group FIFO Reset Control Register (ADEVFIFORESETCR) [offset = 168h]
31
1
0
Reserved
EV_FIFO_RESET
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-65. ADC Event Group FIFO Reset Control Register (ADEVFIFORESETCR)
Field Descriptions
Bit
31-1
0
Field
Reserved
Value
0
EV_FIFO_RESET
Description
Reads return zeros, writes have no effect.
ADC Event Group FIFO Reset. The application can set this bit in case of an overrun condition. This
allows the ADC module to overwrite the contents of the Event Group results memory starting from
the first location.
When this bit is set to 1, the ADC module resets its internal Event Group results memory pointers.
Then this bit automatically gets cleared, so that the ADC module allows the Event Group results
memory to be overwritten only once each time this bit is set to 1. As a result, the EV_FIFO_RESET
bit will always be read as a 0.
The EV_FIFO_RESET bit will only have the desired effect when the Event Group results memory is
in an overrun condition. It must be used when the data already available in the results memory can
be discarded.
If the application needs the Event Group memory to always be overwritten with the latest available
conversion results, then the OVR_EV_RAM_IGN bit in the Event Group operating mode control
register (ADEVMODECR) needs to be set to 1.
19.11.61 ADC Group1 FIFO Reset Control Register (ADG1FIFORESETCR)
ADC Group1 FIFO Reset Control Register (ADG1FIFORESETCR) is shown in Figure 19-90 and
described in Table 19-66.
Figure 19-90. ADC Group1 FIFO Reset Control Register (ADG1FIFORESETCR) [offset = 16Ch]
31
1
0
Reserved
G1_FIFO_RESET
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-66. ADC Group1 FIFO Reset Control Register (ADG1FIFORESETCR) Field Descriptions
Bit
31-1
0
Field
Reserved
G1_FIFO_RESET
Value
0
Description
Reads return zeros, writes have no effect.
ADC Group1 FIFO Reset. The application can set this bit in case of an overrun condition. This
allows the ADC module to overwrite the contents of the Group1 results memory starting from the
first location.
When this bit is set to 1, the ADC module resets its internal Group1 results memory pointers. Then
this bit automatically gets cleared, so that the ADC module allows the Group1 results memory to be
overwritten only once each time this bit is set to 1. As a result, the G1_FIFO_RESET bit will always
be read as a 0.
The G1_FIFO_RESET bit will only have the desired effect when the Group1 results memory is in an
overrun condition. It must be used when the data already available in the results memory can be
discarded.
If the application needs the Group1 memory to always be overwritten with the latest available
conversion results, then the OVR_G1_RAM_IGN bit in the Group1 operating mode control register
(ADG1MODECR) needs to be set to 1.
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19.11.62 ADC Group2 FIFO Reset Control Register (ADG2FIFORESETCR)
ADC Group2 FIFO Reset Control Register (ADG2FIFORESETCR) is shown in Figure 19-91 and
described in Table 19-67.
Figure 19-91. ADC Group2 FIFO Reset Control Register (ADG2FIFORESETCR) [offset = 170h]
31
1
0
Reserved
G2_FIFO_RESET
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-67. ADC Group2 FIFO Reset Control Register (ADG2FIFORESETCR) Field Descriptions
Bit
31-1
0
Field
Value
Reserved
0
G2_FIFO_RESET
Description
Reads return zeros, writes have no effect.
ADC Group2 FIFO Reset. The application can set this bit in case of an overrun condition. This
allows the ADC module to overwrite the contents of the Group2 results memory starting from the
first location.
When this bit is set to 1, the ADC module resets its internal Group2 results memory pointers. Then
this bit automatically gets cleared, so that the ADC module allows the Group2 results memory to be
overwritten only once each time this bit is set to 1. As a result, the G2_FIFO_RESET bit will always
be read as a 0.
The G2_FIFO_RESET bit will only have the desired effect when the Group2 results memory is in an
overrun condition. It must be used when the data already available in the results memory can be
discarded.
If the application needs the Group2 memory to always be overwritten with the latest available
conversion results, then the OVR_G2_RAM_IGN bit in the Group2 operating mode control register
(ADG2MODECR) needs to be set to 1.
19.11.63 ADC Event Group RAM Write Address Register (ADEVRAMWRADDR)
ADC Event Group RAM Write Address Register (ADEVRAMWRADDR) is shown in Figure 19-92 and
described in Table 19-68.
Figure 19-92. ADC Event Group RAM Write Address Register (ADEVRAMWRADDR) [offset = 174h]
31
9
8
0
Reserved
EV_RAM_ADDR
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-68. ADC Event Group RAM Write Address Register (ADEVRAMWRADDR)
Field Descriptions
Bit
Field
31-9
Reserved
8-0
EV_RAM_ADDR
Value
0
Description
Reads return zeros, writes have no effect.
Event Group results memory write pointer. This field shows the address of the location where the
next Event Group conversion result will be stored. This is specified in terms of the buffer number.
The application can read this register to determine the number of valid Event Group conversion
results available until that time.
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19.11.64 ADC Group1 RAM Write Address Register (ADG1RAMWRADDR)
ADC Group1 RAM Write Address Register (ADG1RAMWRADDR) is shown in Figure 19-93 and described
in Table 19-69.
Figure 19-93. ADC Group1 RAM Write Address Register (ADG1RAMWRADDR) [offset = 178h]
31
9
8
0
Reserved
G1_RAM_ADDR
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-69. ADC Group1 RAM Write Address Register (ADG1RAMWRADDR)
Field Descriptions
Bit
Field
31-9
Reserved
8-0
G1_RAM_ADDR
Value
0
Description
Reads return zeros, writes have no effect.
Group1 results memory write pointer. This field shows the address of the location where the next
Group1 conversion result will be stored. This is specified in terms of the buffer number.
The application can read this register to determine the number of valid Group1 conversion results
available until that time.
19.11.65 ADC Group2 RAM Write Address Register (ADG2RAMWRADDR)
ADC Group2 RAM Write Address Register (ADG2RAMWRADDR) is shown in Figure 19-94 and described
in Table 19-70.
Figure 19-94. ADC Group2 RAM Write Address Register (ADG2RAMWRADDR) [offset = 17Ch]
31
9
8
0
Reserved
G2_RAM_ADDR
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-70. ADC Group2 RAM Write Address Register (ADG2RAMWRADDR) Field Descriptions
Bit
Field
31-9
Reserved
8-0
G2_RAM_ADDR
Value
0
Description
Reads return zeros, writes have no effect.
Group2 results memory write pointer. This field shows the address of the location where the next
Group2 conversion result will be stored. This is specified in terms of the buffer number.
The application can read this register to determine the number of valid Group2 conversion results
available until that time.
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19.11.66 ADC Parity Control Register (ADPARCR)
ADC Parity Control Register (ADPARCR) is shown in Figure 19-95 and described in Table 19-71.
Figure 19-95. ADC Parity Control Register (ADPARCR) [offset = 180h]
31
16
Reserved
R-0
15
9
8
7
4
3
0
Reserved
TEST
Reserved
PARITY_ENA
R-0
R/WP-0
R-0
R/WP-5h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 19-71. ADC Parity Control Register (ADPARCR) Field Descriptions
Bit
31-9
8
Field
Value
Reserved
0
TEST
Description
Reads return zeros, writes have no effect.
This bit maps the parity bits into the ADC results' RAM frame so that the application can
access them.
Any operation mode read, privileged mode write:
7-4
Reserved
3-0
PARITY_ENA
0
The parity bits are not memory-mapped.
1
The parity bits are memory mapped.
0
Reads return zeros, writes have no effect.
Enable/disable parity checking. These bits enable/disable the parity check on read
operations and the parity calculation on write operations to the ADC results memory.
If parity checking is enabled and a parity error is detected the ADC module sends a parity
error signal to the System module.
Any operation mode read, privileged mode write:
5h
Parity check is disabled.
Any other
Parity check is enabled.
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19.11.67 ADC Parity Error Address Register (ADPARADDR)
ADC Parity Error Address Register (ADPARADDR) is shown inFigure 19-96 and described in Table 19-72.
Figure 19-96. ADC Parity Error Address Register (ADPARADDR) [offset = 184h]
31
16
Reserved
R-0
15
12
11
2
1
0
Reserved
ERROR_ADDRESS
Reserved
R-0
R-U
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -U = value after reset is unknown
Table 19-72. ADC Parity Error Address Register (ADPARADDR) Field Descriptions
Bit
Field
31-12
Reserved
11-2
ERROR_ADDRESS
1-0
Reserved
Value
0
Description
Reads return zeros, writes have no effect.
These bits hold the address of the first parity error generated in the ADC results' RAM. This
error address is frozen from being updated until it is read by the application. In emulation mode,
this address is maintained frozen even when read.
0
Reads return zeros, writes have no effect. Reading [11:0] provides the 32-bit aligned address.
19.11.68 ADC Power-Up Delay Control Register (ADPWRUPDLYCTRL)
Figure 19-97 and Table 19-73 describe the ADPWRDLYCTRL register.
Figure 19-97. ADC Power-Up Delay Control Register (ADPWRUPDLYCTRL) [offset = 188h]
31
10
9
Reserved
R-0
0
PWRUP_DLY
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-73. ADC Power-Up Delay Control Register (ADPWRUPDLYCTRL) Field Descriptions
Bit
31-10
9-0
790
Field
Reserved
PWRUP_DLY
Value
0
Description
Reads return zeros, writes have no effect.
This register defines the number of VCLK cycles that the ADC state machine has to wait after
releasing the ADC core from power down before starting a new conversion. Please refer to
Section 19.8.3 for more details.
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Chapter 20
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High-End Timer (N2HET) Module
This chapter provides a general description of the High-End Timer (N2HET). The N2HET is a softwarecontrolled timer with a dedicated specialized timer micromachine and a set of 30 instructions. The N2HET
micromachine is connected to a port of up to 32 input/output (I/O) pins.
NOTE: This chapter describes a superset implementation of the N2HET module that includes
features and functionality that require DMA. Since not all devices have DMA capability,
consult your device-specific datasheet to determine the applicability of these features and
functions to your device being used.
Topic
20.1
20.2
20.3
20.4
20.5
20.6
...........................................................................................................................
Overview .........................................................................................................
N2HET Functional Description ...........................................................................
Angle Functions ...............................................................................................
N2HET Control Registers ...................................................................................
HWAG Registers...............................................................................................
Instruction Set..................................................................................................
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20.1 Overview
The N2HET is a fifth-generation Texas Instruments (TI) advanced intelligent timer module. It provides an
enhanced feature set compared to previous generations.
This timer module provides sophisticated timing functions for real-time applications such as engine
management or motor control. The high resolution hardware channels allow greater accuracy for widely
used timing functions such as period and pulse measurements, output compare, and PWMs.
The reduced instruction set, based mostly on very simple, but comprehensive instructions, improves the
definition and development cycle time of an application and its derivatives. The N2HET breakpoint feature,
combined with various stop capabilities, makes the N2HET software application easy to debug.
20.1.1 Features
•
•
•
•
•
•
•
•
•
•
•
Programmable timer for input and output timing functions
Reduced instruction set (30 instructions) for dedicated time and angle functions
Up to maximum of 128 96-bit words of instruction RAM protected by parity. Check your datasheet for
the actual number of words implemented.
User defined configuration of 25-bit virtual counters for timer, event counters and angle counters
7-bit hardware counters for each pin allow up to 32-bit resolution in conjunction with the 25-bit virtual
counters
Up to 32 pins usable for input signal measurements or output signal generation
Programmable suppression filter for each input pin with adjustable suppression window
Low CPU overhead and interrupt load
Efficient data transfer to or from the CPU memory with dedicated High-End-Timer Transfer Unit (HTU)
or DMA
Diagnostic capabilities with different loopback mechanisms and pin status readback functionality
Hardware Angle Generator (HWAG)
20.1.2 Major Advantages
In addition to classic time functions such as input capture or multiple PWMs, higher-level time functions
can be easily implemented in the timer program main loop. Higher-level time functions include angle
driven wave forms, angle- and time-driven pulses, and input pulse width modulation (PWM) duty cycle
measurement.
Because of these high-level functions, data exchanges with the CPU are limited to the fundamental
parameters of the application (periods, pulse widths, angle values, etc.); and the real-time constraints for
parameter communication are dramatically minimized; for example, few interrupts are required and
asynchronous parameter updates are allowed.
The reduced instruction set and simple execution flow control make it simple and easy to develop and
modify programs. Simple algorithms can embed the entire flow control inside the N2HET program itself.
More complex algorithms can take advantage of the CPU access to the N2HET RAM. With this, the CPU
program can make calculations and can modify the timer program flow by changing the data and control
fields of the N2HET RAM. CPU access to the N2HET RAM also improves the debug and development of
timer programs. The CPU program can stop the N2HET and view the contents of the program, control,
and data fields that reside in the N2HET RAM.
Finally, the modular structure provides maximum flexibility to address a wide range of applications. The
timer resolution can be selected from two cascaded prescalers to adjust the loop resolution and HR
clocks. The 32 I/O pins can provide any combination of input, period or pulse capture, and output
compare, including high resolution for each channel.
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20.1.3 Block Diagram
The N2HET module (see Figure 20-1) comprises four separate components:
• Host interface
• N2HET RAM
• Specialized timer micromachine
• I/O control (the N2HET is attached to an I/O port of up to 32 pins)
Figure 20-1. N2HET Block Diagram
Peripheral bus
High Resolution
prescaler
HETPFR.5:0
Shadow Registers
Shadow Registers
HR clock
(to IO PIN
CONTROL)
Loop resolution
prescaler
HETPFR.10:8
Address Decode
HOST
INTERFACE
Slave
Master
HETGCR.16
internal multiN2HET sync
Control RAM
Program RAM
Data RAM
N2HET
RAM
CURRENT INSTRUCTION
PROGRAM FIELD
Ignore Suspend
CONTROL FIELD
DATA FIELD
OFF
Stop
ON
HETGCR.17
Register A
HETGCR.0
SPECIALIZED
TIMER
MICROMACHINE
Register B
Register R
Register S
Register T
HETADDR.8:0
To VIM
Priority 1
HETFLG. 31:0
HETOFF1.7:0
Compare
To VIM
32 ALU
Priority 2
HETOFF2.7:0
HETPRY.31:0
Rotate/
Shift by N
HETDIN.31:0
HET[31:0]
32
HETDSET.31:0
I/O
PIN
CONTROL
HETDOUT.31:0
HETDIR.31:0
HR clock
HETDCLR.31:0
HR block
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20.1.4 Timer Module Structure and Execution
The timer consists of a specialized micromachine that operates a reduced instruction set. Two 25-bit
registers and three 32-bit registers are available to manipulate information such as time, event counts, and
angle values. System performance is improved by a wide instruction format (96 bits) that allows the
N2HET to fetch the instructional operation code and data in one system cycle, thus increasing the speed
at which data can be processed. The typical operations performed in the ALU are additions (count),
compares, and magnitude compares (higher or same).
Each instruction is made up of a 32-bit program field, a 32-bit control field and a 32-bit data field. The
N2HET execution unit fetches the complete 96-bit instruction in one cycle and executes it. All instructions
include a 9-bit field for specifying the address of the next instruction to be executed. Some instructions
also include a 9-bit conditional address, which is used as the next address whenever a particular condition
is true. This makes controlling the flow of an N2HET program inexpensive; in many cases a separate
branch instruction is not required.
The interface to the host CPU is based on both communication memory and control registers. The
communication memory includes timer instructions (program and data). This memory is typically initialized
by the CPU or DMA after reset before the timer starts execution. Once the timer program is loaded into
the memory, the CPU starts the timer execution, and typically data parameters are then read or written
into the timer memory. The control registers include bits for selecting timer clock, configuring I/O pins, and
controlling the timer module.
The programmer implements timer functions by combining instructions in specific sequences. For
instance, a single count (CNT) instruction implements a timer. A simple PWM generator can be
implemented with a two instruction sequence: CNT and compare (ECMP or MCMP). A complex time
function may include many instructions in the sequence. The total timer program is a set of instructions
executed sequentially, one after the other. Reaching the end, the program must roll to the first instruction
so that it behaves as a loop. The time for a loop to execute is referred to as a loop resolution clock cycle
or loop resolution period (LRP). When the N2HET rolls over to the first instruction, the timer waits for the
loop resolution clock to restart the execution of the loop to ensure that only one loop is executed for each
loop resolution clock.
The longest path through an N2HET program must be completed within the loop resolution clock (LRP).
Otherwise, the program will execute unpredictably because some instructions will not be executed each
time through the loop. This effect creates a strong link between the accuracy of the timer functions and the
number of functions (the number of instructions) the timer can perform. High resolution (HR) hardware
timer extensions are available for each of the N2HET pins to help overcome this limitation.
The high resolution hardware timers operate from the high resolution clock, which may be configured for
frequency multiples between 2 and 128 times the loop resolution clock frequency. This extending the
resolution of timer events and measurements well beyond what is possible with only loop resolution
instructions.
Most of the commonly used N2HET instructions can operate either at loop resolution or high resolution;
with the restriction that for each pin at most one high resolution instruction can be executed per loop
resolution period.
Certain instructions (MOV32, ADM32, ...) can modify the data fields of other instructions. This feature
enables the N2HET program to implement double buffering on capture and compare functions. For
example, an ECMP compare instruction can be followed by a MOV32 instruction that is conditionally
executed when the ECMP instruction matches. The host CPU can update the next compare value by
writing asynchronously to the data field of the MOV32 instruction instead of writing directly to the data field
of the ECMP instruction. The copy from the buffer (MOV32 data field) to the compare register (ECMP data
field) will occur when the MOV32 instruction is actually executed which occurs after the ECMP instruction
matches its current compare value. This is the same behavior as one would expect from a double buffered
hardware compare register.
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Other instructions (MOV64, RADM64) can modify both the control and data fields of other instructions.
This allows the N2HET to implement toggle functionality. For example, an ECMP instruction can be
followed by a pair of MOV64 instructions. The MOV64 instruction updates the data field of the ECMP
instruction to implement the double buffering behavior. But it also updates the control field of the ECMP
instruction which allows it to change things like pin action and the conditional address. If one MOV64
instruction configures the ECMP pin action to SET while the second changes it to CLEAR, and the two
MOV64 instructions update the conditional address to point to each other, then a single ECMP instruction
can be used to toggle a pin each time the compare match occurs.
20.1.5 Performance
Most instructions execute in one cycle, but a few take two or three cycles.
The N2HET can generate many complex output waveforms without CPU interrupts. Where special
algorithms are needed following a specific event (for example, missing teeth or a short/long input signal), a
minimal number of interrupts to the CPU are needed freeing the CPU for other tasks.
20.1.6 N2HET Compared to NHET
N2HET enhancements from NHET include:
• Eight new instructions: ADD, ADC, SUB, SBB, AND, OR, XOR, RCNT
• Full set of ALU flags Carry (C), Negative (N), Zero (Z), Overflow (V)
• Branch instruction (BR) extended to support signed and unsigned arithmetic comparison conditions
• Two additional 32-bit temporary working registers R, S.
• New HETAND register for AND-Sharing of High Resolution structure between pairs of pins
• Improved high resolution PCNT instruction
20.1.7 NHET and N2HET Compared to HET
Compared to the HET module, the N2HET contains all of the enhancements described in Section 20.1.6
plus the following additional enhancements:
• New Interrupt Enable Set and Clear registers
• Capability to generate requests to the DMA module or the HET Transfer Unit (HTU) including new
Request Enable Set and Clear registers
• N2HET RAM parity error detection
• Suppression filters for each of the 32 I/O channel and control register to configure the limiting
frequency and counter clock
• Enhanced edge detection hardware that does not rely on the previous bit field in the control word of
the N2HET instruction.
• The next, conditional and remote addresses are extended from 8 to 9 bits
• The loop resolution data fields are extended from 20 to 25 bits
• The high resolution data fields are extended from 5 to 7 bits
• Instructions with an adequate condition are able to specify the number of the request line, which
triggers either the HET Transfer Unit (HTU) or the DMA module
• The CNT instruction provides a bit, which allows to configure either an equal comparison or a greater
or equal comparison when comparing the selected register value with the Max-value
• The MOV32 instruction provides a new bit. If set to one the MOV32 will only perform the move, when
the Z-flag is set. If set to zero the MOV32 will perform the move whenever it is executed (independent
on the state of the Z-flag)
• There is a new instruction WCAPE, which is a combination of a time stamp and an edge counter
• New Open Drain, Pull Disable, and Pull Select registers
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20.1.8 Instructions Features
The N2HET has the following instructions features:
• N2HET uses a RISC-based specialized timer micromachine to carry out a set of 30 instructions
• Instructions are implemented in a Very Long Instruction Word (VLIW) format (96-bits wide)
• The N2HET program execution is self-driven by external or internal events, branching to special
routines based on input edges or output compares
• Instructions point to the next instruction executed, eliminating the need for a program counter
• Several instructions can change the program flow based on internal or external conditions
20.1.9 Program Usage
The N2HET instructions/program can be assembled with the N2HET assembler. The assembler generates
a C-structure which can be included into the main application program. The application has to copy the
content of the structure into the N2HET RAM, set up necessary registers and start the N2HET program
execution. In addition to the C-structure, the assembler generates also a header file which makes it easy
for the main application to access the different instructions and change for example the duty cycle of a
PWM or read out the captured value of a specific signal edge.
20.2 N2HET Functional Description
The N2HET contains RAM into which N2HET code is loaded. The N2HET code is run by the specialized
timer micromachine. The host interface and I/O control provide an interface to the CPU and external pins
respectively.
20.2.1 Specialized Timer Micromachine
The N2HET has its own instruction set, detailed in Section 20.6.1. The timer micromachine reads each
instruction from the N2HET RAM. The program and control fields contain the instructions for how the
specialized timer micromachine executes the command. For most instructions, the data field stores the
information that needs to be manipulated.
The specialized timer micromachine executes the instructions stored in the N2HET RAM sequentially. The
N2HET program execution is self-driven by external or internal events. This means that input edges or
output compares may force the program to branch to special routines using a conditional address.
Figure 20-2 shows some of the major operations that the N2HET can carry out, namely compares,
captures, angle functions, additions, and shifts. The N2HET contains five registers (A, B, R, S, and T)
used to hold compare or counter values and are used by the N2HET instructions. Data may be taken from
the registers or the data field for manipulation; likewise, the data may be returned to the registers or the
data field.
20.2.1.1 Time Slots and Resolution Loop
Each instruction requires a specific number of cycles or time slots to execute. The resolution specified in
the prescaler bitfields determines the timer accuracy. All input captures, event counts, and output
compares are executed once in each resolution loop. HR captures and compares are possible (up to
N2HET clock accuracy) on the HR I/O pins. For more information about the HR I/O structure, see
Section 20.2.5.
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Figure 20-2. Specialized Timer Micromachine
From N2HET RAM
CURRENT INSTRUCTION
PROGRAM FIELD
Cont.
Off
Stop
On
DATA FIELD
CONTROL FIELD
Register A
HETGCR.0
HETGCR.17
Register B
Register R
Register S
Register T
HETADDR.8:0
Priority 1
HETFLG. 31:0
Priority 2
HETOFF1.7:0
HETOFF2.7:0
To VIM
To VIM
Compare
32 Bit ALU
HETPRY.31:0
Rotate/
Shift By N
Specialized timer micromachine
To I/O Control
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20.2.1.2 Program Loop Time
The program loop time is the sum of all cycles used for instruction execution. This time may vary from one
loop to another if the N2HET program includes conditionally executed instructions.
The timer program restarts on every resolution loop. The start address is fixed at N2HET RAM address
00h. The longest path through a program must fit within one loop resolution period to guarantee complete
accuracy.
The last instruction of a program must branch back to the fixed start address (next program address =
00h). When an N2HET program branches back to address 00h before the end of a loop resolution period,
the N2HET detects this and pauses instruction execution until the beginning of the next loop resolution
period.
The timing diagram in Figure 20-3 illustrates the program flow execution.
Figure 20-3. Program Flow Timings
Loop Resolution Period = LRP
Time slot
...
VCLK2
...
High Res.
clock
Loop Res.
clock
Instructions
Program loop
1
2 34
N
1
2 34
Next program address=00h
20.2.1.3 Instruction Execution Sequence
The execution of a N2HET program begins with the first occurrence of the loop resolution clock, after the
N2HET is turned on. At the first and subsequent occurrences of the loop resolution, the instruction at
location address 00h is prefetched. The program execution begins at the occurrence of the loop resolution
clock and continues executing the instructions until the program branches to 00h location. The instruction
is prefetched at location 00h and execution flag is reset. The N2HET pauses instruction execution until the
occurrence of the loop resolution clock and resumes normal execution.
N2HET programs must be written so that they complete execution and return to address 00h before the
occurrence of the next loop resolution clock. If the N2HET program exceeds this execution time limit, then
a program overflow condition occurs as described in Section 20.2.1.4.
20.2.1.4 Program Overflow Condition
If the number of time slots used in a program loop exceeds the number available time slots in one loop
resolution, the timer sets the program overflow interrupt flag located in the HETEXC2 register. To maintain
synchronization of the I/Os, this condition should never be allowed to occur in a normal operation. The
HETEXC2.PRGMOVRFLFLAG flag provides a mechanism for checking that the condition does not occur
during the debug and validation phases.
As Figure 20-4 illustrates, when a program overflow occurs, the currently executing N2HET program
sequence is interrupted and restarted at N2HETaddress 0 for the beginning of the next loop resolution
clock period. Also, HETEXC2.PRGMOVRFLFLAG is set.
If the instruction that caused the overflow (instruction at address 0xC in Figure 20-4) has any pin actions
selected, these pin actions will not be performed. However other actions of the instruction including
register and RAM updates will still be performed.
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Figure 20-4. Use of the Overflow Interrupt Flag (HETEXC2)
Loop Resolution clock
N2HET Program
Address
0 1 2 3 7 8 A B
0
1 2 3 7 8 9 A B C 0 1 2
Program Overflow
(HETEXC2
.PRGMOVRFLFLAG)
No Overflow.
Program returns to address 0
before start of next loop
Overflow.
Program did not return
to address 0 before start
of next loop.
20.2.1.5 Architectural Restrictions on N2HET Programs
Certain architectural restrictions apply to N2HET programs:
1. The size of an N2HET program must be greater than one instruction.
2. An extra wait state is incurred by any instruction that modifies a field in the next instruction to be
executed.
3. Only one instruction (using high resolution) is allowed per high resolution pin.
4. Consecutive break points are not supported. Instructions with break points must have at least a
distance of two instructions (for example, at addresses 1, 3, 5, 7, and so on, assuming the program
executes linearly)
NOTE: While it would be unusual to code an N2HET program that is only one instruction long, it is
trivial to modify such a program to meet the requirement of restriction 1. Simply add a
second instruction to the program, which may be a simple branch to zero.
To enforce restriction 3, the high resolution pin structures respond only to the first instruction
that is executed matching their pin number with hr_lr=HIGH, regardless of whether or not the
en_pin_action field is ON. Subsequent instructions are ignored by the high resolution pin
structure for the remainder of the loop resolution period.
20.2.1.6 Multi-Resolution Scheme
The N2HET has the capability to virtually extend the counter width by executing instructions only once
every N loop resolution periods. This decreases the timer resolution, but extends the counter range which
may be useful when generating or measuring slow signals. Figure 20-5 illustrates how a multi-resolution
scheme may be implemented in an N2HET program. An unconditional Branch instruction and an index
sequence, using a MOV64 instruction in each low resolution loop, is required to control this particular
program flow.
NOTE: HR instructions must be placed in the main (full resolution) loop to ensure proper operation.
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Figure 20-5. Multi-Resolution Operation Flow Example
Instructions with
full resolution
(2 Ps)
Branch on
conditional address
0
Instructions with
lower resolution
(6 Ps)
Change conditional
address
1
2
Instructions with
lower resolution
(6 Ps)
Change conditional
address
Instructions with
lower resolution
(6 Ps)
Change conditional
address
20.2.1.7 Debug Capability
The N2HET supports breakpoints to allow you to more easily debug your N2HET program. Figure 20-6
provides an illustration of the breakpoint mechanism.
The steps to enable an N2HET breakpoint are:
1. Make sure the device nTRST pin is high, since N2HET breakpoints are disabled whenever this pin is
low. (Normally this is handled automatically when a JTAG debugger is attached).
2. Attach a JTAG debugger and connect to the device that has been already programmed with the
N2HET code that needs to debugged. (downloading to on-chip flash is outside the scope of this
section).
3. Execute the CPU program at least until the point where the N2HET program RAM has been initialized
by the CPU.
4. Open a memory window in the N2HET registers.
5. Make sure HETEXC2.DEBUGSTATUSFLAG bit is cleared.
6. Open a memory window on the N2HET RAM
7. Set bit 22 in the program field of the instruction(s) on which you wish to break. Note that this instruction
will be executed before the N2HET is halted - slightly different from how CPU breakpoints behave.
8. Make sure the CPU and N2HET are running, if they are halted then restart the CPU through the JTAG
emulator (N2HET will start when the CPU starts).
9. Both the CPU and N2HET will halt when breakpoint is reached.
When the N2HET is halted, its state machines are frozen but all of the N2HET control registers can be
accessed through the JTAG emulator interface.
The current N2HET instruction address can be inspected by reading the HETADDR register; this should
be pointing to the instruction that caused the breakpoint.
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The N2HET internal working registers (A,B,R,S,T) are not directly visible through the JTAG emulator
interface. If the content of these registers needs to be inspected, it is best to add an instruction like
MOV32 which copies the register value to the N2HET RAM. This RAM location can be inspected when the
N2HET halts.
To
1.
2.
3.
restart execution of both the CPU and the N2HET from the halted state:
Clear HETEXC2.DEBUGSTATUSFLAG bit.
Clear bit 22 in the program field of the instruction on which the breakpoint was reached.
Restart the CPU through the normal JTAG emulator procedure (‘Run’ or ‘Go’). The N2HET will
automatically start executing when it sees that the CPU has exited the debug state.
Figure 20-6. Debug Control Configuration
Breakpoint bit (P22)
N2HET RAM
Device test
mode enable
(nTRST)
nTRST signal = 0: Functional mode
nTRST signal = 1: Test/Debug mode
Debug
mode
control
Debug request to CPU
Debug ack from CPU
Debug
status
bit
NOTE: Consecutive break points are not supported. Instructions with break points must have at
least a distance of two instructions (for example, at N2HET addresses 1, 3, 5, 7, and so on)
20.2.2 N2HET RAM Organization
The N2HET RAM is organized into two sections. The first contains the N2HET program itself. The second
contains parity protection bits for the N2HET program.
Each N2HET instruction is 96-bits wide but aligned to a 128-bit boundary. Instructions consist of three 32bit fields: Program, Control, and Data. Instructions are separated by a fourth unimplemented address to
force alignment to 128-bit boundaries.
The integrity of the N2HET program can be protected by Parity. Parity protection is enabled through the
N2HET Parity Control Register (HETPCR).
Table 20-1 shows the base addresses for N2HET RAM and N2HET Parity RAM.
Table 20-1. N2HET RAM Base Addresses
N2HET1 Base Address
N2HET2 Base Address
0xFF46_0000
0xFF44_0000
Memory
N2HET Instruction RAM (Program/Control/Data)
0xFF46_2000
0xFF44_2000
N2HET Parity RAM
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20.2.2.1 N2HET RAM Banking
Because the CPU must make updates to the N2HET RAM while the N2HET is executing, for example to
update the duty cycle value of a PWM, it is important to understand how the N2HET RAM organization
facilitates simultaneous accesses by both the HOST CPU and the N2HET.
The N2HET RAM is implemented as 4 banks of 96-bit wide two port RAM. This means that there a total of
8 ports available; four read and four write. Normally the N2HET will use up to two of these ports at a time.
One read port is used to allow the N2HET to prefetch the next N2HET instruction while a write port may
be used to update the data or control fields that have changed as a result of executing the current
instruction.
N2HET accesses to its own internal RAM are given priority over accesses from an external host (CPU or
DMA), this makes N2HET program execution deterministic which is a critical requirement for a timer.
Most N2HET instructions execute in a single cycle. Cases where a wait state impacts the N2HET program
execution time are:
• The current N2HET instruction writes data back to the next N2HET in the execution sequence.
• The external host reads from an N2HET instruction where the automatic read-clear option is set, while
the N2HET is executing from/on the same address (See Section 20.2.4.3).
Except for the case of automatic read-clear, the external host is stalled when the host and N2HET have a
bank conflict. However this will typically only result in a stall of one cycle, due to the N2HET bank ordering
which is organized on the N2HET Address least significant bit boundaries (See Table 20-2).
Assuming most of the N2HET program executes linearly through the N2HET Address space; if a bank
conflict does exist it is usually resolved in the next cycle as the N2HET program moves to the next bank.
N2HET programmers should avoid writing a program that accesses the same bank of N2HET RAM on
every cycle, as this could lock the external host out of the N2HET memory completely.
Table 20-2 describes the N2HET memory map, as viewed by the N2HET as well as from the memory
space of the host CPU and DMA.
Table 20-2. N2HET RAM Bank Structure
N2HET Address
Host CPU or DMA Address Space
Instruction
Program Field
Address
Control Field
Address
Data Field
Address
Reserved
Address
N2HET RAM
Bank
000h
XX0000h
XX0004h
XX0008h
XX000Ch
A
001h
XX0010h
XX0014h
XX0018h
XX001Ch
B
002h
XX0020h
XX0024h
XX0028h
XX002Ch
C
003h
XX0030h
XX0034h
XX0038h
XX003Ch
D
004h
XX0040h
XX0044h
XX0048h
XX004Ch
A
:
:
:
:
:
:
03Fh
XX03F0h
XX03F4h
XX03F8h
XX03FCh
D
040h
XX0400h
XX0404h
XX0408h
XX040Ch
A
:
:
:
:
:
:
1FFh
XX1FF0h
XX1FF4h
XX1FF8h
XX1FFCh
D
NOTE: The external host interface supports any access size for reads, but only 32-bit writes to the
N2HET RAM are supported. Reserved addresses should not be accessed, the result of
doing so is indeterminate.
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20.2.2.2 Parity Checking
The N2HET module can detect parity errors in N2HET RAM. As described in Section 20.2.2 the N2HET
allows 32-bit writes only. Therefore N2HET RAM parity checking is implemented using one parity bit per
32-bit field in N2HET RAM.
Even or odd parity selection for N2HET parity detection can be configured in the system module. Parity
calculation and checking can be enabled/disabled by a 4-bit key in HETPCR.
During a read access to the N2HET RAM, the parity is calculated based on the data read from the RAM
and compared with the good parity value stored in the parity bits. The parity check is performed when the
N2HET execution unit makes a read access to N2HET RAM, but also when a different master (for
example, CPU, HTU, DMA) performs the read access. If any 32-bit-word fails the parity check then an
error is signaled to the ESM module. The N2HET address, which generated the error is detected and is
captured in HETPAR for host system debugging. The address is frozen from being updated until it is read
by the bus master.
The N2HET execution unit reads the instructions, which are 96-bit wide. They contain the program-,
control- and data-field whereby each is 32-bit wide. So when fetching N2HET instructions parity checking
is performed on three words in parallel.
If a parity error is detected in two or more words in the same cycle then only one address (word at the
lower address) is captured. The captured N2HET address is always aligned to a 32-bit word boundary.
During debug, parity checking is still performed on accesses originating from the on-chip host CPU and
DMA. However, parity errors that are detected during an access initiated by the debugger itself are
ignored.
20.2.2.3 Parity Error Detection Actions
Detection of a N2HET parity error causes the following actions:
1. An error is signaled to the ESM module.
2. The Parity Address Register (HETPAR) is loaded with the address of the faulty N2HET field.
3. N2HET execution immediately stops. (The instruction that triggered the parity error is not executed.)
4. The Turn-On/Off-Bit in the N2HET Global Configuration Register (HETGCR) is automatically cleared.
5. All N2HET internal flags are cleared.
6. All N2HET pins selected by N2HET Parity Pin Register (HETPPR) enter a predefined safe state.
7. Register HETDOUT is also updated to reflect changes in pin state due to HETPPR.
The safe state for N2HET pins selected through the HETPPR register depends on how the pin is
configured in the HETDIR, HETPDR, and HETPSL registers. Table 20-3 explains how the safe state is
determined.
Table 20-3. Pin Safe State Upon Parity Error Detection
Safe State
HETDIR
HETPDR
HETPSL
Drive Low
1
0
0
Drive High
1
0
1
High Impedance
1
1
x
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20.2.2.4 Testing Parity Detection Logic
To test the parity detection logic, the parity RAM has to be made accessible to the CPU in order to allow a
diagnostic program to insert parity errors. The control register bit HETPCR.TEST must be set in order to
make the parity RAM accessible. Once HETPCR.TEST is set, the parity bits are accessible as described
in Table 20-4.
Each 32-bit N2HET field has its own parity bit in the N2HET Parity RAM as shown in Table 20-4. There
are no parity bits for the reserved fields, since there is no physical N2HET RAM for these fields.
Table 20-4. N2HET Parity Bit Mapping
Bits
Address
N2HET1
Address
N2HET2
[31:1]
[0]
0xFF46_2000
0xFF44_2000
Reads 0, Writes have no effect
Instruction 0 Program Field Parity Bit
0xFF46_2004
0xFF44_2004
Reads 0, Writes have no effect
Instruction 0 Control Field Parity Bit
0xFF46_2008
0xFF44_2008
Reads 0, Writes have no effect
Instruction 0 Data Field Parity Bit
0xFF46_200C
0xFF44_200C
Reads 0, Writes have no effect
Read 0
0xFF46_2010
0xFF44_2010
Reads 0, Writes have no effect
Instruction 1 Program Field Parity Bit
....
....
...
...
20.2.2.5 Initialization of Parity RAM
After device power up, the N2HET RAM contents including the parity bits cannot be guaranteed. In order
to avoid false parity failures due to the random state in which RAM powers up, the RAM has to be
initialized.
Before initializing the N2HET RAM, enable the N2HET parity logic by writing to HETPCR. Then the
N2HET Instruction RAM should be initialized. With parity enabled, the N2HET parity RAM will be initialized
automatically by N2HET at the same time that the N2HET instruction RAM is initialized by the CPU. Note
that loading the N2HET program with parity enabled is also effective.
Another possibility to initialize the N2HET memory and its parity bits is, to use the system module to start
the automatic initialization of all RAMs on the microcontroller. The RAMs will be initialized to ‘0’.
Depending on the even/odd parity selection, the parity bit will be calculated accordingly.
20.2.3 Time Base
All N2HET timings are derived from VCLK2 (see Figure 20-7). Internally N2HET instructions execute at
the VCLK2 rate; but the timer loop clock and the high-resolution hardware timer clock can be scaled down
from VCLK2. Two prescalers are available to adjust the timer loop resolution clock for the program loop,
and the high resolution (HR) clock for the HR I/O counters.
• Time Slots: The number of cycles available for instruction execution per loop. Time Slots is the
number of VCLK2 cycles in a Loop Resolution Clock.
• High Resolution Clock: The high resolution clock is the smallest time increment with which a pin can
change it’s state or can be measured in the case of input signals. A 6-bit prescaler dividing VCLK2 by
a user-defined HR prescale divide rate (hr) stored in the 6-bit HR prescale factor code (HETPFR). See
Table 20-5.
• Loop Resolution Clock: The loop resolution clock defines the timebase for executing all instructions
in a N2HET program. Since instructions can be conditionally executed, the longest path through the
N2HET program must fit into one loop resolution clock period (LRP).A 3-bit prescaler dividing the HR
clock by a user-defined loop-resolution prescale divide rate (lr) stored in the 3-bit loop-resolution
prescale factor code (HETPFR). See Table 20-5.
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Figure 20-7. Prescaler Configuration
HR
prescaler
(6 bits)
VCLK2
Loop resolution
prescaler
(3 bits)
Loop resolution
clock
HR
clock
The following abbreviations and relations are used in this document:
1. hr: high resolution prescale factor (1, 2, 3, 4,..., 63, 64)
2. lr: loop resolution prescale factor (1, 2, 4, 8, 16, 32, 64,128)
3. ts: Time slots (cycles) available for instruction execution per loop. ts = hr x lr
4. HRP = high resolution clock period HRP = hr × TVCLK2 (ns)
5. LRP = loop resolution clock period LRP = lr × HRP (ns)
The loop resolution period (LRP) must be selected to be larger than the number of Time slots (VCLK2
cycles) required to complete the worst-case execution path through the N2HET program. Otherwise a
program overflow condition may occur (see Section 20.2.1.4). Because of the relationship of time slots to
the hr and lr prescalers as described in item 3 above, increasing either hr or lr increases the number of
time slots available for program execution. However, lr would typically be increased first, since increasing
hr results in a decrease in timer resolution since it reduces the clock to the High Resolution IO structures.
The divide rates hr and lr can be defined in the HETPFR register. Table 20-5 lists the bit field encodings
for the prescale options.
Table 20-5. Prescale Factor Register Encoding
LRPFC - Loop Resolution
HRPFC - High Resolution
HETPFR[10:8]
Prescale Factor lr
HETPFR[5:0]
Prescale Factor hr
000
/1
000000
/1
001
/2
000001
/2
010
/4
000010
/3
011
/8
000011
/4
100
/16
:
:
101
/32
111101
/62
110
/64
111110
/63
111
/128
111111
/64
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20.2.3.1 Determining Loop Resolution
As an example, consider an application that requires high resolution of HRP = 62.5 ns, and loop resolution
of LRP = 8 μs, and needs at least 250 time slots for the N2HET application program.
Assuming VCLK2 = 32 MHz, the following shows which divide-by rates and which value in the Prescale
Factor Register (HETPFR) is required for the above requirements:
2
hr
hr = 2
HRP = -------------------= ------------------ = 62.5ns
VCLK2 32MHz
lr =128
lr x HRP = 128 x 62.5ns = 8 μs
ts = hr x lr = 2 x 128 = 256
hr = 2, lr = 128
HETPFR[31:0] = 0x00000701
(29)
In the example above, if the loop resolution period needs to decrease from 8 μs to 4 μs, then only 128
time slots will be available for program execution. The program may need to be restructured as suggested
in Section 20.2.1.6.
20.2.3.2 The 7-Bit HR Data Field
The instruction execution examples of ECMP (Section 20.2.5.9), MCMP (Section 20.2.5.10), PCNT
(Section 20.2.5.12), PWCNT (Section 20.2.5.11), and WCAP (Section 20.2.5.13) show that the 7-bit HR
data field can generate or measure high resolution delays (HR delay) relative to the start of an LRP within
one N2HET loop LRP. The last section showed that:
LRP = lr × HRP
There are lr high resolution clock periods (HRP) within the N2HET loop resolution clock period (LRP). If lr
= 128 then the HR delay can range from 0 to127 HRP clocks within LRP and all 7 bits of the HR data field
are needed. Instead of being limited to measuring and triggering events based on the loop resolution clock
period (LRP) the HR extension allows measurements and events to be described in terms fractions of an
LRP (down to 1/128 of an LRP). The only limitation is that a maximum of one HR delay can be specified
per pin during each loop resolution period.
Table 20-6 shows which bits of the HR data field are not used by the high resolution IO structures if lr is
less than 128. In this case the non-relevant bits (LSBs) of the HR data fields will be one of the following:
• Written as 0 for HR capture (for PCNT, WCAP)
• Or interpreted as 0 for HR compare (for ECMP, MCMP. PWCNT)
Table 20-6. Interpretation of the 7-Bit HR Data Field
Loop Resolution
Prescale divide rate (lr)
Bits of the HR data field
D[6]
D[5]
D[4]
1
(1)
806
D[3]
(1)
D[2]
D[1]
D[0]
XXXXXXX
2
1/2
4
1/2
1/4
HRP Cycles delay range
0
XXXXXX
0 to 1
XXXXX
0 to 3
8
1/2
1/4
1/8
16
1/2
1/4
1/8
1/16
XXXX
0 to 7
32
1/2
1/4
1/8
1/16
1/32
64
1/2
1/4
1/8
1/16
1/32
1/64
X
0 to 63
128
1/2
1/4
1/8
1/16
1/32
1/64
1/128
0 to 127
XXX
0 to 15
XX
0 to 31
X = Non-relevant bit (treated as '0')
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20.2.3.2.1 Example:
Prescale Factor Register (HETPFR) = 0x0300
—> lr = 8 —> LRP = 8 × HRP
Assumption: HR data field = 0x50 = 1010000b
lr = 8 —> Bits D[3:0] are ignored —> HR delay = 101b = 5 HRPs
or by using the calculation with weight factors:
HR Delay
= lr · (D[6] · 1/2 + D[5] · 1/4 + D[4] · 1/8 + D[3] · 1/16 + D[2] · 1/32 + D[1] · 1/64 + D[0] · 1/128)
= 8 · (1 · 1/2 + 0 · 1/4 + 1 · 1/8 + 0 · 1/16 + 0 · 1/32 + 0 · 1/64 + 0 · 1/128)
= 5 HRPs
20.2.4 Host Interface
The host interface controls all communications between timer-RAM and masters accessing the N2HET
RAM. It includes following components:
20.2.4.1 Host Accesses to N2HET RAM
The host interface supports the following types of accesses to N2HET RAM:
• Read accesses of 8, 16, or 32 bits
• Read accesses of 64-bits that follow the shadow register sequence described in Section 20.2.4.2.
• Write accesses of 32 bits
Writes of 8 or 16 bits to N2HET RAM by an external host are not supported.
20.2.4.2 64-bit Read Access
The consecutive read of a control field CF(n) and a data field DF(n) of the same instruction (n) performed
by the same master (for example, CPU, DMA, or any other master) is always done as a simultaneous 64bit read access. This means that at the same time CF(n) is read, DF(n) is loaded in a shadow register. So
the second access will read DF(n) from the shadow register instead of the N2HET RAM.
In general a 64-bit read access of one master could be interrupted by a 64-bit read access of another
master. A total of three shadow registers are available. Therefore up to three masters can perform 64-bit
reads in an interleaved manner (Master1 CF, Master2 CF, Master3 CF, Master1 DF, Master2 DF, Master3
DF).
If all three shadow registers are activated and a 4th master performs a CF or DF read it will result in an
address error and the RAM access will not happen. Other access types by a fourth master (reads from the
PF field or writes to any of the fields) will occur because these access types do not require an available
shadow register resource to complete.
20.2.4.3 Automatic Read Clear Feature
The N2HET provides a feature allowing to automatically clear the data field immediately after the data field
is read by the external host CPU (or DMA). This feature is implemented via the control bit, which is
located in the control field (bit C26). This is a static bit that can be used by any instruction, and specified in
the N2HET program by adding the option (control = ON) to the N2HET instruction. The automatic read
clear feature works for both 32 and 64 bit reads that follow the sequence described in Section 20.2.4.2.
When the host CPU reads the data field of that instruction, the current data value is returned to the host
CPU but the field is cleared automatically as a side effect of the read. In case the master reads data from
an instruction currently executing, any new capture result is stored and this takes priority over the
automatic read clear feature, so that the new capture result is not lost.
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As an example of where the automatic read clear feature is useful, consider the PCNT instruction. If this
instruction is configured for automatic read clear, then when the host CPU reads the PCNT data field it will
be cleared automatically. The host CPU can then poll the PCNT data field again, and as long as the field
returns a value of zero the host CPU program knows a new capture event has not occurred. If the data
field were not cleared, it would be impossible for the host CPU to determine whether the data field holds
data from the previous capture event, or if it happens to be data from a new capture event with the same
value.
20.2.4.4 Emulation Mode
Emulation mode, used by the software debugger, is specified in the global configuration register. When
the host CPU debugger hits a breakpoint, the CPU sends a suspend signal to the modules. Two modes of
operation are provided: suspend and ignore suspend.
• Suspend
When a suspend is issued, the timer operation stops at the end of the current timer instruction. However,
the CPU accesses to the timer RAM or control registers are freely executed.
• Ignore suspend
The timer RAM ignores the suspend signal and operates real time as normal.
20.2.4.5 Power-Down
After setting the turn-off bit in the Global Configuration Register (HETGCR), it is required to delay until the
end of the timer program loop before putting the N2HET in power-down mode. This can be done by
waiting until the N2HET Current Address (HETADDR) becomes zero, before disabling the N2HET clock
source in the device’s Global Clock Module (GCM).
20.2.5 I/O Control
The N2HET has up to 32 pins. Refer to device specific data sheets for information concerning the number
of N2HETIO available. All of the N2HET pins available are programmable as either inputs or outputs.
These 32 I/Os have an identical structure connected to pins HET[31] to HET[0]. See Figure 20-8 for an
illustration of the I/O control. In addition all 32 I/Os have a special HR structure based on the HR clock.
This structure allows any N2HET instruction to use any of these I/Os with an accuracy of either loop
resolution or high resolution accuracy.
Figure 20-8. I/O Control
HETDIN
Timer data in
Loop
Resolution
Clock
HET[x]
HETDSET
Timer data out
HETDOUT
HETDCLR
HETDIR
High Resolution
Structure
Pins N2HET [31] to N2HET [0] can be used by the CPU as general-purpose inputs or outputs using the
N2HET Data Input Register (HETDIN) for reading and N2HET Data Output Register (HETDOUT), N2HET
Data Set Register (HETDSET) or N2HET Data Clear Register (HETDCLR) for writing, depending on the
type of action to perform. The N2HET pins used as general-purpose inputs are sampled on each VCLK2
period.
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20.2.5.1 Using General-Purpose I/O Data Set and Clear Registers
The N2HET Data Clear Register (HETDCLR) and N2HET Data Set Register (HETDSET) can be used to
minimize the number of accesses to the peripheral to modify the output register and output pins. When the
application needs to set or to reset some N2HET pins without changing the value of the others pins, the
first possibility is to read N2HET Data Output Register (HETDOUT), modify the content (AND, OR, and so
on), and write the result into N2HET Data Output Register (HETDOUT). However, this read-modify-write
sequence could be interrupted by a different function modifying the same register which will result in a
data coherency problem.
Using the N2HET Data Set Register (HETDSET) or N2HET Data Clear Register (HETDCLR), the
application program must write the mask value (same mask value for the first option) to the register to set
or reset the desired pins. Any bits written as 0 to HETDSET and HETDCLR are left unchanged, which
avoids the possible coherency problem of the read-modify-write approach.
Coding Example (C program): Set pins using the 2 methods.
unsigned
volatile
...
*HETDOUT
*HETDSET
int MASK;
unsigned int *HETDOUT,*HETDSET;
/* Variable that content the bit mask
/* Pointer to HET registers
*/
*/
= *HETDOUT | MASK;
= MASK;
/* Read-modify-write of HETDOUT
*/
/* Set the pin without reading HETDOUT */
20.2.5.2 Loop Resolution Structure
The N2HET uses the pins N2HET [31:0] as input and/or output by the way of the instruction set. Actually,
each pin could monitor the N2HET program or could be monitored by the N2HET program. By using the
I/O register of the N2HET, the CPU is able to interact with the N2HET program flow.
When an action (set or reset) is taken on a pin by the N2HET program, the N2HET will modify the pin at
the rising edge of the next loop resolution clock.
When an event occurs on a N2HET I/O pin, it is taken into account at the next rising edge of the loop
resolution clock.
The structure of each pin is shown in Figure 20-9.
Figure 20-9. N2HET Loop Resolution Structure for Each Bit
HETDIN
Timer data in
Loop
Resolution
Clock
HET[x]
HETDSET
Timer data out
HETDOUT
HETDCLR
HETDIR
The example in Figure 20-10 shows a simple PWM generation with loop resolution accuracy. The
corresponding program is:
HETPFR[31:0] register = 0x201 --> lr=4 and hr=2 --> ts = 8
N2HET Program:
L00
L01
CNT
ECMP
{ next= L01, reg=A, irq=OFF, max = 4 }
{ next= L00, cond_addr= L00, hr_lr=LOW, en_pin_action=ON, pin=0,
action=PULSEHI, reg=A, irq=OFF, data= 1, hr_data = 0x0 }
; 25 bit compare value is 1 and the 7-bit HR compare value is 0
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The CNT and ECMP instructions are executed once each loop resolution cycle. When the CNT instruction
is executed, the specified register (A) and the CNT instruction data field are both incremented by one.
Next the ECMP is executed and the data field of the ECMP is compared with the specified register (A). If
both values match, then the pin action (PULSEHI in this case) will be performed in the next loop resolution
cycle. The CNT continues incrementing each loop resolution cycle. When the data field overflows (max +
1), then the Z-flag is set by the CNT instruction. In the next loop resolution cycle, the Z-flag is evaluated
and the opposite pin action is performed if it is set. The Z-flag will only be active for one loop resolution
cycle.
Figure 20-10. Loop Resolution Instruction Execution Example
LRP
VCLK2
HR Clock
HRP
LR Clock
Instruction
0 1
0 1
0 1
0 1
0 1
0 1
0 1
Counter
4 0
1
2
3
4
0
1
Pin HET[0]
Z-Flag
25-bit ECMP
match
Pin action in next
loop resolution cycle
CNT resets
Sets Z-Flag
Opposite Pin action in
next loop resolution
cycle
20.2.5.3 High Resolution Structure
All 32 I/Os provide the HR structure based on the HR clock. The HR clock frequency is programmed
through the Prescale Factor Register (HETPFR). In addition to the standard I/O structure, all pins have HR
hardware so that these pins can be used as HR input captures (using the HR instructions PCNT or
WCAP) or HR output compares (using the HR instructions ECMP, MCMP, or PWCNT).
All five HR instructions (PCNT, WCAP, ECMP, MCMP, and PWCNT) have a dedicated hr_lr bit (high
resolution/low resolution; program field bit 8) allowing operation either in HR mode or in standard
resolution mode by ignoring the HR field. By default, the hr_lr bit value is 0 which implies HR operation
mode. However, setting this bit to one allows the use of several HR instructions on a single HR pin. Only
one instruction is allowed to operate in HR mode (bit cleared to 0), but the other instructions can be used
in standard resolution mode (bit set to 1).
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20.2.5.4 HR Block Diagram
Each time an HR instruction is executed on a given pin, the HR structure for that pin is programmed and
synchronized to the next loop-resolution cycle (which HR function to perform and on which edges it should
take an action) with the information given by the instruction. The HR structure for each pin decodes the
pin select field of the instruction and programs its HR structure if it matches.
NOTE: For each N2HET pin, only one instruction specifying a high resolution operation
(hr_lr = HIGH) is allowed to execute per loop resolution period. This includes any
instructions where (hr_lr = HIGH) but (en_pin_action = OFF).
The first high resolution instruction that executes and specifies a particular pin locks out
subsequent high resolution instructions from operating on the same pin until the end fo the
current loop resolution period.
Figure 20-11. HR I/O Architecture
HETDIR
HETDIN
Timer data in
>
Loop
Resolution
Clock
HET[x]
HETDSET
Timer data out
HETDOUT
HETDCLR
HR
Structure
One Per
Pin
{
HR control logic
Timer data in
HR prescale driver
Resolution clock
HR flags
HR up/down counter (7 bits)
HR compare data
HR register
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20.2.5.5 HR Structures Sharing (Input)
The HR Share Control Register (HETHRSH) allows two HR structures to share the same pin for input
capture only. If these bits are set, the HR structures N and N+1 are connected to pin N. In this structure,
pin N+1 remains available for general-purpose input/output. See Figure 20-12.
Figure 20-12. Example of HR Structure Sharing for N2HET Pins 0/1
N2HET
HR 0
HET[0]
1
0
HET[1]
N2HET
HR 1
HR share 1/0
The following program gives an example how the HR share feature (HET[0] HR structure and HET[1] HR
structure shared) can be used for the PCNT instruction:
L00 PCNT { next=L01, type=rise2fall, pin=0 }
L01 PCNT { next=L00, type=fall2rise, pin=1 }
The HET[1] HR structure is also connected to the HET[0] pin. The L00_PCNT data field is able to capture
a high pulse and the L01_PCNT captures a low pulse on the same pin (N2HET [0] pin).
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20.2.5.6 AND / XOR-shared HR Structure (Output)
Usually the N2HET design allows only one HR structure to generate HR edges on a pin configured as
output pin. The HETXOR register allows a logical XOR of the output signals of two consecutive HR
structures N (even) and N+1 (odd). See Figure 20-13. In this way, it is possible to generate pulses smaller
than the loop resolution clock since both edges can be generated by two independent HR structures. This
is especially required for symmetrical PWM. See Figure 20-14.
The hardware provides a XOR gate that is connected to the outputs of the HR structure of two
consecutive pins. In this structure, pin N+1 remains available for general-purpose input/output.
Figure 20-13. XOR-shared HR I/O
HETXOR0
0
HET[0]
N2HET HR 0
1
0
HET[1]
N2HET HR 1
HETXOR0
The following N2HET program gives an example for one channel of the symmetrical PWM. The generated
timing is given in Figure 20-14.
MAXC .equ 22
A_
.equ 0 ; HR structure HR0
B_
.equ 1 ; HR structure HR1
CN CNT
{ next=EA, reg=A, max=MAXC }
EA ECMP
{ next=EB, cond_addr=MA, hr_lr=HIGH, en_pin_action=ON, pin=A_,
action=PULSELO, reg=A, data=17, hr_data=115 }
MA MOV32 { next=EB, remote=EA, type=IMTOREG&REM, reg=NONE, data=17, hr_data=19 }
EB ECMP
{ next=CN, cond_addr=MB, hr_lr=HIGH, en_pin_action=ON, pin=B_,
action=PULSELO, reg=A, data=5, hr_data=13 }
MB MOV32 { next=CN, remote=EB, type=IMTOREG&REM, reg=NONE, data=5, hr_data=13 }
N2HET Settings and output signal calculation for this example program:
• Pin HET[0] and HET[1] are XOR-shared.
• HETPFR[31:0] register = 0x700: lr=128, hr=1, time slots ts = 128
• PWM period (determined by CNT_max field) = (22+1) · LRP = 2944 HRP
• Length of high pulse of (HET[0] XOR HET[1]) =
LH = (17·LRP+115·HRP) - (5·LRP+13·HRP)
With lr=128 there is LRP = 128 · HRP, so
LH = (2291 - 653) · HRP = 1638 HRP
• Duty cycle = DC = LH / PWM_period = 1638 HRP / (2944·HRP) = 55.6 %
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Figure 20-14 graphically shows the implementation of the XOR-shared feature. The first 2 waveforms
(symmetrical counter and CNT) show a symmetric counter and asymmetric counter. The symmetric
counter is shown only to highlight the axis of symmetry and is not implemented in the N2HET. The
asymmetric counter, which is implemented with a CNT instruction, needs to be set to the period of the
symmetric counter. The next two waveforms (HR [0] and HR [1]) show the output of the HR structures,
which are the inputs for the XOR gate to create the PWM output on pin HET[0]. Notice that the pulses of
signal HET[0] are centered about the axis of symmetry.
Figure 20-14. Symmetrical PWM with XOR-sharing Output
Symmetrical
counter
(not in HET)
Asymmetrical
counter
(CNT)
HET[0]
HR0
HR1
As an alternative, HR structures may be shared using a logical AND function to combine the effects of the
pin structures. The HETAND allows sharing two consecutive HR structures N (even) and N+1 (odd). See
Figure 20-15. In this structure, pin N+1 remains available for general-purpose input/output.
NOTE: Setting both the HETAND bit and HETXOR bits at the same time for a given pair of N2HET
pins is not supported, must be avoided by the application program.
Figure 20-15. AND-shared HR I/O
HETAND0
HET[0]
0
N2HET HR 0
1
HET[1]
0
N2HET HR 1
HETAND0
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20.2.5.7 Loop Back Mode
The loop back feature can be used by the application to monitor an N2HET output signal. For example, if
a PWM is generated by HR structure 0, then a PCNT instruction assigned to HR structure 1 can measure
back the pulse length or periods of the PWM output signal.
Loopback mode is activated between two high resolution structures by setting LBPSEL[x] to 1 in the
HETLBPSEL register for the corresponding structure pair. The direction of the loopback between the two
structures in the structure pair is determined by the value of LBPDIR[x] in the HETLBPDIR Register.
For example, if bit LBPSEL[0] is set to 1, then HR structures 0 and 1 will be internally connected in loop
back mode. If bit LBPDIR[0] is set to 0, then structure 0 will be the input and structure 1 will be the output.
Digital Loopback
Digital loopback mode is enabled by setting LBPTYPE[x] to 0 in the HETLBPSEL register for the
corresponding structure pairs. In digital loopback mode, the structure pairs are connected directly and the
output buffers are bypassed. Therefore, the loopback values will NOT be seen on the corresponding pins.
Figure 20-16 shows an example of digital loopback between structures HR0 and HR1. LBSEL[0] has been
set to 1 to enable loopback between the two structures. LBTYPE[0] has been set to 0 to select digital
mode for the loopback pair. The LPBDIR[0] value will determine the direction of the loopback by selecting
which of the HR blocks is output, and which is input. The bold lines show the digital loopback path.
Figure 20-16. HR0 to HR1 Digital Loopback Logic: LBTYPE[0] = 0
Loopback values will NOT be
seen on the pins in Digital
Loopback Mode
HR 0
LBPDIR [0] value
determines which HR
block is input and which
is output
Output
Buffer
X
Pin 0
X
Pin 1
LBSEL[0] value
determines whether or
not loopback is enabled
for these two blocks
HR 1
Output
Buffer
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Analog Loopback
Analog loopback mode is enabled by setting LBPTYPE[x] to 1 in the HETLBPSEL register for the
corresponding structure pairs. In analog loopback mode, the structure pairs are connected outside of the
output buffers. Therefore, the loopback values WILL be seen on the corresponding pins. Figure 20-17
shows an example of analog loopback between structures HR0 and HR1. LBSEL[0] has been set to 1 to
enable loopback between the two structures. LBTYPE[0] has been set to 1 to select analog mode for the
loopback pair. The LPBDIR[0] value will determine the direction of the loopback by selecting which of the
HR blocks is output, and which is input. The bold lines show the analog loopback path.
Figure 20-17. HR0 to HR1 Analog Loop Back Logic: LBTYPE[0] = 1
Loopback values WIL L be seen
on the pin s in Analog Loopback
Mode
LBPDIR [0] value
determ ines which HR
block is input and which
is output
HR 0
Outpu t
Buffer
X
Pin 0
X
Pin 1
LBSEL[0] value
determ ines whether or
not loopback is enabled
for these two block s
HR 1
Output
Buffer
Note:
• The loop back direction can be selected independent of the HETDIR register setting.
• The pin that is not driven by the N2HET output pin actions can still be used as normal GIO pin.
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20.2.5.8 Edge Detection Input Timing
There are several timing requirements for input signals in order to be captured correctly by N2HET.
Figure 20-18 illustrates these requirements, with min and max values described in Table 20-7 (Loop
Resolution) and Table 20-8 (High Resolution).
Figure 20-18. N2HET Input Edge Detection
1
N2HETx
3
4
2
Table 20-7. Edge Detection Input Timing for Loop Resolution Instructions
Parameter #
Description
1
Input Signal Period, rising edge to rising edge
2
Input Signal Period, falling edge to falling edge
3
Input Signal, high phase
4
Input Signal, high phase
min
max
> 2 (hr) (lr) tc(VCLK2)
< 225 (hr) (lr) tc(VCLK2)
> (hr) (lr) tc(VCLK2)
Table 20-8. Edge Detection Input Timing for High Resolution Instructions
Parameter #
Description
1
Input Signal Period, rising edge to rising edge
2
Input Signal Period, falling edge to falling edge
3
Input Signal, high phase
4
Input Signal, high phase
min
max
> (hr) (lr) tc(VCLK2)
< 225 (hr) (lr) tc(VCLK2)
> 2 (hr) tc(VCLK2)
These are the N2HET architectural limitations. Actual limitations will be slightly different due to on chip
routing and IO buffer delays, usually by several nanoseconds. Be sure to consult the device datasheet for
actual timings that apply to that device. Also, certain devices place additional restrictions on which pins
support the high resolution timings of Table 20-8, if present these additional limitations will also be called
out in the device datasheet.
Note that the max limit in Table 20-7 and Table 20-8 is based on the counter range of a single N2HET
instruction. The max value could be extended by employing an additional N2HET instruction to keep track
of counter overflows of the input counter / capture instruction.
20.2.5.9 PWM Generation Example 1 (in HR Mode)
The following example shows how an ECMP instruction works in high resolution mode. The example
assumes a VCLK2 of 32 MHz and the following values for the prescale divide rates (hr and lr), number of
time slots (ts), high and loop resolution period (HRP and LRP):
hr = 2, lr = 4, ts = hr × lr = 8
HRP = hr / VCLK2 = 2 / 32 MHz = 62.5 ns
LRP = (hr × lr) / VCLK2 = 8 / 32 MHz = 250 ns
With ts = 8, there are eight time slots available for the program execution, which in this case will consist of
one CNT and one ECMP instruction as shown below. The data field of the ECMP instruction is the 32-bit
compare value, whereby the lower 7 bits represent the high resolution compare field.
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When the 25-bit (loop resolution) compare matches, the HR compare value will be loaded from the 7 lower
bits of the instruction data field to the HR counter. At the next loop resolution clock, the HR counter will
count down at the HR clock frequency and perform the pin action when it reaches zero.
In the example illustrated by Figure 20-19, the 25-bit compare value is 1 and the 7-bit HR compare value
is 2. According to Section 20.2.3.2, depending on the loop resolution divide rate (lr), only certain bits of the
7-bit HR compare value are valid. In this example only the upper 2 bits (D[6:5]) are taken into account.
The example program below has a setting of hr_data = 100000b. Shifting this value right by 5 bits, results
in 10b which equals the two HR clock cycles delay mentioned above.
Figure 20-19. ECMP Execution Timings
LRP
VCLK2
HR Clock
HRP
LR Clock
Instruction
01
LR Counter
4 0
HR Counter
0
0 1
01
1
01
2
2
01
3
1
01
4
01
0
1
0
HR delay
Pin HET[0]
Z-Flag
Pin action in next
loop resolution cycle
+
high resolution delay
25-bit ECMP
match
CNT resets
Sets Z-Flag
Opposite Pin action in
next loop resolution
cycle
HETPFR[31:0] register = 0x201 --> lr=4 and hr=2 --> ts = 8
N2HET Program:
L00
L01
CNT
ECMP
{ next= L01, reg=A, irq=OFF, max = 4 }
{ next= L00, cond_addr= L00, hr_lr=HIGH, en_pin_action=ON, pin=0,
action=PULSEHI, reg=A, irq=OFF, data= 1, hr_data = 0x40 }
; 25 bit compare value is 1 and the 7-bit HR compare value is 2
; (Because of lr=4 the D[4:0] of the 7-bit HR field are ignored )
NOTE: ECMP Opposite Actions
ECMP opposite pin actions are always synchronized to the loop resolution clock.
Changing the duty cycle of a PWM generated by an ECMP instruction, can lead to a missing pulse if the
data field of the instruction is updated directly. This can happen when it is changed from a high value to a
lower value while the CNT instruction has already passed the new updated lower value. To avoid this a
synchronous duty cycle update can be performed with the use of an additional instruction (MOV32). This
instruction is only executed when the compare of the ECMP matches. For this the cond_addr of the ECMP
needs to point to the MOV32. On execution of the MOV32, it moves its data field into the data field of the
ECMP. The update of the duty cycle has to be made to the MOV32 data field instead of the ECMP data
field.
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20.2.5.10 PWM Generation Example 2 (in HR Mode)
The MCMP instruction can also be used in HR mode. In this case operation is exactly the same as for the
ECMP instruction except that the 25-bit low resolution is now the result of a magnitude compare (greater
or equal) rather than an equality compare. When the 25-bit (loop resolution) magnitude compare matches,
the HR compare value will be loaded from the 7 lower bits of the instruction data field to the HR counter.
At the next loop resolution clock, the HR counter will count down at the HR clock frequency and perform
the pin action when it reaches zero.
The MCMP instruction avoids the missing pulse problem of the ECMP instruction (see previous example),
however the duty cycle of the signal might not be exact for one PWM period. The benefit of the MCMP is
that it avoids adding another instruction to do the duty cycle update synchronously.
20.2.5.11 Pulse Generation Example (in HR Mode)
The PWCNT instruction may also be used in HR mode to generate pulse outputs with HR width. It
generates a single pulse when the data field of the instruction is non-zero. It remains at the opposite pin
action when the data field is zero.
The PWCNT instruction operates conversely to the ECMP instruction. See Figure 20-20. For PWCNT, the
opposite pin action is synchronous with the HR clock and for ECMP the pin action is synchronous with the
HR clock. The PWCNT pin action is synchronous with the loop resolution clock.
Figure 20-20. High/Low Resolution Modes for ECMP and PWCNT
ECMP
HR clock
Pin
action
PWCNT
LR clock
Pin
action
LR clock
Opposite
pin action
clock HR
Opposite
pin action
20.2.5.12 Pulse Measurement Example (in HR Mode)
The PCNT instruction captures HR measurement of the high/low pulse time or periods of the input. As
shown in Figure 20-21, at marker (1) the input goes HIGH and the HR counter immediately begins to
count. The counter increments and rolls over until the falling edge on the input pin, where it captures the
counter value into the HR capture register (marker (2)). The PCNT instruction begins counting when the
synchronized input signal goes HIGH and captures both the 25-bit data field and the HR capture register
into RAM when the synchronized input falls (marker (3)).
NOTE: The HR capture value written into RAM is shifted appropriately depending on the loop
resolution prescale divide rate (lr). (See also Section 20.2.3.2).
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Figure 20-21 shows what happens when the capture edge arrives after the HR counter overflows. This
causes the incremented value to be captured by the PCNT instruction.
Figure 20-21. PCNT Instruction Timing (With Capture Edge After HR Counter Overflow)
HR clock
Loop res
clock
PCNT CF
X
HR counter
0
0
1
2
3
0
1
1
2
3
2
0
0
HR capt.
reg
X
1
PCNT DF
X
2
Input pin
Input pin
sync’d
1
2
3
Figure 20-22 shows what happens when the capture edge arrives before the HR counter overflows. This
causes the non-incremented value to be captured by the PCNT instruction.
Figure 20-22. PCNT Instruction Timing (With Capture Edge Before HR Counter Overflow)
HR clock
Loop res
clock
PCNT CF
X
HR counter
0
0
1
2
3
HR capt.
reg
X
PCNT DF
X
0
1
1
2
3
2
0
0
3
1
Input pin
Input pin
sync’d
1
820
2
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20.2.5.13 WCAP Execution Example (in HR Mode)
The HR capability is enabled for WCAP, if its hr_lr bit is zero. In this case the HR counter is always
enabled and is synchronized with the resolution loop. When the specified edge is detected, the current
value of the HR counter is captured in the HR capture register and written into the RAM after the next
WCAP execution. The WCAP instruction effectively time stamps the free running timer saved in a register
(for example, register A shown in Figure 20-23).
Figure 20-23. WCAP Instruction Timing
LRP
HR clock
HRP
Loop res
clock
Instruction
A register
HR counter
CNT WCAP
CNT WCAP
0
0
CNT WCAP
1
1
2
CNT WCAP
2
3
0
1
2
CNT WCAP
3
3
0
1
2
CNT WCAP
4
3
0
1
2
5
3
0
1
2
6
3
0
1
2
3
Input pin HET[0]
sync’d to VCLK2
Input pin HET[0]
sampled by LRP
HR capt.
reg
X
WCAP DF
X
2
4
WCAP
Previous bit
0x0240 captured to WCAP DF [31:0]
HETPFR_register = 0x0200 --> lr = 4, hr = 1, ts = 4
N2HET Program:
L00 CNT {reg=A, max=01ffffffh}
L01 WCAP {next=L00, cond_addr=L00, hr_lr=high, reg=A, event= FALL, pin=0,
data=0}
In the example, the WCAP is configured to capture the counter when a falling edge occurs. The WCAP
data field (WCAP_DF) is updated in the loop succeeding the loop in which the edge occurred. The WCAP
instruction evaluates an edge by comparing its Previous bit with the sync’d input signal. In Figure 20-23,
the current value of the counter (4) is captured to WCAP_DF[31:7] and the value of the HR capture
register (2) is transferred to the valid bits (according the lr prescaler) of WCAP_DF[6:0]. Therefore, in the
example 0x0240 is captured in WCAP_DF[31:0].
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20.2.5.14 I/O Pull Control Feature
Figure 20-24. I/O Block Diagram Including Pull Control Logic
Output enable
Data out
N2HET pin
Data in
Input enable
Pull control disable
Pull select
Pull control
logic
The following apply if the device is under reset:
• Pull control: The reset pull control on the pins is enabled and a pulldown is configured.
• Input buffer: The input buffer is enabled.
• Output buffer: The output buffer is disabled.
The following apply if the device is out of reset:
• Pull control: The pull control is enabled by clearing the corresponding bit in the N2HET Pull Disable
Register (HETPULDIS). In this case, if the corresponding bit in the N2HET Pull Select Register
(HETPSL) is set, the pin will have a pull-up; if the bit in the N2HET Pull Select Register (HETPSL) is
cleared, the pin will have a pull-down. If the bit in the N2HET Pull Disable Register (HETPULDIS) is
set, there is no pull-up or pull-down on the pin.
• Input buffer: The input buffer is disabled only if the pin direction is set to input AND the pull control is
disabled AND pull down is selected as the pull bias. In all other cases, the input buffer is enabled.
NOTE: The pull-disable logic depends on the pin direction. If the pin is configured as output, then
the pulls are disabled automatically. If the pin is configured as input, the pulls are enabled or
disabled depending on the pull disable register bit.
•
Output buffer: A pin can be driven as an output pin if the corresponding bit in the N2HET Direction
Register (HETDIR) is set AND the open-drain feature (N2HET Open Drain Register (HETPDR)) is not
enabled. See Section 20.2.5.15 for more details.
The behavior of the input buffer, output buffer, and the pull control is summarized in Table 20-9. When an
input buffer is disabled, it appears as a logic low to on-chip logic.
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Table 20-9. Input Buffer, Output Buffer, and Pull Control Behavior
(1)
Device
under
Reset?
Pin Direction
(DIR) (1)
Pull Disable
(PULDIS) (1)
Pull Select
(PULSEL) (1)
Yes
X
X
No
0
0
No
0
No
No
No
Pull Control
Output Buffer
Input Buffer
X
Enabled
Disabled
Enabled
0
Pull down
Disabled
Enabled
0
1
Pull up
Disabled
Enabled
0
1
0
Disabled
Disabled
Disabled
0
1
1
Disabled
Disabled
Enabled
1
X
X
Disabled
Enabled
Enabled
X = Don’t care
20.2.5.15 Open-Drain Feature
The following apply if the open-drain feature is enabled on a pin, that is, the corresponding bit in the
N2HET Open Drain Register (HETPDR) is set:
• Output buffer is enabled if a low signal is being driven internally to the pin.
• The output buffer is disabled if a high signal is being driven internally to the pin.
20.2.5.16 N2HET Pin Disable Feature
This feature is provided for the safe operation of systems such as power converters and motor drives. It
can be used to inform the monitoring software of motor drive abnormalities such as over-voltage, overcurrent, and excessive temperature rise.
Table 20-10 shows the conditions for the output buffer to be enabled/disabled.
Figure 20-25. N2HET Pin Disable Feature Diagram
HETPINDIS
HETDIR
0
1
HETDOUT
N2HET pin
HETDIN
to other N2HET pin structures
A
B
nDIS pin*
N2HET pin enable
*nDIS pin realized by GIOA[5] (N2HET1) and GIOB[2] (N2HET2)
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Table 20-10. N2HET Pin Disable Feature
HETPINDIS.x
nDIS Pin (Input)
HET_PIN_ENA (HETGCR.24)
HETDIR.x
Output Buffer
0
X
X
0
Disabled
0
X
X
1
Enabled
1
0
X
0
Disabled
1
0
X
1
Disabled
1
1
X
0
Disabled
1
1
0
1
Disabled
1
1
1
1
Enabled
An interrupt capable device I/O pin can share the same pin as the N2HET nDIS signal. Normally GIOA[5]
serves as nDIS for N2HET1 and GIOB[2] as nDIS for N2HET2. Check the device datasheet for the actual
implementation. Sharing a pin with a GIO pin that is Interrupt capable allows the N2HET nDIS input to
also generate an interrupt to the CPU. An active low level on nDIS is intended to signal an abnormal
situation as described above. All N2HET pins, which are selected with the N2HET Pin Disable Register
(HETPINDIS), will be put in the high-impedance state by hardware immediately after the nDIS signal is
pulled low. At this time a CPU interrupt is issued, if it is enabled in the GIO pin logic.
The bit HET_PIN_ENA is automatically cleared in the failure condition and this state remains as long as
the software explicitly sets the bit again. The steps to do this are:
• Software detects, by reading the HETDIN register of the GIO pin, that the level on nDIS is inactive
(high).
• Software sets bit HET_PIN_ENA to deactivate the high impedance state of the pins.
20.2.6 Suppression Filters
Each N2HET pin is equipped with a suppression filter. If the pin is configured as an input it enables to filter
out pulses shorter than a programmable duration. Each filter consists of a 10-bit down counter, which
starts counting at a programmable preloaded value and is decremented using the VCLK2 clock.
• The counter starts counting when the filter input signal has the opposite state of the filter output signal.
The output signal is preset to the same input signal state after reset, in order to ensure proper
operation after device reset.
• Once the counter reaches zero without detecting an opposite pin state on the filter input signal, the
output signal is set to the opposite state.
• When the counter detects an opposite pin action on the filter input signal before reaching zero, the
counter is loaded with it's preload value and the opposite pin action on the filter output signal does not
take place. The counter resumes at the preload value until it detects an opposite pin action on the
input signal again.
• Therefore the filter output signal is delayed compared to the filter input signal. The amount of delay
depends on the counter clock frequency (VCLK2) and the programmed preload value.
• The accuracy of the output signal is +/- the counter clock frequency.
Table 20-11 gives examples for a 100 MHz VCLK2 frequency.
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Figure 20-26. Suppression Filter Counter Operation
Filter input
preload value
Counter
0
Filter output
Table 20-11. Pulse Length Examples for Suppression Filter
Possible values for the suppressed pulse length / frequency resulting from the
programmable 10 bit preload value (0,1,..,1023)
Divider CCDIV
VCLK2
1
100.0 MHz
10 ns, 20 ns, …, 10.22 µs, 10.23 µs
50 MHz, 25 MHz, …, 48.924 kHz, 48.876 kHz
2
50.0 MHz
20 ns, 40 ns, …, 20.44 µs, 20.48 µs
25 MHz, 12.5 MHz, …, 24.462 kHz, 24.414 kHz
3
33.3 MHz
30 ns, 60 ns, …, 30.66 µs, 30.69 µs
16.7 MHz, 8.3 MHz, …, 16.308 kHz, 16.292 kHz
20.2.7 Interrupts and Exceptions
N2HET interrupts can be generated by any instruction that has an interrupt enable bit in its instruction
format. When the interrupt condition in an instruction is true and the interrupt enable bit of that instruction
is set, an interrupt flag is then set in the N2HET Interrupt Flag Register (HETFLG). The address code for
this flag is determined by the five LSBs of the current timer program address. The flag in the N2HET
Interrupt Flag Register (HETFLG) is set even if the corresponding bit in the N2HET Interrupt Enable Set
Register (HETINTENAS) is 0. To generate an interrupt, the corresponding bit in the N2HET Interrupt
Enable Set Register (HETINTENAS) must be 1. In the N2HET interrupt service routine, the main CPU
must first determine which source inside the N2HET created the interrupt request. This operation is
accelerated by the N2HET Offset Index Priority Level 1 Register (HETOFF1) or N2HET Offset Index
Priority Level 2 Register (HETOFF2) that automatically provides the number of the highest priority source
within each priority level. Reading the offset register will automatically clear the corresponding N2HET
interrupt flag that created the request. However, if the offset registers are not used by the N2HET interrupt
service routine, the flag should be cleared explicitly by the CPU once the interrupt has been serviced.
Table 20-12. Interrupt Sources and Corresponding Offset Values in Registers HETOFFx
Source No.
Offset Value
no interrupt
0
Instruction 0, 32, 64...
1
Instruction 1, 33, 65...
2
:
:
Instruction 31, 63, 95...
32
Program Overflow
33
APCNT underflow:
34
APCNT overflow
35
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The instructions capable of generating interrupts are listed in Table 20-75.
Figure 20-27. Interrupt Functionality on Instruction Level
Interrupt condition
Interrupt enable
5 LSB address
code 00000
Interrupt
Flag 0
Interrupt condition
Interrupt enable
5 LSB address
code 11111
Interrupt
Flag 31
Each interrupt source is associated with a priority level (level 1 or level 2). When multiple interrupts with
the same priority level occur during the same loop resolution the lowest flag bit is serviced first.
In addition to the interrupts generated by the instructions the N2HET can generate three additional
exceptions:
• Program overflow
• APCNT underflow (see Section 20.3.1.2)
• APCNT overflow (see Section 20.3.1.3)
20.2.8 Hardware Priority Scheme
If two or more software interrupts are pending on the same priority level, the offset value will show the one
with the highest priority. The interrupt with the highest priority is the one with the lower offset value. This
scheme is hard-wired in the offset encoder. See Figure 20-28.
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Figure 20-28. Interrupt Flag/Priority Level Architecture
PL
bit 0
SW Int
flag 0
Offset index
encoder
for level 1
priority
HET interrupt priority 1
offset vector
PL
bit 1
SW Int
flag 1
PL
bit 23
SW Int
flag 23
PL
bit 24
SW Int
flag 24
Priority 1 global
interrupt request
To Vectored
Interrupt Manager
PL
bit 31
SW Int
flag 31
Priority 2 global
interrupt request
PL
bit 34
Exc Int
En 2
Exc Int
flag 2
Offset index
encoder
for level 2
priority
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20.2.9 N2HET Requests to DMA and HTU
As described in Section 20.6.3, the majority of the N2HET instructions are able to generate a transfer
request to the High-End Timer Transfer Unit (HTU) and/or to the DMA module when an instruction-specific
condition is true. One N2HET instruction can select one of 8 request lines by programming the “reqnum”
parameter. The “request” field in an instruction is used to enable, disable, or to generate a quiet request
(see Section 20.6.2) on the selected request line. Quiet requests can be used by the HTU, but not by the
DMA. For quiet request, refer to the High-End Timer Transfer Unit (HTU) Module chapter (see
Section 21.2.4.1).
The configuration of the N2HET Request Destination Select Register (HETREQDS) bits determines if a
request line triggers an HTU-DCP, a DMA channel or both. This means the register bits will determine
whether an N2HET instruction triggers DMAREQ[x], HTUREQ[x] or both signals (shown in Figure 20-29).
The request line number x corresponds to the “reqnum” parameter used in the instruction.
Figure 20-29. Request Line Assignment Example
DMA
DMAREQ[0]
HTUREQ[0]
DMAREQ[1]
HTUREQ[1]
DMAREQ[2]
HTUREQ[2]
DMAREQ[3]
HTUREQ[3]
DMAREQ[4]
HTUREQ[4]
DMAREQ[5]
HTUREQ[5]
DMAREQ[6]
HTUREQ[6]
DMAREQ[7]
HTUREQ[7]
DCP[0]
DCP[1]
DCP[2]
DCP[3]
DCP[4]
DCP[5]
DCP[6]
DCP[7]
HTU
DMAREQ[20]
DMAREQ[21]
DMAREQ[24]
DMAREQ[25]
N2HET
20.3 Angle Functions
Engine management systems require an angle-referenced time base to synchronize signals to the engine
toothed wheel. The N2HET has a method to provide such a time base for low-end engine systems. The
reference is created by the N2HET using three dedicated instructions with fractional angle steps equal to
/8, /16, /32, /64.
20.3.1 Software Angle Generator
The N2HET provides three specialized count instructions to generate an angle referenced time base
synchronized to an external reference signal (the toothed wheel signal) that defines angular reference
points.
The time base is used to generate fractional angle steps between the reference points. The step width K
(= 8, 16, 32, or 64) programmed by the user defines the angle accuracy of the time base. These fractional
steps are then accumulated in an angle counter to form the absolute angle value.
The first counter, APCNT, incremented on each loop resolution clock measures the periods P(n) of the
external signal. The second counter SCNT counts by step K up to the previous period value P(n-1),
measured by APCNT, and then recycles. The resulting period of SCNT is the fraction P(n-1) / K. The third
counter ACNT accumulates the fractions generated by SCNT.
Figure 20-30 illustrates the basic operation of APCNT, SCNT, and ACNT.
A N2HET timer program can only have one angle generator.
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Figure 20-30. Operation of N2HET Count Instructions
HET[2]
ext. ref.
signal
APCNT
period
counter
P(n-1)
P(n)
SCNT
step
counter
P(n-1) P(n-1)
K
K
ACNT
angle
generator
K counts
Due to stepping, the final count of SCNT does not usually exactly match the target value P(n-1).
Figure 20-31 illustrates how SCNT compensates for this feature by starting each cycle with the remainder
(final count - target) of the previous cycle.
Figure 20-31. SCNT Count Operation
Final Count = N0+nK
Target=P(n-1)
Final Count = N1+mK
E
SCNT
step
counter
N0+3K
N1+2K
N0+2K
N0+K
N0
N1+K
N1=N0+nK-P(n-1)
E
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ACNT detects period variations of the external signal measured by APCNT and compensates related
counting errors. A period increase is flagged in the deceleration flag. A period decrease is flagged in the
acceleration flag. If no variation is flagged, ACNT increments the counter value each time SCNT reaches
its target. If acceleration is detected, ACNT increments the counter value on each timer resolution (fast
mode). If deceleration is detected, ACNT is stopped. Figure 20-32 illustrates how the compensations for
acceleration and deceleration operate.
Figure 20-32. ACNT Period Variation Compensations
Deceleration
Acceleration
HET[2]
ext. ref.
signal
P(n)
APCNT
period
counter
P(n+1)
SCNT
step
counter
ACNT
angle
generator
0
1
2
K-1
0
1
2
DCF
Deceleration
flag
ACF
Acceleration
flag
830
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K-1
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20.3.1.1 Singularities
Singularities (gaps, in this case, from missing teeth in a toothed wheel) in the external reference signal
can be masked. The start and end of singularities are defined by gap start and gap end values specified in
SCNT and ACNT. When ACNT reaches gap start or gap end, it sets/resets the gap flag.
While the gap flag is set, new periods of the external reference signal are ignored for angle computation.
SCNT uses the last period measured by APCNT just before gap start.
Figure 20-33 and Figure 20-34 illustrate the behavior of the angle generator during a gap after a
deceleration or acceleration of the N2HET.
Figure 20-33. N2HET Timings Associated with the Gap Flag (ACNT Deceleration)
Singularity
HET[2]
ext. ref.
signal
APCNT
period
counter
DCF
Decel
flag
ACNT
angle
generator
GPF
Gap flag
Gap End
Gap Start
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Figure 20-34. N2HET Timings Associated with the Gap Flag (ACNT Acceleration)
Singularity
HET[2]
ext. ref.
signal
APCNT
period
counter
ACF
Accel.
flag
ACNT
angle
generator
GPF
Gap flag
Gap Start
Gap End
20.3.1.2 APCNT Underflow
The fastest valid external signal APCNT can accept must satisfy the following condition:
Step Width K < Period Min. Resolution (LRP)
This condition fixes the maximum possible step width once the minimum period and the resolution of an
application are specified.
If a period value accidentally falls below the minimum allowed, APCNT stops the capture of these periods
and sets the APCNT underflow interrupt flag located in the exceptions interrupt control register. In such a
situation, SCNT and ACNT continue to be executed using the last valid period captured by APCNT.
20.3.1.3 APCNT Overflow
The slowest valid external signal APCNT can measure must satisfy the following condition:
Period Max Resolution < 33554431
When this limit is reached (APCNT Count equals all 1’s), APCNT stays at a maximum count (stops
counting). APCNT remains in this position until the next specified capture edge is detected on the selected
pin and sets the APCNT overflow interrupt flag located in the exceptions interrupt control register. In this
situation, SCNT and ACNT continue to be executed using the maximum APCNT period count.
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20.3.2 Hardware Angle Generator (HWAG)
20.3.2.1 Overview
More engine control functions require powerful microcontrollers to process the timing. These controllers
must generate signals such as dwell time, spark time, and fuel injection, at precise engine angles. These
signals must be synchronized with the engine cycle.
The hardware angle generator (HWAG) generates angle value from toothed wheels. Because the toothed
wheels are inaccurate (the most widely wheel used has 60 teeth with 6°/tooth), the period between two
tooth edges (\) interpolates the angle value and the step width gives the number of interpolated angles.
For an example of the angle generator principle, see Figure 20-35.
The HWAG can complement the high-end timer (NHET) to generate complex angle-angle or angle-time
wave forms.
To work with the majority of toothed wheels, the HWAG provides registers to allow the CPU to configure
step width, singularity, and filtering when initializing.
Figure 20-35. Angle Generator Principle
Hardware angle generator
Toothed wheel
Speed
Position
20 bit angle value
Toothed
wheel
input
Angular
value
Step width 1/4 - 1/512
20.3.2.1.1 HWAG Features
The HWAG provides the following features:
• Programmable step width from 1/4 to 1/512
• Automatic synchronization check after first singularity synchronization
• Direct interface with the high-end timer
• 15 to 10,000 RPM range
• Programmable toothed-wheel input filter
• Programmable active edge on toothed-wheel
• Start bit synchronized to the tooth edge
• Pin selection capability for toothed-wheel input
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20.3.2.1.2 Block Diagram
Figure 20-36. Hardware Angle Generator Block Diagram
HWAG
To CPU
Angle Tick
Generation
Registers
Noise Filtering
Toothed
Wheel
ICLK
Gap Verification
2
Int
Peripheral
bus
HWAG core
HET Interface
4
Angle increment
HET Resolution
To HET
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20.3.2.2 HWAG Operation
20.3.2.2.1 Angle Tick Generation Algorithm
20.3.2.2.1.1 Angle Tick Generation Principle
The angle tick generator is the core kernel of this module. It uses the time-interpolation algorithm to
generate angle ticks based on the last toothed wheel period. The angle counter is incremented at each
new angle tick.
Because the toothed wheel is too inaccurate to fit with actual power-train applications, the algorithm is
based on dividing the previous tooth period by K angle steps. The tooth period is the period between two
active edges, which the HWAG global control register 2 (HWAGCR2) defines as the falling or the rising
edge of the input signal. For an example of the angle tick generation principle, see Figure 20-37.
The speed of the toothed wheel varies. This variance in speed creates some discontinuities in the angle
counter behavior.
When the toothed wheel accelerates, the current period becomes shorter than the previous one and the
tooth edge arrives before the last tick has been generated. To compensate for any missed ticks, the
HWAG adds them to the angle counter when the active edge of the tooth arrives. The angle value is
updated and resynchronized at each new active tooth edge.
When the toothed wheel decelerates, the period becomes longer than the previous period and K ticks are
already counted before the active edge tooth arrives. After the last tick has been generated, the HWAG
generates a tick only after the active tooth edge arrives.
Figure 20-37. Angle Tick Generation Principle
Toothed wheel
Angle Tick
K Ticks
P(n-1)
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20.3.2.2.1.2 Angle Tick Generation Implementation
The time-interpolation algorithm, which generates ticks based on the toothed wheel tooth period, consists
of the following five main counters linked together:
• Tooth counter (TCNT): Current tooth
• Period counter (PCNT): Period between two teeth
• Step counter (SCNT): Angle step
• Tick counter (TCKC): Angle ticks
• Angle counter (ACNT): Angle value
The algorithm also includes differences comparison, adder, and working registers as shown in Figure 2038.
Figure 20-38. New Angle Tick Generation Architecture
Teeth Register
Toothed wheel
Input
=
Gap Flag
TCNT
+1
PCNT (n)
+1
Teeth’event
P(n) >
2 x P ( n-1 )
Criteria
PCNT (n-1)
£
SCNT
Angle Tick
+
+/Step Register
ACNT
“1”
Tick CNT
-1
ACNT Inc.
Tickcount0
& teeth’event
The TCNT is an 8-bit counter. It counts teeth until it reaches the teeth register value then generates a gap
flag signal. The gap flag signal which changes the behavior of the HWAG during the singularity and resets
the TCNT on the next active edge of the toothed wheel input.
The PCNT calculates the period P(n) between two teeth (two active edges on the toothed wheel input).
The active edge (falling or rising) is selected by setting the TED bit in the HWAG global control register 2
(HWAGCR2). On an active edge from the toothed wheel input, the PCNT is saved in the HWAG previous
tooth period value register (HWAPCNT1).
The SCNT counts by K steps up to the previous period value, which is contained in the HWAPCNT1
register. When the SCNT overflows PCNT(n-1), an angle tick is generated and SCNT is reset to the
remainder between the SCNT and PCNT(n-1). The resulting period of the SCNT is the fraction PCNT(n1)/K.
The TCKC counts every angle tick until it reaches K and then stops the SCNT. If an active edge occurs
before the TCKC has reached K, the remainder is added directly to the ACNT.
When encountering an earlier active edge, the ACNT accumulates the fractions (angle ticks) generated by
the SCNT and the remainder of the TCKC. For an example of angle generation using the time-based
algorithm, see Figure 20-39.
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Figure 20-39. Angle Generation Using Time Based Algorithm
Input pin
P(n-1)
PCNT
Period counter
SCNT
Step counter
P(n)
P(n – 1) P(n – 1)
--------------------- --------------------K
K
ACNT
Angle counter
K counts
Because of stepping, the final count of the SCNT will usually be unequal to the target value PCNT(n-1)
and then will overflow. To compensate for this error generated by the algorithm, reset the SCNT to the
remainder of the difference between (SCNT - PCNT(n-1)).
To see how the SCNT and PCNT(n-1) generate angle ticks and compensate for the error due to the
integer fractions, see Figure 20-40.
Figure 20-40. SCNT Stepping Compensation
Final Count = N0+nK
P(n-1)
Final Count = N1+mK
SCNT
N1 +4K
N0 +4K
N1 +3K
N0 +3K
N1 +2K
N0 +2K
N0 +K
N1 +K
N1=N0+nK-P(n-1)
N2=N1+mK-P(n-1)
N0
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20.3.2.2.1.3 Acceleration and Deceleration
Because the toothed wheel speed is inconstant, it creates discontinuities in the angle counter behavior.
If the TCKC reaches zero before a new active tooth edge during a deceleration, the angle tick signal is no
longer generated by the SCNT and PCNT(n-1). This halts the ACNT until the new active tooth arrives.
If the TCKC is unequal to zero when the new active tooth edge arrives during an acceleration (that is, the
falling edge on the toothed wheel input in the example below), the rest of the tick counter increments the
ACNT. For an example of the ACNT during acceleration and deceleration, see Figure 20-41.
Figure 20-41. ACNT During Acceleration and Deceleration
Toothed Wheel
Toothed Wheel
n
ACNT
ACNT
Step Width
n
Tick CNT
Tick CNT
Acceleration
0
Deceleration
20.3.2.2.1.4 End of Cycle
The HWAG behaves differently during the singularity tooth period of the toothed wheel. During the
singularity period, the HWAG counts three virtual teeth (that is, three times the step width is added to the
ACNT) to ensure that the ACNT reaches the maximum value (that is, every angle step has been counted)
before resetting it.
During the singularity period, the HWAG generates angle ticks like for a normal tooth but with three times
the value. To generate these angle ticks, the HWAG uses a constant period based on the previous tooth
period. Because the period is based on the previous tooth period, the HWAG must recover from a
deceleration or acceleration of three teeth when realizing the active edge tooth at the end of the singularity
tooth.
The HWAG must ensure that the singularity occurs where expected and must verify it. When the
singularity tooth arrives, TCNT reaches the teeth register, sets the signal gap flag, and then keeps
PCNT(n-1) until the first tooth of the next round has passed. Because of these conditions, angle ticks
before the second tooth will be based on the previous singularity tooth period.
The tick counter is first loaded with a normal value. When the counter reaches zero, it is reloaded once
with twice the step width value if the criteria flag is not set. PCNT(n) continues to be incremented and to
check the criteria with PCNT(n-1). For more information on gap verification, see Section 20.3.2.2.4. The
SCNT continues to generate angle ticks until the tick counter reaches zero the second time. The criteria
flag validates the tooth in order to reset the counters. For an example of how the criteria flag validates the
tooth to reset the counters, see Figure 20-42.
When the tooth active edge occurs, the ACNT is incremented with the remainder value if the tick counter
is not equal to zero. When the ACNT contains a value equals to K times the teeth register, the PCNT, the
TCNT and the ACNT are reset to begin a new revolution.
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Figure 20-42. Singularity Check, ACNT Reset and Timing Associated
55
56
57
0
Toothed
wheel
T3 > 2 x T2
T1
Period
counter
T2
T4
T3
3
1
Gap flag
2
Criteria flag
4
Tick counter
P(n-1)
T1
T2
T4
5
ACNT
1
When TCNT = teeth register, the Gap flag is raised
2
Tick CNT reloads automatically with 2x the step-width because the Gap flag = ’1’
3
If PCNT ( n ) > 2 x PCNT ( n-1 ) and the Gap flag = ’1’ then the Criteria flag is raised
4
The tick counter is not reloaded because the Criteria flag is raised
5
The Gap flag and tooth active edge reset, followed by ACNT
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20.3.2.2.2 Angle Zero Initialization
Before any angle operation, initialize the HWAG and then initialize the angle zero as the singularity tooth.
To initialize the angle zero as the singularity tooth, the HWAG can send an interrupt at each new tooth to
help the software detect the first tooth if the interrupt is set. This allows you to decide which algorithm to
apply to detect the zero degree tooth (by enabling the corresponding interrupt, you can also use the wired
criteria).
When researching which algorithm to apply, the counters ACNT and TCNT are frozen and must be
initialized to their start values. The ACNT value is equal to T times the step value (T is the tooth where the
start will take effect and the initial value of the tooth counter). The counters PCNT(n) and PCNT(n-1)
contain the current period and the previous period respectively. These counters allow you to set a
detection criteria. When the application software sets the start bit, the software unfreezes the ACNT and
TCNT counters. The counters count from the preloaded values at the next tooth active edge. The ACNT is
preloaded with the value of 2 teeth and started synchronously with the next active edge of the toothed
wheel. For an example of the HWAG start sequence, see Figure 20-43.
Figure 20-43. Example of HWAG Start Sequence
TCNT
Toothed
wheel
#0
#0
#0
#1
#2
Start bit
ACNT
counter
2 x Step Width
Angle
Tick
Synchronization time
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Figure 20-44 is an example of a singularity research initializing the HWAG at the second tooth to start
synchronously with the third tooth. The HWAG angle value register (HWAACNT) contains 1024 (2 × 512)
and the HWAG current teeth number register (HWATHVL) contains 2.
The code is executed in a tooth interrupt subroutine in code using the PCNT(n-2) > PCNT (n-3) + PCNT
(n-1) algorithm.
Figure 20-44. Code
20.3.2.2.3 Stopping the HWAG
The HWAG starts synchronously with the active edge of the toothed wheel, but stops when the start
(STRT) bit in the HWAG global control register 2 (HWAGCR2) is reset. Within a tooth, the HWAG can be
stopped and parameters can be changed (that is, step width, angle counter, and so on) If this happens,
the restart will take effect on the next active tooth edge.
NOTE: When stopping the HWAG, stop the angle increment delivered to the NHET and set it to
zero. Reload the NHET counter with the same value of the angle counter (± corrections), if
restarting the HWAG.
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20.3.2.2.4 Gap Verification
After the CPU sets the synchronization and puts the HWAG into RUN time (that is, the start bit is set), the
tooth counter counts until reaching the teeth register (the number of real teeth of a full wheel revolution).
When the tooth counter reaches the teeth register, the gap flag signal is set. For more information on the
end of the cycle, see Section 20.3.2.2.1.4. When the gap flag signal is set, it allows the HWAG to verify if
the singularity is in the correct position (last tooth). The module then applies the PCNT(n) > 2 x PCNT(n-1)
criteria by comparing PCNT(n) and PCNT(n-1) with one bit left shifted. If the criteria does not match when
the tooth arrives, then the HWAG sends an interrupt to the CPU and does not reset the ACNT counter.
The application software must recover from such an interrupt to keep the HWAG operating optimally. For
an example of gap verification criteria for a 60-2 toothed wheel, see Figure 20-45.
Figure 20-45. Gap Verification Criteria For a 60-2 Toothed Wheel
Toothed
wheel
55
56
T1
T2
57
T3
0
T4
Period
counter
T3 > 2 x T2
If the hardware criteria is not enabled, you must set the angle reset (ARST) bit in the HWAG global control
register 2 (HWAGCR2) to validate the singularity. The HWAGCR2 register must validate the singularity
before the active edge of the singularity tooth. If the HWAGCR2 register fails to validate the singularity, the
HWAG generates an interrupt and does not clear the ACNT counter when the tooth edge occurs.
NOTE: For a 60-2 toothed wheel, set the ARST flag after the reload of the tick counter( when
PCNT(n) = PCNT(n-1)). By verifying the criteria, the application software can set the ARST
bit after this point.
The CPU can read the PCNT counter and make a custom criteria set the ARST bit on time for the HWAG.
The application software can use the gap flag interrupt to find the singularity tooth. Alternately, the CPU
can verify the validity of the singularity in the second tooth with a more accurate criteria by using the
HWAG previous tooth period value register (HWAPCNT1).
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20.3.2.2.4.1 Use of the ARST Bit In Case of a Toothed Wheel Without Singularity
If a toothed wheel has no singularity (that is, no missing teeth), the ACNT must be reset when it reaches
the angle zero point. To reset the ACNT when it reaches the angle zero point, set the ARST bit to 1.
Setting the ARST bit before the reload of the tick counter will cause the HWAG to fail to reload the tick
counter. The HWAG will act like a normal tooth but the next active edge on the toothed wheel input will
reset the ACNT and TCNT and clear the ARST bit. For an example of using the ARST bit in a toothed
wheel without singularity, see Figure 20-46.
Figure 20-46. Using the ARST Bit in a Toothed Wheel Without Singularity
55
56
57
0
1
Toothed
wheel
Gap flag
ARST
Tick counter
ACNT
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20.3.2.2.5 Input Noise Filtering
The toothed wheel input comes from an analog part and is sensitive to external noise. Due to this
sensitivity, the input needs to be filtered because of glitches in the signal.
The HWAG digitally filters the toothed wheel input signal before it is used inside the core. The filter blocks
the signal which negates the effect inside the HWAG. The HWAG provides two filter registers that filter the
same way.
The filters validate the input signal after n angle ticks. The n angle ticks are like X% of the tick counter.
The value of the remaining percentage of the tick counter (1- X%) need to be set because the tick counter
is a down counter. Calculate the value to put into the filter registers from the step width value (or angle
ticks value per tooth). The toothed wheel input is like a low pass filter with a cut-off frequency that
functions like a toothed-wheel speed, but without acceleration and decelerations side effects. For an
example of a windowing filter for a toothed wheel input on a falling active edge, see Figure 20-47.
NOTE: At any time, the CPU can modify the filter values to fine tune with the application.
Figure 20-47. Windowing Filter for Toothed Wheel Input on Falling Active Edge
Toothed
Input
X%
X%
Filter
Output
glitch during the window
glitch after the window
To calculate this number:
Step Width × (1 – X%) = Filter Register Value
If the step width value is equal to 512 and you want to filter 75% of the tooth, calculate the filter register as
follows:
512 × (1 – 0.75) = 128
When the tick counter reaches the filter register value, the toothed wheel input is unblocked.
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20.3.2.2.5.1 Filter During Singularity Tooth
During the singularity tooth, the filter acts differently than during a normal tooth. The filter releases the
input for a normal tooth. When the tick counter is reloaded, a second filter value is applied to the toothed
wheel input. For an example of filtering during a singularity tooth, see Figure 20-48.
Figure 20-48. Filtering During Singularity Tooth
Toothed
wheel
55
56
57
0
1
X%
X%
Filter
Filter 1
X%
X%
X%
Filter 2
Y%
The second filter value is set using the same equation as the first filter with the step width multiplied by 3.
To calculate this number:
(3 × Step Width) × (1 – Y%) = Second Filter Register Value
(30)
If the step width value is equal to 512 and you want 70% of singularity tooth period to be filtered, calculate
the filter register value as follows:
3 × 512 × (1 – 0.70) = 460
20.3.2.2.6 HWAG Interrupts
When conditions are set, the HWAG interrupts are generated.
When the interrupt condition is true, the corresponding flag is set in the HWAG interrupt flag register
(HWAFLG). If the corresponding enable bit in the HWAG interrupt enable set register (HWAENASET) is
also set, an interrupt request is sent to the CPU through one of the interrupt lines, depending on the
priority of the interrupt (HWAG interrupt level set register (HWALVLSET)).
Because the HWAG can set interruptions, the CPU must determine which source created the interrupt
request and then execute the interrupt service routine. The CPU reads the offset register (HWAOFFx) that
gives the number of the source. If the CPU reads the offset register, it will automatically clear the source
flag that created the request.
NOTE: If the corresponding enable bit is not set, a read in the offset register will not clear a flag. To
set the bit, write a 1 in the corresponding bit within the HWAG interrupt flag register
(HWAFLG).
The HWAG generates eight different interrupts:
• 0 = Overflow period
• 1 = Singularity not found
• 2 = Tooth interrupt
• 3 = ACNT overflow
• 4 = PCNT(n) > 2 × PCNT (n-1) during normal tooth
• 5 = Bad active edge tooth
• 6 = Gap flag
• 7 = Angle increment overflow
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For more information on these interrupts, see Table 20-14. Each interrupt source is associated with a low
or high priority. When one or more interrupts with the same priority occur, a fixed priority determines the
offset vector if the corresponding enable bits are set.
The HWAG generates two interrupt request signals for the central interrupt module (CIM). For information
on servicing interrupts, see Figure 20-49. For a list offset values, see Table 20-13.
Table 20-13. HWAG Interrupt Sources and Offset Values
Source Number
Offset Value
0
1
1
2
:
:
7
8
Figure 20-49. HWAG Interrupt Block Diagram
OVRF Period
Flag
High
Priority
Interrupt
Enable
Interrupt
Priority
Sign. Not Found
Low
Priority
Tooth Interrupt
ACNT OVRF
Criteria Found
Bad active edge tooth
Gap flag
Angle Inc. OVRF
OFFSET A
OFFSET B
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Table 20-14. HWAG Interrupt Descriptions
Interrupt Names
Overflow period
Singularity not found
Interrupt Descriptions
Occurs when the PCNT (n) counter reaches the maximum value. Can occur if the toothed
wheel input remains stable. May indicate failure of an engine stall or a toothed wheel sensor.
When the TCNT counter sets the gap flag, the HWAG waits for the criteria flag to raise
before the toothed wheel active edge. If the toothed wheel active edge occurs before the
criteria flag, the HWAG raises the singularity not found interrupt flag.
New edge tooth
This interrupt can sync or let you control the tick generation. This interrupt indicates the new
active edge tooth. This interrupt could be filtered or unfiltered (Bit FIL in control register).
Angle counter (ACNT) overflow
This interrupt occurs when the singularity is unable to be found. The angle counter (ACNT)
continues until overflow.
Singularity found during normal tooth
This interrupt indicates that the period of the current tooth is at least two times longer than
the previous one when the HWAG expects a normal tooth. This interrupt can detect the
singularity without bit manipulation by the CPU.
Bad active edge tooth
This interrupt indicates that an active edge has occurred before the end of the filtering
(toothed wheel input blocked) but the HWAG remains inactive internally. This interrupt can
detect glitches on the toothed wheel input.
Gap flag
When TCNT reaches the teeth register and the HWAG raises the gap flag , This interrupt is
set when the gap flag is raised by the HWAG,
Angle increment overflow
This interrupt indicates that the number of the angle increment is more than 15 since the last
resolution tick. This interrupt can prevent any discrepancies between the NHET and the
HWAG.
NOTE: Before enabling any interruption, clear the HWAG interrupt flag register (HWAFLG) to ensure
that any interrupts have finished. If interrupts are pending, the HWAG could generate an
interrupt based on an unrealistic event.
20.3.2.3 Emulation
Because the HWAG is designed to synchronize with a real-time environment, the HWAG counters
continue during emulation.
When the CPU is frozen, the HWAG continues to run and update registers. Only the offset registers
remain uncleared when entering debug mode.
During debug mode, interrupts can occur and will wait until the CPU enters run mode again. If interrupts
occur, they could affect synchronization with the toothed wheel
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20.3.2.4 Hardware Angle Generator and High-End Timer
In the engine management application, the HWAG is usually connected to one or more high-end timers.
This connection allows you to perform angle compare and angle/time compare. For an example of the
hardware angle generator/high-end timer interface, see Figure 20-50.
Figure 20-50. Hardware Angle Generator/High End Timer Interface
HWAG
Toothed wheel
B
U
S
HWAG core
To CPU
I
/
F
HET Interface
Angle increment
Resolution
HET
20.3.2.4.1 Signal Description
To perform a resynchronization, the HWAG interface provides to the NHET at every resolution clock an
angle increment value that represents how much the angle counter of the HWAG has been incremented
since the last NHET resolution clock. For an example of the angle count within the HWAG, see Figure 2051.
Figure 20-51. Angle Count Within the HWAG at Resolution Clock
Angle
count
10
11
12
HET
res.
Angle
increment
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When the engine speed increases, the angle count can increment by more than one in a NHET resolution
but the HWAG will continue to provide the angle increment value at every resolution..
The NHET can then implement its own angle counter (using a CNT instruction in angle mode) which will
be incremented once per resolution by the value given by the angle increment. For an example of an
angle count within the NHET with increments, see Figure 20-52.
Figure 20-52. Angle Count Within the NHET With Increments
Angle
counter
9
10
11
12
13
14
15
16
HET
Res.
Angle
increment
3
HET
counter
6
4
9
13
CNT position in the loop
20.3.2.4.2 NHET Operation on Angle Functions (ACMP, CNT)
20.3.2.4.2.1 State of the Art
Because the angle value can be increased by more than one, the compare value could be in-between the
old angle value and the new angle value of the NHET angle counter (where new angle value = old angle
value + angle increment). To perform an angle compare that ensures not to miss a compare value, the
NHET provides the ACMP instruction. For an example of a compare without ACMP instruction, see
Figure 20-53.
Figure 20-53. Compare Without ACMP Instruction
HET
Res.
Angle
increment
HET
counter
3
6
Compare
value
4
9
13
10
When the HET counter passes from 9 to 13, the equality compare can not
match the compare value 10. Consequently, the angle position is missed!
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20.3.2.4.2.2 ACMP Instruction Advantage
The ACMP instruction is more than an equality compare. ACMP instruction performs an in-between
comparison (old angle value < compare value ≤ new angle value) to match the position of the toothed
wheel. This instruction, where an equality compare executes every resolution, may miss a compare
match. For an example of ACMP compare within the NHET, see Figure 20-54.
Figure 20-54. Example of ACMP Compare Within the NHET
HET
Res.
Angle
increment
HET
counter
4
9
13
CNT
Compare
value
3
16
ACMP
10
Associated Pin
With the ACMP instruction, the compare that is performed will be: 9 < 10 £ 13
With the ACMP instruction, the compare is: 9 < 10 ≤ 13
NOTE:
To avoid multiple matches, the ACMP only matches during a single resolution.
Performing the following equations at the same time implements this compare:
CMP > NHET angle counter – Angle increment
CMP ≤ NHET angle counter
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20.3.2.4.3 NHET Interface
20.3.2.4.3.1 Input Signal Selection
The input pin of the toothed-wheel signal is software selectable. In previous generations of NHET/HWAG,
this was fixed to HET[2]. On this device, the input pin is programmable to provide more flexibility for the
system implementation. However, the implementation is done in a way to be backward compatible.
A separate register, HWAG pin select register (HWAPINSEL), is implemented to allow this selection
functionality. The HWAPINSEL register should be programmed before the HWAG is turned on. The
default selection will be HET[2] (PINSEL = 2h) after reset. The signals will be derived from the input buffer
of each pin. This will allow configuring the pin as an output and measure back the output signal with the
HWAG.
You can change the HWAPINSEL register at any time, but the proper functionality of the HWAG is not
assured if the selection is changed while the HWAG is already operational. It is recommended that the
input selection is done before the STRT bit in the HWAG global control register 2 (HWAGCR2)) is
programmed to 1.
20.3.2.4.3.2 HWAG to NHET Interface
The NHET interface is a 11-bit counter sampled by the NHET and reset by the NHET resolution. The
counter contains the value of ACNT incremented during the last resolution (see Section 20.3.2.4.1). For
the NHET interface block diagram, see Figure 20-55.
Figure 20-55. NHET Interface Block Diagram
HET Res.
counter
ACNT Inc.
+
11 bits
Angle Increment
register
Angle Tick
4 bits
Angle
increment [3:0]
When the ACNT register is reset to zero, the angle increment register is not reset. The NHET software
checks if its own angle register is higher than 360° and either clears it or continues to 720°. If ACNT is
reset within the HWAG, the angle increment register gives the NHET the number of angle ticks from the
last resolution.
During a strong acceleration after a tooth active edge, the number of angle ticks can exceed 15. If the
number of ticks exceeds 15, the HWAG delivers to the NHET several angle increments at 15. This allow
the NHET to follow without missing any angle positions from the HWAG. When the counter is below 15,
the angle increment reflects the counter. When the angle increment overflows, sets to 15, and if the
enable bit (bit 7 in the control register) is set, the HWAG can send an interrupt to the CPU.
During a strong deceleration, the angle increment can stay null for one or more NHET resolution clocks.
To minimize the error between the fly-wheel and NHET angle counter, the step width and the NHET
resolution must be set to avoid any overflow of the 11-bit counter of the NHET interface. This can happen
if the number of angle ticks always exceeds 15 during one resolution.
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20.3.2.5 Range of Operations
20.3.2.5.1 Intrinsic HWAG Limitation
The following factors limit the HWAG:
• SYSCLK
• PCNT counter (overflow)
• Number of teeth
• Angle step
These factors will influence the engine speed range (RPM limitation) and the maximum accuracy of the
angle steps (wheel limitation).
• RPM limitation
The toothed wheel speed is limited by the period counter (PCNT) and the angle step for a given
SYSCLK.
RPM minimum is related to PCNT overflow and SYSCLK.
Maximum PCNT value × SYSCLK = Maximum tooth period
60
RPM
TeethNumber u ToothPeriod
PCNT is a 24-bit counter based on SYSCLK.
RPM maximum is related to the angle step and SYSCLK.
Minimum tooth period > Step Width × SYSCLK
The angle ticks period could not be inferior to the SYSCLK.
Example: The toothed wheel is a 60-2, SYSCLK is 50 Mhz (20 ns), and step width is 512:
RPM minimum ≥ 16 777 215 × 20 ns = 335.5443 ms ≥ ~3 RPM
RPM maximum ≥ 512 × 20 ns = 10.24 µs ≥ 97 656 RPM
NOTE: With a 60-2 toothed wheel, the tooth period is the reverse of the RPM number.
•
852
Wheel Limitation
The HWAG is limited by the number of teeth and the increments in a revolution.
The maximum number of teeth is 256. This limits the number of increments per revolution to 512 steps
× 256 teeth = 131 072 angle increments.
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20.3.2.5.2 HWAG-NHET Limitation
The maximum angle accuracy is a function of the angle step and the NHET loop resolution.
The increment per resolution limits the interface between the HWAG and the NHET. The maximum angle
increment per NHET resolution is 15 increments/NHET_res, which is an angular speed. If the angle
increment overflows 15 during a constant speed, the system is diverging.
In the HWAG, the angular speed is given by the relation:
Step Width
Angular Speed
Minimum ToothPeriod
To ensure that the values are correct, they must satisfy the following equation:
MaxHETresolution u Step Width
15
MinimumToothPeriod
Then,
MaxHETresolution
15 u MinToothPeriod
Step Width
Example: For a 60-2 at 10000 RPM, the tooth period is 100 µs and the step width is 512:
15 u 100
MaxHET resolution
2.93 Ps
512
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20.3.2.6 Tricks
20.3.2.6.1 Using HWAG Previous Tooth Period Value Register (HWAPCNT1)
The HWAG previous tooth period value register (HWAPCNT1) can compensate for errors because of
acceleration or deceleration.
If there is a variation of the toothed wheel, the ACNT register will have a discontinuity . For an explanation
of acceleration and deceleration, see Section 20.3.2.2.1.3. Avoid this discontinuity by giving the
HWAPCNT1 register a smaller or larger value, depending of the variation. When HWAPCNT1 is modified,
the angle tick period is also be modified which causes faster or slower tick generation and decreases the
discontinuity on the next falling edge.
Because of this compensation, the NHET interface will not overflow and fewer errors will occur on the
NHET angle counter in case of strong acceleration.
NOTE: Reading the angle increment will give the application the amount of the acceleration.
However, adding the value directly to the NHET counter will result in a discontinuity in the
compare sequence. Particularly angle based compare could be missed.
20.3.2.6.2 Using the Singularity During Normal Tooth Interrupt
This interrupt detects if the HWAG is desynchronized with the toothed wheel and resynchronizes the
HWAG.
Because the criteria was set during a tooth other than the singularity tooth, the interrupt occurs. Because
the criteria is based on PCNT > 2 × PCNT (n-1), this interrupt is likely due to the singularity.
The following steps explain how to resynchronize the HWAG with this interrupt:
1. Stop the HWAG
2. Reset ACNT
3. Reset tooth counter
4. Reset interrupt
5. Set start bit.
The HWAG will restart on the tooth zero.
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20.4
N2HET Control Registers
Table 20-15 summarizes all the N2HET registers. The base address for the control registers is
FFF7 B800h for N2HET1 and FFF7 B900h for N2HET2.
Table 20-15. N2HET Registers
Offset
Acronym
Register Description
00h
HETGCR
Global Configuration Register
Section 20.4.1
Section
04h
HETPFR
Prescale Factor Register
Section 20.4.2
08h
HETADDR
NHET Current Address Register
Section 20.4.3
0Ch
HETOFF1
Offset Index Priority Level 1 Register
Section 20.4.4
10h
HETOFF2
Offset Index Priority Level 2 Register
Section 20.4.5
14h
HETINTENAS
Interrupt Enable Set Register
Section 20.4.6
18h
HETINTENAC
Interrupt Enable Clear Register
Section 20.4.7
1Ch
HETEXC1
Exception Control Register 1
Section 20.4.8
20h
HETEXC2
Exception Control Register 2
Section 20.4.9
24h
HETPRY
Interrupt Priority Register
Section 20.4.10
28h
HETFLG
Interrupt Flag Register
Section 20.4.11
2Ch
HETAND
AND Share Control Register
Section 20.4.12
34h
HETHRSH
HR Share Control Register
Section 20.4.13
38h
HETXOR
HR XOR-Share Control Register
Section 20.4.14
3Ch
HETREQENS
Request Enable Set Register
Section 20.4.15
40h
HETREQENC
Request Enable Clear Register
Section 20.4.16
44h
HETREQDS
Request Destination Select Register
Section 20.4.17
4Ch
HETDIR
NHET Direction Register
Section 20.4.18
50h
HETDIN
NHET Data Input Register
Section 20.4.19
54h
HETDOUT
NHET Data Output Register
Section 20.4.20
58h
HETDSET
NHET Data Set Register
Section 20.4.21
5Ch
HETDCLR
NHET Data Clear Register
Section 20.4.22
60h
HETPDR
NHET Open Drain Register
Section 20.4.23
64h
HETPULDIS
NHET Pull Disable Register
Section 20.4.24
68h
HETPSL
NHET Pull Select Register
Section 20.4.25
74h
HETPCR
Parity Control Register
Section 20.4.26
78h
HETPAR
Parity Address Register
Section 20.4.27
7Ch
HETPPR
Parity Pin Register
Section 20.4.28
80h
HETSFPRLD
Suppression Filter Preload Register
Section 20.4.29
84h
HETSFENA
Suppression Filter Enable Register
Section 20.4.30
8Ch
HETLBPSEL
Loop Back Pair Select Register
Section 20.4.31
90h
HETLBPDIR
Loop Back Pair Direction Register
Section 20.4.32
94h
HETPINDIS
NHET Pin Disable Register
Section 20.4.33
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20.4.1 Global Configuration Register (HETGCR)
N2HET1: offset = FFF7 B800h; N2HET2: offset = FFF7 B900h
Figure 20-56. Global Configuration Register (HETGCR) [offset = 00h]
31
25
23
22
21
24
Reserved
HET_PIN_ENA
R-0
R/W-1
18
17
16
Reserved
MP
20
Reserved
19
PPF
IS
CMS
R-0
R/W-0
R-0
R/W-0
R/W-0
15
R/W-0
1
0
Reserved
TO
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-16. Global Configuration Register (HETGCR) Field Descriptions
Bit
31-25
24
Field
Reserved
Value
0
HET_PIN_ENA
Description
Reads return 0. Writes have no effect.
Enables the output buffers of the pin structures depending on the value of nDIS and DIR.x when
PINDIS.x is set.
Note: This bit will automatically get cleared when nDIS pin (input port) value is 0.
23
22-21
Reserved
0
No affect on the pin output buffer structure.
1
Enables the pin output buffer structure when DIR = output, PINDIS.x is set and nDIS = 1.
0
Reads return 0. Writes have no effect.
MP
Master Priority
The NHET can prioritize master accesses to N2HET RAM between the HET Transfer Unit and
another arbiter, which outputs the access of one of the remaining masters. The MP bits allow the
following selections:
20-19
18
Reserved
0
The HTU has lower priority to access the N2HET RAM than the arbiter output.
1h
The HTU has higher priority to access the N2HET RAM than the arbiter output.
2h
The HTU and the arbiter output use a round robin scheme to access the N2HET RAM.
3h
Reserved
0
Reads return 0. Writes have no effect.
PPF
Protect Program Fields
The PPF bit together with the Turn On/Off bit (TO) allows to protect the program fields of all
instructions in N2HET RAM.
When TO = 0:
0
All masters can read and write the program fields.
1
All masters can read and write the program fields.
When TO = 1:
17
0
All masters can read and write the program fields.
1
The program fields are readable but not writable for all masters, which could access the N2HET
RAM. Possible masters are the CPU, HTU, DMA and a secondary CPU (if available). Writes
initiated by these masters are discarded.
IS
Ignore Suspend
When Ignore Suspend = 0, the timer operation is stopped on suspend (the current timer instruction
is completed). Timer RAM can be freely accessed during suspend. When set to 1, the suspend is
ignored and the N2HET continues operating.
856
0
N2HET stops when in suspend mode.
1
N2HET ignores suspend mode and continues operation.
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Table 20-16. Global Configuration Register (HETGCR) Field Descriptions (continued)
Bit
Field
16
CMS
Value
Description
Clk_master/slave
This bit is used to synchronize multi-N2HETs. If set (N2HET is master), the N2HET outputs a signal
to synchronize the prescalers of the slave N2HET. By default, this bit is reset, which means a slave
configuration.
Note: This bit must be set to one (1) for single-N2HET configuration.
15-1
0
Reserved
0
N2HET is configured as a slave.
1
N2HET is configured as a master.
0
Reads return 0. Writes have no effect.
TO
Turn On/Off
TO does not affect the state of the pins. You must set/reset the timer pins when they are turned off,
or re-initialize the timer RAM and control registers before a reset. After a device reset, the timer is
turned off by default.
0
N2HET is OFF. The timer program stops executing. Turn-off is automatically delayed until the
current timer program loop is completed. Turn-off does not affect the content of the timer RAM, ALU
registers, or control registers. Turn-off resets all flags.
1
N2HET is ON. The timer program execution starts synchronously to the Loop clock. In case of
multiple N2HETs configuration, the slave N2HETs are waiting for the loop clock to come from the
master before starting execution. Then, the timer address points automatically address 00h
(corresponding to program start).
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20.4.2 Prescale Factor Register (HETPFR)
N2HET1: offset = FFF7 B804h; N2HET2: offset = FFF7 B904h
Figure 20-57. Prescale Factor Register (HETPFR)
31
17
16
Reserved
R-0
15
11
10
8
7
6
5
0
Reserved
LRPFC
Reserved
HRPFC
R-0
R/WP-0
R-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 20-17. Prescale Factor Register (HETPFR) Field Descriptions
Bit
Field
31-11
Reserved
10-8
LRPFC
7-6
Reserved
5-0
HRPFC
858
Value
0
Description
Reads return 0. Writes have no effect.
Loop-Resolution Pre-scale Factor Code. LRPFC determines the loop-resolution prescale divide
rate (lr).
0
/1
1h
/2
2h
/4
3h
/8
4h
/16
5h
/32
6h
/64
7h
/128
0
Reads return 0. Writes have no effect.
High-Resolution Pre-scale Factor Code. HRPFC determines the high-resolution prescale divide
rate (hr).
0
/1
1h
/2
2h
/3
3h
/4
:
:
3Dh
/62
3Eh
/63
3Fh
/64
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20.4.3 N2HET Current Address Register (HETADDR)
N2HET1: offset = FFF7 B808h; N2HET2: offset = FFF7 B908h
Figure 20-58. N2HET Current Address (HETADDR)
31
16
Reserved
R-0
15
9
8
0
Reserved
HETADDR
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 20-18. N2HET Current Address (HETADDR) Field Descriptions
Bit
Field
Value
31-9
Reserved
0
8-0
HETADDR
Description
Reads return 0. Writes have no effect.
N2HET Current Address
Read: Returns the current N2HET program address.
Write: Writes have no effect.
20.4.4 Offset Index Priority Level 1 Register (HETOFF1)
N2HET1: offset = FFF7 B80Ch; N2HET2: offset = FFF7 B90Ch
Figure 20-59. Offset Index Priority Level 1 Register (HETOFF1)
31
16
Reserved
R-0
15
6
5
0
Reserved
OFFSET1
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 20-19. Offset Index Priority Level 1 Register (HETOFF1) Field Descriptions
Bit
Field
31-6
Reserved
5-0
OFFSET1
Value
0
Description
Reads return 0. Writes have no effect.
OFFSET1 indexes the currently pending high-priority interrupt. Offset values and sources are listed in
Table 20-20.
Read: Read of these bits determines the pending N2HET interrupt.
Write: Writes have no effect.
Note: In any read operation mode, the corresponding flag (in the HETFLG) is also cleared. In Emulation
mode the corresponding flag is not cleared.
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Table 20-20. Interrupt Offset Encoding Format
Offset Value
Source No.
0
No interrupt
1
Instruction 0, 32, 64...
2
Instruction 1, 33, 65...
:
:
32
Instruction 31, 63, 95...
33
Program Overflow
34
APCNT Underflow
35
APCNT Overflow
20.4.5 Offset Index Priority Level 2 Register (HETOFF2)
N2HET1: offset = FFF7 B810h; N2HET2: offset = FFF7 B910h
Figure 20-60. Offset Index Priority Level 2 Register (HETOFF2)
31
16
Reserved
R-0
15
6
5
0
Reserved
OFFSET2
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 20-21. Offset Index Priority Level 2 Register (HETOFF2) Field Descriptions
Bit
Field
31-6
Reserved
5-0
OFFSET2
Value
0
Description
Reads return 0. Writes have no effect.
OFFSET2 indexes the currently pending low-priority interrupt. Offset values and sources are listed in
Table 20-20.
Read: Read of these bits determines the pending N2HET interrupt.
Write: Writes have no effect.
Note: In any read operation mode, the corresponding flag (in the HETFLG) is also cleared. In Emulation
mode, the corresponding flag is not cleared.
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20.4.6 Interrupt Enable Set Register (HETINTENAS)
N2HET1: offset = FFF7 B814h; N2HET2: offset = FFF7 B914h
Figure 20-61. Interrupt Enable Set Register (HETINTENAS)
31
16
HETINTENAS
R/W-0
15
0
HETINTENAS
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 20-22. Interrupt Enable Set Register (HETINTENAS) Field Descriptions
Bit
31-0
Field
Value
HETINTENAS[n]
Description
Interrupt Enable Set bits. HETINTENAS is readable and writable in any operation mode.
Writing a 1 to bit x enables the interrupts of the N2HET instructions at N2HET addresses x+0,
x+32, x+64, and so on. Generating an interrupt requires to set bit x in HETINTENAS and to enable
the interrupt bit in one of the instructions at addresses x+0, x+32, x+64, and so on. To avoid
ambiguity, only one of the instructions x+0, x+32, x+64, and so on, should have the interrupt enable
bit (inside the instruction) set. Writing a 0 to HETINTENAS has no effect.
When reading from HETINTENAS bit x gives the information, if N2HET instructions x+0, x+32,
x+64, and so on, have the interrupt enabled or disabled.
0
Read: Interrupt is disabled.
Write: Writes have no effect.
1
Read: Interrupt is enabled.
Write: Interrupt is enabled.
20.4.7 Interrupt Enable Clear Register (HETINTENAC)
N2HET1: offset = FFF7 B818h; N2HET2: offset = FFF7 B918h
Figure 20-62. Interrupt Enable Clear (HETINTENAC)
31
16
HETINTENAC
R/W-0
15
0
HETINTENAC
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-23. NHET Interrupt Enable Clear (HETINTENAC) Field Descriptions
Bit
31-0
Field
Value
HETINTENAC[n]
Description
Interrupt Enable Clear bits. HETINTENAC is readable and writable in any operation mode.
Writing a 1 to bit x disables the interrupts of the N2HET instructions at N2HET addresses x+0,
x+32, x+64, and so on. (See also description in Table 20-22). Writing a 0 to HETINTENAC has no
effect.
When reading from HETINTENAC bit x gives the information, if N2HET instructions x+0, x+32,
x+64, and so on, have the interrupt enabled or disabled.
0
Read: Interrupt is disabled.
Write: Writes have no effect.
1
Read: Interrupt is enabled.
Write: Interrupt is disabled.
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20.4.8 Exception Control Register 1 (HETEXC1)
N2HET1: offset = FFF7 B81Ch; N2HET2: offset = FFF7 B91Ch
Figure 20-63. Exception Control Register (HETEXC1)
31
25
24
Reserved
APCNT_OVRFL_
ENA
R-0
R/W-0
23
17
16
Reserved
APCNT_UNRFL_
ENA
R-0
R/W-0
15
9
8
Reserved
PRGM_OVRFL_
ENA
R-0
R/W-0
7
2
1
0
Reserved
3
APCNT_OVRFL_
PRY
APCNT_UNRFL_
PRY
PRGM_OVRFL_
PRY
R-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-24. Exception Control Register 1 (HETEXC1) Field Descriptions
Bit
Field
31-17 Reserved
24
15-9
8
7-3
2
1
0
862
0
APCNT_OVRFL_ENA
23-17 Reserved
16
Value Description
APCNT Overflow Enable
0
APCNT overflow exception is not enabled.
1
Enables the APCNT overflow exception.
0
Reads return 0. Writes have no effect.
APCNT_UNRFL_ENA
Reserved
APCNT Underflow Enable
0
APCNT underflow exception is not enabled.
1
Enables the APCNT underflow exception.
0
Reads return 0. Writes have no effect.
PRGM_OVRFL_ENA
Reserved
Reads return 0. Writes have no effect.
Program Overflow Enable
0
The program overflow exception is not enabled.
1
Enables the program overflow exception.
0
Reads return 0. Writes have no effect.
APCNT_OVRFL_PRY
APCNT Overflow Exception Interrupt Priority
0
Exception priority level 2.
1
Exception priority level 1.
APCNT_UNRFL_PRY
APCNT Underflow Exception Interrupt Priority
0
Exception priority level 2.
1
Exception priority level 1.
PRGM_OVRFL_PRY
ProgramOverflow Exception Interrupt Priority
0
Exception priority level 2.
1
Exception priority level 1.
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20.4.9 Exception Control Register 2 (HETEXC2)
N2HET1: offset = FFF7 B820h; N2HET2: offset = FFF7 B920h
Figure 20-64. Exception Control Register 2 (HETEXC2)
31
16
Reserved
R-0
15
9
8
Reserved
DEBUG_STATUS_
FLAG
R-0
R/WC-0
7
3
2
1
0
Reserved
APCNT_OVRFL_
FLAG
APCNT_UNRFL_
FLAG
PRGM_OVRFL_
FLAG
R-0
R/W1C-0
R/W1C-0
R/W1C-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear; -n = value after reset
Table 20-25. Exception Control Register 2 (HETEXC2) Field Descriptions
Bit
31-9
8
Field
Reserved
Value Description
0
DEBUG_STATUS_FLAG
Reads return 0. Writes have no effect.
Debug Status Flag.
This flag is set when N2HET has stopped at a breakpoint. Also generates a debug
request to halt the ARM CPU.
0
Read: N2HET is either running, or stopped, flag cleared but not yet restarted.
Write: No effect.
1
Read: N2HET is stopped at a breakpoint.
Write: Clears the bit. To restart N2HET clear this bit and then restart the ARM CPU.
The N2HET and ARM CPU will start synchronously.
7-3
2
Reserved
0
APCNT_OVRFL_FLAG
Reads return 0. Writes have no effect.
APCNT Overflow Flag
0
Read: Exception has not occurred since the flag was cleared.
Write: No effect.
1
Read: Exception has occurred since the flag was cleared.
Write: Clears the bit.
1
APCNT_UNDFL_FLAG
APCNT Underflow Flag
0
Read: Exception has not occurred since the flag was cleared.
Write: No effect.
1
Read: Exception has occurred since the flag was cleared.
Write: Clears the bit.
0
PRGM_OVERFL_FLAG
Program Overflow Flag
0
Read: Exception has not occurred since the flag was cleared.
Write: No effect.
1
Read: Exception has occurred since the flag was cleared
Write: Clears the bit.
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20.4.10 Interrupt Priority Register (HETPRY)
N2HET1: offset = FFF7 B824h; N2HET2: offset = FFF7 B924h
Figure 20-65. Interrupt Priority Register (HETPRY)
31
16
HETPRY
R/WP-0
15
0
HETPRY
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 20-26. Interrupt Priority Register (HETPRY) Field Descriptions
Bit
31-0
Field
Value
HETPRY[n]
Description
HET Interrupt Priority Level Bits
Used to select the priority of any of the 32 potential interrupt sources coming from N2HET instructions.
0
Interrupt priority level 2 (low level).
1
Interrupt priority level 1 (high level).
20.4.11 Interrupt Flag Register (HETFLG)
N2HET1: offset = FFF7 B828h; N2HET2: offset = FFF7 B928h
Figure 20-66. Interrupt Flag Register (HETFLG)
31
16
HETFLAG
R/W1C-0
15
0
HETFLAG
R/W1C-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear; -n = value after reset; X = Unknown
Table 20-27. Interrupt Flag Register (HETFLG) Field Descriptions
Bit
31-0
Field
Value
HETFLAG[n]
Description
Interrupt Flag Register Bits
Bit x is set when an interrupt condition has occurred on one of the instructions x+0, x+32, x+64, and so
on. The flag position x (in the register) is decoded from the five LSBs of the instruction address that
generated the interrupt. The hardware will set the flag only if the interrupt enable bit (in the
corresponding instruction) is set. The flag will be set even if bit x in the Interrupt Enable Set Register
(HETINTENAS) is not enabled. Enabling bit x in HETINTENAS is required if an interrupt should be
generated.
Clearing the flag can be done by writing a one to the flag. Alternatively reading the corresponding Offset
Index Priority Level 1 Register (HETOFF1) or Offset Index Priority Level 2 Register (HETOFF2) will
automatically clear the flag.
0
Read: No N2HET instruction with an interrupt has been reached since the flag was cleared.
Write: No effect.
1
Read: A N2HET instruction with an interrupt has been reached since the flag was cleared.
Write: Clears the bit.
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20.4.12 AND Share Control Register (HETAND)
N2HET1: offset = FFF7 B82Ch; N2HET2: offset = FFF7 B92Ch
Figure 20-67. AND Share Control Register (HETAND)
31
16
Reserved
R-0
15
14
13
12
11
10
9
8
AND
SHARE31/30
AND
SHARE29/28
AND
SHARE27/26
AND
SHARE25/24
AND
SHARE23/22
AND
SHARE21/20
AND
SHARE19/18
AND
SHARE17/16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
7
6
5
4
3
2
1
0
AND
SHARE15/14
AND
SHARE13/12
AND
SHARE11/10
AND
SHARE9/8
AND
SHARE7/6
AND
SHARE5/4
AND
SHARE3/2
AND
SHARE1/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-28. AND Share Control Register (HETAND) Field Descriptions
Bit
Field
31-16
Reserved
15-0
ANDSHARE
n+1 / n
Value
0
Description
Reads return 0. Writes have no effect.
AND Share Enable
Enable the AND sharing of the same pin for two HR structures. For example, if bit ANDSHARE1/0
is set, the pin HET[0] will then be commanded by a logical AND of both HR structures 0 and 1.
Note: If HR AND SHARE bits are used, pins not connected to HR structures (the odd number pin in
each pair) can be accessed as general inputs/outputs.
0
HR Output of HET[n+1] and HET[n] are not AND shared.
1
HR Output of HET[n+1] and HET[n] are AND shared onto pin HET[n].
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20.4.13 HR Share Control Register (HETHRSH)
N2HET1: offset = FFF7 B834h; N2HET2: offset = FFF7 B934h
Figure 20-68. HR Share Control Register (HETHRSH)
31
16
Reserved
R-0
15
14
13
12
11
10
9
8
HR
SHARE31/30
HR
SHARE29/28
HR
SHARE27/26
HR
SHARE25/24
HR
SHARE23/22
HR
SHARE21/20
HR
SHARE19/18
HR
SHARE17/16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
7
6
5
4
3
2
1
0
HR
SHARE15/14
HR
SHARE13/12
HR
SHARE11/10
HR
SHARE9/8
HR
SHARE7/6
HR
SHARE5/4
HR
SHARE3/2
HR
SHARE1/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-29. HR Share Control Register (HETHRSH) Field Descriptions
Bit
Field
31-16
Reserved
15-0
HRSHARE
n+1 / n
Value
0
Description
Reads return 0. Writes have no effect.
HR Share Bits
Enables the share of the same pin for two HR structures. For example, if bit HRSHARE1/0 is set,
the pin HET[0] will then be connected to both HR input structures 0 and 1.
Note: If HR share bits are used, pins not connected to HR structures (the odd number pin in each
pair) can be accessed as general inputs/outputs.
866
0
HR Input of HET[n+1] and HET[n] are not shared.
1
HR Input of HET[n+1] and HET[n] are shared; both measure pin HET[n].
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20.4.14 XOR Share Control Register (HETXOR)
N2HET1: offset = FFF7 B838h; N2HET2: offset = FFF7 B938h
Figure 20-69. XOR Share Control Register (HETXOR)
31
16
Reserved
R-0
15
14
13
12
11
10
9
8
XOR
SHARE31/30
XOR
SHARE29/28
XOR
SHARE27/26
XOR
SHARE25/24
XOR
SHARE23/22
XOR
SHARE21/20
XOR
SHARE19/18
XOR
SHARE17/16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
7
6
5
4
3
2
1
0
XOR
SHARE15/14
XOR
SHARE13/12
XOR
SHARE11/10
XOR
SHARE9/8
XOR
SHARE7/6
XOR
SHARE5/4
XOR
SHARE3/2
XOR
SHARE1/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-30. XOR Share Control Register (HETXOR) Field Descriptions
Bit
Field
31-16
Reserved
15-0
XORSHARE
n+1 / n
Value
0
Description
Reads return 0. Writes have no effect.
XOR Share Enable
Enable the XOR-share of the same pin for two output HR structures. For example, if bit
XORSHARE1/0 is set, the pin HET[0] will then be commanded by a logical XOR of both HR
structures 0 and 1.
Note: If XOR share bits are used, pins not connected to HR structures (the odd number pin in each
pair) can be accessed as general inputs/outputs.
0
HR Output of HET[n+1] and HET[n] are not XOR shared.
1
HR Output of HET[n+1] and HET[n] are XOR shared onto pin HET[n].
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20.4.15 Request Enable Set Register (HETREQENS)
N2HET1: offset = FFF7 B83Ch; N2HET2: offset = FFF7 B93Ch
Figure 20-70. Request Enable Set Register (HETREQENS)
31
8
Reserved
R-0
7
6
5
4
3
2
1
0
REQENA7
REQENA6
REQENA5
REQENA4
REQENA3
REQENA2
REQENA1
REQENA0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-31. Request Enable Set Register (HETREQENS) Field Descriptions
Bit
Field
31-8
Reserved
7-0
REQENAn
Value
0
Description
Reads return 0. Writes have no effect.
Request Enable Bits
0
Read: Returns the information that request line n is disabled.
Write: Writing a 0 has no effect.
1
Read: Returns the information that request line n is enabled.
Write: Writing a 1 to bit n enables the N2HET request line n.
Note: The request line can trigger a DMA control packet (DMA channel), an HTU double control
packet (DCP) or both simultaneously. The HETREQDS register determines to which module(s) the
N2HET request line n is assigned.
Note: A disabled request line does not memorize old requests. So there are no pending requests to
service after enabling request line n.
20.4.16 Request Enable Clear Register (HETREQENC)
N2HET1: offset = FFF7 B840h; N2HET2: offset = FFF7 B940h
Figure 20-71. Request Enable Clear Register (HETREQENC)
31
8
Reserved
R-0
7
6
5
4
3
2
1
0
REQDIS7
REQDIS6
REQDIS5
REQDIS4
REQDIS3
REQDIS2
REQDIS1
REQDIS0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-32. Request Enable Clear Register (HETREQENC) Field Descriptions
Bit
Field
31-8
Reserved
7-0
REQDISn
Value
0
Description
Reads return 0. Writes have no effect.
Request Disable Bits
0
Read: Returns the information that request line n is disabled.
Write: Writing a 0 has no effect.
1
Read: Returns the information that request line n is enabled.
Write: Writing a 1 to bit n disables the N2HET request line n.
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20.4.17 Request Destination Select Register (HETREQDS)
N2HET1: offset = FFF7 B844h; N2HET2: offset = FFF7 B944h
Figure 20-72. Request Destination Select Register (HETREQDS) [offset = FFF7 B844h]
31
23
22
21
20
19
18
17
16
Reserved
24
TDBS7
TDBS6
TDBS5
TDBS4
TDBS3
TDBS2
TDBS1
TDBS0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
15
7
6
5
4
3
2
1
0
Reserved
8
TDS7
TDS6
TDS5
TDS4
TDS3
TDS2
TDS1
TDS0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-33. Request Destination Select Register (HETREQDS) Field Descriptions
Bit
Field
31-24
Reserved
23-16
TDBSn
15-8
Reserved
7-0
TDSn
Value
0
Description
Reads return 0. Writes have no effect.
HTU, DMA or Both Select Bits
0
N2HET request line n is assigned to the module specified by TDS bit n.
1
N2HET request line n is assigned to both DMA and HTU. TDS bit n is ignored in this case.
0
Reads return 0. Writes have no effect.
HTU or DMA Select Bits
Note: It must be ensured in the N2HET program, that one request line is triggered by only one N2HET
instruction.
0
N2HET request line n is assigned to HTU (TDBS bit n is zero).
1
N2HET request line n is assigned to DMA (TDBS bit n is zero).
NOTE: Please refer to the device data sheet how each of the 8 N2HET request lines are connected
to these modules. See also Section 20.2.9.
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20.4.18 NHET Direction Register (HETDIR)
N2HET1: offset = FFF7 B84Ch; N2HET2: offset = FFF7 B94Ch
Figure 20-73. N2HET Direction Register (HETDIR)
31
16
HETDIR
R/W-0
15
0
HETDIR
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-34. N2HET Direction Register (HETDIR) Field Descriptions
Bit
31-0
Field
Value
HETDIR[n]
Description
Data direction of NHET pins
0
Pin HET[n] is an input (and its output buffer is tristated).
1
Pin HET[n] is an output.
NOTE: Table 20-9 shows how the register bits of DIR, PULDIS and PULSEL are affecting the
N2HET pins.
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20.4.19 N2HET Data Input Register (HETDIN)
N2HET1: offset = FFF7 B850h; N2HET2: offset = FFF7 B950h
Figure 20-74. N2HET Data Input Register (HETDIN)
31
16
HETDIN
R-x
15
0
HETDIN
R-x
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset;
Table 20-35. N2HET Data Input Register (HETDIN) Field Descriptions
Bit
31-0
Field
Value
HETDIN[n]
Description
Data input. This bit displays the logic state of the pin.
0
Pin HET[n] is at logic low (0).
1
Pin HET[n] is at logic high (1).
20.4.20 N2HET Data Output Register (HETDOUT)
N2HET1: offset = FFF7 B854h; N2HET2: offset = FFF7 B954h
Figure 20-75. N2HET Data Output Register (HETDOUT)
31
16
HETDOUT
R/W-0
15
0
HETDOUT
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-36. N2HET Data Output Register (HETDOUT) Field Descriptions
Bit
31-0
Field
Value
HETDOUT[n]
Description
Data out write. Writes to this bit will only take effect when the pin is configured as an output. The
current logic state of the pin will be displayed by this bit even when the pin state is changed by
writing to HETDSET or HETDCLR.
0
Pin HET[n] is at logic low (0).
1
Pin HET[n] is at logic high (1) if the HETPDR[n] bit = 0 or the output is in high-impedance state if
the HETPDR[n] bit = 1.
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20.4.21 NHET Data Set Register (HETDSET)
N2HET1: offset = FFF7 B858h; N2HET2: offset = FFF7 B958h
Figure 20-76. N2HET Data Set Register (HETDSET)
31
16
HETDSET
R/WS-0
15
0
HETDSET
R/WS-0
LEGEND: R/W = Read/Write; R = Read only; S = Set; -n = value after reset
Table 20-37. N2HET Data Set Register (HETDSET) Field Descriptions
Bit
31-0
Field
Value
HETDSET[n]
Description
This register allows bits of HETDOUT to be set while avoiding the pitfalls of a read-modify-write
sequence in a multitasking environment.
Bits written as a logic 1 set the same bit in the HETDOUT register; while bits written as logic 0
leave the same bit in HETDOUT unchanged. Reads from this address return the value of the
HETDOUT register.
0
Write: HETDOUT[n] is unchanged.
1
Write: HETDOUT[n] is set.
20.4.22 N2HET Data Clear Register (HETDCLR)
N2HET1: offset = FFF7 B85Ch; N2HET2: offset = FFF7 B95Ch
Figure 20-77. N2HET Data Clear Register (HETDCLR)
31
16
HETDCLR
R/WC-0
15
0
HETDCLR
R/WC-0
LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset
Table 20-38. N2HET Data Clear Register (HETDCLR) Field Descriptions
Bit
31-0
Field
Value
HETDCLR[n]
Description
This register allows bits of HETDOUT to be cleared while avoiding the pitfalls of a read-modify-write
sequence in a multitasking environment.
Bits written as a logic 1 clear the same bit in the HETDOUT register; while bits written as logic 0
leave the same bit in HETDOUT unchanged. Reads from this address return the value of the
HETDOUT register.
872
0
Write: HETDOUT[n] is unchanged.
1
Write: HETDOUT[n] is cleared.
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20.4.23 N2HET Open Drain Register (HETPDR)
Values in this register enable or disable the open drain capability of the data pins.
N2HET1: offset = FFF7 B860h; N2HET2: offset = FFF7 B960h
Figure 20-78. N2HET Open Drain Register (HETPDR)
31
16
HETPDR
R/W-0
15
0
HETPDR
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-39. N2HET Open Drain Register (HETPDR) Field Descriptions
Bit
31-0
Field
Value
HETPDR[n]
Description
Open drain control for HET[n] pins
0
The pin is configured in push/pull mode.
1
The pin is configured in open drain mode. The HETDOUT register controls the state of the output
buffer:
HETDOUT[n] = 0 The output buffer of pin HET[n] is driven low.
HETDOUT[n] = 1 The output buffer of pin HET[n] is tristated.
20.4.24 N2HET Pull Disable Register (HETPULDIS)
Values in this register enable or disable the pull-up/-down functionality of the pins.
N2HET1: offset = FFF7 B864h; N2HET2: offset = FFF7 B964h
Figure 20-79. N2HET Pull Disable Register (HETPULDIS)
31
16
HETPULDIS
R/W-n
15
0
HETPULDIS
R/W-n
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; n is device dependent, see device specific data sheet
Table 20-40. N2HET Pull Disable Register (HETPULDIS) Field Descriptions
Bit
31-0
Field
Value
HETPULDIS[n]
Description
Pull disable for N2HET pins
0
The pull functionality is enabled on pin HET[n].
1
The pull functionality is disabled on pin HET[n].
NOTE: See device data sheet for which pins provide programmable pullups/pulldowns.
Table 20-9 shows how the register bits of HETDIR, HETPULDIS, and HETPSL are affecting
the N2HET pins.
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20.4.25 N2HET Pull Select Register (HETPSL)
Values in this register select the pull-up or pull-down functionality of the pins.
N2HET1: offset = FFF7 B868h; N2HET2: offset = FFF7 B968h
Figure 20-80. N2HET Pull Select Register (HETPSL)
31
16
HETPSL
R/W-0
15
0
HETPSL
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-41. N2HET Pull Select Register (HETPSL) Field Descriptions
Bit
31-0
Field
Value
HETPSL[n]
Description
Pull select for NHET pins
0
The pull down functionality is enabled if corresponding bit in HETPULDIS is 0.
1
The pull up functionality is enabled if corresponding bit in HETPULDIS is 0.
NOTE: See device data sheet for which pins provide programmable pullups/pulldowns.
Table 20-9 shows how the register bits of HETDIR, HETPULDIS and HETPSL are affecting
the N2HET pins.
The information of this register is also used to define the pin states after a parity error:
After a parity error all N2HET pins, which are
1. Defined as output pins in the HETDIR register
2. Not defined as open drain pins (with the HETPDR register)
3. Selected with the HETPPR register, will remain outputs, but automatically
change their levels in the following way:
• If the HETPSL register specifies 0 for the pin, it will switch to low level.
• If the HETPSL register specifies 1 for the pin, it will switch to high level.
This behavior is independent of the value, which register HETPULDIS specifies for the
corresponding pin.
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20.4.26 Parity Control Register (HETPCR)
N2HET1: offset = FFF7 B874h; N2HET2: offset = FFF7 B974h
Figure 20-81. Parity Control Register (HETPCR)
31
16
Reserved
R-0
15
9
8
7
4
3
0
Reserved
TEST
Reserved
PARITY_ENA
R-0
R/WP-0
R-0
R/WP-5h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 20-42. Parity Control Register (HETPCR) Field Descriptions
Bit
31-9
8
Field
Value
Reserved
0
TEST
Description
Reads return 0. Writes have no effect.
Test Bit. When this bit is set, the parity bits are mapped into the peripheral RAM frame to make
them accessible by the CPU.
0
Read: Parity bits are not memory mapped.
Write: Disable mapping.
1
Read: Parity bits are memory mapped.
Write: Enable mapping.
7-4
Reserved
3-0
PARITY_ENA
0
Reads return 0. Writes have no effect.
Enable/disable parity checking. This bit field enables or disables the parity check on read
operations and the parity calculation on write operations. If parity checking is enabled and a parity
error is detected the N2HET_UERR signal is activated.
5h
Read: Parity check is disabled.
Write: Disable checking.
Others
Read: Parity check is enabled.
Write: Enable checking.
NOTE: It is recommended to write Ah to enable error detection, to guard against soft errors flipping
PARITY_ENA to a disable state.
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20.4.27 Parity Address Register (HETPAR)
N2HET1: offset = FFF7 B878h; N2HET2: offset = FFF7 B978h
Figure 20-82. Parity Address Register (HETPAR)
31
16
Reserved
R-0
15
13
12
2
1
0
Reserved
PAOFF
Reserved
R-0
R-X
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; X = Value unchanged after reset
Table 20-43. Parity Address Register (HETPAR) Field Descriptions
Bit
Field
31-13
Reserved
12-2
PAOFF
Value
0
Description
Reads return 0. Writes have no effect.
Parity Error Address Offset. This register holds the offset address of the first parity error, which is
detected in N2HET RAM. This error address is frozen from being updated until it is read by the CPU.
During emulation mode, this address is frozen even when read.
In case of a N2HET RAM parity error, PAOFF will contain the offset address of the erroneous 32-bit
N2HET RAM field counted from the beginning of the N2HET RAM.
Examples: The 32-bit program field of instruction 0 will return 0, the 32-bit control field of instruction 0
will return 1, ..., the 32-bit control field of instruction 1 will return 5, and so on.
Read: Returns the offset address of the erroneous 32-bit word in bytes from the beginning of the
N2HET RAM.
Write: Writes have no effect.
1-0
Reserved
0
Reads return 0. Writes have no effect.
NOTE: The Parity Error Address Register will not be reset, neither by PORRST nor by any other
reset source.
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20.4.28 Parity Pin Register (HETPPR)
N2HET1: offset = FFF7 B87Ch; N2HET2: offset = FFF7 B97Ch
Figure 20-83. Parity Pin Register (HETPPR)
31
16
HETPPR
R/W-0
15
0
HETPPR
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-44. Parity Pin Register (HETPPR) Field Descriptions
Bit
31-0
Field
Value
HETPPR[n]
Description
NHET Parity Pin Select Bits. Allows HET[n] pins to be configured to drive to a known state when an
N2HET parity error is detected.
0
Pin HET[n] is not affected by the detection of an N2HET parity error.
1
Pin HET[n] is driven to a known state when an N2HET parity error is detected. The known state is a
function of bits HETDIR[n], HETPSL[n], HETPDR[n] as described in Table 20-45 (this state is also
independent of HETPULDIS[n]).
Table 20-45. Known State on Parity Error
HETDIR[n]
HETPDR[n]
HETPSL[n]
Known State on Parity Error
0
x
x
High Impedance
1
0
0
Drive Logic 0
1
0
1
Drive Logic 1
1
1
x
High Impedance
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20.4.29 Suppression Filter Preload Register (HETSFPRLD)
N2HET1: offset = FFF7 B880h; N2HET2: offset = FFF7 B980h
Figure 20-84. Suppression Filter Preload Register (HETSFPRLD)
31
18
15
10
17
16
Reserved
CCDIV
R-0
R/W-0
9
0
Reserved
CPRLD
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-46. Suppression Filter Preload Register (HETSFPRLD) Field Descriptions
Bit
Field
31-18
Reserved
17-16
CCDIV
Value
Description
0
Reads return 0. Writes have no effect.
Counter Clock Divider
CCDIV determines the ratio between the counter clock and VCLK2.
15-10
9-0
Reserved
0
CCLK = VCLK2
1h
CCLK = VCLK2 / 2
2h
CCLK = VCLK2 / 3
3h
CCLK = VCLK2 / 4
0
Reads return 0. Writes have no effect.
CPRLD
Counter Preload Value
CPRLD contains the preload value for the counter clock.
20.4.30 Suppression Filter Enable Register (HETSFENA)
N2HET1: offset = FFF7 B884h; N2HET2: offset = FFF7 B984h
Figure 20-85. Suppression Filter Enable Register (HETSFENA)
31
16
HETSFENA
R/W-0
15
0
HETSFENA
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-47. Suppression Filter Enable Register (HETSFENA) Field Descriptions
Bit
31-0
Field
Value
HETSFENA[n]
Description
Suppression Filter Enable Bits
Note: If the pin is configured as an output by the N2HET Direction Register (HETDIR), the filter is
automatically disabled independent on the bit in HETSFENA.
878
0
The input noise suppression filter for pin HET[n] is disabled.
1
The input noise suppression filter for pin HET[n] is enabled.
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20.4.31 Loop Back Pair Select Register (HETLBPSEL)
Refer to Section 20.2.5.7 for a description of loopback test functions.
N2HET1: offset = FFF7 B88Ch; N2HET2: offset = FFF7 B98Ch
Figure 20-86. Loop Back Pair Select Register (HETLBPSEL)
31
30
29
28
27
26
25
24
LBPTYPE31/30 LBPTYPE29/28 LBPTYPE27/26 LBPTYPE25/24 LBPTYPE23/22 LBPTYPE21/20 LBPTYPE19/18 LBPTYPE17/16
R/W-0
R/W-0
R/W-0
23
22
21
R/W-0
LBPTYPE15/14 LBPTYPE13/12 LBPTYPE11/10
R/W-0
R/W-0
R/W-0
R/W-0
20
19
18
17
16
LBPTYPE9/8
LBPTYPE7/6
LBPTYPE5/4
LBPTYPE3/2
LBPTYPE1/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
15
14
13
12
11
10
9
8
LBPSEL31/30
LBPSEL29/28
LBPSEL27/26
LBPSEL25/24
LBPSEL23/22
LBPSEL21/20
LBPSEL19/18
LBPSEL17/16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
7
6
5
4
3
2
1
0
LBPSEL15/14
LBPSEL13/12
LBPSEL11/10
LBPSEL9/8
LBPSEL7/6
LBPSEL5/4
LBPSEL3/2
LBPSEL1/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-48. Loop Back Pair Select Register (HETLBPSEL) Field Descriptions
Bit
31-16
15-0
Field
Value
LBPTYPE
n+1 / n
Description
Loop Back Pair Type Select Bits
These bits are valid only when Loopback mode is enabled (HETLBPDIR[19:16] = 1010).
0
Digital loopback is selected for HR structures on pins HET[n+1] and HET[n].
1
Analog loopback is selected for HR structures on pins HET[n+1] and HET[n].
LBPSEL
n+1 / n
Loop Back Pair Select Bits
These bits are valid only when Loopback mode is enabled (HETLBPDIR[19:16] = 1010).
If bit x is set, the HR structures on pins HET[n+1] and HET[n] are connected in a loop back mode. The
direction is given by LBPDIR n+1/n and type is selected by LBPTYPE n+1/n.
The pin which is not driven by the N2HET pin actions can still be used as normal GIO pin.
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20.4.32 Loop Back Pair Direction Register (HETLBPDIR)
Refer to Section 20.2.5.7 for a description of loopback test functions.
N2HET1: offset = FFF7 B890h; N2HET2: offset = FFF7 B990h
Figure 20-87. Loop Back Pair Direction Register (HETLBPDIR)
31
20
19
16
Reserved
LBPTSTENA
R-0
R/WP-5h
15
14
13
12
11
10
9
8
LBPDIR31/30
LBPDIR29/28
LBPDIR27/26
LBPDIR25/24
LBPDIR23/22
LBPDIR21/20
LBPDIR19/18
LBPDIR17/16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
7
6
5
4
3
2
1
0
LBPDIR15/14
LBPDIR13/12
LBPDIR11/10
LBPDIR9/8
LBPDIR7/6
LBPDIR5/4
LBPDIR3/2
LBPDIR1/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 20-49. Loop Back Pair Direction Register (HETLBPDIR) Field Descriptions
Bit
Field
31-20
Reserved
19-16
LBPTSTENA
15-0
LBPDIR
n+1 / n
Value
0
Description
Reads return 0. Writes have no effect.
Loopback Test Enable Key
5h
Loopback Test is disabled.
Ah
Loopback Test is enabled.
Others
Loopback Test is disabled.
Loop Back Pair Direction Bits
0
The HR structures on pins HET[n+1] and HET[n] are internally connected with HET[n] as input and
HET[n+1] as output.
1
The HR structures on pins HET[n+1] and HET[n] connected with HET[n] as output and HET[n+1]
as input.
NOTE: The loop back direction can be selected independent on the HETDIR register setting.
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20.4.33 N2HET Pin Disable Register (HETPINDIS)
N2HET1: offset = FFF7 B894h; N2HET2: offset = FFF7 B994h
Figure 20-88. N2HET Pin Disable Register (HETPINDIS)
31
16
HETPINDIS
R/W-0
15
0
HETPINDIS
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-50. NHET Pin Disable Register (HETPINDIS) Field Descriptions
Bit
31-0
Field
Value
HETPINDIS[n]
Description
N2HET Pin Disable Bits
0
Logic low: No affect on the output buffer enable of the pin (is controlled by the value of the
HETDIR[n] bit).
1
Logic high: Output buffer of the pin is enabled if pin nDIS = 1, HET_PIN_ENA = 1, and HETDIR =
1; or disabled if nDIS = 0, HETDIR = 0, or HET_PIN_ENA = 0.
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20.5 HWAG Registers
Table 20-51 lists the HWAG registers.
Table 20-51. HWAG Registers
Offset
882
Acronym
Register Description
9Ch
HWAPINSEL
HWAG Pin Select Register
Section 20.5.1
Section
A0h
HWAGCR0
HWAG Global Control Register 0
Section 20.5.2
A4h
HWAGCR1
HWAG Global Control Register 1
Section 20.5.3
A8h
HWAGCR2
HWAG Global Control Register 2
Section 20.5.4
ACh
HWAENASET
HWAG Interrupt Enable Set Register
Section 20.5.5
B0h
HWAENACLR
HWAG Interrupt Enable Clear Register
Section 20.5.6
B4h
HWALVLSET
HWAG Interrupt Level Set Register
Section 20.5.7
B8h
HWALVLCLR
HWAG Interrupt Level Clear Register
Section 20.5.8
BCh
HWAFLG
HWAG Interrupt Flag Register
Section 20.5.9
C0h
HWAOFF0
HWAG Interrupt Offset Register 1
Section 20.5.10
C4h
HWAOFF1
HWAG Interrupt Offset Register 2
Section 20.5.11
C8h
HWAACNT
HWAG Angle Value Register
Section 20.5.12
CCh
HWAPCNT1
HWAG Previous Tooth Period Value Register
Section 20.5.13
D0h
HWAPCNT
HWAG Current Tooth Period Value Register
Section 20.5.14
D4h
HWASTWD
HWAG Step Width Register
Section 20.5.15
D8h
HWATHNB
HWAG Teeth Number Register
Section 20.5.16
DCh
HWATHVL
HWAG Current Teeth Number Register
Section 20.5.17
E0h
HWAFIL
HWAG Filter Register
Section 20.5.18
E8h
HWAFIL2
HWAG Filter Register 2
Section 20.5.19
F0h
HWAANGI
HWAG Angle Increment Register
Section 20.5.20
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20.5.1 HWAG Pin Select Register (HWAPINSEL)
Figure 20-89. HWAG Pin Select Register (HWAPINSEL)
31
16
Reserved
R-0
15
5
4
0
Reserved
PINSEL
R-0
R/W-2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-52. HWAG Pin Select Register (HWAPINSEL) Field Descriptions
Bit
Field
31-5
Reserved
4-0
PINSEL
Value
0
Description
Reads return 0. Writes have no effect.
HWAG Pin Select. Selects from which NHET pin input buffer the HWAG toothed-wheel signal is
derived.
0
Read: Pin HET[0] is selected.
Write: Selects pin HET[0].
1h
Read: Pin HET[1] is selected
Write: Selects pin HET[1].
2h
Read: Pin HET[2] is selected
Write: Selects pin HET[2]. Default after reset for backwards compatibility
:
1Fh
:
Read: Pin HET[31] selected
Write: Selects pin HET[31].
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20.5.2 HWAG Global Control Register 0 (HWAGCR0)
Figure 20-90. HWAG Global Control Register 0 (HWAGCR0)
31
16
Reserved
R-0
15
1
0
Reserved
RESET
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-53. HWAG Global Control Register 0 (HWAGCR0) Field Descriptions
Bit
31-1
0
Field
Reserved
Value
0
RESET
Description
Reads return 0. Writes have no effect.
HWAG Module Reset.
0
HWAG module is reset.
1
HWAG module is not in reset.
20.5.3 HWAG Global Control Register 1 (HWAGCR1)
Figure 20-91. HWAG Global Control Register 1 (HWAGCR1)
31
16
Reserved
R-0
15
1
0
Reserved
PPWN
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-54. HWAG Global Control Register 1 (HWAGCR1) Field Descriptions
Bit
31-1
0
884
Field
Value
Description
Reserved
0
Reads return 0. Writes have no effect.
PPWN
0
HWAG Module Power Down. This bit is implemented for legacy purposes, but has no functionality,
however the HWAG module power down is controlled by the NHET power down. The HWAG
cannot be powered down separately.
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20.5.4 HWAG Global Control Register 2 (HWAGCR2)
Figure 20-92. HWAG Global Control Register 2 (HWAGCR2)
31
17
16
Reserved
25
ARST
Reserved
TED
CRI
R-0
R/W-0
R-0
R/W-0
R/W-0
1
0
15
9
24
8
23
18
7
Reserved
FIL
Reserved
STRT
R-0
R/W-0
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-55. HWAG Global Control Register 2 (HWAGCR2) Field Descriptions
Bit
31-25
24
Field
Value
Reserved
0
ARST
Description
Reads return 0. Writes have no effect.
Angle Reset. This bit is used by the HWAG to validate the singularity when the hardware criteria is
not used. The bit is cleared when the HWAG angle value register (HWAACNT) is cleared by the
HWAG, when the last tooth edge occurs.
If this bit is not set before the tooth edge during an singularity tooth, the HWAG generates an
interruption “singularity not found”, if the interrupt is enabled.
23-18
17
16
15-9
8
7-1
0
Reserved
0
Do not reset ACNT once it reaches the angle zero point.
1
Reset ACNT once it reaches the angle zero point.
0
Reads return 0. Writes have no effect.
TED
Tooth Edge. This bit is used to select which edge of the tooth wheel must be considered as active.
0
Falling edge
1
Rising edge
CRI
Reserved
Criteria enable. This bits is used to control whether the criteria are applied. You could set your own
criteria filter by disabling the hardwired criteria.
0
Criteria is disabled.
1
Criteria is enabled.
0
Reads return 0. Writes have no effect.
FIL
Reserved
Input Filter Enable. This bit is used to enable the toothed wheel input filter.
0
Filter is disabled.
1
Filter is enabled.
0
Reads return 0. Writes have no effect.
STRT
Start bit. Put the HWAG into run time. Allows the HWAG to start counting ACNT, TCNT and criteria
mechanism (if set). The HWAG starts at the next active edge from the toothed wheel, once set. If
the start bit is cleared to 0, the HWAG is stopped immediately.
0
Do not start counting.
1
Start counting.
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20.5.5 HWAG Interrupt Enable Set Register (HWAENASET)
Figure 20-93. HWAG Interrupt Enable Set Register (HWAENASET)
31
8
Reserved
R-0
7
6
5
4
3
2
1
0
SETINTENA7
SETINTENA6
SETINTENA5
SETINTENA4
SETINTENA3
SETINTENA2
SETINTENA1
SETINTENA0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-56. HWAG Interrupt Enable Set Register (HWAENASET) Field Descriptions
Bit
Field
31-8
Reserved
7-0
SETINTENA[n]
Value
0
Description
Reads return 0. Writes have no effect.
Enable interrupt. See Table 20-57.
0
Read: Corresponding interrupt is not enabled.
Write: No effect.
1
Read: Corresponding interrupt is enabled.
Write: Enable corresponding interrupt.
Table 20-57. HWAG Interrupts
Bit
886
Interrupt
0
Overflow period
1
Singularity not found
2
Tooth interrupt
3
ACNT overflow
4
PCNT(n) > 2 x PCNT (n-1) during normal tooth
5
Bad active edge tooth
6
Gap flag
7
Angle increment overflow
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20.5.6 HWAG Interrupt Enable Clear Register (HWAENACLR)
Figure 20-94. HWAG Interrupt Enable Clear Register (HWAENACLR)
31
8
Reserved
R-0
7
6
5
4
3
2
1
0
CLRINTENA7
CLRINTENA6
CLRINTENA5
CLRINTENA4
CLRINTENA3
CLRINTENA2
CLRINTENA1
CLRINTENA0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-58. HWAG Interrupt Enable Clear Register (HWAENACLR) Field Descriptions
Bit
Field
31-8
Reserved
7-0
CLRINTENA[n]
Value
0
Description
Reads return 0. Writes have no effect.
Disable interrupt. See Table 20-57.
0
Read: Corresponding interrupt is not enabled.
Write: No effect.
1
Read: Corresponding interrupt is enabled.
Write: Disable corresponding interrupt.
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20.5.7 HWAG Interrupt Level Set Register (HWALVLSET)
Figure 20-95. HWAG Interrupt Level Set Register (HWALVLSET)
31
8
Reserved
R-0
7
6
5
4
3
2
1
0
SETINTLVL7
SETINTLVL6
SETINTLVL5
SETINTLVL4
SETINTLVL3
SETINTLVL2
SETINTLVL1
SETINTLVL0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-59. HWAG Interrupt Level Set Register (HWALVLSET) Field Descriptions
Bit
Field
Value
31-8
Reserved
7-0
SETINTLVL[n]
0
Description
Reads return 0. Writes have no effect.
Set Interrupt Level. See Table 20-57.
0
Read: Low-priority interrupt.
Write: No effect.
1
Read: High-priority interrupt.
Write: Set interrupt priority to high.
20.5.8 HWAG Interrupt Level Clear Register (HWALVLCLR)
Figure 20-96. HWAG Interrupt Level Clear Register (HWALVLCLR)
31
8
Reserved
R-0
7
6
5
4
3
2
1
0
CLRINTLVL7
CLRINTLVL6
CLRINTLVL5
CLRINTLVL4
CLRINTLVL3
CLRINTLVL2
CLRINTLVL1
CLRINTLVL0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-60. HWAG Interrupt Level Clear Register (HWALVLCLR) Field Descriptions
Bit
Field
31-8
Reserved
7-0
CLRINTLVL[n]
Value
0
Description
Reads return 0. Writes have no effect.
Clear Interrupt Level. See Table 20-57.
0
Read: Low-priority interrupt.
Write: No effect.
1
Read: High-priority interrupt.
Write: Set interrupt priority to low.
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20.5.9 HWAG Interrupt Flag Register (HWAFLG)
Figure 20-97. HWAG Interrupt Flag Register (HWAFLG)
31
8
Reserved
R-0
7
6
5
4
3
2
1
0
INTFLG7
INTFLG6
INTFLG5
INTFLG4
INTFLG3
INTFLG2
INTFLG1
INTFLG0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear; -n = value after reset
Table 20-61. HWAG Interrupt Flag Register (HWAFLG) Field Descriptions
Bit
Field
31-8
Reserved
7-0
INTFLG[n]
Value
0
Description
Reads return 0. Writes have no effect.
Interrupt Flag. These bit are set when an interrupt condition has occurred inside the HWAG. The
interrupt is sent to the CPU if, and only if, the corresponding enable bit is set. HWAFLG is cleared
by either reading the HWAOFF0 or HWAOFF1 register (if the corresponding bit is set) or by writing
1 to the bit. If HWAFLG is 1 but the corresponding interrupt is not enabled then it will not generate
an interrupt, also the OFFSET index will not be generated for that particular HWAFLG bit. So, a
read of HWAOFF registers will not clear a HWAFLG bit that is not enabled. See Table 20-57.
0
Read: No interrupt is pending.
Write: No effect.
1
Read: Interrupt is pending.
Write: Clear the corresponding interrupt flag.
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20.5.10 HWAG Interrupt Offset Register 0 (HWAOFF0)
This register is a read-only register and provides a numerical value that represents the pending interrupt
with a high priority. The index can be used to locate the interrupt routine position in the vector table. A
read to this register clears the corresponding interrupt pending bit in the HWAG interrupt flag register
(HWAFLG). An interrupt pending bit in the HWAFLG register is the bit for which the corresponding
interrupt enable bit is set.
During suspend mode, a read to this register does not clear the corresponding interrupt bit.
Figure 20-98. HWAG Interrupt Offset Register 0 (HWAOFF0)
31
16
Reserved
R-0
15
8
7
0
Reserved
OFFSET1
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 20-62. HWAG Interrupt Offset Register 0 (HWAOFF0) Field Descriptions
Bit
Field
31-8
Reserved
7-0
OFFSET1
890
Value
0
Description
Reads return 0. Writes have no effect.
High-Priority Interrupt Offset. These bits give the offset for the corresponding interrupts.
0
Phantom interrupt
1
Overflow period
2
Singularity not found
3
Tooth interrupt
4
ACNT overflow
5
PCNT(n) > 2 × PCNT (n-1) during normal tooth
6
Bad active edge tooth
7
Gap flag
8
Angle increment overflow
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20.5.11 HWAG Interrupt Offset Register 1 (HWAOFF1)
This register is a read-only register and provides a numerical value that represents the pending interrupt
with a low priority. The index can be used to locate the interrupt routine position in the vector table. A read
to this register clears the corresponding interrupt pending bit in the HWAG interrupt flag register
(HWAFLG). An interrupt pending bit in the HWAFLG register is the bit for which the corresponding
interrupt enable bit is set.
During suspend mode, a read to this register does not clear the corresponding interrupt bit.
Figure 20-99. HWAG Interrupt Offset Register 1 (HWAOFF1)
31
16
Reserved
R-0
15
8
7
0
Reserved
OFFSET2
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 20-63. HWAG Interrupt Offset Register 1 (HWAOFF1) Field Descriptions
Bit
Field
31-8
Reserved
7-0
OFFSET2
Value
0
Description
Reads return 0. Writes have no effect.
Low-Priority Interrupt Offset.. These bits give the offset for the corresponding interrupts.
0
Phantom interrupt
1
Overflow period
2
Singularity not found
3
Tooth interrupt
4
ACNT overflow
5
PCNT(n) > 2 × PCNT (n-1) during normal tooth
6
Bad active edge tooth
7
Gap flag
8
Angle increment overflow
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20.5.12 HWAG Angle Value Register (HWAACNT)
Figure 20-100. HWAG Angle Value Register (HWAACNT)
31
24
23
16
Reserved
ACNT
R-0
R/W-0
15
0
ACNT
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-64. HWAG Angle Value Register (HWAACNT) Field Descriptions
Bit
Field
31-24
Reserved
23-0
ACNT
892
Value
0
0-FF FFFFh
Description
Reads return 0. Writes have no effect.
Angle Value. Provides the current angle value from the toothed wheel. This is equal to step
width × teeth value.
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20.5.13 HWAG Previous Tooth Period Value Register (HWAPCNT1)
Figure 20-101. HWAG Previous Tooth Period Value Register (HWAPCNT1)
31
24
23
16
Reserved
PCNT(n-1)
R-0
R/W-0
15
0
PCNT(n-1)
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-65. HWAG Previous Tooth Period Value Register (HWAPCNT1) Field Descriptions
Bit
Field
Value
31-24
Reserved
0
23-0
PCNT(n-1)
0-FF FFFFh
Description
Reads return 0. Writes have no effect.
Period (n-1) Value. Gives the period value of the previous tooth.
20.5.14 HWAG Current Tooth Period Value Register (HWAPCNT)
Figure 20-102. HWAG Current Tooth Period Value Register (HWAPCNT)
31
24
23
16
Reserved
PCNT(n)
R-0
R/W-0
15
0
PCNT(n)
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-66. HWAG Current Tooth Period Value Register (HWAPCNT) Field Descriptions
Bit
Field
Value
31-24
Reserved
0
23-0
PCNT(n)
0-FF FFFFh
Description
Reads return 0. Writes have no effect.
Period (n) Value. Provides the current period since the beginning of the last tooth active
edge seen by the HWAG (PCNT (n)).
This period would not be accurate due to the fact that the PCNT counter is running at VCLK2
and that the peripheral bus is running at VCLK. Then, the value will have changed when
used.
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20.5.15 HWAG Step Width Register (HWASTWD)
Figure 20-103. HWAG Step Width Register (HWASTWD)
31
16
Reserved
R-0
15
4
3
0
Reserved
STWD
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-67. HWAG Step Width Register (HWASTWD) Field Descriptions
Bit
Field
Value
Description
31-4
Reserved
Reads return 0. Writes have no effect.
3-0
STWD
Step Width. Sets the step width for the tick generation, dividing the period into K steps. (131072,
65536, ..., 8, 4). The step count is decoded from the three LSBs using the following encoding:
0h
4 ticks per period
1h
8 ticks per period
2h
16 ticks per period
:
894
:
Eh
65536 ticks per period
Fh
131072 ticks per period
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20.5.16 HWAG Teeth Number Register (HWATHNB)
Figure 20-104. HWAG Teeth Number Register (HWATHNB)
31
16
Reserved
R-0
15
8
7
0
Reserved
THNB
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-68. HWAG Teeth Number Register (HWATHNB) Field Descriptions
Bit
Field
Value
31-8
Reserved
7-0
THNB
0
0-FFh
Description
Reads return 0. Writes have no effect.
Teeth Number. Sets the teeth number with the maximum value of the toothed wheel. This
must be equal to N-1 real teeth (that is, 57 for a 60-2 toothed wheel).
20.5.17 HWAG Current Teeth Number Register (HWATHVL)
Figure 20-105. HWAG Current Teeth Number Register (HWATHVL)
31
16
Reserved
R-0
15
8
7
0
Reserved
THVL
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-69. HWAG Current Teeth Number Register (HWATHVL) Field Descriptions
Bit
Field
31-8
Reserved
7-0
THVL
Value
0
0-FFh
Description
Reads return 0. Writes have no effect.
Teeth Value. Provides the current teeth number.
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20.5.18 HWAG Filter Register (HWAFIL)
Figure 20-106. HWAG Filter Register (HWAFIL)
31
16
Reserved
R-0
15
10
9
0
Reserved
FIL1
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-70. HWAG Filter Register (HWAFIL) Field Descriptions
Bit
31-10
9-0
Field
Value
Reserved
0
FIL1
Description
Reads return 0. Writes have no effect.
0-3FFh
Filter Value. Contains the value to be compared to the tick counter. It allows the tooth signal
to be taken into account by the HWAG. This function works only if the mode filtering is set.
The value is calculated as shown in Section 20.3.2.2.5.
20.5.19 HWAG Filter Register 2 (HWAFIL2)
Figure 20-107. HWAG Filter Register 2 (HWAFIL2)
31
16
Reserved
R-0
15
12
11
0
Reserved
FIL2
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-71. HWAG Filter Register 2 (HWAFIL2) Field Descriptions
Bit
Field
31-12
Reserved
11-0
FIL2
896
Value
0
0-FFFh
Description
Reads return 0. Writes have no effect.
Filter Value 2. Contains the value to be compared to the tick counter during the singularity
tooth. It allows the tooth signal to be taken into account by the HWAG. This function works
only if the mode filtering is set. The value is calculated as shown in Section 20.3.2.2.5.1.
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20.5.20 HWAG Angle Increment Register (HWAANGI)
Figure 20-108. HWAG Angle Increment Register (HWAANGI)
31
16
Reserved
R-0
15
10
9
0
Reserved
ANGI
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 20-72. HWAG Angle Increment Register (HWAANGI) Field Descriptions
Bit
31-10
9-0
Field
Reserved
ANGI
Value
0
0-3FFh
Description
Reads return 0. Writes have no effect.
Angle Increment Value. Provides the current angle increment value. The value is
incremented by the tick counter and is decremented by the NHET resolution clock.
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20.6 Instruction Set
20.6.1 Instruction Summary
Table 20-73 presents a list of the instructions in the N2HET instruction set. The pages following describe
each instruction in detail.
Table 20-73. Instruction Summary
(1)
898
Abbreviation
Instruction Name
Opcode
Sub-Opcode
Cycles (1)
ACMP
Angle Compare
Ch
-
1
ACNT
Angle Count
9h
-
2
ADCNST
Add Constant
5h
-
2
ADC
Add with Carry and Shift
4h
C[25:23] = 011, C5 = 1
1-3
ADD
Add and Shift
4h
C[25:23] = 001, C5 = 1
1-3
ADM32
Add Move 32
4h
C[25:23] = 000, C5 = 1
1-2
AND
Bitwise AND and Shift
4h
C[25:23] = 010, C5 = 1
1-3
APCNT
Angle Period Count
Eh
-
1-2
BR
Branch
Dh
-
1
CNT
Count
6h
-
1-2
DADM64
Data Add Move 64
2h
-
2
DJZ
Decrement and Jump if -zero
Ah
P[7:6] = 10
1
ECMP
Equality Compare
0h
C[6:5] = 00
1
1
ECNT
Event Count
Ah
P[7:6] = 01
MCMP
Magnitude Compare
0h
C[6] = 1
1
MOV32
Move 32
4h
C[5] = 0
1-2
MOV64
Move 64
1h
-
1
OR
Bitwise OR
4h
C[25:23] = 100, C5 = 1
1-3
PCNT
Period/Pulse Count
7h
-
1
PWCNT
Pulse Width Count
Ah
P[7:6] = 11
1
RADM64
Register Add Move 64
3h
-
1
RCNT
Ratio Count
Ah
P[7:6] = 00, P[0] = 1
3
SBB
Subtract with Borrow and Shift
4h
C[25:23] =110, C[5] = 1
1-3
SCMP
Sequence Compare
0h
C[6:5] = 01
1
SCNT
Step Count
Ah
P[7:6] = 00, P[0] = 0
3
SHFT
Shift
Fh
C[3] = 0
1
SUB
Subtract and Shift
4h
C[25:23] = 101, C[5] = 1
1-3
1
WCAP
Software Capture Word
Bh
-
WCAPE
Software Capture Word and Event Count
8h
-
1
XOR
Bitwise Exclusive-Or and Shift
4h
C[25:23] = 111, C[5] = 1
1-3
Cycles refers to the clock cycle of the N2HET module; which on most devices is VCLK2. (Check the device datasheet
description of clock domains to confirm). If the high-resolution prescale value is set to /1, then this is also the same as the
number of HR clock cycles.
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Table 20-74. FLAGS Generated by Instruction
Abbreviation
Flag Name
Set/Reset by
Used by
C
Carry Flag
ADC, ADD, AND, OR, RCNT, SBB, SUB, XOR
ADC, BR, SBB
N
Negative Flag
ADC, ADD, AND, OR, SBB, SUB, XOR
BR
V
Overflow Flag
ADC, ADD, AND, OR, SBB, SUB, XOR
BR
Z
Zero flag
ACNT, ADC, ADD, AND, APCNT, CNT, OR, PCNT,
SBB, SCNT, SHFT, SUB, XOR
ACMP, ACNT, BR, ECMP,
MCMP, MOV32, RCNT,
SCMP, SHFT
X
Angle Compare Match
Flag
ACMP
SCMP
SWF 0-1
Step Width flags
SCNT
ACNT
NAF
New Angle Flag
ACNT
NAF_global
New Angle Flag (global)
HWAG or NAF
ACMP, BR, CNT, ECMP,
ECNT
,ACNT, SCNT
NAF_global
ACF
Acceleration Flag
ACNT
DCF
Deceleration Flag
ACNT
,ACNT, SCNT
GPF
Gap Flag
ACNT
ACNT, APCNT
The instructions capable of generating software interrupts are listed in Table 20-75.
Table 20-75. Interrupt Capable Instructions
Interrupt Capable Instructions
Non Interrupt Capable Instructions
ACMP
ADC
ACNT
ADCNST
APCNT
ADD
BR
ADM32
CNT
AND
DJZ
DADM32
ECMP
MOV32
ECNT
MOV64
MCMP
OR
PCNT
RADM64
PWCNT
RCNT
SCMP
SBB
SHFT
SCNT
WCAP
SUB
WCAPE
XOR
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20.6.2 Abbreviations, Encoding Formats and Bits
Abbreviations marked with a star (*) are available only on specific instructions.
U
Reading a bit marked with U will return an indeterminate value.
BRK
Defines the software breakpoint for the device software debugger.
Default: OFF
Location: Program field [22]
next
Defines the program address of the next instruction in the program flow. This value
may be a label or an 9-bit unsigned integer.
Default: Current instruction + 1
Location: Program field [21:13]
reqnum*
Defines the number of the request line (0,1,..,7) to trigger either the HTU or the DMA.
Default: 0
Location: Program field [25:23]
request*
Allows to select between no request (NOREQ), request (GENREQ) and quiet request
(QUIET). See Section 20.2.9.
Default: No request
Location: Control Field [28:27]
Request
C[28]
C[27]
0
0
1
0
GENREQ
0
1
request
request
QUIET
1
1
quiet request
no request
NOREQ
To HTU
To DMA
no request
no request
remote*
Determines the 9-bit address of the remote address for the instruction.
Default: Current instruction + 1
Location: Program field [8:0]
control
Determines whether the immediate data field [31:0] is cleared when it is read. When
the bit is not set, reads do not clear the immediate data field.
Default: OFF
Location: Control field [26]
en_pin_action* Determines whether the selected pin is ON so that the action occurs on the chosen pin
Default: OFF
Location: Control field [22]
900
Cond_addr*
Conditional address (optional): Defines the address of the next instruction when the
condition occurs.
Default: Current address + 1
Location: Control field [21:13]
Pin*
Pin Select: Selects the pin on which the action occurs. Enter the pin number.
Default: pin 0
Location: Control field [12:8] except PCNT
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The format CC{pin number} is also supported.
MSB
0
0
0
0
LSB
Description
0
0
0
Select HET[0]
0
0
1
Select HET[1]
(Each pin may be selected by writing its number in binary)
1
1
1
1
0
Select HET[30]
1
1
1
1
1
Select HET[31]
Reg*
Register select: Selects the register for data comparison and storage
Default: No register (None)
Location: Control field [2:1] except for CNT instruction.
Extended Register Select C[7] is available for ACMP, ADC, ADD, ADM32, AND,
DADM64, ECMP, ECNT, MCMP, MOV32, MOV64, OR, RADM64, SBB, SHFT, SUB,
WCAP, WCAPE instructions.
Register
Ext Reg. C[7]
C[2]
C[1]
A
0
0
0
B
0
0
1
T
0
1
0
None
0
1
1
R
1
0
0
S
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Action*
(2 Action Option) Either sets or clears the pin
Default: Clear
Location: Control Field [4]
Action*
Action
C[4]
Clear
0
Set
1
(4 Action Option) Either sets, clears, pulse high or pulse low on the pin. Set/clear are
single pin actions, pulse high/low include the opposite pin action.
Default: Clear
Location: Control Field [4:3]
Action
Action Type
C[4]
C[3]
Clear
Set low on match
0
0
Set
Set high on match
1
0
Pulse Low
Set low on match + reset to high on Z=1 (opposite action)
0
1
Pulse High
Set high on match + reset to low on Z=1 (opposite action)
1
1
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hr_lr*
902
Specifies HIGH/LOW data resolution. If the hr_lr field is HIGH, the instruction uses the
hr_data field. If the hr_lr field is LOW, the hr_data field is ignored.
Default: HIGH
Location: Program Field [8]
hr_lr
Prog. field [8]
LOW
1
HIGH
0
prv*
Specifies the initial value defining the previous bit (see Section 20.2.5.8). A value of
ON sets the previous pin-level bit to 1. A value of OFF sets the initial value of the
previous (prv) bit to 0. The prv bit is overwritten (set or reset) by the N2HET the first
time the instruction is executed.
Default: OFF
Location: Control Field [25]
cntl_val*
Available for DADM64, MOV64, and RADM64, this bit field allows the user to specify
the replacement value for the remote control field.
comp_mode*
Specifies the compare mode. This field is used with the 64-bit move instructions. This
field ensures that the sub-opcodes are moved correctly.
Default: ECMP
Location: Control Field [6:5]
Action
C[6]
C[5]
ECMP
0
0
Order
SCMP
0
1
MCMP1
1
0
REG_GE_DATA
MCMP2
1
1
DATA_GE_REG
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20.6.3 Instruction Description
The following sections provide information for individual instructions.
Parameters in [] are optional. Refer to the N2HET assembler user guide for the default values when
parameters are omitted.
20.6.3.1 ACMP (Angle Compare)
Syntax
ACMP {
[brk={OFF | ON}]
[next={label | 9-bit unsigned integer}]
[reqnum={3-bit unsigned integer}]
[request={NOREQ | GENREQ | QUIET}]
[control={OFF | ON}]
[en_pin_action={OFF | ON}]
[cond_addr={label | 9-bit unsigned integer}]
pin={pin number}
[action={CLEAR | SET}]
reg={A | B | R | S | T | NONE}
[irq ={OFF | ON}]
data={25-bit unsigned integer}
}
Figure 20-109. ACMP Program Field (P31:P0)
31
26 25
23
22
21
13 12
9
8
0
0
Request
Number
BRK
Next program address
1100
Reserved
6
3
1
9
4
9
Figure 20-110. ACMP Control Field (C31:C0)
31
29
26
25
Reserved
Request type
Control
Cout
prv
Reserved
En. pin
action
Conditional address
3
2
1
1
2
1
9
15
13
28
27
12
24
8
23
7
22
21
6
5
16
4
3
Conditional address
Pin select
Ext.
Reg
Reserved
Pin
action
Res.
Register select
2
1
Int.
ena
0
9
5
1
2
1
1
2
1
Figure 20-111. ACMP Data Field (D31:D0)
31
7
6
0
Data
Reserved
25
7
Cycles
One
Register modified
Selected register (A, B, R, S, or T)
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The purpose of the comparison is to assert pin action when the angle compare value lies between the old
counter value and the new counter value (held in the selected register). Since the angle increment varies
from one loop resolution clock to another, an exact equality test cannot be applied. Instead, the following
inequality is used to determine the occurrence of a match:
Old counter value < Angle compare value ≤ New counter value
This is done by performing following comparisons:
Selected register value minus angle increment < angle compare value
Angle compare value ≤ Selected register value
register
Register B is recommended for typical applications with ACMP.
irq
Specifies whether or not an interrupt is generated. Specifying ON
generates an interrupt when the edge state is satisfied and the gap
flag is set. Specifying OFF prevents an interrupt from being
generated.
Default: OFF.
data
Specifies the 25-bit angle compare value.
Execution
X = 0;
If (Data 0) {
IR2[31 : 31 - scount + 1] = IR1[31]
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IC2 = IR1[scount-1]
}
else {
IC2 = IC1
}
IN2 = IR2[31];
if (IR2 == 0) { IZ2 = 1 } else {IZ2 = 0};
IV2 = (IR2[31] XOR IR1[31]) OR IV1
case 010: // smode = Logical Shift Left
IR2[31 : scount] = IR1[31 - scount: 0]
if (scount > 0) {
IR2[scount - 1 : 0] = 0
}
IC2 = IC1
IN2 = IR2[31];
if (IR2 == 0) { IZ2 = 1 } else {IZ2 = 0};
IV2 = (IR2[31] XOR IR1[31]) OR IV1
case 011: // smode = Carry Shift Left
IR2[31 : scount] = IR1[31 - scount: 0]
if (scount>0) {
IR2[scount - 1 : 0] = [IC1,...IC1]
IC2 = IR1[31 - scount + 1]
}
else
{
IC2 = IC1
}
IN2 = IR2[31];
if (IR2 == 0) { IZ2 = 1 } else {IZ2 = 0};
IV2 = (IR2[31] XOR IR1[31]) OR IV1
case 100: // smode = Logical Shift Right
IR2[31 - scount : 0] = IR1[31:scount]
if (scount>0) {
IR2[31 : 31 - scount + 1] = 0
}
IC2 = IC1
IN2 = IR2[31];
if (IR2 == 0) { IZ2 = 1 } else {IZ2 = 0};
IV2 = (IR2[31] XOR IR1[31]) OR IV1
case 101: // smode = Carry Shift Right
IR2[31 - scount : 0] = IR1[31:scount]
if(scount>0) {
IR2[31:31-scount + 1] = [IC1,...IC1]
IC2 = IR1[scount-1]
}
else {
IC2 = IC1
}
IN2 = IR2[31];
IZ2 = Set if IR2 == 0;
IV2 = (IR2[31] XOR IR1[31]) OR IV1
case 110: // smode = Rotate Right
914
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IR2[31 - scount : 0] = IR1[31:scount]
if(scount>0) {
IR2[31:31-scount+1] = IR1[scount-1:0]
IC2 = IR1[scount-1]
}
else {
IC2 = IC1
}
IN2 = IR2[31];
if (IR2 == 0) { IZ2 = 1 } else {IZ2 = 0};
IV2 = (IR2[31] XOR IR1[31]) OR IV1
case 111: // smode = Carry Rotate Right
IR2[31 - scount : 0] = IR1[31:scount]
if (scount == 0) {
IC2 = IC1
}
else if (scount == 1) {
IR2[31] = IC1
IC2 = IR1[0]
}
else {
IR2[31:31-scount+1] = {IR1[scount-2:0],IC1}
IC2 = IR1[scount - 1]
}
IN2 = IR2[31];
if (IR2 == 0) { IZ2 = 1 } else {IZ2 = 0};
IV2 = (IR2[31] XOR IR1[31]) OR IV1
}
/********** WRITE REGISTER DESTINATION STAGE ***********/
switch (C7, C2:C1)
{
case 000:A[24:0] = IR2[31:8]
case 001:B[24:0] = IR2[31:8]
case 010:T[31:0] = IR2[31:0]
case 011:IR2 is not stored in register, immediate
case 100:R[31:0] = IR2[31:0]
case 101:S[31:0] = IR2[31:0]
case 110:Immediate Data Field[31:0] = IR2
case 111:IR2 is not stored in register, immediate
}
/*********** WRITE REMOTE DESTINATION STAGE ***********/
switch (C4:3)
{
case
case
case
case
00:IR2 is
01:Remote
10:Remote
11:IR2 is
not stored in remote
Data Field D[31:0] =
Program Field P[8:0]
not stored in remote
field
IR2
= IR2[8:0]
field
}
/***************** UPDATE FLAGS STAGE *****************/
C FLAG = IC2
N FLAG = IN2
Z FLAG = IZ2
V FLAG = IV2
If (Init Flag == 1)
{
ACF = 0;
DCF = 1;
GPF = 0;
NAF = 0;
}
else ACF, DCF, GPF, NAF remain unchanged;
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20.6.3.5 ADM32 (Add Move 32)
Syntax
ADM32 {
[brk={OFF | ON}]
[next={label | 9-bit unsigned integer}]
remote={label | 9-bit unsigned integer}
[control={OFF | ON}]
[init={OFF | ON}]
type={IM®TOREG | REM®TOREG | IM&REMTOREG |
IM®TOREM}
reg={A | B | R | S | T }
data={25-bit unsigned integer}
[hr_data={7-bit unsigned integer}]
}
Figure 20-123. ADM32 Program Field (P31:P0)
31
26 25
23
22
21
13 12
9
8
0
0
Reserved
BRK
Next program address
0100
Remote address
6
3
1
9
4
9
Figure 20-124. ADM32 Control Field (C31:C0)
31
27
26
25
23
22
16
Reserved
Control
000
Reserved
5
1
3
15
15
7
6
5
4
Reserved
8
Ext Reg
Init flag
1
Move type
3
Register select
2
1
Res.
0
15
1
1
1
2
2
1
Figure 20-125. ADM32 Data Field (D31:D0)
31
7
0
HR Data
25
7
Cycles
One or two cycles (see Table 20-81)
Register modified
Selected register (A, B, R, S, or T)
Description
This instruction modifies the selected ALU register or data field values at the
remote address depending on the move type. The modified value results from
adding the immediate or remote data field to the ALU register or the remote
data field, depending on the move type. Table description shows the C2 and
C1 bit encoding for determining which register is selected.
init
916
6
Data
(Optional) Determines whether or not system flags are initialized. A
value of ON reinitializes the following system flags to these states:
Acceleration flag (ACF) = 0
Deceleration flag (DCF) = 1
Gap flag (GPF) = 0
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New angle flag (NAF) = 0
A value of OFF results in no change to the system flags.
Default: OFF
type
Specifies the move type to be executed.
Table 20-81. Move Types for ADM32
Type
C4
C3
Add
Destination(s)
Cycles
Register A, B, R, S, or T
1
IM®TOREG
0
0
Imm. data field + Reg. A, B, R, S,
or T
REM®TOREG
0
1
Remote data field + Reg. A, B, R,
S, or T
Register A, B, R, S, or T
2
IM&REMTOREG
1
0
Imm. data field + Remote data
field
Register A, B, R, S, or T
2
IM®TOREM
1
1
Imm. data field + Reg. A, B, R, S,
or T
Remote data field
1
If selected register is R, S, or T, the operation is a 32-bit Addition/move. If A or B register is selected, it is
limited to 25-bit operation since A and B only support 25-bit.
data
Specifies the 25-bit integer value for the immediate data field.
hr_data
Specifies the 7 least significant bits of the immediate data field.
Default: 0.
Execution
switch (C4:C3)
{
case 00:
Selected register
case 01:
Selected register
case 10:
Selected register
case 11:
Remote Data Field
}
= Selected register + Immediate Data Field;
= Selected register + Remote Data Field;
= Immediate Data Field + Remote Data Field;
= Selected register + Immediate Data Field;
If (Init Flag == 1)
{
ACF = 0;
DCF = 1;
GPF = 0;
NAF = 0;
}
else
All flags remain unchanged;
Jump to Next Program Address;
Figure 20-126 and Figure 20-127 illustrate the ADM32 operation for various cases.
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Figure 20-126. ADM32 Add and Move Operation for IM®TOREG (Case 00)
25/32-bit addition/move
LSBs (HR data field)
32 bits
HR
Immediate DF
+
HR
Register A, B, R, S or T
(dashed for R, S, T)
=
HR
Register A, B, R, S or T
(dashed for R, S, T)
Figure 20-127. ADM32 Add and Move Operation for REM®TOREG (Case 01)
25/32-bit addition/move
LSBs (HR data field)
32 bits
918
HR
Remote DF
+
HR
Register A, B, R, S, or T
(dashed for R, S, T)
=
HR
Register A, B, R, S, or T
(dashed for R, S, T)
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20.6.3.6 APCNT (Angle Period Count)
Syntax
APCNT {
[brk={OFF | ON}]
[next={label | 9-bit unsigned integer}]
[reqnum={3-bit unsigned integer}]
[request={NOREQ | GENREQ | QUIET}]
[irq={OFF | ON}]
type={FALL2FALL | RISE2RISE}
[control={OFF | ON}]
prv={OFF | ON}}]
period={25-bit unsigned integer}
data={25-bit unsigned integer}
}
Figure 20-128. APCNT Program Field (P31:P0)
31
26 25
23
22
21
13 12
9
8
7
6
5
0
0
Request
Number
BRK
Next program address
1110
Int.
ena
Edge
select
Reserved
6
3
1
9
4
1
2
6
Figure 20-129. APCNT Control Field (C31:C0)
31
29 28
27
26
Res.
Request
type
Control
3
2
1
25
24
0
Prv.
Period Count
1
25
Figure 20-130. APCNT Data Field (D31:D0)
31
7
6
0
Data
Reserved
25
7
Cycles
One or two cycles
• Cycle 1: edge detected (normal operation)
• Cycle 2: edge detected and GPF = 1 and underflow condition is true
One cycle (normal operation) two cycles (edge detected)
Register modified
Register A and T (implicitly)
Description
This instruction is used before SCNT and ACNT to generate an anglereferenced time base synchronized to an external signal (that is, a toothed
wheel signal). It is assumed that the pin and edge selections are the same for
APCNT and ACNT.
APCNT is restricted to pin HET[2]. The toothed wheel must then be connected
to pin HET[2].
APCNT uses the gap flag (GPF) defined by ACNT to start or stop captures in
the period count field [C24:C0]. When GPF = 1, the previous period value is
held in the control field and in register T. When GPF = 0, the current period
value is captured in the control field and in register T.
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APCNT uses the step width flags (SWF0 and SWF1) defined by SCNT to
detect period durations shorter than one step, and then disables capture.
The edge select encoding is shown in Table 20-82.
irq
ON generates an interrupt when the edge state is satisfied. OFF
prevents an interrupt from being generated.
Default: OFF.
type
Specifies the edge type that triggers the instruction.
Default: Fall2Fall.
Table 20-82. Edge Select Encoding for APCNT
920
type
P7
P6
Selected Condition
Fall2Fall
1
0
Falling edge
Rise2Rise
1
1
Rising edge
period
Contains the 25-bit count value from the previous APCNT period.
data
25-bit value serving as a counter.
Default: 0.
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Execution
Z = 0;
If (Data field register != 1FFFFFFh)
{
Register A = Data field register + 1;
Data field register = Data field register + 1;
}
elseIf (specified edge not detected on HET[2])
{
Register A = 1FFFFFFh;
APCNT Ovflw flag = 1;
}
If (specified edge detected on HET[2])
{
Z = 1;
If (Data field register == 1FFFFFFh)
{
Register A = 1FFFFFFh;
Register T = 1FFFFFFh;Period count = 1FFFFFFh;
Period count = 1FFFFFFh;
}
elseIf (GPF == 0 AND Data Field register >= Step width)
{
Register A = Data field register + 1;
Register T = Register A;
Period count = Register T;
If (Interrupt Enable == 1)
HETFLG[n] = 1;
/* n depends on address */
If ([C28:C27] == 01)
Generate request on request line [P25:P23];
If ([C28:C27] == 11)
Generate quiet request on request line [P25:P23];
}
If (GPF == 1)
Register T = Period count;
If (Data Field register < Step width)
{
Register T = Period count;
APCNT Undflw flag = 1;
Period Count = 000000h;
}
Data field register = 000000h;
}
else
{
Register T = Period count;
}
Prv bit = Current Lx value of HET[2] pin;
Jump to Next Program Address;
The specific interrupt flag that is triggered depends on the address from which the instruction is executed,
see Section 20.2.7.
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20.6.3.7 BR (Branch)
Syntax
BR {
[brk={OFF | ON}]
[next={label | 9-bit unsigned integer}]
[reqnum={3-bit unsigned integer}]
[request={NOREQ | GENREQ | QUIET}]
[control={OFF | ON}]
[prv={OFF | ON}]
cond_addr={label | 9-bit unsigned integer}
[pin= {pin number}]
event={NOCOND | FALL | RISE | BOTH | ZERO | NAF | LOW | HIGH | C | NC
| EQ | Z | NE | NZ | N | PZ | V | NV | ZN | P | GE | LT | GT | LE | LO | HS }
[irq={OFF | ON}]
}
Figure 20-131. BR Program Field (P31:P0)
31
26 25
23
0
Request
Number
6
3
22
21
13 12
BRK
Next program address
1
9
8
0
1101
Reserved
4
9
9
Figure 20-132. BR Control Field (C31:C0)
31
29
28
27
26
25
Reserved
Request type
Control
Prv
3
2
1
1
15
13
12
24
22
Reserved
Pin select
9
5
16
Conditional address
3
8
Conditional address
21
9
7
3
Branch cond.
5
2
1
0
Reserved
Int. ena
2
1
Figure 20-133. BR Data Field (D31:D0)
31
0
Reserved
32
Cycles
One
Register modified
None
Description
This instruction executes a jump to the conditional address [C21:C13] on a pin
or a flag condition, and can be used with all pins.
Table 20-83 provides the branch condition encoding.
event
922
Specifies the event that triggers a jump to the indexed program
address.
Default: FALL
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irq
ON generates an interrupt when the event occurs that triggers the
jump. If irq is set to OFF, no interrupt is generated.
Default: OFF.
Table 20-83. Branch Condition Encoding for BR
Event
C7
C6
C5
C4
C3
NOCOND
0
0
0
0
0
Branch Condition
Always
FALL
0
0
1
0
0
On falling edge on the selected pin
RISE
0
1
0
0
0
On rising edge on selected pin
BOTH
0
1
1
0
0
On rising or falling edge on selected pin
ZERO
1
0
0
0
0
If Zero flag is set
NAF
1
0
1
0
0
If NAF_global flag is set
LOW
1
1
0
0
0
On LOW level on selected pin
HIGH
1
1
1
0
0
On HIGH level on selected pin
C
0
0
0
0
1
Carry Set: C==1
Carry Not Set: C==0
NC
0
0
0
1
1
EQ, Z
0
0
1
0
1
Equal or Zero: Z==1
NE, NZ
0
0
1
1
1
Not Equal or Not Zero: Z==0
N
0
1
0
0
1
Negative: N==1
PZ
0
0
1
1
1
Positive or Zero: N==0
V
0
1
1
0
1
Overflow: V==1
NV
0
1
1
1
1
No Overflow: V==0
ZN
1
0
0
0
1
Zero or Negative: (Z OR N) == 1
P
1
0
0
1
1
Positive: (Z OR N) == 0
GE
1
0
1
1
1
Signed Greater Than or Equal: (N XOR V) == 0
L
1
0
1
0
1
Signed Less Than (N XOR V) == 1
G
1
1
0
1
1
Signed Greater Than (Z OR (N XOR V)) == 0
LE
1
1
0
0
1
Signed Less Than (Z OR (N XOR V)) == 1
LO
1
1
1
1
1
Unsigned Less Than: (C OR Z) == 0
HS
1
1
1
0
1
Unsigned Higher or Same (C OR Z) == 1
Execution
If (Condition is true)
{
If (Interrupt Enable == 1) HETFLG[n] = 1;
/* n depends on address */
If ([C28:C27] == 01) Generate request on request line [P25:P23];
If ([C28:C27] == 11) Generate quiet request on request line [P25:P23];
Jump to Conditional Address;
}
else
{
Jump to Next Program Address;
}
Prv bit = Current Lx value of selected pin; (Always Executed)
The specific interrupt flag that is triggered depends on the address from which the instruction is executed,
see Section 20.2.7.
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20.6.3.8 CNT (Count)
Syntax
CNT {
[brk={OFF | ON}]
[next={label | 9-bit unsigned integer}]
[reqnum={3-bit unsigned integer}]
[request={NOREQ | GENREQ | QUIET}]
[angle_count={OFF | ON}]
[reg={A | B | T | NONE}]
[comp ={EQ | GE}]
[irq={OFF | ON}]
[control={OFF | ON}]
max={25-bit unsigned integer}
[data={25-bit unsigned integer]
}
Figure 20-134. CNT Program Field (P31:P0)
31
26 25
23
22
0
Request
Number
BRK
6
3
1
21
13 12
Next program address
9
9
0110
8
Angle
count
4
7
6
Register
1
2
5
4
Comp.
select
1
Res.
1
4
0
Int. ena
1
Figure 20-135. CNT Control Field (C31:C0)
31
29 28
27
26
Res.
Request
type
Control
3
2
1
25
24
0
Res.
Max Count
1
25
Figure 20-136. CNT Data Field (D31:D0)
31
924
7
6
0
Data
Reserved
25
7
Cycles
One or two
One cycle (time mode), two cycles (angle mode)
Register modified
Selected register (A, B or T)
Description
This instruction defines a virtual timer. The counter value stored in the data
field [D31:7] is incremented unconditionally on each execution of the
instruction when in time mode (angle count bit [P8] = 0). When the count
reaches the maximum count specified in the control field, the counter is reset.
It takes one cycle in this mode.
In angle mode (angle count bit [P8] = 1), CNT needs data from the software
angle generator (SWAG). When in angle count mode the angle increment
value will be 0 or 1. It takes two cycles in this mode.
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angle_count
Specifies when the counter is incremented. A value of ON causes the
counter value to be incremented only if the new angle flag is set
(NAF_global = 1). A value of OFF increments the counter each time
the CNT instruction is executed.
Default value for this field is OFF.
comp
When set to EQ the counter is reset, when it is equal to the maximum
count.
When set to GE the counter is reset, when it is greater or equal to the
maximum count.
Default: GE.
irq
ON generates an interrupt when the counter overflows to zero. The
interrupt is not generated until the data field is reset to zero. If irq is
set to OFF, no interrupt is generated.
Default: OFF.
max
Specifies the 25-bit integer value that defines the maximum count
value allowed in the data field. When the count in the data field is
equal to max, the data field is reset to 0 and the Z system flag is set
to 1.
data
Specifies the 25-bit integer value serving as a counter.
Default: 0.
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Execution
Z = 0;
If (Angle Count (bit P8 == 1))
{
If (NAF_global == 0)
{
Selected register = immediate data field;
Jump to Next Program Address;
}
else
{
If ((Immediate Data Field + Angle Increment) >= Max count)
{
Z = 1;
Selected register = ((Immediate Data Field + Angle Inc.) - Max count);
Immediate Data Field = ((Immediate Data Field + Angle Inc.) - Max count);
If (Interrupt Enable == 1) HETFLG[n] = 1;
/* n depends on address */
If ([C28:C27] == 01) Generate request on request line [P25:P23];
If ([C28:C27] == 11) Generate quiet request on request line [P25:P23];
}
else
{
Selected register = Immediate Data Field + Angle Increment;
Immediate Data Field = Immediate Data Field + Angle Increment;
}
}
}
else if(Time mode (bit P8 == 0))
{
If [(P5==0) AND (Immediate Data Field == Max count)]
OR [(P5==1) AND (Immediate Data Field >= Max count)]
{
Z = 1;
Selected register = 00000;
Immediate Data Field = 00000;
If (Interrupt Enable == 1) HETFLG[n] = 1;
/* n depends on address */
If ([C28:C27] == 01) Generate request on request line [P25:P23];
If ([C28:C27] == 11) Generate quiet request on request line [P25:P23];
}
else
{
Selected register = Immediate Data Field + 1;
Immediate Data Field = Immediate Data Field + 1;
}
}
Jump to Next Program Address;
The specific interrupt flag that is triggered depends on the address from which the instruction is executed,
see Section 20.2.7.
926
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20.6.3.9 DADM64 (Data Add Move 64)
Syntax
DADM64 {
[brk={OFF | ON}]
[next={label | 9-bit unsigned integer}]
remote={label | 9-bit unsigned integer}
[request={NOREQ | GENREQ | QUIET}]
[control={OFF | ON}]
[en_pin_action={OFF | ON}]
[cond_addr={label | 9-bit unsigned integer}]
[pin={pin number}]
comp_mode={ECMP | SCMP | MCMP1 | MCMP2}
[action={CLEAR | SET | PULSELO | PULSEHI}]
[reg={A | B | R | S | T | NONE}]
[irq={OFF | ON}]
[data={25-bit unsigned integer]
[hr_data= {7-bit unsigned integer}]
}
-orSyntax
DADM64 {
[brk={OFF | ON}]
[next={label | 9-bit unsigned integer}]
remote={label | 9-bit unsigned integer}
cntl_val={29-bit unsigned integer}
data={25-bit unsigned integer}
[hr_data= {7-bit unsigned integer}]
}
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Figure 20-137. DADM64 Program Field (P31:P0)
31
26 25
23
0
Reserved
6
3
22
21
BRK
13 12
Next program address
1
9
9
8
0
0010
Remote Address
4
9
Figure 20-138. DADM64 Control Field (C31:C0)
31
29
28
27
26
Reserved
Request type
Control
3
2
1
15
13
25
23
Reserved
22
3
12
8
21
16
En. pin
action
Conditional address
1
7
9
6
5
4
3
2
1
0
Conditional address
Pin select
Ext
Reg
Comp. mode
Action
Register select
Int.
ena
9
5
1
2
2
2
1
Figure 20-139. DADM64 Data Field (D31:D0)
31
7
6
0
Data
HR Data
25
7
Cycles
Two
Register modified
Register T (implicitly)
Description
This instruction modifies the data field and the control field at the remote
address. The remote data field value is not just replaced, but is added with the
DADM64 data field.
DADM64 has two distinct syntaxes. In the first syntax, bit values may be set
by assigning a value to each of the control fields. This syntax is convenient for
modifying control fields that are arranged similarly to the format of the
DADM64 control field. A second syntax, in which the entire 29-bit control field
is specified by the cntl_val field, is convenient when the remote control field is
dissimilar to the DADM64 control field. Either syntax may be used, but you
must use one or the other but not a combination of syntaxes.
Figure 20-140 shows the DADM64 add and move operation.
Figure 20-140. DADM64 Add and Move Operation
LSBs (HR Data Field)
32 bits
Immediate CF
Remote CF
HR
Immediate DF
+
HR
Remote DF
=
HR
Remote DF
Table 20-84. DADM64 Control Field Description
request
control
en_pin_action
cond_addr
maintains the control field for
maintains the control field for
maintains the control field for
maintains the control field for
the remote
the remote
the remote
the remote
instruction
instruction
instruction
instruction
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Table 20-84. DADM64 Control Field Description (continued)
pin
register
action
irq
data
hr_data
cntl_val
maintains the control field for the remote instruction
maintains the control field for the remote instruction
maintains the control field for the remote instruction
maintains the control field for the remote instruction
Specifies the 25-bit initial value for the data field.
Seven least significant bits of the 32 bit data field.
Default: 0
Specifies the 29 least significant bits of the Control field.
Execution
Remote Data Field = Remote Data Field + Immediate Data Field;
Register T = Immediate Data Field;
Remote Control Field = Immediate Control Field;
Jump to Next Program Address;
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20.6.3.10 DJZ (Decrement and Jump if Zero)
DJNZ is also a supported syntax. The functionality of the two instruction names is identical.
Syntax
DJZ {
[brk={OFF | ON}]
[next={label | 9-bit unsigned integer}]
[reqnum={3-bit unsigned integer}
[request={NOREQ | GENREQ | QUIET}]
[control={OFF | ON}]
[cond_addr={label | 9-bit unsigned integer}]
[reg={A | B | T | NONE}]
[irq={OFF | ON}]
[data={25-bit unsigned integer]
}
Figure 20-141. DJZ Program Field (P31:P0)
31
26 25
23
0
Request
Number
6
3
22
21
BRK
13 12
Next program address
1
9
9
8
7
6
5
0
1010
Res.
10
Reserved
4
1
2
6
Figure 20-142. DJZ Control Field (C31:C0)
31
29
28
27
26
25
22
21
16
Reserved
Request type
Control
Reserved
Conditional address
3
2
1
4
9
15
13
12
8
7
3
2
1
0
Conditional address
Reserved
Register select
Int. ena
9
10
2
1
Figure 20-143. DJZ Data Field (D31:D0)
31
930
7
6
0
Data
Reserved
25
7
Cycles
One
Register modified
Selected register (A, B, or T)
Description
This instruction defines a virtual down counter used for delayed execution of
certain instructions (to generate minimum on/off times). When DJZ is
executed with counter value not zero, the counter value is decremented. If the
counter value is zero, the counter remains zero until it is reloaded with a nonzero value. The program flow can be modified when down counter value is
zero by using the conditional address.
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cond_addr
This field is not optional for the DJZ instruction.
irq
ON generates an interrupt when the data field reaches zero. No
interrupt is generated when the bit is OFF.
Default: OFF.
data
Specifies the 25-bit integer value used as a counter. This counter is
decremented each time the DJZ instruction is executed until the
counter reaches 0.
Default: 0.
Execution
If (Data != 0)
{
Data = Selected register = Data - 1;
Jump to Next Program Address;
}
else
{
Selected register = 000000h;
If (Interrupt Enable == 1) HETFLG[n] = 1;
/* n depends on address */
If ([C28:C27] == 01) Generate request on request line [P25:P23];
If ([C28:C27] == 11) Generate quiet request on request line [P25:P23];
Jump to conditional Address;
}
The specific interrupt flag that is triggered depends on the address from which the instruction is executed,
see Section 20.2.7.
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20.6.3.11 ECMP (Equality Compare)
Syntax
ECMP {
[brk={OFF | ON}]
[next={label | 9-bit unsigned integer}]
[reqnum={3-bit unsigned integer}
[request={NOREQ | GENREQ | QUIET}]
[hr_lr={HIGH | LOW}]
[angle_comp={OFF | ON}]
[control={OFF | ON}]
[en_pin_action={OFF | ON}]
[cond_addr={label | 9-bit unsigned integer}]
pin={pin number}
[action={CLEAR | SET | PULSELO | PULSEHI}]
[reg={A | B | R | S| T | NONE}]
[irq={OFF | ON}]
[data={25-bit unsigned integer]
[hr_data={7-bit unsigned integer}]
}
Figure 20-144. ECMP Program Field (P31:P0)
31
26 25
23
0
Request
Number
6
3
22
21
BRK
13 12
Next program address
1
9
8
7
0000
9
hr_lr
Angle
comp.
6
Reserved
0
4
1
1
7
Figure 20-145. ECMP Control Field (C31:C0)
31
29
28
27
26
25
23
22
21
16
Reserved
Request type
Control
Reserved
En. pin
action
Conditional address
3
2
1
3
1
9
15
13
12
8
7
6
5
4
3
2
1
0
Conditional address
Pin select
Ext
Reg
00
Action
Register select
Int.
ena
9
5
1
2
2
2
1
Figure 20-146. ECMP Data Field (D31:D0)
31
932
7
6
0
Data
HR Data
25
7
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Cycles
One
Register modified
Register A, B, R, S or T if selected
Description
ECMP can use all pins. This instruction compares a 25-bit data value stored in
the data field (D31–D7) to the value stored in the selected ALU register (A, B,
R, S, or T). Register select encoding can be found in Section 20.6.2.
If R, S, or T registers are selected, and if the 25-bit data field matches, ECMP
updates the register with the 32-bit value (D31-D0).
If the hr_lr bit is cleared, the pin action will occur after a high resolution delay
from the next loop resolution clock. If the hr_lr bit is set, the delay is ignored.
This delay is programmed in the data field (D6–D0).
The behavior of the pins is governed by the four action options in bits C4:C3.
ECMP uses the zero flag to generate opposite pin action (synchronized to the
loop resolution clock).
angle_comp
Determines if an angle compare is performed. A value of ON causes
the comparison to be performed only if the new angle flag is set (NAF
= 1). If OFF is specified, the compare is then performed regardless of
the state of the new angle flag.
Default: OFF.
irq
Specifies whether or not an interrupt is generated. A value of ON
sends an interrupt if register and data field values are equivalent. If
OFF is selected, no interrupt is generated.
Default: OFF.
data
Specifies the value for the data field. This value is compared with the
selected register.
hr_data
Specifies the HR delay.
Default: 0.
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Execution
If (Angle Comp. bit == 0 OR (Angle Comp. bit == 1 AND NAF_global == 1))
{
If (Selected register value == Immediate data field value)
{
If (hr_lr bit == 0)
{
If (Enable Pin action
{
Selected Pin = Pin
}
}
else
{
If (Enable Pin action
{
Selected Pin = Pin
}
}
== 1)
Action AT next loop resolution clock + HR delay;
== 1)
Action AT next loop resolution clock;
If (Z == 1 AND Opposite action == 1)
{
If (Enable Pin action == 1)
{
Selected Pin = opposite Pin Action AT next loop resolution clock;
}
If (Interrupt Enable == 1) HETFLG[n] = 1;
/* n depends on address */
If ([C28:C27] == 01) Generate request on request line [P25:P23];
If ([C28:C27] == 11)Generate quiet request on request line [P25:P23];
If (register R is selected) R register = Compare value (32 bit);
If (register S is selected) S register = Compare value (32 bit);
If (register T is selected) T register = Compare value (32 bit);
Jump to Conditional Address;
}
}
elseIf (Z == 1 AND Opposite action == 1)
{
If (Enable Pin action == 1)
{
Selected Pin = opposite Pin Action AT next loop resolution clock;
}
Jump to Next Program Address;
}
else // Angle Comp. bit == 1 AND NAF_global == 0
{
Jump to Next Program Address;
}
The specific interrupt flag that is triggered depends on the address from which the instruction is executed,
see Section 20.2.7.
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20.6.3.12 ECNT (Event Count)
Syntax
ECNT {
[brk={OFF | ON}]
[next={label | 9-bit unsigned integer}]
[reqnum={3-bit unsigned integer}
[request={NOREQ | GENREQ | QUIET}]
[control={OFF | ON}]
[prv={OFF | ON}]
[cond_addr={label | 9-bit unsigned integer}]
pin={pin number}
event={NAF | FALL | RISE | BOTH | ACCUHIGH | ACCULOW}
[reg={A | B | R| S | T | NONE}]
[irq={OFF | ON}]
[data={25-bit unsigned integer]
}
Figure 20-147. ECNT Program Field (P31:P0)
31
26 25
23
0
Request
Number
6
3
22
21
13 12
BRK
Next program address
1
9
9
8
7
6
5
0
1010
Res.
01
Reserved
4
1
2
6
Figure 20-148. ECNT Control Field (C31:C0)
31
26
25
Reserved
29
Request type
Control
Prv.
Reserved
Conditional address
3
2
1
1
3
9
15
13
28
27
12
24
8
22
7
21
6
16
4
3
2
1
0
Conditional address
Pin select
Ext
Reg
Event
Res.
Register select
Int.
ena
9
5
1
3
1
2
1
Figure 20-149. ECNT Data Field (D31:D0)
31
7
6
0
Data
Reserved
25
7
Cycles
One cycle
Register modified
Selected Register (A, B, R, S, T or none)
Description
This instruction defines a specialized 25-bit virtual counter used as an event
counter or pulse accumulator (see Table 20-85). The counter value is stored
in the data field [D31:D7] and the selected register. If one of the 32-bit
registers (R,S,T) is selected, the 25 bit count value is stored left justified in the
register with zeros in the seven least significant bits.
When an event count condition is specified, the counter value is incremented
on a pin edge condition or on the NAF condition (NAF is defined in ACNT).
This instruction can be used with all pins.
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event
The event that triggers the counter.
Table 20-85. Event Encoding Format for ECNT
Event
C6
C5
C4
Count Conditions
Mode
Int. Available
NAF
0
0
0
NAF flag is Set
Angle counter
Y
FALL
0
0
1
Falling edge on selected pin
Event counter
Y
RISE
0
1
0
Rising edge on selected pin
Event counter
Y
BOTH
0
1
1
Rising and Falling edge on
selected pin
Event counter
Y
ACCUHIGH
1
0
-
while pin is high level
Pulse accumulation
N
ACCULOW
1
1
-
while pin is low level
Pulse accumulation
N
irq
ON generates an interrupt when event in counter mode occurs. No
interrupt is generated with OFF.
Default: OFF.
data
25-bit integer value serving as a counter.
Default: 0.
Execution
If (event occurs)
{
If (Register A or B Selected) {
Selected register = Immediate Data Field + 1;
}
If (Register R, S or T Selected)
{
Selected register[31:7] = Immediate Data Field + 1;
Selected register[6:0] = 0;
}
Immediate Data Field = Immediate Data Field + 1;
If (Interrupt Enable == 1) HETFLG[n] = 1;
/* n depends on address */
If ([C28:C27] == 01) Generate request on line [P25:P23];
If ([C28:C27] == 11) Generate quiet request on line [P25:P23];
Jump to Conditional Address;
}
else
{
Jump to Next Program Address;
}
Prv bit = Current Logic (Lx) value of selected pin; (Always executed)
The specific interrupt flag that is triggered depends on the address from which the instruction is executed,
see Section 20.2.7.
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20.6.3.13 MCMP (Magnitude Compare)
Syntax
MCMP {
[brk={OFF | ON}]
[next={label | 9-bit unsigned integer}]
[reqnum={3-bit unsigned integer}
[request={NOREQ | GENREQ | QUIET}]
[hr_lr={LOW |HIGH}]
[angle_comp={OFF | ON}]
[savesub={OFF | ON}]
[control={OFF | ON}]
[en_pin_action={OFF | ON}]
[cond_addr={label | 9-bit unsigned integer}]
pin={pin number}
order={REG_GE_DATA | DATA_GE_REG}
[action={CLEAR | SET | PULSELO | PULSEHI}]
reg={A | B | R | S | T | NONE}
[irq={OFF | ON}]
[data={25-bit unsigned integer]
[hr_data={7-bit unsigned integer}]
}
Figure 20-150. MCMP Program Field (P31:P0)
31
26 25
23
0
Request
Number
6
3
22
21
BRK
13 12
Next program address
1
9
8
7
6
5
0000
9
hr_lr
Angle
comp.
Res.
Save
sub.
4
Res.
0
4
1
1
1
1
5
Figure 20-151. MCMP Control Field (C31:C0)
31
29
28
27
26
25
23
22
21
16
Reserved
Request type
Control
Reserved
En. pin
action
Conditional address
3
2
1
3
1
9
15
7
6
5
Conditional address
13
12
Pin select
8
Ext
Reg
1
Order
4
Action
3
Register select
2
1
Int.
ena
0
9
5
1
1
1
2
2
1
Figure 20-152. MCMP Data Field (D31:D0)
31
7
6
0
Data
HR Data
25
7
Cycles
One
Register modified
T (if save sub bit P[5] is set)
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Description
This instruction compares the magnitude of the 25-bit data value stored in the
data field (D31-D7) and the 25-bit value stored in the selected ALU register
(A, B, R, S, or T).
If the hr_lr bit is reset, pin action will occur after a delay from the next loop
resolution clock. If the hr_lr bit is set, the delay is ignored. This delay is
programmed in the data field (D6-D0).
When the data value matches, an output pin can be set or reset according to
the pin action bit (C[4]). The pin will not change states if the enable pin action
bit (C[22]) is reset.
MCMP uses the zero flag set to generate opposite pin action (synchronized to
the loop resolution clock). The save sub bit (P[5]) provides the option to save
the result of a subtraction into register T.
NOTE: The Difference Between Compare Values
The difference between the two data values must not exceed (224) - 1.
angle_comp
Determines whether or not an angle compare is performed. A value of
ON causes the comparison to be performed only if the new angle flag
is set (NAF = 1). If OFF is specified, the compare is then performed
regardless of the state of the new angle flag.
Default: OFF.
savesub
When set, the comparison result is saved into the T register (upper
25 bits).
Default: OFF.
order
Specifies the order of the operands for the comparison.
Table 20-86. Magnitude Compare Order for MCMP
938
Order
C5
Description
REG_GE_DATA
0
Evaluates to true if the register value is greater than or equal to the data field value.
DATA_GE_REG
1
Evaluates to true if the data field value is greater than or equal to the register value.
irq
Specifies whether or not an interrupt is generated. A value of ON
sends an interrupt if the compare match occurs according to the order
selected. If OFF is selected, no interrupt is generated.
data
Specifies the value for the data field. This value is compared with the
selected register.
hr_data
HR delay. The default value for an unspecified bit is 0.
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Execution
If (Angle Compare P[7] == 0 OR (P[7] == 1 AND NAF_global == 1))
{
If( (Order C[5] == 1) AND (Data[31:7]- Selected register[31:7]) >= 0))
OR ( (Order C[5] == 0) AND Selected register[31:7] - Data[31:7]) >= 0))
{
If (Order C[5] == 1 AND Save subtract P[5] == 1)
{
Register T[31:7] = Data[31:7] - Selected register[31:7];
Register T[6:0] = 0;
}
If (Order C[5] == 0 AND Save subtract P[5] == 1)
{
Register T[31:7] = Selected register[31:7] - Data[31:7];
Register T[6:0] = 0;
}
If (Enable Pin Action C[22] == 1)
{
If (hr_lr P[8] = 0) {
Schedule Action on Selected Pin C[12:8] at start of next loop
+ HR Delay D[6:0];
}
else
{
Schedule Pin Action on Selected Pin C[12:8] at start of next loop;
}
}
If (Interrupt Enable == 1) HETFLG[n] = 1;
/* n depends on address */
If ([C28:C27] == 01) Generate request on request line [P25:P23];
If ([C28:C27] == 11) Generate quiet request on request line [P25:P23];
Jump to Conditional Address;
}
else if (Z == 1 AND Opposite Action C[3] == 1 )
{
If (Enable Pin Action C[22] == 1)
{
Schedule Opposite Pin Action on Selected Pin C[12:8] at start of next loop;
}
Jump to Next Program Address;
}
else
Jump to Next Program Address;
}
else // Angle Comp. bit == 1 AND NAF_global == 0
Jump to Next Program Address;
The specific interrupt flag that is triggered depends on the address from which the instruction is executed,
see Section 20.2.7.
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20.6.3.14 MOV32 (Data Move 32)
Syntax
MOV32 {
[brk={OFF | ON}]
[next={label | 9-bit unsigned integer}]
remote={label | 9-bit unsigned integer}
[control={OFF | ON}]
[z_cond={OFF | ON}]
[init={OFF | ON}]| ON}]
type={IMTOREG | IMTOREG&REM | REGTOREM | REMTOREG}
[reg={A | B | R | S | T | NONE}]
[data={25-bit unsigned integer]
[hr_data={7-bit unsigned integer}]
}
Figure 20-153. MOV32 Program Field (P31:P0)
31
26 25
23
0
Reserved
6
3
22
21
BRK
13 12
Next program address
1
9
9
8
0
0100
Remote Address
4
9
Figure 20-154. MOV32 Control Field (C31:C0)
31
27
26
Reserved
Control
5
1
25
23
Reserved
22
8
Reserved
14
16
Z Fl. Cond.
3
15
21
Reserved
1
14
7
6
5
4
Ext Reg
Init flag
0
Move type
Register select
Res.
1
1
2
2
1
1
3
2
1
0
Figure 20-155. MOV32 Data Field (D31:D0)
31
940
7
6
0
Data
HR Data
25
7
Cycles
One or two cycles
Register modified
Selected register (A, B, R, S, or T)
Description
MOV32 replaces the selected ALU register and/or the data field values at the
remote address location depending on the move type.
Figure 20-156 through Figure 20-159 illustrate these operations. If no register
is selected, the move is not executed, except for configuration C4:C3 = 01,
where the remote data field is written with the immediate data field value.
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remote
Determines the location of the remote address.
Default: Current instruction + 1.
z_cond
When set to OFF the MOV32 performs the move operation specified
by the move type whenever it is executed (independent on the state
of the Z-Flag).
When set to ON the MOV32 performs the move operation specified
by the move type only when the Z-Flag is set.
init
(Optional) Determines whether or not system flags are initialized. A
value of ON reinitializes the following system flags to these states:
Acceleration flag (ACF) = 0
Deceleration flag (DCF) = 1
Gap flag (GPF) = 0
New angle flag (NAF) = 0
A value of OFF results in no change to the system flags.
type
Specifies the move type to be executed.
Table 20-87. Move Type Encoding Selection
Move Type
C4
C3
Source
Destination(s)
Cycles
IMTOREG
0
0
Immediate data field
Register A, B, R, S, or T
1
Remote data field and register
A, B, R, S, or T
1
IMTOREG&REM
0
1
Immediate data field
REGTOREM
1
0
Register A, B, R, S, or T
Remote data field
1
REMTOREG
1
1
Remote data field
Register A, B, R, S, or T
2
Figure 20-156. MOV32 Move Operation for IMTOREG (Case 00)
25/32-bit move
LSBs (HR data field)
32 bits
HR
Immediate DF
HR
Register A, B, or R, S or T
(dashed for R, S, T)
reg
Specifies which register (A, B, T, or NONE) is involved in the move. A
register (A, B, or T) must be specified for every move type except
IMTOREG&REM. If NONE is used with move type IMTOREG&REM,
the MOV32 executes a move from the immediate data field to the
remote data field. If NONE is used with any other move type, no
move is executed.
data
Specifies a 25-bit integer value to be written to the remote data field
or selected register.
hr_data
(Optional) HR delay. The default value for an unspecified bit is 0.
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Figure 20-157. MOV32 Move Operation for IMTOREG&REM (Case 01)
25/32-bit move
LSBs (HR data field)
32 bits
HR
Immediate DF
HR
HR
Remote DF
Register A, B, R, S or T
(dashed for R, S, T)
Figure 20-158. MOV32 Move Operation for REGTOREM (Case 10)
25/32-bit move
HR
Register A, B, R, S, or T
(dashed for R, S, T)
HR
Remote DF
LSBs (HR data field = 0 if A or B)
Figure 20-159. MOV32 Move Operation for REMTOREG (Case 11)
LSBs (HR data field)
25/32-bit move
32 bits
HR
Remote DF
HR Register A, B, R, S, or T
(dashed for R, S, T)
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Execution
If [(z_cond C[22] ==0) OR ((z_cond C[22] == 1) AND (Z Flag == 1))]
{
switch (type C[4:3])
{
case 00: // IMTOREG
Selected register = Immediate Data Field;
case 01: // IMTOREG&REM
Selected register = Immediate Data Field;
Remote Data Field = Immediate Data Field;
case 10: // REGTOREM
Remote Data Field = Selected register;
case 11: // REMTOREG
Selected register = Remote Data Field;
}
}
If (Init Flag == 1)
{
ACF = 0;
DCF = 1;
GPF = 0;
NAF = 0;
}
else
All flags remain unchanged;
Jump to Next Program Address;
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20.6.3.15 MOV64 (Data Move 64)
Syntax
MOV64 {
[brk={OFF | ON}]
[next={label | 9-bit unsigned integer}]
remote={label | 9-bit unsigned integer}
[request={NOREQ | GENREQ | QUIET}]
[control={OFF | ON}]
[en_pin_action={OFF | ON}]
[cond_addr={label | 9-bit unsigned integer}]
[pin={pin number}]
comp_mode={ECMP | SCMP | MCMP1 | MCMP2}
[action={CLEAR | SET | PULSELO | PULSEHI}]
[reg={A | B | R | S | T | NONE}]
[irq={OFF | ON}]
[data={25-bit unsigned integer]
[hr_data= {7-bit unsigned integer}
}
-orSyntax
944
MOV64 {
[brk={OFF | ON}]
[next={label | 9-bit unsigned integer}]
remote={label | 9-bit unsigned integer}
cntl_val={29-bit unsigned integer}
[data={25-bit unsigned integer]
[hr_data= {7-bit unsigned integer}
}
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Figure 20-160. MOV64 Program Field (P31:P0)
31
26 25
23
0
Reserved
6
3
22
21
BRK
13 12
Next program address
1
9
9
8
0
0001
Remote Address
4
9
Figure 20-161. MOV64 Control Field (C31:C0)
31
29
28
27
26
25
23
Reserved
Request type
Control
Reserved
3
2
1
3
15
13
12
8
22
21
16
En. pin
action
Conditional address
1
7
9
6
5
4
3
2
1
0
Conditional address
Pin select
Ext
Reg
Comp. mode
Action
Register select
Int.
ena
9
5
1
2
2
2
1
Figure 20-162. MOV64 Data Field (D31:D0)
31
7
6
0
Data
HR Data
25
7
Cycles
One
Register modified
None
Description
This instruction modifies the data field and the control field at the remote
address.
MOV64 has two distinct syntaxes. In the first syntax, bit values may be set by
assigning a value to each of the control fields. This syntax is convenient for
modifying control fields that are arranged similarly to the format of the MOV64
control field. A second syntax, in which the entire 29-bit control field is
specified by the cntl_val field, is convenient when the remote control field is
dissimilar to the MOV64 control field. Either syntax may be used, but you must
use one or the either but not a combination of syntaxes. See Figure 20-163.
Figure 20-163. MOV64 Move Operation
HR
Immediate CF + DF
HR
Remote CF + DF
Table 20-88. MOV64 Control Field Descriptions
request
control
en_pin_action
cond_addr
pin
register, ext reg
comp_mode
Maintains the control field for the remote instruction.
Maintains the control field for the remote instruction.
Maintains the control field for the remote instruction.
Maintains the control field for the remote instruction.
Maintains the control field for the remote instruction.
Maintains the control field for the remote instruction.
Selects the comparison mode type to be used by the remote instruction.
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Table 20-88. MOV64 Control Field Descriptions (continued)
action
irq
data
hr_data
Maintains the control field for the remote instruction.
Maintains the control field for the remote instruction.
Specifies the 25-bit initial count value for the data field. If omitted, the field defaults to 0.
(Optional) HR delay. The default value for an unspecified bit is 0.
Table 20-89. Comparison Type Encoding Format
comp_mode
C[6]
C[5]
ECMP
0
0
MCMP Order
SCMP
0
1
MCMP1
1
0
REG_GE_DATA
MCMP2
1
1
DATA_GE_REG
Execution
Remote Data Field = Immediate Data Field;
Remote Control Field = Immediate control Field;
Jump to Next Program Address;
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20.6.3.16 PCNT (Period/Pulse Count)
Syntax
PCNT {
[hr_lr={HIGH | LOW}]
[brk={OFF | ON}]
[next={label | 9-bit unsigned integer}]
[reqnum={3-bit unsigned integer}
[request={NOREQ | GENREQ | QUIET}]
[irq={OFF | ON}]
type={FALL2RISE | RISE2FALL | FALL2FALL | RISE2RISE}
pin={pin number}
[control={OFF | ON}]
[prv={OFF | ON}]
[period={25-bit unsigned integer}]
[data={25-bit unsigned integer]
[hr_data= {7-bit unsigned integer}
}
Figure 20-164. PCNT Program Field (P31:P0)
31
26 25
23
0
Request
Number
6
3
22
21
BRK
13 12
Next program address
1
9
9
8
7
6
5
4
0
0111
Int.
ena
Type select
hr_lr
Pin
select
4
1
2
1
5
Figure 20-165. PCNT Control Field (C31:C0)
31
29 28
27
26
Res.
Request
type
Control
3
2
1
25
24
0
Prv.
Period Count
1
25
Figure 20-166. PCNT Data Field (D31:D0)
31
7
6
0
Data
HR Data
25
7
Cycles
One
Register modified
Register A
Description
This instruction detects the edges of the external signal at loop start and
measures its period or pulse duration. The counter value stored in the control
field C[24:0] and in the register A is incremented each N2HET loop. PCNT
uses the HR structure on the pin to measure an HR period/pulse count value.
hr_lr
(Optional) Specifies whether the PCNT instruction captures the HR
delay into the HR data field on the selected edge condition. If hr_lr is
0 (HIGH) then PCNT captures the HR delay. if hr_lr is 1 (LOW) then
PCNT only captures at loop resolution.
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irq
(Optional) Specifies whether or not an interrupt is generated. A value
of ON sends an interrupt when a new value is captured. If OFF is
selected, no interrupt is generated.
type
(Optional) Determines the type of counter that is implemented.
Table 20-90. Counter Type Encoding Format
P7
P6
Period/Pulse Select
Reset On
Capture On
Falling edge
Rising edge
FALL2RISE
0
0
Count low-pulse duration on
selected pin
RISE2FALL
0
1
Count high-pulse duration on
selected pin
Rising edge
Falling edge
FALL2FALL
1
0
Count period between falling edges
on selected pin
Falling edge
Falling edge
RISE2RISE
1
1
Count period between rising edges
on selected pin
Rising edge
Rising edge
period
Specifies the 25-bit integer value that holds the counter value. The
counter value is also stored in register A.
Default: 0.
data
25-bit integer representing the last captured counter value.
Default: 0.
hr_data
HR delay.
Default: 0.
If period-measure is selected, PCNT captures the counter value into the period/pulse data field [D31:D7]
on the selected edge. The HR structure provides HR capture field [D6:D0]. The counter value [C24:C0] is
reset on the same edge. The captured period value is a 32-bit value.
If pulse-measure is selected, PCNT captures the counter value into the period/pulse count field [D31:D7]
on the selected edge. The HR structure provides HR capture field [D6:D0]. The counter value [C24:C0] is
reset on the next opposite edge. The captured pulse value is a 32-bit value.
When the overflow count (all 1’s in the counter value) is reached, PCNT stops counting until the next reset
edge is detected.
Note: For FALL2FALL/RISE2RISE, the user should always discard the first interrupt/HTU request if
interrupt/request are enabled before HET_ON. For both the types, reset edge and capture edge are the
same and the interrupt or HTU request is triggered on capture edge (which is nothing but the reset edge).
Once the execution unit is enabled, the first edge generates an interrupt but the value of the counter is of
no use as this is not the period between 2 edges. So first edge after turning on N2HET is used mainly for
resetting the counter and start the period count.
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Execution
Z = 0;
If (Period C[24:0] != 1FF_FFFFh) {
Period C[24:0] = Period C[24:0] + 1;
}
Register A = Period C[24:0];
If (specified capture edge detected on selected pin)
{
Z = 1;
If (Period value != 1FF_FFFFh)
{
HR Capture Value = selected HR counter;
}
else
{
HR Capture Value = 7Fh;
}
If (Interrupt Enable == 1) HETFLG[n] = 1;
/* n depends on address */
If ([C28:C27] == 01) Generate request on request line [P25:P23];
If ([C28:C27] == 11) Generate quiet request on request line [P25:P23];
}
If (specified reset edge detected on selected pin)
{
Period value = 0000000h;
}
Prv bit = Current Logic (Lx) value of selected pin;
Jump to Next Program Address;
The specific interrupt flag that is triggered depends on the address from which the instruction is executed,
see Section 20.2.7.
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20.6.3.17 PWCNT (Pulse Width Count)
Syntax
PWCNT {
[brk={OFF | ON}]
[next={label | 9-bit unsigned integer}]
[reqnum={3-bit unsigned integer}
[request={NOREQ | GENREQ | QUIET}]
[hr_lr={HIGH | LOW}]
[control={OFF | ON}]
[cond_addr={label | 9-bit unsigned integer}
[en_pin_action={OFF | ON}]
pin ={pin number}
[action={CLEAR | SET | PULSELO | PULSEHI}]
[reg={A | B | T | NONE}]
[irq={OFF | ON}]
[data={25-bit unsigned integer]
[hr_data={7-bit unsigned integer}]
}
Figure 20-167. PWCNT Program Field (P31:P0)
31
26 25
23
0
Request
Number
6
3
22
21
BRK
13 12
Next program address
1
9
9
8
7
6
5
0
1010
hr_lr
11
Reserved
4
1
2
6
Figure 20-168. PWCNT Control Field (C31:C0)
31
29
28
27
26
25
23
22
21
16
Reserved
Request type
Control
Reserved
En. pin
action
Conditional address
3
2
1
3
1
9
15
13
12
8
7
5
4
3
2
1
0
Conditional address
Pin select
Reserved
Action
Register select
Int.
ena
9
5
3
2
2
1
Figure 20-169. PWCNT Data Field (D31:D0)
31
950
7
6
0
Data
HR Data
25
7
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Cycles
One
Register modified
Selected register (A, B or T)
Description
This instruction defines a virtual timer used to generate variable length pulses.
The counter value stored in the data field is decremented unconditionally on
each timer resolution until it reaches zero, and it then stays at zero until it is
reloaded with a non-zero value.
The specified pin action is performed as long as the count after count value is
decremented is greater than 0. The opposite pin action is performed when the
count after decrement just reaches 0.
If the hr_lr bit is reset, the opposite pin action will be taken after a HR delay
from the next loop resolution clock. If the hr_lr bit is set, the delay is ignored.
This delay is programmed in bits [D6:D0].
irq
ON generates an interrupt when the data field value reaches 0. No
interrupt is generated for OFF.
Default: OFF.
data
25-bit integer value serving as a counter.
hr_data
HR delay.
Default: 0.
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Execution
If (Data field value == 0)
{
Selected register = 0;
Jump to Next Program Address;
}
If (Data field value > 1)
{
Selected register = Data field value - 1;
Data field value = Counter value - 1;
If (Enable Pin action == 1)
{
Selected Pin = Pin Action AT next loop resolution clock;
}
Jump to Next Program Address;
}
If (Data field value == 1)
{
Selected register = 0000000h;
Data field value = 0000000h;
If (Opposite action == 1)
{
If (hr_lr bit == 0)
{
If (Enable Pin action == 1)
{
Selected Pin = Opposite level of Pin Action AT next loop resolution clock
+ HR delay;
}
}
else
{
If (Enable Pin action == 1)
{
Selected Pin = Opposite level of Pin Action AT next loop
resolution clock;
}
}
If (Interrupt Enable == 1) HETFLG[n] = 1;
/* n depends on address */
If ([C28:C27] == 01) Generate request on request line [P25:P23];
If ([C28:C27] == 11) Generate quiet request on request line [P25:P23];
}
Jump to Conditional Address
}
The specific interrupt flag that is triggered depends on the address from which the instruction is executed,
see Section 20.2.7.
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20.6.3.18 RADM64 (Register Add Move 64)
Syntax
RADM64 {
[brk={OFF | ON}]
[next={label | 9-bit unsigned integer}]
remote={label | 9-bit unsigned integer}
[request={NOREQ | GENREQ | QUIET}]
[control={OFF | ON}]
[en_pin_action={OFF | ON}]
[cond_addr={label | 9-bit unsigned integer}]
[pin={pin number}]
comp_mode={ECMP | SCMP | MCMP1 | MCMP2}
[action={CLEAR | SET | PULSELO | PULSEHI}]
[reg={A | B | R | S | T | NONE}]
[irq={OFF | ON}]
[data={25-bit unsigned integer]
[hr_data= {7-bit unsigned integer}
}
-orSyntax
RADM64 {
[brk={OFF | ON}]
[next={label | 9-bit unsigned integer}]
remote={label | 9-bit unsigned integer}
cntl_val={29-bit unsigned integer}
[data={25-bit unsigned integer]
[hr_data= {7-bit unsigned integer}
}
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Figure 20-170. RADM64 Program Field (P31:P0)
31
26 25
23
0
Reserved
6
3
22
21
13 12
BRK
Next program address
1
9
9
8
0
0011
Remote Address
4
9
Figure 20-171. RADM64 Control Field (C31:C0)
31
29
28
27
26
25
23
22
21
16
Reserved
Request type
Control
Reserved
En. pin
action
Conditional address
3
2
1
3
1
9
15
13
12
8
7
6
5
4
3
2
1
0
Conditional address
Pin select
Ext
Reg
Comp. mode
Action
Register select
Int.
ena
9
5
1
2
2
2
1
Figure 20-172. RADM64 Data Field (D31:D0)
31
7
6
0
Data
HR Data
25
7
Cycles
Normally One Cycle. Two cycles if writing to remote address that is also the
next address.
Register modified
None
Description
This instruction modifies the data field, the HR data field and the control field
at the remote address. The advantage over DADM64 is that It executes one
cycle faster. In case the R, S, or T register is selected, the addition is a 32-bit
addition. The table description shows the bit encoding for determining which
ALU register is selected.
RADM64 has two distinct syntaxes. In the first syntax, bit values may be set
by assigning a value to each of the control fields. This syntax is convenient for
modifying control fields that are arranged similar to the format of the RADM64
control field. A second syntax, in which the entire 29-bit control field is
specified by the cntl_val field, is convenient when the remote control field is
dissimilar from the RADM64 control field. Either syntax may be used, but you
must use one or the either but not a combination of syntaxes. See Figure 20173.
Figure 20-173. RADM64 Add and Move Operation
LSBs (HR data field)
32 bits
Immediate CF
Remote CF
comp_mode
954
HR
Immediate DF
+
HR
Register A, B, R, S, or T
(dashed for R, S, T)
=
HR
Remote DF
Selects the comparison mode type to be used.
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Table 20-91. Comparison Type Encoding Format
comp_mode
C[6]
C[5]
ECMP
0
0
MCMP Order
SCMP
0
1
MCMP1
1
0
REG_GE_DATA
MCMP2
1
1
DATA_GE_REG
Table 20-92. RADM64 Control Field Descriptions
request
Control
en_pin_action
cond_addr
pin
register
action
irq
data
hr_data
cntl_val
Maintains the control field for the remote instruction.
Maintains the control field for the remote instruction.
Maintains the control field for the remote instruction.
Maintains the control field for the remote instruction.
Maintains the control field for the remote instruction.
Maintains the control field for the remote instruction.
Maintains the control field for the remote instruction.
Maintains the control field for the remote instruction.
Specifies the 25-bit initial value for the data field. If omitted, the field defaults to 0.
Seven least significant bits of the 32-bit data field.
Default: 0.
Specifies the 29 least significant bits of the Control field.
Execution
Remote Data Field = Selected register + Immediate Data Field (including HR field);
Remote Control Field = Immediate Control Field;
Jump to Next Program Address;
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20.6.3.19 RCNT (Ratio Count)
Syntax
RCNT {
[brk={OFF | ON}]
[next={label | 9-bit unsigned integer}]
[control={OFF | ON}]
divisor={25-bit unsigned integer}
[data={25-bit unsigned integer]
}
Figure 20-174. RCNT Program Field (P31:P0)
31
26 25
23
22
21
13 12
9
8
7
6
5
4
3
1
0
0
Reserved
BRK
Next program address
1010
Res.
00
Step
width
Res.
1
6
3
1
9
4
1
2
2
3
1
Figure 20-175. RCNT Control Field (C31:C0)
31
27
26
Reserved
Control
5
1
25
24
0
Res.
Divisor
1
25
Figure 20-176. RCNT Data Field (D31:D0)
31
7
6
0
Data
Reserved
25
7
Cycles
Two Cycles (One Cycle if T=0)
Register modified
None
Description
RCNT is used with other instructions to convert an input period measurement
TInput to the form of (Equation 31) where the input period is expressed as a
fraction of a reference period TReference.
æ N ö
T In p u t = T R e fe re n c e · ç
÷
èM ø
(31)
RCNT computes the numerator N of (Equation 31). The denominator M of
(Equation 31) is a constant that is of interest. For example, choosing M = 100
allows the input period to be expressed as a percentage (%) of the reference
period. Note that if TInput > TReference , then RCNT will return N > M ; which would
be correct if, for example, the input pulse period is 110% of the reference
pulse period.
RCNT expects that register T is loaded with the value of TReference. The input
period TInput is determined by counting the number of loop resolution periods
between edges on the input pin. This information is conveyed through the Z
flag from a PCNT instruction that precedes the RCNT instruction.
The divisor field of the RCNT instruction should be chosen as:
Divisor = M ·
lr , where M is the desired denominator from
(Equation 31) and lr is the loop resolution prescale value.
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An example N2HET program that makes use of the RCNT instruction is:
L0: MOV32 { remote=dummy,type=IMTOREG,reg=T,data=0x8,hr_data=0};
L1: PCNT { hr_lr=HIGH,brk=OFF,type=FALL2FALL,pin=0};
L2: RCNT { divisor=320,data=0x4};
L3: BR {cond_addr=L5, event = Z}
L4: ADC { src1=ZERO,src2=IMM,dest=IMM,next=L0,data=0,hr_data=0};
L5: ADD { src1=REM,src2=ZERO,dest=IMM,remote=L4,data=0,hr_data=0};
L6: ADD { src1=ZERO,src2=ZERO,dest=NONE,rdest=REM,
next=L0,remote=L4,data=0,hr_data=0};
dummy
In this small program an input signal on pin 0 is measured both in terms of absolute cycles by the PCNT
instruction at L1 and as in 1/10ths of the reference period by the RCNT instruction at L2. In this example
the reference period is a constant 0x400 cycles; this value is loaded into register T by the MOV32
instruction at L0. (0x400 is data=8, hr_data=0)
RCNT follows PCNT and is initialized to a working count of T/2 (0x200) whenever the PCNT instruction
detects a falling edge on pin 0. Between falling edges on pin0, RCNT accumulates counts 10x faster than
PCNT; so that the working data field of RCNT will reach the reference value of 0x400 in 1/10th the time
that a PCNT instruction would. Each time the RCNT instruction passes the reference value, it sets the
carry out flag and subtracts the reference value from the working count. By accumulating carry-outs from
RCNT, the add with carry instruction at L4 effectively counts in increments of 1/10th of the reference
period. Note that the divisor value 320 is 10 times 32; this assumes lr=32.
When the next falling edge is detected on pin 0, PCNT sets the Z flag and the RCNT instruction resets
again to the initial data field of T/2. RCNT does not modify the Z flag, so that the branch instruction at L3
can execute instructions at L5, L6 instead of L4. The instructions at L5 and L6 capture the final result from
L4 and reset the ADC instruction at L4 to zero for the start of the next period measurement.
Execution
If (register T[31:0] != 00000000h)
{
C = 0;
If (Z == 0)
{
Data Field[31:0] = Data Field[31:0] + Divisor[24:0];
If (Data Field[31:0] >= Reg T[31:0])
{
Data Field[31:0]=Data Field[31:0] - Reg T[31:0];
C = 1;
}
}
else
{
Data Field[31:0] = T[31:0] >> 1; /* T/2 */
}
}
Jump to Next Program Address;
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20.6.3.20 SCMP (Sequence Compare)
Syntax
SCMP {
[brk={OFF | ON}]
[next={label | 9-bit unsigned integer}]
[reqnum={3-bit unsigned integer}
[request={NOREQ | GENREQ | QUIET}]
[control={OFF | ON}]
[en_pin_action={OFF | ON}]
cond_addr={label | 9-bit unsigned integer}
pin ={pin number}
[action={CLEAR | SET}]
[restart={OFF | ON}]
[irq={OFF | ON}]
[data={25-bit unsigned integer]
}
Figure 20-177. SCMP Program Field (P31:P0)
31
26 25
23
0
Request
Number
6
3
22
21
BRK
13 12
Next program address
1
9
8
0
0000
Reserved
4
9
9
Figure 20-178. SCMP Control Field (C31:C0)
31
29
Reserved
28
27
Request type
3
2
15
13
26
25
Control
Cout
prv
Reserved
En. pin
action
Conditional address
1
2
1
9
1
12
Conditional address
24
8
Pin select
9
5
23
7
22
21
6
5
16
1
0
Res.
01
Action
4
Reserved
3
2
Restart
enable
Int.
ena
1
2
1
2
1
1
Figure 20-179. SCMP Data Field (D31:D0)
31
958
7
6
0
Data
Reserved
25
7
Cycles
One
Register modified
Register T (implicitly)
Description
This instruction alternately performs angle- and time-based operations to
generate pulse sequences, using the angle referenced time base. These
pulse sequences last for a relative duration using a free running time base.
Generally, register B holds the angle values and register A holds the time
values. Bit 0 of the conditional address field (C13) specifies whether the
instruction is operating in angle or time operation mode.
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When the compared values match in angle mode, a pin can be set or reset
according to the pin action bit (C4). The pin does not change states if the
enable pin action bit (C22) is reset.
The restart enable bit (C1) provides the option to unconditionally restart a
sequence using the X-flag bit of ACMP.
restart
If restart is set to ON and the X flag = 1, the assembler writes a value
of 1 into the immediate index field, writes the value in register A into
the immediate data field, and jumps to the next program address. The
X flag is set or cleared by the ACMP instruction. If restart is set to
OFF, the X flag is ignored; no special action is performed.
Default: OFF.
irq
ON generates an interrupt if the compare match occurs in angle
mode. No interrupt is generated when the field is OFF.
Default: OFF.
data
Specifies the 25-bit compare value.
cond_addr
Since the LSB of the conditional address is used to select between
time mode and angle mode, and since the conditional address is
taken only in time mode, the destination for the conditional address
must be odd.
Execution
If (Data field value = 0)
{
Data field register = Data Field register - register T;
Z = 1;
}
Register A = Gap start value;
}
Jump to Next Program Address;
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20.6.3.22 SHFT (Shift)
Syntax
SHFT {
[brk={OFF | ON}]
[next={label | 9-bit unsigned integer}]
[reqnum={3-bit unsigned integer}
[request={NOREQ | GENREQ | QUIET}]
smode={OR0 | OL0 | OR1 | OL1 | ORZ | OLZ | IRM | ILL | IRZ | ILZ}
[control={OFF | ON}]
[prv={OFF | ON}]
[cond_addr={label | 9-bit unsigned integer}
cond={UNC | FALL | RISE}
pin ={pin number}
[reg={A | B | R | S | T | NONE}]
[irq={OFF | ON}]
[data={25-bit unsigned integer]
}
Figure 20-183. SHFT Program Field (P31:P0)
31
26 25
23
0
Request
Number
6
3
22
21
BRK
13 12
Next program address
1
9
9
8
4
3
0
1111
Reserved
Smode
4
5
4
Figure 20-184. SHFT Control Field (C31:C0)
31
29
28
27
Reserved
Request type
3
2
15
13
26
25
Control
24
Prv.
1
22
8
16
Conditional address
3
9
1
12
21
Reserved
7
6
5
4
3
2
1
0
Conditional address
Pin select
Ext
Reg
Shift condition
Res.
0
Register select
Int.
ena
9
5
1
2
1
1
2
1
Figure 20-185. SHFT Data Field (D31:D0)
31
962
7
6
0
Data
Reserved
25
7
Cycles
One
Register modified
Selected register (A, B, R, S or T)
Description
This instruction shifts the data field of the Instruction. N2HET pins can be
used for data in or data out. SHFT includes parameters to select the shift
direction (in, out, left, right), shift condition (shift on a defined clock edge on
HET[0] or shift always), register for data storage (A, B, R, S or T), and the
data pin.
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smode
Shift mode
Table 20-94. SHIFT MODE Encoding Format
smode
P3
P2
P1
P0
Operation
OR0
0
0
0
0
Shift Out / Right
LSB 1st on HETx / 0 into MSB
OL0
0
0
0
1
Shift Out / Left
MSB 1st on HETx / 0 into LSB
OR1
0
0
1
0
Shift Out / Right
LSB 1st on HETx / 1 into MSB
OL1
0
0
1
1
Shift Out / Left
MSB 1st on HETx / 1 into LSB
ORZ
0
1
0
0
Shift Out / Right
LSB 1st on HETx / Z into MSB
OLZ
0
1
0
1
Shift Out / Left
MSB 1st on HETx / Z into LSB
IRM
1
0
0
0
Shift In / Right
HETx into MSB
ILL
1
0
0
1
Shift In / Left
HETx into LSB
IRZ
1
0
1
0
Shift In / Right
HETx in MSB / LSB into Z
ILZ
1
0
1
1
Shift In / Left
HETx in LSB / MSB into Z
cond
Specifies the shift condition.
Table 20-95. SHIFT Condition Encoding
C6
C5
0
X
Shift Condition
Always
1
0
Rising edge of HET[0]
1
1
Falling edge of HET[0]
irq
ON generates an interrupt if the Z flag is set. A value of OFF does not
generate an interrupt.
Default: OFF.
data
Specifies the 25-bit value for the data field.
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Execution
If (SHIFT condition == 0X)
OR (SHIFT condition == 10 AND HET[0] rising edge)
OR (SHIFT condition == 11 AND HET[0] falling edge)
{
If ([P3:P2] == 00)
{
If ((Immediate Data Field == all 0’s AND [P3:P0] == 000X)
OR (Immediate Data Field == all 1’s AND [P3:P0] == 001X))
{
Z = 1;
}
else
{
Z = 0;
}
}
else If ([P3:P0] == 1010)
{
Z = LSB of the Immediate Data Field;
}
else if ([P3:P0] == 1011)
{
Z = MSB of the Immediate Data Field;
}
}
If( (Immediate Data Field == all 0’s) OR
(Immediate Data Field == all 1’s))
{
if (Interrupt Enable == 1)
HETFLG[n] = 1;
{
/* n depends on address */
}
Jump to Conditional Address;
}
else
{
Jump to Next Program Address;
}
Prv. bit = HET[0] Pin level; (Always executed)
Shift Immediate Data Field once according to P[3:0];
Immediate Data Field = Result of the shift;
Selected register = Result of the shift;
Jump to Next Program Address;
NOTE: The immediate data field evaluates all 0s or all 1s and is performed before the shift
operation.
The specific interrupt flag that is triggered depends on the address from which the instruction is executed,
see Section 20.2.7.
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20.6.3.23 WCAP (Software Capture Word)
Syntax
WCAP {
[brk={OFF | ON}]
[next={label | 9-bit unsigned integer}]
[reqnum={3-bit unsigned integer}
[request={NOREQ | GENREQ | QUIET}]
[hr_lr={HIGH | LOW}]
[control={OFF | ON}]
[prv={OFF | ON}]
[cond_addr={label | 9-bit unsigned integer}]
pin ={pin number}
event={NOCOND | FALL | RISE | BOTH}
reg={A | B | R | S | T | NONE}
[irq={OFF | ON}]
[data={25-bit unsigned integer]
[hr_data={7-bit unsigned integer}]
}
Figure 20-186. WCAP Program Field (P31:P0)
31
26 25
23
22
21
13 12
9
8
7
0
0
Request
Number
BRK
Next program address
1011
hr_lr
Reserved
6
3
1
9
4
1
8
Figure 20-187. WCAP Control Field (C31:C0)
31
29
28
27
Reserved
Request type
3
2
15
13
26
25
Control
24
Prv.
1
1
12
8
22
21
16
Reserved
Conditional address
3
9
7
6
5
4
3
2
1
0
Conditional address
Pin select
Ext
Reg
Capture
condition
Reserved
Register select
Int.
ena
9
5
1
2
2
2
1
Figure 20-188. WCAP Data Field (D31:D0)
31
7
6
0
Data
HR Data
25
7
Cycles
One
Register modified
None
Description
This instruction captures the selected register into the data field if the specified
capture condition is true on the selected pin. This instruction can be used with
all pins.
If the hr_lr bit is reset, the WCAP instruction will capture an HR time stamp
into the data field on the selected edge condition. If the hr_lr bit is set, the HR
capture is ignored.
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event
Specifies the event that triggers the capture.
Table 20-96. Event Encoding Format for WCAP
C6
C5
Capture Condition
0
0
Always
0
1
Capture on falling edge
1
0
Capture on rising edge
1
1
Capture on rising and falling edge
irq
ON generates an interrupt when the capture condition is met. No
interrupt is generated for OFF.
Default: OFF.
data
Specifies the 25-bit integer value to be written to the data field or
selected register.
hr_data
HR capture value.
Default: 0.
NOTE: WCAP in HR Mode: The HR Counter starts on a WCAP instruction execution (in the first
loop clock) and will synchronize to the next loop clock. When N2HET is turned on and a
capture edge occurs in the first loop clock (where the HR counter hasn’t been synchronized
to the loop clock), then the captured HR counter value is wrong and is of no use. So the
captured HR data in the first loop clock should be ignored.
Execution
If (Specified Capture Condition is true on Selected Pin
OR Unconditional capture is selected)
{
Immediate Data Field = Selected register value;
If (hr_lr bit == 0) Capture the HR value in Immediate HR Data Field;
If (Interrupt Enable == 1) HETFLG[n] = 1;
/* n depends on address */
If ([C28:C27] == 01) Generate request on request line [P25:P23];
If ([C28:C27] == 11) Generate quiet request on request line [P25:P23];
Jump to Conditional Address;
}
Jump to Next Program Address;
Prv bit = Current Logic (Lx) value of selected pin; (always executed)
The specific interrupt flag that is triggered depends on the address from which the instruction is executed,
see Section 20.2.7.
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20.6.3.24 WCAPE (Software Capture Word and Event Count)
Syntax
WCAPE {
[brk={OFF | ON}]
[next={label | 9-bit unsigned integer}]
[reqnum={3-bit unsigned integer}
[request={NOREQ | GENREQ | QUIET}]
[control={OFF | ON}]
[prv={OFF | ON}]
[cond_addr={label | 9-bit unsigned integer}
pin ={pin number}
event={NOCOND | FALL | RISE | BOTH}
[reg={A | B | R | S | T | NONE}]
[irq={OFF | ON}]
[ts_data={25-bit unsigned integer]
[ec_data={7-bit unsigned integer}]
}
Figure 20-189. WCAPE Program Field (P31:P0)
31
26 25
23
0
Request
Number
6
3
22
21
BRK
13 12
Next program address
1
9
9
8
0
1000
Reserved
4
9
Figure 20-190. WCAPE Control Field (C31:C0)
31
29
28
27
Reserved
Request type
3
2
15
13
26
25
Control
24
Prv.
1
1
12
8
23
22
21
16
Reserved
Conditional address
3
9
7
6
5
4
3
2
1
0
Conditional address
Pin select
Ext
Reg
Capture
condition
Reserved
Register select
Int.
ena
9
5
1
2
2
2
1
Figure 20-191. WCAPE Data Field (D31:D0)
31
7
6
0
Time Stamp
Edge Counter
25
7
Cycles
One
Register modified
None
Description
This instruction captures the selected register into the data field [D31:D7] and
increments an event counter [D6:D0] if the specified capture condition is true
on the selected pin. This instruction can be used with all pins, but the time
stamp [D31:D7] has loop resolution only.
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event
Specifies the event that triggers the capture.
Table 20-97. Event Encoding Format for WCAPE
C6
C5
Capture Condition
0
0
Always
0
1
Capture on falling edge
1
0
Capture on rising edge
1
1
Capture on rising and falling edge
irq
ON generates an interrupt when the capture condition is met. No
interrupt is generated for OFF.
Default: OFF.
ts_data
Specifies the 25-bit integer value for [D31:D7]
Default: 0.
ec_data
Specifies the initial 7-bit integer value for [D6:D0].
Default: 0.
Execution
If (Specified Capture Condition is true on Selected Pin
OR Unconditional capture is selected)
{
Immediate Data Field[31:7] = Selected register value;
Immediate Data Field [6:0] = Immediate Data Field [6:0] + 1;
If (Interrupt Enable == 1) HETFLG[n] = 1;
/* n depends on address */
If ([C28:C27] == 01) Generate request on request line [P25:P23];
If ([C28:C27] == 11) Generate quiet request on request line [P25:P23];
Jump to Conditional Address;
}
Jump to Next Program Address;
Prv bit = Current Logic (Lx) value of selected pin; (always executed)
The specific interrupt flag that is triggered depends on the address from which the instruction is executed,
see Section 20.2.7.
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Chapter 21
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High-End Timer Transfer Unit (HTU) Module
This chapter describes the high-end timer transfer unit (HTU) module. The HTU is similar to the DMA
(Direct Memory Access) module, but it is specialized to transfer N2HET (High-End Timer) data to or from
the microcontroller RAM.
NOTE: This chapter describes a superset implementation of the HTU module that includes features
and functionality that require DMA. Since not all devices have DMA capability, consult your
device-specific datasheet to determine applicability of these features and functions to your
device being used.
Topic
21.1
21.2
21.3
21.4
21.5
21.6
...........................................................................................................................
Page
Overview ......................................................................................................... 970
Module Operation ............................................................................................. 971
Use Cases ....................................................................................................... 983
HTU Control Registers ...................................................................................... 986
Double Control Packet Configuration Memory .................................................... 1012
Examples ....................................................................................................... 1019
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21.1 Overview
The HET transfer unit is a dedicated direct memory access controller that transfers data between the
N2HET RAM and RAM buffers located in the main memory address range. This eliminates time
consuming CPU accesses to the N2HET RAM to gather measurement data or creating output waveforms
and thus freeing up the CPU to perform other tasks.
21.1.1 Features
•
•
•
•
•
•
•
•
•
970
Independently transfers data between the N2HET and the main memory
8 double control packets supporting dual buffer configuration
Transfer requests generated by N2HET instructions/events
One shot, circular and auto switch buffer transfer modes for each double control packet for flexible
buffer handling
Constant and post-increment addressing modes
32- or 64-bit transactions
Programmable memory protection region
Parity protect control packet RAM
Extensive diagnostic functionality
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21.2 Module Operation
The HTU is tightly coupled to the N2HET and is not intended to transfer data from other peripheral
modules. It initiates transfers with the help of requests generated by the N2HET program and configurable
control packets. Figure 21-1 shows a system block diagram of the HTU and the main path for the data
transfer. The tight coupling and the dedicated bus into the SCR (Switched Central Resource) reduces the
amount of data transferred on the peripheral bus, which increases the overall system performance.
However if the application decides to use the direct CPU access method to the N2HET RAM, it is free to
do so.
Figure 21-2 shows a more detailed block diagram of the HTU module.
Figure 21-1. System Block Diagram
RAM0
ARM
Main Datapath
SCR2
Slave
Port
RAM1
Main Datapath
Master
Port
SCR
Peripheral Bus
HTU
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Figure 21-2. HTU Block Diagram
HTU
N2HET
Control
Data
Data
FIFO
Address
Normal
Memory Protection
8
SCR2
Request
Quiet
8
Request
Control Packet
RAM
with Parity
Transfers between N2HET RAM and the main memory are triggered by 8 different normal N2HET
requests. Quiet requests are used for specific cases and are discussed in Section 21.2.4.1. Control
packets, which store the source and destination addresses, the transfer count and other information (see
Section 21.5), are associated with the requests. A FIFO decouples the read- and write-path and allows to
do data-packing in the case of different read- and write-data sizes. The application can specify a section of
memory into or from which the data is transferred. This serves as memory protection in the case that
information in the control packet RAM was unintentionally altered and avoids that the HTU can overwrite
important application data.
Control packets are implemented as double control packets (DCP) which allow to specify two buffers for
the data transfer. This enables the CPU to work with one buffer, while new data is transferred to/from the
other buffer.
The control packet defines:
• the start address of the source/destination buffers
• the N2HET instruction address location
• how many elements need to be transferred per request
• the buffer size as the number of elements times the number of frames
• the buffer handling
A transfer is triggered when a certain condition (for example, capture, compare condition) is detected by a
N2HET instruction. The N2HET instruction specifies which request line to the HTU will be triggered at the
event. The DCPs have a fixed assignment to the request lines and the corresponding assignment can be
found in the device datasheet. Once a request is triggered, it starts a frame transfer. A frame can contain
one or more elements. Elements are defined as 32-bit or 64-bit words of data.
Figure 21-3. Example of a HTU Transfer
Element Count =2
Frame count =4
Frame 1
Element1
HTUREQ
972
Frame 3
Frame 2
Element2
Element3
HTUREQ
Element4
Element5
Frame 4
Element6
HTUREQ
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Element8
HTUREQ
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21.2.1 Data Transfers between Main RAM and N2HET RAM
21.2.1.1 Addressing Modes
The addressing modes of a control packet need to be distinguished between the main RAM of the CPU
and the N2HET RAM.
Main RAM
For each double control packet (see Section 21.2.1.3), the addressing mode for the main RAM (RAM0/1)
can be configured to constant or post-increment mode in register IHADDRCT.
• Constant Addressing: In constant mode, the HTU writes/reads the data to/from the same address in
the main RAM.
• Post-increment Addressing: In post-increment mode, the HTU writes/reads the data to/from the main
RAM by incrementing through the addresses after each transfer. If 32-bit transfers are selected it will
automatically increment by 4 Byte, if 64-bit transfers are selected, it will increment by 8 Byte. The
examples of Use Cases illustrate the post-increment mode, where the elements of consecutive frames
are transferred to/from consecutive locations in the main RAM buffer.
N2HET RAM
How a DCP addresses the N2HET RAM is determined by the initial N2HET address, the initial element
counter (IETCOUNT) and the N2HET addressing mode (ADDMH). The main difference to the main RAM
addressing mode is that the HET address is reset to the initial HET address for every first element of a
frame. To implement constant addressing, the initial element counter needs to be set to 1. Post-increment
addressing is selected by programming the initial element counter to a value other than 1.
21.2.1.2 Single Buffer Implementation
In a single buffer implementation, the DCP is set up to transfer data to/from a single buffer in the main
RAM. With each transfer request, the programmed number of elements is transferred and the buffer
pointer is reset to its starting address after the programmed number of frame transfers have completed.
Figure 21-4 shows the request on one request line of the HTU and the frame running on the assigned
control packet visualized by the element counter. In the diagram, the frame has 5 element transfers
(element count = 5).
Before the application reads the buffer, it has to disable the control packet to avoid that new data
overwrites the buffer while it's being accessed by the application. Regardless of the control packet being
disabled at t1 or t2 the last frame will always be completed, since the trigger request has been received
already. The application can determine any ongoing transfers by the TIPF flag and the NACP bits.
• One Shot Buffer Mode: If TMBA or TMBB is set to one shot buffer mode then the data stream will
stop after all elements of buffer A or buffer B have been transferred. This means that the
corresponding DCP will be disabled after the last frame was transferred to/from buffer A or B and
CFTCTA or CFTCTB decrements to 0.
• Circular Buffer Mode: If TMBA or TMBB is set to circular buffer mode, then the data stream will
continue back at the start of buffer A or B after all elements of buffer A or B have been transferred. The
example of Timing Example for Circular Buffer Mode assumes IETCOUNT = 3 (Initial Element Transfer
Count), IFTCOUNT = 3 (Initial Frame Transfer Count, SIZE = 0 (Size of Transfer = 32-bit) and
ADDFM = 0 (Addressing Mode Main Memory = Post Increment). So there are in total 9 32-bit values in
the buffer. It also assumes IFADDRx = 10h. "U" means uninitialized.
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Figure 21-4. Single Buffer Timing and Memory Representation
t2
t1
TU request (1)
Element Counter
Element Number
X
X
X
5 4 3 2 1
6 7 8 9 10
5 4 3 2 1
1 2 3 4 5
5 4 3 2 1
11 12 13 14 15
Memory View
15
14
13
12
Increasing Address
11
10
9
1 Buffer
8
7
15
6
15
5
15
4
15
3
15
2
15
1
Figure 21-5. Timing Example for Circular Buffer Mode
end of
buffer
end of
buffer
request
3
element counter
buffer location
2
1
3
2
1
3
1Ch 20h 24h
10h 14h 18h
2
1
3
2
1
3
10h 14h 18h
28h 2Ch 30h
2
1
3
1Ch 20h 24h
2
1
28h 2Ch 30h
busy bit
frame counter
CFTCTx
U
2
1
0
2
1
full address
CFADDRx
U
1Ch
28h
34h
1Ch
28h
buffer full flag
BFINTFL
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21.2.1.3 Dual Buffer Implementation
The transfer unit provides double control packets (DCPs) supporting the use of two buffers per data
stream (per HTU request source). If one buffer should be read by the CPU or DMA, the data stream is
directed to the other buffer and the first buffer is frozen. Switching to the other buffer can be triggered with
a write access to the CPENA register or with the DCP configured to automatically switch to the other
buffer when the programmed number of frames has been transmitted. Freezing the buffer avoids this
buffer to be overwritten with new HET data while the CPU or DMA reads this buffer.
Figure 21-6 shows a timing example of two HET instructions 1 and 2, which are the request sources for
the HTU (and are controlled by DCP 1 and DCP 2). Each generated frame has 5 element transfers.
Request source 1 has two RAM buffers, controlled by two control packets 1A and 1B. Request source 2
has two RAM buffers, controlled by two control packets 2A and 2B.
Figure 21-6. Dual Buffer Timing
t1
TU request (1)
Element Counter 1A
Element Counter 1B
Element Number
X
TU request (2)
Element Counter 2A
Element Counter 2B
Element Number
X
X
5 4 3 2 1
5 4 3 2 1
1 2 3 4 5
6 7 8 9 10
X
X
5 4 3 2 1
11 12 13 14 15
X
5 4 3 2 1
16 17 18 19 20
X
5 4 3 2 1
5 4 3 2 1
1 2 3 4 5
6 7 8 9 10
X
5 4 3 2 1
11 12 13 14 15
t3
t2
5 4 3 2 1
16 17 18 19 20
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10
9
8
7
6
5
4
3
2
1
Buffer 1A
Switch
Increasing Address
Increasing Address
Memory View for DCP-1A/B
10
9
8
7
6
5
4
3
2
1
Buffer 1A
20
19
18
17
16
15
14
13
12
11
Buffer 1B
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Figure 21-6 shows a switch at time t1, where buffer 1A is frozen and data stream 1 is directed to buffer
1B, but only after the frame has been completed. It also shows the time (t2 or t3) where 2A is frozen and
data stream 2 is directed to buffer 2B. If the switch happens between the request and the start of the
frame (for example, time t3), then the frame is processed by the new control packet (although the old
control packet was active at the time of the request). The delays between the HTU requests and the start
of the element transfers result from the fact that the HTU can process only one transfer at a time.
Auto Switch Buffer Mode
If TMBA is set to auto switch mode, then the data stream will continue at the start of buffer B after all
elements of buffer A have been transferred. This means that in the CPENA register, CP A is disabled and
CP B is enabled automatically and buffer B uses its initial main memory address and initial frame counter
to start. The same principle is valid for TMBB and buffer B.
The examples of Figure 21-7 assumes IETCOUNT=3 (Initial Element Transfer Count), IFTCOUNT=3
(Initial Frame Transfer Count, SIZE=0 (Size of Transfer = 32-bit) and ADDFM=0 (Addressing Mode Main
Memory = Post Increment). So there are in total 9 32-bit values in buffer A and B. It also assumes
IFADDRB=10h and IFADDRA=40h. "U" means uninitialized.
Figure 21-7. Timing Example for Auto Switch Buffer Mode
auto
switch
auto
switch
request
element counter
3
buffer location
2
1
3
10h 14h 18h
2
1
3
1Ch 20h 24h
2
1
3
2
1
3
2
1
3
2
1
28h 2Ch 30h
busy bit
frame counter
CFTCTB
U
2
1
0
full address
CFADDRB
U
1Ch
28h
34h
buffer full flag
BFINTFL
buffer location
40h 44h 48h
4Ch 50h 54h
58h 5Ch 60h
busy bit
frame counter
CFTCTA U
full address
CFADDRA U
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1
0
4Ch
58h
64h
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21.2.1.4 General Control Packet Behavior
The action defined by the selected mode will be performed at the end of the last frame, which has the
frame counter value of 1. The one shot and auto switch mode will automatically update the CPENA
register at this time. Note, that for all three modes listed above, it is possible to switch to the other buffer
by writing to CPENA before the end of the current buffer is reached.
If a write access to CPENA happens while the last frame of DCP x (with frame counter = 1) is transferred
then the priority is defined by Table 21-1.
Table 21-1. CPENA / TMBx Priority Rules
Write access to CPENA bits (2 × x+1) and (2 × x) during the
frame with frame counter = 1 (1)
Priority Rule
Disable:
01 --> 00 or
10 --> 00
Disabling the DCP by the write to CPENA has priority, TMBx is
ignored.
Stay:
01 --> 01 or
10 --> 10
The write access to CPENA is ignored, TMBx has priority and
defines the action.
Switch:
01 --> 10 or
10 --> 01
Switching the DCP by the write to CPENA has priority, TMBx is
ignored.
(1)
See read table of CPENA register (Table 21-14)
There could be a case where the CPU wants to do main memory operations, but does not want the HTU
modifying the main memory. It could happen that a request was already active, but the frame transfer
hasn't started yet when the application disabled the control packets. The timing diagram in Figure 21-8
shows this scenario.
Figure 21-8. Timing for Disabling Control Packets
DCP Disable
Request
Busy Bit
Frame Start
Since the request for the transfer was already received before the DCPx is disabled, the HTU will still start
the frame transfer. The application would poll the BUSYx bit during the time the DCPx was disabled and
before the frame was started and would read a non-busy information. It then would start the main memory
operations thinking all transfers have completed, however after some time the HTU will start the
outstanding frame transfer and corrupt the main memory.
To avoid this, the application can set the VBUSHOLD bit to disable all transactions between the HTU and
the main memory. It has to poll the BUSBUSY bit to ensure that no outstanding transactions on the bus
are pending. The HTU will still receive all transfer requests from the N2HET, but it will not be able to
transfer any data to or from the main memory, while the VBUSHOLD bit is set.
21.2.2 Arbitration of HTU Elements and Frames
•
•
Frames do not interrupt each other. If a request occurs on DCP x while another frame runs on DCP y
(and x ≠ y), then the current frame completes before the new frame starts.
If two or more request lines are active, the request line with the lower number (specified in the request
number field of the corresponding N2HET instruction) is serviced first.
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21.2.3 Conditions for Frame Transfer Interruption
If a frame is currently transferred on DCP x and one of the events listed below happens, then the event
will (1.) clear the element counter of DCP x, (2.) stop new element transfers on DCP x (3.) clear the active
busy bit of DCP x and (4.) disable DCP x in the CPENA register. The DCPs other than DCP x will not be
affected.
• Request Lost Error of DCP x (with CORL bit set to 0).
• Parity Error of DCP x (with parity check enabled and COPE bit set to 0). See also Section 21.2.6.
• Bus Error of DCP x.
• Memory Protection Error of DCP x (with memory protection enabled). See also Section 21.2.5.
• Writing a 1 to a BUSY bit (belonging to DCP x) if that bit is 1. There is no effect if the BUSY bit is 0.
• Writing a 1 to the HTURES bit.
When a memory protection error occurs, the access to the protected address is blocked. The frame is
stopped before the element, which caused the violation transfer, starts. All other errors will let the current
element transfer finish.
In case of the Request Lost and Bus Error, one more element transfer goes on the bus, before the frame
is actually stopped. Accordingly, the busy bit is cleared after the element, which follows the element that
caused the error.
In case of the Bus Error, the counter for the element, which follows the element that caused the error, is
captured to the ERRETC register field.
NOTE: If the HTUEN bit is cleared during a frame is transferred, then the frame will be completed
before the HTU is disabled.
21.2.4 HTU Overload and Request Lost Detection
If the number of different HTU request sources is "high", the period between the requests is "short" and/or
the initial element counter values are "big", then the HTU could get into a overload situation. In Figure 219, all requests marked with "L" are lost, since their frame is not completed at the time the next request
occurs. Each number in the rows "TU request (x)" represents a time, where the associated N2HET
instruction generates a request on DCP x. The arrows in Figure 21-9 point to the associated frame, which
could be delayed compared to the request. The delays are caused by different frames, which are currently
processed. The figure assumes that the CORL bit in the RLBECTRL register is set, which causes the DCP
to stay enabled and let the data stream continue after a request lost error occurred on the DCP (see 3-L
for TU request (2)).
Figure 21-9. Timing Example Including Lost Requests
1
TU request (1)
Element Counter
54321
TU request (2)
Element Counter
2
3
54321
1
2
3-L
54321
54321
1
TU request (3)
ElementCounter
4
54321 54321
2
4
54321
3-L
54321
Lost requests are signaled with the RLOSTFL register, and if enabled, can generate request lost
interrupts.
If the CORL bit is set, a frame will be completed and the corresponding DCP stays enabled even if a
request lost was generated during this frame.
In dual buffer mode, the request lost detection works continuously, independent of the CP switches.
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21.2.4.1 Requests and Quiet Requests
In addition to generating too many transfer requests and thus overloading the HTU and not being able to
transfer data at all, it can happen that inconsistent data is transferred. The following examples illustrate
such scenarios.
In the examples below, the HTU reads a frame of three elements from the datafield of three different
instructions. In Figure 21-10, the L3-Instruction generates the HTU request at time t2, t7, and so on. and
the according frame (at t3). The frame is delayed because of the HTU load. However, as shown in
Figure 21-10, the delay still allows the frame to complete before the datafield of instruction L1 is updated
again. However, when the delay is longer (as shown in Figure 21-11), then the frame could fall into the
N2HET loop (LRP), in which the N2HET updates the data fields of the L1, L2 and L3 instructions. In this
case, the HTU could read inconsistent data as shown in the diagram. A wrong (new) value is read from L1
(at time t3), but correct ("old") values are read from L2 and L3 (at times t4 and t5).
Figure 21-10. Timing that Generates No Request Lost Error
LRP
Signal
Quiet Request
L1_Instr_DF[31:7]
Quiet Request
3
L2_Instr_DF[31:7]
6
1
L3_Instr_DF[31:7]
2
3
2
Delay caused by TU load
t1 t2
t3 t4 t5
t6 t7
Frame
Request
Request
Figure 21-11. Timing that Generates a Request Lost Error
LRP
Signal
L1_Instr_DF[31:7]
L2_Instr_DF[31:7]
L3_Instr_DF[31:7]
Quiet Request
Quiet Request
3
6
1
2
2
3
Delay caused by TU load
t1 t2
t3 t4 t5 t6 t7
Frame
Request
Request
To prevent sending inconsistent data, the N2HET instructions are able to generate a quiet request, which
does not originate a transfer but is only used by the HTU for consistency check. If a frame has not
completed since the last request (or has not even started) at the time the quiet request occurs, then the
HTU signals a request lost error. All instructions, which allow to generate a request can be configured to
generate a quiet request instead. So in the examples of Figure 21-10 and Figure 21-11, instruction L1
should be configured to generate a quiet request and instruction L3 to generate a normal request. In the
case of Figure 21-11, the corresponding bit in the RLOSTFL register will be set.
It is the responsibility of the N2HET software to enable a quiet request for the first instruction of an
instruction block, which is addressed by DCP x, and to enable a normal request only for the last
instruction of this block. Since enabling the quiet request should enable a proper request lost detection for
DCP x, both N2HET instructions need to specify the same DCP x (reqnum=x).
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The control fields of the HET instructions provide a 2-bit field to configure one of the following possibilities
(as shown in Table 21-2). A 3-bit field in the program field will select which of the 8 Double Control
Packets will be triggered by the request.
Table 21-2. Triggered Control Packets
Request Type Bit 1
Request Type Bit 0
Don't care
0
No request
Request Number
0
1
Generate normal request
1
1
Generate quiet request
Specify number 0, 1,... or 7, which selects the
HTU or DMA request line.
In the case of very light HTU load, but higher signal requirements (for example, high frequency), the quiet
request could also be used to define periods in which the data read by a control packet is safe. The
following HET code will capture counter time stamps to the L1-WCAP data field after rising edges (at pin
CC6) and to the L2-WCAP data field after falling edges (at pin CC6):
L0 CNT {reg=A, max=0x1FFFFFF}
L1 WCAP {reqnum=3, request=GENREQ, event=RISE, reg=A, pin=CC6}
L2 WCAP {reqnum=3, request=QUIET, event=FALL, reg=A, pin=CC7}
; HET HRSHARE feature configured to assign both WCAPs to pin CC6
Figure 21-12. Timing Example for Two WCAP Instructions
f(n-1)
LRP
r(n)
f(n)
r(n+1)
Pin CC6
L00-CNT-DF
20
21
22
L01-WCAP-DF
23
24
22
R
L02-WCAP-DF
24
21
QR
OK
QR
RL
OK
RL
e1 e2
e2
TU Delay Frame
The HTU frame will have two elements: The first gives the time stamp of the rising edge r(n) and the
second gives the time stamp of the previous falling edge f(n-1). Using the code above, requests (R) and
the quiet requests (QR) will occur at the times shown in Figure 21-12, and a request lost will only be
signaled when the frame makes an access during the times marked with RL. So reading [22, 21] as frame
elements is correct. If the signal frequency would increase, then a wrong pair [22, 23] could be read, but
this will be signaled by a request lost error since at least e2 falls into the RL period.
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21.2.5 Memory Protection
This feature allows restricting accesses to certain areas in memory in order to protect critical application
data from unintentionally being manipulated by the HTU.
If the HTU memory protection feature is disabled, the full 4 GB address range can be accessed by the
HTU without exception. There are two memory regions that start and end addresses can be configured.
With the HTU memory protection feature enabled, read and write accesses by the HTU IFADDRA and
IFADDRB registers inside the defined regions are allowed. HTU access to its tightly-coupled memory is
independent of the MPU, it routes through the dedicated HTU/N2HET bus using the IHADDR bits in the
IHADDRCT register. See Section 21.2 for details on the tightly-coupled bus. For accesses outside the
regions, one of two modes is configurable:
• Any access performed by the HTU is forbidden and will be signaled to the ESM module. Write
accesses will be blocked.
• Read access is allowed but write access will be blocked and signaled to the ESM module.
To use one region only, REG01ENA must be 0. Bits ACCR01, INTENA01, and register settings of MP1S
and MP1E will be ignored.
To
1.
2.
3.
4.
use both regions, the following rules must be followed:
Memory mapped region 0 covers a lower memory area as Memory mapped region 1.
REG01ENA is a 1 and REG0ENA is a 0.
ACCR01 is set for the desired access type, ACCR0 is ignored.
INTENA01 is set for the desired action, INTENA0 is ignored.
If an element transfer of DCP x generates a memory protection error, then:
1. The element counter of DCP x is cleared.
2. All new element transfers on DCP x are stopped.
3. The active busy bit of DCP x is cleared.
4. DCP x is disabled in the CPENA register. The DCPs other than DCP x will not be affected.
5. The FT flag will be set.
6. An error is signaled to the ESM module.
21.2.6 Control Packet RAM Parity Checking
The HTU module can detect parity errors in the DCP (Double Control Packet) RAM. DCP RAM parity
checking is implemented using one parity bit per byte. Even or odd parity checking can be selected in the
DEVCR1 register of the system module and can be enabled/disabled by a 4-bit key in the PCR register.
During a read access to the DCP RAM, the parity is calculated based on the data read from the RAM and
compared with the good parity value stored in the parity bits. The parity check is performed when the HTU
or any other master (for example, CPU) makes a read access to the DCP RAM. A read access within the
RAM section of an initial or current DCP checks all 16 bytes of the DCP at a time (see also DCP memory
map). For example, if a byte read access happens for DCP RAM address 0, but there is a parity error at
byte address Ch then the parity error will occur and the captured parity address will be Ch and not 0. The
address of the byte in which the error occurred can be read from the PAR register. If successive DCP
RAM read accesses generate multiple parity errors, only the address of the first detected error will be
captured and the PAR register will not be updated by subsequent errors until it is read by the application.
When multiple errors in a 16 byte word are detected, only the address of the lowest byte will be captured.
The application can decide whether to stop any transfers when a parity error is detected or to continue
transferring data. If the COPE (Continue On Parity Error) bit is 0 and parity checking is enabled, then the
HTU will not start the frame and the corresponding DCP will be automatically disabled in the CPENA
register. If a master other than the HTU (for example, CPU) reads the RAM section of DCP x and a parity
error is detected during this read access, while the parity check is enabled and the COPE bit is 0, then the
DCP x will be automatically disabled in the CPENA register. If a frame for this DCP x is ongoing during
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this read access, then in addition the element counter of DCP x is cleared, all new element transfers on
DCP x are stopped and the active busy bit of DCP x is cleared. With COPE set to 1 and the parity check
enabled, the parity checking will still be performed, but the data transfer of an active DCP continues after
a parity error was detected for this DCP. So neither the DCP with the parity error will be disabled nor the
frame will be stopped.
After a DCP is enabled (with CPENA using BIM=0), then at the start of the first frame, the HTU performs
the parity check only on the initial DCP, since it does not need the current DCP information. For further
frames, the HTU performs the parity check for both initial and current DCP, since it needs both
information.
On a parity error detection, an error will also be signaled to the ESM module.
21.2.6.1 Parity Bit Mapping and Testing
To test the parity checking mechanism, the parity RAM can be made accessible in order to allow manual
fault insertion. Once the TEST bit is set, the parity bits are mapped to address FF4E 0200h.
When in test mode (the parity RAM is accessible), no parity checking will be done when reading from
parity RAM, but parity checking will still be performed for read accesses to the DCP RAM.
Table 21-3 and Table 21-4 show how the corresponding parity bits of the DCP RAM bytes are mapped
into the memory.
Table 21-3. DCP RAM
Bit
31
24
23
16
15
8
7
0
FF4E 0000h
Byte 0
Byte 1
Byte 2
Byte 3
FF4E 0004h
Byte 4
Byte 5
Byte 6
Byte 7
FF4E 0008h
Byte 8
Byte 9
Byte 10
Byte 11
FF4E 000Ch
Byte 12
Byte 13
Byte 14
Byte 15
Table 21-4. DCP Parity RAM
Bit
24
16
8
0
FF4E 0200h
P0
P1
P2
P3
FF4E 0204h
P4
P5
P6
P7
FF4E 0208h
P8
P9
P10
P11
FF4E 020Ch
P12
P13
P14
P15
Each byte in DCP RAM has its own parity bit in the DCP Parity RAM. P0 is the parity bit for byte 0, P1 is
the parity bit for byte 1, and so on.
21.2.6.2 Initializing Parity Bits
After device power up, the DCP RAM content including the parity bit cannot be guaranteed. In order to
avoid parity failures, when reading DCP RAM, the RAM has to be initialized first. This can simply be done
by writing known values into the RAM by software and the corresponding parity bit will be automatically
calculated.
Another possibility to initialize the DCP memory and its parity bits is to use the system module, which is an
on-chip module external to the HTU. This module can start the automatic initialization of all RAMs on the
microcontroller including the HTU DCP RAM. This function initializes the complete DCP RAM to 0 when
activated by the system module. Depending on the even/odd parity selection, all parity bits will be
calculated accordingly. The HTUEN bit must be cleared and the parity functionality must be enabled (by
PARITY_ENA) during the automatic DCP RAM initialization. If HTUEN is 1 when the initialization is
triggered by the system module, then the initialization will not be performed and the HTU operation is not
affected. If a 1 is written to HTUEN during the initialization, then the HTUEN bit will be set but the HTU will
not be enabled before the initialization completes.
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21.3 Use Cases
21.3.1 Example: Single Element Transfer with One Trigger Request
This example considers the case that the HTU fills a RAM buffer in the main (CPU) data RAM. The HTU
reads from the instruction which generates the HTU requests.
This example uses a PCNT instruction. Every time the PCNT has captured a new pulse or period value, it
will automatically generate a transfer request to the HTU, which then transfers the value from the N2HET
RAM to the buffer RAM. So over time consecutive locations in the RAM buffer can be filled with
consecutive measurement values captured into the N2HET RAM data field of the same PCNT instruction
without loading or interrupting the CPU.
21.3.2 Example: Multiple Element Transfer with One Trigger Request
The following example shows how the HTU could be used to fill a RAM buffer with a data stream including
different types of measurement values belonging to the same N2HET input signal (on one pin): Time
stamp values (WCAP), edge counter values (ECNT) and last period values (PCNT).
Figure 21-13 shows the timing and Table 21-5 shows the byte addresses of the program- (PF), control(CF), data- (DF) and reserved field (res) of the WCAP-ECNT-PCNT instruction block. The timing and code
example assumes that all three instructions are assigned to the same N2HET pin.
Figure 21-13. Timing of the WCAP, ECNT, PCNT Example
CNT
2
WCAP
3
5
4
1
9
12
10
3
3
Quiet Request
Request
11
10
2
2
PCNT
8
6
3
ECNT
7
6
4
Quiet Request
Request
Quiet Request
Request
Table 21-5. Field Addresses of the WCAP, ECNT, PCNT Example
PF
CF
DF
Res
WCAP
30h
34h
38h
3Ch
ECNT
40h
44h
48h
4Ch
PCNT
50h
54h
58h
5Ch
In the HET code the HTU request is enabled only for the last instruction (PCNT) of the WCAP-ECNTPCNT block. When the PCNT condition is true, it will cause the generated HTU frame to perform three
HTU element reads from the data fields of WCAP, ECNT, and PCNT.
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32-Bit-Transfer of data fields:
Table 21-6 shows how the internal element counter, frame counter and the address registers change over
time for the example described above. Every time the PCNT instruction captures a new value it generates
a request to the HTU, which starts a frame. At the end of each frame the frame counter decrements.
Table 21-6. 32-Bit-Transfer of Data Fields (1)
Frame Counter
3
Element Counter
2
1
3
2
1
3
2
1
3
2
1
Source Address (HET)
38h
48h
58h
38h
48h
58h
38h
48h
58h
Destination Address (main CPU RAM)
70h
74h
78h
7Ch
80h
84h
88h
8Ch
90h
(1)
Shows the byte addresses
The destination buffer is filled with the WCAP, ECNT, and PCNT data field values as shown in Table 21-7.
Table 21-7. Destination Buffer Values
Address
Frame Count
Instruction
Value
70h
3
WCAP
3
74h
3
ECNT
1
78h
3
PCNT
2
7Ch
2
WCAP
6
80h
2
ECNT
2
84h
2
PCNT
3
88h
1
WCAP
10
8Ch
1
ECNT
3
90h
1
PCNT
4
The corresponding setup of the HTU control packet for this example is as follows:
IHADDR
= 0x38
// points to WCAP data field
IFADDRA
= 0x70
// points to buffer
ITCOUNT [frame count = 3] [element count = 3]
IHADDRCT = [DIR: Read HET and write to full address]
[SIZE: 32 bit]
[ADDMH: Increment HET address by 16 bytes]
[ADDMF: Post increment full address mode]
[Any transfer mode]
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21.3.3 Example: 64-Bit-Transfer of Control Field and Data Fields
Table 21-8 shows how the internal element counter, frame counter and the address registers change over
time assuming the same example as in Section 21.3.2, but now with a transfer size set to 64-bit. The HET
address now points to the control field of the instruction, so CF and DF are transferred as 64 bit data.
Table 21-8. 64-Bit-Transfer of Control Field and Data Fields (1)
Frame Counter
Element Counter
3
2
1
3
2
1
3
2
1
3
2
1
HET (Source) Address
34h
44h
54h
34h
44h
54h
34h
44h
54h
Full (Destination) Address
70h
78h
80h
88h
90h
98h
A0h
A8h
B0h
(1)
Shows the byte addresses.
The destination buffer is filled with the WCAP, ECNT, and PCNT control and data field values as shown
on the right in Table 21-9.
Table 21-9. Destination Buffer Values
Address
Frame Count
Instruction
Value
70h
3
WCAP
Control Field Value
74h
3
WCAP
3
78h
3
ECNT
Control Field Value
7Ch
3
ECNT
1
80h
3
PCNT
Control Field Value
84h
3
PCNT
2
88h
2
WCAP
Control Field Value
8Ch
2
WCAP
6
90h
2
ECNT
Control Field Value
94h
2
ECNT
2
Control Field Value
98h
2
PCNT
9Ch
2
PCNT
3
A0h
1
WCAP
Control Field Value
A4h
1
WCAP
10
A8h
1
ECNT
Control Field Value
ACh
1
ECNT
3
B0h
1
PCNT
Control Field Value
B4h
1
PCNT
4
The necessary setup of the HTU control packet (see Section 21.5) for this example is as follows:
IHADDR
= 0x34 (points to WCAP control field)
IFADDR
= 0x70 (points to buffer)
ITCOUNT [frame count = 3] [element count = 3]
IHADDRCT = [DIR: Read HET and write to full address]
[SIZE: 64 bit]
[ADDMH: Increment HET address by 16 bytes]
[ADDMF: post increment full address mode]
[Any transfer mode]
For different applications, which have the transfer direction set for reading the buffer and writing to HET
fields, the 64-bit transfer could be used to change the conditional addresses together with a new data
field.
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21.4 HTU Control Registers
Table 21-10 provides a summary of the registers. The registers support 8-bit, 16-bit, and 32-bit writes. The
offset is relative to the associated peripheral select. See the following sections for detailed descriptions of
the registers. The base address for the control registers is FFF7 A400h for HTU1 and FFF7 A500h for
HTU2. The address locations not listed, are reserved.
Table 21-10. HTU Control Registers
986
Offset
Acronym
Register Description
Section
00h
HTU GC
Global Control Register
Section 21.4.1
04h
HTU CPENA
Control Packet Enable Register
Section 21.4.2
08h
HTU BUSY0
Control Packet Busy Register 0
Section 21.4.3
0Ch
HTU BUSY1
Control Packet Busy Register 1
Section 21.4.4
10h
HTU BUSY2
Control Packet Busy Register 2
Section 21.4.5
14h
HTU BUSY3
Control Packet Busy Register 3
Section 21.4.6
18h
HTU ACPE
Active Control Packet and Error Register
Section 21.4.7
20h
HTU RLBECTRL
Request Lost and Bus Error Control Register
Section 21.4.8
24h
HTU BFINTS
Buffer Full Interrupt Enable Set Register
Section 21.4.9
28h
HTU BFINTC
Buffer Full Interrupt Enable Clear Register
Section 21.4.10
2Ch
HTU INTMAP
Interrupt Mapping Register
Section 21.4.11
34h
HTU INTOFF0
Interrupt Offset Register 0
Section 21.4.12
38h
HTU INTOFF1
Interrupt Offset Register 1
Section 21.4.13
3Ch
HTU BIM
Buffer Initialization Mode Register
Section 21.4.14
40h
HTU RLOSTFL
Request Lost Flag Register
Section 21.4.15
44h
HTU BFINTFL
Buffer Full Interrupt Flag Register
Section 21.4.16
48h
HTU BERINTFL
BER Interrupt Flag Register
Section 21.4.17
4Ch
HTU MP1S
Memory Protection 1 Start Address Register
Section 21.4.18
50h
HTU MP1E
Memory Protection 1 End Address Register
Section 21.4.19
54h
HTU DCTRL
Debug Control Register
Section 21.4.20
58h
HTU WPR
Watch Point Register
Section 21.4.21
5Ch
HTU WMR
Watch Mask Register
Section 21.4.22
60h
HTU ID
Module Identification Register
Section 21.4.23
64h
HTU PCR
Parity Control Register
Section 21.4.24
68h
HTU PAR
Parity Address Register
Section 21.4.25
70h
HTU MPCS
Memory Protection Control and Status Register
Section 21.4.26
74h
HTU MP0S
Memory Protection 0 Start Address Register
Section 21.4.27
78h
HTU MP0E
Memory Protection 0 End Address Register
Section 21.4.28
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21.4.1 Global Control Register (HTU GC)
Figure 21-14. Global Control Register (HTU GC) [offset = 00]
31
25
24
23
17
16
Reserved
VBUSHOLD
Reserved
HTUEN
R-0
R/WP-0
R-0
R/WP-0
15
9
8
7
1
0
Reserved
DEBM
Reserved
HTURES
R-0
R/WP-0
R-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 21-11. Global Control Register (HTU GC) Field Descriptions
Bit
31-25
24
23-17
16
Field
Reserved
Value
0
VBUSHOLD
Reserved
Description
Reads return 0. Writes have no effect.
Hold the VBUS bus
0
The VBUS is not held.
1
The VBUSHOLD bit holds the bus used to transfer data between the HTU and the N2HET module.
When the BUS_BUSY bit is 0 then the bus is no longer busy. While the bus is held, requests will still be
accepted. They will be acted upon when the VBUSHOLD is 0. Request lost conditions will be detected
and interrupts generated if they are enabled.
0
Reads return 0. Writes have no effect.
HTUEN
Transfer Unit Enable Bit
0
The Transfer Unit is disabled.
1
The Transfer Unit is enabled.
The configuration registers and control packets should be set up first before the HTUEN bit is set to 1 to
prevent it from carrying out unintended bus transactions. If the HTUEN bit is cleared to 0 during a frame
is transferred, then the frame will be completed before the HTU is disabled.
The HTUEN bit must be cleared to 0 and the parity functionality must be enabled (by PARITY_ENA)
during the automatic DCP RAM initialization (see Initializing Parity Bits). If HTUEN is 1 when the
initialization is triggered by the system module, then the initialization will not be performed and the HTU
operation is not affected. If a 1 is written to HTUEN during the initialization, then the HTUEN bit will be
set but the HTU will not be enabled before the initialization completes.
Note: If HTU is disabled during a frame transfer, then the ongoing current frame will be
completed before the HTU module is disabled. If enabled again, then the transfer will restart
from the initial frame count for the CP programmed.
15-9
8
Reserved
0
DEBM
Reads return 0. Writes have no effect.
Debug Mode
0
The Transfer Unit is stopped in debug mode.
The HTU will complete the current frame, but not start any new frames. It will also ignore all requests
from the HET and not generate any request lost signals.
1
The Transfer Unit continues operation in debug mode.
Note: Since the HET has also an "ignore suspend" bit, there a several possibilities for the behavior of
the HET and HTU in suspend mode.
7-1
Reserved
0
HTURES
0
Reads return 0. Writes have no effect.
HTU Software Reset Request
0
Reset request is not issued to the HTU module. Writing a 0 has no effect.
1
Reset request is issued to the HTU module.
Ongoing element transfers will be completed, before resetting the complete HTU module, similar to a
hardware reset. The HTURES bit will also be cleared. The recommended order of operations is:
•
•
•
•
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Set the software reset bit. This also clears HTUEN.
Wait for the HTURES bit to clear.
Configure the HTU registers and packets.
Set the HTUEN bit to begin operation.
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21.4.2 Control Packet Enable Register (HTU CPENA)
This register enables or disables the individual double control packets (DCP).
Figure 21-15. Control Packet Enable Register (HTU CPENA) [offset = 04h]
31
16
Reserved
R-0
15
0
CPENA
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 21-12. Control Packet Enable Register (HTU CPENA) Field Descriptions
Bit
Field
Value
31-16
Reserved
15-0
CPENA
0
Description
Reads return 0. Writes have no effect.
CP Enable Bits
Bits (2*x) and (2*x+1) of CPENA control the double control packet (DCP) x (whereby x must be within
0,1,....,7).
See Table 21-13 for write rules.
See Table 21-14 for read rules.
Table 21-13. CPENA Write Results
Control packets (CP) B and A of DCP x are affected as
follows:
Bit (2*x+1)
Bit (2*x)
0
0
CP B and A are not changed.
0
1
CP B is disabled and CP A are enabled simultaneously.
1
0
CP B is enabled and CP A are disabled simultaneously.
1
1
CP B and CP A are both disabled simultaneously.
Table 21-14. CPENA Read Results
•
•
•
988
Bit (2*x+1)
Bit (2*x)
0
0
State of DCP:
The DCP is disabled.
0
1
CP B is disabled and CP A is enabled.
1
0
CP B is enabled and CP A is disabled.
1
1
Cannot be read.
The conditions listed in Section 21.2.3 can automatically disable DCP x. In this case, bits (2*x) and
(2*x+1) are both automatically set to 0.
When bits (2*x) and (2*x+1) change from 00 to 01 or from 00 to 10 caused by a write access to
CPENA, then old pending requests on the corresponding request line are cleared. This means only
new requests which occur after this write access cause the first HTU transfer for this DCP. This is not
the case when switching CPs (from 10 to 01 or from 01 to 10).
CP A and/or CP B of a DCP can be configured to one-shot, circular or auto-switch transfer mode via
the TMBA or TMBB bits in the IHADDRCT control packet configuration. If a write access to CPENA
occurs during the last frame of a buffer (with frame counter = 1) then the action defined by the write
access to CPENA and the action defined by TMBx can contradict. The priority rules for this case are
given in Table 21-1.
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21.4.3 Control Packet (CP) Busy Register 0 (HTU BUSY0)
This register displays the status of individual control packets.
Figure 21-16. Control Packet (CP) Busy Register 0 (HTU BUSY0) [offset = 08h]
31
25
24
23
17
16
Reserved
BUSY0A
Reserved
BUSY0B
R-0
R/W1CP-0
R-0
R/W1CP-0
15
9
8
7
1
0
Reserved
BUSY1A
Reserved
BUSY1B
R-0
R/W1CP-0
R-0
R/W1CP-0
LEGEND: R/W = Read/Write; R = Read only; W1CP = Write 1 in privilege mode only to clear the bit; -n = value after reset
Table 21-15. Control Packet (CP) Busy Register 0 (HTU BUSY0) Field Descriptions
Bit
Field
31-25
Reserved
24
BUSY0A
23-17
Reserved
16
BUSY0B
15-9
Reserved
8
BUSY1A
7-1
Reserved
0
BUSY1B
Value
0
Description
Reads return 0. Writes have no effect.
Busy Flag for CP A of DCP 0
0
Reads return 0. Writes have no effect.
Busy Flag for CP B of DCP 0
0
Reads return 0. Writes have no effect.
Busy Flag for CP A of DCP 1
0
Reads return 0. Writes have no effect.
Busy Flag for CP B of DCP 1
The bit is set when the frame on the according control packet starts (as shown in the diagram below,
there could be a delay between the request and the start of the frame).
The bit is automatically cleared at any of the following conditions:
1. At the end of a frame.
2. Writing a 1 to a BUSY bit (of DCP x) if that bit is 1. This will:
a. clear the element counter of DCP x
b. stop all new element transfers on DCP x
c. clear the busy bit
d. and disable DCP x in the CPENA register.
There is no effect, if the BUSY bit is 0.
3. At the conditions listed in Section 21.2.3.
A write access to the CPENA register can stop a control packet (CP) in single buffer mode or it can switch
to the other CP of a DCP in dual buffer mode. If stopping or switching occurs while a frame runs on the
currently active control packet, the CPU can poll the busy bit to determine when it is safe to read the
buffer.
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21.4.4 Control Packet (CP) Busy Register 1 (HTU BUSY1)
This register displays the status of individual control packets.
Figure 21-17. Control Packet (CP) Busy Register 1 (HTU BUSY1) [offset = 0Ch]
31
25
24
23
17
16
Reserved
BUSY2A
Reserved
BUSY2B
R-0
R/W1CP-0
R-0
R/W1CP-0
15
9
8
7
1
0
Reserved
BUSY3A
Reserved
BUSY3B
R-0
R/W1CP-0
R-0
R/W1CP-0
LEGEND: R/W = Read/Write; R = Read only; W1CP = Write 1 in privilege mode only to clear the bit; -n = value after reset
Table 21-16. Control Packet (CP) Busy Register 1 (HTU BUSY1) Field Descriptions
Bit
Field
Value
31-25
Reserved
24
BUSY2A
23-17
Reserved
16
BUSY2B
15-9
Reserved
8
BUSY3A
7-1
Reserved
0
BUSY3B
0
Description
Reads return 0. Writes have no effect.
Busy Flag for CP A of DCP 2
0
Reads return 0. Writes have no effect.
Busy Flag for CP B of DCP 2
0
Reads return 0. Writes have no effect.
Busy Flag for CP A of DCP 3
0
Reads return 0. Writes have no effect.
Busy Flag for CP B of DCP 3
See Section 21.4.3 for more details.
21.4.5 Control Packet (CP) Busy Register 2 (HTU BUSY2)
Figure 21-18. Control Packet (CP) Busy Register 2 (HTU BUSY2) [offset = 10h]
31
25
24
23
17
16
Reserved
BUSY4A
Reserved
BUSY4B
R-0
R/W1CP-0
R-0
R/W1CP-0
15
9
8
7
1
0
Reserved
BUSY5A
Reserved
BUSY5B
R-0
R/W1CP-0
R-0
R/W1CP-0
LEGEND: R/W = Read/Write; R = Read only; W1CP = Write 1 in privilege mode only to clear the bit; -n = value after reset
Table 21-17. Control Packet (CP) Busy Register 2 (HTU BUSY2) Field Descriptions
Bit
Field
31-25
Reserved
24
BUSY4A
23-17
Reserved
16
BUSY4B
15-9
Reserved
8
BUSY5A
7-1
Reserved
0
BUSY5B
990
Value
0
Description
Reads return 0. Writes have no effect.
Busy Flag for CP A of DCP 4
0
Reads return 0. Writes have no effect.
Busy Flag for CP B of DCP 4
0
Reads return 0. Writes have no effect.
Busy Flag for CP A of DCP 5
0
Reads return 0. Writes have no effect.
Busy Flag for CP B of DCP 5
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21.4.6 Control Packet (CP) Busy Register 3 (HTU BUSY3)
Figure 21-19. Control Packet (CP) Busy Register 3 (HTU BUSY3) [offset = 14h]
31
25
24
23
17
16
Reserved
BUSY6A
Reserved
BUSY6B
R-0
R/W1CP-0
R-0
R/W1CP-0
15
9
8
7
1
0
Reserved
BUSY7A
Reserved
BUSY7B
R-0
R/W1CP-0
R-0
R/W1CP-0
LEGEND: R/W = Read/Write; R = Read only; W1CP = Write 1 in privilege mode only to clear the bit; -n = value after reset
Table 21-18. Control Packet (CP) Busy Register 3 (HTU BUSY3) Field Descriptions
Bit
Field
Value
31-25
Reserved
24
BUSY6A
23-17
Reserved
16
BUSY6B
15-9
Reserved
8
BUSY7A
7-1
Reserved
0
BUSY7B
Description
0
Reads return 0. Writes have no effect.
Busy Flag for CP A of DCP 6
0
Reads return 0. Writes have no effect.
Busy Flag for CP B of DCP 6
0
Reads return 0. Writes have no effect.
Busy Flag for CP A of DCP 7
0
Reads return 0. Writes have no effect.
Busy Flag for CP B of DCP 7
21.4.7 Active Control Packet and Error Register (HTU ACPE)
Figure 21-20. Active Control Packet and Error Register (HTU ACPE) [offset = 18h]
31
30
29
28
24
23
20
19
16
ERRF
Reserved
ERRETC
Reserved
ERRCPN
R/W1CP-0
R-0
R-0
R-0
R-0
15
14
13
TIPF
BUSBUSY
Rsvd
12
CETCOUNT
8
7
Reserved
4
3
NACP
0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; W1CP = Write 1 in privilege mode only to clear the bit; -n = value after reset
Table 21-19. Active Control Packet and Error Register (HTU ACPE) Field Descriptions
Bit
Field
31
ERRF
30-29
Value
Reserved
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Description
Error Flag
0
No error occurred.
1
This bit is set when one of the conditions listed at ERRETC is fulfilled and ERRETC and ERRCPN
are captured. Once ERRF is set, it is cleared when reading the upper 16-bit word of the ACPE
register or the complete 32-bit register. It is also cleared when writing a 1 to ERRF. ERRF can be
used to indicate if ERRETC and ERRCPN contain new unread data.
0
Reads return 0. Writes have no effect.
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Table 21-19. Active Control Packet and Error Register (HTU ACPE) Field Descriptions (continued)
Bit
28-24
Field
Value
ERRETC
Description
Error Element Transfer Count
If one of the following conditions happens the current element transfer counter of the control packet
(specified by ERRCPN) is captured to ERRETC. Please see Section 21.2.3.
• Request Lost Error of control packet specified by ERRCPN. This is independent of the CORL bit.
• Parity Error of control packet specified by ERRCPN. This requires the parity check to be enabled,
but is independent of the COPE bit.
• Bus Error of control packet specified by ERRCPN.
• Memory Protection Error of control packet specified by ERRCPN. This requires the memory
protection to be enabled.
• Writing a 1 to a BUSY bit, which belongs to the control packet specified by ERRCPN, if that bit is
1. There is no effect, if the BUSY bit is 0.
ERRETC is frozen from being updated until the upper 16-bit word of the ACPE register or the
complete 32-bit register is read by the CPU. After this read, the HTU will update ERRETC if one of
the above conditions is fulfilled again. During debugging, ERRETC stays frozen even when reading
the upper 16-bit word or the 32-bit register.
23-20
Reserved
19-16
ERRCPN
0
Reads return 0. Writes have no effect.
Error Control Packet Number
If one of the conditions listed at ERRETC happens the number of the control packet, which caused
the condition, is captured to ERRCPN.
Control Packet
ERRCPN Value
CP A of DCP x
2x
CP B of DCP x
2 x+1
With x = 0,1,...or 7
ERRCPN is frozen from being updated until the upper 16-bit word of the ACPE register or the
complete 32-bit register is read by the CPU. After this read, the HTU will update ERRCPN if one of
the above conditions is fulfilled again. During debugging, ERRCPN stays frozen even when reading
the upper 16-bit word or the 32-bit register. If one of the conditions is fulfilled, ERRETC and
ERRCPN are updated simultaneously.
15
14
13
12-8
TIPF
Transfer in Progress Flag
0
No transfers are in progress.
1
A transfer is currently active. This bit is the result of a logical OR function of all BUSYxx flags of the
4 BUSYx registers.
BUSBUSY
Reserved
Bus is Busy
0
Bus between N2HET and HTU is not busy.
1
When BUSBUSY is 1, the bus is busy with a transfer. It is different from TIPF above because
BUSBUSY will go low after VBUSHOLD is set to 1 and no transfers are pending between the HTU
and the main memory. TIPF will remain 1, if a transfer is still pending and VBUSPHOLD is 1.
0
Reads return 0. Writes have no effect.
CETCOUNT
Current Element Transfer Count
CETCOUNT shows the current element transfer counter for the frame that is currently processed. If
the HTU does not currently transfer any frame, CETCOUNT is 0.
CETCOUNT is updated after the write part of a transfer. There is a period of up to 7 cycles between
the time the CETCOUNT is 0 and the HTU is finished updating the current DCP (and the CPENA
registers, if the required conditions are fulfilled).
7-4
Reserved
3-0
NACP
0
Reads return 0. Writes have no effect.
Number of Active Control Packet
Indicates which CP currently processes a frame.
Active or Recent DCP
NACP Value
CP A of DCP x
2x
CP B of DCP x
2 x+1
With x = 0,1,...or 7
NACP is updated at the time the frame starts on the according CP, and it is updated with a new
value when a frame starts on a different CP. Note, that there can be a delay between the request
and the start of the frame.
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21.4.8 Request Lost and Bus Error Control Register (HTU RLBECTRL)
Figure 21-21. Request Lost and Bus Error Control Register (HTU RLBECTRL) [offset = 20h]
31
17
15
9
16
Reserved
BERINTENA
R-0
R/WP-0
8
7
1
0
Reserved
CORL
Reserved
RLINTENA
R-0
R/WP-0
R-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 21-20. Request Lost and Bus Error Control Register (HTU RLBECTRL) Field Descriptions
Bit
31-17
16
15-9
8
7-1
0
Field
Reserved
Value
0
BERINTENA
Reserved
Reads return 0. Writes have no effect.
Bus Error Interrupt Enable Bit
0
The bus error interrupt is disabled for all DCPs.
1
The bus error interrupt is enabled for all DCPs.
0
Reads return 0. Writes have no effect.
CORL
Reserved
Description
Continue On Request Lost Error
0
Stop current frame on request lost detection. Please see Section 21.2.3.
1
If CORL is 1 and DCP x is enabled, then DCP x will stay enabled after a request lost condition on DCP
x and element transfers will continue.
0
Reads return 0. Writes have no effect.
RLINTENA
Request Lost Interrupt Enable Bit
0
The request lost interrupt is disabled for all DCPs. Disabling RLINTENA will not clear the flags in the
RLOSTFL register.
1
The request lost interrupt is enabled for all DCPs. If bits are set in the RLOSTFL flag register at the time
RLINTENA is (re-) enabled, then the according interrupt(s) will occur (in the order of the priority of the
request lines).
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21.4.9 Buffer Full Interrupt Enable Set Register (HTU BFINTS)
This registers allows to enable the buffer full interrupts for the different control packets. Reading registers
BFINTS and BFINTC will return the same bits indicating the status which interrupt is enabled (1) or
disabled (0).
Figure 21-22. Buffer Full Interrupt Enable Set Register (HTU BFINTS) [offset = 24h]
31
16
Reserved
R-0
15
0
BFINTENA
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 21-21. Buffer Full Interrupt Enable Set Register (HTU BFINTS) Field Descriptions
Bit
Field
Value
31-16
Reserved
15-0
BFINTENA
0
Description
Reads return 0. Writes have no effect.
Bus Full Interrupt Enable Bits. If the interrupt for CP A of a DCP is enabled, then the interrupt is
generated once buffer A is full, that is, once the frame counter CFTCTA decrements to 0. The same
applies for CP B (and CFTCTB).
0
Interrupt is disabled. Writing a 0 has no effect.
1
Writing to bit (2*x) enables the interrupt for CP A of DCP x.
Writing to bit (2*x+1) enables the interrupt for CP B of DCP x.
21.4.10 Buffer Full Interrupt Enable Clear Register (HTU BFINTC)
This registers allows to disable the buffer full interrupts for the different control packets. Reading registers
BFINTS and BFINTC will return the same bits indicating the status which interrupt is enabled (1) or
disabled (0)
Figure 21-23. Buffer Full Interrupt Enable Clear Register (HTU BFINTC) [offset = 28h]
31
16
Reserved
R-0
15
0
BFINTDIS
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 21-22. Buffer Full Interrupt Enable Clear Register (HTU BFINTC) Field Descriptions
Bit
Field
31-16
Reserved
15-0
BFINTDIS
Value
0
Description
Reads return 0. Writes have no effect.
Buffer Full Interrupt Disable Bits
0
Interrupt is disabled. Writing a 0 has no effect.
1
Writing to bit (2*x) disables the interrupt for CP A of DCP x.
Writing to bit (2*x+1) disables the interrupt for CP B of DCP x.
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21.4.11 Interrupt Mapping Register (HTU INTMAP)
Figure 21-24. Interrupt Mapping Register (HTU INTMAP) [offset = 2Ch]
31
17
16
Reserved
MAPSEL
R-0
R/WP-0
15
0
CPINTMAP
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 21-23. Interrupt Mapping Register (HTU INTMAP) Field Descriptions
Bit
Field
31-17
Reserved
16
MAPSEL
15-0
Value
0
Description
Reads return 0. Writes have no effect.
Interrupt Mapping Select Bit
0
If MAPSEL is 0, then one bit of CPINTMAP selects one of two interrupt priorities 0 or 1 for the buffer
full interrupt for the according CP. The request lost and bus error interrupts of all CPs are set to
priority 0, independent of CPINTMAP.
1
If MAPSEL is 1, then one bit of CPINTMAP determines if the buffer full, request lost and bus error
interrupts of the according CP are assigned either to interrupt line 0 or to 1.
CPINTMAP
CP Interrupt Mapping Bits
0
Interrupt of CP A (bit 2-x) of DCP x is mapped to interrupt line 0.
Interrupt of CP B (bit 2*x+1) of DCP x is mapped to interrupt line 0.
1
Interrupt of CP A (bit 2-x) of DCP x is mapped to interrupt line 1.
Interrupt of CP B (bit 2*x+1) of DCP x is mapped to interrupt line 1.
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21.4.12 Interrupt Offset Register 0 (HTU INTOFF0)
The INTOFF0 register reflects the highest priority interrupt flag bit set in the BERINTFL, RLOSTFL, or
BFINTFL flag registers with the appropriate CPINTMAP bit set to 0. The priority order (from high to low) is:
BER, RLOST, buffer-full. Interrupts for request lines with lower number have higher priority.
Figure 21-25. Interrupt Offset Register 0 (HTU INTOFF0) [offset = 34h]
31
16
Reserved
R-0
15
10
9
8
7
4
3
0
Reserved
INTTYPE0
Reserved
CPOFF0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 21-24. Interrupt Offset Register 0 (HTU INTOFF0) Field Descriptions
Bit
Field
31-10
Reserved
9-8
INTTYPE0
7-4
Reserved
3-0
CPOFF0
Value
0
Description
Reads return 0. Writes have no effect.
Interrupt Type of Interrupt Line 0. Indicates whether a buffer-full, RLOST, or BER interrupt, assigned to
interrupt line 0, is currently pending.
0
No interrupt.
1h
Interrupt caused by full buffer on CP/DCP specified by CPOFF0.
2h
RLOST interrupt generated by CP/DCP specified by CPOFF0.
3h
BER interrupt generated by CP/DCP specified by bits CPOFF0.
0
Reads return 0. Writes have no effect.
CP Offset. Indicates for which control packet the interrupt is pending, which is classified by INTTYPE0
and is assigned to interrupt line 0.
0
DCP 0, CP A
1h
DCP 0, CP B
2h
DCP 1, CP A
3h
DCP 1, CP B
4h
DCP 2, CP A
5h
DCP 2, CP B
6h
DCP 3, CP A
7h
DCP 3, CP B
8h
DCP 4, CP A
9h
DCP 4, CP B
Ah
DCP 5, CP A
Bh
DCP 5, CP B
Ch
DCP 6, CP A
Dh
DCP 6, CP B
Eh
DCP 7, CP A
Fh
DCP 7, CP B
NOTE: Reading CPOFF0 will clear the bit generating the current interrupt from appropriate flag
register (BERINTFL, RLOSTFL, or BFINTFL), except when in debug mode where reading
CPOFF0 will have no effect on the flag registers.
In order to read INTTYPE0 and CPOFF0 simultaneously, always read this register using
word or half-word but not using byte accesses.
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21.4.13 Interrupt Offset Register 1 (HTU INTOFF1)
This register is organized identically to the INTOFF0 register. The difference is that INTOFF1 reflects the
highest priority interrupt flag bit set in the BERINTFL, RLOSTFL, or BFINTFL flag registers with the
appropriate CPINTMAP bit set to 1.
Figure 21-26. Interrupt Offset Register 1 (HTU INTOFF1) [offset = 38h]
31
16
Reserved
R-0
15
10
9
8
7
4
3
0
Reserved
INTTYPE1
Reserved
CPOFF1
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 21-25. Interrupt Offset Register 1 (HTU INTOFF1) Field Descriptions
Bit
Field
31-10
Reserved
9-8
INTTYPE1
7-4
Reserved
3-0
CPOFF1
Value
0
Description
Reads return 0. Writes have no effect.
Interrupt Type of Interrupt Line 1. Indicates whether a buffer-full, RLOST, or BER interrupt, assigned to
interrupt line 1, is currently pending.
0
No interrupt.
1h
Interrupt caused by full buffer on CP/DCP specified by CPOFF1.
2h
RLOST interrupt generated by CP/DCP specified by CPOFF1.
3h
BER interrupt generated by CP/DCP specified by bits CPOFF1.
0
Reads return 0. Writes have no effect.
CP Offset. Indicates for which DCP / CP the interrupt is pending, which is classified by INTTYPE1 and
is assigned to interrupt line 1.
0
DCP 0, CP A
1h
DCP 0, CP B
2h
DCP 1, CP A
3h
DCP 1, CP B
4h
DCP 2, CP A
5h
DCP 2, CP B
6h
DCP 3, CP A
7h
DCP 3, CP B
8h
DCP 4, CP A
9h
DCP 4, CP B
Ah
DCP 5, CP A
Bh
DCP 5, CP B
Ch
DCP 6, CP A
Dh
DCP 6, CP B
Eh
DCP 7, CP A
Fh
DCP 7, CP B
NOTE: Reading CPOFF1 will clear the bit generating the current interrupt from appropriate flag
register (BERINTFL, RLOSTFL, or BFINTFL), except when in debug mode where reading
CPOFF1 will have no effect on the flag registers.
In order to read INTTYPE1 and CPOFF1 simultaneously, always read this register using
word or half-word but not using byte accesses.
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21.4.14 Buffer Initialization Mode Register (HTU BIM)
This register enables special applications, where one CP is temporarily disabled, but after having reenabled the CP, filling the buffer should not start back at its beginning, but should continue after the last
element of the previous run.
Table 21-27 shows more details on the BIM usage.
Figure 21-27. Buffer Initialization Mode Register (HTU BIM) [offset = 3Ch]
31
16
Reserved
R-0
15
8
7
0
Reserved
BIM
R-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 21-26. Buffer Initialization Mode Register (HTU BIM) Field Descriptions
Bit
Field
31-8
Reserved
7-0
BIM
Value
0
Description
Reads return 0. Writes have no effect.
Buffer Initialization Mode
The BIM bits and the TMBx bits determine when a buffer is initialized, that means when its initial full
address IFADDRx and its initial frame counter IFTCOUNT is used.
When initializing (restarting) a buffer the information in the corresponding initial DCP RAM is loaded to a
internal state machine but not to the current DCP RAM (CFADDRx, CFTCTx). The current DCP RAM is
updated the first time when the first frame has finished.
A buffer is initialized:
• In circular buffer transfer mode (defined by TMBx) when the end of the buffer is reached.
• When CPs are switched or enabled according to Buffer Initialization. The CPENA bits (2*x+1) and
(2*x) are changed by write access to CPENA. For the first two rows of the table, the change of the
CPENA bits could also be the result of the auto switch feature (as defined by TMBx).
BIM bit x only affects DCP x (with x = 0,1,...or 7).
Table 21-27. Buffer Initialization
Case
Change of CPENA bits
(2*x+1) and (2*x)
Old state
(1)
(2)
(3)
998
(1)
New state
Action on buffer A or B (of DCP x)
(2)
BIM bit x = 0
(normal mode)
BIM bit x = 1
(special mode)
A
01
10
Switch from CP A to B
Next frame starts at the
initial address of buffer B (3)
Same as for BIM bit x = 0
B
10
01
Switch from CP B to A
Next frame starts at the
initial address of buffer A (3)
Same as for BIM bit x = 0
C
01
01
Stay at CP A
Write to CPENA bits
(2*x+1) and (2*x) is ignored
Same as for BIM bit x = 0
E
10
10
Stay at CP B
Write to CPENA bits
(2*x+1) and (2*x) is ignored
Same as for BIM bit x = 0
E
00
01
Enable CP A
Next frame starts at the
initial address of buffer A
Next frame continues at the
current address of buffer A
F
00
10
Enable CP B
Next frame starts at the
initial address of buffer B
Next frame continues at the
current address of buffer B
G
xx
11
Disable both CPs
Stop DCP x
Same as for BIM bit x = 0
See read table of CPENA register (Table 21-14).
See write table of CPENA register (Table 21-13).
This is regardless of whether the switch is done by a write access to CPENA or by the auto-switch feature.
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NOTE: For cases E and F above, after the last frame of a buffer, the HTU sets CFTCTx to 0 and
CFADDRx to the next address after the buffer. If the DCP was disabled during this state,
then both CFTCTx and CFADDRx would contain invalid initialization values. Therefore, if a
DCP should continue at its current address, then the software should use one of the
following two procedures before it (re-) enables the DCP (as per Table 21-27):
1. If CFTCTx ≠ 0 then set BIM=1
2.
If CFTCTx = 0 then set
BIM=0
If CFTCTx ≠ 0 then set
BIM=1
If CFTCTx = 0 then {set
BIM=1;
set CFTCTx = IFTCOUNT;
set CFADDRx = IFADDRx}
But note that these procedures are only required for the cases E and F and not for all the
other cases shown in Table 21-27. Also, when a buffer reaches its end in circular mode, it
uses the initial DCP information to restart independently of the BIM setting (assuming it is not
temporarily disabled during CFTCTx = 0).
NOTE: Similarly, care needs to be taken when BIM is set to 1 and a DCP is enabled for the very first
time. Also, in this case, CFTCTx and CFADDRx usually contain invalid initialization values.
The software can either solve this by setting BIM = 0 for the first time or setting CFADDRx to
IFADDRx and CFTCTx to IFTCOUNT before the DCP is enabled.
NOTE: If
•
•
the HTUEN bit is changed to 1 after the HTU was disabled HTUEN = 0
the CPENA bit pair is 01 or 10 (during this HTUEN change)
then the corresponding BIM bit will decide if the corresponding buffer continues at its initial or
current address. Cases E and F in Table 21-27 also apply for this situation. The software
should use the procedures explained in the first note before setting HTUEN.
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21.4.15 Request Lost Flag Register (HTU RLOSTFL)
Figure 21-28. Request Lost Flag Register (HTU RLOSTFL) [offset = 40h]
31
16
Reserved
R-0
15
0
CPRLFL
R/W1CP-0
LEGEND: R/W = Read/Write; R = Read only; W1CP = Write 1 in privilege mode to clear the bit; -n = value after reset
Table 21-28. Request Lost Flag Register (HTU RLOSTFL) Field Descriptions
Bit
Field
31-16
Reserved
15-0
CPRLFL
Value
0
Description
Reads return 0. Writes have no effect.
CP Request Lost Flags
0
No request was lost. Writing a 0 has no effect.
1
If bit (2*x) is set, a request was lost on CP A of DCP x.
If bit (2*x+1) is set, a request was lost on CP B of DCP x. Reading from INTOFFx in case of a RLOST
interrupt clears the corresponding flag. The state of the flag bit can be polled even if RLINTENA is
cleared.
• Reading CPRLFL will not clear the flags or
• Reading from INTOFFx clears the corresponding flag.
• Writing a 1 clears the corresponding flag.
21.4.16 Buffer Full Interrupt Flag Register (HTU BFINTFL)
Figure 21-29. Buffer Full Interrupt Flag Register (HTU BFINTFL) [offset = 44h]
31
16
Reserved
R-0
15
0
BFINTFL
R/W1CP-0
LEGEND: R/W = Read/Write; R = Read only; W1CP = Write 1 in privilege mode to clear the bit; -n = value after reset
Table 21-29. Buffer Full Interrupt Flag Register (HTU BFINTFL) Field Descriptions
Bit
Field
31-16
Reserved
15-0
BFINTFL
Value
0
Description
Reads return 0. Writes have no effect.
Buffer Full Interrupt Flags
0
No buffer full condition is detected. Writing a 0 has no effect.
1
If bit (2*x) is set, a buffer full condition on CP A of DCP x has been detected.
If bit (2*x+1) is set, a buffer full condition on CP B of DCP x has been detected.
The BFINTFL flag is set after the last frame finishes on the corresponding buffer regardless of whether
the buffer is configured to one shot, circular or auto-switch mode. If BFINTFL is set in circular mode,
then a circular overrun has occurred on the corresponding buffer. This can be used to indicate whether
the buffer section after the frozen full address contains valid data or not.
Reading from INTOFFx in case of a buffer-full interrupt clears the corresponding flag. The state of the
flag bit can be polled even if the corresponding interrupt enable bit is cleared.
• Reading BFINTFL will not clear the flags or
• Reading INTOFFx will clear the corresponding flags or
• Writing a 1 clears the corresponding flag.
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21.4.17 BER Interrupt Flag Register (HTU BERINTFL)
A bus error interrupt results due to an address error or a timeout condition on the main memory access. A
bus error will stop the frame transfer. Please see Section 21.2.3.
Figure 21-30. BER Interrupt Flag Register (HTU BERINTFL) [offset = 48h]
31
16
Reserved
R-0
15
0
BERINTFL
R/W1CP-0
LEGEND: R/W = Read/Write; R = Read only; W1CP = Write 1 in privilege mode to clear the bit; -n = value after reset
Table 21-30. BER Interrupt Flag Register (HTU BERINTFL) Field Descriptions
Bit
Field
31-16
Reserved
15-0
BERINTFL
Value
0
Description
Reads return 0. Writes have no effect.
Bus Error Interrupt Flags
0
No bus error condition is detected. Writing a 0 has no effect.
1
If bit (2*x) is set, then a BER interrupt is pending on CP A of DCP x.
If bit (2*x+1) is set, then a BER interrupt is pending on CP B of DCP x.
The state of the flag bit can be polled even if BERINTENA is cleared.
• Reading BERINTFL will not clear the flags or
• Reading from INTOFFx in case of a BER interrupt clears the corresponding flag or
• Writing a 1 clears the corresponding flag.
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21.4.18 Memory Protection 1 Start Address Register (HTU MP1S)
This register configures the start address of memory protection region 1.
Figure 21-31. Memory Protection 1 Start Address Register (HTU MP1S) [offset = 4Ch]
31
16
STARTADDRESS1
R/WP-0
15
2
STARTADDRESS1
1
0
0
0
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset
Table 21-31. Memory Protection 1 Start Address Register (HTU MP1S) Field Descriptions
Bit
31-0
Field
Description
STARTADDRESS1
The start address defines at which main memory address the region begins. A memory protection error
will be triggered, if the HTU accesses an address smaller than STARTADDRESS1 and the MPCS bit
REG01ENA register is configured accordingly. The address is 32-bit aligned, so the 2 LSBs are not
significant and will always read 0.
21.4.19 Memory Protection 1 End Address Register (HTU MP1E)
Figure 21-32. Memory Protection 1 End Address Register (HTU MP1E) [offset = 50h]
31
16
ENDADDRESS1
R/WP-0
15
2
ENDADDRESS1
1
0
0
0
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset
Table 21-32. Memory Protection 1 End Address Register (HTU MP1E) Field Descriptions
Bit
31-0
1002
Field
Description
ENDADDRESS1
The end address defines at which address the region ends. A memory protection error will be
triggered, if the HTU accesses an address bigger than ENDADDRESS1 and the register bit
REG01ENA is configured accordingly. The address is 32-bit aligned, so the 2 LSBs are not significant
and will always read 0. The effective end address is rounded up to the nearest word end address, that
is, 0x200 = 0x203.
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21.4.20 Debug Control Register (HTU DCTRL)
This register allows to create watch points on access to a certain location. It is intended to help debug the
application execution during program development.
Figure 21-33. Debug Control Register (HTU DCTRL) [offset = 54h]
31
28
27
24
23
17
16
Reserved
CPNUM
Reserved
HTUDBGS
R-0
R-0
R-0
R/W1CS-0
15
1
0
Reserved
DBREN
R-0
R/WS-0
LEGEND: R/W = Read/Write; R = Read only; W1CS = Write 1 in suspend mode to clear the bit; WS = Write in suspend mode only; -n =
value after reset
Table 21-33. Debug Control Register (HTU DCTRL) Field Descriptions
Bit
Field
31-28
Reserved
27-24
CPNUM
23-17
16
Reserved
Value
0
Description
Reads return 0. Writes have no effect.
CP Number. These bit fields indicate the CP that should cause the watch point to match.
0
CP A of DCP0
1h
CP B of DCP0
2h
CP A of DCP1
3h
CP B of DCP1
4h
CP A of DCP2
5h
CP B of DCP2
6h
CP A of DCP3
7h
CP B of DCP3
8h
CP A of DCP4
9h
CP B of DCP4
Ah
CP A of DCP5
Bh
CP B of DCP5
Ch
CP A of DCP6
Dh
CP B of DCP6
Eh
CP A of DCP7
Fh
CP B of DCP7
0
HTUDBGS
Reads return 0. Writes have no effect.
HTU Debug Status. When the main memory address is equal to the unique address defined by WPR, or
lies in the specified range resulting from WMR, then the HTUDBGS is set. If in addition DBREN is set,
then the application code execution will be stopped.
A 1 must be written to this bit in order to clear it and to release the CPU from debug halting state.
0
Read: No watch point condition was detected.
Write: No effect.
1
Read: A watch point condition was detected.
Write: Clears the bit.
15-1
0
Reserved
0
DBREN
Reads return 0. Writes have no effect.
Debug Request Enable
If a watch point matches and DBREN is set, then the application code execution will be stopped. This
bit can only be set or cleared when in debug mode. This bit and all other bits of the DCTRL, WPR and
WMR registers are reset by the test reset (nTRST) but not by the normal device reset.
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21.4.21 Watch Point Register (HTU WPR)
This register defines the main memory address of the watch point.
Figure 21-34. Watch Point Register (HTU WPR) [offset = 58h]
31
16
WP
R/WS-0
15
0
WP
R/WS-0
LEGEND: R/W = Read/Write; WS = Write in suspend mode only; -n = value after reset
Table 21-34. Watch Point Register (HTU WPR) Field Descriptions
Bit
31-0
Field
Description
WP
Watch Point Register
A 32-bit address can be programmed into this register as a watch point. The WPR register is used along with
the Watch Mask Register ( WMR). When the main memory address is equal to the unique address defined by
WPR, or lies in the specified range resulting from WMR, then the HTUDBGS is set. If in addition DBREN is set,
then the application code execution is stopped.
This register can only be programmed during debug mode. This register and all other bits of the DCTRL and
WMR registers are reset by the test reset (nTRST) but not by the normal device reset.
21.4.22 Watch Mask Register (HTU WMR)
This register defines a mask of the main memory address of the watch point. It can be used to define a
memory range in conjunction with the WPR register.
Figure 21-35. Watch Mask Register (HTU WMR) [offset = 5Ch]
31
16
WM
R/WS-0
15
0
WM
R/WS-0
LEGEND: R/W = Read/Write; WS = Write in suspend mode only; -n = value after reset
Table 21-35. Watch Mask Register (HTU WMR) Field Descriptions
Bit
Field
Description
31-0
WM
Watch Mask Register
Setting a bit in the WMR register to 1 has the effect of masking the corresponding bit in of the main memory
address, so that this bit is ignored for the address comparison.
This register can only be programmed during debug mode. This register and all other bits of the DCTRL and
WPR registers are reset by the test reset (nTRST) but not by the normal device reset.
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21.4.23 Module Identification Register (HTU ID)
This register is for TI internal purposes and allows to keep track of the HTU module version on different
devices.
Figure 21-36. Module Identification Register (HTU ID) [offset = 60h]
31
24
23
16
Reserved
CLASS
R-0
R - Module Class Number
15
8
7
0
TYPE
REV
R - Class Subtype Number
R - Module Revision Number
LEGEND: R = Read only; -n = value after reset
Table 21-36. Module Identification Register (HTU ID) Field Descriptions
Bit
Field
31-24
Reserved
23-16
CLASS
Value
0
Description
Reads return 0. Writes have no effect.
Module Class
This field defines the module class number as read-only constant value for the HTU module. Writes
have no effect.
15-8
TYPE
Subtype within a Class
This field defines the subtype within a class as read-only constant value for the HTU module. Writes
have no effect.
7-0
REV
Module Revision Number
This field defines the module revision number as read-only constant value for the HTU module. Writes
have no effect.
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21.4.24 Parity Control Register (HTU PCR)
Figure 21-37. Parity Control Register (HTU PCR) [offset = 64h]
31
17
15
9
16
Reserved
COPE
R-0
R/WP-0
8
7
4
3
0
Reserved
TEST
Reserved
PARITY_ENA
R-0
R/WP-0
R-0
R/WP-5h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 21-37. Parity Control Register (HTU PCR) Field Descriptions
Bit
31-17
16
Field
Reserved
Value
0
COPE
Description
Reads return 0. Writes have no effect.
Continue on Parity Error
0
The HTU performs parity checks every time it reads the RAM section of DCP x (with x = 0, 1,... or
7), before the next frame (of DCP x) is started. If a parity error is detected during this read access
and if the parity check is enabled, then the frame will not be started and DCP x will be automatically
disabled in the CPENA register.
If a master different than the HTU (for example, CPU) reads the RAM section of DCP x and a parity
error is detected during this read access, while the parity check is enabled, then the DCP x will
automatically be disabled in the CPENA register. If a frame is active on DCP x during this read
access, then in addition the element counter of DCP x is cleared and all new element transfers on
DCP x are stopped and the active busy bit of DCP x is cleared.
15-9
8
Reserved
1
The difference to COPE = 0 is, that the data transfer on a active DCP continues after a parity error
was detected on this DCP. So, neither the DCP with the parity error will be disabled nor the frame
will be stopped.
0
Reads return 0. Writes have no effect.
TEST
7-4
Reserved
3-0
PARITY_ENA
Test. When this bit is set, the parity bits are mapped into the peripheral RAM frame to make them
accessible by the CPU.
0
Parity bits are not memory-mapped.
1
Parity bits are memory-mapped.
0
Reads return 0. Writes have no effect.
Enable/Disable Parity Checking. This bit field enables or disables the parity check on read
operations and the parity calculation on write operations. If parity checking is enabled and a parity
error is detected, then the PEFT flag is set, PAOFF is captured if it is not currently frozen and an
interrupt is generated if it is enabled.
5h
Parity check is disabled.
All
Others
Parity check is enabled.
Note: It is recommended to write Ah to enable error detection, to guard against single bit changes
from flipping PARITY_ENA to a disable state.
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21.4.25 Parity Address Register (HTU PAR)
Figure 21-38. Parity Address Register (HTU PAR) [offset = 68h]
31
17
15
16
Reserved
PEFT
R-0
R/W1CP-0
9
8
0
Reserved
PAOFF
R-0
R-X
LEGEND: R/W = Read/Write; R = Read only; W1CP = Write 1 in privilege mode to clear the bit; -n = value after reset; X = undefined
Table 21-38. Parity Address Register (HTU PAR) Field Descriptions
Bit
31-10
16
Field
Reserved
Value
0
PEFT
Description
Reads return 0. Writes have no effect.
Parity Error Fault Flag. This bit is set, when the HTU detects a parity error and parity checking is
enabled.
0
No fault is detected.
1
Fault is detected.
Note: Once PEFT is set, a read access to the lower 16 bits or to the complete 32-bit HTUPAR register
will clear the PEFT flag in non-debug mode. Another possibility to clear PEFT is to write a 1 to the
PEFT bit.
15-9
Reserved
8-0
PAOFF
0
Reads return 0. Writes have no effect.
Parity Error Address Offset. This bit field holds the address of the first parity error, which is detected in
the DCP RAM. PAOFF provides the offset address of the erroneous byte counted from the beginning of
the DCP memory. This error address is frozen from being updated until a read access to the lower 16
bits or to the complete 32-bit HTUPAR register happens. During debug mode, this address is frozen
even when read.
Note: The Parity Error Address bits will not be reset, neither by PORRST nor by any other reset source.
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21.4.26 Memory Protection Control and Status Register (HTU MPCS)
Figure 21-39. Memory Protection Control and Status Register (HTU MPCS) [offset = 70h]
31
28
27
24
Reserved
CPNUM0
R-0
R-0
23
18
MPEFT1
MPEFT0
R-0
R/W1CP-0
R/W1CP-0
12
11
8
Reserved
CPNUM1
R-0
R-0
6
16
Reserved
15
7
17
5
4
3
2
1
0
Reserved
INT ENA01
ACCR01
REG01ENA
INT ENA0
ACCR0
REG0ENA
R-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; W1CP = Write 1 in privilege mode to clear the bit; -n =
value after reset
Table 21-39. Memory Protection Control and Status Register (HTU MPCS) Field Descriptions
Bit
Field
31-28
Reserved
27-24
CPNUM0
23-18
Reserved
17
MPEFT1
16
1008
Value
0
Description
Reads return 0. Writes have no effect.
Control Packet Number for single memory protection region configuration. CPNUM0 holds the number
of the CP, which has caused the first memory protection error when only one memory protection region
is used. This number is not updated for multiple access violations until it is read by the CPU. During
debug mode, CPNUM0 is frozen even when read.
0
CP A of DCP0
1h
CP B of DCP0
2h
CP A of DCP1
3h
CP B of DCP1
4h
CP A of DCP2
5h
CP B of DCP2
6h
CP A of DCP3
7h
CP B of DCP3
8h
CP A of DCP4
9h
CP B of DCP4
Ah
CP A of DCP5
Bh
CP B of DCP5
Ch
CP A of DCP6
Dh
CP B of DCP6
Eh
CP A of DCP7
Fh
CP B of DCP7
0
Reads return 0. Writes have no effect.
Memory Protection Error Fault Flag 1. This bit is set, when the HTU performs an access outside the
region defined by the MP0S and MP0E and the MP1S and MP1E registers, when the access violates
the rights defined by ACCR01, and when the REG01ENA bit is set.
0
No fault detected. Writing a 0 has no effect.
1
Fault detected. Writing a 1 will clear the bit.
MPEFT0
Memory Protection Error Fault Flag 0. This bit is set, when the HTU performs an access outside the
region defined by the MP0S and MP0E registers, when the access violates the rights defined by ACCR,
and when the REG0ENA bit is set.
0
No fault detected. Writing a 0 has no effect.
1
Fault detected. Writing a 1 will clear the bit.
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Table 21-39. Memory Protection Control and Status Register (HTU MPCS) Field Descriptions (continued)
Bit
Field
15-12
Reserved
11-8
CPNUM1
7-6
Reserved
5
INTENA01
4
3
2
1
Value
0
Description
Reads return 0. Writes have no effect.
Control Packet Number for single memory protection region configuration. CPNUM1 holds the number
of the CP, which has caused the first memory protection error when only one memory protection region
is used. This number is not updated for multiple access violations until it is read by the CPU. During
debug mode, CPNUM1 is frozen even when read.
0
CP A of DCP0
1h
CP B of DCP0
2h
CP A of DCP1
3h
CP B of DCP1
4h
CP A of DCP2
5h
CP B of DCP2
6h
CP A of DCP3
7h
CP B of DCP3
8h
CP A of DCP4
9h
CP B of DCP4
Ah
CP A of DCP5
Bh
CP B of DCP5
Ch
CP A of DCP6
Dh
CP B of DCP6
Eh
CP A of DCP7
Fh
CP B of DCP7
0
Reads return 0. Writes have no effect.
Interrupt Enable 01. This bit needs to be set when working with two memory-mapped regions and a
error should be generated to the ESM module on an access violation.
0
Error signaling is disabled.
1
Error signaling is enabled.
ACCR01
Access Rights 01. This bit defines the access rights for the HTU for accesses outside the region defined
by the MP0S and MP0E and the MP1S and MP1E registers.
0
HTU read access is allowed but write access will be signaled.
1
Any access performed by the HTU is forbidden and will be signaled.
REG01ENA
Region Enable 01. This bit needs to be set when working with two memory-mapped regions. REG0ENA
must be cleared to 0 if this bit is set to a 1. Memory region 0 must be less than memory region 1.
0
The protection outside the memory region defined by the MP0S and MP0E and the MP1S and MP1E
registers is not enabled. This means the HTU can access any implemented memory space. REG0ENA
could still enabled to give protection outside the MP0S:MP0E region.
1
The protection outside the memory region defined by the MP0S and MP0E and the MP1S and MP1E
registers is enabled. This means the HTU can perform any access within the regions, but if it attempts
to perform a forbidden access outside of both of the regions (according to the ACCR01 configuration),
the access is signaled by the MPEFT1 flag. The number of the CP, which has caused the memory
protection error, is captured to CPNUM1 if it is not currently frozen and an error is generated if it is
enabled.
INTENA0
Interrupt Enable 0. This bit needs to be set when working with one memory-mapped region and a error
should be generated to the ESM module on an access violation.
0
Error signaling is disabled.
1
Error signaling is enabled.
ACCR
Access Rights 0. This bit defines the access rights for the HTU for accesses outside the region defined
by the MP0S and MP0E registers for a single memory protection region configuration.
0
HTU read access is allowed but write access will be signaled.
1
Any access performed by the HTU is forbidden and will be signaled.
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Table 21-39. Memory Protection Control and Status Register (HTU MPCS) Field Descriptions (continued)
Bit
0
1010
Field
Value
REG0ENA
Description
Region Enable 0
0
The protection outside the memory region defined by the MP0S and MP0E registers is not enabled.
This means the HTU can access any implemented memory space.
1
The protection outside the memory region defined by the MP0S and MP0E registers is enabled. This
means the HTU can perform any access within the region, but if it attempts to perform a forbidden
access outside the region (according to the ACCR configuration), the access is signaled by the
MPEFT0 flag, the number of the CP, which has caused the memory protection error, is captured to
CPNUM0 if it is not currently frozen and an error is generated if it is enabled.
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21.4.27 Memory Protection Start Address Register 0 (HTU MP0S)
This register configures the start address of memory protection region 0
Figure 21-40. Memory Protection Start Address Register 0 (HTU MP0S) [offset = 74h]
31
16
STARTADDRESS0
R/WP-0
15
2
STARTADDRESS0
1
0
0
0
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset
Table 21-40. Memory Protection 0 Start Address Register (HTU MP0S) Field Descriptions
Bit
31-0
Field
Description
STARTADDRESS0
The start address defines at which main memory address the region begins. A memory protection error
will be triggered, if the HTU accesses an address smaller than STARTADDRESS0 and the MPCS
register is configured accordingly. The address is 32-bit aligned, so the 2 LSBs are not significant and
will always read 0.
21.4.28 Memory Protection End Address Register (HTU MP0E)
Figure 21-41. Memory Protection End Address Register (HTU MP0E) [offset = 78h]
31
16
ENDADDRESS0
R/WP-0
15
2
ENDADDRESS0
1
0
0
0
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset
Table 21-41. Memory Protection End Address Register (HTU MP0E) Field Descriptions
Bit
31-0
Field
Description
ENDADDRESS0
The end address defines at which address the region ends. A memory protection error will be
triggered, if the HTU accesses an address bigger than ENDADDRESS0 and the register bit MPCS
register is configured accordingly. The address is 32-bit aligned, so the 2 LSBs are not significant and
will always read 0. The effective end address is rounded up to the nearest word end address, that is,
0x200 = 0x203.
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21.5 Double Control Packet Configuration Memory
All bits marked "reserved' are implemented in RAM and will be initialized to unknown values after power
on. Reserved locations can be written and read but should be written with 0 to ensure future compatibility.
The HTU RAM can be cleared with the system RAM initialization function.
Table 21-42 provides a summary of the memory configuration. There are eight sets of DCP registers and
eight sets of CF registers. The base address for the DCP registers is FF4E 0000h for HTU1 and
FF4C 0000h for HTU2.
Table 21-42. Double Control Packet Memory Map
Offset
Acronym
Register Description
00h
HTU DCP0 IFADDRA
Initial Full Address A Register
Section 21.5.1
04h
HTU DCP0 IFADDRB
Initial Full Address B Register
Section 21.5.2
08h
HTU DCP0 IHADDRCT
Initial N2HET Address and Control Register
Section 21.5.3
0Ch
HTU DCP0 ITCOUNT
Initial Transfer Count Register
Section 21.5.4
10h
HTU DCP1 IFADDRA
Initial Full Address A Register
Section 21.5.1
14h
HTU DCP1 IFADDRB
Initial Full Address B Register
Section 21.5.2
18h
HTU DCP1 IHADDRCT
Initial N2HET Address and Control Register
Section 21.5.3
1Ch
HTU DCP1 ITCOUNT
Initial Transfer Count Register
Section 21.5.4
:
:
70h
HTU DCP7 IFADDRA
Initial Full Address A Register
Section 21.5.1
74h
HTU DCP7 IFADDRB
Initial Full Address B Register
Section 21.5.2
78h
HTU DCP7 IHADDRCT
Initial N2HET Address and Control Register
Section 21.5.3
7Ch
HTU DCP7 ITCOUNT
Initial Transfer Count Register
Section 21.5.4
100h
HTU CDCP0 CFADDRA
Current Full Address A Register
Section 21.5.5
104h
HTU CDCP0 CFADDRB
Current Full Address B Register
Section 21.5.6
108h
HTU CDCP0 CFCOUNT
Current Frame Count Register
Section 21.5.7
110h
HTU CDCP1 CFADDRA
Current Full Address A Register
Section 21.5.5
114h
HTU CDCP1 CFADDRB
Current Full Address B Register
Section 21.5.6
118h
HTU CDCP1 CFCOUNT
Current Frame Count Register
Section 21.5.7
:
:
170h
HTU CDCP7 CFADDRA
Current Full Address A Register
Section 21.5.5
174h
HTU CDCP7 CFADDRB
Current Full Address B Register
Section 21.5.6
178h
HTU CDCP7 CFCOUNT
Current Frame Count Register
Section 21.5.7
:
:
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21.5.1 Initial Full Address A Register (HTU IFADDRA)
Figure 21-42. Initial Full Address A Register (HTU IFADDRA)
31
16
IFADDRA
R/WP-X
15
0
IFADDRA
R/WP-X
LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset; X = Unknown
Table 21-43. Initial Full Address A Register (HTU IFADDRA) Field Descriptions
Bit
31-0
Field
Description
IFADDRA
Initial Address of Buffer A in main memory.
Initial (byte) address of buffer A placed in the main memory address range. Bits 0 and 1 are ignored by the
logic, due to 32-bit alignment.
21.5.2 Initial Full Address B Register (HTU IFADDRB)
Figure 21-43. Initial Full Address B Register (HTU IFADDRB)
31
16
IFADDRB
R/WP-X
15
0
IFADDRB
R/WP-X
LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset; X = Unknown
Table 21-44. Initial Full Address B Register (HTU IFADDRB) Field Descriptions
Bit
31-0
Field
Description
IFADDRB
Initial Address of Buffer B in main memory.
Initial (byte) address of buffer B placed in the main memory address range. Bits 0 and 1 are ignored by the
logic, due to 32-bit alignment.
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21.5.3 Initial N2HET Address and Control Register (HTU IHADDRCT)
Figure 21-44. Initial N2HET Address and Control Register (HTU IHADDRCT)
31
24
Reserved
R-0
23
22
21
DIR
SIZE
ADDMH
ADDMF
TMBA
TMBB
R/WP-X
R/WP-X
R/WP-X
R/WP-X
R/WP-X
R/WP-X
15
13
20
19
18
17
12
16
2
1
0
Reserved
IHADDR
Reserved
R-0
R/WP-X
R-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset; X = Unknown
Table 21-45. Initial N2HET Address and Control Register (HTU IHADDRCT) Field Descriptions
Bit
31-24
23
22
Field
Reserved
Value
0
DIR
Description
Reads return 0. Writes have no effect.
Direction of Transfer
0
N2HET address is read and main memory address is written.
1
Main memory address is read and N2HET address is written.
SIZE
Size of Transferred Data
0
32-bit transfer
1
64-bit transfer
64-bit transfer examples: If the N2HET address points to the N2HET instruction Control Field (CF), then
the CF and Data Field (DF) will be transferred. If the N2HET address points to the Program Field (PF),
then the PF and CF will be transferred.
21
ADDMH
Addressing Mode N2HET Address. This bit determines the N2HET address index from one to the next
element of a frame.
0
Increment by 16 bytes.
Examples:
If the initial N2HET address points to data field of instruction (n). Then the N2HET fields to be
transferred by the elements of a frame are: data field of instruction (n), data field of instruction (n+1),
data field of instruction (n+2) and so on. If the initial N2HET address points to control field of instruction
(n), then the N2HET fields to be transferred by the elements of a frame are: control field of instruction
(n), control field of instruction (n+1), control field of instruction (n+2) and so on.
1
Increment by 8 bytes.
This mode is intended to be used together with the 64-bit transfer size to load short N2HET instruction
blocks into the N2HET RAM. So the sequence of transferred 64-bit elements could be: [PF and CF of
instruction (n)], [DF and RF of instruction (n)], [PF and CF of instruction (n+1)], [DF and RF of
instruction (n+1)] and so on.
20
ADDMF
Addressing Mode Main Memory Address
0
Post-increment
Note: When post-increment is selected the HTU will automatically increment by 4 bytes for a 32-bit data
size and by 8 bytes for a 64-bit data size.
1
19-18
TMBA
Transfer Mode for Buffer A
0
One-Shot buffer mode
1h
Circular buffer mode
2h-3h
17-16
TMBB
Auto Switch mode
Transfer Mode for Buffer B
0
One-Shot buffer mode
1h
Circular buffer mode
2h-3h
1014
Constant
Auto Switch mode
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Table 21-45. Initial N2HET Address and Control Register (HTU IHADDRCT) Field Descriptions (continued)
Bit
Field
15-13
Reserved
12-2
IHADDR
Value
0
Description
Reads return 0. Writes have no effect.
Initial N2HET Address
The initial N2HET Address points to the N2HET field, which is the first element of the frame. The
N2HET address (bits 12:2) increments by 1 for each 32-bit N2HET field and starts with 0 at the first 32bit field in the N2HET RAM.
Note: When the HTU addresses the N2HET RAM it uses only the number of address bits required for
the actual N2HET RAM size. If the N2HET address exceeds the actual N2HET RAM size, the unused
MSB bits of the address will be ignored and the address rolls over to the start of the N2HET RAM.
1-0
Reserved
0
Reads return 0. Writes have no effect.
21.5.4 Initial Transfer Count Register (HTU ITCOUNT)
Figure 21-45. Initial Transfer Count Register (HTU ITCOUNT)
31
21
20
16
Reserved
IETCOUNT
R-0
R/WP-X
15
8
7
0
Reserved
IFTCOUNT
R-0
R/WP-X
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset; X = Unknown
Table 21-46. Initial Transfer Count Register (HTU ITCOUNT) Field Descriptions
Bit
Field
31-21
Reserved
20-16
IETCOUNT
15-8
Reserved
7-0
IFTCOUNT
Value
0
Description
Reads return 0. Writes have no effect.
Initial Element Transfer Count
Defines the number of element transfers.
0
Reads return 0. Writes have no effect.
Initial Frame Transfer Count
Defines the number of frame transfers.
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21.5.5 Current Full Address A Register (HTU CFADDRA)
Figure 21-46. Current Full Address A Register (HTU CFADDRA)
31
16
CFADDRA
R/WP-X
15
0
CFADDRA
R/WP-X
LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset; X = Unknown
Table 21-47. Current Full Address A Register (HTU CFADDRA) Field Descriptions
Bit
31-0
Field
Description
CFADDRA
Current (byte) Address of Buffer A
The current main memory address register is updated at the end of each frame. Therefore it points to the start
address of the frame, which is the next to transfer, if currently no frame is transferred on this DCP. For an
ongoing frame transfer, it points to the start address of this frame. After the last element of a buffer was
transferred it will point to the buffer end address plus 0x4.
The main purpose of the current full address registers for buffer A and buffer B (see next section) is to enable
the software to find out the recently transferred element in the frozen buffer while the address of the active
buffer increments.
Note: A frame can be automatically stopped if any of the events listed in Conditions for Frame Transfer
Interruption happens. If a frame is stopped before it could complete, then the current full address register is not
updated and it will point to the start of the bad frame after the DCP was automatically disabled.
To transfer the first frame of buffer x, the information in the corresponding initial DCP RAM (IFADDRx,
IHADDRCT, ITCOUNT) is loaded to an internal state machine but not to the current DCP RAM
(CFADDRx, CFTCTx).
This is valid for all of the following modes:
• Buffer x has reached it's end in circular mode and rolls back to its start address.
• CP x is enabled by a CPENA access (and corresponding BIM bit is 0).
• A CPENA access or auto-switch mode causes a switch from CP y to CP x.
This means after starting the transfer to/from buffer x, CFADDRx and CFTCTx is not updated before the
end of the first frame. So before the software switches from CP y to CP x using a write access to the
CPENA register, it needs to initialize CFADDRx, CFTCTx. This allows the software to find out if the next
request on CP x after the switching to CP x was delayed or never occurring.
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21.5.6 Current Full Address B Register (HTU CFADDRB)
Figure 21-47. Current Full Address B Register (HTU CFADDRB)
31
16
CFADDRB
R/WP-X
15
0
CFADDRB
R/WP-X
LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset; X = Unknown
Table 21-48. Current Full Address B Register (HTU CFADDRB) Field Descriptions
Bit
31-0
Field
Description
CFADDRB
Current (byte) Address of Buffer B
The current main memory address register is updated at the end of each frame. Therefore it points to the start
address of the frame, which is the next to transfer, if currently no frame is transferred on this DCP. If currently a
frame is transferred, then it points to the start address of this frame. After the last element of a buffer was
transferred it will point to the buffer end address plus 0x4.
The main purpose of the current full address registers for buffer A and buffer B (see next section) is to enable
the software to find out the recently transferred element in the frozen buffer while the address of the active
buffer increments.
Note: A frame can be automatically stopped if any of the events listed in Conditions for Frame Transfer
Interruption happens. If a frame is stopped before it could complete, then the current full address register is not
updated and it will point to the start of the bad frame after the DCP was automatically disabled.
To transfer the first frame of buffer x, the information in the corresponding initial DCP RAM (IFADDRx,
IHADDRCT, ITCOUNT) is loaded to an internal state machine but not to the current DCP RAM
(CFADDRx, CFTCTx).
This is valid for all of the following modes:
• Buffer x has reached it's end in circular mode and rolls back to its start address.
• CP x is enabled by a CPENA access (and corresponding BIM bit is 0).
• A CPENA access or auto-switch mode causes a switch from CP y to CP x.
This means after starting the transfer to/from buffer x, CFADDRx and CFTCTx is not updated before the
end of the first frame. So before the software switches from CP y to CP x using a write access to the
CPENA register, it needs to initialize CFADDRx, CFTCTx. This allows the software to find out if the next
request on CP x after the switching to CP x was delayed or never occurring.
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21.5.7 Current Frame Count Register (HTU CFCOUNT)
The current frame count register enables the software to find out the recent frame in the buffer while the
counter of the active buffer decrements.
Figure 21-48. Current Frame Count Register (HTU CFCOUNT)
31
24
23
16
Reserved
CFTCTA
R-0
R/WP-X
15
8
7
0
Reserved
CFTCTB
R-0
R/WP-X
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset; X = Unknown
Table 21-49. Current Frame Count Register (HTU CFCOUNT) Field Descriptions
Bit
Field
31-24
Reserved
23-16
CFTCTA
15-8
Reserved
7-0
CFTCTB
1018
Value
0
Description
Reads return 0. Writes have no effect.
Current Frame Transfer Count for CP A. It is updated at the end of each frame.
0
Reads return 0. Writes have no effect.
Current Frame Transfer Count for CP B. It is updated at the end of each frame.
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21.6 Examples
21.6.1 Application Examples for Setting the Transfer Modes of CP A and B of a DCP
Table 21-50. Application Examples for Setting the Transfer Modes of CP A and B of a DCP
CP A
CP B
One shot
Not used
Buffer A can be used as a "one shot" buffer. A buffer full interrupt enabled for CP A
can signal reaching the end of the buffer.
Auto switch
One shot
Can double the buffer size for a "one shot" buffer. A buffer full interrupt enabled for CP
B can signal reaching the end of the buffer.
Circular
Circular
The CPU can switch the buffers at arbitrary times. It will fill or read the frozen buffer
during the other buffer is filled or read by the HTU. Interrupts are not required for this
case.
Auto switch
Auto switch
Buffer full interrupts (enabled for CP A and B) signal when the end of a buffer is
reached. After one buffer is completed the according CPU interrupt routine will read or
refill this buffer. At the same time the other buffer is read or filled by the HTU. Here the
time when the buffer must be read is determined by the time of the interrupt
(determined by the frequency of the N2HET transfer requests).
21.6.2 Software Example Sequence Assuming Circular Mode for Both CP A and B
The example assumes the N2HET address to be read and the main memory address to be written.
I1
I2
I3
I4
CPU initializes initial DCP: IFADDRA, IFADDRB, IHADDRCT, ITCOUNT
CPU clears current DCP: CFADDRA, CFADDRB, CFTCTA, CFTCTB
CPU clears BFINTFL flag of CP A and B
Enable CP A with the CPENA register. Now the HTU fills buffer A
After some time the CPU intends to read buffer A:
A1
A2
A3
A4
A5
A6
A7
A8
CPU enables CP B and disables CP A by writing to the CPENA register. After this
switch, the HTU fills buffer B. Filling buffer B starts with its initial full address and initial
frame counter.
CPU waits for CP A busy bit equals 0
Optional: CPU verifies that the CP A request lost flag is not set. The bus error flag of CP
A could also be checked.
CPU reads the frozen CFTCTA, which indicates the fill level in the buffer
CPU sets current CP A (CFTCTA and/or CFADDRA) to 0. This allows to find out if any
request has happened during the next time buffer A is active.
CPU reads BFINTFL flag of buffer A
CPU clears the BFINTFL flag of buffer A. This is an initialization for the next time buffer
A is used.
CPU reads valid values of frozen buffer A. After reading the CPU does not need to clear
the frozen buffer A.
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After some time the CPU intends to read buffer B:
B1
B2
B3
B4
B5
B6
B7
B8
CPU enables CP A and disables CP B by writing to the CPENA register. After this
switch, the HTU fills buffer A. Filling buffer A starts with its initial full address and initial
frame counter.
CPU waits for CP B busy bit equals 0
Optional: CPU verifies that the CP B request lost flag is not set. The bus error flag of CP
B could also be checked.
CPU reads the frozen CFTCTB, which indicates the fill level in the buffer
CPU sets current CP B (CFTCTB and/or CFADDRB) to 0. This allows to find out if any
request has happened during the next time buffer B is active.
CPU reads BFINTFL flag of buffer B
CPU clears the BFINTFL flag of buffer B. This is an initialization for the next time buffer
B is used.
CPU reads valid values of frozen buffer B. After reading the CPU does not need to clear
the frozen buffer B.
After some time the CPU intends to read buffer A:
A1) ... see above...
NOTE: The buffer full interrupt doesn't need to be enabled. The BFINTFL flag is used to indicate a
circular overrun of the buffer. If the BFINTFL flag is set, also the buffer section after the
frozen full address could be read.
Steps A3 and B3 in the example sequence above imply that request lost interrupts are disabled. The
example below assumes that request lost interrupts are enabled.
Request lost detection with interrupt enabled.
21.6.3 Example of an Interrupt Dispatch Flow for a Request Lost Interrupt
•
•
•
•
•
1020
A request lost occurs and the interrupt routine starts.
Reading INTOFFx.INTYPEx shows that RLOSTFL is the interrupt source.
Reading INTOFFx.CPOFFx = Ah shows that DCP 5 / CP A has caused the RLOSTFL interrupt. The
hardware automatically clears bit (2·5+0) in RLOSTFL.
Reading RLOSTFL= 84h shows that also another request lost event happened on DCP 1 / CP A [bit
(2·1+0)] and on DCP 3 / CP B [bit (2·3+1)] at the same time or after the request lost occurred on DCP
5 / CP A.
Writing back 84h to RLOSTFL clears bits 2 and 7 and the according pending interrupts.
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Chapter 22
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General-Purpose Input/Output (GIO) Module
This chapter describes the general-purpose input/output (GIO) module. The GIO module provides the
family of devices with input/output (I/O) capability. The I/O pins are bidirectional and bit-programmable.
The GIO module also supports external interrupt capability.
Topic
22.1
22.2
22.3
22.4
22.5
22.6
...........................................................................................................................
Overview........................................................................................................
Quick Start Guide ...........................................................................................
Functional Description of GIO Module ...............................................................
Device Modes of Operation ..............................................................................
GIO Control Registers .....................................................................................
I/O Control Summary .......................................................................................
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22.1 Overview
The GIO module offers general-purpose input and output capability. It supports up to eight 8-bit ports for a
total of up to 64 GIO terminals. Each of these 64 terminals can be independently configured as input or
output and configured as required by the application. The GIO module also supports generation of
interrupts whenever a rising edge or falling edge or any toggle is detected on up to 32 of these GIO
terminals. Refer to the device datasheet for identifying the number of GIO ports supported and the GIO
terminals capable of generating an interrupt.
The main features of the GIO module are summarized as follows:
• Allows each GIO terminal to be configured for general-purpose input or output functions
• Supports programmable pull directions on each input GIO terminal
• Supports GIO output in push/pull or open-drain modes
• Allows up to 32 GIO terminals to be used for generating interrupt requests
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22.2 Quick Start Guide
The GIO module comprises two separate components: an input/output (I/O) block and an interrupt
generation block. Figure 22-1 and Figure 22-2 show what you should do after reset to configure the GIO
module as I/O or for generating interrupts.
In GIO interrupt service routine, you shall read the GIO offset register (GIOOFF1 or GIOOFF2, depending
on high-/low-level interrupt) to clear the flag and find the pending interrupt GIO channel.
Figure 22-1. I/O Function Quick Start Flow Chart
Power-On Reset
Release Peripheral Reset by setting PENA bit in
Clock Control Register (0xFFFFFFD0)
Enable clock to GIO through PCR
(Check device datasheet for the peripheral select)
Bring GIO out of reset by writing 1 to GIOGCR0
Configure as input/output?
Input
Output
Clear corresponding bits in GIODIR to 0
Set corresponding bits in GIODIR to 1
Enable pull?
Open drain?
Yes
No
Clear corresponding bits in
GIOPULDIS to 0
Set corresponding bits in
GIOPULDIS to 1
Yes
No
Set corresponding bits in
GIOPDR to 1
Clear corresponding bits in
GIOPDR to 0
Pull up/down?
Down
Clear corresponding
bits in GIOPSL to 0
Output 1 or 0?
Set corresponding bits
in to GIOPSL to 1
0
1
Write 1 to corresponding bits
in GIODSET
Write 1 to corresponding bits
in GIODCLR
Read corresponding bits in GIODIN, getting input value
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Figure 22-2. Interrupt Generation Function Quick Start Flow Chart
Power-On Reset
Enable Peripherals by setting PENA bit in Clock Control Register (0xFFFFFFD0)
Enable GIO through PCR (Check devicedatasheet for the peripheral select)
Initialize vector interrupt table - Map GIO low level interrupt and / or high level
interrupt service routine to pre-defined device specific interrupt channel.
(Check device datasheet)
Enable the FIQ/IRQ interrupt in VIM (Check VIM User Guide)
Enable the FIQ/IRQ interrupt in CPU (Check CPU User Guide)
Bring GIO out of reset (See register GIOGCR0)
Both rising and falling edge / single edge trigger interrupt?
Both edge
Single edge
Set corresponding bits in GIOINTDETto 1
Clear corresponding bits in GIOINTDETto 0
Rising/Falling edge?
Rising
Falling
Set corresponding bits in
GIOPOL to 1
Clear corresponding bits in
GIOPOL to 0
Configure as high /low level interrupt?
High level
Low level
Write 1 to corresponding bits in GIOLVLSET
Write 1 to corresponding bits in GIOLVLCLR
Write 0xFF to clean the GIO interrupt flag register GIOFLG
Write 1 to corresponding bits in GIOENASET to enable interrupt
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22.3 Functional Description of GIO Module
As shown in Figure 22-3, the GIO module comprises of two separate components: an input/output (I/O)
block and an interrupt block.
Figure 22-3. GIO Module Diagram
GIO Module
xx
xx
GIOx[7:0] port
PIN
CONTROL
BLOCK
Interrupt Requests
INTERRUPT
CONTROL
BLOCK
To Interrupt Manager
Host Interface
22.3.1 I/O Functions
The I/O block allows each GIO terminal to be configured for use as a general-purpose input or output in
the application. The GIO module supports multiple registers to control the various aspects of the input and
output functions. These are described as follows.
• Data direction (GIODIR)
Configures GIO terminal(s) as input (default) or output through the GIODIRx registers.
• Data input (GIODIN)
Reflects the logic level on GIO terminals in the GIODINx registers. A high voltage (V IH or greater)
applied to the pin causes a high value (1) in the data input register (GIODIN[7:0]). When a low voltage
(V IL or less) is applied to the pin, the data input register reads a low value (0). The V IH and V IL values
are device specific and can be found in the device datasheet.
• Data output (GIODOUT)
Configures the logic level to be output on GIO terminal(s) configured as outputs. A low value (0) written
to the data output register forces the pin to a low output voltage (V OL or lower). A high value (1) written
to the data output register (GIODOUTx) forces the pin to a high output voltage (V OH or higher) if the
open drain functionality is disabled (GIOPDRx[7:0]). If open drain functionality is enabled, a high value
(1) written to the data output register forces the pin to a high-impedance state (Z).
• Data set (GIODSET)
Allows logic HIGH to be output on GIO terminal(s) configured as outputs by writing 1's to the required
bits in the GIODSETx registers. If open drain functionality is enabled, a high value (1) written to the
data output register forces the pin to a high-impedance state (Z). The GIODSETx registers eliminate
the need for the application to perform a read-modify-write operation when it needs to set one or more
GIO pin(s).
• Data clear (GIODCLR)
Allows logic LOW to be output on GIO terminal(s) configured as outputs by writing 1s to the required
bits in the GIODCLRx registers. The GIODCLRx registers eliminate the need for the application to
perform a read-modify-write operation when it needs to clear one or more GIO pin(s).
• Open drain (GIOPDR)
Open drain functionality is enabled or disabled (default) using the open drain register GIOPDR[7:0]
register. If open-drain mode output is enabled on a pin, a high value (1) written to the data output
register (GIODOUTx[7:0]) forces the pin to a high impedance state (Z).
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Pull disable (GIOPULDIS)
Disables the internal pull on GIO terminal(s) configured as inputs by writing to the GIOPULDISx
registers.
Pull select (GIOPSL)
Selects internal pull down (default) or pull up on GIO terminal(s) configured as inputs by writing to the
GIOPULSELx registers.
Refer to the specific device's datasheet to identify the number of GIO ports as well as the input and output
functions supported. Some devices may not support the programmable pull controls. In that case, the pull
disable and the pull select register controls will not work.
22.3.2 Interrupt Function
The GIO module supports up to 32 terminals to be configured for generating an interrupt to the host
processor through the Vectored Interrupt Manager (VIM). The main functions of the interrupt block are:
• Select the GIO pin(s) that is/are used to generate interrupt(s)
This is done via the interrupt enable set and clear registers, GIOENASET and GIOENACLR.
• Select the edge on the selected GIO pin(s) that is/are used to generate interrupt(s): rising/falling/both
Rising or falling edge can be selected via the GIOPOL register. If interrupt is required to be generated
on both rising and falling edges, this can be configured via the GIOINTDET register.
• Select the interrupt priority
Low- or high-level interrupt can be selected through the GIOLVLSET and GIOLVLCLR registers.
• Individual interrupt flags are set in the GIOFLG register
The terminals on GIO ports A through D are all interrupt-capable and can be used to handle either general
I/O functions or interrupt requests. Each interrupt request can be connected to the VIM at one of two
different levels – High (or A) and Low (or B), depending on the VIM channel number. The VIM has an
inherent priority scheme so that a request on a lower number channel has a higher priority than a request
on a higher number channel. Refer the device datasheet to identify the VIM channel numbers for the GIO
level A and level B interrupt requests. Also note that the interrupt priority of level A and level B interrupt
handling blocks can be re-programmed in the VIM.
22.3.3 GIO Block Diagram
The GIO block diagram (Figure 22-4) represents the flow of information through a pin. The shaded area
corresponds to the I/O block; the unshaded area corresponds to the interrupt block.
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Figure 22-4. GIO Block Diagram
GIOPSL
Pull Select
GIOPULDIS
Pull Disable
GIODIRx
GIOPDRx
GIODSETx
external pin
GIODOUTx
GIODINx
Falling edge
Interrupt disable
Rising edge
Interrupt enable
Low-level
High-level
GIOPOL
GIOFLG
GIOENASET
GIOENACLR
GIOLVLSET
GIOLVLCLR
Low-level
(level B)
interrupt
(1)
handling
High-level
(level A)
interrupt
GIOINTDET
To
VIM
VBUSP (peripheral bus)
GIODCLRx
(1)
To
VIM
handling
(1)
A single low-level-interrupt-handling block and a single high-level-interrupt-handling block service all of the
interrupt-capable external pins, but only one pin can be serviced by an interrupt block at a time.
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22.4 Device Modes of Operation
The GIO module behaves differently in different modes of operation. There are two main modes:
• Emulation mode
• Power-down mode (low-power mode)
22.4.1 Emulation Mode
Emulation mode is used by debugger tools to stop the CPU at breakpoints to read registers.
NOTE: Emulation Mode and Emulation Registers
Emulation mode is a mode of operation of the device and is separate from the GIO
emulation registers (GIOEMU1 and GIOEMU2). The contents of these emulation registers
are identical to the contents of GIO offset registers (GIOOFF1 and GIOOFF2). Both
emulation registers and GIO offset registers are NOT cleared when they are read in
emulation mode. GIO offset registers are cleared when they are read in normal mode (other
than emulation mode). The emulation registers are NOT cleared when they are read in
normal mode. The intention for the emulation registers is that software can use them without
clearing the flags.
During emulation mode:
• External interrupts are not captured because the VIM is unable to service interrupts.
• Any register can be read without affecting the state of the system.
• A write to a register still does affect the state of the system.
22.4.2 Power-Down Mode (Low-Power Mode)
In power-down mode, the clock signal to the GIO module is disabled. Thus, there is no switching and the
only current draw comes from leakage current. In power-down mode, interrupt pins become level-sensitive
rather than edge-sensitive. The polarity bit changes function from falling-edge-triggered to low-leveltriggered and rising-edge-triggered to high-level-triggered. A corresponding level on an interrupt pin pulls
the module out of low-power mode, if the interrupt is also enabled to wake up the device out of a lowpower mode.
22.4.2.1 Module-Level Power Down
The GIO module can be placed into a power down state by disabling the GIO peripheral module via the
appropriate bit in the peripheral power down register. Please refer to the Peripheral Central Resource
Registers (Section 2.5.3) for details.
22.4.2.2 Device-Level Power Down
The entire device can be placed in one of the pre-defined low-power modes: doze, snooze, or sleep using
the clock source and clock domain disable registers in the system module.
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22.5 GIO Control Registers
Table 22-1 shows the summary of the GIO registers. The registers are accessible in 8-, 16-, and 32-bit
reads or writes.
The start address for the GIO module is FFF7 BC00h.
The GIO module supports up to 8 ports. Refer to your device-specific data manual to identify the actual
number of GIO ports and the number of pins in each GIO port implemented on this device.
The GIO module supports up to 4 interrupt-capable ports. Refer to the device datasheet to identify the
actual number of interrupt-capable GIO ports and the number of pins in each GIO port implemented on
this device.
Table 22-1. GIO Control Registers
Offset
Acronym
Register Description
00h
GIOGCR0
GIO Global Control Register
Section 22.5.1
Section
08h
GIOINTDET
GIO Interrupt Detect Register
Section 22.5.2
0Ch
GIOPOL
GIO Interrupt Polarity Register
10h
GIOENASET
GIO Interrupt Enable Set Register
Section 22.5.4.1
14h
GIOENACLR
GIO Interrupt Enable Clear Register
Section 22.5.4.2
Section 22.5.3
18h
GIOLVLSET
GIO Interrupt Priority Set Register
Section 22.5.5.1
1Ch
GIOLVLCLR
GIO Interrupt Priority Clear Register
Section 22.5.5.2
20h
GIOFLG
GIO Interrupt Flag Register
Section 22.5.6
24h
GIOOFF1
GIO Offset 1 Register
Section 22.5.7
Section 22.5.8
28h
GIOOFF2
GIO Offset 2 Register
2Ch
GIOEMU1
GIO Emulation 1 Register
Section 22.5.9
30h
GIOEMU2
GIO Emulation 2 Register
Section 22.5.10
34h
GIODIRA
GIO Data Direction Register
Section 22.5.11
38h
GIODINA
GIO Data Input Register
Section 22.5.12
3Ch
GIODOUTA
GIO Data Output Register
Section 22.5.13
40h
GIODSETA
GIO Data Set Register
Section 22.5.14
44h
GIODCLRA
GIO Data Clear Register
Section 22.5.15
48h
GIOPDRA
GIO Open Drain Register
Section 22.5.16
4Ch
GIOPULDISA
GIO Pull Disable Register
Section 22.5.17
50h
GIOPSLA
GIO Pull Select Register
Section 22.5.18
54h
GIODIRB
GIO Data Direction Register
Section 22.5.11
58h
GIODINB
GIO Data Input Register
Section 22.5.12
5Ch
GIODOUTB
GIO Data Output Register
Section 22.5.13
60h
GIODSETB
GIO Data Set Register
Section 22.5.14
64h
GIODCLRB
GIO Data Clear Register
Section 22.5.15
68h
GIOPDRB
GIO Open Drain Register
Section 22.5.16
6Ch
GIOPULDISB
GIO Pull Disable Register
Section 22.5.17
70h
GIOPSLB
GIO Pull Select Register
Section 22.5.18
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22.5.1 GIO Global Control Register (GIOGCR0)
The GIOGCR0 register contains one bit that controls the module reset status. Writing a 0 to this bit puts
the module in a reset state. After system reset, this bit must be set to 1 before configuring any other
register of the GIO module. Figure 22-5 and Table 22-2 describe this register.
Figure 22-5. GIO Global Control Register (GIOGCR0) [offset = 00h]
31
16
Reserved
R-0
15
1
0
Reserved
RESET
R-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 22-2. GIO Global Control Register (GIOGCR0) Field Descriptions
Bit
31-1
0
Field
Reserved
Value
0
RESET
Description
Reads return 0. Writes have no effect.
GIO reset.
0
The GIO is in reset state.
1
The GIO is operating normally.
NOTE: Note that putting the GIO module in reset state is not the same as putting it in a low-power
state.
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22.5.2 GIO Interrupt Detect Register (GIOINTDET)
The GIO module supports generation of an interrupt request to CPU when a rising edge, falling edge, or
both edges is detected on one or more GIO pin(s). The GIOINTDET register allows both rising and falling
edges to be detected, while the GIOPOL register allows the application to define whether a rising edge or
a falling edge is to be detected. Figure 22-6 and Table 22-3 describe this register.
Figure 22-6. GIO Interrupt Detect Register (GIOINTDET) [offset = 08h]
31
24
23
16
GIOINTDET 3
GIOINTDET 2
R/W-0
R/W-0
15
8
7
0
GIOINTDET 1
GIOINTDET 0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 22-3. GIO Interrupt Detect Register (GIOINTDET) Field Descriptions
Bit
31-24
23-16
15-8
7-0
Field
Value
GIOINTDET 3
Interrupt detection select for pins GIOD[7:0]
0
The flag sets on either a falling or a rising edge on the corresponding pin, depending on the polarity
setup in the polarity register (GIOPOL).
1
The flag sets on both the rising and falling edges on the corresponding pin.
GIOINTDET 2
Interrupt detection select for pins GIOC[7:0]
0
The flag sets on either a falling or a rising edge on the corresponding pin, depending on the polarity
setup in the polarity register (GIOPOL).
1
The flag sets on both the rising and falling edges on the corresponding pin.
GIOINTDET 1
Interrupt detection select for pins GIOB[7:0]
0
The flag sets on either a falling or a rising edge on the corresponding pin, depending on the polarity
setup in the polarity register (GIOPOL).
1
The flag sets on both the rising and falling edges on the corresponding pin.
GIOINTDET 0
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Description
Interrupt detection select for pins GIOA[7:0]
0
The flag sets on either a falling or a rising edge on the corresponding pin, depending on the polarity
setup in the polarity register (GIOPOL).
1
The flag sets on both the rising and falling edges on the corresponding pin.
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22.5.3 GIO Interrupt Polarity Register (GIOPOL)
The GIOPOL register configures the polarity of the edge, rising edge or falling edge, that needs to be
detected. When the device is in low-power mode, the GIOPOL register controls the level, high or low,
which will be detected by the GIO module. Figure 22-7 and Table 22-4 describe this register.
Figure 22-7. GIO Interrupt Polarity Register (GIOPOL) [offset = 0Ch]
31
24
23
16
GIOPOL 3
GIOPOL 2
R/W-0
R/W-0
15
8
7
0
GIOPOL 1
GIOPOL 0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 22-4. GIO Interrupt Polarity Register (GIOPOL) Field Descriptions
Bit
31-24
Field
Value
GIOPOL 3
Description
Interrupt polarity select for pins GIOD[7:0]
Normal operation (user or privileged mode):
0
The flag is set on the falling edge on the corresponding pin.
1
The flag is set on the rising edge on the corresponding pin.
Low-power mode (GIO module clocks off):
23-16
0
The interrupt is triggered on the low level.
1
The interrupt is triggered on the high level.
GIOPOL 2
Interrupt polarity select for pins GIOC[7:0]
Normal operation (user or privileged mode):
0
The flag is set on the falling edge on the corresponding pin.
1
The flag is set on the rising edge on the corresponding pin.
Low-power mode (GIO module clocks off):
15-8
0
The interrupt is triggered on the low level.
1
The interrupt is triggered on the high level.
GIOPOL 1
Interrupt polarity select for pins GIOB[7:0]
Normal operation (user or privileged mode):
0
The flag is set on the falling edge on the corresponding pin.
1
The flag is set on the rising edge on the corresponding pin.
Low-power mode (GIO module clocks off):
7-0
0
The interrupt is triggered on the low level.
1
The interrupt is triggered on the high level.
GIOPOL 0
Interrupt polarity select for pins GIOA[7:0]
Normal operation (user or privileged mode):
0
The flag is set on the falling edge on the corresponding pin.
1
The flag is set on the rising edge on the corresponding pin.
Low-power mode (GIO module clocks off):
1032
0
The interrupt is triggered on the low level.
1
The interrupt is triggered on the high level.
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22.5.4 GIO Interrupt Enable Registers (GIOENASET and GIOENACLR)
The GIOENASET and GIOENACLR registers control which interrupt-capable pins are actually configured
as interrupts. If the interrupt is enabled, the rising edge, falling edge, or both edges on the selected pin
lead to an interrupt request.
22.5.4.1 GIOENASET Register
Figure 22-8 and Table 22-5 describe this register.
NOTE: Enabling Interrupt at the Device Level
The interrupt channel in the Vectored Interrupt Manager (VIM) must be enabled for the
interrupt request to be forwarded to the CPU. Additionally, the ARM CPU (CPSR bit 7 or 6)
must be cleared to respond to interrupt requests (IRQ/FIQ).
Figure 22-8. GIO Interrupt Enable Set Register (GIOENASET) [offset = 10h]
31
24
23
16
GIOENASET 3
GIOENASET 2
R/W-0
R/W-0
15
8
7
0
GIOENASET 1
GIOENASET 0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 22-5. GIO Interrupt Enable Set Register (GIOENASET) Field Descriptions
Bit
31-24
Field
Value
GIOENASET 3
Description
Interrupt enable for pins GIOD[7:0]
0
Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.
1
Read: The interrupt is enabled.
Write: Enables the interrupt.
23-16
GIOENASET 2
Interrupt enable for pins GIOC[7:0]
0
Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.
1
Read: The interrupt is enabled.
Write: Enables the interrupt.
15-8
GIOENASET 1
Interrupt enable for pins GIOB[7:0]
0
Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.
1
Read: The interrupt is enabled.
Write: Enables the interrupt.
7-0
GIOENASET 0
Interrupt enable for pins GIOA[7:0]
0
Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.
1
Read: The interrupt is enabled.
Write: Enables the interrupt.
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22.5.4.2 GIOENACLR Register
This register disables the interrupt. Figure 22-9 and Table 22-6 describe this register.
Figure 22-9. GIO Interrupt Enable Clear Register (GIOENACLR) [offset = 14h]
31
24
23
16
GIOENACLR 3
GIOENACLR 2
R/W-0
R/W-0
15
8
7
0
GIOENACLR 1
GIOENACLR 0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 22-6. GIO Interrupt Enable Clear Register (GIOENACLR) Field Descriptions
Bit
31-24
Field
Value
GIOENACLR 3
Description
Interrupt disable for pins GIOD[7:0]
0
Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.
1
Read: The interrupt is enabled.
Write: Disables the interrupt.
23-16
GIOENACLR 2
Interrupt disable for pins GIOC[7:0]
0
Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.
1
Read: The interrupt is enabled.
Write: Disables the interrupt.
15-8
GIOENACLR 1
Interrupt disable for pins GIOB[7:0]
0
Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.
1
Read: The interrupt is enabled.
Write: Disables the interrupt.
7-0
GIOENACLR 0
Interrupt disable for pins GIOA[7:0]
0
Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.
1
Read: The interrupt is enabled.
Write: Disables the interrupt.
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22.5.5 GIO Interrupt Priority Registers (GIOLVLSET and GIOLVLCLR)
The GIOLVLSET and GIOLVLCLR registers configure the interrupts as high-level (level A) or low-level
(level B) going to the Vectored Interrupt Manager (VIM). Each interrupt is individually configured.
• The high-level interrupts are recorded to GIOOFF1 and GIOEMU1.
• The low-level interrupts are recorded to GIOOFF2 and GIOEMU2.
NOTE: The GIO module can generate two interrupt requests. These are connected to two separate
channels on the Vectored Interrupt Manager (VIM). The lower-numbered VIM channels are
higher priority. The GIO interrupt connected to a lower-number channel is the high-level (also
called level A) GIO interrupt, while the GIO interrupt connected to a higher-number channel
is the low-level (also called level B) GIO interrupt.
22.5.5.1 GIOLVLSET Register
The GIOLVLSET register is used to configure an interrupt as a high-level interrupt going to the VIM. An
interrupt can be configured as a high-level interrupt by writing a 1 into the corresponding bit of the
GIOLVLSET register. Writing a 0 has no effect. Figure 22-10 and Table 22-7 describe this register.
Figure 22-10. GIO Interrupt Priority Register (GIOLVLSET) [offset = 18h]
31
16
GIOLVLSET 3
GIOLVLSET 2
R/W-0
R/W-0
15
8
7
0
GIOLVLSET 1
GIOLVLSET 0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 22-7. GIO Interrupt Priority Register (GIOLVLSET) Field Descriptions
Bit
31-24
Field
Value
GIOLVLSET 3
Description
GIO high-priority interrupt for pins GIOD[7:0].
0
Read: The interrupt is a low-level interrupt. The low-level interrupts are recorded to GIOOFF2
and GIOEMU2.
Write: Writing a 0 to this bit has no effect.
1
Read: The interrupt is set as a high-level interrupt. The high-level interrupts are recorded to
GIOOFF1 and GIOEMU1.
Write: Sets the interrupt as a high-level interrupt. The high-level interrupts are recorded to
GIOOFF1 and GIOEMU1.
23-16
GIOLVLSET 2
GIO high-priority interrupt for pins GIOC[7:0].
0
Read: The interrupt is a low-level interrupt. The low-level interrupts are recorded to GIOOFF2
and GIOEMU2.
Write: Writing a 0 to this bit has no effect.
1
Read: The interrupt is set as a high-level interrupt. The high-level interrupts are recorded to
GIOOFF1 and GIOEMU1.
Write: Sets the interrupt as a high-level interrupt. The high-level interrupts are recorded to
GIOOFF1 and GIOEMU1.
15-8
GIOLVLSET 1
GIO high-priority interrupt for pins GIOB[7:0].
0
Read: The interrupt is a low-level interrupt. The low-level interrupts are recorded to GIOOFF2
and GIOEMU2.
Write: Writing a 0 to this bit has no effect.
1
Read: The interrupt is set as a high-level interrupt. The high-level interrupts are recorded to
GIOOFF1 and GIOEMU1.
Write: Sets the interrupt as a high-level interrupt. The high-level interrupts are recorded to
GIOOFF1 and GIOEMU1.
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Table 22-7. GIO Interrupt Priority Register (GIOLVLSET) Field Descriptions (continued)
Bit
Field
7-0
GIOLVLSET 0
Value
Description
GIO high-priority interrupt for pins GIOA[7:0].
0
Read: The interrupt is a low-level interrupt. The low-level interrupts are recorded to GIOOFF2
and GIOEMU2.
Write: Writing a 0 to this bit has no effect.
1
Read: The interrupt is set as a high-level interrupt. The high-level interrupts are recorded to
GIOOFF1 and GIOEMU1.
Write: Sets the interrupt as a high-level interrupt. The high-level interrupts are recorded to
GIOOFF1 and GIOEMU1.
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22.5.5.2 GIOLVLCLR Register
The GIOLVLCLR register is used to configure an interrupt as a low-level interrupt going to the VIM. An
interrupt can be configured as a low-level interrupt by writing a 1 into the corresponding bit of the
GIOLVLCLR register. Writing a 0 has no effect. Figure 22-11 and Table 22-8 describe this register.
Figure 22-11. GIO Interrupt Priority Register (GIOLVLCLR) [offset = 1Ch]
31
16
GIOLVLCLR 3
GIOLVLCLR 2
R/W-0
R/W-0
15
8
7
0
GIOLVLCLR 1
GIOLVLCLR 0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 22-8. GIO Interrupt Priority Register (GIOLVLCLR) Field Descriptions
Bit
31-24
Field
Value
GIOLVLCLR 3
Description
GIO low-priority interrupt for pins GIOD[7:0]
0
Read: The interrupt is a low-level interrupt.
Write: Writing a 0 to this bit has no effect.
1
Read: The interrupt is set as a high-level interrupt. The high-level interrupts are recorded to
GIOOFF1 and GIOEMU1.
Write: Sets the interrupt as a low-level interrupt. The low-level interrupts are recorded to
GIOOFF2 and GIOEMU2.
23-16
GIOLVLCLR 2
GIO low-priority interrupt for pins GIOC[7:0]
0
Read: The interrupt is a low-level interrupt.
Write: Writing a 0 to this bit has no effect.
1
Read: The interrupt is set as a high-level interrupt. The high-level interrupts are recorded to
GIOOFF1 and GIOEMU1.
Write: Sets the interrupt as a low-level interrupt. The low-level interrupts are recorded to
GIOOFF2 and GIOEMU2.
15-8
GIOLVLCLR 1
GIO low-priority interrupt for pins GIOB[7:0]
0
Read: The interrupt is a low-level interrupt.
Write: Writing a 0 to this bit has no effect.
1
Read: The interrupt is set as a high-level interrupt. The high-level interrupts are recorded to
GIOOFF1 and GIOEMU1.
Write: Sets the interrupt as a low-level interrupt. The low-level interrupts are recorded to
GIOOFF2 and GIOEMU2.
7-0
GIOLVLCLR 0
GIO low-priority interrupt for pins GIOA[7:0]
0
Read: The interrupt is a low-level interrupt.
Write: Writing a 0 to this bit has no effect.
1
Read: The interrupt is set as a high-level interrupt. The high-level interrupts are recorded to
GIOOFF1 and GIOEMU1.
Write: Sets the interrupt as a low-level interrupt. The low-level interrupts are recorded to
GIOOFF2 and GIOEMU2.
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22.5.6 GIO Interrupt Flag Register (GIOFLG)
The GIOFLG register contains flags indicating that the transition edge (as set in GIOINTDET and GIOPOL
registers) has occurred. The flag can be cleared by the CPU writing a 1 to the flag that is set. The flag is
also cleared by reading the appropriate interrupt offset register (GIOOFF1 or GIOOFF2). Figure 22-12 and
Table 22-9 describe this register.
Figure 22-12. GIO Interrupt Flag Register (GIOFLG) [offset = 20h]
31
24
23
16
GIOFLG 3
GIOFLG 2
R/W1C-0
R/W1C-0
15
8
7
0
GIOFLG 1
GIOFLG 0
R/W1C-0
R/W1C-0
LEGEND: R/W = Read/Write; W1C = Write 1 to clear; -n = value after reset
Table 22-9. GIO Interrupt Flag Register (GIOFLG) Field Descriptions
Bit
31-24
Field
Value
GIOFLG 3
Description
GIO flag for pins GIOD[7:0]
0
Read: A transition has not occurred since the last clear.
Write: Writing a 0 to this bit has no effect.
1
Read: The selected transition on the corresponding pin has occurred.
Write: The corresponding bit is cleared to 0.
Note: This bit is also cleared by a read to the corresponding bit in the appropriate offset
register.
23-16
GIOFLG 2
GIO flag for pins GIOC[7:0]
0
Read: A transition has not occurred since the last clear.
Write: Writing a 0 to this bit has no effect.
1
Read: The selected transition on the corresponding pin has occurred.
Write: The corresponding bit is cleared to 0.
Note: This bit is also cleared by a read to the corresponding bit in the appropriate offset
register.
15-8
GIOFLG 1
GIO flag for pins GIOB[7:0]
0
Read: A transition has not occurred since the last clear.
Write: Writing a 0 to this bit has no effect.
1
Read: The selected transition on the corresponding pin has occurred.
Write: The corresponding bit is cleared to 0.
Note: This bit is also cleared by a read to the corresponding bit in the appropriate offset
register.
7-0
GIOFLG 0
GIO flag for pins GIOA[7:0]
0
Read: A transition has not occurred since the last clear.
Write: Writing a 0 to this bit has no effect.
1
Read: The selected transition on the corresponding pin has occurred.
Write: The corresponding bit is cleared to 0.
Note: This bit is also cleared by a read to the corresponding bit in the appropriate offset
register.
NOTE: An interrupt flag gets set when the selected transition happens on the corresponding GIO pin
regardless of whether the interrupt generation is enabled or not. It is recommended to
clear a flag before enabling the interrupt generation for a transition on the corresponding GIO
pin.
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22.5.7 GIO Offset Register 1 (GIOOFF1)
The GIOOFF1 register provides a numerical offset value that represents the pending external interrupt
with high priority. The offset value can be used to locate the position of the interrupt routine in a vector
table in application software. Figure 22-13 and Table 22-10 describe this register.
NOTE: Reading this register clears it, GIOEMU1 and the corresponding flag bit in the GIOFLG
register. However, in emulation mode, a read to this register does not clear any register or
flag. If more than one GIO interrupts are pending, then reading the GIOOFF1 register will
change the contents of GIOOFF1 and GIOEMU1 to show the offset value for the next
highest-priority pending interrupt. The application can choose to service all GIO interrupts
from the same service routine by continuing to read the GIOOFF1 register until it reads
zeros.
Figure 22-13. GIO Offset 1 Register (GIOOFF1) [offset = 24h]
31
16
Reserved
R-0
15
6
5
0
Reserved
GIOOFF1
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 22-10. GIO Offset 1 Register (GIOOFF1) Field Descriptions
Bit
Field
31-6
Reserved
5-0
GIOOFF1
Value
0
Description
Reads return 0. Writes have no effect.
GIO offset 1. These bits index the currently pending high-priority interrupt. This register and the
flag bit (in the GIOFLG register) are also cleared when this register is read, except in emulation
mode.
0
No interrupt is pending.
1h
Interrupt 0 (corresponding to GIOA0) is pending with a high priority.
:
8h
Interrupt 7 (corresponding to GIOA7) is pending with a high priority.
9h
Interrupt 8 (corresponding to GIOB0) is pending with a high priority.
:
10h
:
20h
21h-3Fh
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:
Interrupt 16 (corresponding to GIOB7) is pending with a high priority.
:
Interrupt 32 (corresponding to GIOD7) is pending with a high priority.
Reserved
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22.5.8 GIO Offset B Register (GIOOFF2)
The GIOOFF2 register provides a numerical offset value that represents the pending external interrupt
with low priority. The offset value can be used to locate the position of the interrupt routine in a vector
table in application software. Figure 22-14 and Table 22-11 describe this register.
NOTE: Reading this register clears it, GIOEMU2 and the corresponding flag bit in the GIOFLG
register. However, in emulation mode, a read to this register does not clear any register or
flag. If more than one GIO interrupts are pending, then reading the GIOOFF1 register will
change the contents of GIOOFF2 and GIOEMU2 to show the offset value for the next
highest-priority pending interrupt. The application can choose to service all GIO interrupts
from the same service routine by continuing to read the GIOOFF1 register until it reads
zeros.
Figure 22-14. GIO Offset 2 Register (GIOOFF2) [offset = 28h]
31
16
Reserved
R-0
15
6
5
0
Reserved
GIOOFF2
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 22-11. GIO Offset 2 Register (GIOOFF2) Field Descriptions
Bit
Field
31-6
Reserved
5-0
GIOOFF2
Value
0
Reads return 0. Writes have no effect.
GIO offset 2. These bits index the currently pending low-priority interrupt. This register and the
flag bit (in the GIOFLG register) are also cleared when this register is read, except in emulation
mode.
0
No interrupt is pending.
1h
Interrupt 0 (corresponding to GIOA0) is pending with a low priority.
:
:
8h
Interrupt 7 (corresponding to GIOA7) is pending with a low priority.
9h
Interrupt 8 (corresponding to GIOB0) is pending with a low priority.
:
10h
:
20h
21h-3Fh
1040
Description
:
Interrupt 16 (corresponding to GIOB7) is pending with a low priority.
:
Interrupt 32 (corresponding to GIOD7) is pending with a low priority.
Reserved
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22.5.9 GIO Emulation A Register (GIOEMU1)
The GIOEMU1 register is a read-only register. The contents of this register are identical to the contents of
GIOOFF1. The intention for the this register is that software can use it without clearing the flags.
Figure 22-15 and Table 22-12 describe this register.
NOTE: The corresponding flag in the GIOFLG register is not cleared when the GIOEMU1 register is
read.
Figure 22-15. GIO Emulation 1 Register (GIOEMU1) [offset = 2Ch]
31
16
Reserved
R-0
15
6
5
0
Reserved
GIOEMU1
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 22-12. GIO Emulation 1 Register (GIOEMU1) Field Descriptions
Bit
Field
31-6
Reserved
5-0
GIOEMU1
Value
0
Description
Reads return 0. Writes have no effect.
GIO offset emulation 1. These bits index the currently pending high-priority interrupt. No register
or flag is cleared by reading this register.
0
No interrupt is pending.
1h
Interrupt 0 (corresponding to GIOA0) is pending with a high priority.
:
8h
Interrupt 7 (corresponding to GIOA7) is pending with a high priority.
9h
Interrupt 8 (corresponding to GIOB0) is pending with a high priority.
:
10h
:
20h
21h-3Fh
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:
Interrupt 16 (corresponding to GIOB7) is pending with a high priority.
:
Interrupt 32 (corresponding to GIOD7) is pending with a high priority.
Reserved
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22.5.10 GIO Emulation B Register (GIOEMU2)
The GIOEMU2 register is a read-only register. The contents of this register are identical to the contents of
GIOOFF2. The intention for the this register is that software can use it without clearing the flags.
Figure 22-16 and Table 22-13 describe this register.
NOTE: The corresponding flag in the GIOFLG register is not cleared when the GIOEMU2 register is
read.
Figure 22-16. GIO Emulation 2 Register (GIOEMU2) [offset = 30h]
31
16
Reserved
R-0
15
6
5
0
Reserved
GIOEMU2
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 22-13. GIO Emulation 2 Register (GIOEMU2) Field Descriptions
Bit
Field
31-6
Reserved
5-0
GIOEMU2
Value
0
Reads return 0. Writes have no effect.
GIO offset emulation 2. These bits index the currently pending low-priority interrupt. No register
or flag is cleared by reading this register.
0
No interrupt is pending.
1h
Interrupt 0 (corresponding to GIOA0) is pending with a low priority.
:
:
8h
Interrupt 7 (corresponding to GIOA7) is pending with a low priority.
9h
Interrupt 8 (corresponding to GIOB0) is pending with a low priority.
:
10h
:
20h
21h-3Fh
1042
Description
:
Interrupt 16 (corresponding to GIOB7) is pending with a low priority.
:
Interrupt 32 (corresponding to GIOD7) is pending with a low priority.
Reserved
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22.5.11 GIO Data Direction Registers (GIODIR[A-B])
The GIODIR register controls whether the pins of a given port are configured as inputs or outputs.
Figure 22-17 and Table 22-14 describe this register.
Figure 22-17. GIO Data Direction Registers (GIODIR[A-B]) [offset = 34h, 54h]
31
16
Reserved
R-0
15
8
7
0
Reserved
GIODIR[7:0]
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22-14. GIO Data Direction Registers (GIODIR[A-B]) Field Descriptions
Bit
Field
31-8
Reserved
7-0
GIODIR[n]
Value
0
Description
Reads return 0. Writes have no effect.
GIO data direction of port n, pins [7:0]
0
The GIO pin is an input. Note: If the pin direction is set as an input, the output buffer is tristated.
1
The GIO pin is an output.
22.5.12 GIO Data Input Registers (GIODIN[A-B])
Values in the GIODIN register reflect the current state (high = 1 or low = 0) on the pins of the port.
Figure 22-18 and Table 22-15 describe this register.
Figure 22-18. GIO Data Input Registers (GIODIN[A-B]) [offset = 38h, 58h]
31
16
Reserved
R-0
15
8
7
0
Reserved
GIODIN[7:0]
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22-15. GIO Data Input Registers (GIODIN[A-B]) Field Descriptions
Bit
Field
31-8
Reserved
7-0
GIODIN[n]
Value
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0
Description
Reads return 0. Writes have no effect.
GIO data input for port n, pins [7:0]
0
The pin is at logic low (0).
1
The pin is at logic high (1).
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22.5.13 GIO Data Output Registers (GIODOUT[A-B])
Values in the GIODOUT register specify the output state (high = 1 or low = 0) of the pins of the port when
they are configured as outputs. Figure 22-19 and Table 22-16 describe this register.
NOTE: Values in the GIODSET register set the data output control register bits to 1 regardless of
the current value in the GIODOUT bits.
Figure 22-19. GIO Data Output Registers (GIODOUT[A-B]) [offset = 3Ch, 5Ch]
31
16
Reserved
R-0
15
8
7
0
Reserved
GIODOUT[7:0]
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22-16. GIO Data Output Registers (GIODOUT[A-B]) Field Descriptions
Bit
Field
31-8
Reserved
7-0
GIODOUT[n]
Value
0
Description
Reads return 0. Writes have no effect.
GIO data output of port n, pins[7:0].
0
The pin is driven to logic low (0).
1
The pin is driven to logic high (1).
Note: Output is in high impedance state if the GIOPDRx bit = 1 and GIODOUTx bit = 1.
Note: GIO pin is placed in output mode by setting the GIODIRx bit to 1.
22.5.14 GIO Data Set Registers (GIODSET[A-B])
Values in this register set the data output control register bits to 1 regardless of the current value in the
GIODOUT bits. The contents of this register reflect the contents of GIODOUT. Figure 22-20 and Table 2217 describe this register.
Figure 22-20. GIO Data Set Registers (GIODSET[A-B]) [offset = 40h, 60h]
31
16
Reserved
R-0
15
8
7
0
Reserved
GIODSET[7:0]
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22-17. GIO Data Set Registers (GIODSET[A-B]) Field Descriptions
Bit
Field
31-8
Reserved
7-0
GIODSET[n]
Value
0
Description
Reads return 0. Writes have no effect.
GIO data set for port n, pins[7:0]. This bit drives the output of GIO pin high.
0
Write: Writing a 0 has no effect.
1
Write: The corresponding GIO pin is driven to logic high (1).
Note: The current logic state of the GIODOUT bit will also be displayed by this bit.
Note: GIO pin is placed in output mode by setting the GIODIRx bit to 1.
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22.5.15 GIO Data Clear Registers (GIODCLR[A-B])
Values in this register clear the data output register (GIO Data Output Register [A-H]) bit to 0 regardless of
its current value. The contents of this register reflect the contents of GIODOUT. Figure 22-21 and
Table 22-18 describe this register.
Figure 22-21. GIO Data Clear Registers (GIODCLR[A-B]) [offset = 44h, 64h]
31
16
Reserved
R-0
15
8
7
0
Reserved
GIODCLR[7:0]
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22-18. GIO Data Clear Registers (GIODCLR[A-B]) Field Descriptions
Bit
Field
31-8
Reserved
7-0
GIODCLR[n]
Value
0
Description
Reads return 0. Writes have no effect.
GIO data clear for port n, pins[7:0]. This bit drives the output of GIO pin low.
0
Write: Writing a 0 has no effect.
1
Write: The corresponding GIO pin is driven to logic low (0).
Note: The current logic state of the GIODOUT bit will also be displayed by this bit.
Note: GIO pin is placed in output mode by setting the GIODIRx bit to 1.
22.5.16 GIO Open Drain Registers (GIOPDR[A-B])
Values in this register enable or disable the open drain capability of the data pins. Figure 22-22 and
Table 22-19 describe this register.
Figure 22-22. GIO Open Drain Registers (GIOPDR[A-B]) [offset = 48h, 68h]
31
16
Reserved
R-0
15
8
7
0
Reserved
GIOPDR[7:0]
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22-19. GIO Open Drain Registers (GIOPDR[A-B]) Field Descriptions
Bit
Field
31-8
Reserved
7-0
GIOPDR[n]
Value
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0
Description
Reads return 0. Writes have no effect.
GIO open drain for port n, pins[7:0]
0
The GIO pin is configured in push/pull (normal GIO) mode. The output voltage is V
GIODOUT bit = 0 and V OH or higher if GIODOUT bit = 1.
1
The GIO pin is configured in open drain mode. The GIODOUTx bit controls the state of the GIO
output buffer: GIODOUTx = 0, the GIO output buffer is driven low; GIODOUTx = 1, the GIO output
buffer is tristated.
OL
or lower if
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22.5.17 GIO Pull Disable Registers (GIOPULDIS[A-B])
Values in this register enable or disable the pull control capability of the pins. Figure 22-23 and Table 2220 describe this register.
Figure 22-23. GIO Pull Disable Registers (GIOPULDIS[A-B]) [offset = 4Ch, 6Ch]
31
16
Reserved
R-0
15
8
7
0
Reserved
GIOPULDIS[7:0]
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22-20. GIO Pull Disable Registers (GIOPULDIS[A-B]) Field Descriptions
Bit
Field
31-8
Reserved
7-0
GIOPULDIS[n]
Value
0
Description
Reads return 0. Writes have no effect.
GIO pull disable for port n, pins[7:0]. Writes to this bit will only take effect when the GIO pin
configured as an input pin.
0
The pull functionality is enabled.
1
The pull functionality is disabled.
Note: The GIO pin is placed in input mode by clearing the GIODIRx bit to 0.
22.5.18 GIO Pull Select Registers (GIOPSL[A-B])
Values in this register select the pull up or pull down functionality of the pins. Figure 22-24 and Table 2221 describe this register.
Figure 22-24. GIO Pull Select Registers (GIOPSL[A-B]) [offset = 50h, 70h]
31
16
Reserved
R-0
15
8
7
0
Reserved
GIOPSL[7:0]
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22-21. GIO Pull Select Registers (GIOPSL[A-B]) Field Descriptions
Bit
Field
31-8
Reserved
7-0
GIOPSL[n]
Value
0
Description
Reads return 0. Writes have no effect.
GIO pull select for port n, pins[7:0]
0
The pull down functionality is select, when pull up/pull down logic is enabled.
1
The pull up functionality is select, when pull up/pull down logic is enabled.
Note: The pull up/pull down functionality is enabled by clearing corresponding bit in
GIOPULDIS to 0.
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22.6 I/O Control Summary
The behavior of the output buffer and the pull control is summarized in Table 22-22.
Table 22-22. Output Buffer and Pull Control Behavior for GIO Pins
(1)
(2)
(3)
(4)
(5)
(6)
Module under
Reset?
Pin Direction
(GIODIR) (1) (2)
Open Drain
Enable
(GIOPDR) (1) (3)
Pull Disable
(GIOPULDIS) (1) (4)
Pull Select
(GIOPSL) (1) (5)
Yes
X
X
X
No
0
X
0
No
0
X
No
0
No
0
No
No
Pull Control
Output Buffer (6)
X
Enabled
Disabled
0
Pull down
Disabled
0
1
Pull up
Disabled
X
1
0
Disabled
Disabled
X
1
1
Disabled
Disabled
1
0
X
X
Disabled
Enabled
1
1
X
X
Disabled
Enabled
X = Don't care
GIODIR = 0 for input; = 1 for output
See Section 22.5.16
GIOPULDIS = 0 for enabling pull control; = 1 for disabling pull control
GIOPSL= 0 for pull-down functionality; = 1 for pull-up functionality
If open drain is enabled, output buffer will be disabled if a high level (1) is being output.
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Chapter 23
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FlexRay Module
This chapter provides the specification for TI’s FlexRay module and its features from the application
programmer’s point of view.
Topic
...........................................................................................................................
23.1
23.2
23.3
23.4
23.5
23.6
23.7
23.8
23.9
23.10
23.11
23.12
23.13
23.14
23.15
23.16
23.17
23.18
23.19
23.20
23.21
23.22
1048
Overview........................................................................................................
FlexRay Module Block Diagram ........................................................................
FlexRay Module Block Mapping ........................................................................
Transfer Unit Block Diagram ............................................................................
Transfer Unit Functional Description .................................................................
Communication Cycle .....................................................................................
Communication Modes ....................................................................................
Clock Synchronization.....................................................................................
Error Handling ................................................................................................
Communication Controller States ....................................................................
Network Management .....................................................................................
Filtering and Masking .....................................................................................
Transmit Process ..........................................................................................
Receive Process ............................................................................................
FIFO Function ...............................................................................................
Message Handling .........................................................................................
Module RAMs ................................................................................................
Interrupts ......................................................................................................
FlexRay Module Registers ..............................................................................
Minimum Peripheral Clock Frequency .............................................................
Assignment of FlexRay Configuration Parameters ............................................
Emulation/Debug Support ..............................................................................
FlexRay Module
Page
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1050
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1054
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1069
1081
1081
1083
1085
1086
1088
1095
1103
1108
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1243
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23.1 Overview
The FlexRay module performs communication according to the FlexRay protocol specification v2.1
Rev. A. The sample clock bit rate can be programmed to values up to 10 Mbit/s. Additional bus driver (BD)
hardware is required for connection to the physical layer.
For communication on a FlexRay network, individual message buffers with up to 254 data bytes are
configurable. The message storage consists of a single-ported message RAM that holds up to 128
message buffers. All functions concerning the handling of messages are implemented in the message
handler. Those functions are the acceptance filtering, the transfer of messages between the two FlexRay
Channel Protocol Controllers and the message RAM, maintaining the transmission schedule as well as
providing message status information.
The register set of the FlexRay module can be accessed directly by the CPU via the VBUS interface.
These registers are used to control, configure and monitor the FlexRay channel protocol controllers,
message handler, global time unit, system universal control, frame and symbol processing, network
management, interrupt control, and to access the message RAM via the input / output buffer.
23.1.1 Feature List
•
•
•
•
•
•
•
•
•
•
•
•
Conformance with FlexRay protocol specification v2.1 Rev. A
Data rates of up to 10 Mbit/s on each channel
Up to 128 message buffers
8 Kbyte of message RAM for storage of, for example, 128 message buffers with maximum of 48-byte
data section or up to 30 message buffers with 254-byte data section
Configuration of message buffers with different payload lengths
One configurable receive FIFO
Each message buffer can be configured as receive buffer, as transmit buffer or as part of the receive
FIFO
CPU access to message buffers via input and output buffer
Specialized DMA like FlexRay Transfer Unit (FTU) for automatic data transfer between data memory
and message buffers without CPU interaction
Filtering for slot counter, cycle counter, and channel
Maskable module interrupts
Supports Network Management
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FlexRay Module Block Diagram
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23.2 FlexRay Module Block Diagram
Figure 23-1. Block Diagram
FlexRay Module
Rx_A
Tx_A
PRT A
TBF A
Physical
Layer Control
GTU
Rx_B
Tx_B
PRT B
TBF B
SUC
Transfer Unit
Statemachine
FSP
IBF
Message Handler
NEM
OBF
Direct
Access
INT
VBUS IF
(Slave)
uC
Peripheral
Bus
VBUS IF
(Master)
FTU
Message RAM
BCLK
SCLK
VBUSCLK
80MHz
Interrupts
The TI FlexRay module contains the following blocks:
• Peripheral Interface (VBUS IF)
Interface to the Peripheral Bus of the TMS570 microcontroller architecture. The FlexRay module can
either act as a VBUS master or VBUS slave.
• FlexRay Transfer Unit (FTU)
NOTE: Since the FlexRay module is accessed through the FTU, the FTU must be powered up by
the corresponding bit in the Peripheral Power Down Registers of the System Module before
accessing any FlexRay module register. For details, refer to the Architecture chapter and the
device-specific data manual.
•
1050
The internal intelligent state-machine (Transfer Unit State Machine) is able to transfer data between
the input buffer (IBF) and output buffer (OBF) of the communication controller and the system memory
without CPU interaction.
Input Buffer (IBF)
For write access to the message buffers configured in the message RAM, the CPU or the FTU can
write the header and data section for a specific message buffer to the input buffer. The message
handler then transfers the data from the input buffer to the selected message buffer in the message
RAM.
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•
•
•
•
•
•
Output Buffer (OBF)
For read access to a message buffer configured in the message RAM the message handler transfers
the selected message buffer to the output buffer. After the transfer has completed, the CPU or the FTU
can read the header and data section of the transferred message buffer from the output buffer.
Message Handler (MHD)
The message handler controls data transfers between the following components:
– Input / output buffer and message RAM
– Transient buffer RAMs of the two FlexRay protocol controllers and message RAM
Message RAM
The message RAM stores up to 128 FlexRay message buffers together with the related configuration
data (header and data partition).
The Transient Buffer RAM (TBF A/B):
Stores the data section of two complete messages.
FlexRay Channel Protocol Controller (PRT A/B)
The FlexRay channel protocol controllers consist of a shift register and the FlexRay protocol FSM
(Finite State Machine). They are connected to the transient buffer RAMs for intermediate message
storage and to the physical layer via bus drivers (BD).
They perform the following functionality:
– Control and check of bit timing
– Reception / transmission of FlexRay frames and symbols
– Check of header CRC
– Generation / check of frame CRC
– Interfacing to bus driver
The FlexRay channel protocol controllers have interfaces to:
– Physical layer (bus driver)
– Transient buffer RAM
– Message handler
– Global Time Unit
– System universal control
– Frame and symbol processing
– Network management
– Interrupt control
Global time unit (GTU)
The GTU performs the following functions:
– Generation of microtick
– Generation of macrotick
– Fault tolerant clock synchronization by FTM algorithm
• rate and offset correction
• offset correction
– Cycle counter
– Timing control of static segment
– Timing control of dynamic segment (minislotting)
– Support of external clock correction
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•
•
•
•
•
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System Universal Control (SUC)
The SUC controls the following functions:
– Configuration
– Wakeup
– Startup
– Normal Operation
– Passive Operation
– Monitor Mode
Frame and Symbol Processing (FSP)
The frame and symbol processing controls the following functions:
– Checks the correct timing of frames and symbols
– Tests the syntactical and semantic correctness of received frames
– Sets the slot status flags
Network Management (NEM)
Handles the network management vector.
Interrupt Control (INT)
The interrupt controller performs the following functions:
– Provides error and status interrupt flags
– Enable / disable interrupt sources
– Assignment of interrupt sources to the two module interrupt lines
– Enable / disable module interrupt lines
– Manages the two interrupt timers
– Stop watch time capturing
80MHz Clock Signal
NOTE: VCLKA2 is used to provide the 80-MHz clock to the FlexRay Module. The second PLL /
Clock Source 6 in the microcontroller is typically used as source for VCLKA2.
•
1052
Clock signal for the sample clock (SCLK) of the FlexRay module.
Module Clock (VBUSCLK)
The FlexRay module clock (BCLK) is derived from the Peripheral Clock VBUSCLK of the microcontroller.
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23.3 FlexRay Module Block Mapping
Figure 23-2 shows the different module blocks of the FlexRay module. It is split into 3 sections, the
communication controller, the transfer unit and the transfer unit RAM. The RAM of the communication
controller is only memory mapped in test mode, where it is mapped to the register set address range.
Figure 23-2. FlexRay Module Blocks
FlexRay Module
Communication
Controller
offset_TU_RAM
Transfer Unit
RAM
base_TU_RAM
offset_TU
offset_CC
Register Set
Register Set
base_TU
base_CC
The address ranges of the three FlexRay blocks are shown in Table 23-1.
Table 23-1. FlexRay Address Range Table
Module
Address Range
FlexRay Communication Controller
0xFFF7_C800 - 0xFFF7_CFFF
FlexRay TU
0xFFF7_A000 - 0xFFF7_A1FF
FlexRay TU RAM
0xFF50_0000 - 0xFF51_FFFF
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23.4 Transfer Unit Block Diagram
Figure 23-3. Transfer Unit
Transfer Unit
Peripheral Bus
VBUSP
Slave
Interface
VBUSP
Master
Interface
FlexRay
Input Buffer
(IBF)
FlexRay
Output Buffer
(OBF)
Interface
Arbiter
FlexRay
Message
Handler
Transfer
Unit
State
Machine
Transfer
Configuration
RAM (TCR)
Transfer Unit Interrupts
The FlexRay Transfer Unit (FTU) has an internal intelligent state-machine (Transfer Unit State Machine) to
transfer data between the Input and Output Buffer Interfaces of the FlexRay core module and the system
memory of the microcontroller without CPU interaction. It operates in a similar manner to a DMA (Direct
Memory Access) module.
The FlexRay Input Buffer (IBF) and FlexRay Output Buffer (OBF) can also be accessed directly by the
CPU. In this case the IBF and OBF are 8-, 16-, and 32-bit accessible. For transfers using the Transfer Unit
State Machine only 4x32-bit data packages (4 word bursts) are supported.
The Interface Arbiter controls the access to the IBF and OBF. Direct CPU accesses to IBF and OBF are
not possible, if the Transfer Unit State Machine is switched on. Accesses will be ignored and the
associated error interrupt will be generated.
The Transfer Unit State Machine is the head of all manual, event driven and automatic message transfer
activities. It controls the Transfer Unit interrupt generation related to transfer protocol correctness, status
and violations of the message transfers.
With the Transfer Configuration RAM (TCR) the transfer sequence, executed by the Transfer Unit State
Machine, can be configured.
The usage of the Transfer Unit allows the user to setup a mirror of the FlexRay message RAM in the fast
accessible data RAM of the microcontroller. The Transfer Unit can handle the data transfers between the
data RAM and the FlexRay message RAM in the ‘background’ without CPU interaction.
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Transfer Unit Functional Description
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23.5 Transfer Unit Functional Description
Figure 23-4 shows the principle of the Transfer Unit operation.
Figure 23-4. FlexRay Transfer Unit Operation Principle
Data RAM
FTU
Transfer Base
Address (TBA)
Transfer
Configuration RAM
FlexRay
Message RAM
TCR 1
Message Buffer 1
TCR 2
Message Buffer 2
TCR 3
Message Buffer 3
TCR 4
Message Buffer 4
TCR 128
Message Buffer 128
14 bit offset
+
Header / Data
Message Buffer 4
Each FlexRay message buffer of the FlexRay message buffer RAM has one Transfer Configuration RAM
(TCR) entry assigned to it, that is, message buffer 1 is assigned to TCR1, message buffer 2 is assigned to
TCR2, and so on.
The Transfer Base Address (TBA) register of the Transfer Unit holds the message buffer base address in
the data RAM. Each Transfer Configuration RAM (TCR) entry contains a 14 bit offset value to the
dedicated message buffer area in the data RAM.
The following two diagrams show the principle of the Transfer Unit operation including Transfer State
Machine (see Figure 23-5) and Event State Machine (see Figure 23-6).
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Figure 23-5. FlexRay Transfer Unit Operation Principle for Transfer FSM (simplified)
Module reset active
or FTU disabled
(GCS.TUE=0)
IDLE
Wait for FTU being enabled
(GCS.TUE=1, GCS.TUH=0)
FTU disabled
(GCS.TUE=0)
1056
CHECK
Find lowest bit set in TTSM and TTCC
which corresponds to the next message
buffer to be transferred
SETUP
Set up FTU transfer of the message buffer
with help of configuration in Transfer
Configuration RAM (TCR)
XFER
4 word burst by 4 word burst transfer of
message buffer to System Memory (SM)
or to Communication Controller (CC)
STATUS
Reset bit in TTSM or TTCC which
corresponds to the transferred message
buffer and generate status information
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Figure 23-6. FlexRay Transfer Unit Operation Principle for Event FSM (simplified)
Event FSM
Module reset active
or FTU disabled
(GCS.TUE=0)
IDLE
Wait for FTU being enabled
(GCS.TUE=1)
WAIT
Wait for event signaled from
E-Ray that a message buffer
has been updated
FTU disabled
(GCS.TUE=0)
UPDATE
Set up FTU transfer of the message buffer
with help of configuration in Transfer
Configuration RAM (TCR)
ETESMS/R CESMS/R
0
1
1
0
1
Set bit
TTSM
Clear bit
ETESMS/R
False
True
True
False
False
True
23.5.1 Transfer Control
23.5.1.1 Transfer Start and Halt
The Transfer Unit State Machine can be halted, effectively stopping the Transfer Unit transfer sequence
(after completion of the current 4 word burst transfer cycle). After releasing from halt state, the Transfer
Unit resumes exactly, where it was halted without data loss.
NOTE: It is the software’s responsibility to ensure data coherency when the FlexRay module
continues to receive data, but the Transfer Unit doesn't transfer it.
23.5.1.2 Transfer Abort
A Transfer Unit transfer will be aborted and the Transfer Unit will be disabled automatically in case of:
• a parity error while accessing the Transfer Configuration RAM (TCR)
• a memory protection error while accessing the data RAM of the microcontroller. In this case, the
ongoing transfer is aborted but the TUE bit in GCS/R may not get reset. User shall clear the TUE bit
manually by software.
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23.5.1.3 Transfer Reset
The Transfer Unit State Machine can be reset by the Transfer Unit Enable (TUE) bit in the Global Control
register. Though the Transfer Unit State Machine can be reset with the above, the module register
contents and the Transfer Configuration RAM (TCR). So, after re-enabling the Transfer Unit no
reconfiguration of the Transfer Unit is required.
23.5.1.4 Transfer Modes
Possible transfer sequence modes are:
• Manual by triggering the desired transfer by setting the corresponding bit in the Trigger Transfer to
System Memory (TTSM) register or the Trigger Transfer to Communication Controller (TTCC) register
• Event-Driven (transfers from FlexRay Communication Controller to the System Memory only) using the
Enable Transfer on Event to System Memory (ETESM) register.
• Single or continuous event driven transfers by using the Clear on Event to System Memory (CESM)
The transfer event trigger in general occurs upon completion of a reception or transmission of a frame
through the FlexRay bus. Table 23-2 shows more details: Conditions marked with 'X' per row must match
to trigger a FTU transfer event as configured in the Transfer Configuration RAM (TCR):
Table 23-2. FlexRay Transfer Unit Event Trigger Conditions
Event on
Channel
A
Event on
Channel
B
X
FTU Event Trigger
for Receive
Message Buffers
Frame belonging
to dynamic
segment, except
first slot of
dynamic segment
Bus activity
detected on
Channel A
(MBS.ESA = 0)
X
X
Bus activity
detected on
Channel B
(MBS.ESB = 0)
X
X
X
X
FTU Event Trigger
for Transmit
Message Buffers
Frame belonging
to static segment
or first slot of
dynamic segment
X
X
X
X
X
X
X
NOTE: By setting the corresponding bit in the Enable Transfer on Event to System Memory
(ETESM) register prior to an on-demand transfer to the Communication Controller by way of
the Trigger Transfer to Communication Controller (TTCC) register, an event-triggered
transmission back to the System Memory can be initiated, once the buffer has been sent out
on the FlexRay bus. This mechanism can be used, for instance, to automatically read back
the header status information to the system memory after a transmission occurred.
The transmission or reception of null frames in the static segment of a FlexRay
communication cycle triggers transfers of the transfer unit. The header and/or payload is
transferred to the system memory, if the corresponding bits THTSM and/or TPTSM in the
Transfer Configuration RAM (TCR) are set. If neither THTSM nor TPTSM bit is set in TCR,
neither header nor payload gets transferred. The corresponding bit in the Transfer to System
Memory Occurred register (TSMO) gets set in all cases.
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23.5.1.5 Transfer Size and Types
The data transferred by the Transfer Unit can be selected as:
• data and header section
• header section only
• data section only
The number of transferred payload words is derived from the Payload Length Configured (PLC)
information configured in the Write Header Section 2 (WRHS2) register.
As only 4 word bursts are supported for the Transfer Unit transfers, only multiple of 4x32-bit data packets
are supported. Additional transferred words are undefined, as indicated in Figure 23-7 and Figure 23-8.
Figure 23-7. Example: FTU Read Transfer of 6 Words
Output Buffer
Registers
word x
word x
word x+1
word x+1
word x+1
word x+2
internal E-Ray
Transfer
word x+2
word x+3
word x+3
word x+4
word x+5
word x+4
word x+5
word x+2
FTU Transfer
word x+3
word x+4
word x+5
word x+6
undefined x
undefined x
word x+7
undefined x+1
undefined x+2
undefined x+1
undefined x+2
4 word burst
Data RAM
word x
4 word burst
Message RAM
Figure 23-8. Example: FTU Write Transfer of 6 Words
Input Buffer
Registers
word x
word x+1
word x+2
word x+4
word x+5
undefined x
undefined x+1
undefined x+2
FTU Transfer
4 word burst
word x+3
4 word burst
Data RAM
Message Ram
word x
word x
word x+1
word x+1
word x+2
internal E-Ray
Transfer
word x+2
word x+3
word x+3
word x+4
word x+5
word x+4
word x+5
undefined x
undefined x+1
undefined x+2
Physically the FTU continues reading the additional words from the source location it started the burst
transfer. Therefore, on reads, the additional transferred words depend on the contents of the
Communication Controller Output Buffer Registers as indicated in Figure 23-7. On writes the additional
words depend on the contents of the data RAM, as shown in Figure 23-8. The additional data will be
written to the Communication Controller's Input Buffer Registers, but not transferred to the message RAM.
NOTE: It should be ensured that the allocated data RAM space for FTU transfers ends on 4x32 bit
boundary to avoid possible data overwrites or memory protection issues on FTU reads and
avoid reading the additional data from the source location on FTU writes.
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23.5.1.6 Transfer Status Indication
There are 3 registers indicating the transfer status:
• Transfer Status Current Buffer (TSCB) shows the current transfer buffer status
• Last Transferred Buffer to Communication Controller (LTBCC) indicates the last completed buffer
transfer to the communication controller
• Last Transferred Buffer to System Memory (LTBSM) shows the last completed buffer transfer to
system memory
23.5.1.7 Transfer Mirror Function
In order to efficiently access the transfer unit status registers in the system memory, the following registers
can be mirrored to the system memory starting at the base address defined in the Base Address of
Mirrored Status (BAMS) register:
• Transfer Status Current Buffer (TSCB)
• Last Transferred Buffer to Communication Controller (LTBCC)
• Last Transferred Buffer to System Memory (LTBSM)
• Transfer to System Memory Occurred 1/2/3/4 (TSMO1-4)
• Transfer to Communication Controller Occurred 1/2/3/4 (TCCO1-4)
• Transfer Occurred OFFset (TOOFF)
The mirrored values are updated after completion of a buffer transfer.
The mirroring of these registers can be disabled if not needed.
Table 23-3. Mirroring Address Mapping
Address
Register
BAMS+0x00
TSCB
BAMS+0x04
LTBCC
BAMS+0x08
LTBSM
BAMS+0x0C
TSMO1
BAMS+0x10
TSMO2
BAMS+0x14
TSMO3
BAMS+0x18
TSMO4
BAMS+0x1C
TCCO1
BAMS+0x20
TCCO2
BAMS+0x24
TCCO3
BAMS+0x28
TCCO4
BAMS+0x2C
TOOFF
23.5.1.8 Endianness Correction
For the data transfer by the Transfer Unit an Endianness correction mechanism can be used to switch big
Endianness data to little Endianness data and vice versa.
For maximum flexibility, 6 bits are available in the Global Control Set/Reset Register (GCS/R) to control.
• Header Data byte-order
• Payload Data byte-order
• Byte-order of the FlexRay Core registers and the Transfer Configuration RAM data of the Transfer Unit
independently and in both directions.
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23.5.1.9 Transfer Data Package
Table 23-4 shows the data of a transfer data package. Independent of whether the header gets
transferred or not, the buffer address always points to element Header1.
Table 23-4. Mirroring Address Mapping
Address
Register
0x0000
Header1
0x0004
Header2
0x0008
Header3
0x000C
Buffer Status (1)
0x0010
Payload1
0x0014
Payload2
:
:
0x010C
(1)
Payload64
Transferred only from Communication Controller to System Memory
23.5.1.10 Transfer Start Address to Message Buffer Number Assignment
The assignment of a FlexRay message buffer number to the transfer location in system memory is done
by the combination of
• the Transfer Start Offset (TSO) field in a Transfer Configuration RAM (TCR) entry
• the Transfer Base Address (TBA) register
Each entry of the TCR holds a 14 bit offset value (TSO). The TSO offset will be added to the content of
the TBA register. The TBA register holds the 32bit base address-pointer to a location of the data RAM.
A value written to Next Transfer Base Address (NTBA) will be loaded in the TBA at the next
communication cycle start. This allows efficient multi-buffering of the message buffers in the system
memory. The Transfer Not Ready (NTR) flag in the Transfer Error Interrupt Flag (TEIF) register can be
used to determine, if NTBA can be reloaded by the CPU.
NOTE: If a value is written to TBA, NTBA is set to the same value.
Figure 23-9. Transfer Start Address to Message Buffer Number Assignment
communication
cycle start
Buffer Addr
=
TBA
NTBA
+
TSO
23.5.1.11 Transfer Priority
The Transfer Unit will transfer the message buffers from low to high message buffer numbers.
In case the same buffer is pending in both the Trigger Transfer to Communication (TTCC) register and the
Trigger Transfer to System Memory (TTSM) register, the priority between TTCC and TTSM is determined
by the Transfer Priority bit (GC.PRIO) in the Transfer Unit Global Control Set/Reset Register (GCS/R).
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23.5.1.12 Read Transfers
A read transfer is the data transfer from FlexRay message buffer RAM to the system memory of the
microcontroller.
For read transfers, the registers Trigger Transfer to System Memory (TTSM), Enable Transfer on Event to
System Memory (ETESM), and Clear on Event to System Memory (CESM) have to be set up.
The amount and type of data to be transferred can be selected as:
• data and header section
• header section only
• data section only
that can be configured on the Transmit Configuration RAM (TCR).
The number of 32 bit words per buffer to be transferred is read from the Payload Length Configured
(RDHS2.PLC) configuration information. This information is part of the header section stored in the
message RAM of the Communication Controller.
23.5.1.13 Write Transfers
A write transfer is the data transfer from the system memory of the microcontroller to the FlexRay
message buffer RAM.
For write transfers, the Trigger Transfer to Communication (TTCC) register has to be set up.
The amount and type of data transferred can be selected as:
• data and header section
• header section only
• data section only
that can be configured on the Transmit Configuration RAM (TCR).
It can be configured in the TCR, if Set Transmission Request Host (STXRH) bit in the Input Buffer
Command Mask (IBCM) of the Communication Controller should be set. This would trigger the transfer to
the FlexRay bus.
If a data and header section transfer is selected, the number of 32 bit words to be transferred is read from
the Payload Length Configured (PLC) configuration information stored in Header2 word in the system
memory.
If a data section only transfer is selected, the number of 32 bit words to be transferred is read from the
Payload Length Configured (RDHS2.PLC) configuration information. This information is part of the header
section stored in the message RAM of the Communication Controller.
23.5.1.14 Transfer Unit Event Interface
The Transfer Unit Event Control generates transfer trigger signals for transfers in the following cases:
• For transmit (TX) message buffers, a write transfer trigger is generated, if a transmit event occurs. The
configured TX message buffers generate a transfer trigger, except when a Nullframe in static segment
or no frame in the dynamic segment is sent.
• For receive (RX) message buffers, a read transfer trigger is generated, if a receive event occurs in the
static segment.
• For receive (RX) message buffers, a read transfer trigger is generated if a receive event occurs in the
dynamic segment, updated in the current cycle and no Nullframe.
If a buffer is part of the FIFO, no transfer trigger is generated!
When the Transfer Unit is disabled (TUE bit in Global Control Register (GCS/R) is 0), no transfer trigger is
generated, whereas if the Transfer Unit is enabled, but in halt mode (TUH bit and TUE bit in Global
Control Register (GCS/R) are 1), the occurring triggers remain pending and get executed when the
Transfer Unit will be resumed from halt mode.
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23.5.2 Transfer Configuration RAM
The Transfer Configuration RAM (TCR) consists of 128 entries, one entry for each possible FlexRay
buffer. Entry 1 is assigned to FlexRay buffer 1, entry 2 to FlexRay buffer 2,..., and entry 128 is assigned to
FlexRay buffer 128.
Each TCR entry defines:
• data transfer size (header + data, header only or data only)
• whether the transmit request flag (STRXH) should be set for the data transferred by the FTU to the CC
to send out the data to the FlexRay bus.
• the 14-bit buffer address offset, which, in combination with the Transfer Base Address defined in TBA,
specifies the start of the corresponding FlexRay message buffer in the system memory RAM.
NOTE: It is recommended to clear the whole TCR before configuring it, in order to avoid unexpected
transfer behavior due to old configuration contents or random TCR RAM contents after
power on reset.
If a transfer is triggered but no transfer size (header or data) is setup in the TCR, no data will
be transferred, but the corresponding flag in the Transfer to Communication Controller
Occurred (TCCOx) or the Transfer to System Memory Occurred (TSMOx) will be set.
23.5.2.1 Parity Protection
The Transfer Configuration RAM (TCR) is parity protected. The parity error interrupt generation is disabled
by default and can be switched on by writing a 4 bit key to dedicated parity lock bits in the Global Control
Set/Reset Register (GCS/R).
The parity protection supports even and odd parity. The parity information is stored together with the
corresponding 19 bit data word entry.
The parity is checked each time a data word is read from the TCR RAM. If a parity error is detected, the
PE error flag is set in the Transfer Error Interrupt Flag (TEIF) register.
Additionally an uncorrectable RAM error interrupt/event will be generated. The uncorrectable RAM error
interrupt/event is non maskable and therefore cannot be switched off. The uncorrectable RAM error is
hooked up to the ESM module (event).
For parity errors the faulty TCR RAM address can be read from the Parity Error Address (PEADR)
register.
23.5.3 Memory Protection Mechanism
This feature allows to restrict accesses to certain areas in memory in order to protect critical application
data from unintentionally being accessed by the Transfer Unit State Machine.
One memory section (start- and end address) can be defined, which allows read and write accesses for
the Transfer Unit State Machine.
If the end address is smaller or equal to the start address, data transfers will be blocked. Any accesses
performed outside this memory area by the Transfer Unit State Machine result in no transfers being
performed. In case of a protection violation a flag will be set and the Memory Protection Violation interrupt
will be activated. The Transfer Unit State Machine will be disabled in this case.
The default setting of the Transfer Unit State Machine memory protection address range setup is:
• 0x00000000 for start address
• 0x00000000 for end address
This means a valid address range must be setup, before the Transfer Unit can be used.
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23.6 Communication Cycle
Figure 23-10. Structure of Communication Cycle
Time base
derived trigger
Time base
derived trigger
t
Static segment
Communication
cycle x-1
A
•
•
•
•
Dynamic segment
Symbol
window
NIT
Communication cycle x
Dynamic
Static segment segment
Communication
cycle x+1
communication cycle in FlexRay consists of the following elements:
Static segment
Dynamic segment
Symbol window
Network idle time (NIT)
Static segment, dynamic segment, and symbol window form the network communication time (NCT). For
each communication channel the slot counter starts at 1 and counts up until the end of the dynamic
segment is reached. Both channels share the same arbitration grid which means that they use the same
synchronized macrotick.
23.6.1 Static Segment
The Static Segment is characterized by the following features:
• Time slots of fixed length (optionally protected by bus guardian)
• Start of frame transmission at action point of the corresponding static slot
• Payload length same for all frames on both channels
Parameters: number of static slots GTUC7.NSS, static slot length GTUC7.SSL, Payload Length Static
MHDC.SFDL, action point offset GTUC9.APO
23.6.2 Dynamic Segment
The Dynamic Segment is characterized by the following features:
• All controllers have bus access (no bus guardian protection possible)
• Variable payload length and duration of slots, different for both channels
• Start of transmission at minislot action point
Parameters: number of minislots GTUC8.NMS, minislot length GTUC8.MSL, minislot action point offset
GTUC9.MAPO, start of latest transmit (last minislot) MHDC.SLT
23.6.3 Symbol Window
During the symbol window only one media access test symbol (MTS) may be transmitted per channel.
MTS symbols are sent in NORMAL_ACTIVE state to test the bus guardian.
The symbol window is characterized by the following features:
• Send single symbol
• Transmission of the MTS symbol starts at the symbol windows action point
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Parameters: Symbol Window Action Point Offset GTUC9.APO (same as for static slots), Network Idle
Time Start GTUC4.NIT
23.6.4 Network Idle Time (NIT)
During network idle time the communication controller has to perform the following tasks:
• Calculate clock correction terms (offset and rate)
• Distribute offset correction over multiple macroticks after offset correction start
• Perform cluster cycle related tasks
Parameters: network idle time start GTUC4.NIT, offset correction start GTUC4.OCS
23.6.5 Configuration of NIT Start and Offset Correction Start
Figure 23-11. Configuration of NIT Start and Offset Correction Start
n
0
n+1
k
m+1
k+1
GTUC2.MPC = m
GTUC4.NIT = k
GTUC4.OCS = NIT+1
Static / Dynamic Segment
Symbol Window
NIT
The number of macroticks per cycle is assumed to be m. It is configured by programming GTUC2.MPC =
m in the GTU Configuration register 2.
The static / dynamic segment starts with macrotick 0 and ends with macrotick n: n = static segment length
+ dynamic segment offset + dynamic segment length - 1MT
The static segment length is configured by GTUC7.SSL and GTUC7.NSS. The dynamic segment length is
configured by GTUC8.MSL and GTUC8.NMS.
The dynamic segment offset is ActionPointOffset - MinislotActionPointOffset or 0 MT if the result is
negative. For details, refer to the FlexRay Communications System Protocol Specification from the
FlexRay Consortium.
The NIT starts with macrotick k+1 and ends with the last macrotick of cycle m-1. It has to be configured by
setting GTUC4.NIT = k.
For this FlexRay module, the offset correction start is required to be:
GTUC4.OCS >= GTUC4.NIT + 1 = k+1.
The length of symbol window results from the number of macroticks between the end of the static /
dynamic segment and the beginning of the NIT. It can be calculated by k - n.
23.7 Communication Modes
The FlexRay protocol specification v2.1 Rev. A defines the Time-Triggered Distributed (TT-D) mode.
23.7.1 Time-Triggered Distributed (TT-D)
In TT-D mode the following configurations are possible:
• Pure static: minimum 2 static slots + symbol window (optional)
• Mixed static/dynamic: minimum 2 static slots + dynamic segment + symbol window (optional)
A minimum of two coldstart nodes need to be configured for distributed time-triggered operation. Two
fault-free coldstart nodes are necessary for the cluster startup. Each startup frame must be a sync frame,
therefore all coldstart nodes are sync nodes.
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23.8 Clock Synchronization
In TT-D mode a distributed clock synchronization is used. Each node individually synchronizes itself to the
cluster by observing the timing of received sync frames from other nodes.
23.8.1 Global Time
Activities in a FlexRay node, including communication, are based on the concept of a global time, even
though each individual node maintains its own view of it. It is the clock synchronization mechanism that
differentiates the FlexRay cluster from other node collections with independent clock mechanisms. The
global time is a vector of two values; the cycle (cycle counter) and the cycle time (macrotick counter).
Cluster specific:
• Macrotick (MT) = basic unit of time measurement in a FlexRay network, a macrotick consists of an
integer number of microticks (μT)
• Cycle length = duration of a communication cycle in units of macroticks (MT)
23.8.2 Local Time
Internally, nodes time their behavior with microtick resolution. Microticks are time units derived from the
oscillator clock tick of the specific node. Therefore microticks are controller-specific units. They may have
different duration in different controllers. The precision of a nodes local time difference measurements is a
microtick (μT).
Node specific:
• Sample clock -> prescaler -> microtick (µT); typically 25ns.
• μT = basic unit of time measurement in a communication controller, clock correction is done in units of
μTs
• Cycle counter + macrotick counter = nodes local view of the global time
23.8.3 Synchronization Process
Clock synchronization is performed by means of sync frames. Only preconfigured nodes (sync nodes) are
allowed to send sync frames. In a two-channel cluster, a sync node has to send its sync frame on both
channels.
For synchronization in FlexRay the following constraints have to be considered:
• Max. one sync frame per node in one communication cycle
• Max. 15 sync frames per cluster in one communication cycle
• Every node has to use a preconfigured number of sync frames (GTUC2.SNM) for clock
synchronization
• Minimum of two sync nodes required for clock synchronization and startup
For clock synchronization, the time difference between expected and observed arrival time of sync frames
received during the static segment is measured. In a two channel cluster, the sync node has to be
configured to send sync frames on both channels. The calculation of correction terms is done during NIT
(offset: every cycle, rate: odd cycle) by using a FTA / FTM algorithm. For details, see FlexRay protocol
specification v2.1 Rev. A.
23.8.3.1
•
•
•
•
•
•
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Offset (Phase) Correction
Only deviation values measured and stored in the current cycle used
For a two channel node the smaller value will be taken
Calculation during NIT of every communication cycle
Offset correction value calculated in even cycles used for error checking only
Checked against limit values
Correction value is a signed integer number of μTs
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•
23.8.3.2
•
•
•
•
•
•
•
Correction done in odd numbered cycles, distributed over the macroticks beginning at offset correction
start up to cycle end (end of NIT) to shift nodes next start of cycle (MTs lengthened / shortened)
Rate (Frequency) Correction
Pairs of deviation values measured and stored in even / odd cycle pair used
For a two channel node the average of the differences from the two channels is used
Calculated during NIT of odd numbered cycles
Cluster drift damping is performed using global damping value
Checked against limit values
Correction value is a signed integer number of μTs
Distributed over macroticks comprising the next even/odd cycle pair (MTs lengthened / shortened)
23.8.4 Sync Frame Transmission
Sync frame transmission is only possible from buffer 0 and 1. Message buffer 1 may be used for sync
frame transmission in case that sync frames should have different payloads on the two channels. In this
case bit MRC.SPLM has to be programmed to 1.
Message buffers used for sync frame transmission have to be configured with the key slot ID and can be
(re)configured in DEFAULT_CONFIG or CONFIG state only. For nodes transmitting sync frames
SUCC1.TXSY must be set to 1.
23.8.5 External Clock Synchronization
During normal operation, independent clusters can drift significantly. If synchronous operation across
independent clusters is desired, external synchronization is necessary; even though the nodes within each
cluster are synchronized. This can be accomplished with synchronous application of host-deduced rate
and offset correction terms to the clusters.
• External offset / rate correction value is a signed integer
• External offset / rate correction value is added to calculated offset / rate correction value
• Aggregated offset / rate correction term (external + internal) is not checked against configured limits
23.9 Error Handling
The implemented error handling concept of the FlexRay protocol is intended to ensure that in the
presence of a lower layer protocol error in a single node, communication between non-affected nodes can
be maintained. In some cases, higher layer program command activity is required for the communication
controller to resume normal operation. A change of the error handling state will set bit EIR.PEMC and can
trigger an interrupt to the host if enabled. The current error mode is signaled by CCEV.ERRM.
Table 23-5. Error Modes of the POC (Degradation Model)
Error Mode
Activity
ACTIVE
Full operation, State: NORMAL_ACTIVE
The communication controller is fully synchronized and supports the cluster wide clock synchronization. The
host is informed of any error condition(s) or status change by interrupt (if enabled) or by reading the error
and status flags from registers EIR and SIR.
PASSIVE
Reduced operation, State: NORMAL_PASSIVE, communication controller self rescue allowed
The communication controller stops transmitting frames and symbols, but received frames are still
processed. Clock synchronization mechanisms are continued based on received frames. No active
contribution to the cluster wide clock synchronization. The host is informed of any error condition(s) or status
change by interrupt (if enabled) or by reading the error and status flags from registers EIR and SIR.
COMM_HALT
Operation halted, State: HALT, communication controller self rescue not allowed
The communication controller stops frame and symbol processing, clock synchronization processing, and
the macrotick generation. The host has still access to error and status information by reading the error and
status flags from registers EIR and SIR. The bus drivers are disabled.
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23.9.1 Clock Correction Failed Counter
When the Clock Correction Failed Counter reaches the “maximum without clock correction passive” limit
defined by SUCC3.WCP, the POC transits from NORMAL_ACTIVE to NORMAL_PASSIVE state. When it
reaches the “maximum without clock correction fatal” limit defined by SUCC3.WCF, it transits
NORMAL_ACTIVE or NORMAL_PASSIVE to the HALT state.
The Clock Correction Failed Counter CCEV.CCFC allows the host to monitor the duration of the inability of
a node to compute clock correction terms after the communication controller passed protocol startup
phase. It will be incremented by one at the end of any odd numbered communication cycle where either
the Missing Offset Correction flag SFS.MOCS or the Missing Rate Correction flag SFS.MRCS is set.
The clock correction failed counter is reset to zero at the end of an odd communication cycle if neither the
Missing Offset Correction flag SFS.MOCS nor the Missing Rate Correction flag SFS.MRCS is set.
The Clock Correction Failed Counter stops incrementing when the “maximum without clock correction
fatal” value SUCC3.WCF is reached (that is, incrementing the counter at its maximum value will not cause
it to wraparound back to zero). The clock correction failed counter will be initialized to zero when the
communication controller enters READY state or when NORMAL_ACTIVE state is entered.
NOTE: The transition to HALT state is prevented if SUCC1.HCSE is not set.
23.9.2 Passive to Active Counter
The passive to active counter controls the transition of the POC from NORMAL_PASSIVE to
NORMAL_ACTIVE state. SUCC1.SUCC1.PTA defines the number of consecutive even / odd cycle pairs
that must have valid clock correction terms before the communication controller is allowed to transit from
NORMAL_PASSIVE to NORMAL_ACTIVE state. If SUCC1.PTA is set to zero the communication
controller is not allowed to transit from NORMAL_PASSIVE to NORMAL_ACTIVE state.
23.9.3 HALT Command
In case the host wants to stop FlexRay communication of the local node it can bring the communication
controller into HALT state by asserting the HALT command. This can be done by writing SUCC1.CMD =
0110. In order to shut down communication on an entire FlexRay network, a higher layer protocol is
required to assure that all nodes apply the HALT command at the same time.
The POC state from which the transition to HALT state took place can be read from CCSV.PSL.
When called in NORMAL_ACTIVE or NORMAL_PASSIVE state the POC transits to HALT state at the end
of the current cycle. When called in any other state SUCC1.CMD will be reset to 0000 =
“command_not_accepted” and bit EIR.CNA in the error interrupt register is set to 1. If enabled an interrupt
to the host is generated.
23.9.4 FREEZE Command
In case the host detects a severe error condition it can bring the communication controller into HALT state
by asserting the FREEZE command. This can be done by writing SUCC1.CMD = 0111. The FREEZE
command triggers the entry of the HALT state immediately regardless of the current POC state.
The POC state from which the transition to HALT state took place can be read from CCSV.PSL.
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23.10 Communication Controller States
23.10.1 Communication Controller State Diagram
Figure 23-12. Overall State Diagram of Communication Controller
HW Reset
Power On
T1
DEFAULT_
CONFIG
MONITOR
MODE
T2
T3
T4
T17
CONFIG
T5
T6
T16
T7
WAKEUP
T8
READY
T9
HALT
T14
T13
T15
T12
STARTUP
T10
NORMAL
ACTIVE
T11
NORMAL
PASSIVE
Transition triggered by host command
Transition triggered by internal conditions
Transition triggered by host command OR internal conditions
State transitions are controlled by the reset and FlexRay receive (rxd1, 2) pins, the POC state machine,
and by the CHI command vector SUCC1.CMD.
The Communication Controller exits from all states to HALT state after application of the FREEZE
command (SUCC1.CMD = 0111).
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Table 23-6. State Transitions of Communication Controller Overall State Machine
T#
Condition
From
To
1
Hardware reset
All States
DEFAULT_CONFIG
2
Command CONFIG, SUCC1.CMD = 0001
DEFAULT_CONFIG
CONFIG
3
Unlock sequence followed by command MONITOR_MODE,
SUCC1.CMD = 1011
CONFIG
MONITOR_MODE
4
Command CONFIG, SUCC1.CMD = 0001
MONITOR_MODE
CONFIG
5
Unlock sequence followed by command READY, SUCC1.CMD = 0010
CONFIG
READY
6
Command CONFIG, SUCC1.CMD = 0001
READY
CONFIG
7
Command WAKEUP, SUCC1.CMD = 0011
READY
WAKEUP
8
Complete, non-aborted transmission of wakeup pattern OR received
WUP OR received frame header OR command READY, SUCC1.CMD
= 0010
WAKEUP
READY
9
Command RUN, SUCC1.CMD = 0100
READY
STARTUP
10
Successful startup
STARTUP
NORMAL_ACTIVE
11
Clock correction failed counter reached “maximum without clock
correction passive” limit configured by SUCC3.WCP
NORMAL_ACTIVE
NORMAL_PASSIVE
12
Number of valid correction terms reached the Passive to Active limit
configured by SUCC1.PTA
NORMAL_PASSIVE
NORMAL_ACTIVE
13
Command READY, SUCC1.CMD = 0010
STARTUP,
NORMAL_ACTIVE,
NORMAL_PASSIVE
READY
14
Clock Correction Failed counter reached “maximum without clock
correction fatal” limit configured by SUCC3.WCF AND bit
SUCC1.HCSE set to 1 OR command HALT, SUCC1.CMD = 0110
NORMAL_ACTIVE
HALT
15
Clock Correction Failed counter reached “maximum without clock
correction fatal” limit configured by SUCC3.WCF AND bit
SUCC1.HCSE set to 1 OR command HALT, SUCC1.CMD = 0110
NORMAL_PASSIVE
HALT
16
Command FREEZE, SUCC1.CMD = 0111
All States
HALT
17
Command CONFIG, SUCC1.CMD = 0001
HALT
DEFAULT_CONFIG
23.10.2 DEFAULT_CONFIG State
In DEFAULT_CONFIG state, the communication controller is stopped. All configuration registers are
accessible and the pins to the physical layer are in their inactive state.
The communication controller enters this state:
• When leaving hardware reset
• When exiting from HALT state
To leave DEFAULT_CONFIG state the host has to write SUCC1.CMD = 0001. The communication
controller then transits to CONFIG state.
23.10.3 CONFIG State
In CONFIG state, the communication controller is stopped. All configuration registers are accessible and
the pins to the physical layer are in their inactive state. This state is used to initialize the communication
controller configuration.
The communication controller enters this state:
• When exiting from DEFAULT_CONFIG state
• When exiting from MONITOR_MODE or READY state
When the state has been entered by HALT and DEFAULT_CONFIG state, the host can analyze status
information and configuration. Before leaving CONFIG state the host has to assure that the configuration
is fault-free.
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To leave CONFIG state, the host has to perform the unlock sequence. Directly after unlocking the
CONFIG state the host has to write SUCC1.CMD to enter the next state.
NOTE: The message buffer status registers (MHDS, TXRQ[1-4], NDAT[1-4], MBSC[1-4]) and status
data stored in the message RAM and are not affected by the transition of the POC from
CONFIG to READY state.
When the communication controller is in CONFIG state it is also possible to bring the communication
controller into a power saving mode by halting the module clocks. To do this the host has to assure that all
Message RAM transfers have finished before turning off the clocks.
23.10.4 MONITOR_MODE
After unlocking CONFIG state and writing SUCC1.CMD = 1011 the communication controller enters
MONITOR_MODE. In this mode the communication controller is able to receive FlexRay frames and to
detect wakeup pattern. The temporal integrity of received frames is not checked, and therefore cycle
counter filtering is not supported. This mode can be used for debugging purposes in case e.g. that startup
of a FlexRay network fails. After writing SUCC1.CMD = 0001 the communication controller transits back to
CONFIG state.
In MONITOR_MODE the pick first valid mechanism is disabled. This means that a receive message buffer
may only be configured to receive on one channel. Received frames are stored into message buffers
according to frame ID and receive channel. Null frames are handled like data frames. After frame
reception only status bits MBS.VFRA, MBS.VFRB, MBS.MLST, MBS.RCIS, MBS.SFIS, MBS.SYNS,
MBS.NFIS, MBS.PPIS, MBS.RESS have valid values.
In MONITOR_MODE the communication controller is not able to distinguish between CAS and MTS
symbols. In case one of these symbols is received on one or both of the two channels, the flags
SIR.MTSA/SIR.MTSB are set. SIR.CAS has no function in MONITOR_MODE.
23.10.5 READY State
After unlocking CONFIG state and writing SUCC1.CMD = 0010 the communication controller enters
READY state. From this state the communication controller can transit to WAKEUP state and perform a
cluster wakeup or to STARTUP state to perform a coldstart or to integrate into a running cluster.
The communication controller enters this state:
• When exiting from CONFIG, WAKEUP, STARTUP, NORMAL_ACTIVE, or NORMAL_PASSIVE state
by writing SUCC1.CMD = 0010 (READY command).
The communication controller exits from this state:
• To CONFIG state by writing SUCC1.CMD = 0001 (CONFIG command)
• To WAKEUP state by writing SUCC1.CMD = 0011 (WAKEUP command)
• To STARTUP state by writing SUCC1.CMD = 0100 (RUN command)
Internal counters and the communication controller status flags are reset when the communication
controller enters STARTUP state.
NOTE: Status bits MHDS, registers TXRQ[1-4], and status data stored in the Message RAM are not
affected by the transition of the POC from READY to STARTUP state.
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23.10.6 WAKEUP State
The description below is intended to help configuring wakeup for the FlexRay module. A detailed
description of the wakeup procedure can be found in the FlexRay protocol specification v2.1 Rev. A.
The communication controller enters this state:
• When exiting from READY state by writing SUCC1.CMD = 0011 (WAKEUP command).
The communication controller exits from this state to READY state:
• After complete non-aborted transmission of wakeup pattern
• After WUP reception
• After detecting a WUP collision
• After reception of a frame header
• By writing SUCC1.CMD = 0010 (READY command)
The communication controller exits from this state to HALT state:
• By writing SUCC1.CMD = 0111 (FREEZE command)
The cluster wakeup must precede the communication startup in order to ensure that all nodes in a cluster
are awake. The minimum requirement for a cluster wakeup is that all bus drivers are supplied with power.
A bus driver has the ability to wake up the other components of its node when it receives a wakeup
pattern on its channel. At least one node in the cluster needs an external wakeup source.
The host completely controls the wakeup procedure. It is informed about the state of the cluster by the bus
driver and the communication controller and configures bus guardian (if available) and communication
controller to perform the cluster wakeup. The communication controller provides to the host the ability to
transmit a special wakeup pattern on each of its available channels separately. The communication
controller needs to recognize the wakeup pattern only during wakeup and startup phase.
Wakeup may be performed on only one channel at a time. The host has to configure the wakeup channel
while the communication controller is in CONFIG state by writing bit WUCS in the SUC configuration
register 1. The communication controller ensures that ongoing communication on this channel is not
disturbed. The communication controller cannot guarantee that all nodes connected to the configured
channel awake upon the transmission of the wakeup pattern, since these nodes cannot give feedback
until the startup phase. The wakeup procedure enables single-channel devices in a two-channel system to
trigger the wakeup, by only transmitting the wakeup pattern on the single channel to which they are
connected. Any coldstart node that deems a system startup necessary will then wake the remaining
channel before initiating communication startup.
The wakeup procedure tolerates any number of nodes simultaneously trying to wakeup a single channel
and resolves this situation such that only one node transmits the pattern. Additionally the wakeup pattern
is collision resilient, so even in the presence of a fault causing two nodes to simultaneously transmit a
wakeup pattern, the resulting collided signal can still wake the other nodes.
After wakeup the communication controller returns to READY state and signals the change of the wakeup
status to the host by setting bit SIR.WST in the status interrupt register. The wakeup status vector
CCSV.WSV can be read from the communication controller status vector register. If a valid wakeup
pattern was received also either bit SIR.WUPA or bit SIR.WUPB in the status interrupt register is set.
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Figure 23-13. Structure of POC State WAKEUP
READY
Tenter
Texit
WAKEUP
STANDBY
T1
T4
T6
T2
T3
WAKEUP
LISTEN
T5
WAKEUP
SEND
WAKEUP
DETECT
WAKEUP
Table 23-7. State Transitions WAKEUP
T#
Condition
From
To
enter
Host commands change to WAKEUP state by writing SUCC1.CMD =
0011 (WAKEUP command)
READY
WAKEUP
1
CHI command WAKEUP triggers wakeup FSM to transit to
WAKEUP_LISTEN state
WAKEUP_STANDBY
WAKEUP_LISTEN
2
Received WUP on wakeup channel selected by bit SUCC1.WUCS OR
frame header on either available channel
WAKEUP_LISTEN
WAKEUP_STANDBY
3
Timer event
WAKEUP_LISTEN
WAKEUP_SEND
4
Complete, non-aborted transmission of wakeup pattern
WAKEUP_SEND
WAKEUP_STANDBY
5
Collision detected
WAKEUP_SEND
WAKEUP_DETECT
6
Wakeup timer expired OR WUP detected on wakeup channel selected WAKEUP_DETECT
by bit SUCC1.WUCS OR frame header received on either available
channel
WAKEUP_STANDBY
exit
Wakeup completed (after T2 or T4 or T6) OR host commands change
to READY state by writing SUCC1.CMD = 0010 (READY command).
This command also resets the wakeup FSM to WAKEUP_STANDBY
state.
READY
WAKEUP
The WAKEUP_LISTEN state is controlled by the wakeup timer and the wakeup noise timer. The two
timers are controlled by the parameters Listen Timeout SUCC2.LT and Listen Timeout Noise SUCC2.LTN.
Listen timeout enables a fast cluster wakeup in case of a noise free environment, while listen timeout
noise enables wakeup under more difficult conditions regarding noise interference.
In WAKEUP_SEND state the communication controller transmits the wakeup pattern on the configured
channel and checks for collisions. After return from wakeup the host has to bring the communication
controller into STARTUP state by CHI command RUN.
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In WAKEUP_DETECT state the communication controller attempts to identify the reason for the wakeup
collision detected in WAKEUP_SEND state. The monitoring is bounded by the expiration of listen timeout
as configured by SUCC2.LT in the SUC configuration register 2. Either the detection of a wakeup pattern
indicating a wakeup attempt by another node or the reception of a frame header indication existing
communication, causes the direct transition to READY state. Otherwise WAKEUP_DETECT is left after
expiration of listen timeout; in this case the reason for wakeup collision is unknown.
The host has to be aware of possible failures of the wakeup and act accordingly. It is advisable to delay
any potential startup attempt of the node having instigated the wakeup by the minimal time it takes
another coldstart node to become awake and to be configured.
The FlexRay Protocol Specification recommends that two different communication controllers shall wake
the two channels.
23.10.6.1 Host Activities
The host must coordinate the wakeup of the two channels and must decide whether, or not, to wake a
specific channel. The sending of the wakeup pattern is initiated by the host. The wakeup pattern is
detected by the remote BDs and signaled to their local hosts.
Wakeup procedure controlled by host (single-channel wakeup):
• Configure the communication controller in CONFIG state
– Select wakeup channel by programming bit SUCC1.WUCS
• Check local BDs whether a WUP was received
• Activate BD of selected wakeup channel
• Command communication controller to enter READY state
• Command communication controller to start wakeup on the configured channel by writing SUCC1.CMD
= 0011
– communication controller enters WAKEUP_LISTEN
– communication controller returns to READY state and signals status of wakeup attempt to host
• Wait predefined time to allow the other nodes to wakeup and configure themselves
• Coldstart node:
– in dual channel cluster wait for WUP on the other channel
– Reset Coldstart Inhibit flag CCSV.CSI by writing SUCC1.CMD = 1001 (ALLOW_COLDSTART
command)
• Command communication controller to enter startup by writing SUCC1.CMD = 0100 (RUN command)
Wakeup procedure triggered by the bus driver:
• Wakeup recognized by bus driver
• bus driver triggers power-up of host (if required)
• bus driver signals wakeup event to host
• Host configures its local communication controller
• If necessary host commands wakeup of second channel and waits predefined time to allow the other
nodes to wakeup and configure themselves
• Host commands communication controller to enter STARTUP state by writing SUCC1.CMD = 0100
(RUN command)
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23.10.6.2 Wake Up Pattern (WUP)
The wake up pattern (WUP) is composed of at least two wakeup symbols (WUS). Wakeup symbol and
wakeup pattern are configured by the PRT configuration registers 1,2.
• Single channel wakeup, wake up symbol may not be sent on both channels at the same time
• Wakeup symbol collision resilient for up to two sending nodes (two overlapping wakeup symbols still
recognizable)
• Wakeup symbol must be configured identical in all nodes of a cluster
• Wakeup symbol transmit low time configured by PRTC2.TXL
• Wakeup symbol idle time configured by PRTC2.TXI, used to listen for activity on the bus
• A wakeup pattern composed of at least two Tx-wakeup symbols needed for wakeup
• Number of repetitions configurable by PRTC1.RWP (2 to 63 repetitions)
• Wakeup symbol receive window length configured by PRTC1.RXW
• Wakeup symbol receive low time configured by PRTC2.RXL
• Wakeup symbol receive idle time configured by PRTC2.RXI
Figure 23-14. Timing of Wake Up Pattern
TXL = 15-60 bit times
TXI = 45-180 bit times
Tx-wakeup Symbol
Rx-wakeup Pattern
(no collision)
Rx-wakeup Pattern
(collision, worst case)
23.10.7 STARTUP State
The description below is intended to help configuring startup for the FlexRay module. A detailed
description of the startup procedure can be found in the FlexRay protocol specification v2.1 Rev. A.
Any node entering STARTUP state that has coldstart capability should assure that both channels attached
have been awakened before initiating coldstart.
It cannot be assumed that all nodes and stars need the same amount of time to become completely
awake and to be configured. Since at least two nodes are necessary to start up the cluster
communication, it is advisable to delay any potential startup attempt of the node having instigated the
wakeup by the minimal amount of time it takes another coldstart node to become awake, to be configured
and to enter startup. It may require several hundred milliseconds (depending on the hardware used)
before all nodes and stars are completely awakened and configured.
Startup is performed on all channels synchronously. During startup, a node only transmits startup frames.
Startup frames are both sync frames and null frames during startup.
A fault-tolerant, distributed startup strategy is specified for initial synchronization of all nodes. In general, a
node may enter NORMAL_ACTIVE state by:
• Coldstart path initiating the schedule synchronization (leading coldstart node)
• Coldstart path joining other coldstart nodes (following coldstart node)
• Integration path integrating into an existing communication schedule (all other nodes)
See also Figure 23-15 for more information.
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A coldstart attempt begins with the transmission of a collision avoidance symbol (CAS). Only a coldstart
node that transmitted the CAS, transmits frames in the first four cycles after the CAS. it is then joined
firstly by the other coldstart nodes and afterwards by all other nodes.
A coldstart node has bits SUCC1.TXST and SUCC1.TXSY set to 1. Message buffer 0 holds the key slot
ID which defines the slot number where the startup frame is sent. The startup frame indicator bit is set in
the frame header of the startup frame.
In clusters consisting of three or more nodes, at least three nodes shall be configured to be coldstart
nodes. In clusters consisting of two nodes, both nodes must be coldstart nodes. At least two fault-free
coldstart nodes are necessary for the cluster to startup.
Each startup frame must also be a sync frame; therefore each coldstart node will also be a sync node.
The number of coldstart attempts is configured by SUCC1.CSA in the SUC configuration register 1.
A non-coldstart node requires at least two startup frames from distinct nodes for integration. It may start
integration before the coldstart nodes have finished their startup. It will not finish its startup until at least
two coldstart nodes have finished their startup.
Both non-coldstart nodes and coldstart nodes start passive integration through the integration path as
soon as they receive sync frames from which to derive the TDMA schedule information. During integration
the node has to adapt its own clock to the global clock (rate and offset) and has to make its cycle time
consistent with the global schedule observable at the network. Afterwards, these settings are checked for
consistency with all available network nodes. The node can only leave the integration phase and actively
participate in communication when these checks are passed.
23.10.7.1 Coldstart Inhibit Mode
In coldstart inhibit mode, the node is prevented from initializing the TDMA communication schedule. If the
CCSV.CSI bit in the communication controller status vector register is set, the node is not allowed to
initialize the cluster communication, that is, entering the coldstart path is prohibited. The node is allowed to
integrate to a running cluster or to transmit startup frames after another coldstart node starts the
initialization of the cluster communication.
The coldstart inhibit bit CCSV.CSI is set whenever the POC enters READY state. The bit has to be
cleared under control of the host by CHI command ALLOW_COLDSTART (SUCC1.CMD = 1001).
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Figure 23-15. State Diagram Time-Triggered Startup
Leading coldstart node
Following coldstart node
Non-coldstart node integrating
READY
ABORT
STARTUP
STARTUP
PREPARE
COLDSTART
LISTEN
INTEGRATION
LISTEN
COLDSTART ABORT
COLLISION
RESOLUTION STARTUP
INITIALIZE
SCHEDULE
COLDSTART ABORT
CONSISTENCY
CHECK
STARTUP
INTEGRATION
COLDSTART
STARTUP
CHECK
ABORT
COLDSTART
GAP
STARTUP
ABORT
COLDSTART
JOIN
STARTUP
INTEGRATION ABORT
CONSISTENCY
STARTUP
CHECK
ABORT
STARTUP
NORMAL
ACTIVE
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23.10.7.2 Startup Timeouts
The communication controller supplies two different μT timers supporting two timeout values, startup
timeout and startup noise timeout. The two timers are started when the communication controller enters
the COLDSTART_LISTEN state. The expiration of either of these timers causes the node to leave the
initial sensing phase (COLDSTART_LISTEN state) with the intention of starting up communication.
NOTE: The startup and startup noise timers are identical with the wakeup and wakeup noise timers
and use the same configuration values SUCC2.LT and SUCC2.LTN from the SUC
configuration register 2.
23.10.7.2.1 Startup Timeout
The startup timeout limits the listen time used by a node to determine if there is already communication
between other nodes or at least one coldstart node actively requesting the integration of others. The
startup timer is configured by programming SUCC2.LT in the SUC configuration register 2.
The startup timeout time can be calculated from the contents of SUCC2.LT (Refer to the FlexRay Protocol
Specification: pdListenTimeout)
The startup timer is restarted upon:
• Entering the COLDSTART_LISTEN state
• Both channels reaching idle state while in COLDSTART_LISTEN state
The startup timer is stopped:
• If communication channel activity is detected on one of the configured channels while the node is in
the COLDSTART_LISTEN state
• When the COLDSTART_LISTEN state is left
Once the startup timeout expires, neither an overflow nor a cyclic restart of the timer is performed. The
timer status is kept for further processing by the startup state machine.
23.10.7.2.2 Startup Noise Timeout
At the same time the startup timer is started for the first time (transition from STARTUP_PREPARE state
to COLDSTART_LISTEN state), the startup noise timer is started. This additional timeout is used to
improve reliability of the startup procedure in the presence of noise. The startup noise timer is configured
by programming SUCC2.LTN in the SUC configuration register 2.
The startup noise timeout time can be calculated as the product of SUCC2.LT × SUCC2.LTN (Refer to the
FlexRay Protocol Specification: pdListenTimeout • gListenNoise)
The startup noise timer is restarted upon:
• Entering the COLDSTART_LISTEN state
• Reception of correctly decoded headers or CAS symbols while the node is in COLDSTART_LISTEN
state
The startup noise timer is stopped when the COLDSTART_LISTEN state is left.
Once the startup noise timeout expires, neither an overflow nor a cyclic restart of the timer is performed.
The status is kept for further processing by the startup state machine. Since the startup noise timer won’t
be restarted when random channel activity is sensed, this timeout defines the fall-back solution that
guarantees that a node will try to start up the communication cluster even in the presence of noise.
23.10.7.3 Path of Leading Coldstart Node (Initiating Coldstart)
When a coldstart node enters COLDSTART_LISTEN, it listens to its attached channels.
If no communication is detected, the node enters the COLDSTART_COLLISION_RESOLUTION state and
commences a coldstart attempt. The initial transmission of a CAS symbol is succeeded by the first regular
cycle. This cycle has the number zero.
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From cycle zero on, the node transmits its startup frame. Since each coldstart node is allowed to perform
a coldstart attempt, it may occur that several nodes simultaneously transmit the CAS symbol and enter the
coldstart path. This situation is resolved during the first four cycles after CAS transmission.
As soon as a node that initiates a coldstart attempt receives a CAS symbol or a frame header during
these four cycles, it re-enters the COLDSTART_LISTEN state. Thereby, only one node remains in this
path. In cycle four, other coldstart nodes begin to transmit their startup frames.
After four cycles in COLDSTART_COLLISION_RESOLUTION state, the node that initiated the coldstart
enters the COLDSTART_CONSISTENCY_CHECK state. It collects all startup frames from cycle four and
five and performs clock correction. If the clock correction does not deliver any errors and it has received at
least one valid startup frame pair, the node leaves COLDSTART_CONSISTENCY_CHECK and enters
NORMAL_ACTIVE state.
The number of coldstart attempts that a node is allowed to perform is configured by SUCC1.CSA in the
SUC configuration register 1. The number of remaining coldstarts attempts can be read from CCSV.RCA
of communication controller status vector register. The number of remaining attempts is reduced by one
for each attempted coldstart. A node may enter the COLDSTART_LISTEN state only if this value is larger
than one and it may enter the COLDSTART_COLLISION_RESOLUTION state only if this value is larger
than zero. If the number of coldstart attempts is one, coldstart is inhibited but integration is still possible.
23.10.7.4 Path of Following Coldstart Node (Responding to Leading Coldstart Node)
When a coldstart node enters the COLDSTART_LISTEN state, it tries to receive a valid pair of startup
frames to derive its schedule and clock correction from the leading coldstart node.
As soon as a valid startup frame has been received, the INITIALIZE_SCHEDULE state is entered. If the
clock synchronization can successfully receive a matching second valid startup frame and derive a
schedule from this, the INTEGRATION_COLDSTART_CHECK state is entered.
In INTEGRATION_COLDSTART_CHECK state, it is assured that the clock correction can be performed
correctly and that the coldstart node from which this node has initialized its schedule is still available. The
node collects all sync frames and performs clock correction in the following double-cycle. If clock
correction does not signal any errors and if the node continues to receive sufficient frames from the same
node it has integrated on, the COLDSTART_JOIN state is entered.
In COLDSTART_JOIN state, following coldstart nodes begin to transmit their own startup frames and
continue to do so in subsequent cycles. Thereby, the leading coldstart node and the nodes joining it can
check if their schedules agree with each other. If the clock correction signals any error, the node aborts
the integration attempt. If a node in this state sees at least one valid startup frame during all even cycles
in this state and at least one valid startup frame pair during all double cycles in this state, the node leaves
COLDSTART_JOIN state and enters NORMAL_ACTIVE state. Thereby it leaves STARTUP at least one
cycle after the node that initiated the coldstart.
23.10.7.5 Path of Non-Coldstart Node
When a non-coldstart node enters the INTEGRATION_LISTEN state, it listens to its attached channels.
As soon as a valid startup frame has been received the INITIALIZE_SCHEDULE state is entered. If the
clock synchronization can successfully receive a matching second valid startup frame and derive a
schedule from this, the INTEGRATION_CONSISTENCY_CHECK state is entered.
In INTEGRATION_CONSISTENCY_CHECK state it is verified that the clock correction can be performed
correctly and that enough coldstart nodes (at least 2) send startup frames that agree with the nodes own
schedule. Clock correction is activated, and if any errors are signaled, the integration attempt is aborted.
During the first even cycle in this state, either two valid startup frames or the startup frame of the node
that this node has integrated on must be received; otherwise the node aborts the integration attempt.
During the first double-cycle in this state, either two valid startup frame pairs or the startup frame pair of
the node that this node has integrated on must be received; otherwise the node aborts the integration
attempt.
If after the first double-cycle less than two valid startup frames are received within an even cycle, or less
than two valid startup frame pairs are received within a double-cycle, the startup attempt is aborted.
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Nodes in this state need to see two valid startup frame pairs for two consecutive double-cycles each to be
allowed to leave STARTUP and enter NORMAL_OPERATION. Consequently, they leave startup at least
one double-cycle after the node that initiated the coldstart and only at the end of a cycle with an odd cycle
number.
23.10.8 NORMAL_ACTIVE State
As soon as the node that transmitted the first CAS symbol (resolving the potential access conflict and
entering STARTUP through the coldstart path) and one additional node have entered the
NORMAL_ACTIVE state, the startup phase for the cluster has finished. In the NORMAL_ACTIVE state, all
configured messages are scheduled for transmission. This includes all data frames as well as the sync
frames. Rate and offset measurement is started in all even cycles (even/odd cycle pairs required).
In
•
•
•
NORMAL_ACTIVE state the communication controller supports regular communication functions:
The communication controller performs transmissions and reception on the FlexRay bus as configured
Clock synchronization is running
The host interface is operational
The communication controller exits from that state to:
• HALT state by writing SUCC1.CMD = 0110 (HALT command, at the end of the current cycle)
• HALT state by writing SUCC1.CMD = 0111 (FREEZE command, immediately)
• HALT state due to change of the error state from ACTIVE to COMM_HALT
• NORMAL_PASSIVE state due to change of the error state from ACTIVE to PASSIVE
• READY state by writing SUCC1.CMD = 0010 (READY command)
23.10.9 NORMAL_PASSIVE State
NORMAL_PASSIVE state is entered from NORMAL_ACTIVE state when the error state changes from
ACTIVE to PASSIVE.
In NORMAL_PASSIVE state, the node is able to receive all frames (node is fully synchronized and
performs clock synchronization). Contrary to the NORMAL_ACTIVE state, the node does not actively
participate in communication, that is, neither symbols nor frames are transmitted.
In
•
•
•
•
NORMAL_PASSIVE state:
The communication controller performs reception on the FlexRay bus
The communication controller does not transmit any frames or symbols on the FlexRay bus
Clock synchronization is running
The host interface is operational
The communication controller exits from this state to
• HALT state by writing SUCC1.CMD = 0110 (HALT command, at the end of the current cycle)
• HALT state by writing SUCC1.CMD = 0111 (FREEZE command, immediately)
• HALT state due to change of the error state from PASSIVE to COMM_HALT
• NORMAL_ACTIVE state due to change of the error state from PASSIVE to ACTIVE. The transition
takes place when CCEV.PTAC equals SUCC1.PTA - 1.
• To READY state by writing SUCC1.CMD = 0010 (READY command)
23.10.10 HALT State
In this state all communication (reception and transmission) is stopped.
The communication controller enters this state:
• By writing SUCC1.CMD = 0110 (HALT command) while the communication controller is in
NORMAL_ACTIVE or NORMAL_PASSIVE state
• By writing SUCC1.CMD = 0111 (FREEZE command) from all states
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•
•
When exiting from NORMAL_ACTIVE state because the clock correction failed counter reached the
“maximum without clock correction fatal” limit and SUCC1.HCSE is set
When exiting from NORMAL_PASSIVE state because the clock correction failed counter reached the
“maximum without clock correction fatal” limit and SUCC1.HCSE is set
The communication controller exits from this state to DEFAULT_CONFIG state
• By writing SUCC1.CMD = 0001 (CONFIG command)
When the communication controller transits from HALT state to DEFAULT_CONFIG state all configuration
and status data is maintained for analyzing purposes.
When the host writes SUCC1.CMD = 0110 (HALT command), the communication controller sets bit
CCSV.HRQ and enters HALT state at next end of cycle.
When the host writes SUCC1.CMD = 0111 (FREEZE command), the communication controller enters
HALT state immediately and sets the CCSV.FSI bit in the communication controller status vector register.
The POC state from which the transition to HALT state took place can be read from CCSV.PSL.
23.11 Network Management
The accrued network management (NM) vector is located in the Network Management Registers (NMV[13]). The communication controller performs a logical OR operation over all NM vectors out of all received
valid NM frames with the Payload Preamble Indicator (PPI) bit set. Only a static frame may be configured
to hold NM information. The communication controller updates the NM vector at the end of each cycle.
The length of the NM vector can be configured from 0 to 12 bytes by NEMC.NML. The NM vector length
must be configured identically in all nodes of a cluster.
To configure a transmit buffer to send FlexRay frames with the PPI bit set, the PPIT bit in the header
section of the corresponding transmit buffer has to be set WRHS1.PPIT. In addition the host has to write
the NM information to the data section of the corresponding transmit buffer.
The evaluation of the NM vector has to be done by the application running on the host.
NOTE: In case a message buffer is configured for transmission / reception of network management
frames, the payload length configured in header 2 of that message buffer should be equal or
greater than the length of the NM vector configured by NEMC.NM. When the Communication
Controller transits to HALT state, the cycle count is not incremented and therefore the NM
vector is not updated. In this case NMV1/2/3 holds the value from the cycle before.
23.12 Filtering and Masking
Filtering is done by comparison of the configuration of assigned message buffers against current slot and
cycle counter values and channel ID (channel A, B). A message buffer is only updated / transmitted if the
required matches occur.
Filtering is done on:
• Slot counter
• Cycle counter
• Channel ID
The following filter combinations for acceptance / transmit filtering are allowed:
• Slot counter + Channel ID
• Slot counter + Cycle counter + Channel ID
All configured filters must match in order to store a received message in a message buffer.
NOTE: For the FIFO the acceptance filter is configured by the FIFO Rejection Filter and the FIFO
Rejection Filter mask.
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A message will be transmitted in the time slot corresponding to the configured frame ID on the configured
channel(s). If cycle counter filtering is enabled the configured cycle filter value must also match.
23.12.1 Slot Counter Filtering
Every transmit and receive buffer contains a frame ID stored in the header section. This frame ID is
compared against the current slot counter value in order to assign receive and transmit buffers to the
corresponding slot.
If two or more message buffers are configured with the same frame ID and channel ID, and if they have a
matching cycle counter filter value for the same slot, then the message buffer with the lowest message
buffer number is used.
23.12.2 Cycle Counter Filtering
Cycle counter filtering is based on the notion of a cycle set. For filtering purposes, a match is detected if
any one of the elements of the cycle set is matched. The cycle set is defined by the cycle code field in the
header section 1 of each message buffer.
If message buffer 0 or 1 is configured to hold the startup / sync frame or the single slot frame by bits
TXST, TXSY, and TSM of SUC Configuration Register 1, cycle counter filtering for message buffer 0 or 1
respectively shall be disabled.
NOTE: Sharing of a static time slot by cycle counter filtering between different nodes of a FlexRay
network is not allowed.
The set of cycle numbers belonging to a cycle set is determined as described in Table 23-8.
Table 23-8. Definition of Cycle Set
Cycle Code
Matching Cycle Counter Values
0b000000x
All cycles
0b000001c
Every second cycle
at (cycle count)mod2
=c
0b00001cc
Every fourth cycle
at (cycle count)mod4
= cc
0b0001ccc
Every eighth cycle
at (cycle count)mod8
= ccc
0b001cccc
Every sixteenth cycle
at (cycle count)mod16
= cccc
0b01ccccc
Every thirty-second cycle
at (cycle count)mod32
= ccccc
0b1cccccc
Every sixty-fourth cycle
at (cycle count)mod64
= cccccc
Table 23-9 gives some examples for valid cycle sets to be used for cycle counter filtering.
Table 23-9. Examples for Valid Cycle Sets
Cycle Code
Matching Cycle Counter Values
0b0000011
1-3-5-7- …. -63 ↵
0b0000100
0-4-8-12- …. -60 ↵
0b0001110
6-14-22-30- …. -62 ↵
0b0011000
8-24-40-56 ↵
0b0100011
3-35 ↵
0b1001001
9↵
The received message is stored only if the cycle counter value of the cycle during which the message is
received matches an element of the receive buffer’s cycle set. Other filter criteria must also be met.
The content of a transmit buffer is transmitted on the configured channel(s) when an element of the cycle
set matches the current cycle counter value. Other filter criteria must also be met.
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23.12.3 Channel ID Filtering
There is a 2-bit channel filtering field (CHA, CHB) located in the header section of each message buffer in
the message RAM. It serves as a filter for receive buffers, and as a control field for transmit buffers (see
Table 23-10).
Table 23-10. Channel Filtering Configuration
Transmit Buffer
Receive Buffer
CHA
CHB
Transmit frame
Store valid receive frame
1
1
On both channels (static segment only)
Received on channel A or B (store first semantically
valid frame, static segment only)
1
0
On channel A
Received on channel A
0
1
On channel B
Received on channel B
0
0
No transmission
Ignore frame
The contents of a transmit buffer is transmitted on the channels specified in the channel filtering field when
the slot counter filtering and cycle counter filtering criteria are also met. Only in static segment a transmit
buffer may be set up for transmission on both channels (CHA and CHB set).
Valid received frames are stored if they are received on the channels specified in the channel filtering field
when the slot counter filtering and cycle counter filtering criteria are also met. Only in static segment a
receive buffer may be setup for reception on both channels (CHA and CHB set).
NOTE: If a message buffer is configured for the dynamic segment and both bits of the channel
filtering field are set to 1, no frames are transmitted and received frames are ignored (same
function as CHA = CHB = 0)
23.12.4 FIFO Filtering
For FIFO filtering there is one rejection filter and one rejection filter mask available. The FIFO filter
consists of channel filter FRF.CH, frame ID filter FRF.FID, and cycle counter filter FRF.CYF. Registers
FRF and FRFM can be configured in DEFAULT_CONFIG or CONFIG state only. The filter configuration in
the header section of message buffers belonging to the FIFO is ignored.
The 7-bit cycle counter filter determines the cycle set to which frame ID and channel rejection filter are
applied. In cycles not belonging to the cycle set specified by FRF.CYF, all frames are rejected.
A valid received frame is stored in the FIFO if channel ID, frame ID, and cycle counter are not rejected by
the configured rejection filter and rejection filter mask, and if there is no matching dedicated receive buffer.
23.13 Transmit Process
23.13.1 Static Segment
For the static segment, if there are several messages pending for transmission, the message with the
frame ID corresponding to the next sending slot is selected for transmission.
The data section of transmit buffers assigned to the static segment can be updated until the end of the
preceding time slot. This means that a transfer from the input buffer has to be started by writing to the
Input Buffer Command Request Register latest at this time.
23.13.2 Dynamic Segment
In the dynamic segment, if several messages are pending, the message with the highest priority (lowest
frame ID) is selected next. In the dynamic segment different slot counter sequences on channel A and
channel B are possible (concurrent sending of different frame IDs on both channels).
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The data section of transmit buffers assigned to the dynamic segment can be updated until the end of the
preceding slot. This means that a transfer from the input buffer has to be started by writing to the Input
Buffer Command Request Register latest at this time.
The start of latest transmit configured by MHDC.SLT in the MHD configuration register 1 defines the
maximum minislot value allowed before inhibiting new frame transmission in the dynamic segment of the
current cycle.
23.13.3 Transmit Buffers
Communication Controller message buffers can be configured as transmit buffers by programming bit
CFG in the header section of the corresponding message buffer to 1 in WRHS1.
There exist the following possibilities to assign a transmit buffer to the communication controller channels:
• Static segment:
– channel A or channel B
– channel A and channel B
• Dynamic segment:
– channel A or channel B
Message buffer 0 or 1 is dedicated to hold the startup frame, the sync frame, or the designated single slot
frame as configured by SUCC1.TXST, SUCC1.TXSY, and SUCC1.TSM in the SUC Configuration register
1. In this case it can be reconfigured in DEFAULT_CONFIG or CONFIG state only. This ensures that any
node transmits at most one startup / sync frame per communication cycle. Transmission of startup / sync
frames from other message buffers is not possible.
All other message buffers configured for transmission in static or dynamic segment are reconfigurable
during runtime depending on the configuration of MRC.SEC. Due to the organization of the data partition
in the message RAM (reference by data pointer), reconfiguration of the configured payload length and the
data pointer in the header section of a message buffer may lead to erroneous configurations.
If a message buffer is reconfigured (header section updated) during runtime, it may happen that this
message buffer is not sent out in the currently active communication cycle.
The communication controller does not have the capability to calculate the header CRC. The host is
supposed to provide the header CRCs for all transmit buffers. If network management is required the host
has to set the PPIT bit in the header section of the corresponding message buffer to 1 and write the
network management information to the data section of the message buffer.
The payload length field configures the data payload length in 2-byte words. If the configured payload
length of a static transmit buffer is shorter than the payload length configured for the static segment by
MHDC.SFDL in the message handler configuration register 1, the communication controller generates
padding bytes to ensure that frames have proper physical length. The padding pattern is logical zero.
NOTE: In case of an odd payload length (PLC = 1,3,5, and so on), the application needs to write
zeros to the last 16 bits of the message buffers data section to ensure that the padding
pattern is all zero.
Each transmit buffer provides a transmission mode flag TXM that allows the host to configure the
transmission mode for the transmit buffer. If this bit is set, the transmitter operates in the single-shot
mode. If this bit is cleared, the transmitter operates in the continuous mode.
In single-shot mode the Communication Controller resets the corresponding TXR flag after transmission
has completed after which the host may update the transmit buffer.
In continuous mode, the Communication Controller does not reset the corresponding transmission request
flag TXR after successful transmission. In this case a frame is sent out each time the filter criteria match.
The TXR flag can be reset by the Host by writing the corresponding message buffer number to the IBCR
register while bit IBCM.STXRH is set to 0.
If two or more transmit buffers meet the filter criteria simultaneously, the transmit buffer with the lowest
message buffer number will be transmitted in the corresponding slot.
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23.13.4 Frame Transmission
The following steps are required to prepare a message buffer for transmission:
• Configure the transmit buffer in the Message RAM through WRHS1, WRHS2, and WRHS3
• Write the data section of the transmit buffer through WRDSn
• Transfer the configuration and message data from Input Buffer to the Message RAM by writing the
number of the target message buffer to register IBCR
• If configured in the Input Buffer Command Mask (IBCM) register the Transmission request flag (TXR)
for the corresponding message buffer will be set as soon as the transfer has completed, and the
message buffer is ready for transmission.
• Check whether the message buffer has been transmitted by checking the TXR bits (TXR = 0) in the
Transmission request 1,2,3,4 registers (single-shot mode only).
After transmission has completed, the corresponding TXR flag in the Transmission request 1,2,3,4 register
is reset (single- shot mode), and, if bit MBI in the header section of the message buffer is set, flag SIR.TXI
in the Status Interrupt register is set to 1. If enabled, an interrupt is generated.
23.13.5 Null Frame Transmission
If in static segment the host does not set the transmission request flag before transmit time, and if there is
no other transmit buffer with matching filter criteria, the communication controller transmits a null frame
with the null frame indication bit set and the payload data set to zero.
In the following cases the communication controller transmits a null frame:
• If the message buffer with the lowest message buffer number matching the filter criteria does not have
its transmission request flag set (TXR = 0).
• No transmit buffer configured for the slot has a cycle counter filter that matches the current cycle. In
this case, no message buffer status MBS is updated.
Null frames are not transmitted in the dynamic segment.
23.14 Receive Process
23.14.1 Dedicated Receive Buffers
A portion of the Communication Controller message buffers can be configured as dedicated receive
buffers by programming bit CFG in the header section of the corresponding message buffer to 0. This can
be done through the Write Header Section 1 register.
The following possibilities exist to assign a receive buffer to the Communication Controller channels:
• Static segment:
– channel A or channel B
– channel A and channel B (the communication controller stores the first semantically valid frame)
• Dynamic segment:
– channel A or channel B
The communication controller transfers payload data of valid received messages from the shift registers of
the FlexRay protocol controller (channel A or B) to the receive buffer with the matching filter configuration.
A receive buffer stores all frame elements except the frame CRC.
All message buffers configured for reception in static or dynamic segment are reconfigurable during
runtime depending on the configuration of MRC.SEC of the Message RAM Configuration register. If a
message buffer is reconfigured (header section updated) during runtime it may happen that in the
currently active communication cycle a received message is lost.
If two or more receive buffers meet the filter criteria simultaneously, the receive buffer with the lowest
message buffer number is updated with the received message.
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23.14.2 Frame Reception
The following steps are required to prepare a dedicated message buffer for reception:
• Configure the receive buffer in the Message RAM through WRHS1, WRHS2, and WRHS3
• Transfer the configuration from input buffer to the message RAM by writing the number of the target
message buffer to the Input Buffer Command Request (IBCR) register.
Once these steps are performed, the message buffer functions as an active receive buffer and participates
in the internal acceptance filtering process, which takes place every time the communication controller
receives a message. The first matching receive buffer is updated from the received message.
If a valid payload segment was stored in the data section of a message buffer, the corresponding ND flag
in the NDAT[1-4] registers is set, and, if bit MBI in the header section of that message buffer is set, flag
SIR.RXI in the Status Interrupt Register is set to 1. If enabled, an interrupt is generated.
In case that bit ND was already set when the Message Handler updates the message buffer, bit
MBS.MLST of the corresponding message buffer is set and the unprocessed message data is lost.
If no frame, a null frame, or a corrupted frame is received in a slot, the data section of the message buffer
configured for this slot is not updated. In this case only the flags in the corresponding message buffer
status (MBS) is updated.
When the Message Handler changes the message buffer status MBS in the header section of a message
buffer, the corresponding MBC flag in the Message Buffer Status Changed 1,2,3 or 4 register is set, and if
bit MBI in the header section of that message buffer is set, flag SIR.MBSI in the Status Interrupt Register
is set to 1. If enabled an interrupt is generated.
If the payload length of a received frame PLR is longer than the value programmed by PLC in the header
section of the corresponding message buffer, the data field stored in the message buffer is truncated to
that length.
NOTE: The ND and MBS flags are automatically cleared by the message handler when the payload
data and the header of a received message have been transferred to the output buffer,
respectively.
23.14.3 Null Frame Reception
The payload segment of a received null frame is not copied into the matching dedicated receive buffer. If a
null frame has been received, only the message buffer status MBS of the matching message buffer is
updated from the received null frame. All bits in header 2 and 3 of the matching message buffer remain
unchanged. They are updated from received data frames only.
23.15 FIFO Function
23.15.1 Description
A group of the message buffers can be configured as a cyclic First-In-First-Out (FIFO) buffer. The group of
message buffers belonging to the FIFO is contiguous in the register map starting with the message buffer
referenced by MRC.FFB and ending with the message buffer referenced by MRC.LCB in the message
RAM configuration register. Up to 128 message buffers can be assigned to the FIFO.
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Every valid incoming message not matching with any dedicated receive buffer but passing the
programmable FIFO filter is stored into the FIFO. In this case frame ID, payload length, receive cycle
count, and the message buffer status MBS of the addressed FIFO message buffer are overwritten with
frame ID, payload length, receive cycle count, and the status from the received frame. Bit SIR.RFNE in the
status interrupt register shows that the FIFO is not empty, bit SIR.RFCL is set when the receive FIFO fill
level FSR.RFFL is equal or greater than the critical level as configured by FCL.CL, bit EIR.RFO shows
that a FIFO overrun has been detected. If enabled, interrupts are generated.
If null frames are not rejected by the FIFO rejection filter, the null frames will be treated like data frames
when they are stored into the FIFO.
There are two index registers associated with the FIFO. The PUT Index register (PIDX) is an index to the
next available location in the FIFO. When a new message has been received it is written into the message
buffer addressed by the PIDX register. The PIDX register is then incremented and addresses the next
available message buffer. If the PIDX register is incremented past the highest numbered message buffer
of the FIFO, the PIDX register is loaded with the number of the first (lowest numbered) message buffer in
the FIFO chain. The GET Index register (GIDX) is used to address the next message buffer of the FIFO to
be read. The GIDX register is incremented after transfer of the contents of a message buffer belonging to
the FIFO to the output buffer. The PUT Index register and the GET Index register are not memory mapped
and are not accessible by the host CPU.
The FIFO is completely filled when the PUT index (PIDX) reaches the value of the GET index (GIDX).
When the next message is written to the FIFO before the oldest message has been read, both PUT index
and GET index are incremented and the new message overwrites the oldest message in the FIFO. This
will set FIFO overrun flag EIR.RFO in the error interrupt register.
A FIFO not empty status is detected when the PUT index (PIDX) differs from the GET index (GIDX). In
this case flag SIR.RFNE is set. This indicates that there is at least one received message in the FIFO. The
FIFO empty, FIFO not empty, and the FIFO overrun states are explained in Figure 23-16 for a three
message buffer FIFO.
The programmable FIFO Rejection Filter register (FRF) defines a filter pattern for messages to be
rejected. The FIFO rejection filter consists of channel filter, frame ID filter, and cycle counter filter. If bit
FRF.RSS is set to 1 (default), all messages received in the static segment are rejected by the FIFO. If bit
FRF.RNF is set to 1 (default), received null frames are not stored in the FIFO.
The FIFO Rejection Filter mask register (FRFM) specifies which bits of the frame ID filter in the FIFO
Rejection Filter register are marked don’t care for rejection filtering.
Figure 23-16. FIFO Status: Empty, Not Empty, and Overrun
FIFO empty
PIDX
(store next)
FIFO not empty
FIFO overrun
PIDX
(store next)
PIDX
(store next)
Buffers
1
2
3
Buffers
1
2
3
Buffers
1
2
3
Messages
-
-
-
Messages
A
-
-
Messages
A
D
B
C
GIDX
(read oldest)
GIDX
(read oldest)
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(read oldest)
- PIDX incremented last
- Next received message
will be stored into buffer 1
- If buffer 1 has not been read
before message A is lost
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23.15.2 Configuration of the FIFO
(Re)configuration of message buffers belonging to the FIFO is only possible when the Communication
Controller is in DEFAULT_CONFIG or CONFIG state. While the Communication Controller is in
DEFAULT_CONFIG or CONFIG state, the FIFO function is not available.
For all message buffers belonging to the FIFO should have the same payload length configured in
WRHS2.PLC of the Write Header Section 2 register. The data pointer to the first 32-bit word in the data
section of the corresponding message buffer has to be configured by WRHS3.DP.
All information required for acceptance filtering is taken from the FIFO rejection filter and the FIFO
rejection filter mask. With the exception of DP and PLC, the values configured in the header sections of
the message buffers belonging to the FIFO are irrelevant.
NOTE: It is recommended to program the MBI bits of the message buffers belonging to the FIFO to
0 by WRHS1.MBI to avoid RX interrupts to be generated.
If the payload length of a received frame is longer than the value programmed by
WRHS2.PLC in the header section of the corresponding message buffer, the data field
stored in a message buffer of the FIFO is truncated to that length.
23.15.3 Access to the FIFO
For FIFO access outside DEFAULT_CONFIG and CONFIG state, the Host has to trigger a transfer from
the Message RAM to the Output Buffer by writing the number of the first message buffer of the FIFO
(referenced by MRC.FFB) to the Output Buffer Command Request (OBCR) register. The message handler
then transfers the message buffer addressed by the GET Index register (GIDX) to the output buffer. After
this transfer the GET Index register (GIDX) is incremented.
23.16 Message Handling
The message handler controls data transfers between the input / output buffer and the message RAM and
between the message RAM and the two transient buffer RAMs. All accesses to the internal RAMs are 32
bit accesses.
Access to the message buffers stored in the message RAM is done under control of the message handler
state machine. This avoids conflicts between accesses of the two protocol controllers and the host CPU to
the message RAM.
Frame IDs of message buffers assigned to the static segment have to be in the range from 1 to
GTU7.NSS as configured in the GTU configuration register 7. Frame IDs of message buffers assigned to
the dynamic segment have to be in the range from GTU7.NSS + 1 to 2047.
Received messages with no matching dedicated receive buffer (static or dynamic segment) are stored in
the receive FIFO (if configured) if they pass the FIFO rejection filter.
23.16.1 Reconfiguration of Message Buffers
In case that an application needs to operate with more than 128 different messages, static and dynamic
message buffers may be reconfigured during FlexRay operation. This is done by updating the header
section of the corresponding message buffer through Input Buffer registers WRHS[1-3].
Reconfiguration has to be enabled through control bits MRC.SEC in the Message RAM Configuration
register.
If a message buffer has not been transmitted / updated from a received frame before reconfiguration
starts, the corresponding message is lost.
The point in time when a reconfigured message buffer is ready for transmission / reception according to
the reconfigured frame ID depends on the current state of the slot counter when the update of the header
section has completed. Therefore it may happen that a reconfigured message buffer is not transmitted /
updated from a received frame in the cycle where it was reconfigured.
The Message RAM is scanned according to Table 23-11.
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Table 23-11. Scan of Message RAM
Start of Scan in Slot
Scan for Slots
1
2...15, 1 (next cycle)
8
16...23, 1 (next cycle)
16
24...31, 1 (next cycle)
24
32...39, 1 (next cycle)
....
...
A Message RAM scan is terminated with the start of NIT irrespective of its completion. The scan of the
Message RAM for slots 2 to 15 starts at the beginning of slot 1 of the current cycle. The scan of the
Message RAM for slot 1 is done in the cycle before by checking in parallel to each scan of the Message
RAM whether there is a message buffer configured for slot 1 of the next cycle.
The number of the first dynamic message buffer is configured by MRC.FDB in the Message RAM
Configuration register. In case a Message RAM scan starts while the Communication Controller is in
dynamic segment, the scan starts with the message buffer number configured by MRC.FDB.
In case a message buffer needs to be reconfigured to be used in slot 1 of the next cycle, the following has
to be considered:
• If the message buffer to be reconfigured for slot 1 is part of the Static Buffers, it will only be found if it
is reconfigured before the last Message RAM scan in the static segment of the current cycle evaluates
this message buffer.
• If the message buffer to be reconfigured for slot 1 is part of the Static + Dynamic Buffers, it will be
found if it is reconfigured before the last Message RAM scan in the current cycle evaluates this
message buffer.
• The start of NIT terminates the Message RAM scan. In case the Message RAM scan has not
evaluated the reconfigured message buffer until this point in time, the message buffer will not be
considered for the next cycle.
NOTE: Reconfiguration of message buffers may lead to the loss of messages and therefore has to
be used very carefully. In worst case (reconfiguration in consecutive cycles) it may happen
that a message buffer is never transmitted / updated from a received frame.
23.16.2 Host Access to Message RAM
The message transfer between input buffer and message RAM as well as between message RAM and
output buffer is triggered by the host CPU by writing the number of the target / source message buffer to
be accessed to the input or output buffer command request register (IBCR/OBCR).
The input / output buffer command mask registers can be used to write / read header and data section of
the selected message buffer separately.
If bit IBCM.STXR in the input buffer command mask register is set (STXR = 1), the transmission request
flag TXR of the selected message buffer is automatically set after the message buffer has been updated.
If bit IBCM.STXR in the input buffer command mask register is reset (STXR = 0), the transmission request
flag TXR of the selected message buffer is reset. This can be used to stop transmission from message
buffers operated in continuous mode.
Input buffer (IBF) and the output buffer (OBF) are built up as a double buffer structure. One half of this
double buffer structure is accessible by the host CPU (IBF host / OBF host), while the other half (IBF
shadow / OBF shadow) is accessed by the message handler for data transfers between IBF / OBF and
message RAM.
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Figure 23-17. Host Access to Message RAM
AddressDecoder
and Control
Data(31-0)
Output Buffer
[Shadow]
Control
Address
Data(31-0)
Input Buffer
[Shadow]
Address
Data(31-0)
Host CPU
Address
Data(31-0)
Message handler
Header Partition
Data Partition
Message RAM
23.16.2.1 Data Transfer from Input Buffer to Message RAM
To configure / update a message buffer in the message RAM, the host has to write the data to WRDSn
and the header to WRHS[1-3]. The specific action is selected by configuring the input buffer command
mask IBCM.
When the host writes the number of the target message buffer in the message RAM to IBCR.IBRH in the
input buffer command request register IBCR, IBF host and IBF shadow are swapped (see Figure 23-18).
With this write operation the IBCR.IBSYS bit in the input buffer command request register is set to 1. The
message handler then starts to transfer the contents of IBF shadow to the message buffer in the message
RAM selected by IBCR.IBRS.
While the message handler transfers the data from IBF shadow to the target message buffer in the
message RAM, the host may write the next message to IBF host. After the transfer between IBF shadow
and the message RAM has completed, the IBCR.IBSYS bit is set back to 0 and the next transfer to the
message RAM may be started by the host by writing the corresponding target message buffer number to
IBCR.IBRH in the input buffer command request register.
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Figure 23-18. Double Buffer Structure Input Buffer
FlexRay
IBF
Shadow
IBF
Host
Host
Message
RAM
IBF = Input Buffer
Figure 23-19. Swapping of IBCM and IBCR Bits
IBCM
IBCR
18 17 16
2 1 0
swap
31
22 21 20 19 18 17 16
15
6 5 4 3 2 1 0
swap
If a write access to IBCR.IBRH occurs while IBCR.IBSYS is 1, IBCR.IBSYH is set to 1. After completion of
the ongoing data transfer from IBF shadow to the message RAM, IBF host and IBF shadow are swapped,
IBCR.IBSYH is reset to 0, IBCR.IBSYS remains set to 1, and the next transfer to the message RAM is
started. In addition the message buffer numbers stored under IBCR.IBRH and IBCR.IBRS and the
command mask flags are also swapped.
Example of a 8/16/32-bit host access sequence:
• Configure / update n-th message buffer through IBF
• Wait until IBCR.IBSYH is reset
• Write data section to WRDSn
• Write header section to WRHS[1-3]
• Write command mask: write IBCM.STXRH, IBCM.LHSH, IBCM.LDSH
• Demand data transfer to target message buffer: write IBCR.IBRH
Configure / update further message buffer through IBF in the same way.
NOTE: Any write access to IBF while IBCR.IBSYH is 1 will set error flag EIR.IIBA in the Error
Interrupt Register to 1. In this case, the write access has no effect.
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Table 23-12. Assignment of Input Buffer Command Mask Bits
Position
Access
Bit
18
r
STXRS
Function
17
r
LDSS
Load Data Section shadow ongoing or finished
Load Header Section shadow ongoing or finished
Set Transmission Request shadow ongoing or finished
16
r
LHSS
2
r/w
STXRH
1
r/w
LDSH
Load Data Section Host
0
r/w
LHSH
Load Header Section Host
Set Transmission Request Host
Table 23-13. Assignment of Input Buffer Command Request Bits
Position
Access
Bit
31
r
IBSYS
22…16
r
IBRS
15
r
IBSYH
6…0
r/w
IBRH
Function
IBF Busy Shadow, signals ongoing transfer from IBF shadow to message RAM
IBF Request Shadow, number of message buffer currently / last updated
IBF Busy Host, transfer request pending for message buffer referenced by IBRH
IBF Request Host, number of message buffer to be updated next
23.16.2.2 Data Transfer from Message RAM to Output Buffer
To read out a message buffer from the message RAM, the host has to write to the output buffer command
mask and command request register to trigger the data transfer. After a transfer has completed the host
can read the transferred data from the RDDSn, RDHS[1-3], and MBS.
Figure 23-20. Double Buffer Structure Output Buffer
FlexRay
Host
OBF
Host
OBF
Shadow
Message
RAM
OBF = Output Buffer
OBF host and OBF shadow as well as bits OBCM.RHSS, OBCM.RDSS, OBCM.RHSH, OBCM.RDSH
from the output buffer command mask register and bits OBCM.OBRS, OBCM.OBRH from the output
buffer command request register are swapped under control of bits OBCR.VIEW and OBCR.REQ from the
output buffer command request register.
Writing bit OBCR.REQ in the output buffer command request register to 1 copies bits OBCM.RHSS,
OBCM.RDSS from the output buffer command mask register and bits OBCR.OBRS from the output buffer
command request register to an internal storage (see Figure 23-21).
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After setting OBCR.REQ to 1, OBCR.OBSYS is set to 1, and the transfer of the message buffer selected
by OBCR.OBRS from the message RAM to OBF shadow is started. After the transfer between the
message RAM and OBF shadow has completed, the OBCR.OBSYS bit is set back to 0. Bits OBCR.REQ
and OBCR.VIEW can only be set to 1 while OBCR.OBSYS is 0.
Figure 23-21. Swapping of OBCM and OBCR Bits
OBCM
17 16
view
internal storage
1 0
1 0
request
OBCR
22 21 20 19 18 17 16
internal storage
view
6 5 4 3 2 1 0
15
9 8
6 5 4 3 2 1 0
request
OBF host and OBF shadow are swapped by setting bit OBCR.VIEW in the output buffer command request
register to 1 while bit OBCR.OBSYS is 0 (see Figure 23-20).
In addition bits OBCR.OBRH are swapped with the output buffer command request registers internal
storage and bits OBCM.RHSH, OBCM.RDSH are swapped with the output buffer command mask
registers internal storage thus assuring that the message buffer number stored in OBCR.OBRH and the
mask configuration stored in OBCM.RHSH, OBCM.RDSH matches the transferred data stored in OBF
host (see Figure 23-21).
Now the host can read the transferred message buffer from OBF host while the message handler may
transfer the next message from the message RAM to OBF shadow.
NOTE: If bits REQ and VIEW are set to 1 with the same write access while OBSYS is 0, OBSYS is
automatically set to 1 and OBF shadow and OBF host are swapped. Additionally mask bits
OBCM.RDSH and OBCM.RHSH are swapped with the registers internal storage to keep
them attached to the corresponding Output Buffer transfer. Afterwards OBRS is copied to the
register internal storage, mask bits OBCM.RDSS and OBCM.RHSS are copied to register
OBCM internal storage, and the transfer of the selected message buffer from the Message
RAM to OBF shadow is started. While the transfer is ongoing the Host can read the
message buffer transferred by the previous transfer from OBF Host. When the current
transfer between Message RAM and OBF shadow has completed, this is signaled by setting
OBSYS back to 0.
Example of an 8/16/32-bit host access to a single message buffer:
If a single message buffer has to be read out, two separate write accesses to OBCR.REQ and
OBCR.VIEW are necessary:
• Wait until OBCR.OBSYS is reset
• Write Output Buffer Command Mask OBCM.RHSS, OBCM.RDSS
• Request transfer of message buffer to OBF Shadow by writing OBCR.OBRS and OBCR.REQ (in case
of and 8-bit Host interface, OBCR.OBRS has to be written before OBCR.REQ)
• Wait until OBCR.OBSYS is reset
• Toggle OBF Shadow and OBF Host by writing OBCR.VIEW = 1
• Read out transferred message buffer by reading RDDSn, RDHS[1-3], and MBS
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Example of an 8/16/32-bit host access sequence:
Request transfer of 1st message buffer to OBF shadow
• Wait until OBCR.OBSYS is reset
• Write Output Buffer Command Mask OBCM.RHSS, OBCM.RDSS for 1st message buffer
• Request transfer of 1st message buffer to OBF Shadow by writing OBCR.OBRS and OBCR.REQ (in
case of an 8-bit Host interface, OBCR.OBRS has to be written before OBCR.REQ).
Toggle OBF Shadow and OBF Host to read out 1st transferred message buffer and request transfer of
2nd message buffer:
Request transfer of 2nd message buffer to OBF shadow, read out 1st message buffer from OBF host
• Wait until OBCR.OBSYS is reset
• Write Output Buffer Command Mask OBCM.RHSS, OBCM.RDSS for 2nd message buffer
• Toggle OBF Shadow and OBF Host and start transfer of 2nd message buffer to OBF Shadow
simultaneously by writing OBCR.OBRS of 2nd message buffer, OBCR.REQ, and OBCR.VIEW (in case
of and 8-bit Host interface, OBCR.OBRS has to be written before OBCR.REQ and OBCR.VIEW).
• Read out 1st transferred message buffer by reading RDDSn, RDHS[1-3], and MBS
For further transfers continue the same way.
Demand access to last requested message buffer without request of another message buffer:
• Wait until OBCR.OBSYS is reset
• Demand access to last transferred message buffer by writing OBCR.VIEW
• Read out last transferred message buffer by reading RDDSn, RDHS[1-3], and MBS
Table 23-14. Assignment of Output Buffer Command Mask Bits
Position
Access
Bit
Function
17
r
RDSH
Read Data Section Host access
16
r
RHSH
Read Header Section Host access
1
r/w
RDSS
Read Data Section Shadow
0
r/w
RHSS
Read Header Section Shadow
Table 23-15. Assignment of Output Buffer Command Request Bits
Position
Access
Bit
22…16
r
OBRH
Function
OBF Request Host, number of message buffer available for host access
15
r
OBSYS
OBF Busy Shadow, signals ongoing transfer from message RAM to OBF Shadow
9
r/w
REQ
Request Transfer from message RAM to OBF Shadow
8
r/w
VIEW
View OBF Shadow, swap OBF Shadow and OBF Host
6…0
r/w
OBRS
OBF Request Shadow, number of message buffer for next request
23.16.3 FlexRay Protocol Controller Access to Message RAM
The two transient buffer RAMs (TBF A,B) are used to buffer the data for transfer between the two FlexRay
channel protocol controllers and the message RAM.
Each transient buffer RAM is built up as a double buffer, able to store two complete FlexRay messages.
There is always one buffer assigned to the corresponding protocol controller while the other one is
accessible by the message handler.
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If for example, the message handler writes the next message to be sent to transient buffer Tx, the
FlexRay Channel protocol controller can access transient buffer Rx to store the message it is currently
receiving. During transmission of the message stored in transient buffer Tx, the message handler transfers
the last received message stored in transient buffer Rx to the message RAM (if it passes acceptance
filtering) and updates the corresponding message buffer.
Data transfers between the transient buffer RAMs and the shift registers of the FlexRay channel protocol
controllers are done in words of 32 bit. This enables the use of a 32 bit shift register independent of the
length of the FlexRay messages.
Figure 23-22. Access to Transient Buffer RAMs
Txd2
Shift Register
Shift Register
Control
Control
Transient Buffer Rx
Transient Buffer Rx
Transient Buffer Tx
Data(31-0)
Transient Buffer Tx
Data(31-0)
FlexRay PRT B
Data(31-0)
FlexRay PRT A
Data(31-0)
Address-Decoder
Address
TBF A
Rxd2
Address-Decoder
Txd1
TBF B
Address
Rxd1
Message Handler
23.17 Module RAMs
The FlexRay module contains the following RAM portions:
• Message RAM
• Transient Buffer RAM Channel A (TBF A)
• Transient Buffer RAM Channel B (TBF B)
• Input Buffer (IBF)
• Input Buffer Shadow (IBFS)
• Output Buffer (OBF)
• Output Buffer Shadow (OBFS)
• Transfer Configuration RAM (TCR)
All RAMs except the TCR are part of the Communication Controller core.
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23.17.1 Message RAM
To avoid conflicts between host access to the message RAM and FlexRay message reception /
transmission, the host CPU cannot directly access the message buffers in the message RAM. These
accesses are handled through the input and output buffers. The message RAM is able to store up to 128
message buffers depending on the configured payload length.
The message RAM has a structure as shown in Figure 23-23.
The data partition is allowed to start at Message RAM word number: (MRC.LCB + 1) × 4
Figure 23-23. Configuration Example of Message Buffers in the Message RAM
Message RAM
Header MB0
Header MB1
‚
‚
‚
Header Partition
Header MBn
Data MB0
2048
words
Data MB1
‚
‚
‚
Data Partition
Data MBn
unused
32 bit
Header Partition
Stores header segments of FlexRay frames:
• Supports a maximum of 128 message buffers
• Each message buffer has a header of four 32 bit words
• Header 3 of each message buffer holds the 11-bit data pointer to the corresponding data section in the
data partition
Data Partition
Flexible storage of data sections with different length. Some maximum values are:
• 30 message buffers with 254 byte data section each
• Or 56 message buffers with 128 byte data section each
• Or 128 message buffers with 48 byte data section each
Restriction: header partition + data partition may not occupy more than 2048 × 32 bit words.
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23.17.1.1 Header Partition
The elements used for configuration of a message buffer as well as the current message buffer status are
stored in the header partition of the message RAM as listed in Figure 23-24. Configuration of the header
sections of the message buffers is done through IBF (Write Header Section 1,2,3). Read access to the
header sections is done through OBF (read header section 1,2,3 + message buffer status). The data
pointer has to be calculated by the programmer to define the starting point of the data section for the
corresponding message buffer in the data partition of the message RAM. The data pointer should not be
modified during runtime. For message buffers belonging to the receive FIFO (re)configuration should be
done in DEFAULT_CONFIG or CONFIG state only.
The header section of each message buffer occupies four 32 bit words in the header partition of the
message RAM. The header of message buffer 0 starts with the first word in the message RAM.
For transmit buffers the Header CRC has to be calculated by the host CPU.
Payload length received (PLR), receive cycle count (RCC), Received on Channel Indication (RCI), Startup
Frame Indication bit (SFI), sync bit (SYN), null frame indication bit (NFI), payload preamble indication bit
(PPI), and reserved bit (RES) are only updated from received valid data frames only.
Header word 3 of each configured message buffer holds the corresponding message buffer status MBS.
Figure 23-24. Header Section of Message Buffer in Message RAM
Bit
Word
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
M T
B X
I M
0
P
P
I
T
C
F
G
C
H
B
C
H
A
Payload Length
Received
1
R
E
S
P
P
I
N
F
I
S
Y
N
S
F
I
R
C
I
3
R
E
S
S
P
P
I
S
N
F
I
S
S
Y
N
S
S
F
I
S
R
C
I
S
7
Cycle Code
6
5
4
3
2
1
0
V
F
R
B
V
F
R
A
Frame ID
Payload Length
Configured
2
8
Tx Buffer: Header CRC Configured
Rx Buffer: Header CRC Received
Receive
Cycle Count
Data Pointer
F
T
B
Cycle Count Status
:
:
:
:
F
T
A
M
L
S
T
E
S
B
E
S
A
T
C
I
B
T
C
I
A
S
V
O
B
S
V
O
A
C
E
O
B
C
E
O
A
S
E
O
B
S
E
O
A
Frame Configuration
Filter Configuration
Message Buffer Control
Message RAM Configuration
Updated from received Frame
Message Buffer Status
unused
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Header 1 (Word 0)
Write access through WRHS1, read access through RDHS1:
• Frame ID- Slot counter filtering configuration
• Cycle Code- Cycle counter filtering configuration
• CHA, CHB- Channel filtering configuration
• CFG- Message buffer configuration: receive / transmit
• PPIT- Payload Preamble Indicator Transmit
• TXM- Transmit mode configuration: single-shot / continuous
• MBI- Message buffer receive / transmit interrupt enable
Header 2 (Word 1)
Write access through WRHS2, read access through RDHS2:
• Header CRC Transmit Buffer: Configured by the host (calculated from frame header)
– Receive Buffer: Updated from received frame
• Payload Length Configured: Length of data section (2-byte words) as configured by the host
• Payload Length Received: Length of payload segment (2-byte words) stored from received frame
Header 3 (Word 2)
Write access through WRHS3, read access through RDHS3:
• Data Pointer- Pointer to the beginning of the corresponding data section in the data partition
Read access through RDHS3, valid for receive buffers only, updated from received frames:
• Receive Cycle Count - Cycle count from received frame
• RCI- Received on Channel Indicator
• SFI- Startup Frame Indicator
• SYN- Sync Frame Indicator
• NFI- Null Frame Indicator
• PPI- Payload Preamble Indicator
• RES- REServed bit
Message Buffer Status MBS (Word 3)
Read access through MBS, updated by the communication controller at the end of the configured slot.
• VFRA- Valid Frame received on channel A
• VFRB- Valid Frame received on channel B
• SEOA- Syntax Error Observed on channel A
• SEOB- Syntax Error Observed on channel B
• CEOA- Content Error Observed on channel A
• CEOB- Content Error Observed on channel B
• SVOA- Slot Boundary Violation Observed on channel A
• SVOB- Slot Boundary Violation Observed on channel B
• TCIA- Transmission Conflict Indication channel A
• TCIB- Transmission Conflict Indication channel B
• ESA- Empty Slot Channel A
• ESB- Empty Slot Channel B
• MLST- Message Lost
• FTA- Frame Transmitted on Channel A
• FTB- Frame Transmitted on Channel B
• Cycle Count Status- Current cycle count when status was updated
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•
•
•
•
•
•
RCIS- Received on Channel Indicator Status
SFIS- Startup Frame Indication Status
SYNS- Sync Frame Indicator Status
NFIS- Null Frame Indicator Status
PPIS- Payload Preamble Indicator Status
RESS- Reserved Bit Status
23.17.1.2 Data Partition
The data partition of the message RAM stores the data sections of the message buffers configured for
reception / transmission as defined in the header partition. The number of data bytes for each message
buffer can vary from 0 to 254. In order to optimize the data transfer between the shift registers of the two
FlexRay protocol controllers and the message RAM as well as between the host interface and the
message RAM, the physical width of the message RAM is word wise (4 bytes).
The data partition starts right after the last word of the header partition. When configuring the message
buffers in the message RAM the programmer has to assure that the data pointers point to addresses
within the data partition.
Figure 23-25 shows an example how the payload of the configured message buffers can be stored in the
data partition of the message RAM. Message buffers 0 to 2 are static buffers with a payload of 3, whereas
message buffers 3 to n are dynamic buffers with variable payload.
The beginning of a message buffer’s data section is determined by the data pointer and the payload
length configured in the message buffer’s header section. This enables a flexible usage of the available
RAM space for storage of message buffers with different data lengths.
The storage of the payload data is word aligned. If the size of a message buffer payload is an odd number
of 2-byte words, the remaining 16 bits in the last 32-bit word are unused (see Figure 23-25).
Figure 23-25. Example Structure of Data Partition in Message RAM
Bit /
Word
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
2046
2047
31
24
MB0 Data3
unused
MB1 Data3
unused
MB2 Data3
unused
MB3 Data3
º
MB3 Data(k)
MBn Data3
º
º
MBn Data(m)
unused
unused
unused
unused
23
16
MB0 Data2
unused
MB1 Data2
unused
MB2 Data2
unused
MB3 Data2
º
MB3 Data(k-1)
MBn Data2
º
º
MBn Data(m-1)
unused
unused
unused
unused
15
8
MB0
MB0
MB1
MB1
MB2
MB2
MB3
Data1
Data5
Data1
Data5
Data1
Data5
Data1
º
MB3 Data(k-2)
MBn Data1
º
º
MBn Data(m-2)
unused
unused
unused
unused
7
0
MB0
MB0
MB1
MB1
MB2
MB2
MB3
Data0
Data4
Data0
Data4
Data0
Data4
Data0
º
MB3 Data(k-3)
MBn Data0
º
º
MBn Data(m-3)
unused
unused
unused
unused
23.17.2 Parity Check
In order to assure the integrity of the data stored in the different RAM blocks of the module (message
RAM, 2 transient buffer RAMs, 2 input buffer RAMs, 2 output buffer RAMs, Transfer Configuration RAM),
the FlexRay module RAMs are parity protected.
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The RAM blocks are parity protected and the parity protection cannot be disabled. Only the Transfer
Configuration RAM has the exceptional functionality that parity protection can either be switched on or off
by writing a 4 bit key to the dedicated parity lock bits (PEL) in the Global Control Register (GCS/R) of the
Transfer Unit register frame. By default the parity protection of the TCR is switched off.
Figure 23-26 shows the structure of the parity concerning enabling/disabling and error indication.
Figure 23-26. Parity Structure
PERRE
(EIES/R)
PERRL
(EILS)
CC_int1
CC_int0
EIR
PERR flag
FlexRay RAMs
E-Ray
Parity check
PEL(3-0)
(GCS/R1)
TCR Parity off
• Message RAM
• Transient Buffer RAM A
• Transient Buffer RAM B
• Input Buffer RAM
• Input Buffer Shadow RAM
• Output Buffer RAM
• Output Buffer Shadow RAM
Parity/ECC failure
TCR Parity on
faulty frame indication
faulty address indication
Transfer Unit
FMB(6-0)
(MHDS)
ADR(8-0)
(PEADR)
Parity/ECC failure
• Transfer Configuration RAM (TCR)
TEIF
PE flag
TU_PE_int
NOTE: For the seven RAM blocks of the Communication Controller portion (message RAM, 2
transient buffer RAMs, 2 input buffer RAMs and 2 output buffer RAMs) parity protection is
switched on, which can be selected by the parity lock bits (PEL). Parity protection cannot be
switched off completely. For the TCR of the Transfer Unit actually the parity error generation
will be switched on and off by the parity lock bits, the parity generation itself remains always
on.
The following sections describe the protection for the Communication Controller related RAM blocks.
All the RAM blocks have a parity generator and a parity checker attached as shown in Figure 23-27.
When data is written to a RAM block, the local parity generator generates the corresponding parity
information.
The parity is checked each time a data word is read from any of the RAM blocks. The module internal
data buses have a width of 32 bits. If a parity error is detected, the PERR error flag is set in the error
interrupt register (EIR). Additionally a parity error interrupt can be generated, if enabled by the PERRE bit
in the error interrupt enable register (EIES/EIER). The faulty message buffer number together with the
information of the failing RAM can be read from the message handler status (MHDS) register.
Figure 23-27 shows the data paths between the RAM blocks and the parity generators and parity
checkers.
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Figure 23-27. Parity Generation and Check
Input
Buffer
RAM 1,2
GEN
CHK
Message
RAM
CHK
GEN
Transient
Buffer
RAM A
CHK
GEN
PRT A
Transient
Buffer
RAM B
Output
Buffer
RAM 1,2
CHK
GEN
CHK
GEN
PRT B
GEN Parity Generator
CHKI Parity Checker
NOTE: The parity generator and parity checker are not part of the RAM blocks, but of the RAM
access logic.
For parity generation, the FlexRay module uses an even parity (with an even number of ones in the 32-bit
data word a zero parity bit is generated).
When a parity error has been detected the following actions will be performed:
In all cases
• The corresponding error flag in the message handler status (MHDS) register is set and the faulty
message buffer is indicated.
• The error flag EIR.PERR in the error interrupt register is set, and if enabled, a module interrupt to the
CPU will be generated.
Additionally in specific cases of parity errors:
1. Parity error during data transfer from input buffer RAM 1,2 ⇒ message RAM
a. Transfer of header and/or data section and parity error occurs during header and/or data section
transfer to message RAM:
• MHDS.PIBF bit is set
• MHDS.FMBD bit is set to indicate that MHDS.FMB points to a faulty message buffer
• MHDS.FMB indicates the number of the faulty message buffer
• Header and/or data section of the corresponding message buffer is updated
• Transmission request for the corresponding message buffer is not set (no transfer to the
FlexRay bus)
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3.
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5.
6.
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8.
9.
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b. Transfer of data section only and parity error occurs when reading header section of the
corresponding message buffer from the message RAM.
• MHDS.PMR bit is set
• MHDS.FMBD bit is set to indicate that MHDS.FMB points to a faulty message buffer
• MHDS.FMB indicates the number of the faulty message buffer
• The data section of the corresponding message buffer is not updated
• Transmission request for the corresponding message buffer is not set (no transfer to the
FlexRay bus)
Parity error during host CPU reading input buffer RAM 1,2
• MHDS.PIBF bit is set
Parity error during scan of header sections in message RAM
• MHDS.PMR bit is set
• MHDS.FMBD bit is set to indicate that MHDS.FMB points to a faulty message buffer
• MHDS.FMB indicates the number of the faulty message buffer
• Ignore message buffer (the transfer of the message buffer is skipped)
Parity error during data transfer from message RAM to transient buffer RAM 1,2
• MHDS.PMR bit is set
• MHDS.FMBD bit is set to indicate that MHDS.FMB points to the faulty message buffer
• MHDS.FMB indicates the number of the faulty message buffer
• Frame not transmitted, frames already in transmission are invalidated by setting the frame CRC to
zero
Parity error during data transfer from transient buffer RAM 1,2 to protocol controller 1, 2
• MHDS.PTBF1,2 bit is set
• Frames already in transmission are invalidated by setting the frame CRC to zero
Parity error during data transfer from transient buffer RAM 1,2 to message RAM
a. Parity error when reading header section of corresponding message buffer from message RAM
• MHDS.PMR bit is set
• MHDS.FMBD bit is set to indicate that MHDS.FMB points to a faulty message buffer
• MHDS.FMB indicates the number of the faulty message buffer
• The data section of the corresponding message buffer is not updated
b. Parity error when reading transient buffer RAM 1,2:
• MHDS.PTBF1,2 bit is set
• MHDS.FMBD bit is set to indicate that MHDS.FMB points to a faulty message buffer
• MHDS.FMB indicates the number of the faulty message buffer
• The data section of the corresponding message buffer is updated
Parity error during data transfer from message RAM to output buffer RAM
• MHDS.PMR bit is set
• MHDS.FMBD bit is set to indicate that MHDS.FMB points to faulty message buffer
• MHDS.FMB indicates the number of the faulty message buffer
• Header and/or data section of the output buffer is updated, but should not be used by the host
CPU
Parity error during host CPU reading output buffer RAM 1,2
• MHDS.POBF bit is set
Parity error during data read of transient buffer RAM 1,2. When a parity error occurs during when the
Message Handler reads a frame, with network management information (PPI = 1), from the transient
buffer RAM 1,2, the corresponding network management vector register NMV[1-3] is not updated from
that frame.
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23.17.2.1 Host Handling of Parity Errors
Parity errors caused by transient bit flips can be fixed by:
Self-healing
Parity errors located in:
• Input Buffer RAM 1,2
• Output Buffer RAM 1,2
• Data Section of Message RAM
• Transient Buffer RAM A
• Transient Buffer RAM B
• Transfer Configuration RAM (TCR)
are overwritten with the next write access to the disturbed bit(s) caused by host access or by FlexRay
communication.
CLEAR_RAMS Command
When called in DEFAULT_CONFIG or CONFIG state POC command CLEAR_RAMS initializes all
module-internal RAMs to zero and the parity bits are initialized accordingly, depending what mode is
enabled.
Temporary Unlocking of Header Section
A parity error in the header section of a locked message buffer can be fixed by a transfer from the input
buffer to the locked buffer header section. For this transfer, the write-access to the IBCR (specifying the
message buffer number) must be immediately preceded by the unlock sequence normally used to leave
CONFIG state. For that single transfer the corresponding message buffer header is unlocked, regardless
whether it belongs to the FIFO or whether its locking is controlled by MRC.SEC, and will be updated with
new data.
NOTE: In case above methods do not work, it is recommended to execute the PBIST test at device
level to confirm a hard error in the module internal RAMs.
23.18 Interrupts
This section describes the transfer unit interrupts and the communication controller interrupts.
23.18.1 Transfer Unit Interrupts
23.18.1.1 Interrupt Structure
For transfer interrupts, one enable bit is provided for each bit in the transfer occurred status registers.
Maskable error interrupts are possible for all error conditions except parity error and memory protection
error.
The parity error and the memory protection error have separate non-maskable lines. Both turn off the
Transfer Unit after finishing the current word access cycle.
Figure 23-28 shows the interrupt structure of the FlexRay Transfer Unit.
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Figure 23-28. Transfer Unit (TU) Interrupt Structure
Flags
(TSMO 0/1/2/3,
TCCO 0/1/2/3)
Transfer
Interrupts
Interrupt Mask
(TSMIES/R 0/1/2/3,
TCCIES/R 0/1/2/3)
Transf
er
Transfer
Buffer 1
Transf er
Transfer
Buffer 2
Global Interrupt
Mask (GCS/R)
Transfer
Tran
sfe r
Buffer 128
Buffer
TU_Int0 to VIM
Error Interrupt
Flags (TEIF)
Error
Interrupts
Error Interrupt
Mask (TEIRES/R)
TU_Int1 to VIM
Forbidden
Access
Acces s
Transfer
Transf er
not ready
VBUS
read
VBUS
write
Uncorrectable
Uncorrectable
1104
TCR error
TCR
TU_UCT_err to ESM
Memor
Memoryy
Protection
Violation
TU_MPV_err to ESM
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23.18.1.2 Enable Interrupts
The TSMIES/TSMIER and TCCIES/TCCIER registers control the buffer transfer interrupts for each buffer
in both directions. The TEIRES/TEIRER registers control the maskable error interrupt sources that are:
• VBUS transaction errors
If an error occurs during VBUS read or write transfer a error interrupt will be generated.
• Forbidden access to IBF or OBF
Since host accesses to communication controller through the IBF and the OBF (0x400-0x7FF) are
forbidden, as long as the Transfer Unit State Machine is enabled, accesses will be ignored and an
error interrupt will be generated.
• Transfer not ready when TBA should be loaded
When a transfer is ongoing/pending during base address reload on FlexRay communication cycle start
(only occurs if NTBA != TBA) the TBA will not be loaded and an error interrupt will be generated.
The transfer interrupts use a separate interrupt line (TU_int0) than the error interrupts (TU_int1).
23.18.1.3 Interrupt Flags
The TSMO and TCCO flags indicate buffer transfer status interrupts whereas the TEIF flags indicate
interrupt sources for maskable and non-maskable error interrupts.
The error interrupt flags are set by the Transfer Unit State Machine and can be cleared by the CPU by
writing a 1. If the CPU clears the flag, while the Transfer Unit State Machine sets it at the same time, the
flag remains set.
23.18.1.4 Non Maskable Error Indication
Memory protection violation and uncorrectable TCR error have their own non maskable error lines, which
can be connected to the Vectored Interrupt Module (VIM) and/or the Error Signaling Module (ESM).
Please refer to the device-specific data manual on the hookup.
• If a memory protection violation occurs the Memory Protection Violation Error (TU_MPV_err) line will
be activated.
• If a uncorrectable TCR error occurs while accessing the TCR, the Parity Error (TU_UCT_err) line will
be activated.
23.18.2 Communication Controller Interrupts
In general, interrupts provide a close link to the protocol timing as they are triggered almost immediately
when an error or status change is detected by the controller, a frame is received or transmitted, a
configured timer interrupt is activated, or a stop watch event occurred. This enables the host CPU to react
very quickly on specific error conditions, status changes, or timer events. To remain flexible though, the
communication controller supports disable / enable controls for each individual interrupt source separately.
An interrupt may be triggered, for example when:
• a frame is received or transmitted
• an error was detected
• a status flag is set
• a timer reaches a preconfigured value
• a message transfer from input buffer to message RAM or from message RAM to output buffer has
completed
• a stop watch event occurred
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Figure 23-29. Communication Controller (CC) Interrupt Structure
Interrupt
Source 1
Status/Error
Interrupt Enable
Set/Clear
(SIES/EIES, SIER/
EIER
Status/Error
Interrupt Line
Select
(SILS/EILS)
0
Interrupt Line
Enable
EINT0
CC_int0
EINT1
Interrupt
Line 1
1
Interrupt
Source 2
0
1
Interrupt
Line 0
CC_int1
Status/Error
Interrupt
Register
(SIR/EIR
Source 1
Flag
Source 2
Flag
Timer 0
Interrupt
CC_tint0
Timer 1
Interrupt
CC_tint1
Tracking status and generating interrupts when a status change or an error occurs are two independent
tasks. Independent of an interrupt being enabled, the corresponding status is tracked and indicated by the
Communication Controller. The host has access to the current status and error information by reading the
error interrupt register and the status interrupt register.
The interrupt lines to the host, CC_int0 and CC_int1, are controlled by the enabled interrupts. In addition
each of the two interrupt lines to the host CPU can be enabled / disabled separately by programming bit
EINT0 and EINT1 in the Interrupt Line Enable register.
The two timer interrupts generated by interrupt timer 0 and 1 are available on pins CC_tint0 and CC_tint1.
They can be configured via the timer 0 and timer 1 configuration register.
When a transfer between IBF / OBF and the Message RAM has completed bit SIR.TIBC or SIR.TOBC is
set.
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Table 23-16. Module Interrupt Flags and Interrupt Line Enable
Register
Bit
Function
EIR
PEMC
Protocol error Mode Changed
CNA
Command Not Valid
SFBM
Sync Frames Below Minimum
SFO
Sync Frame Overflow
CCF
Clock Correction Failure
CCL
CHI Command Locked
PERR
Parity error
RFO
Receive FIFO Overrun
EFA
Empty FIFO Access
IIBA
Illegal Input Buffer Access
IOBA
Illegal Output Buffer Access
MHF
Message Handler Constraints Flag
EDA
Error Detected on Channel A
LTVA
Latest Transmit Violation Channel A
TABA
Transmission Across Boundary Channel A
EDB
Error Detected on Channel B
LTVB
Latest Transmit Violation Channel B
TABB
Transmission Across Boundary Channel B
WST
Wakeup Status
CAS
Collision Avoidance Symbol
CYCS
Cycle Start Interrupt
TXI
Transmit Interrupt
RXI
Receive Interrupt
RFNE
Receive FIFO not Empty
RFCL
Receive FIFO Critical Level
NMVC
Network Management Vector Changed
TI0
Timer Interrupt 0
TI1
Timer Interrupt 1
TIBC
Transfer Input Buffer Completed
TOBC
Transfer Output Buffer Completed
SWE
Stop Watch Event
SUCS
Startup Completed Successfully
MBSI
Message Buffer Status Interrupt
SDS
Start of Dynamic Segment
WUPA
Wakeup Pattern Channel A
MTSA
MTS Received on Channel A
WUPB
Wakeup Pattern Channel B
MTSB
MTS Received on Channel B
EINT0
Enable Interrupt Line 0
EINT1
Enable Interrupt Line 1
SIR
ILE
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23.19 FlexRay Module Registers
23.19.1 Transfer Unit Registers
Table 23-17 provides a summary of the registers. All registers are organized as 32-bit registers. 32/16/8bit accesses are supported. For FlexRayTU transfers only, 4 × 32-bit data packages are supported. The
base address for the Transfer Unit registers is FFF7 A000h.
The Transfer Unit State Machine registers use the offset address range 00 to 1FCh.
Transfer Configuration RAM uses the offset address range 00 to 1FCh in normal mode and 00 to 3FCh in
parity test mode from the base address of FF50 0000h.
Table 23-17. Transfer Unit Registers
Offset Address Acronym
Register Description
Section
00h
GSN0
Global Static Number 0
Section 23.19.1.1
04h
GSN1
Global Static Number 1
Section 23.19.1.2
Reserved
Reserved
10h
GCS
Global Control Set
Section 23.19.1.3
14h
GCR
Global Control Reset
Section 23.19.1.3
18h
TSCB
Transfer Status Current Buffer
Section 23.19.1.4
1Ch
LTBCC
Last Transferred Buffer to Communication Controller
Section 23.19.1.5
20h
LTBSM
Last Transferred Buffer to System Memory
Section 23.19.1.6
24h
TBA
Transfer Base Address
Section 23.19.1.7
28h
NTBA
Next Transfer Base Address
Section 23.19.1.8
2Ch
BAMS
Base Address of Mirrored Status
Section 23.19.1.9
30h
SAMP
Start Address of Memory Protection
Section 23.19.1.10
34h
EAMP
End Address of Memory Protection
Section 23.19.1.11
Reserved
Reserved
40h
TSMO1
Transfer to System Memory Occurred 1
Section 23.19.1.12
44h
TSMO2
Transfer to System Memory Occurred 2
Section 23.19.1.12
48h
TSMO3
Transfer to System Memory Occurred 3
Section 23.19.1.12
4Ch
TSMO4
Transfer to System Memory Occurred 4
Section 23.19.1.12
50h
TCCO1
Transfer to Communication Controller Occurred 1
Section 23.19.1.13
54h
TCCO2
Transfer to Communication Controller Occurred 2
Section 23.19.1.13
08h-0Ch
38h-3Ch
58h
TCCO3
Transfer to Communication Controller Occurred 3
Section 23.19.1.13
5Ch
TCCO4
Transfer to Communication Controller Occurred 4
Section 23.19.1.13
60h
TOOFF
Transfer Occurred Offset
Section 23.19.1.14
Reserved
Reserved
70h
PEADR
Parity Error Address
Section 23.19.1.15
74h
TEIF
Transfer Error Interrupt
Section 23.19.1.16
78h
TEIRES
Transfer Error Interrupt Enable Set
Section 23.19.1.17
7Ch
TEIRER
Transfer Error Interrupt Enable Reset
Section 23.19.1.17
80h
TTSMS1
Trigger Transfer to System Memory Set 1
Section 23.19.1.18
84h
TTSMR1
Trigger Transfer to System Memory Reset 1
Section 23.19.1.18
64h-6Ch
88h
TTSMS2
Trigger Transfer to System Memory Set 2
Section 23.19.1.18
8Ch
TTSMR2
Trigger Transfer to System Memory Reset 2
Section 23.19.1.18
90h
TTSMS3
Trigger Transfer to System Memory Set 3
Section 23.19.1.18
94h
TTSMR3
Trigger Transfer to System Memory Reset 3
Section 23.19.1.18
98h
TTSMS4
Trigger Transfer to System Memory Set 4
Section 23.19.1.18
9Ch
TTSMR4
Trigger Transfer to System Memory Reset 4
Section 23.19.1.18
A0h
TTCCS1
Trigger Transfer to Communication Controller Set 1
Section 23.19.1.19
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Table 23-17. Transfer Unit Registers (continued)
Offset Address Acronym
Register Description
Section
A4h
TTCCR1
Trigger Transfer to Communication Controller Reset 1
Section 23.19.1.19
A8h
TTCCS2
Trigger Transfer to Communication Controller Set 2
Section 23.19.1.19
ACh
TTCCR2
Trigger Transfer to Communication Controller Reset 2
Section 23.19.1.19
B0h
TTCCS3
Trigger Transfer to Communication Controller Set 3
Section 23.19.1.19
B4h
TTCCR3
Trigger Transfer to Communication Controller Reset 3
Section 23.19.1.19
B8h
TTCCS4
Trigger Transfer to Communication Controller Set 4
Section 23.19.1.19
BCh
TTCCR4
Trigger Transfer to Communication Controller Reset 4
Section 23.19.1.19
C0h
ETESMS1
Enable Transfer on Event to System Memory Set 1
Section 23.19.1.20
C4h
ETESMR1
Enable Transfer on Event to System Memory Reset 1
Section 23.19.1.20
C8h
ETESMS2
Enable Transfer on Event to System Memory Set 2
Section 23.19.1.20
CCh
ETESMR2
Enable Transfer on Event to System Memory Reset 2
Section 23.19.1.20
D0h
ETESMS3
Enable Transfer on Event to System Memory Set 3
Section 23.19.1.20
D4h
ETESMR3
Enable Transfer on Event to System Memory Reset 3
Section 23.19.1.20
D8h
ETESMS4
Enable Transfer on Event to System Memory Set 4
Section 23.19.1.20
DCh
ETESMR4
Enable Transfer on Event to System Memory Reset 4
Section 23.19.1.20
E0h
CESMS1
Clear on Event to System Memory Set 1
Section 23.19.1.21
E4h
CESMR1
Clear on Event to System Memory Reset 1
Section 23.19.1.21
E8h
CESMS2
Clear on Event to System Memory Set 2
Section 23.19.1.21
ECh
CESMR2
Clear on Event to System Memory Reset 2
Section 23.19.1.21
F0h
CESMS3
Clear on Event to System Memory Set 3
Section 23.19.1.21
F4h
CESMR3
Clear on Event to System Memory Reset 3
Section 23.19.1.21
F8h
CESMS4
Clear on Event to System Memory Set 4
Section 23.19.1.21
FCh
CESMR4
Clear on Event to System Memory Reset 4
Section 23.19.1.21
100h
TSMIES1
Transfer to System Memory Interrupt Enable Set 1
Section 23.19.1.22
104h
TSMIER1
Transfer to System Memory Interrupt Enable Reset 1
Section 23.19.1.22
108h
TSMIES2
Transfer to System Memory Interrupt Enable Set 2
Section 23.19.1.22
10Ch
TSMIER2
Transfer to System Memory Interrupt Enable Reset 2
Section 23.19.1.22
110h
TSMIES3
Transfer to System Memory Interrupt Enable Set 3
Section 23.19.1.22
114h
TSMIER3
Transfer to System Memory Interrupt Enable Reset 3
Section 23.19.1.22
118h
TSMIES4
Transfer to System Memory Interrupt Enable Set 4
Section 23.19.1.22
11Ch
TSMIER4
Transfer to System Memory Interrupt Enable Reset 4
Section 23.19.1.22
120h
TCCIES1
Transfer to Communication Controller Interrupt Enable Set 1
Section 23.19.1.23
124h
TCCIER1
Transfer to Communication Controller Interrupt Enable Reset 1
Section 23.19.1.23
128h
TCCIES2
Transfer to Communication Controller Interrupt Enable Set 2
Section 23.19.1.23
12Ch
TCCIER2
Transfer to Communication Controller Interrupt Enable Reset 2
Section 23.19.1.23
130h
TCCIES3
Transfer to Communication Controller Interrupt Enable Set 3
Section 23.19.1.23
134h
TCCIER3
Transfer to Communication Controller Interrupt Enable Reset 3
Section 23.19.1.23
138h
TCCIES4
Transfer to Communication Controller Interrupt Enable Set 4
Section 23.19.1.23
13Ch
TCCIER4
Transfer to Communication Controller Interrupt Enable Reset 4
Section 23.19.1.23
140h-1FCh
Reserved
Reserved
TCR
Transfer Configuration RAM
Section 23.19.1.24
TCR Parity
TCR Parity Test Mode
Section 23.19.1.25
0-1FCh
200h-3FCh
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23.19.1.1 Global Static Number 0 (GSN0)
This register contains a constant to check correctness of data transfers.
Figure 23-30. Global Static Number 0 (GSN0) [offset_TU = 00h]
31
16
Data_A
R-0x5432
15
0
Data_B
R-0xABCD
LEGEND: R = Read only; -n = value after reset
Table 23-18. Global Static Number 0 (GSN0) Field Descriptions
Bit
Field
Value
Description
31-16
Data_A
0-FFFFh Data_A
15-0
Data_B
0-FFFFh Complement of Data_A
23.19.1.2 Global Static Number 1 (GSN1)
This register contains a constant to check correctness of data transfers.
Figure 23-31. Global Static Number 1 (GSN1) [offset_TU = 04h]
31
16
Data_C
R-0xABCD
15
0
Data_D
R-0x5432
LEGEND: R = Read only; -n = value after reset
Table 23-19. Global Static Number 1 (GSN1) Field Descriptions
Bit
Field
Value
Description
31-16
Data_C
0-FFFFh Data_C
15-0
Data_D
0-FFFFh Complement of Data_C
1110
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23.19.1.3 Global Control Set/Reset (GCS/GCR)
The GCx Registers reflects the configuration mode and allows to configure the basic Transfer Unit
behavior.
The GCx registers consist of a set register (GCS) and a reset register (GCR). Bits are set by writing 1 to
GCS and reset by writing 1 to GCR. Writing a 0 has no effect. Reading from both addresses will result in
the same value.
Figure 23-32. Global Control Set (GCS) [offset_TU = 10h]
31
30
ENDVBM
ENDVBS
29
ENDR
28
27
ENDH
26
25
ENDP
R/W1S-0
R/W1S-0
R/W1S-0
R/W1S-0
R/W1S-0
23
22
21
20
Reserved
PRIO
PEFT
PEL
R-0
R/W1S-0
R/W1S-0
R/W1S-5h
24
19
16
15
14
13
12
Reserved
CETESM
CTTCC
CTTSM
Reserved
ETSM
R-0
R/W1S-0
R/W1S-0
R/W1S-0
R-0
R/W1S-0
7
6
11
9
3
2
8
5
4
1
0
Reserved
SILE
EILE
Reserved
TUH
TUE
R-0
R/W1S-0
R/W1S-0
R-0
R/W1S-0
R/W1S-0
LEGEND: R/W = Read/Write; R = Read only; W1S = Write 1 to set (writing a 0 has no effect); -n = value after reset
NOTE: For Global Control Reset (GCR) bit descriptions, see Table 23-20.
Figure 23-33. Global Control Reset (GCR) [offset_TU = 14h]
31
30
29
28
27
26
25
ENDVBM
ENDVBS
ENDR
ENDH
ENDP
R/W1S-0
R/W1S-0
R/W1S-0
R/W1S-0
R/W1S-0
23
22
21
20
Reserved
PRIO
PEFT
PEL
R-0
R/W1S-0
R/W1S-0
R/W1S-5h
24
19
16
15
14
13
12
Reserved
CETESM
CTTCC
CTTSM
11
Reserved
9
ETSM
R-0
R/W1S-0
R/W1S-0
R/W1S-0
R-0
R/W1S-0
7
6
5
4
3
2
8
1
0
Reserved
SILE
EILE
Reserved
TUH
TUE
R-0
R/W1S-0
R/W1S-0
R-0
R/W1S-0
R/W1S-0
LEGEND: R/W = Read/Write; R = Read only; W1S = Write 1 to set (writing a 0 has no effect); -n = value after reset
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Table 23-20. Global Control Set/Reset (GCS/GCR) Field Descriptions
Bit
Field
31
ENDVBM
30
29-28
Value
Description
Endianness Correction on VBusp Master
0
Endianness correction switched off (Endianness is default: Little Endianness equal to Big Endian
word invariant (ARM:BE-32), same as all other peripherals) (Example 32 Bit Word = ABCD).
1
Endianness correction switched on (E-Ray Register, Header and Payload Endianness is according
the configuration of bits ENDR0/1 ENDH0/1, ENDP0/1).
ENDVBS
Endianness correction on VBusp Slave
0
Endianness correction switched off (Endianness is default: Little Endianness equal to Big Endian
word invariant (ARM:BE-32), same as all other peripherals) Example 32 Bit Word = ABCD.
1
Endianness correction switched on (E-Ray Register, Header and Payload Endianness is according
the configuration of bits ENDR0/1, ENDH0/1, ENDP0/1).
ENDRx
Endianness Correction for No (header or payload) Data Sink Access
Byte-order control of CPU access to E-Ray register, Transfer Unit register and Transfer Unit ram
data. Data transferred between CPU and data sink will be corrected.
27-26
25-24
23-22
21
20
19-16
0
Remapped to ABCDh.
1h
Remapped to BADCh.
2h
Remapped to CDABh.
3h
Remapped to DCBAh.
ENDHx
Endianness Correction for Header
0
Remapped to ABCDh.
1h
Remapped to BADCh.
2h
Remapped to CDABh.
3h
Remapped to DCBAh.
ENDPx
Reserved
Endianness Correction for Payload
0
Remapped to ABCDh.
1h
Remapped to BADCh.
2h
Remapped to CDABh.
3h
Remapped to DCBAh.
0
Reads return 0. Writes have no effect.
PRIO
Transfer Priority
0
TTSM gets higher priority than TTCC.
1
TTCC gets higher priority than TTSM.
PEFT
Parity for Test
0
Do not use parity test feature. TCRP not readable and writable.
1
Use test feature for testing parity mechanism. TCRP is readable and writable.
PEL
Parity Lock
5h
Others
Parity protection for TCR is switched off. Parity protection remains activated for message RAM,
transient buffer RAMs, input buffer RAMs and output buffer RAMs.
Parity protection for TCR is switched on. Parity protection is activated for message RAM, transient
buffer RAMs, input buffer RAMs and output buffer RAMs.
Note: For TCR, PEL enables/disables the parity error interrupt generation. While the parity feature
is disabled the parity generation is still ongoing and the error indication by the parity interrupt flag
(PE) in the Transfer Error Interrupt Flag register (TEIF) remains active. Only the parity interrupt
generation gets disabled.
15
Reserved
14
CETESM
0
Reads return 0. Writes have no effect.
Clear ETESM Register
Clear all bits of Enable Transfer on Event to System Memory register.
13
1112
0
Do not clear the register.
1
Clear the register when bit is set from 0 to 1.
CTTCC
Clear TTCC Register
0
Do not clear the register.
1
Clear the register when bit is set from 0 to 1.
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Table 23-20. Global Control Set/Reset (GCS/GCR) Field Descriptions (continued)
Bit
Field
12
CTTSM
11-9
8
Value
Reserved
Description
Clear TTSM Register
0
Do not clear the register.
1
Clear the register when bit is set from 0 to 1.
0
Reads return 0. Writes have no effect.
ETSM
Enable Transfer Status Mirrored
Mirror technique must be adjustable.
7-6
5
Reserved
0
Disable mirror function for TSCB, LTBCC, LTBSM, TSMO1-4, TCCO1-4, and TOOFF.
1
Enable mirror function for TSCB, LTBCC, LTBSM, TSMO1-4, TCCO1-4, and TOOFF.
0
Reads return 0. Writes have no effect.
SILE
Status Interrupt Line Enable
Enable/Disable status line interrupt.
4
0
TU_Int0 is disabled.
1
TU_Int0 is enabled.
EILE
Error Interrupt Line Enable
Enable/Disable error interrupt line.
3-2
1
Reserved
0
TU_Int1 is disabled.
1
TU_Int1 is enabled.
0
Reads return 0. Writes have no effect.
TUH
Transfer Unit Halted
When halted, the Transfer Unit State Machine finishes the ongoing VBUSM access before it stops
working. After deassertion, the Transfer Unit State Machine continues at the point it was halted
before. No reconfiguration is required.
0
Transfer Unit is not halted.
1
Transfer Unit is halted.
Note: If the Transfer Unit State Machine halts, all mirroring registers contained the last
transfer not the current transfer information.
0
TUE
Transfer Unit Enabled
Enable/Disable transfer unit.
0
Transfer Unit is disabled, reset Transfer Unit State Machine, completion of the current VBUS
transfer cycle but data could be corrupt.
1
Transfer Unit is enabled.
Note: Before switching on the Transfer Unit, the registers must be set up. After re-enabling
of the Transfer Unit State Machine the contents of the module registers and the TCR is still
valid (assuming it was continuously powered).
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23.19.1.4 Transfer Status Current Buffer (TSCB)
The Transfer Status Current Buffer displays the current buffer in progress and indicates if the Transfer
Unit State Machine is idle and is halt. The IDLE flag is cleared by writing a 1 to it.
Figure 23-34. Transfer Status Current Buffer (TSCB) [offset_TU = 18h]
31
21
15
13
12
20
16
Reserved
TSMS
R-0
R-0
8
7
Reserved
STUH
11
Reserved
9
IDLE
Rsvd
6
BN
0
R-0
R-0
R-0
R/W1
C-1
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing 0 has no effect); -n = value after reset
Table 23-21. Transfer Status Current Buffer (TSCB) Field Descriptions
Bit
Field
31-21
Reserved
20-16
TSMS
Value
0
Description
Reads return 0. Writes have no effect.
Transfer State Machine Status
Reflects the current status of the transfer state machine for debug purpose (only available in
debug mode in combination with a debugger). In Normal Operation Mode the value of TSMS is
always read as 0.
1h
IDLE state
Transfer Trigger to System Memory:
2h
Start state (TTSM_START)
3h
Output Buffer Command Mask access state (TTSM_OBCM)
4h
Request state (TTSM_REQ)
5h
View state (TTSM_VIEW)
6h
Check state (TTSM_CHECK)
7h
Read Header Section access state (TTSM_RDHS)
8h
Read Data Section access state (TTSM_RDDS)
Transfer Trigger to Communication Controller:
9h
Start state (TTCC_START)
Ah
Busy state (TTCC_IBUSY)
Bh
Check state (TTCC_CHECK)
Ch
Write Header Section access state (TTCC_WRHS)
Dh
Payload Read state (TTCC_PLC_READ)
Eh
Payload Calculation state (TTCC_PLC_CALC)
Fh
Write Data Section access state (TTCC_WRDS)
10h
Input Buffer Command Mask access state (TTCC_IBCM)
11h
Input Buffer Command Request access state (TTCC_IBCR)
12h
Mirror state (TTCC_MIRROR)
13h
End state (TTSM_END)
14h-1Eh
1Fh
15-13
12
11-9
1114
Reserved
0
STUH
Reserved
Reserved
Undefined state
Reads return 0. Writes have no effect.
Status of Transfer Unit State Machine for Halt Detection
0
Not in HALT status.
1
In HALT status.
0
Reads return 0. Writes have no effect.
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Table 23-21. Transfer Status Current Buffer (TSCB) Field Descriptions (continued)
Bit
Field
8
IDLE
Value
Description
Detects Transfer State Machine State IDLE
Will be set if the transfer unit state machine is in IDLE state and ready to start the next transfer,
but nothing is requested.
7
6-0
Reserved
BN
0
IDLE state is not reached since last clear.
1
IDLE state is reached.
0
Reads return 0. Writes have no effect.
0-7Fh
Buffer Number
7-bit value of buffer number, which is currently in transfer. If state machine enters IDLE mode, the
last transferred buffer number is shown.
23.19.1.5 Last Transferred Buffer to Communication Controller (LTBCC)
Shows the number of the last completely transferred message buffer from system memory to the
communication controller.
Figure 23-35. Last Transferred Buffer to Communication Controller (LTBCC) [offset_TU = 1Ch]
31
7
6
0
Reserved
BN
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 23-22. Last Transferred Buffer to Communication Controller (LTBCC) Field Descriptions
Bit
Field
Value
31-7
Reserved
6-0
BN
0
0-7Fh
Description
Reads return 0. Writes have no effect.
Buffer number.
7-bit value of last completely transferred message buffer from system memory to the communication
controller.
23.19.1.6 Last Transferred Buffer to System Memory (LTBSM)
Shows the number of the last completely transferred message buffer from communication controller to the
system memory.
Figure 23-36. Last Transferred Buffer to System Memory (LTBSM) [offset_TU = 20h]
31
7
6
0
Reserved
BN
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 23-23. Last Transferred Buffer to System Memory (LTBSM) Field Descriptions
Bit
Field
31-7
Reserved
6-0
BN
Value
0
0-7Fh
Description
Reads return 0. Writes have no effect.
Buffer number.
7-bit value of last completely transferred message buffer from system memory to the communication
controller to the system memory.
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23.19.1.7 Transfer Base Address (TBA)
The Transfer Base Address register holds a 32-bit aligned 32-bit base-pointer, which defines the base
address for the data to be transferred.
NOTE: A write to this register also modifies the NTBA register.
Figure 23-37. Transfer Base Address (TBA) [offset_TU = 24h]
31
16
TBA
R/W-0
15
0
TBA
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 23-24. Transfer Base Address (TBA) Field Descriptions
Bit
Field
Value
31-0
TBA
0-FFFF FFFFh
Description
Transfer Base Address. 32-bit base pointer, 2 LSBs are not significant (32-bit accesses
only) and will always be 0.
23.19.1.8 Next Transfer Base Address (NTBA)
The Next Transfer Base Address holds a 32-bit aligned 32-bit base-pointer to be loaded into TBA during
next cycle start.
NOTE: A write on TBA register also modifies the NTBA register.
Figure 23-38. Next Transfer Base Address (NTBA) [offset_TU = 28h]
31
16
NTBA
R/W-0
15
0
NTBA
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 23-25. Next Transfer Base Address (NTBA) Field Descriptions
Bit
Field
Value
31-0
NTBA
0-FFFF FFFFh
1116
Description
Next Transfer Base Address. 32-bit base pointer, 2 LSBs are not significant (32-bit
accesses only) and will always be 0.
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23.19.1.9 Base Address of Mirrored Status (BAMS)
The Base Address of Mirrored Status holds a 32-bit aligned 32-bit base-pointer to be use for mirror
transactions. Further details about the transfer mirror mechanism can be found in Section 23.5.1.7.
Figure 23-39. Base Address of Mirrored Status (BAMS) [offset_TU = 2Ch]
31
16
BAMS
R/W-0
15
0
BAMS
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 23-26. Base Address of Mirrored Status (BAMS) Field Descriptions
Bit
Field
Value
31-0
BAMS
0-FFFF FFFFh
Description
Base Address of Mirrored Status. 32-bit base pointer, 2 LSBs are not significant (32-bit
accesses only) and will always be 0.
23.19.1.10 Start Address of Memory Protection (SAMP)
The Start Address of Memory Protection hold a 32bit address.
Figure 23-40. Start Address of Memory Protection (SAMP) [offset_TU = 30h]
31
16
SAMP
R/W-0
15
0
SAMP
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 23-27. Start Address of Memory Protection (SAMP) Field Descriptions
Bit
Field
Value
31-0
SAMP
0-FFFF FFFFh
Description
Start Address Memory Protection.
Start address of the memory area, which allows read and write accesses for the Transfer
Unit State Machine. 32-bit base pointer, 2 LSBs are not significant (32-bit accesses only)
and will always be 0.
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23.19.1.11 End Address of Memory Protection (EAMP)
The End Address of Memory Protection hold a 32bit address.
Figure 23-41. End Address of Memory Protection (EAMP) [offset_TU = 34h]
31
16
EAMP
R/W-0
15
0
EAMP
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 23-28. End Address of Memory Protection (EAMP) Field Descriptions
Bit
Field
Value
31-0
EAMP
0-FFFF FFFFh
Description
End Address Memory Protection.
End address of the memory area, which allows read and write accesses for the Transfer
Unit State Machine. 32-bit address, 2 LSBs are not significant (32-bit accesses only) and
will always be 0.
1118
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23.19.1.12 Transfer to System Memory Occurred (TSMO[1-4])
The Transfer to System Memory Occurred register reflects the message buffer transfer status for a
transfer transaction to the system memory. Four 32-bit registers reflect all possible 128 message buffers.
NOTE: Writing 1 will clear a bit. Writing 0 will leave a bit unchanged.
Figure 23-42. Transfer to System Memory Occurred 1 (TSMO1) [offset_TU = 40h]
31
16
TSMO1[31-16]
R/W1C-0
15
0
TSMO1[15-0]
R/W1C-0
LEGEND: R/W = Read/Write; W1C = Write 1 to clear (writing 0 has no effect); -n = value after reset
Figure 23-43. Transfer to System Memory Occurred 2 (TSMO2) [offset_TU = 44h]
31
16
TSMO2[63-48]
R/W1C-0
15
0
TSMO2[47-32]
R/W1C-0
LEGEND: R/W = Read/Write; W1C = Write 1 to clear (writing 0 has no effect); -n = value after reset
Figure 23-44. Transfer to System Memory Occurred 3 (TSMO3) [offset_TU = 48h]
31
16
TSMO3[95-80]
R/W1C-0
15
0
TSMO3[79-64]
R/W1C-0
LEGEND: R/W = Read/Write; W1C = Write 1 to clear (writing 0 has no effect); -n = value after reset
Figure 23-45. Transfer to System Memory Occurred 4 (TSMO4) [offset_TU = 4Ch]
31
16
TSMO4[127-112]
R/W1C-0
15
0
TSMO4[111-96]
R/W1C-0
LEGEND: R/W = Read/Write; W1C = Write 1 to clear (writing 0 has no effect); -n = value after reset
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Table 23-29. Transfer to System Memory Occurred (TSMOn) Field Descriptions
Bit
31-0
Field
Value
TSMO(1-4)[n]
Description
Transfer to System Memory Occurred Register
The register bits correspond to message buffers 0 to 127. Each bit of the register reflects a finished
message buffer transfer to the system memory.
1120
0
No transfer occurred.
1
Transfer occurred.
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23.19.1.13 Transfer to Communication Controller Occurred (TCCO[1-4])
The Transfer to Communication Controller Occurred reflects the message buffer transfer status for a
VBUSP master transfer transaction from the system memory. Four 32-bit registers reflect all possible 128
message buffers.
NOTE: Writing 1 will clear a bit. Writing 0 will leave a bit unchanged.
Figure 23-46. Transfer to Communication Controller Occurred 1 (TCCO1) [offset_TU = 50h]
31
16
TCCO1[31-16]
R/W1C-0
15
0
TCCO1[15-0]
R/W1C-0
LEGEND: R/W = Read/Write; W1C = Write 1 to clear (writing 0 has no effect); -n = value after reset
Figure 23-47. Transfer to Communication Controller Occurred 2 (TCCO2) [offset_TU = 54h]
31
16
TCCO2[63-48]
R/W1C-0
15
0
TCCO2[47-32]
R/W1C-0
LEGEND: R/W = Read/Write; W1C = Write 1 to clear (writing 0 has no effect); -n = value after reset
Figure 23-48. Transfer to Communication Controller Occurred 3 (TCCO3) [offset_TU = 58h]
31
16
TCCO3[95-80]
R/W1C-0
15
0
TCCO3[79-64]
R/W1C-0
LEGEND: R/W = Read/Write; W1C = Write 1 to clear (writing 0 has no effect); -n = value after reset
Figure 23-49. Transfer to Communication Controller Occurred 4 (TCCO4) [offset_TU = 5Ch]
31
16
TCCO4[127-112]
R/W1C-0
15
0
TCCO4[111-96]
R/W1C-0
LEGEND: R/W = Read/Write; W1C = Write 1 to clear (writing 0 has no effect); -n = value after reset
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Table 23-30. Transfer to Communication Controller Occurred (TCCOn) Field Descriptions
Bit
31-0
Field
Value
TCCO(1-4)[n]
Description
Transfer to Communication Controller Occurred Register
The register bits correspond to message buffers 0 to 127. Each bit of the register reflects a finished
message buffer transfer from the system memory.
1122
0
No transfer occurred.
1
Transfer occurred.
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23.19.1.14 Transfer Occurred Offset (TOOFF)
The Transfer Occurred Offset register contains the offset vector to the highest prior pending transfer
occurred interrupt and the transfer direction.
After a read access, the transfer occurred flag is cleared and the register contents are updated
automatically.
Figure 23-50. Transfer Occurred Offset (TOOFF) [offset_TU = 60h]
31
16
Reserved
R-0
15
9
8
7
0
Reserved
TDIR
OFF
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 23-31. Transfer Occurred Offset (TOOFF) Field Descriptions
Bit
31-9
8
7-0
Field
Value
Reserved
0
TDIR
Description
Reads return 0. Writes have no effect.
Transfer Direction. In case the same interrupt occurs for communication controller and Transfer
Unit State Machine transfers the PRIO bit in the Global Control register decides about the
higher priority.
0
A transfer to System Memory occurred.
1
A transfer to the Communication Controller occurred.
OFF
Offset Vector
0
Offset is not valid (no transfer occurred, interrupt is pending).
1h
Interrupt is pending for buffer 0.
2h
Interrupt is pending for buffer 1.
3h
Interrupt is pending for buffer 2.
:
80h
81h-FFh
:
Interrupt is pending for buffer 127.
Reserved
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23.19.1.15 Parity Error Address (PEADR)
After a parity error in the Transfer Configuration RAM occurred, the affected address is stored in this not
resettable register.
The contents of the Parity Error Address register as well as the PE bit in the Transfer Error Interrupt Flag
(TEIF) register is cleared automatically when reading the Parity Error Address register.
NOTE:
A parity error can only be indicated by the PE bit of TEIF register when the PEADR register
is cleared. Since the contents of PEADR are undefined after reset, it is recommended to
clear the register by reading it.
Figure 23-51. Parity Error Address (PEADR) [offset_TU = 70h]
31
9
8
0
Reserved
ADR
R-0
RC-U
LEGEND: R = Read only; RC = Clear on read; U = Undefined; -n = value after reset
Table 23-32. Parity Error Address (PEADR) Field Descriptions
Bit
Field
31-9
Reserved
8-0
ADR
Value
0
Description
Reads return 0. Writes have no effect.
0-1FFh Address of failing TCR location.
ADR(8-2) is the TCR word address were the parity error occurred.
ADR(1-0) can be used to find the failing byte in the TCR word the parity error occurred.
Table 23-33. Coding of Parity Error Address
Parity Error in Byte 2
Parity Error in Byte 1
Parity Error in Byte 0
(LSB)
ADR1
ADR0
-
-
1
0
1
NOTE:
1124
-
1
0
1
0
1
0
0
1
1
0
0
0
0
0
No Byte 3 is defined in TCR.
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23.19.1.16 Transfer Error Interrupt Flag (TEIF)
The Transfer Error Interrupt Flag register includes the Transfer Unit error flags. The bits in the TEIF are
cleared by writing a 1.
NOTE: Memory Protection Violation (MPV) and Parity Error (PE) interrupts are nonmaskable and
cannot be disabled. Therefore, the bits MPV and PE are not part of the Transfer Error
Interrupt Enable Set/Reset (TEIRES/TEIRER) registers.
Figure 23-52. Transfer Error Interrupt Flag (TEIF) [offset_TU = 74h]
31
18
15
11
17
16
Reserved
MPV
PE
R-0
R/W1C-0
R/W1C-0
1
0
Reserved
10
RSTAT
8
Rsvd
7
6
WSTAT
4
3
Reserved
2
TNR
FAC
R-0
R/W1C-0
R-0
R/W1C-0
R-0
R/W1C-0
R/W1C-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing 0 has no effect); -n = value after reset
Table 23-34. Transfer Error Interrupt Flag (TEIF) Field Descriptions
Bit
31-18
17
16
Field
Value
Reserved
0
MPV
Reserved
10-8
RSTAT
Reads return 0. Writes have no effect.
Memory Protection Violation.
0
No MPV occurred.
1
MPV occurred.
PE
15-11
Description
Parity Error. The flag signals a parity error to the host. The flag is set when a parity error in TCR is
detected.
0
No parity error occurred.
1
Parity error occurred.
0
Reads return 0. Writes have no effect.
Status of VBUS on read transfers.
0
Success.
1h
Addressing error.
2h
Protection error.
3h
Timeout error.
4h
Data error.
5h
Unsupported addressing mode error.
6h
Reserved
7h
Exclusive read failure.
Note: Any value other than 000 indicates a VBUS read error. The information of the specific VBUS
fault is for debug reasons only and is not relevant for normal usage.
7
Reserved
0
Reads return 0. Writes have no effect.
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Table 23-34. Transfer Error Interrupt Flag (TEIF) Field Descriptions (continued)
Bit
Field
6-4
WSTAT
Value
Description
Status of VBUS on write transfers.
0
Success.
1h
Addressing error.
2h
Protection error.
3h
Timeout error.
4h
Reserved.
5h
Unsupported addressing mode error.
6h
Reserved.
7h
Exclusive write failure.
Note: Any value other than 000 indicates a VBUS read error. The information of the specific VBUS
fault is for debug reasons only and is not relevant for normal usage.
3-2
1
0
1126
Reserved
0
TNR
Reads return 0. Writes have no effect.
Transfer Not Ready.
0
Transfer started and NTBA is loaded to TBA.
1
Transfer is not ready on communication cycle start and therefore NTBA is not loaded to TBA.
FAC
Forbidden Access.
0
No forbidden access occurred.
1
A forbidden CPU access to IBF or OBF occurred when the Transfer Unit State Machine is enabled.
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23.19.1.17 Transfer Error Interrupt Enable Set/Reset (TEIRES/TEIRER)
The Transfer Error Interrupt Enable Set controls the interrupt activation of interrupt line TU_Int1. An
interrupt is generated if both the interrupt flag in TEIF and the corresponding bit in TEIRES are set.
Exceptions are the memory protection violation (MPV) and the parity (PE) error, which are related to
nonmaskable interrupts and therefore are not part of the TEIRES/TEIRER registers. Those errors have
private error lines (TU_MPV_err and TU_UCT_err), which can be connected to the Vectored Interrupt
Module (VIM) and/or the Error Signaling Module (ESM). Please refer to the device-specific data manual
for more details about the signal hookup.
A Transfer Error Interrupt is enabled by writing 1 to TEIRES register and disabled by writing 1 to TIERER
register. Writing 0 has no effect. Reading from both addresses will result in the same value.
Figure 23-53. Transfer Error Interrupt Enable Set (TEIRES) [offset_TU = 78h]
31
16
Reserved
R-0
15
1
0
Reserved
11
10
RSTATE
8
Rsvd
7
6
WSTATE
4
3
Reserved
2
TNRE
FACE
R-0
R/S-0
R-0
R/S-0
R-0
R/S-0
R/S-0
LEGEND: R/W = Read/Write; R = Read only; S = Set; -n = value after reset
Table 23-35. Transfer Error Interrupt Enable Set (TEIRES) Field Descriptions
Bit
Field
31-11
Reserved
10-8
RSTATE
Value
0
Description
Reads return 0. Writes have no effect.
Read Error Interrupt Generation (interrupt generation on VBUS read transfer errors).
0
Interrupt generation on VBUS read transfer error is disabled.
7h
Interrupt generation on VBUS read transfer error is enabled.
Note: Any value different from 7h does not assure the interrupt error generation of all possible
VBUS read errors.
7
Reserved
6-4
WSTATE
0
Reads return 0. Writes have no effect.
Write Error Interrupt Generation (interrupt generation on VBUS write transfer errors).
0
Interrupt generation on VBUS write transfer error is disabled.
7h
Interrupt generation on VBUS write transfer error is enabled.
Note: Any value different from 7h does not assure the interrupt error generation of all possible
VBUS read errors.
3-2
1
0
Reserved
0
TNRE
Reads return 0. Writes have no effect.
Transfer Not Ready Enable.
0
TNR interrupt is disabled.
1
TNR interrupt is enabled.
FACE
Forbidden Access Enable.
0
FAC interrupt is disabled.
1
FAC interrupt is enabled.
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Figure 23-54. Transfer Error Interrupt Enable Reset (TEIRER) [offset_TU = 7Ch]
31
16
Reserved
R-0
15
1
0
Reserved
11
10
RSTATE
8
Rsvd
7
6
WSTATE
4
3
Reserved
2
TNRE
FACE
R-0
R/C-0
R-0
R/C-0
R-0
R/C-0
R/C-0
LEGEND: R/W = Read/Write; R = Read only; C = Clear; S = Set; -n = value after reset
Table 23-36. Transfer Error Interrupt Enable Reset (TEIRER) Field Descriptions
Bit
Field
31-11
Reserved
10-8
RSTATE
Value
0
Description
Reads return 0. Writes have no effect.
Read Error Interrupt Generation (interrupt generation on VBUS read transfer errors).
0
Interrupt generation on VBUS read transfer error is disabled.
7h
Interrupt generation on VBUS read transfer error is enabled.
Note: Any value different from 7h does not assure the interrupt error generation of all possible
VBUS read errors.
7
Reserved
6-4
WSTATE
0
Reads return 0. Writes have no effect.
Write Error Interrupt Generation (interrupt generation on VBUS write transfer errors).
0
Interrupt generation on VBUS write transfer error is disabled.
7h
Interrupt generation on VBUS write transfer error is enabled.
Note: Any value different from 7h does not assure the interrupt error generation of all possible
VBUS read errors.
3-2
1
0
1128
Reserved
0
TNRE
Reads return 0. Writes have no effect.
Transfer Not Ready Enable.
0
TNR interrupt is disabled.
1
TNR interrupt is enabled.
FACE
Forbidden Access Enable.
0
FAC interrupt is disabled.
1
FAC interrupt is enabled.
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23.19.1.18 Trigger Transfer to System Memory Set/Reset (TTSMS[1-4]/TTSMR[1-4])
The Trigger Transfer to System Memory register selects the current message buffer for a Transfer Unit
State Machine transfer transaction to system memory. Four 32-bit registers reflect all possible 128
message buffers.
The bits are set by writing 1 to TTSMS[1-4] and reset by writing 1 to TTSMR[1-4] or after the transfer
occurred. Writing 0 has no effect. Reading from both addresses will result in the same value.
Figure 23-55. Trigger Transfer to System Memory Set 1 (TTSMS1)
[offset_TU = 80h]
31
16
TTSMS1[31-16]
R/S-0
15
0
TTSMS1[15-0]
R/S-0
LEGEND: R/W = Read/Write; R = Read only; S = Set; -n = value after reset
Table 23-37. Trigger Transfer to System Memory Set 1 (TTSMS1)
Field Descriptions
Bit
Field
31-0
Value
TTSMS1[n]
Description
Trigger Transfer to System Memory Set 1. The register bits 0 to 31 correspond to message buffers
0 to 31. Each bit of the register controls the message buffer transfer to the system memory in the
following manner (note that only the least-significant bit of all four combined TTSM registers will be
currently scheduled for transmission).
0
No transfer request.
1
Transfer is based on address defined in TBA.
Figure 23-56. Trigger Transfer to System Memory Reset 1 (TTSMR1)
[offset_TU = 84h]
31
16
TTSMR1
R/C-0
15
0
TTSMR1
R/C-0
LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset
Table 23-38. Trigger Transfer to System Memory Reset 1 (TTSMR1)
Field Descriptions
Bit
31-0
Field
TTSMR1
Value
0-FFFF FFFFh
Description
Trigger Transfer to System Memory Reset 1. The TTSMR1 register shows the identical
values to TTSMS1 if read.
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Figure 23-57. Trigger Transfer to System Memory Set 2 (TTSMS2)
[offset_TU = 88h]
31
16
TTSMS2[63-48]
R/S-0
15
0
TTSMS2[47-32]
R/S-0
LEGEND: R/W = Read/Write; R = Read only; S = Set; -n = value after reset
Table 23-39. Trigger Transfer to System Memory Set 2 (TTSMS2)
Field Descriptions
Bit
Field
31-0
Value
TTSMS2[n]
Description
Trigger Transfer to System Memory Set 2. The register bits 0 to 31 correspond to message buffers
32 to 63. Each bit of the register controls the message buffer transfer to the system memory in the
following manner (note that only the least-significant bit of all four combined TTSM registers will be
currently scheduled for transmission).
0
No transfer request.
1
Transfer is based on address defined in TBA.
Figure 23-58. Trigger Transfer to System Memory Reset 2 (TTSMR2)
[offset_TU = 8Ch]
31
16
TTSMR2
R/C-0
15
0
TTSMR2
R/C-0
LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset
Table 23-40. Trigger Transfer to System Memory Reset 2 (TTSMR2)
Field Descriptions
Bit
31-0
1130
Field
TTSMR2
Value
0-FFFF FFFFh
Description
Trigger Transfer to System Memory Reset 2. The TTSMR2 register shows the identical
values to TTSMS2 if read.
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Figure 23-59. Trigger Transfer to System Memory Set 3 (TTSMS3)
[offset_TU = 90h]
31
16
TTSMS3[95-80]
R/S-0
15
0
TTSMS3[79-64]
R/S-0
LEGEND: R/W = Read/Write; R = Read only; S = Set; -n = value after reset
Table 23-41. Trigger Transfer to System Memory Set 3 (TTSMS3)
Field Descriptions
Bit
Field
31-0
Value
TTSMS3[n]
Description
Trigger Transfer to System Memory Set 3. The register bits 0 to 31 correspond to message buffers
64 to 95. Each bit of the register controls the message buffer transfer to the system memory in the
following manner (note that only the least-significant bit of all four combined TTSM registers will be
currently scheduled for transmission).
0
No transfer request.
1
Transfer is based on address defined in TBA.
Figure 23-60. Trigger Transfer to System Memory Reset 3 (TTSMR3)
[offset_TU = 94h]
31
16
TTSMR3
R/C-0
15
0
TTSMR3
R/C-0
LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset
Table 23-42. Trigger Transfer to System Memory Reset 3 (TTSMR3)
Field Descriptions
Bit
31-0
Field
TTSMR3
Value
0-FFFF FFFFh
Description
Trigger Transfer to System Memory Reset 3. The TTSMR3 register shows the identical
values to TTSMS3 if read.
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Figure 23-61. Trigger Transfer to System Memory Set 4 (TTSMS4)
[offset_TU = 98h]
31
16
TTSMS4[127-112]
R/S-0
15
0
TTSMS4[111-96]
R/S-0
LEGEND: R/W = Read/Write; R = Read only; S = Set; -n = value after reset
Table 23-43. Trigger Transfer to System Memory Set 4 (TTSMS4)
Field Descriptions
Bit
Field
31-0
Value
TTSMS4[n]
Description
Trigger Transfer to System Memory Set 4. The register bits 0 to 31 correspond to message buffers
96 to 127. Each bit of the register controls the message buffer transfer to the system memory in the
following manner (note that only the least-significant bit of all four combined TTSM registers will be
currently scheduled for transmission).
0
No transfer request.
1
Transfer is based on address defined in TBA.
Figure 23-62. Trigger Transfer to System Memory Reset 4 (TTSMR4)
[offset_TU = 9Ch]
31
16
TTSMR4
R/C-0
15
0
TTSMR4
R/C-0
LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset
Table 23-44. Trigger Transfer to System Memory Reset 4 (TTSMR4)
Field Descriptions
Bit
31-0
1132
Field
TTSMR4
Value
0-FFFF FFFFh
Description
Trigger Transfer to System Memory Reset 4. The TTSMR4 register shows the identical
values to TTSMS4 if read.
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23.19.1.19 Trigger Transfer to Communication Controller Set/Reset (TTCCS[1-4]/TTCCR[1-4])
The Trigger Transfer to Communication Controller registers select the current message buffer for a
Transfer Unit State Machine transfer transaction from system memory. Four 32-bit registers reflect all
possible 128 message buffers.
The bits are set by writing 1 to TTCCS[1-4] and reset by writing 1 to TTCCR[1-4] or after the transfer
occurred. Writing 0 has no effect. Reading from both addresses will result in the same value.
Figure 23-63. Trigger Transfer to Communication Controller Set 1 (TTCCS1)
[offset_TU = A0h]
31
16
TTCCS1[31-16]
R/S-0
15
0
TTCCS1[15-0]
R/S-0
LEGEND: R/W = Read/Write; R = Read only; S = Set; -n = value after reset
Table 23-45. Trigger Transfer to Communication Controller Set 1 (TTCCS1)
Field Descriptions
Bit
Field
31-0
Value
TTCCS1[n]
Description
Trigger Transfer to Communication Controller Set 1.
The register bits 0 to 31 correspond to message buffers 0 to 31. Each bit of the register controls the
message buffer transfer to the communication controller in the following manner.
0
No transfer request.
1
Transfer is based on address defined in TBA.
Figure 23-64. Trigger Transfer to Communication Controller Reset 1 (TTCCR1)
[offset_TU = A4h]
31
16
TTCCR1
R/C-0
15
0
TTCCR1
R/C-0
LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset
Table 23-46. Trigger Transfer to Communication Controller Reset 1 (TTCCR1)
Field Descriptions
Bit
31-0
Field
TTCCR1
Value
0-FFFF FFFFh
Description
Trigger Transfer to Communication Controller Reset 1The TTCCR1 register shows the
identical values to TTCCS1 if read.
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Figure 23-65. Trigger Transfer to Communication Controller Set 2 (TTCCS2)
[offset_TU = A8h]
31
16
TTCCS2[63-48]
R/S-0
15
0
TTCCS2[47-32]
R/S-0
LEGEND: R/W = Read/Write; R = Read only; S = Set; -n = value after reset
Table 23-47. Trigger Transfer to Communication Controller Set 2 (TTCCS2)
Field Descriptions
Bit
Field
31-0
Value
TTCCS2[n]
Description
Trigger Transfer to Communication Controller Set 2. The register bits 0 to 31 correspond to
message buffers 32 to 63. Each bit of the register controls the message buffer transfer to the
communication controller in the following manner.
0
No transfer request.
1
Transfer is based on address defined in TBA.
Figure 23-66. Trigger Transfer to Communication Controller Reset 2 (TTCCR2)
[offset_TU = ACh]
31
16
TTCCR2
R/C-0
15
0
TTCCR2
R/C-0
LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset
Table 23-48. Trigger Transfer to Communication Controller Reset 2 (TTCCR2)
Field Descriptions
Bit
31-0
1134
Field
TTCCR2
Value
0-FFFF FFFFh
Description
Trigger Transfer to Communication Controller Reset 2. The TTCCR2 register shows the
identical values to TTCCS2 if read.
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Figure 23-67. Trigger Transfer to Communication Controller Set 3 (TTCCS3)
[offset_TU = B0h]
31
16
TTCCS3[95-80]
R/S-0
15
0
TTCCS3[79-64]
R/S-0
LEGEND: R/W = Read/Write; R = Read only; S = Set; -n = value after reset
Table 23-49. Trigger Transfer to Communication Controller Set 3 (TTCCS3)
Field Descriptions
Bit
Field
31-0
Value
TTCCS3[n]
Description
Trigger Transfer to Communication Controller Set 3. The register bits 0 to 31 correspond to
message buffers 64 to 95. Each bit of the register controls the message buffer transfer to the
communication controller in the following manner.
0
No transfer request.
1
Transfer is based on address defined in TBA.
Figure 23-68. Trigger Transfer to Communication Controller Reset 3 (TTCCR3)
[offset_TU = B4h]
31
16
TTCCR3
R/C-0
15
0
TTCCR3
R/C-0
LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset
Table 23-50. Trigger Transfer to Communication Controller Reset 3 (TTCCR3)
Field Descriptions
Bit
31-0
Field
TTCCR3
Value
0-FFFF FFFFh
Description
Trigger Transfer to Communication Controller Reset 3. The TTCCR3 register shows the
identical values to TTCCS3 if read.
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Figure 23-69. Trigger Transfer to Communication Controller Set 4 (TTCCS4)
[offset_TU = B8h]
31
16
TTCCS4[127-112]
R/S-0
15
0
TTCCS4[111-96]
R/S-0
LEGEND: R/W = Read/Write; R = Read only; S = Set; -n = value after reset
Table 23-51. Trigger Transfer to Communication Controller Set 4 (TTCCS4)
Field Descriptions
Bit
Field
31-0
Value
TTCCS4[n]
Description
Trigger Transfer to Communication Controller Set 4. The register bits 0 to 31 correspond to
message buffers 96 to 127. Each bit of the register controls the message buffer transfer to the
communication controller in the following manner.
0
No transfer request.
1
Transfer is based on address defined in TBA.
Figure 23-70. Trigger Transfer to Communication Controller Reset 4 (TTCCR4)
[offset_TU = BCh]
31
16
TTCCR4
R/C-0
15
0
TTCCR4
R/C-0
LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset
Table 23-52. Trigger Transfer to Communication Controller Reset 4 (TTCCR4)
Field Descriptions
Bit
31-0
1136
Field
TTCCR4
Value
0-FFFF FFFFh
Description
Trigger Transfer to Communication Controller Reset 4. The TTCCR4 register shows the
identical values to TTCCS4 if read.
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23.19.1.20 Enable Transfer on Event to System Memory Set/Reset (ETESMS[1-4]/ETESMR[1-4])
The Enable Transfer on Event to System Memory Set registers enable a message buffer transfer to the
system memory after a receive or transmit event. Four 32-bit registers reflect all possible 128 message
buffers.
The bits are set by writing 1 to ETESMS[1-4] and reset by writing 1 to ETESMR[1-4]. Writing 0 has no
effect. Reading from both addresses will result in the same value.
Figure 23-71. Enable Transfer on Event to System Memory Set 1 (ETESMS1)
[offset_TU = C0h]
31
16
ETESMS1[31-16]
R/S-0
15
0
ETESMS1[15-0]
R/S-0
LEGEND: R/W = Read/Write; R = Read only; S = Set; -n = value after reset
Table 23-53. Enable Transfer on Event to System Memory Set 1 (ETESMS1)
Field Descriptions
Bit
Field
31-0
Value
ETESMS1[n]
Description
Enable Transfer on Event to System Memory Set 1. The register bits 0 to 31 correspond to
message buffers 0 to 31. Each bit of the register enables a message buffer transfer on event to the
system memory.
0
Transfer on event is disabled.
1
Transfer on event is enabled.
Figure 23-72. Enable Transfer on Event to System Memory Reset 1 (ETESMR1)
[offset_TU = C4h]
31
16
ETESMR1
R/C-0
15
0
ETESMR1
R/C-0
LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset
Table 23-54. Enable Transfer on Event to System Memory Reset 1 (ETESMR1)
Field Descriptions
Bit
31-0
Field
ETESMR1
Value
0-FFFF FFFFh
Description
Enable Transfer on Event to System Memory Reset 1. The ETESMR1 register shows the
identical values to ETESMS1 if read.
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Figure 23-73. Enable Transfer on Event to System Memory Set 2 (ETESMS2)
[offset_TU = C8h]
31
16
ETESMS2[63-48]
R/S-0
15
0
ETESMS2[47-32]
R/S-0
LEGEND: R/W = Read/Write; R = Read only; S = Set; -n = value after reset
Table 23-55. Enable Transfer on Event to System Memory Set 2 (ETESMS2)
Field Descriptions
Bit
Field
31-0
Value
ETESMS2[n]
Description
Enable Transfer on Event to System Memory Set 2. The register bits 0 to 31 correspond to
message buffers 32 to 63. Each bit of the register enables a message buffer transfer on event to
the system memory.
0
Transfer on event is disabled.
1
Transfer on event is enabled.
Figure 23-74. Enable Transfer on Event to System Memory Reset 2 (ETESMR2)
[offset_TU = CCh]
31
16
ETESMR2
R/C-0
15
0
ETESMR2
R/C-0
LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset
Table 23-56. Enable Transfer on Event to System Memory Reset 2 (ETESMR2)
Field Descriptions
Bit
31-0
1138
Field
ETESMR2
Value
0-FFFF FFFFh
Description
Enable Transfer on Event to System Memory Reset 2. The ETESMR2 register shows the
identical values to ETESMS2 if read.
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Figure 23-75. Enable Transfer on Event to System Memory Set 3 (ETESMS3)
[offset_TU = D0h]
31
16
ETESMS3[95-80]
R/S-0
15
0
ETESMS3[79-64]
R/S-0
LEGEND: R/W = Read/Write; R = Read only; S = Set; -n = value after reset
Table 23-57. Enable Transfer on Event to System Memory Set 3 (ETESMS3)
Field Descriptions
Bit
Field
31-0
Value
ETESMS3[n]
Description
Enable Transfer on Event to System Memory Set 3. The register bits 0 to 31 correspond to
message buffers 64 to 95. Each bit of the register enables a message buffer transfer on event to
the system memory.
0
Transfer on event is disabled.
1
Transfer on event is enabled.
Figure 23-76. Enable Transfer on Event to System Memory Reset 3 (ETESMR3)
[offset_TU = D4h]
31
16
ETESMR3
R/C-0
15
0
ETESMR3
R/C-0
LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset
Table 23-58. Enable Transfer on Event to System Memory Reset 3 (ETESMR3)
Field Descriptions
Bit
31-0
Field
ETESMR3
Value
0-FFFF FFFFh
Description
Enable Transfer on Event to System Memory Reset 3. The ETESMR3 register shows the
identical values to ETESMS3 if read.
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Figure 23-77. Enable Transfer on Event to System Memory Set 4 (ETESMS4)
[offset_TU = D8h]
31
16
ETESMS4[127-112]
R/S-0
15
0
ETESMS4[111-96]
R/S-0
LEGEND: R/W = Read/Write; R = Read only; S = Set; -n = value after reset
Table 23-59. Enable Transfer on Event to System Memory Set 4 (ETESMS4)
Field Descriptions
Bit
Field
31-0
Value
ETESMS4[n]
Description
Enable Transfer on Event to System Memory Set 4. The register bits 0 to 31 correspond to
message buffers 96 to 127. Each bit of the register enables a message buffer transfer on event to
the system memory.
0
Transfer on event is disabled.
1
Transfer on event is enabled.
Figure 23-78. Enable Transfer on Event to System Memory Reset 4 (ETESMR4)
[offset_TU = DCh]
31
16
ETESMR4
R/C-0
15
0
ETESMR4
R/C-0
LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset
Table 23-60. Enable Transfer on Event to System Memory Reset 4 (ETESMR4)
Field Descriptions
Bit
31-0
1140
Field
ETESMR4
Value
0-FFFF FFFFh
Description
Enable Transfer on Event to System Memory Reset 4. The ETESMR4 register shows the
identical values to ETESMS4 if read.
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23.19.1.21 Clear on Event to System Memory Set/Reset (CESMS[1-4]/CESMR[1-4])
The Clear on Event to System Memory registers disables an enabled transfer on event (enabled in
ETESM) after a receive or transmit event. Four 32-bit registers reflect all possible 128 message buffers.
The bits are set by writing 1 to CESMS[1-4] and reset by writing 1 to CESMR[1-4]. Writing 0 has no effect.
Reading from both addresses will result in the same value.
Figure 23-79. Clear on Event to System Memory Set 1 (CESMS1)
[offset_TU = E0h]
31
16
CESMS1[31-16]
R/S-0
15
0
CESMS1[15-0]
R/S-0
LEGEND: R/W = Read/Write; R = Read only; S = Set; -n = value after reset
Table 23-61. Clear on Event to System Memory Set 1 (CESMS1)
Field Descriptions
Bit
Field
31-0
Value
CESMS1[n]
Description
Clear on Event to System Memory Set 1. The register bits 0 to 31 correspond to message buffers 0
to 31. Each bit of the register enables an automatic clear of the corresponding ETESM1 bit after a
receive or transmit event.
0
No clear.
1
Activate clear.
Figure 23-80. Clear on Event to System Memory Reset 1 (CESMR1)
[offset_TU = E4h]
31
16
CESMR1
R/C-0
15
0
CESMR1
R/C-0
LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset
Table 23-62. Clear on Event to System Memory Reset 1 (CESMR1)
Field Descriptions
Bit
31-0
Field
CESMR1
Value
0-FFFF FFFFh
Description
Clear on Event to System Memory Reset 1. The CESMR1 register shows the identical
values to CESMS1 if read.
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Figure 23-81. Clear on Event to System Memory Set 2 (CESMS2)
[offset_TU = E8h]
31
16
CESMS2[63-48]
R/S-0
15
0
CESMS2[47-32]
R/S-0
LEGEND: R/W = Read/Write; R = Read only; S = Set; -n = value after reset
Table 23-63. Clear on Event to System Memory Set 2 (CESMS2)
Field Descriptions
Bit
Field
31-0
Value
CESMS2[n]
Description
Clear on Event to System Memory Set 2. The register bits 0 to 31 correspond to message buffers
32 to 63. Each bit of the register enables an automatic clear of the corresponding ETESM2 bit after
a receive or transmit event.
0
No clear.
1
Activate clear.
Figure 23-82. Clear on Event to System Memory Reset 2 (CESMR2)
[offset_TU = ECh]
31
16
CESMR2
R/C-0
15
0
CESMR2
R/C-0
LLEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset
Table 23-64. Clear on Event to System Memory Reset 2 (CESMR2)
Field Descriptions
Bit
31-0
1142
Field
CESMR2
Value
0-FFFF FFFFh
Description
Clear on Event to System Memory Reset 2. The CESMR2 register shows the identical
values to CESMS2 if read.
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Figure 23-83. Clear on Event to System Memory Set 3 (CESMS3)
[offset_TU = F0h]
31
16
CESMS3[95-80]
R/S-0
15
0
CESMS3[79-64]
R/S-0
LEGEND: R/W = Read/Write; R = Read only; S = Set; -n = value after reset
Table 23-65. Clear on Event to System Memory Set 3 (CESMS3)
Field Descriptions
Bit
Field
31-0
Value
CESMS3[n]
Description
Clear on Event to System Memory Set 3. The register bits 0 to 31 correspond to message buffers
64 to 95. Each bit of the register enables an automatic clear of the corresponding ETESM3 bit after
a receive or transmit event.
0
No clear.
1
Activate clear.
Figure 23-84. Clear on Event to System Memory Reset 3 (CESMR3)
[offset_TU = F4h]
31
16
CESMR3
R/C-0
15
0
CESMR3
R/C-0
LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset
Table 23-66. Clear on Event to System Memory Reset 3 (CESMR3)
Field Descriptions
Bit
31-0
Field
CESMR3
Value
0-FFFF FFFFh
Description
Clear on Event to System Memory Reset 3. The CESMR3 register shows the identical
values to CESMS3 if read.
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Figure 23-85. Clear on Event to System Memory Set 4 (CESMS4)
[offset_TU = F8h]
31
16
CESMS4[127-112]
R/S-0
15
0
CESMS4[111-96]
R/S-0
LEGEND: R/W = Read/Write; R = Read only; S = Set; -n = value after reset
Table 23-67. Clear on Event to System Memory Set 4 (CESMS4)
Field Descriptions
Bit
Field
31-0
Value
CESMS4[n]
Description
Clear on Event to System Memory Set 4. The register bits 0 to 31 correspond to message buffers
96 to 127. Each bit of the register enables an automatic clear of the corresponding ETESM4 bit
after a receive or transmit event.
0
No clear.
1
Activate clear.
Figure 23-86. Clear on Event to System Memory Reset 4 (CESMR4)
[offset_TU = FCh]
31
16
CESMR4
R/C-0
15
0
CESMR4
R/C-0
LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset
Table 23-68. Clear on Event to System Memory Reset 4 (CESMR4)
Field Descriptions
Bit
31-0
1144
Field
CESMR4
Value
0-FFFF FFFFh
Description
Clear on Event to System Memory Reset 4. The CESMR4 register shows the identical
values to CESMS4 if read.
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23.19.1.22 Transfer to System Memory Interrupt Enable Set/Reset (TSMIES[1-4]/TSMIER[1-4])
The Transfer to System Memory Interrupt Enable registers enable the interrupt generation on interrupt line
TU_Int0, after a transfer to the system memory occurred (flagged in TSMO). Four 32-bit Registers reflect
all 128 MB’s.
The bits are set by writing 1 to TSMIES[1-4] and reset by writing 1 to TSMIER[1-4]. Writing 0 has no
effect. Reading from both addresses will result in the same value.
Figure 23-87. Transfer to System Memory Interrupt Enable Set 1 (TSMIES1)
[offset_TU = 100h]
31
16
TSMIES1[31-16]
R/S-0
15
0
TSMIES1[15-0]
R/S-0
LEGEND: R/W = Read/Write; R = Read only; S = Set; -n = value after reset
Table 23-69. Transfer to System Memory Interrupt Enable Set 1 (TSMIES1)
Field Descriptions
Bit
Field
31-0
Value
TSMIES1[n]
Description
Transfer to System Memory Interrupt Enable Set 1. The register bits 0 to 31 correspond to
message buffers 0 to 31. Each bit of the register enables a potential interrupt, which occurs if the
corresponding TSMO1 bit is set.
0
No interrupt.
1
Interrupt is generated.
Figure 23-88. Transfer to System Memory Interrupt Enable Reset 1 (TSMIER1)
[offset_TU = 104h]
31
16
TSMIER1
R/C-0
15
0
TSMIER1
R/C-0
LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset
Table 23-70. Transfer to System Memory Interrupt Enable Reset 1 (TSMIER1)
Field Descriptions
Bit
31-0
Field
TSMIER1
Value
0-FFFF FFFFh
Description
Transfer to System Memory Interrupt Enable Reset 1. The TSMIER1 register shows the
identical values to TSMIES1 if read.
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Figure 23-89. Transfer to System Memory Interrupt Enable Set 2 (TSMIES2)
[offset_TU = 108h]
31
16
TSMIES2[63-48]
R/S-0
15
0
TSMIES2[47-32]
R/S-0
LEGEND: R/W = Read/Write; R = Read only; S = Set; -n = value after reset
Table 23-71. Transfer to System Memory Interrupt Enable Set 2 (TSMIES2)
Field Descriptions
Bit
Field
31-0
Value
TSMIES2[n]
Description
Transfer to System Memory Interrupt Enable Set 2. The register bits 0 to 31 correspond to
message buffers 32 to 63. Each bit of the register enables a potential interrupt, which occurs if the
corresponding TSMO2 bit is set.
0
No interrupt.
1
Interrupt is generated.
Figure 23-90. Transfer to System Memory Interrupt Enable Reset 2 (TSMIER2)
[offset_TU = 10Ch]
31
16
TSMIER2
RC-0
15
0
TSMIER2
R/C-0
LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset
Table 23-72. Transfer to System Memory Interrupt Enable Reset 2 (TSMIER2)
Field Descriptions
Bit
31-0
1146
Field
TSMIER2
Value
0-FFFF FFFFh
Description
Transfer to System Memory Interrupt Enable Reset 2. The TSMIER2 register shows the
identical values to TSMIES2 if read.
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Figure 23-91. Transfer to System Memory Interrupt Enable Set 3 (TSMIES3)
[offset_TU = 110h]
31
16
TSMIES3[95-80]
R/S-0
15
0
TSMIES3[79-64]
R/S-0
LEGEND: R/W = Read/Write; R = Read only; S = Set; -n = value after reset
Table 23-73. Transfer to System Memory Interrupt Enable Set 3 (TSMIES3)
Field Descriptions
Bit
Field
31-0
Value
TSMIES3[n]
Description
Transfer to System Memory Interrupt Enable Set 3. The register bits 0 to 31 correspond to
message buffers 64 to 95. Each bit of the register enables a potential interrupt, which occurs if the
corresponding TSMO3 bit is set.
0
No interrupt.
1
Interrupt is generated.
Figure 23-92. Transfer to System Memory Interrupt Enable Reset 3 (TSMIER3)
[offset_TU = 114h]
31
16
TSMIER3
R/C-0
15
0
TSMIER3
R/C-0
LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset
Table 23-74. Transfer to System Memory Interrupt Enable Reset 3 (TSMIER3)
Field Descriptions
Bit
31-0
Field
TSMIER3
Value
0-FFFF FFFFh
Description
Transfer to System Memory Interrupt Enable Reset 3. The TSMIER3 register shows the
identical values to TSMIES3 if read.
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Figure 23-93. Transfer to System Memory Interrupt Enable Set 4 (TSMIES4)
[offset_TU = 118h]
31
16
TSMIES4[127-112]
R/S-0
15
0
TSMIES4[111-96]
R/S-0
LEGEND: R/W = Read/Write; R = Read only; S = Set; -n = value after reset
Table 23-75. Transfer to System Memory Interrupt Enable Set 4 (TSMIES4)
Field Descriptions
Bit
Field
31-0
Value
TSMIES4[n]
Description
Transfer to System Memory Interrupt Enable Set 4. The register bits 0 to 31 correspond to
message buffers 96 to 127. Each bit of the register enables a potential interrupt, which occurs if the
corresponding TSMO4 bit is set.
0
No interrupt.
1
Interrupt is generated.
Figure 23-94. Transfer to System Memory Interrupt Enable Reset 4 (TSMIER4)
[offset_TU = 11Ch]
31
16
TSMIER4
R/C-0
15
0
TSMIER4
R/C-0
LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset
Table 23-76. Transfer to System Memory Interrupt Enable Reset 4 (TSMIER4)
Field Descriptions
Bit
31-0
1148
Field
TSMIER4
Value
0-FFFF FFFFh
Description
Transfer to System Memory Interrupt Enable Reset 4. The TSMIER4 register shows the
identical values to TSMIES4 if read.
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23.19.1.23 Transfer to Communication Controller Interrupt Enable Set/Reset (TCCIES[1-4]/TCCIER[1-4])
The Transfer to Communication Controller Interrupt Enable registers enables the interrupt generation on
interrupt line TU_Int0, after a transfer to the communication controller occurred (flagged in TCCO). Four
32-bit Registers reflect all 128 MBs.
The bits are set by writing 1 to TCCIES[1-4] and reset by writing 1 to TCCIER[1-4]. Writing 0 has no
effect. Reading from both addresses will result in the same value.
Figure 23-95. Transfer to Communication Controller Interrupt Enable Set 1 (TCCIES1)
[offset_TU = 120h]
31
16
TCCIES1[31-16]
R/S-0
15
0
TCCIES1[15-0]
R/S-0
LEGEND: R/W = Read/Write; R = Read only; S = Set; -n = value after reset
Table 23-77. Transfer to Communication Controller Interrupt Enable Set 1 (TCCIES1)
Field Descriptions
Bit
Field
31-0
Value
TCCIES1[n]
Description
Transfer to Communication Controller Interrupt Enable Set 1. The register bits 0 to 31 correspond
to message buffers 0 to 31. Each bit of the register enables a potential interrupt, which occurs if the
corresponding TCCO1 bit is set.
0
No interrupt.
1
Interrupt is generated.
Figure 23-96. Transfer to Communication Controller Interrupt Enable Reset 1 (TCCIER1)
[offset_TU = 124h]
31
16
TCCIER1
R/C-0
15
0
TCCIER1
R/C-0
LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset
Table 23-78. Transfer to Communication Controller Interrupt Enable Reset 1 (TCCIER1)
Field Descriptions
Bit
31-0
Field
TCCIER1
Value
0-FFFF FFFFh
Description
Transfer to Communication Controller Interrupt Enable Reset 1. The TCCIER1 register
shows the identical values to TCCIES1 if read.
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Figure 23-97. Transfer to Communication Controller Interrupt Enable Set 2 (TCCIES2)
[offset_TU = 128h]
31
16
TCCIES2[63-48]
R/S-0
15
0
TCCIES2[47-32]
R/S-0
LEGEND: R/W = Read/Write; R = Read only; S = Set; -n = value after reset
Table 23-79. Transfer to Communication Controller Interrupt Enable Set 2 (TCCIES2)
Field Descriptions
Bit
Field
31-0
Value
TCCIES2[n]
Description
Transfer to Communication Controller Interrupt Enable Set 2. The register bits 0 to 31 correspond
to message buffers 32 to 63. Each bit of the register enables a potential interrupt, which occurs if
the corresponding TCCO2 bit is set.
0
No interrupt.
1
Interrupt is generated.
Figure 23-98. Transfer to Communication Controller Interrupt Enable Reset 2 (TCCIER2)
[offset_TU = 12Ch]
31
16
TCCIER2
R/C-0
15
0
TCCIER2
R/C-0
LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset
Table 23-80. Transfer to Communication Controller Interrupt Enable Reset 2 (TCCIER2)
Field Descriptions
Bit
31-0
1150
Field
TCCIER2
Value
0-FFFF FFFFh
Description
Transfer to Communication Controller Interrupt Enable Reset 2. The TCCIER2 register
shows the identical values to TCCIES2 if read.
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Figure 23-99. Transfer to Communication Controller Interrupt Enable Set 3 (TCCIES3)
[offset_TU = 130h]
31
16
TCCIES3[95-80]
R/S-0
15
0
TCCIES3[79-64]
R/S-0
LEGEND: R/W = Read/Write; R = Read only; S = Set; -n = value after reset
Table 23-81. Transfer to Communication Controller Interrupt Enable Set 3 (TCCIES3)
Field Descriptions
Bit
Field
31-0
Value
TCCIES3[n]
Description
Transfer to Communication Controller Interrupt Enable Set 3. The register bits 0 to 31 correspond
to message buffers 64 to 95. Each bit of the register enables a potential interrupt, which occurs if
the corresponding TCCO3 bit is set.
0
No interrupt.
1
Interrupt is generated.
Figure 23-100. Transfer to Communication Controller Interrupt Enable Reset 3 (TCCIER3)
[offset_TU = 134h]
31
16
TCCIER3
R/C-0
15
0
TCCIER3
R/C-0
LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset
Table 23-82. Transfer to Communication Controller Interrupt Enable Reset 3 (TCCIER3)
Field Descriptions
Bit
31-0
Field
TCCIER3
Value
0-FFFF FFFFh
Description
Transfer to Communication Controller Interrupt Enable Reset 3. The TCCIER3 register
shows the identical values to TCCIES3 if read.
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Figure 23-101. Transfer to Communication Controller Interrupt Enable Set 4 (TCCIES4)
[offset_TU = 138h]
31
16
TCCIES4[127-112]
R/S-0
15
0
TCCIES4[111-96]
R/S-0
LEGEND: R/W = Read/Write; R = Read only; S = Set; -n = value after reset
Table 23-83. Transfer to Communication Controller Interrupt Enable Set 4 (TCCIES4)
Field Descriptions
Bit
Field
31-0
Value
TCCIES4[n]
Description
Transfer to Communication Controller Interrupt Enable Set 4. The register bits 0 to 31 correspond
to message buffers 96 to 127. Each bit of the register enables a potential interrupt, which occurs if
the corresponding TCCO4 bit is set.
0
No interrupt.
1
Interrupt is generated.
Figure 23-102. Transfer to Communication Controller Interrupt Enable Reset 4 (TCCIER4)
[offset_TU = 13Ch]
31
16
TCCIER4
R/C-0
15
0
TCCIER4
R/C-0
LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset
Table 23-84. Transfer to Communication Controller Interrupt Enable Reset 4 (TCCIER4)
Field Descriptions
Bit
31-0
1152
Field
TCCIER4
Value
0-FFFF FFFFh
Description
Transfer to Communication Controller Interrupt Enable Reset 4. The TCCIER4 register
shows the identical values to TCCIES4 if read.
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23.19.1.24 Transfer Configuration RAM (TCR)
The TCR consists of 128 entries, each 19 bit wide. The TCR is parity protected. The parity protection can
be switched on/off by the 4-bit key (PEL) in the Global Control Set/Reset (GCS/GCR) registers.
Figure 23-103. Transfer Configuration RAM (TCR) [offset_TU_RAM = 0h-1FFh]
31
18
17
16
Reserved
19
STXR
THTSM
TPTSM
R-0
R/W-0
R/W-0
R/W-0
15
14
THTCC
TPTCC
13
TSO
0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23-85. Transfer Configuration RAM (TCR) Field Descriptions
Bit
31-19
18
Field
Value
Reserved
0
STXR
Description
Reads return 0. Writes have no effect.
Set Transmit Request.
Control set/reset of buffer transmit requests in the communication controller.
17
16
15
14
13-0
0
Transfer Unit State Machine will set IBCM.STXRH to 0 during a transfer to the communication
controller.
1
Transfer Unit State Machine will set IBCM.STXRH to 1 during a transfer to the communication
controller.
THTSM
Transfer Header to System Memory.
0
Transfer Unit State Machine will not transfer buffer header to system memory.
1
Transfer Unit State Machine will transfer buffer header to system memory.
TPTSM
Transfer Payload to System Memory.
0
Transfer Unit State Machine will not transfer buffer payload to system memory.
1
Transfer Unit State Machine will transfer buffer payload to system memory.
THTCC
Transfer Header to Communication Controller.
0
Transfer Unit State Machine will not transfer buffer header to the communication controller.
1
Transfer Unit State Machine will transfer buffer header to the communication controller.
TPTCC
TSO
Transfer Payload to Communication Controller.
0
Transfer Unit State Machine will not transfer buffer payload to the communication controller.
1
Transfer Unit State Machine will transfer buffer payload to the communication controller.
Transfer Start Offset.
14-bit buffer address offset in system memory. The resulting address in system memory is
computed by adding the 32-bit aligned buffer address offset (TSO = buffer address offset bits 15:2)
to the base address defined in the TBA register.
Example: A TSO contents of 0x40 results in a Transfer Start Offset of 0x40 × 4 = 0x100
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23.19.1.25 TCR Parity Test Mode
In parity test mode (PEFT bit is set in Global Control Register (GC)) the parity information are visible and
can be read or written. The corresponding TCR entry can be found by subtracting 0x200 from the TCR
offset.
Figure 23-104. Parity Information in TCR Parity Test Mode [offset_TU_RAM = 200h-3FFh]
31
16
15
9
Reserved
PAB2
R-0
R/W-0
8
7
1
0
Reserved
PAB1
Reserved
PAB0
R-0
R/W-0
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23-86. Parity Information in TCR Parity Test Mode Field Descriptions
Bit
31-17
16
15-9
8
7-1
0
1154
Field
Reserved
Value
0
PAB2
Reserved
PAB0
Reads return 0. Writes have no effect.
Parity Bit for TCRx Byte 2. Parity information for byte 2 of TCRx(18-16). Reserved TCR bits are
ignored for parity calculation.
0
PAB1
Reserved
Description
Reads return 0. Writes have no effect.
Parity Bit for TCRx Byte 1. Parity information for byte 1 of TCRx(15:8).
0
Reads return 0. Writes have no effect.
Parity Bit for Byte 0.
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23.19.2 Communication Controller Registers
The FlexRay Communication Controller module allocates an address space of 2 Kbytes (0000h to 07FFh).
The registers are organized as 32-bit registers. 8/16-bit accesses are also supported. CPU access to the
message RAM is done through the input and output buffers. They buffer data to be transferred to and from
the message RAM under control of the message handler, avoiding conflicts between CPU accesses and
message reception / transmission. Alternatively to increase performance the Transfer Unit can be used for
transferring buffer data.
The test registers located on address 0010h and 0014h are writable only under the conditions.
The assignment of the message buffers is done according to the scheme shown in Figure 23-105. The
number N of available message buffers depends on the payload length of the configured message buffers.
The maximum number of message buffers is 128. The maximum payload length supported is 254 bytes.
The message buffers are separated into three consecutive groups; see Figure 23-105:
• Static buffers - Transmit / receive buffers assigned to static segment
• Static + Dynamic buffers - Transmit / receive buffers assigned to static or dynamic segment
• FIFO - Receive FIFO
The message buffer separation configuration can be changed in DEFAULT_CONFIG or CONFIG state
only by programming register MRC.
The first group starts with message buffer 0 and consists of static message buffers only. Message buffer 0
is dedicated to hold the startup / sync frame or the single slot frame, if the node transmits one, as
configured by SUCC1.TXST, SUCC1.TXSY, and SUCC1.TSM. In addition, message buffer 1 may be used
for sync frame transmission in case that sync frames or single-slot frames should have different payloads
on the two channels. In this case bit MRC.SPLM has to be programmed to 1 and message buffers 0 and 1
have to be configured with the key slot ID and can be (re)configured in DEFAULT_CONFIG or CONFIG
state only.
The second group consists of message buffers assigned to the static or to the dynamic segment.
Message buffers belonging to this group may be reconfigured during run time from dynamic to static or
vice versa depending on the state of MRC.SEC.
The message buffers belonging to the third group are concatenated to a single receive FIFO.
Figure 23-105. Message Buffer Assignment
Message Buffer 0
Message Buffer 1
⇓ Static Buffers
⇓ Static + Dynamic Buffers
...
⇓ FIFO
Message Buffer N-1
Message Buffer N
Table 23-87 provides a summary of the registers. The base address for the Communication Controller
registers is FFF7 C800h.
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Table 23-87. Communication Controller Registers
Offset
Acronym
Register Description
Section
Special Registers
0-0Ch
Reserved
Reserved
10h
TEST1
Test Register 1
Section 23.19.2.1.1
14h
TEST2
Test Register 2
Section 23.19.2.1.2
18h
Reserved
Reserved
1Ch
LCK
Lock Register
20h
EIR
Error Interrupt Register
Section 23.19.2.2.1
24h
SIR
Status Interrupt Register
Section 23.19.2.2.2
28h
EILS
Error Interrupt Line Select Register
Section 23.19.2.2.3
2Ch
SILS
Status Interrupt Line Select Register
Section 23.19.2.2.4
30h
EIES
Error Interrupt Enable Set Register
Section 23.19.2.2.5
34h
EIER
Error Interrupt Enable Reset Register
Section 23.19.2.2.5
38h
SIES
Status Interrupt Enable Set Register
Section 23.19.2.2.6
3Ch
SIER
Status Interrupt Enable Reset Register
Section 23.19.2.2.6
40h
ILE
Interrupt Line Enable Register
Section 23.19.2.2.7
44h
T0C
Timer 0 Configuration Register
Section 23.19.2.2.8
48h
T1C
Timer 1 Configuration Register
Section 23.19.2.2.9
4Ch
STPW1
Stop Watch Register 1
Section 23.19.2.2.10
50h
STPW2
Stop Watch Register 2
Section 23.19.2.2.11
Reserved
Reserved
80h
SUCC1
SUC Configuration Register 1
Section 23.19.2.3.1
84h
SUCC2
SUC Configuration Register 2
Section 23.19.2.3.2
88h
SUCC3
SUC Configuration Register 3
Section 23.19.2.3.3
8Ch
NEMC
NEM Configuration Register
Section 23.19.2.3.4
90h
PRTC1
PRT Configuration Register 1
Section 23.19.2.3.5
94h
PRTC2
PRT Configuration Register 2
Section 23.19.2.3.6
Section 23.19.2.3.7
Section 23.19.2.1.3
Interrupt Registers
54h-7Ch
Communication Controller Control Registers
98h
MHDC
MHD Configuration Register 1
9Ch
Reserved
Reserved
A0h
GTUC1
GTU Configuration Register 1
A4h
GTUC2
GTU Configuration Register 2
Section 23.19.2.3.9
A8h
GTUC3
GTU Configuration Register 3
Section 23.19.2.3.10
ACh
GTUC4
GTU Configuration Register 4
Section 23.19.2.3.11
B0h
GTUC5
GTU Configuration Register 5
Section 23.19.2.3.12
B4h
GTUC6
GTU Configuration Register 6
Section 23.19.2.3.13
B8h
GTUC7
GTU Configuration Register 7
Section 23.19.2.3.14
BCh
GTUC8
GTU Configuration Register 8
Section 23.19.2.3.15
C0h
GTUC9
GTU Configuration Register 9
Section 23.19.2.3.16
C4h
GTUC10
GTU Configuration Register 10
Section 23.19.2.3.17
C8h
GTUC11
GTU Configuration Register 11
Section 23.19.2.3.18
CCh-FCh
Reserved
Reserved
100h
CCSV
Communication Controller Status Vector Register
Section 23.19.2.4.1
104h
CCEV
Communication Controller Error Vector Register
Section 23.19.2.4.2
Reserved
Reserved
SCV
Slot Counter Value Register
Section 23.19.2.3.8
Communication Controller Status Registers
108h-10Ch
110h
1156
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Table 23-87. Communication Controller Registers (continued)
Offset
Acronym
Register Description
114h
MTCCV
Macrotick and Cycle Counter Value Register
Section 23.19.2.4.4
Section
118h
RCV
Rate Correction Value Register
Section 23.19.2.4.5
11Ch
OCV
Offset Correction Value Register
Section 23.19.2.4.6
120h
SFS
Sync Frame Status Register
Section 23.19.2.4.7
124h
SWNIT
Symbol Window and NIT Status Register
Section 23.19.2.4.8
128h
ACS
Aggregated Channel Status Register
Section 23.19.2.4.9
12Ch
Reserved
Reserved
ESIDn
Even Sync ID Register [1-15]
Reserved
Reserved
OSIDn
Odd Sync ID Register [1-15]
Reserved
Reserved
1B0h-1B8h
NMVn
Network Management Vector Register [1-3]
1BCh-2FCh
Reserved
Reserved
130h-168h
16Ch
170h-1A8h
1ACh
Section 23.19.2.4.10
Section 23.19.2.4.11
Section 23.19.2.4.12
Message Buffer Control Registers
300h
MRC
Message RAM Configuration Register
Section 23.19.2.5.1
304h
FRF
FIFO Rejection Filter Register
Section 23.19.2.5.2
308h
FRFM
FIFO Rejection Filter Mask Register
Section 23.19.2.5.3
30Ch
FCL
FIFO Critical Level Register
Section 23.19.2.5.4
310h
MHDS
Message Handler Status
Section 23.19.2.6.1
314h
LDTS
Last Dynamic Transmit Slot
Section 23.19.2.6.2
Message Buffer Status Registers
318h
FSR
FIFO Status Register
Section 23.19.2.6.3
31Ch
MHDF
Message Handler Constraints Flags
Section 23.19.2.6.4
320h
TXRQ1
Transmission Request Register 1
Section 23.19.2.6.5
324h
TXRQ2
Transmission Request Register 2
Section 23.19.2.6.5
328h
TXRQ3
Transmission Request Register 3
Section 23.19.2.6.5
32Ch
TXRQ4
Transmission Request Register 4
Section 23.19.2.6.5
330h
NDAT1
New Data Register 1
Section 23.19.2.6.6
334h
NDAT2
New Data Register 2
Section 23.19.2.6.6
338h
NDAT3
New Data Register 3
Section 23.19.2.6.6
33Ch
NDAT4
New Data Register 4
Section 23.19.2.6.6
340h
MBSC1
Message Buffer Status Changed Register 1
Section 23.19.2.6.7
344h
MBSC2
Message Buffer Status Changed Register 2
Section 23.19.2.6.7
348h
MBSC3
Message Buffer Status Changed Register 3
Section 23.19.2.6.7
34Ch
MBSC4
Message Buffer Status Changed Register 4
Section 23.19.2.6.7
Reserved
Reserved
350h-3ECh
Identification Registers
3F0h
CREL
Core Release Register
Section 23.19.2.7.1
3F4h
ENDN
Endian Register
Section 23.19.2.7.2
Reserved
Reserved
3F8h-3FCh
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Table 23-87. Communication Controller Registers (continued)
Offset
Acronym
Register Description
Section
Input Buffer
400h-4FCh
WRDSn
Write Data Section Register [1-64]
Section 23.19.2.8.1
500h
WRHS1
Write Header Section Register 1
Section 23.19.2.8.2
504h
WRHS2
Write Header Section Register 2
Section 23.19.2.8.3
508h
WRHS3
Write Header Section Register 3
Section 23.19.2.8.4
50Ch
Reserved
Reserved
510h
IBCM
Input Buffer Command Mask Register
Section 23.19.2.8.5
514h
IBCR
Input Buffer Command Request Register
Section 23.19.2.8.6
518h-5FCh
Reserved
Reserved
600h-6FCh
RDDSn
Read Data Section Register [1-64]
Section 23.19.2.9.1
700h
RDHS1
Read Header Section Register 1
Section 23.19.2.9.2
704h
RDHS2
Read Header Section Register 2
Section 23.19.2.9.3
708h
RDHS3
Read Header Section Register 3
Section 23.19.2.9.4
70Ch
MBS
Message Buffer Status Register
Section 23.19.2.9.5
710h
OBCM
Output Buffer Command Mask Register
Section 23.19.2.9.6
714h
OBCR
Output Buffer Command Request Register
Section 23.19.2.9.7
Reserved
Reserved
Output Buffer
718h-7FCh
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23.19.2.1 Special Registers
23.19.2.1.1 Test Register 1 (TEST1)
Test register 1 holds the control bits to configure the test modes of the FlexRay module. Write access to
these bits is only possible if the WRTEN bit is set. Figure 23-106 and Table 23-88 illustrate this register.
When the FlexRay module is operated in one of its test modes that requires WRTEN to be set (RAM Test
Mode, I/O Test Mode, Asynchronous Transmit Mode, and Loop Back Mode) only the selected test mode
functionality is available.
NOTE: To return from test mode operation to regular FlexRay operation we strongly recommend to
apply a hardware reset (Power on Reset or nReset) to reset all FlexRay internal state
machines to their initial state.
The test functions are not available in addition to the normal operational mode functions, they change the
functions of parts of the FlexRay module. Therefore normal operation as specified outside this chapter and
as required by the FlexRay protocol specification and the FlexRay conformance test is not possible. Test
mode functions may not be combined with each other or with FlexRay protocol functions.
NOTE: The FlexRay module should be kept in CONFIG state, while RAM Test Mode TMC = 01 is
enabled.
The test mode features are intended for hardware testing or for FlexRay bus analyzer tools. They are not
intended to be used in FlexRay applications.
Figure 23-106. Test Register 1 (TEST1) [offset_CC = 10h]
31
21
20
19
18
17
16
CERB
28
27
CERA
Reserved
TXENB
TXENA
TXB
TXA
RXB
RXA
R-0
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
R-0
5
4
3
2
15
24
10
Reserved
R-0
9
8
AOB
AOA
23
22
7
1
0
Reserved
TMC
Reserved
ELBE
WRTEN
R-0
R/W-0
R-0
R/W-0
R/W-0
R/W-1
6
LEGEND: R = Read only; R/W = Read/Write; -n = value after reset
Table 23-88. Test Register 1 (TEST1) Field Descriptions
Bit
Field
31-28
CERB
Value
Description
Coding Error Report Channel B
Set when a coding error is detected on channel B. Reset to zero when register TEST1 is read or
written. Once the CERB is set it will remain unchanged until the Host accesses the TEST1 register
0
No coding error is detected.
1h
Header CRC error is detected.
2h
Frame CRC error is detected.
3h
Frame Start Sequence FSS too long.
4h
First bit of Byte Start Sequence BSS seen LOW.
5h
Second bit of Byte Start Sequence BSS seen HIGH.
6h
First bit of Frame End Sequence FES seen HIGH.
7h
Second bit of Frame End Sequence FES seen LOW.
8h
CAS / MTS symbol seen too short.
9h
CAS / MTS symbol seen too long.
Ah-Fh
Reserved
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Table 23-88. Test Register 1 (TEST1) Field Descriptions (continued)
Bit
Field
27-24
CERA
Value
Description
Coding Error Report Channel A
Set when a coding error is detected on channel A. Reset to zero when register TEST1 is read or
written. Once the CERA is set it will remain unchanged until the Host accesses the TEST1 register
0
No coding error is detected.
1h
Header CRC error is detected.
2h
Frame CRC error is detected.
3h
Frame Start Sequence FSS too long.
4h
First bit of Byte Start Sequence BSS seen LOW.
5h
Second bit of Byte Start Sequence BSS seen HIGH.
6h
First bit of Frame End Sequence FES seen HIGH.
7h
Second bit of Frame End Sequence FES seen LOW.
8h
CAS / MTS symbol seen too short.
9h
CAS / MTS symbol seen too long.
Ah-Fh
Reserved
Note: Coding errors are also signaled when the communication controller is in
MONITOR_MODE. The error codes regarding CAS / MTS symbols concern only the
monitored bit pattern, irrelevant whether those bit patterns occurred in the symbol window
or elsewhere.
23-22
21
20
19
18
17
16
15-10
9
8
7-6
1160
Reserved
0
TXENB
Control of channel B transmit enable pin.
0
txen2 pin drives a 0
1
txen2 pin drives a 1
TXENA
Control of channel A transmit enable pin.
0
txen1 pin drives a 0
1
txen1 pin drives a 1
TXB
Control of channel B transmit pin.
0
txd2 pin drives a 0
1
txd2 pin drives a 1
TXA
Control of channel A transmit pin.
0
txd1 pin drives a 0
1
txd1 pin drives a 1
RXB
Monitor channel B receive pin.
0
rxd2 = 0
1
rxd2 = 1
RXA
Reserved
Monitor channel A receive pin.
0
rxd1 = 0
1
rxd1 = 1
0
Reads return 0. Writes have no effect.
AOB
Activity on B. The channel idle condition is specified in the FlexRay protocol spec v2.1, BITSTRB
process.
0
No activity is detected, channel B is idle.
1
Activity is detected, channel B is not idle.
AOA
Reserved
Reads return 0. Writes have no effect.
Activity on A. The channel idle condition is specified in the FlexRay protocol spec v2.1, BITSTRB
process.
0
No activity is detected, channel A is idle.
1
Activity is detected, channel A is not idle.
0
Reads return 0. Writes have no effect.
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Table 23-88. Test Register 1 (TEST1) Field Descriptions (continued)
Bit
Field
5-4
TMC
3-2
1
0
Reserved
Value
Description
Test mode control.
0
Normal operation mode, default.
1h
RAM test mode - All RAM blocks of the FlexRay module are directly accessible by the host. This
mode is intended to enable testing of the embedded RAM blocks during production testing.
2h
I/O test mode - The output pins txd1, txd2, txen1, txen2 are driven to the values defined by bits
TXA, TXB, TXENA, TXENB. The values applied to the input pins rxd1, rxd2 can be read from
register bits RXA, RXB
3h
Unused - mapped to normal operation mode.
0
Reads return 0. Writes have no effect.
ELBE
External Loop Back Enable. There are two possibilities to perform a loop back test. External loop
back via physical layer or internal loop back for in-system self-test (default). In case of an internal
loop back pins txen1,2 are in their inactive state, pins txd1,2 are set to HIGH, pins rxd1,2 are not
evaluated. Bit ELBE is evaluated only when POC is in loop back mode and test mode control is in
normal operation mode TMC = 00.
0
Internal loop back (default)
1
External loop back
WRTEN
Write test register enable. Enables write access to the test registers. To set the bit from 0 to 1 the
test mode key has to be written as defined in Lock Register (LCK). The unlock sequence is not
required when WRTEN is kept at 1 while other bits of the register are changed. The bit can be
reset to 0 at any time.
0
Write access to the test register is disabled.
1
Write access to the test register is enabled.
23.19.2.1.1.1 Asynchronous Transmit Mode (ATM)
The asynchronous transmit mode is entered by writing 1110 to the controller host interface command
vector CMD in the SUC configuration register 1 (controller host interface command: ATM) while the
communication controller is in CONFIG state and bit WRTEN in the test register 1 is set to 1. When called
in any other state or when bit WRTEN is not set, CMD will be reset to 0000 = command_not_accepted.
POCS in the communication controller status vector will show 00 1110 while the FlexRay module is in
ATM mode.
Asynchronous transmit mode can be left by writing 0001 (controller host interface command: CONFIG) to
the controller host interface command vector CMD in the SUC configuration register 1.
In ATM mode transmission of a FlexRay frame is triggered by writing the number of the corresponding
message buffer to the input buffer command request register while bit STXR in the input buffer command
mask register is set to 1. In this mode wakeup, startup, and clock synchronization are bypassed, the
controller host interface command SEND_MTS results in the immediate transmission of a MTS symbol.
MTS symbols received while operating in ATM mode will set the status interrupt flags MTSA,B in the
Status Interrupt Register like in monitor mode.
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23.19.2.1.1.2 Loop Back Mode
The loop back mode is entered by writing 1111 to the controller host interface command vector CMD in
the SUC configuration register 1 (controller host interface command: LOOP_BACK) while the
communication controller is in CONFIG state and bit WRTEN in the test register 1 is set to 1. This write
operation has to be directly preceded by two consecutive write accesses to the Configuration Lock Key
(unlock sequence). When called in any other state or when bit WRTEN is not set, CMD will be reset to
0000 = command_not_accepted. POCS in the communication controller status vector will show 00 1101
while the FlexRay module is in loop back mode.
Loop back mode can be left by writing 0001 (controller host interface command: CONFIG) to the controller
host interface command vector CMD in the SUC configuration register 1.
The loop back mode is intended to check the modules internal data paths. Normal, time triggered
operation is not possible in loop back mode.
There are two possibilities to perform a loop back test. External loop back through the physical layer
(TEST1.ELBE = 1) or internal loop back for in-system self-test (TEST1.ELBE = 0). In case of an internal
loop back pins txen1,2_n are in their inactive state, pins txd1,2 are set, pins rxd1,2 are not evaluated.
When the communication controller is in loop back mode, a loop back test is started by the host writing a
message to the input buffer and requesting the transmission by writing to the input buffer command
request register. The message handler will transfer the message into the message RAM and then into the
transient buffer of the selected channel. The channel protocol controller (PRT) will read (in 32-bit words)
the message from the transmit part of the transient buffer and load it into its Rx / Tx shift register. The
serial transmission is looped back into the shift register; its content is written into the receive part of the
channels transient buffer before the next word is loaded.
The PRT and the message handler will then treat this transmitted message like a received message,
perform an acceptance filtering on frame ID and receive channel, and store the message into the
message RAM (assuming the message passed the acceptance filter, thus testing the acceptance filter
logic). The loop back test ends with the host requesting this received message from the message RAM
and then checking the contents of the output buffer.
Each FlexRay channel is tested separately. The FlexRay module cannot receive messages from the
FlexRay bus while it is in the loop back mode.
The cycle counter value of frames used in loop back mode can be programmed by writing to the CCV bits
of the MTCCV register (writable in ATM and loop back mode only).
NOTE: In case of an odd payload, the last two bytes of the looped-back payload will be right aligned
(shifted by 16 bits to the right) inside the last 32-bit data word.
The controller host interface command SEND_MTS results in the immediate transmission of an MTS
symbol. Transmitted MTS symbols will not cause status interrupt flags MTSA,B to be set in the Status
Interrupt Register. MTS symbols received while operating in loop back mode will set status interrupt flags
MTSA,B in System Interrupt Register like in monitor mode. The reception of an MTS symbol can be
emulated by driving the FlexRay receive pins RxD1,2 to low for the duration of the symbol in external loop
back mode, or by driving the FlexRay pins TxD1,2 and TxEN1,2 to low using the TXA,B and TXENA,B of
Test Register1 in internal or external loop back mode.
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23.19.2.1.2 Test Register 2 (TEST2)
Test register 2 holds all bits required for RAM test of the seven embedded RAM blocks of the
communication controller. Write access to this register is only possible when bit WRTEN in the test
register 1 is set.
Figure 23-107 and Table 23-89 illustrate this register.
Figure 23-107. Test Register 2 (TEST2) [offset_CC = 14h]
31
16
Reserved
R-0
15
14
RDPB
WRPB
13
Reserved
7
6
SSEL
4
Rsvd
3
1
RS
0
R-0
R/W-0
R-0
R/W-0
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23-89. Test Register 2 (TEST2) Field Descriptions
Bit
31-16
Field
Reserved
Value
0
Description
Reads return 0. Writes have no effect.
15
RDPB
0-1
Read parity bit. Value of parity bit read from the selected RAM location.
14
WRPB
0-1
Write parity bit. Value of parity bit to be written to the selected RAM location
13-7
Reserved
6-4
SSEL
3
2-0
Reserved
0
Reads return 0. Writes have no effect.
Segment select. To enable access to the complete message RAM (8192 byte addresses) the message
RAM is segmented.
0
Access to RAM bytes 0000h to 03FFh is enabled.
1h
Access to RAM bytes 0400h to 07FFh is enabled.
2h
Access to RAM bytes 0800h to 0BFFh is enabled.
3h
Access to RAM bytes 0C00h to 0FFFh is enabled.
4h
Access to RAM bytes 1000h to 13FFh is enabled.
5h
Access to RAM bytes 1400h to 17FFh is enabled.
6h
Access to RAM bytes 1800h to 1BFFh is enabled.
7h
Access to RAM bytes 1C00h to 1FFFh is enabled.
0
Reads return 0. Writes have no effect.
RS
RAM select. In RAM test mode the RAM blocks selected by RS are mapped to module address 400h to
7FFh (1024 byte addresses).
0
Input buffer RAM 1
1h
Input buffer RAM 2
2h
Output buffer RAM 1
3h
Output buffer RAM 2
4h
Transient buffer RAM A
5h
Transient buffer RAM B
6h
Message RAM
7h
Reserved
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23.19.2.1.2.1 RAM Test Mode
In RAM test mode (TEST1.TMC = 01), one of the seven RAM blocks can be selected for direct read and
write access by programming RS to the corresponding value; see Figure 23-108.
For external RAM access in RAM test mode, the selected RAM block is mapped to the address range
offset_CC 400h to 7FFh, which is the address space for the input and output buffer register sets in normal
operation. Hence, the functionality of the input and output buffer register sets is not available in RAM test
mode.
With the available address space (offset_CC 400h to 7FFh) in RAM test mode, 1024 bytes of RAM can be
addressed for direct access. Since the length of the Message RAM exceeds the available address space,
the Message RAM is segmented into segments of 1024 bytes. The segments can be selected by
programming the bits SSEL of test register 2.
Figure 23-108. Test Mode Access to Communication Controller RAM Blocks
offset_CC
Normal
Operation
RAM Test
000h
RS(2-0) =
000
001
010
011
100
101
110
SSEL(2-0) =
3FCh
400h
Input and
Output
Register Set
IBF1
IBF2
OBF1
OBF2
TBF1
7FCh
TBF2
000
001
010
011
100
101
110
111
MBF
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23.19.2.1.3 Lock Register (LCK)
The lock register is write-only. Reading the register will return 00.
Figure 23-109 and Table 23-90 illustrate this register.
Figure 23-109. Lock Register (LCK) [offset_CC = 1Ch]
31
16
Reserved
R-0
15
8
7
0
TMK
CLK
W-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 23-90. Lock Register (LCK) Field Descriptions
Bit
Field
31-16
Reserved
15-8
TMK
Value
0
0-1FFh
Description
Reads return 0. Writes have no effect.
Test mode key. To write bit WRTEN in the test register to 1, the write operation has to be directly
preceded by two consecutive write accesses to the test mode key (unlock sequence). If this write
sequence is interrupted by other write accesses, bit WRTEN is not set to 1 and the sequence has
to be repeated.
First write (LCK.TMK): 75h = 0111 0101
Second write (LCK.TMK): 8Ah = 1000 1010
Third write: TEST1.WRTEN = 1
7-0
CLK
0-FFh
Configuration lock key. To leave CONFIG state by writing to CMD in the SUC configuration
register 1 (commands READY; MONITOR_MODE; ATM; LOOP_BACK), the write operation has to
be directly preceded by two consecutive write accesses to the configuration lock key (unlock
sequence). If this write sequence is interrupted by other write accesses, the communication
controller remains in CONFIG state and the sequence has to be repeated.
First write (LCK.CLK): CEh = 1100 1110
Second write (LCK.CLK): 31h = 0011 0001
Third write (SUCC.CMD)
NOTE: In case that the Host uses 8/16-bit accesses to write the listed bit fields, the programmer has
to ensure that no "dummy accesses" (for example, the remaining register bytes / words) are
inserted by the compiler.
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23.19.2.2 Interrupt Registers
23.19.2.2.1 Error Interrupt Register (EIR)
The flags are set when the communication controller detects one of the listed error conditions. They
remain set until the host clears them. A flag is cleared by writing a 1 to the corresponding bit position.
Writing a 0 has no effect on the flag. A reset will also clear the register.
Figure 23-110 and Table 23-91 illustrate this register.
Figure 23-110. Error Interrupt Register (EIR) [offset_CC = 20h]
31
26
25
24
18
17
16
Reserved
27
TABB
LTVB
EDB
Reserved
TABA
LTVA
EDA
R-0
R/W-0
R/W-0
R/W-0
R-0
R/W-0
R/W-0
R/W-0
15
12
23
19
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
MHF
IOBA
IIBA
EFA
RFO
PERR
CCL
CCF
SFO
SFBM
CNA
PEMC
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23-91. Error Interrupt Register (EIR) Field Descriptions
Bit
31-27
26
25
24
23-19
18
17
16
15-12
11
1166
Field
Reserved
Value
0
TABB
0
No transmission across slot boundary is detected on channel B.
1
Transmission across slot boundary is detected on channel B.
Latest transmit violation channel B. The flag signals a latest transmit violation on channel B to the
host.
0
No latest transmit violation is detected on channel B.
1
Latest transmit violation is detected on channel B.
EDB
Error detected on channel B. This bit is set whenever one of the flags SEDB, CEDB, CIB, SBVB in
the Aggregated channel status register is set.
0
No error is detected on channel B.
1
Error is detected on channel B.
0
Reads return 0. Writes have no effect.
TABA
Transmission Across Boundary Channel A. The flag signals to the Host that a transmission across
a slot boundary occurred for channel A.
0
No transmission across slot boundary is detected on channel A.
1
Transmission across slot boundary is detected on channel A.
LTVA
Latest transmit violation channel A. The flag signals a latest transmit violation on channel A to the
host.
0
No latest transmit violation is detected on channel A.
1
Latest transmit violation is detected on channel A.
EDA
Reserved
Reads return 0. Writes have no effect.
Transmission Across Boundary Channel B. The flag signals to the Host that a transmission across
a slot boundary occurred for channel B.
LTVB
Reserved
Description
Error detected on channel A. This bit is set whenever one of the flags SEDA, CEDA, CIA, SBVA in
the Aggregated channel status register is set.
0
No error is detected on channel A.
1
Error is detected on channel A.
0
Reads return 0. Writes have no effect.
MHF
Message Handler Constraints Flag. The flag signals a Message Handler constraints violation
condition. It is set whenever one of the flags MHDF.SNUA, MHDF.SNUB, MHDF.FNFA,
MHDF.FNFB, MHDF.TBFA, MHDF.TBFB, MHDF.WAHP changes from 0 to 1.
0
No Message Handler failure is detected.
1
Message Handler failure is detected.
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Table 23-91. Error Interrupt Register (EIR) Field Descriptions (continued)
Bit
Field
10
IOBA
9
Value
Description
Illegal Output buffer Access. This flag is set by the communication controller when the Host
requests the transfer of a message buffer from the Message RAM to the Output Buffer while
OBCR.OBSYS is set to 1.
0
No illegal Host access to Output Buffer occurred.
1
Illegal Host access to Output Buffer occurred.
IIBA
Illegal Input Buffer Access. This flag is set by the communication controller when the Host wants to
modify a message buffer via Input Buffer and one of the following conditions applies:
• The communication controller is not in CONFIG or DEFAULT_CONFIG state and the Host writes
to the Input Buffer Command Request register to modify the following:
–
the Header section of message buffer 0, 1 if configured for transmission in key slot
–
the Header section of static message buffers with buffer number < MRC.FDB while
MRC.SEC = 01
–
the Header section of any static or dynamic message buffer while MRC.SEC = 1x
–
Header and / or data section of any message buffer belonging to the receive FIFO
• The Host writes to any register of the Input Buffer while IBCR.IBSYH is set to 1.
8
7
6
0
No illegal Host access to Input Buffer occurred.
1
Illegal Host access to Input Buffer occurred.
EFA
Empty FIFO Access. This flag is set by the communication controller when the Host requests the
transfer of a message from the receive FIFO via Output Buffer while the receive FIFO is empty.
0
No Host access to empty FIFO occurred.
1
Host access to empty FIFO occurred.
RFO
Receive FIFO overrun. This flag is set by the communication controller when a receive FIFO
overrun was detected. The flag is cleared by the next FIFO read access of the host. After this read
access one position in the FIFO is empty again.
0
No receive FIFO overrun is detected.
1
A receive FIFO overrun has been detected.
PERR
Parity error. The flag signals a parity error to the host. The flag is set by the parity logic of the
communication controller when it detects a parity error while reading from one of the FlexRay RAM
blocks.
Note: Parity Error in the TCR RAM is an exception indicated by the PE flag in Transfer Error
Interrupt Flag (TEIF) register
5
4
0
No parity error is detected.
1
Parity error is detected.
CCL
CHI Command Locked. The flag signals that the write access to the CHI command vector
SUCC1.CMD was not successful because it coincided with a POC state change triggered by
protocol functions. In this case bit CNA is also set to 1.
0
CHI command is accepted.
1
CHI command is not accepted.
CCF
Clock correction failure. This flag is set at the end of the cycle whenever one of the following errors
occurred:
• Missing rate correction signal
• Missing offset correction signal
• Clock correction Failed counter stopped at 15
• Clock correction Limit Reached
The clock correction status is monitored in the communication controller error vector and sync
frame status register.
3
0
No clock correction error.
1
Clock correction failed.
SFO
Sync frame overflow. Set when either the number of sync frames received during the last
communication cycle or the total number of different sync frame IDs received during the last double
cycle exceeds the maximum number of sync frames as defined by SNM in the GTU configuration
register 2.
0
Number of received sync frames in the configured range.
1
More sync frames received than configured by SNM.
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Table 23-91. Error Interrupt Register (EIR) Field Descriptions (continued)
Bit
Field
2
SFBM
1
0
Value
Description
Sync frames below minimum. This flag signals that the number of sync frames received during the
last communication cycle was below the limit required by the FlexRay protocol. The minimum
number of sync frames per communication cycle is 2.
0
Two or more sync frames received during last communication cycle.
1
Less than two sync frame received during last communication cycle.
CNA
Command not accepted. The flag signals that the controller host interface command vector CMD in
the SUC configuration register 1 was reset to 0000 due to an unaccepted controller host interface
command.
0
Controller host interface command is accepted.
1
Controller host interface command is not accepted.
PEMC
POC error mode changed. This flag is set whenever the error mode signaled by ERRM in the
communication controller error vector register has changed.
0
Error mode has not changed.
1
Error mode has changed.
23.19.2.2.2 Status Interrupt Register (SIR)
The flags are set by the communication controller when a corresponding event occurs. They remain set
until the host clears them. If enabled, an interrupt is pending while one of the bits is set. A flag is cleared
by writing a 1 to the corresponding bit position. Writing a 0 has no effect on the flag. A hardware reset will
also clear the register.
Figure 23-111 and Table 23-92 illustrate this register.
Figure 23-111. Status Interrupt Register (SIR) [offset_CC = 24h]
31
25
24
17
16
Reserved
26
MTSB
WUPB
23
Reserved
18
MTSA
WUPA
R-0
R/W-0
R/W-0
R-0
R/W-0
R/W-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SDS
MBSI
SUCS
SWE
TOBC
TIBC
TI1
TI0
NMVC
RFCL
RFNE
RXI
TXI
CYCS
CAS
WST
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23-92. Status Interrupt Register (SIR) Field Descriptions
Bit
31-26
25
24
23-18
17
1168
Field
Reserved
Value
0
MTSB
Reads return 0. Writes have no effect.
MTS received on channel B. Media access test symbol received on channel B during the last
symbol window. Updated by the communication controller for each channel at the end of the
symbol window.
0
No MTS symbol is received.
1
MTS symbol is received.
WUPB
Reserved
Description
Wakeup pattern channel B. This flag is set by the communication controller when a wakeup pattern
was received on channel B.
0
No wakeup pattern is on channel B.
1
Wakeup pattern is on channel B.
0
Reads return 0. Writes have no effect.
MTSA
MTS received on channel A. Media access test symbol received on channel A during the last
symbol window. Updated by the communication controller for each channel at the end of the
symbol window.
0
No MTS symbol is received.
1
MTS symbol is received.
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Table 23-92. Status Interrupt Register (SIR) Field Descriptions (continued)
Bit
Field
16
WUPA
15
14
Value
Description
Wakeup pattern channel A. This flag is set by the communication controller when a wakeup pattern
was received on channel A.
0
No wakeup pattern is on channel A.
1
Wakeup pattern is on channel A.
SDS
Start of Dynamic Segment. This flag is set by the communication controller when the dynamic
segment starts.
0
Dynamic segment is not yet started.
1
Dynamic segment is started.
MBSI
Message buffer status interrupt. This flag is set by the communication controller if bit MBI of a
dedicated receive buffer is set to 1 and when the status of that message buffer has been updated
due to reception of a:
• valid frame with payload
• valid frame with payload zero
• null frame
• corrupted frame or an empty slot
13
12
11
10
9
8
7
6
0
No message buffer status has been updated.
1
Message buffer status of at least one receive buffer has been updated.
SUCS
Startup completed successfully. This flag is set whenever a startup completed successfully and the
communication controller entered NORMAL_ACTIVE state.
0
No startup is completed successfully.
1
Startup is completed successfully.
SWE
Stop watch event. If enabled by the respective control bits located in the Stop watch register, a
detected edge on external stop watch pin or a software trigger event will generate a stop watch
event.
0
No stop watch event.
1
Stop watch event occurred.
TOBC
Transfer output buffer completed. This flag is set whenever a transfer from the message RAM to
the output buffer has completed and bit OBSYS in the output buffer command request register has
been reset by the message handler.
0
No transfer completed since bit was reset.
1
Transfer between message RAM and output buffer is completed.
TIBC
Transfer input buffer completed. This flag is set whenever a transfer from input buffer to the
message RAM has completed and bit IBSYS in the input buffer command request register has
been reset by the message handler.
0
No transfer completed since bit was reset.
1
Transfer between input buffer and message RAM is completed.
TI1
Timer interrupt 1. This flag is set whenever the conditions programmed in the timer interrupt 1
configuration register are met. A timer interrupt 1 is also signaled on pin CC_tint1.
0
No timer interrupt 1.
1
Timer interrupt 1 occurred.
TI0
Timer interrupt 0. This flag is set whenever the conditions programmed in the timer interrupt 0
configuration register are met. A timer interrupt 0 is also signaled on pin CC_tint0.
0
No timer interrupt 0.
1
Timer interrupt 0 occurred.
NMVC
Network management vector changed. This interrupt flag signals a change in the Network
management vector visible to the host.
0
No change in the network management vector.
1
Network management vector is changed.
RFCL
Receive FIFO critical level. This flag is set when the receive FIFO fill level FSR.RFFL is equal or
greater than the critical level as configured by FCL.CL.
0
Receive FIFO is below critical level.
1
Receive FIFO critical level is reached.
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Table 23-92. Status Interrupt Register (SIR) Field Descriptions (continued)
Bit
Field
5
RFNE
4
3
2
1
0
1170
Value
Description
Receive FIFO not empty. This flag is set by the communication controller when a received valid
frame was stored into the empty receive FIFO. The actual state of the receive FIFO is monitored in
register FSR.
0
Receive FIFO is empty.
1
Receive FIFO is not empty.
RXI
Receive interrupt. This flag is set by the communication controller when the payload segment of a
received valid frame was stored into the data section of a matching dedicated receive buffer and if
bit MBI of that message buffer is set to 1.
0
No data section has been updated.
1
At least one data section has been updated.
TXI
Transmit interrupt. This flag is set by the communication controller after successful frame
transmission if bit MBI in the respective message buffer is set to 1.
0
No frame is transmitted.
1
At least one frame was transmitted successfully.
CYCS
Cycle start interrupt. This flag is set by the communication controller when a communication cycle
starts.
0
No communication cycle is started.
1
Communication cycle is started.
CAS
Collision avoidance symbol. This flag is set by the communication controller when a CAS was
received.
0
No CAS symbol is received.
1
CAS symbol is received.
WST
This flag is set when WSV in the communication controller status vector register changes to a value
other than UNDEFINED.
0
Wakeup status is unchanged.
1
Wakeup status is changed.
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23.19.2.2.3 Error Interrupt Line Select (EILS)
The settings in the error interrupt line select register assigns an interrupt generated by a specific error
interrupt flag to one of the two module interrupt lines (CC_int0 or CC_int1).
Figure 23-112 and Table 23-93 illustrate this register.
Figure 23-112. Error Interrupt Line Select Register (EILS) [offset_CC = 28h]
31
27
Reserved
R-0
15
12
26
25
24
23
19
TABBL LTVBL
EDBL
Reserved
R/W-0
R/W-0
R-0
R/W-0
18
17
16
TABAL LTVAL
EDAL
R/W-0
R/W-0
R/W-0
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
MHFL
IOBAL
IIBAL
EFAL
RFOL
PERRL
CCLL
CCFL
SFOL
SFBML
CNAL
PEMCL
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23-93. Error Interrupt Line Select Register (EILS) Field Descriptions
Bit
31-27
26
25
24
23-19
18
17
16
15-12
11
10
9
8
Field
Value
Reserved
0
TABBL
Transmission Across Boundary Channel B Interrupt Line.
Interrupt is assigned to interrupt line CC_int0.
1
Interrupt is assigned to interrupt line CC_int1.
Latest Transmit Violation Channel B Interrupt Line.
0
Interrupt is assigned to interrupt line CC_int0.
1
Interrupt is assigned to interrupt line CC_int1.
EDBL
Error Detected on Channel B Interrupt Line.
0
Interrupt is assigned to interrupt line CC_int0.
1
Interrupt is assigned to interrupt line CC_int1.
0
Reads return 0. Writes have no effect.
TABAL
Transmission Across Boundary Channel A Interrupt Line.
0
Interrupt is assigned to interrupt line CC_int0.
1
Interrupt is assigned to interrupt line CC_int1.
LTVAL
Latest Transmit Violation Channel A Interrupt Line.
0
Interrupt is assigned to interrupt line CC_int0.
1
Interrupt is assigned to interrupt line CC_int1.
EDAL
Reserved
Reads return 0. Writes have no effect.
0
LTVBL
Reserved
Description
Error Detected on Channel A Interrupt Line.
0
Interrupt is assigned to interrupt line CC_int0.
1
Interrupt is assigned to interrupt line CC_int1.
0
Reads return 0. Writes have no effect.
MHFL
Message Handler Constraints Flag Interrupt Line.
0
Interrupt is assigned to interrupt line CC_int0.
1
Interrupt is assigned to interrupt line CC_int1.
IOBAL
Illegal Output Buffer Access Interrupt Line.
0
Interrupt is assigned to interrupt line CC_int0.
1
Interrupt is assigned to interrupt line CC_int1.
IIBAL
Illegal Input Buffer Access Interrupt Line.
0
Interrupt is assigned to interrupt line CC_int0.
1
Interrupt is assigned to interrupt line CC_int1.
EFAL
Empty FIFO Access Interrupt Line.
0
Interrupt is assigned to interrupt line CC_int0.
1
Interrupt is assigned to interrupt line CC_int1.
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Table 23-93. Error Interrupt Line Select Register (EILS) Field Descriptions (continued)
Bit
Field
7
RFOL
6
5
4
3
2
1
0
1172
Value
Description
Receive FIFO Overrun Interrupt Line.
0
Interrupt is assigned to interrupt line CC_int0.
1
Interrupt is assigned to interrupt line CC_int1.
PERRL
Parity Error Interrupt Line.
0
Interrupt is assigned to interrupt line CC_int0.
1
Interrupt is assigned to interrupt line CC_int1.
CCLL
CHI Command Locked Interrupt Line.
0
Interrupt is assigned to interrupt line CC_int0.
1
Interrupt is assigned to interrupt line CC_int1.
CCFL
Clock Correction Failure Interrupt Line.
0
Interrupt is assigned to interrupt line CC_int0.
1
Interrupt is assigned to interrupt line CC_int1.
SFOL
Sync Frame Overflow Interrupt Line.
0
Interrupt is assigned to interrupt line CC_int0.
1
Interrupt is assigned to interrupt line CC_int1.
SFBML
Sync Frames Below Minimum Interrupt Line.
0
Interrupt is assigned to interrupt line CC_int0.
1
Interrupt is assigned to interrupt line CC_int1.
CNAL
Command Not Accepted Interrupt Line.
0
Interrupt is assigned to interrupt line CC_int0.
1
Interrupt is assigned to interrupt line CC_int1.
PEMCL
POC Error Mode Changed Interrupt Line.
0
Interrupt is assigned to interrupt line CC_int0.
1
Interrupt is assigned to interrupt line CC_int1.
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23.19.2.2.4 Status Interrupt Line Select (SILS)
The settings in the status interrupt line select register assign an interrupt generated by a specific status
interrupt flag to one of the two module interrupt lines (CC_int0 or CC_int1).
Figure 23-113 and Table 23-94 illustrate this register.
Figure 23-113. Status Interrupt Line Select Register (SILS) [offset_CC = 2Ch]
31
25
24
17
16
Reserved
26
MTSBL
WUPBL
23
Reserved
18
MTSAL
WUPAL
R-0
R/W-1
R/W-1
R-0
R/W-1
R/W-1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SDSL
MBSIL
SUCSL
SWEL
TOBCL
TIBCL
TI1L
TI0L
NMVCL
RFFL
RFNEL
RXIL
TXIL
CYCSL
CASL
WSTL
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23-94. Status Interrupt Line Select Register (SILS) Field Descriptions
Bit
31-26
25
24
23-18
17
16
15
14
13
12
11
10
Field
Value
Reserved
0
MTSBL
Reads return 0. Writes have no effect.
Media access test symbol channel B interrupt line.
0
Interrupt is assigned to interrupt line CC_int0.
1
Interrupt is assigned to interrupt line CC_int1.
WUPBL
Reserved
Description
Wakeup pattern channel B interrupt line.
0
Interrupt is assigned to interrupt line CC_int0.
1
Interrupt is assigned to interrupt line CC_int1.
0
Reads return 0. Writes have no effect.
MTSAL
Media access test symbol channel A interrupt line.
0
Interrupt is assigned to interrupt line CC_int0.
1
Interrupt is assigned to interrupt line CC_int1.
WUPAL
Wakeup pattern channel A interrupt line.
0
Interrupt is assigned to interrupt line CC_int0.
1
Interrupt is assigned to interrupt line CC_int1.
SDSL
Start of Dynamic Segment interrupt line.
0
Interrupt is assigned to interrupt line CC_int0.
1
Interrupt is assigned to interrupt line CC_int1.
MBSIL
Message buffer status interrupt line.
0
Interrupt is assigned to interrupt line CC_int0.
1
Interrupt is assigned to interrupt line CC_int1.
SUCSL
Startup completed Successfully interrupt line.
0
Interrupt is assigned to interrupt line CC_int0.
1
Interrupt is assigned to interrupt line CC_int1.
SWEL
Stop watch event interrupt line.
0
Interrupt is assigned to interrupt line CC_int0.
1
Interrupt is assigned to interrupt line CC_int1.
TOBCL
Transfer output buffer completed interrupt line.
0
Interrupt is assigned to interrupt line CC_int0.
1
Interrupt is assigned to interrupt line CC_int1.
TIBCL
Transfer input buffer completed interrupt line.
0
Interrupt is assigned to interrupt line CC_int0.
1
Interrupt is assigned to interrupt line CC_int1.
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Table 23-94. Status Interrupt Line Select Register (SILS) Field Descriptions (continued)
Bit
Field
9
TI1L
8
7
6
5
4
3
2
1
0
1174
Value
Description
Timer interrupt 1 line.
0
Interrupt is assigned to interrupt line CC_int0.
1
Interrupt is assigned to interrupt line CC_int1.
TI0L
Timer interrupt 0 line.
0
Interrupt is assigned to interrupt line CC_int0.
1
Interrupt is assigned to interrupt line CC_int1.
NMVCL
Network management vector changed interrupt line.
0
Interrupt is assigned to interrupt line CC_int0.
1
Interrupt is assigned to interrupt line CC_int1.
RFCLL
Receive FIFO full interrupt line.
0
Interrupt is assigned to interrupt line CC_int0.
1
Interrupt is assigned to interrupt line CC_int1.
RFNEL
Receive FIFO not empty interrupt line.
0
Interrupt is assigned to interrupt line CC_int0.
1
Interrupt is assigned to interrupt line CC_int1.
RXIL
Receive interrupt line.
0
Interrupt is assigned to interrupt line CC_int0.
1
Interrupt is assigned to interrupt line CC_int1.
TXIL
Transmit interrupt line.
0
Interrupt is assigned to interrupt line CC_int0.
1
Interrupt is assigned to interrupt line CC_int1.
CYCSL
Cycle start interrupt line.
0
Interrupt is assigned to interrupt line CC_int0.
1
Interrupt is assigned to interrupt line CC_int1.
CASL
Collision Avoidance symbol interrupt line.
0
Interrupt is assigned to interrupt line CC_int0.
1
Interrupt is assigned to interrupt line CC_int1.
WSTL
Wakeup status interrupt line.
0
Interrupt is assigned to interrupt line CC_int0.
1
Interrupt is assigned to interrupt line CC_int1.
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23.19.2.2.5 Error Interrupt Enable Set/Reset (EIES/EIER)
The settings in the error interrupt enable register determine which status changes in the error interrupt
register will result in an interrupt. The enable bits are set by writing to EIES (address 30h) and reset by
writing to EIER (address 34h). Writing 1 sets or resets the specific enable bit, writing 0 has no effect.
Figure 23-114 and Table 23-95 illustrate this register.
Figure 23-114. Error Interrupt Enable Set/Reset Register (EIES/EIER) [offset_CC = 30h/34h]
31
26
25
24
18
17
16
Reserved
27
TABBE
LTVBE
EDBE
Reserved
TABAE
LTVAE
EDAE
R-0
R/W-0
R/W-0
R/W-0
R-0
R/W-0
R/W-0
R/W-0
15
12
23
19
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
MHFE
IOBAE
IIBAE
EFAE
RFOE
PERRE
CCLE
CCFE
SFOE
SFBME
CNAE
PEMCE
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23-95. Error Interrupt Set/Reset Register (EIES/EIER) Field Descriptions
Bit
31-27
26
25
24
23-19
18
17
16
15-12
11
10
9
8
Field
Value
Reserved
0
TABBE
0
Interrupt is disabled.
1
Transmission across boundary channel B interrupt is enabled.
Latest transmit violation channel B interrupt enable.
0
Interrupt is disabled.
1
Latest transmit violation channel B interrupt is enabled.
EDBE
Error detected on channel B interrupt enable.
0
Interrupt is disabled.
1
Error detected on channel B interrupt is enabled.
0
Reads return 0. Writes have no effect.
TABAE
Transmission across boundary channel A interrupt enable.
0
Interrupt is disabled.
1
Transmission across boundary channel A interrupt is enabled.
LTVAE
Latest transmit violation channel A interrupt enable.
0
Interrupt is disabled.
1
Latest transmit violation channel A interrupt is enabled.
EDAE
Reserved
Reads return 0. Writes have no effect.
Transmission across boundary channel B interrupt enable.
LTVBE
Reserved
Description
Error detected on channel A interrupt enable.
0
Interrupt is disabled.
1
Error detected on channel A interrupt is enabled.
0
Reads return 0. Writes have no effect.
MHFE
Message handler constraints flag interrupt enable.
0
Interrupt is disabled.
1
Message handler constraints flag interrupt is enabled.
IOBAE
Illegal output buffer access interrupt enable.
0
Interrupt is disabled.
1
Illegal output buffer access interrupt is enabled.
IIBAE
Illegal input buffer access interrupt enable.
0
Interrupt is disabled.
1
Illegal input buffer access interrupt is enabled.
EFAE
Empty FIFO access interrupt enable.
0
Interrupt is disabled.
1
Empty FIFO access interrupt is enabled.
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Table 23-95. Error Interrupt Set/Reset Register (EIES/EIER) Field Descriptions (continued)
Bit
Field
7
RFOE
6
5
4
3
2
1
0
1176
Value
Description
Receive FIFO overrun interrupt enable.
0
Interrupt is disabled.
1
Receive FIFO overrun interrupt is enabled.
PERRE
Parity error interrupt enable.
0
Interrupt is disabled.
1
Parity error interrupt is enabled.
CCLE
CHI command locked interrupt enable.
0
Interrupt is disabled.
1
CHI command locked interrupt is enabled.
CCFE
Clock correction failure interrupt enable.
0
Interrupt is disabled.
1
Clock correction failure interrupt is enabled.
SFOE
Sync frame overflow interrupt enable.
0
Interrupt is disabled.
1
Sync frame overflow interrupt is enabled.
SFBME
Sync frames below minimum interrupt enable.
0
Interrupt is disabled.
1
Sync frames below minimum interrupt is enabled.
CNAE
Command not Accepted interrupt enable.
0
Interrupt is disabled.
1
Command not valid interrupt is enabled.
PEMCE
POC error mode changed interrupt enable.
0
Interrupt is disabled.
1
Protocol error mode changed interrupt is enabled.
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23.19.2.2.6 Status Interrupt Enable Set/Reset Register (SIES/SIER)
The settings in the status interrupt enable register determine which status changes in the status interrupt
register will result in an interrupt. The enable bits are set by writing to SIES (address 38h) and reset by
writing to SIER (address 3Ch). Writing 1 sets or resets the specific enable bit, writing 0 has no effect.
Figure 23-115 and Table 23-96 illustrate this register.
Figure 23-115. Status Interrupt Enable Set/Reset Register (SIES/SIER) [offset_CC = 38h/3Ch]
31
26
Reserved
25
24
23
18
MTSBE WUPBE
R-0
R/W-0
Reserved
R/W-0
17
16
MTSAE WUPAE
R-0
R/W-0
R/W-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SDSE
MBSIE
SUCSE
SWEE
TOBCE
TIBCE
TI1E
TI0E
NMVCE
RFFE
RFNEE
RXIE
TXIE
CYCSE
CASE
WSTE
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23-96. Status Interrupt Enable Set/Reset Register (SIES/SIER) Field Descriptions
Bit
31-26
25
24
23-18
17
16
15
14
13
12
11
10
Field
Value
Reserved
0
MTSBE
Reads return 0. Writes have no effect.
MTS received on channel B interrupt enable.
0
Interrupt is disabled.
1
MTS received on channel B interrupt is enabled.
WUPBE
Reserved
Description
Wakeup pattern channel B interrupt enable.
0
Interrupt is disabled.
1
Wakeup pattern channel B interrupt is enabled.
0
Reads return 0. Writes have no effect.
MTSAE
MTS received on channel A interrupt enable
0
Interrupt is disabled.
1
MTS received on channel A interrupt is enabled.
WUPAE
Wakeup pattern channel A interrupt enable.
0
Interrupt is disabled.
1
Wakeup pattern channel A interrupt is enabled.
SDSE
Start of dynamic segment interrupt enable.
0
Interrupt is disabled.
1
Start of dynamic segment interrupt is enabled.
MBSIE
Message buffer status interrupt enable.
0
Interrupt is disabled.
1
Message buffer status interrupt is enabled.
SUCSE
Startup completed successfully interrupt enable.
0
Interrupt is disabled.
1
Startup completed successfully interrupt is enabled.
SWEE
Stop watch event interrupt enable.
0
Interrupt is disabled.
1
Stop watch event interrupt is enabled.
TOBCE
Transfer output buffer completed interrupt enable.
0
Interrupt is disabled.
1
Transfer output buffer completed interrupt is enabled.
TIBCE
Transfer input buffer completed interrupt enable.
0
Interrupt is disabled.
1
Transfer input buffer completed interrupt is enabled.
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Table 23-96. Status Interrupt Enable Set/Reset Register (SIES/SIER) Field Descriptions (continued)
Bit
Field
9
TI1E
8
7
6
5
4
3
2
1
0
1178
Value
Description
Timer interrupt 1 enable.
0
Interrupt is disabled.
1
Timer interrupt is 1 is enabled.
TI0E
Timer interrupt 0 enable.
0
Interrupt is disabled.
1
Timer interrupt is 0 is enabled.
NMVCE
Network management vector changed interrupt enable.
0
Interrupt is disabled.
1
Network management vector changed interrupt is enabled.
RFCLE
Receive FIFO full interrupt enable.
0
Interrupt is disabled.
1
Receive FIFO overrun interrupt is enabled.
RFNEE
Receive FIFO not empty interrupt enable.
0
Interrupt is disabled.
1
Receive FIFO not empty interrupt is enabled.
RXIE
Receive interrupt enable.
0
Interrupt is disabled.
1
Receive interrupt is enabled.
TXIE
Transmit interrupt enable.
0
Interrupt is disabled.
1
Transmit interrupt is enabled.
CYCSE
Cycle start interrupt enable.
0
Interrupt is disabled.
1
Cycle start interrupt is enabled.
CASE
Collision avoidance symbol interrupt enable.
0
Interrupt is disabled.
1
Collision Avoidance symbol interrupt is enabled.
WSTE
Wakeup status interrupt enable.
0
Interrupt is disabled.
1
Wakeup status interrupt is enabled.
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23.19.2.2.7 Interrupt Line Enable Register (ILE)
Each of the two interrupt lines (CC_int0, CC_int1) can be enabled and disabled separately by
programming bit EINT0 and EINT1.
Figure 23-116 and Table 23-97 illustrate this register.
Figure 23-116. Interrupt Line Enable Register (ILE) [offset_CC = 40h]
31
16
Reserved
R-0
15
2
1
0
Reserved
EINT
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23-97. Interrupt Line Enable Register (ILE) Field Descriptions
Bit
Field
31-2
Reserved
1-0
EINT
Value
0
Description
Reads return 0. Writes have no effect.
Enable interrupt line (1-0).
0
Interrupt line CC_int1 and CC_int0 are disabled.
1h
Interrupt line CC_int1 is disabled and CC_int0 is enabled.
2h
Interrupt line CC_int1 is enabled and CC_int0 is disabled.
3h
Interrupt line CC_int1 and CC_int0 are enabled.
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23.19.2.2.8 Timer 0 Configuration Register (T0C)
This absolute timer specifies, in terms of cycle count and macrotick, the point in time when the timer 0
interrupt occurs. The timer 0 interrupt generates a non maskable interrupt signal on CC_tint0.
Timer 0 can be activated as long as the POC is either in NORMAL_ACTIVE state or in
NORMAL_PASSIVE state. Timer 0 is deactivated when leaving NORMAL_ACTIVE state or
NORMAL_PASSIVE state except for transitions between the two states.
Before reconfiguration of the timer, the timer has to be halted first by writing bit T0RC to 0.
Figure 23-117 and Table 23-98 illustrate this register.
Figure 23-117. Timer 0 Configuration Register (T0C) [offset_CC = 44h]
31
30
29
16
Reserved
T0MO
R-0
R/W-0
1
0
Rsvd
15
14
T0CC
8
7
Reserved
2
T0MS
T0RC
R-0
R/W-0
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23-98. Timer 0 Configuration Register (T0C) Field Descriptions
Bit
Field
31-30
Reserved
29-16
T0MO
15
Reserved
14-8
T0CC
7-2
Reserved
1
0
1180
Value
0
0-3FFFh
0
0-FFh
0
T0MS
Description
Reads return 0. Writes have no effect.
Timer 0 macrotick offset. Configures the macrotick offset from the beginning of the cycle where the
interrupt is to occur. The Timer 0 interrupt occurs at this offset for each cycle in the cycle set.
Reads return 0. Writes have no effect.
Timer 0 cycle code. The 7-bit timer 0 cycle code determines the cycle set used for generation of
the timer 0 interrupt.
Reads return 0. Writes have no effect.
Timer 0 mode select.
0
Single-shot mode
1
Continuous mode
T0RC
Timer 0 run control.
0
Timer 0 is halted.
1
Timer 0 is running.
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23.19.2.2.9 Timer 1 Configuration Register (T1C)
This relative timer generates an interrupt on the non maskable interrupt signal CC_tint1 after the specified
number of macroticks has expired.
Timer 1 can be activated as long as the POC is either in NORMAL_ACTIVE state or in
NORMAL_PASSIVE state. Timer 1 is deactivated when leaving NORMAL_ACTIVE state or
NORMAL_PASSIVE state except for transitions between the two states.
Before reconfiguration of the timer, the timer has to be halted first by writing a 0 to bit T1RC.
Figure 23-118 and Table 23-99 illustrate this register.
Figure 23-118. Timer 1 Configuration Register (T1C) [offset_CC = 48h]
31
30
29
16
Reserved
T1MC
R-0
R/W-2
15
2
Reserved
R-0
1
0
T1MS
T1RC
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23-99. Timer 1 Configuration Register (T1C) Field Descriptions
Bit
Field
31-30
Reserved
29-16
T1MC
15-2
1
0
Reserved
Value
0
Description
Reads return 0. Writes have no effect.
Timer 1 macrotick count. When the configured macrotick count is reached, the timer 1 interrupt is
generated. In case the configured macrotick count is not within the valid range, timer 1 will not
start.
2h-3FFFh
2 to 16383 macroticks in continuous mode.
1h-3FFFh
1 to 16383 macroticks in single-shot mode.
0
T1MS
Reads return 0. Writes have no effect.
Timer 1 mode select.
0
Single-shot mode
1
Continuous mode
T1RC
Timer 1 run control.
0
Timer 1 is halted.
1
Timer 1 is running.
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23.19.2.2.10 Stop Watch Register 1 Register (STPW1)
The stop watch is activated by an interrupt event (CC_int0 or CC_int1), by writing bit SSWT to 1, or by an
external event.
With the macrotick counter increment following next to the stop watch activation the actual cycle counter
and macrotick value is stored in the stop watch register 1 (stop watch event) and the slot counter values
for channel A and channel B are stored in stop watch register 2.
Figure 23-119 and Table 23-100 illustrate this register.
Figure 23-119. Stop Watch Register 1 (STPW1) [offset_CC = 4Ch]
31
30
29
16
Reserved
SMTV
R-0
R-0
15
7
6
5
4
3
Reserved
14
13
SCCV
8
Rsvd
EINT1
EINT0
EETP
SSWT
EDGE SWMS ESWT
2
1
R-0
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23-100. Stop Watch Register 1 (STPW1) Field Descriptions
Bit
Field
31-30
Reserved
29-16
SMTV
15-14
Reserved
13-8
SCCV
7
Reserved
6
EINT1
5
4
3
2
1
0
1182
Value
0
0-3E80h
0
0-3Fh
0
Description
Reads return 0. Writes have no effect.
Stopped macrotick value. State of the macrotick counter when the stop watch event occurred.
Reads return 0. Writes have no effect.
Stopped cycle counter value. State of the cycle counter when the stop watch event occurred.
Reads return 0. Writes have no effect.
Enable interrupt 1 trigger. Enables stop watch trigger by CC_int1 event if ESWT = 1.
0
Stop watch trigger by CC_int1 is disabled.
1
CC_int1 event triggers stop watch.
EINT0
Enable interrupt 0 trigger. Enables stop watch trigger by CC_int0 event if ESWT = 1.
0
Stop watch trigger by CC_int0 is disabled.
1
CC_int0 event triggers stop watch.
EETP
Enable external trigger pin. Enables stop watch trigger event from external pin, if ESWT = 1.
0
External trigger is disabled.
1
Stop watch activated by external trigger.
SSWT
Software stop watch trigger. When the host writes this bit to 1 the stop watch is activated. After the
actual cycle counter and macrotick value are stored in the stop watch register this bit is reset to 0.
The bit is only writable while ESWT = 0.
0
Software trigger reset.
1
Stop watch activated by software trigger.
EDGE
Stop watch trigger edge select.
0
Falling edge
1
Rising edge
SWMS
Stop watch mode select.
0
Single-shot mode
1
Continuous mode
ESWT
External stop watch trigger. If enabled an external event activates the stop watch. In single-shot
mode this bit is reset to 0 after the stop watch event occurred.
0
External stop watch trigger is disabled.
1
External stop watch trigger is enabled.
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NOTE: Bits ESWT and SSWT cannot be set to 1 simultaneously. In this case the write access to the
register is ignored, and both bits keep their previous values. Either the external stop watch
trigger or the software stop watch trigger may be used.
The availability of an external stop watch pin is device dependant. Please refer to the device
data sheet for details.
23.19.2.2.11 Stop Watch Register 2 Register (STPW2)
Figure 23-120 and Table 23-101 illustrate this register.
Figure 23-120. Stop Watch Register 2 (STPW2) [offset_CC = 50h]
31
27
26
16
Reserved
SSCVB
R-0
R-0
15
11
10
0
Reserved
SSCVA
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23-101. Stop Watch Register 2 (STPW2) Field Descriptions
Bit
Field
31-27
Reserved
26-16
SSCVB
15-11
Reserved
10-0
SSCVA
Value
0
0-7FFh
0
0-7FFh
Description
Reads return 0. Writes have no effect.
Stop watch captured slot counter value channel B. State of the slot counter for channel B when the
stop watch event occurred.
Reads return 0. Writes have no effect.
Stop watch captured slot counter value channel A. State of the slot counter for channel A when the
stop watch event occurred.
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23.19.2.3 Control Registers
This section describes the registers provided by the communication controller to allow the host to control
the operation of the communication controller. The FlexRay protocol specification requires the host to write
application configuration data in CONFIG state only.
NOTE: Be aware that the configuration registers are not locked for writing in DEFAULT_CONFIG
state.
The configuration data is reset when DEFAULT_CONFIG state is entered from hardware reset. To change
POC state from DEFAULT_CONFIG to CONFIG state the host has to apply the controller host interface
command CONFIG. If the host wants the communication controller to leave CONFIG state, the host has to
proceed as described in Lock Register (LCK).
NOTE: All bits marked with an asterisk (*) can be updated in DEFAULT_CONFIG or CONFIG state
only.
23.19.2.3.1 SUC Configuration Register 1 (SUCC1)
The communication controller accepts modifications of the register in DEFAULT_CONFIG or CONFIG
state only.
Figure 23-121 and Table 23-102 illustrate this register.
Figure 23-121. SUC Configuration Register 1 (SUCC1) [offset_CC = 80h]
31
27
26
25
Reserved
28
CCHB*
CCHA*
MTSB*
R-0
R/W-1
R/W-1
R/W-0 R/W-0 R/W-0 R/W-1
15
11
10
CSA*
Rsvd
R/W-2h
R-0
9
24
MTSA*
8
TXSY* TXST*
R/W-0
R/W-0
23
22
HCSE*
TSM*
7
21
20
16
WUCS*
PTA*
R/W-0
R/W-0
6
4
3
0
PBSY
Reserved
CMD*
R-1
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; *These bits can be updated in DEFAULT_CONFIG or CONFIG state
only
Table 23-102. SUC Configuration Register 1 (SUCC1) Field Descriptions
Bit
31-28
27
26
25
Field
Reserved
Value
0
CCHB
Description
Reads return 0. Writes have no effect.
Connected to channel B. Configures whether the node is connected to channel B.
0
Node is not connected to channel B.
1
Node is connected to channel B (default by hardware reset).
CCHA
Connected to channel A. Configures whether the node is connected to channel A.
0
Node is not connected to channel A.
1
Node is connected to channel A (default by hardware reset).
MTSB
Select channel B for MTS Transmission. The bit selects channel B for MTS symbol
transmission if requested by writing CMD = 8h. The flag is reset by default and may be modified
only in DEFAULT_CONFIG or CONFIG state.
0
Channel B is not selected for MTS transmission.
1
Channel B is selected for MTS transmission.
Note: MTSB may also be changed outside DEFAULT_CONFIG or CONFIG state when the
write to SUC Configuration Register 1 (SUCC1) is directly preceded by the unlock
sequence for the Configuration Lock Key as described in the Lock Register (LCK). This
may be combined with CHI command SEND_MTS. If both bits MTSA and MTSB are set to
1 an MTS symbol will be transmitted on both channels when requested by writing CMD =
8h.
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Table 23-102. SUC Configuration Register 1 (SUCC1) Field Descriptions (continued)
Bit
Field
24
MTSA
Value
Description
Select channel A for MTS Transmission. The bit selects channel A for MTS symbol
transmission if requested by writing CMD = 8h. The flag is reset by default and may be modified
only in DEFAULT_CONFIG or CONFIG state.
0
Channel A is not selected for MTS transmission.
1
Channel A is selected for MTS transmission.
Note: MTSA may also be changed outside DEFAULT_CONFIG or CONFIG state when the
write to SUC Configuration Register 1 (SUCC1) is directly preceded by the unlock
sequence for the Configuration Lock Key as described in the Lock Register (LCK). This
may be combined with CHI command SEND_MTS. If both bits MTSA and MTSB are set to
1 an MTS symbol will be transmitted on both channels when requested by writing CMD =
8h.
23
22
21
HCSE
Halt due to clock sync error. Controls reaction of the communication controller to a clock
synchronization error. The bit can be modified in DEFAULT_CONFIG or CONFIG state only.
0
Communication controller will enter/remain in NORMAL_PASSIVE.
1
Communication controller will enter HALT state.
TSM
Transmission slot mode. Selects the initial transmission slot mode. In SINGLE slot mode the
communication controller may only transmit in the pre-configured key slot. This slot is defined
by the key slot ID, which is configured in the header section of message buffer 0. In all slot
mode the communication controller may transmit in all slots. The bit can be written in
DEFAULT_CONFIG or CONFIG state only. The communication controller changes to all slot
mode when the host successfully applied the ALL_SLOTS command by writing CMD = 5h in
POC states NORMAL_ACTIVE or NORMAL_PASSIVE. The actual slot mode is monitored by
SLM in register CCSV.
0
All slot mode
1
Single slot mode (default by hardware reset)
WUCS
Wakeup channel select. With this bit the host selects the channel on which the communication
controller sends the Wakeup pattern. The communication controller ignores any attempt to
change the status of this bit when not in DEFAULT_CONFIG or CONFIG state.
0
Send wakeup pattern on channel A.
1
Send wakeup pattern on channel B.
20-16
PTA
0-1Fh
even/odd
cycle pairs
Passive to active. Defines the number of consecutive even/odd cycle pairs that must have valid
clock correction terms before the communication controller is allowed to transit from
NORMAL_PASSIVE to NORMAL_ACTIVE state. If set to 0 the communication controller is not
allowed to transit from NORMAL_PASSIVE to NORMAL_ACTIVE state. It can be modified in
DEFAULT_CONFIG or CONFIG state only.
15-11
CSA
2h-1Fh
Cold start attempts. Configures the maximum number of attempts that a cold starting node is
permitted to try to start up the network without receiving any valid response from another node.
It can be modified in DEFAULT_CONFIG or CONFIG state only. Must be identical in all nodes
of a cluster.
10
Reserved
9
TXSY
0
Reads return 0. Writes have no effect.
Transmit sync frame in key slot. Defines whether the key slot is used to transmit a sync frame.
The bit can be modified in DEFAULT_CONFIG or CONFIG state only.
Note: The protocol requires that both bits TXST and TXSY are set for coldstart nodes.
8
0
No sync frame transmission in key slot, node is neither sync nor coldstart node.
1
Key slot used to transmit sync frame, node is sync node.
TXST
Transmit startup frame in key slot. Defines whether the key slot is used to transmit a startup
frame. The bit can be modified in DEFAULT_CONFIG or CONFIG state only.
Note: The protocol requires that both bits TXST and TXSY are set for coldstart nodes.
7
6-4
0
No startup frame transmitted in key slot, node is non-coldstarter.
1
Key slot used to transmit startup frame, node is leading or following coldstarter.
PBSY
Reserved
POC busy. Signals that the POC is busy and cannot accept a command from the host. CMD is
locked against write accesses.
0
POC is not busy, CMD(3-0) is writable.
1
POC is busy, CMD(3-0) is locked.
0
Reads return 0. Writes have no effect.
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Table 23-102. SUC Configuration Register 1 (SUCC1) Field Descriptions (continued)
Bit
Field
3-0
CMD
Value
Description
The controller host interface command vector. The host may write any controller host interface
command at any time, but certain commands are enabled only in certain POC states. If a
command is not enabled, it will not be executed, the controller host interface command vector
CMD will be reset to 0000 = command_not_accepted, and flag CNA in the error interrupt
register will be set to 1. In case the previous controller host interface (CHI) command has not
yet completed, EIR.CCL is set to 1 together with EIR.CNA; the CHI command needs to be
repeated. Except for HALT state, a POC state change command applied while the
communication controller is already in the requested POC state neither causes a state change
nor will EIR.CNA be set.
0
command_not_accepted
1h
CONFIG
2h
READY
3h
WAKEUP
4h
RUN
5h
ALL_SLOTS
6h
HALT
7h
FREEZE
8h
SEND_MTS
9h
ALLOW_COLDSTART
Ah
RESET_STATUS_INDICATORS
Bh
MONITOR_MODE
Ch
CLEAR_RAMS
Dh-Eh
Fh
Reserved
LOOPBACK MODE
Controller Host Interface Command Vector:
The following gives more information about the controller host interface commands.
• Reading CMD shows whether the last controller host interface command was accepted.
• The actual POC state is monitored by POCS in the communication controller status vector
• In most cases the Host must check SUCC1.PBSY before writing a new CHI command.
command_not_accepted
CMD is reset to 0000 due to one of the following conditions:
• Illegal command applied by the host
• Host applied command to leave CONFIG state without preceding configuration lock key
• Host applied new command while execution of the previous host command has not completed
• Host writes command_not_accepted
When CMD is reset to 0000 due to an unaccepted command, bit CNA in the error interrupt register is set,
and, if enabled, an interrupt is generated. Commands which are not accepted are not executed.
CONFIG
Go to POC state CONFIG when called in POC states DEFAULT_CONFIG, READY, or in
MONITOR_MODE. When called in HALT state the communication controller transits to POC state
DEFAULT_CONFIG. When called in any other state, CMD will be reset to 0000 =
command_not_accepted.
READY
Go to POC state READY when called in POC states CONFIG, NORMAL_ACTIVE, NORMAL_PASSIVE,
STARTUP, or WAKEUP. When called in any other state, CMD will be reset to 0000 =
command_not_accepted.
1186
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WAKEUP
Go to POC state WAKEUP when called in POC state READY. When called in any other state, CMD will
be reset to 0000 = command_not_accepted.
RUN
Go to POC state STARTUP when called in POC state READY. When called in any other state, CMD will
be reset to 0000 = command_not_accepted.
ALL_SLOTS
Leave single slot mode after successful startup / integration at the next end of cycle when called in POC
states NORMAL_ACTIVE or NORMAL_PASSIVE. When called in any other state, CMD will be reset to
0000 = command_not_accepted.
HALT
Set the Halt request HRQ bit in the communication controller status vector register and go to POC state
HALT at the next end of cycle when called in POC states NORMAL_ACTIVE or NORMAL_PASSIVE.
When called in any other state, CMD will be reset to 0000 = command_not_accepted.
FREEZE
Go to POC state HALT immediately and set the Freeze status Indicator FSI bit in the communication
controller status vector register. Can be called from any state.
SEND_MTS
Send single MTS symbol during the symbol window of the following cycle on the channel configured by
MTSA, MTSB, when called in POC state NORMAL_ACTIVE. When called in any other state, CMD will be
reset to 0000 = command_not_accepted.
ALLOW_COLDSTART
The command resets bit CSI in the CCSV register to enable coldstarting of the node when called in any
POC state except DEFAULT_CONFIG, CONFIG or HALT. When called in these states, CMD will be reset
to 0000 = command_not_accepted.
RESET_STATUS_INDICATORS
Reset status flags FSI, HRQ, CSNI, and CSAI in the communication controller status vector register.
CLEAR_RAMS
Sets bit CRAM in the message handler status register when called in DEFAULT_CONFIG or CONFIG
state. When called in any other state, CMD will be reset to 0000 = command_not_accepted. Bit CRAM is
also set when the communication controller leaves hardware reset. By setting bit CRAM all internal RAM
blocks are initialized to zero. During the initialization of the RAMs, PBSY will show POC busy. Access to
the configuration and status registers is possible during execution of CHI command CLEAR_RAMS.
The initialization of the Communication Controller internal RAM blocks takes 2048 VBUS clock cycles.
There should be no host access to IBF or OBF during initialization of the internal RAM blocks after
hardware reset or after assertion of controller host interface command CLEAR_RAMS. Before asserting
controller host interface command CLEAR_RAMS the host should be aware that no transfer between
message RAM and IBF / OBF or the transient buffer RAMs is ongoing. This command also resets the
message buffer status registers (MHDS, TXRQ[1-4], NDAT[1-4], MBSC[1-4]).
NOTE: All accepted commands with exception of CLEAR_RAMS and SEND_MTS will cause a
change of the POC state in the VBUS clock domain after at most 8 cycles of the slower of
the two clocks VBUS clock and 80MHz sample clock coming from the PLL. It is assumed
that POC was not busy when the command was applied and that no POC state change was
forced by bus activity in that time frame. Reading register Communication Controller Status
Vector (CCSV) will show data that is additionally delayed by synchronization from sample
clock to VBUS clock domain and by the CPU interface. The maximum additional delay is
12 cycles of the slower of the two clocks VBUS clock and sample clock.
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MONITOR_MODE
Enter MONITOR_MODE when called in POC state CONFIG. In this mode the communication controller is
able to receive FlexRay frames and CAS / MTS symbols. It is also able to detect coding errors. The
temporal integrity of received frames is not checked. This mode can be used for debugging purposes, for
example, in case that the startup of a FlexRay network fails. When called in any other state, CMD will be
reset to 0000 = command_not_accepted.
23.19.2.3.2 SUC Configuration Register 2 (SUCC2)
The communication controller accepts modifications of the register in DEFAULT_CONFIG or CONFIG
state only.
Figure 23-122 and Table 23-103 illustrate this register.
Figure 23-122. SUC Configuration Register 2 (SUCC2) [offset_CC = 84h]
31
28
27
24
23
21
20
16
Reserved
LTN*
Reserved
LT*
R-0
R/W-1h
R-0
R/W-504h
15
0
LT*
R/W-504h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; *These bits can be updated in DEFAULT_CONFIG or CONFIG state
only.
Table 23-103. SUC Configuration Register 2 (SUCC2) Field Descriptions
Bit
Field
31-28
Reserved.
27-24
LTN
23-21
Reserved.
20-0
LT
Value
0
2h-Fh
Description
Reads return 0. Writes have no effect.
Listen timeout noise. Configures the upper limit for the startup and wakeup listen timeout in the
presence of noise. Must be identical in all nodes of a cluster.
The wakeup / startup noise timeout is calculated as follows: LT × (LTN + 1)
1188
0
Reads return 0. Writes have no effect.
504h-139706h µT Listen timeout. Configures the upper limit of the startup and wakeup listen timeout.
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23.19.2.3.3 SUC Configuration Register 3 (SUCC3)
The communication controller accepts modifications of the register in DEFAULT_CONFIG or CONFIG
state only.
Figure 23-123 and Table 23-104 illustrate this register.
Figure 23-123. SUC Configuration Register 3 (SUCC3) [offset_CC = 88h]
31
16
Reserved
R-0
15
8
7
4
3
0
Reserved
WCF*
WCP*
R-0
R/W-1h
R/W-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; *These bits can be updated in DEFAULT_CONFIG or CONFIG state
only.
Table 23-104. SUC Configuration Register 3 (SUCC3) Field Descriptions
Bit
Field
31-8
Reserved
7-4
WCF
Value
0
1h-Fh
Description
Reads return 0. Writes have no effect.
Maximum without clock correction fatal. These bits define the number of consecutive even/odd
cycle pairs with missing clock correction terms that will cause a transition from NORMAL_ACTIVE
or NORMAL_PASSIVE state. These must be identical in all nodes of a cluster.
Note: The transition to HALT state is prevented if SUCC1.HCSE is not set.
3-0
WCP
1h-Fh
Maximum without clock correction passive. These bits define the number of consecutive even/odd
cycle pairs with missing clock correction terms that will cause a transition from NORMAL_ACTIVE
to NORMAL_PASSIVE to HALT state. These must be identical in all nodes of a cluster.
23.19.2.3.4 NEM Configuration Register (NEMC)
The communication controller accepts modifications of the register in DEFAULT_CONFIG or CONFIG
state only.
Figure 23-124 and Table 23-105 illustrate this register.
Figure 23-124. NEM Configuration Register (NEMC) [offset_CC = 8Ch]
31
16
Reserved
R-0
15
4
3
0
Reserved
NML*
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; *These bits can be updated in DEFAULT_CONFIG or CONFIG state
only
Table 23-105. NEM Configuration Register (NEMC) Field Descriptions
Bit
Field
31-4
Reserved.
3-0
NML
Value
0
0-Ch bytes
Description
Reads return 0. Writes have no effect.
Network management vector length (in bytes).
These bits configure the length of the NM vector. The configured length must be identical in all
nodes of a cluster.
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23.19.2.3.5 PRT Configuration Register 1 (PRTC1)
The communication controller accepts modifications of the register in DEFAULT_CONFIG or CONFIG
state only.
Figure 23-125 and Table 23-106 illustrate this register.
Figure 23-125. PRT Configuration Register 1 (PRTC1) [offset_CC = 90h]
31
26
15
14
25
24
16
RWP*
Rsvd
RXW*
R/W-2h
R-0
R/W-4Ch
13
12
11
10
4
3
0
BRP*
SPP*
Rsvd
CASM*
TSST*
R/W-0
R/W-0
R-0
R/W-23h
R/W-3h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; *These bits can be updated in DEFAULT_CONFIG or CONFIG state
only
Table 23-106. PRT Configuration Register 1 (PRTC1) Field Descriptions
Bit
Field
Value
Description
31-26
RWP
2h-3Fh
Repetition of transmission wakeup pattern. These bits configure the number of repetitions
(sequences) of the transmission wakeup symbol.
25
Reserved
24-16
RXW
15-14
BRP
0
4Ch-12Dh
Wakeup symbol receive window length. Configures the number of bit times used by the node to
test the duration of the received wakeup pattern. Must be identical in all nodes of a cluster.
Baud rate prescaler. These bits configure the baud rate on the FlexRay bus. The baud rates
listed below are valid with a sample clock of 80 MHz. One bit time always consists of 8 samples
independent of the configured baud rate.
0
10 Mbit/s (Sample Clock Period = 12.5ns; 1 µT = 25ns; Samples per µT = 2)
1h
5 Mbit/s (Sample Clock Period = 25ns; 1 µT = 25ns; Samples per µT = 1)
2h, 3h
13-12
Reads return 0. Writes have no effect.
SPP
2.5 Mbit/s (Sample Clock Period = 50ns; 1 µT = 50ns; Samples per µT = 1)
Strobe Point Position. Defines the sample count value for strobing. The strobed bit value is set
to the voted value when the sample count is incremented to the value configured by SPP.
Note: The current revision 2.1 of the FlexRay protocol requires that SPP = 00. The
alternate strobe point positions could be used to compensate for asymmetries in the
physical layer.
11
Reserved
10-4
CASM
3-0
TSST
1190
0, 3h
Sample 5
1h
Sample 4
2h
Sample 6
0
Reads return 0. Writes have no effect.
43h-63h bit times Collision avoidance symbol max (in bit times). These bits configure the upper limit of the
acceptance window for a collision avoidance symbol (CAS). CASM6 is always 1.
3h-Fh bit times
Transmission start sequence transmitter (in bit times). These bits configure the duration of the
transmission start sequence (TSS) in terms of bit times (1 bit time = 4 µT = 100ns @ 10Mbps).
Must be identical in all nodes of a cluster.
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23.19.2.3.6 PRT Configuration Register 2 (PRTC2)
The communication controller accepts modifications of the register in DEFAULT_CONFIG or CONFIG
state only.
Figure 23-126 and Table 23-107 illustrate this register.
Figure 23-126. PRT Configuration Register 2 (PRTC2) [offset_CC = 94h]
31
30
29
24
23
16
Reserved
TXL*
TXI*
R-0
R/W-Fh
R/W-2Dh
15
14
13
8
7
6
5
0
Reserved
RXL*
Reserved
RXI*
R-0
R/W-Ah
R-0
R/W-Eh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; *These bits can be updated in DEFAULT_CONFIG or CONFIG state
only
Table 23-107. PRT Configuration Register 2 (PRTC2) Field Descriptions
Bit
Field
31-30
Reserved
29-24
TXL
23-16
TXI
15-14
Reserved
13-8
RXL
7-6
Reserved
5-0
RXI
Value
0
Fh-3Ch bit times
Description
Reads return 0. Writes have no effect.
Wakeup symbol transmit low (in bit times). These bits configure the active low phase of the
wakeup symbol. The duration must be identical in all nodes of a cluster.
2Dh-B4h bit times Wakeup symbol transmit idle (in bit times). These bits configure the number of bit times used by
the node to transmit the idle phase of the wakeup symbol. Durations must be identical in all
nodes of a cluster.
0
Ah-37h bit times
0
Eh-37h bit times
Reads return 0. Writes have no effect.
Wakeup symbol receive low (in bit times). These bits configure the number of bit times used by
the node to test the duration of the low phase of the received wakeup symbol. Must be identical
in all nodes of a cluster.
Reads return 0. Writes have no effect.
Wakeup symbol receive idle (in bit times). These bits configure the number of bit times used by
the node to test the duration of the idle phase of the received wakeup symbol. Must be identical
in all nodes of a cluster.
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23.19.2.3.7 MHD Configuration Register (MHDC)
The communication controller accepts modifications of the register in DEFAULT_CONFIG or CONFIG
state only.
Figure 23-127 and Table 23-108 illustrate this register.
Figure 23-127. MHD Configuration Register (MHDC) [offset_CC = 98h]
31
29
28
16
Reserved
SLT*
R-0
R/W-2h
15
7
6
0
Reserved
SFDL*
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; *These bits can be updated in DEFAULT_CONFIG or CONFIG state
only
Table 23-108. MHD Configuration Register (MHDC) Field Descriptions
Bit
Field
31-29
Reserved
28-16
SLT
15-7
Reserved
6-0
SFDL
1192
Value
0
0-1F2Dh
minislots
0
0-7Fh
Description
Reads return 0. Writes have no effect.
Start of latest transmit (in minislots). These bits configure the maximum minislot value allowed
before inhibiting new frame transmissions in the Dynamic Segment of the cycle. There is no
transmission in dynamic segment if SLT is cleared to 0.
Reads return 0. Writes have no effect.
Static frame data length. These bits configure the cluster-wide payload length for all frames sent
in the static segment in double bytes. The payload length must be identical in all nodes of a
cluster.
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23.19.2.3.8 GTU Configuration Register 1 (GTUC1)
The communication controller accepts modifications of the register in DEFAULT_CONFIG or CONFIG
state only.
Figure 23-128 and Table 23-109 illustrate this register.
Figure 23-128. GTU Configuration Register 1 (GTUC1) [offset_CC = A0h]
31
20
19
16
Reserved
UT*
R-0
R/W-0
15
0
UT*
R/W-0280h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; *These bits can be updated in DEFAULT_CONFIG or CONFIG state
only
Table 23-109. GTU Configuration Register 1 (GTUC1) Field Descriptions
Bit
Field
Value
31-20
Reserved.
19-0
UT
0
280h-9C400h µT
Description
Reads return 0. Writes have no effect.
Microtick per cycle (in microticks).
These bits configure the duration of the communication cycle in microticks.
23.19.2.3.9 GTU Configuration Register 2 (GTUC2)
The communication controller accepts modifications of the register in DEFAULT_CONFIG or CONFIG
state only.
Figure 23-129 and Table 23-110 illustrate this register.
Figure 23-129. GTU Configuration Register 2 (GTUC2) [offset_CC = A4h]
31
20
15
14
19
16
Reserved
SNM*
R-0
R/W-2h
13
0
Reserved
MPC*
R-0
R/W-Ah
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; *These bits can be updated in DEFAULT_CONFIG or CONFIG state
only
Table 23-110. GTU Configuration Register 2 (GTUC2) Field Descriptions
Bit
Field
31-20
Reserved
19-16
SNM
15-14
Reserved
13-0
MPC
Value
0
2h-Fh frames
0
Ah-3E80h MT
Description
Reads return 0. Writes have no effect.
Sync node max (in frames). These bits configure the maximum number of frames within a
cluster with sync frame indicator bit SYN set. The number of frames must be identical in all
nodes of a cluster.
Reads return 0. Writes have no effect.
Macrotick per cycle (in macroticks). These bits configure the duration of one communication
cycle in macroticks. The cycle length must be identical in all nodes of a cluster.
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23.19.2.3.10 GTU Configuration Register 3 (GTUC3)
The communication controller accepts modifications of the register in DEFAULT_CONFIG or CONFIG
state only.
Figure 23-130 and Table 23-111 illustrate this register.
Figure 23-130. GTU Configuration Register 3 (GTUC3) [offset_CC = A8h]
31
30
24
23
22
16
Rsvd
MIOB*
Rsvd
MIOA*
R-0
R/W-2h
R-0
R/W-2h
15
8
7
0
UIOB*
UIOA*
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; *These bits can be updated in DEFAULT_CONFIG or CONFIG state
only.
Table 23-111. GTU Configuration Register 3 (GTUC3) Field Descriptions
Bit
Field
31
Reserved
30-24
23
MIOB
Reserved
Value
0
2h-48h MT
0
Description
Reads return 0. Writes have no effect.
Macrotick initial offset channel B (in macroticks). These bits configure the number of macroticks
between the static slot boundary and the subsequent macrotick boundary of the secondary time
reference point based on the nominal macrotick duration. Must be identical in all nodes of a
cluster.
Reads return 0. Writes have no effect.
22-16
MIOA
2h-48h MT
15-8
UIOB
0-F0h µT
Microtick initial offset channel B (in microticks). These bits configure the number of microticks
between the actual time reference point on channel B and the subsequent macrotick boundary of
the secondary time reference point. The parameter has to be set for each channel independently.
7-0
UIOA
0-F0h µT
Microtick initial offset channel A (in microticks). These bits configure the number of microticks
between the actual time reference point on channel A and the subsequent macrotick boundary of
the secondary time reference point. The parameter has to be set for each channel independently.
1194
Macrotick initial offset channel A (in macroticks). These bits configure the number of macroticks
between the static slot boundary and the subsequent macrotick boundary of the secondary time
reference point based on the nominal macrotick duration. Must be identical in all nodes of a
cluster.
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23.19.2.3.11 GTU Configuration Register 4 (GTUC4)
The communication controller accepts modifications of the register in DEFAULT_CONFIG or CONFIG
state only. Figure 23-131 and Table 23-112 illustrate this register.
Figure 23-131. GTU Configuration Register 4 (GTUC4) [offset_CC = ACh]
31
30
29
16
Reserved
OCS*
R-0
R/W-Ah
15
14
13
0
Reserved
NIT*
R-0
R/W-9h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; *These bits can be updated in DEFAULT_CONFIG or CONFIG state
only
Table 23-112. GTU Configuration Register 4 (GTUC4) Field Descriptions
Bit
Field
31-30
Reserved
29-16
OCS
15-14
Reserved
13-0
NIT
Value
0
8h-3E7Eh MT
0
7h-3E7Dh MT
Description
Reads return 0. Writes have no effect.
Offset correction start (in macroticks). These bits determine the start of the offset correction
within the NIT phase, calculated from start of cycle. Must be identical in all nodes of a cluster.
Reads return 0. Writes have no effect.
Network idle time start (in macroticks). These bits configure the starting point of the network idle
time (NIT) at the end of the communication cycle expressed in terms of macroticks from the
beginning of the cycle. The number must be identical in all nodes of a cluster.
23.19.2.3.12 GTU Configuration Register 5 (GTUC5)
The communication controller accepts modifications of the register in DEFAULT_CONFIG or CONFIG
state only. Figure 23-132 and Table 23-113 illustrate this register.
Figure 23-132. GTU Configuration Register 5 (GTUC5) [offset_CC = B0h]
31
24
23
21
20
16
DEC*
Reserved
CDD*
R/W-Eh
R-0
R/W-0
15
8
7
0
DCB*
DCA*
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; *These bits can be updated in DEFAULT_CONFIG or CONFIG state
only
Table 23-113. GTU Configuration Register 5 (GTUC5) Field Descriptions
Bit
Field
Value
31-24
DEC
Eh-8Fh µT
23-21
Reserved.
20-16
CDD
0-14h µT
Cluster drift damping (in microticks). These bits configure the cluster drift damping value used in
clock synchronization to minimize accumulation of rounding errors.
15-8
DCB
0-C8h µT
Delay compensation channel B (in microticks). These bits are used to compensate for reception
delays on the indicated channel. This compensates propagation delays for microticks in the
range of 0.0125 to 0.05s. In practice, the minimum propagation delay of all sync nodes should
be applied.
7-0
DCA
0-C8h µT
Delay compensation channel A (in microticks). These bits are used to compensate for reception
delays on the indicated channel. This compensates propagation delays for microticks in the
range of 0.0125 to 0.05s. In practice, the minimum propagation delay of all sync nodes should
be applied.
0
Description
Decoding correction (in microticks). These bits configure the decoding correction value used to
determine the primary time reference point.
Reads return 0. Writes have no effect.
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23.19.2.3.13 GTU Configuration Register 6 (GTUC6)
The communication controller accepts modifications of the register in DEFAULT_CONFIG or CONFIG
state only.
Figure 23-133 and Table 23-114 illustrate this register.
Figure 23-133. GTU Configuration Register 6 (GTUC6) [offset_CC = B4h]
31
27
26
16
Reserved
MOD*
R-0
R/W-2h
15
11
10
0
Reserved
ASR*
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; *These bits can be updated in DEFAULT_CONFIG or CONFIG state
only
Table 23-114. GTU Configuration Register 6 (GTUC6) Field Descriptions
Bit
Field
31-27
Reserved
26-16
MOD
15-11
Reserved
10-0
ASR
Value
0
2h-783h µT
0
0-753h µT
Description
Reads return 0. Writes have no effect.
Maximum oscillator drift (in microticks). Maximum drift offset between two nodes that operate with
unsynchronized clocks over one communication cycle in µT.
Reads return 0. Writes have no effect.
Accepted startup range (in microticks). Number of microticks constituting the expanded range of
measured deviation for startup frames during integration.
23.19.2.3.14 GTU Configuration Register 7 (GTUC7)
The communication controller accepts modifications of the register in DEFAULT_CONFIG or CONFIG
state only.
Figure 23-134 and Table 23-115 illustrate this register.
Figure 23-134. GTU Configuration Register 7 (GTUC7) [offset_CC = B8h]
31
26
25
16
Reserved
NSS*
R-0
R/W-2h
15
10
9
0
Reserved
SSL*
R-0
R/W-4h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; *These bits can be updated in DEFAULT_CONFIG or CONFIG state
only
Table 23-115. GTU Configuration Register 7 (GTUC7) Field Descriptions
Bit
Field
31-26
Reserved.
25-16
NSS
15-10
Reserved.
9-0
1196
SSL
Value
0
2h-3FFh MT
0
4h-293h MT
Description
Reads return 0. Writes have no effect.
Number of static slots (in macroticks). These bits configure the number of static slots in a cycle.
At least two coldstart nodes must be configured to startup a FlexRay network. The number of
static slots must be identical in all nodes of a cluster.
Reads return 0. Writes have no effect.
Static slot length (in macroticks). These bits configure the duration of a static slot. The static slot
length must be identical in all nodes of a cluster.
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23.19.2.3.15 GTU Configuration Register 8 (GTUC8)
The communication controller accepts modifications of the register in DEFAULT_CONFIG or CONFIG
state only.
Figure 23-135 and Table 23-116 illustrate this register.
Figure 23-135. GTU Configuration Register 8 (GTUC8) [offset_CC = BCh]
31
29
28
16
Reserved
NMS*
R-0
R/W-0
15
6
5
0
Reserved
MSL*
R-0
R/W-2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; *These bits can be updated in DEFAULT_CONFIG or CONFIG state
only
Table 23-116. GTU Configuration Register 8 (GTUC8) Field Descriptions
Bit
Field
31-29
Reserved
28-16
NMS
15-6
Reserved
5-0
MSL
Value
0
0-1F32h
0
2h-3Fh MT
Description
Reads return 0. Writes have no effect.
Number of minislots. These bits configure the number of minislots in the dynamic segment of a
cycle. The number of minislots must be identical in all nodes of a cluster.
Reads return 0. Writes have no effect.
Minislot length (in macroticks). These bits configure the duration of a minislot. The minislot length
must be identical in all nodes of a cluster.
23.19.2.3.16 GTU Configuration Register 9 (GTUC9)
The communication controller accepts modifications of the register in DEFAULT_CONFIG or CONFIG
state only.
Figure 23-136 and Table 23-117 illustrate this register.
Figure 23-136. GTU Configuration Register 9 (GTUC9) [offset_CC = C0h]
31
18
15
13
12
17
16
Reserved
DSI*
R-0
R/W-0
8
7
6
5
0
Reserved
MAPO*
Reserved
APO*
R-0
R/W-1h
R-0
R/W-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; *These bits can be updated in DEFAULT_CONFIG or CONFIG state
only
Table 23-117. GTU Configuration Register 9 (GTUC9) Field Descriptions
Bit
Field
31-18
Reserved
17-16
DSI
15-13
Reserved
12-8
MAPO
7-6
Reserved
5-0
APO
Value
0
0-2h
0
1h-1Fh MT
0
1h-3Fh MT
Description
Reads return 0. Writes have no effect.
Dynamic slot idle phase (in minislots). The duration of the dynamic slot idle phase has to be
greater or equal than the idle detection time. Must be identical in all nodes of a cluster.
Reads return 0. Writes have no effect.
Minislot action point offset (in macroticks). These bits configure the minislot action point offset
within the minislots of the dynamic segment. The minislot action point offset must be identical in all
nodes of a cluster.
Reads return 0. Writes have no effect.
Action point offset (in macroticks). These bits configure the action point offset within static slots
and symbol window. The action point offset must be identical in all nodes of a cluster.
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23.19.2.3.17 GTU Configuration Register 10 (GTUC10)
The communication controller accepts modifications of the register in DEFAULT_CONFIG or CONFIG
state only.
Figure 23-137 and Table 23-118 illustrate this register.
Figure 23-137. GTU Configuration Register 10 (GTUC10) [offset_CC = C4h]
31
27
15
26
16
Reserved
MRC*
R-0
R/W-2h
14
13
0
Reserved
MOC*
R-0
R/W-5h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; *These bits can be updated in DEFAULT_CONFIG or CONFIG state
only
Table 23-118. GTU Configuration Register 10 (GTUC10) Field Descriptions
Bit
Field
31-27
Reserved
26-16
MRC
15-14
Reserved
13-0
MOC
1198
Value
0
2h-783h µT
0
Description
Reads return 0. Writes have no effect.
Maximum rate correction (in microticks). Holds the maximum permitted rate correction value to be
applied by the internal clock synchronization algorithm. The communication controller checks the
internal rate correction value against the maximum rate correction value (absolute value).
Reads return 0. Writes have no effect.
5h-3BA2h µT Maximum offset correction (in microticks). Holds the maximum permitted offset correction value to
be applied by the internal clock synchronization algorithm (absolute value). The communication
controller checks the internal offset correction value against the maximum offset correction value.
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23.19.2.3.18 GTU Configuration Register 11 (GTUC11)
Figure 23-138 and Table 23-119 illustrate this register.
Figure 23-138. GTU Configuration Register 11 (GTUC11) [offset_CC = C8h]
31
27
26
24
23
19
18
16
Reserved
ERC*
Reserved
EOC*
R-0
R/W-0
R-0
R/W-0
15
10
9
8
7
2
1
0
Reserved
ERCC*
Reserved
EOCC*
R-0
R/W-0
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; *These bits can be updated in DEFAULT_CONFIG or CONFIG state
only
Table 23-119. GTU Configuration Register 11 (GTUC11) Field Descriptions
Bit
Field
31-27
Reserved
26-24
ERC
23-19
Reserved
18-16
EOC
15-10
Reserved
9-8
Value
0
0-7h µT
0
0-7h µT
0
ERCC
Reserved
1-0
EOCC
Reads return 0. Writes have no effect.
External rate correction (in microticks). Holds the external clock rate correction value to be applied
by the internal clock synchronization algorithm. The value is subtracted/added from/to the
calculated rate correction value. The value is applied during NIT. May be modified in
DEFAULT_CONFIG or CONFIG state only.
Reads return 0. Writes have no effect.
External offset correction (in microticks). Holds the external clock offset correction value to be
applied by the internal clock synchronization algorithm. The value is subtracted/added from/to the
calculated offset correction value. The value is applied during NIT. May be modified in
DEFAULT_CONFIG or CONFIG state only.
Reads return 0. Writes have no effect.
External rate correction control. By writing to ERCC, the external rate correction is enabled as
specified below. Should be modified only outside NIT.
0, 1h
7-2
Description
No external rate correction.
2h
External rate correction value is subtracted from calculated rate correction value.
3h
External rate correction value is added to calculated rate correction value.
0
Reads return 0. Writes have no effect.
External offset correction control. By writing to EOCC, the external offset correction is enabled as
specified below. Should be modified only outside NIT.
0, 1h
No external offset correction.
2h
External offset correction value is subtracted from calculated offset correction value.
3h
External offset correction value is added to calculated offset correction value.
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23.19.2.4 Status Registers
During 8/16-bit accesses to status variables coded with more than 8/16-bit, the variable might be updated
by the communication controller between two accesses (non-atomic read accesses). All internal counters
and the communication controller status flags are reset when the communication controller transits from
CONFIG to READY state.
23.19.2.4.1 Communication Controller Status Vector (CCSV)
Figure 23-139 and Table 23-120 illustrate this register.
Figure 23-139. Communication Controller Status Vector Register (CCSV) [offset_CC = 100h]
31
30
29
24
23
19
18
16
Reserved
PSL
RCA
WSV
R-0
R-0
R-2
R-0
15
14
13
12
7
6
Rsvd
CSI
CSAI
CSNI
11
Reserved
10
9
SLM
8
HRQ
FSI
5
POCS
0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 23-120. Communication Controller Status Vector Register (CCSV) Field Descriptions
Bit
Field
31-30
Reserved
29-24
PSL
23-19
RCA
18-16
WSV
15
Reserved
14
CSI
13
1200
CSAI
Value
0
Description
Reads return 0. Writes have no effect.
POC Status Log. Status of POCS immediately before entering HALT state. Set when entering
HALT state. Set to HALT when FREEZE command is applied during HALT state and FSI is not
already set, that is, the HALT state was not reached by FREEZE command. Reset to 0 when
leaving HALT state.
0-1Fh
Remaining coldstart attempts. Indicates the number of remaining coldstart attempts. The maximum
number of coldstart attempts is configured by CSA in the SUC configuration register 1.
Wakeup status. Indicates the status of the current wakeup attempt. Reset by CHI command
RESET_STATUS_INDICATORS or by transition from HALT to EFAULT_CONFIG state.
0
UNDEFINED. No wakeup attempt since CONFIG state was left.
1h
RECEIVED_HEADER. Set when the communication controller finishes wakeup due to the
reception of a frame header without coding violation on either channel in WAKEUP_LISTEN or
WAKEUP_DETECT state.
2h
RECEIVED_WUP. Set when the communication controller finishes wakeup due to the reception of
a valid wakeup pattern on the configured wakeup channel in WAKEUP_LISTEN or
WAKEUP_DETECT state.
3h
COLLISION_HEADER. Set when the communication controller stops wakeup due to a detected
collision during wakeup pattern transmission by receiving a valid header on either channel.
4h
COLLISION_WUP. Set when the communication controller stops wakeup due to a detected
collision during wakeup pattern transmission by receiving a valid wakeup pattern on the configured
wakeup channel.
5h
COLLISION_UNKNOWN. Set when the communication controller stops wakeup by leaving
WAKEUP_DETECT state after expiration of the wakeup timer without receiving a valid wakeup
pattern or a valid frame header.
6h
TRANSMITTED. Set when the communication controller has successfully completed the
transmission of the wakeup pattern.
7h
Reserved
0
Reads return 0. Writes have no effect.
Cold start inhibit. Indicates that the node is disabled from cold starting. The flag is set whenever
the POC enters READY state. The flag has to be reset under control of the host by the controller
host interface command ALLOW_COLDSTART (CMD = 1001).
0
Cold starting of node is enabled.
1
Cold starting of node is disabled.
Coldstart abort indicator. Coldstart aborted. Reset by CHI command
RESET_STATUS_INDICATORS or by transition from HALT to DEFAULT_CONFIG state or from
READY to STARTUP state.
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Table 23-120. Communication Controller Status Vector Register (CCSV) Field Descriptions (continued)
Bit
Field
12
CSNI
11-10
9-8
Reserved
Value
Description
Coldstart noise indicator. Indicates that the cold start procedure occurred under noisy conditions.
Reset by CHI command RESET_STATUS_INDICATORS or by transition from HALT to
DEFAULT_CONFIG state or from READY to STARTUP state.
0
SLM
Reads return 0. Writes have no effect.
Slot mode. Indicates the actual slot mode of the POC in states READY, WAKEUP, STARTUP,
NORMAL_ACTIVE, and NORMAL_PASSIVE. Default is SINGLE. Changes to ALL, depending on
SUCC1.TSM. In NORMAL_ACTIVE or NORMAL_PASSIVE state the CHI command ALL_SLOTS
will change the slot mode from SINGLE over ALL_PENDING to ALL. Set to SINGLE in all other
states.
0
SINGLE
1h
Reserved
2h
ALL_PENDING
3h
ALL
7
HRQ
0-1
Halt request. Indicates that a request from the Host has been received to halt the POC at the end
of the communication cycle. Reset by CHI command RESET_STATUS_INDICATORS or by
transition from HALT to DEFAULT_CONFIG state or when entering READY state.
6
FSI
0-1
Freeze status indicator. Indicates that the POC has entered the HALT state due to CHI command
FREEZE or due to an error condition requiring an immediate POC halt. Reset by CHI command
RESET_STATUS_INDICATORS or by transition from HALT to DEFAULT_CONFIG state.
5-0
POCS
Protocol operation control status.
Indicates the actual state of operation of the Communication Controller Protocol Operation
Control:
0
DEFAULT_CONFIG state
1h
READY state
2h
NORMAL_ACTIVE state
3h
NORMAL_PASSIVE state
4h
HALT state
5h
MONITOR_MODE state
6h-Ch
Reserved
Dh
LOOPBACK MODE state
Eh
Reserved
Fh
CONFIG state
Indicates the actual state of operation of the POC in the wakeup path:
10h
WAKEUP_STANDBY state
11h
WAKEUP_LISTEN state
12h
WAKEUP_SEND state
13h
WAKEUP_DETECT state
14h-1Fh
Reserved
Indicates the actual state of operation of the POC in the startup path:
20h
STARTUP_PREPARE state
21h
COLDSTART_LISTEN state
22h
COLDSTART_COLLISION_RESOLUTION state
23h
COLDSTART_CONSISTENCY_CHECK state
24h
COLDSTART_GAP state
25h
COLDSTART_JOIN state
26h
INTEGRATION_COLDSTART_CHECK state
27h
INTEGRATION_LISTEN state
28h
INTEGRATION_CONSISTENCY_CHECK state
29h
INITIALIZE_SCHEDULE state
2Ah
ABORT_STARTUP state
2Bh-3Fh
Reserved
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NOTE: CHI command RESET_STATUS_INDICATORS (SUCC1.CMD = Ah) resets flags FSI, HRQ,
CSNI, CSAI, the slot mode SLM, and the wakeup status WSV.
23.19.2.4.2 Communication Controller Error Vector (CCEV)
Reset by CHI command RESET_STATUS_INDICATORS or by transition from HALT to
DEFAULT_CONFIG state or when entering READY state.
Figure 23-140 and Table 23-121 illustrate this register.
Figure 23-140. Communication Controller Error Vector Register (CCEV) [offset_CC = 104h]
31
16
Reserved
R-0
15
13
12
8
7
6
5
4
3
0
Reserved
PTAC
ERRM
Reserved
CCFC
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 23-121. Communication Controller Error Vector Register (CCEV) Field Descriptions
Bit
Field
31-13
Reserved
12-8
PTAC
7-6
ERRM
5-4
Reserved
3-0
CCFC
1202
Value
0
0-1Fh
Description
Reads return 0. Writes have no effect.
Passive to active count. Indicates the number of consecutive even / odd cycle pairs that have passed
with valid rate and offset correction terms, while the node is waiting to transit from NORMAL_PASSIVE
state to NORMAL_ACTIVE state. The transition takes place when PTAC equals PTA - 1 as defined in
the SUC configuration register 1.
Error mode. Indicates the actual error mode of the POC.
0
ACTIVE
1h
PASSIVE
2h
COMM_HALT
3h
Reserved
0
Reads return 0. Writes have no effect.
0-Fh
Clock correction failed counter. The clock correction failed counter is incremented by one at the end of
any odd communication cycle where either the missing offset correction error or missing rate correction
error are active. The clock correction failed counter is reset to 0 at the end of an odd communication
cycle if neither the offset correction failed nor the rate correction failed errors are active. The clock
correction failed counter stops at 15.
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23.19.2.4.3 Slot Counter Value (SCV)
This register is reset when the Communication Controller leaves CONFIG state or enters STARTUP state.
Figure 23-141 and Table 23-122 illustrate this register.
Figure 23-141. Slot Counter Vector Register (SCV) [offset_CC = 110h]
31
27
26
16
Reserved
SCCB
R-0
R-0
15
11
10
0
Reserved
SCCA
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 23-122. Slot Counter Vector Register (SCV) Field Descriptions
Bit
Field
31-27
Reserved
26-16
SCCB
15-11
Reserved
10-0
SCCA
Value
0
1h-7FFh
0
1h-7FFh
Description
Reads return 0. Writes have no effect.
Slot counter channel B. Current slot counter value channel B. The value is incremented by the
communication controller and reset at the start of a communication cycle.
Reads return 0. Writes have no effect.
Slot counter channel A. Current slot counter value channel A. The value is incremented by the
communication controller and reset at the start of a communication cycle.
23.19.2.4.4 Macrotick and Cycle Counter Value (MTCCV)
Figure 23-142 and Table 23-123 illustrate this register.
Figure 23-142. Macrotick and Cycle Counter Register (MTCCV) [offset_CC = 114h]
31
22
15
14
21
16
Reserved
CCV
R-0
R-0
13
0
Reserved
MTV
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 23-123. Macrotick and Cycle Counter Register (MTCCV) Field Descriptions
Bit
Field
31-22
Reserved
21-16
CCV
15-14
Reserved
13-0
MTV
Value
0
0-3Fh
0
0-3E80h
Description
Reads return 0. Writes have no effect.
Cycle counter value. Current cycle counter value. The value is incremented by the communication
controller at the start of a communication cycle.
Reads return 0. Writes have no effect.
Macrotick value. Current macrotick value. The value is incremented by the communication
controller and reset at the start of a communication cycle.
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23.19.2.4.5 Rate Correction Value (RCV)
This register is reset when the Communication Controller leaves CONFIG state or enters STARTUP state.
Figure 23-143 and Table 23-124 illustrate this register.
Figure 23-143. Rate Correction Value Register (RCV) [offset_CC = 118h]
31
16
Reserved
R-0
15
12
11
0
Reserved
RCV
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 23-124. Rate Correction Value Register (RCV) Field Descriptions
Bit
Field
31-12
Reserved
11-0
RCV
Value
0
Description
Reads return 0. Writes have no effect.
Rate correction value (in microticks). Rate correction value (two's complement). Calculated internal rate
correction value before limitation. If the RCV value exceeds the limits defined by GTUC10.MRC, flag
SFS.RCLR is set to 1.
NOTE: The external rate correction value is added to the limited rate correction value.
23.19.2.4.6 Offset Correction Value (OCV)
Figure 23-144 and Table 23-125 illustrate this register.
Figure 23-144. Offset Correction Value Register (OCV) [offset_CC = 11Ch]
31
20
19
16
Reserved
OCV
R-0
R-0
15
0
OCV
R-0
LEGEND: R = Read only; -n = value after reset
Table 23-125. Offset Correction Value Register (OCV) Field Descriptions
Bit
Field
31-20
Reserved
19-0
OCV
Value
0
Description
Reads return 0. Writes have no effect.
Offset correction value (in microticks). Offset correction value (two's complement). Calculated internal
offset correction value before limitation. If the OCV value exceeds the limits defined by GTUC10.MOC,
flag SFS.OCLR is set to 1.
NOTE: The external offset correction value is added to the limited offset correction value.
1204
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23.19.2.4.7 Sync Frame Status (SFS)
This register is reset when the Communication Controller leaves CONFIG state or enters STARTUP state.
Figure 23-145 and Table 23-126 illustrate this register.
Figure 23-145. Sync Frame Status Register (SFS) [offset_CC = 120h]
31
20
15
12
19
18
17
16
Reserved
RCLR
MRCS
OCLR
MOCS
R-0
R-0
R-0
R-0
R-0
11
8
7
4
3
0
VSBO
VSBE
VSAO
VSAE
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 23-126. Sync Frame Status Register (SFS) Field Descriptions
Bit
31-20
19
18
17
16
Field
Reserved
Value
0
RCLR
Description
Reads return 0. Writes have no effect.
Rate correction limit reached. The Rate Correction Limit Reached flag signals to the Host, that the rate
correction value has exceeded its limit as defined by GTUC10.MRC. The flag is updated by the
communication controller at start of offset correction phase.
0
Rate correction limit is below limit.
1
Rate correction limit is reached.
MRCS
Missing rate correction signal. The missing rate correction signal signals to the host that no rate
correction can be performed because no pairs of even/odd sync frames were received. The flag is
updated by the communication controller at start of offset correction phase.
0
Rate correction signal is valid.
1
Missing rate correction signal.
OCLR
Offset correction limit reached. The offset correction limit reached flag signals to the host that the offset
correction value has reached its limit as defined by GTUC10.MOC. The flag is updated by the
communication controller at start of offset correction phase.
0
Offset correction limit is below limit.
1
Offset correction limit is reached.
MOCS
Missing offset correction signal. The missing offset correction signal signals to the host that no rate
correction can be performed because no pairs of even / odd sync frames were received. The flag is
updated by the communication controller at start of offset correction phase.
0
Offset correction signal is valid.
1
Missing offset correction signal.
15-12
VSBO
0-Fh
Valid sync frames channel B, odd communication cycle. Holds the number of valid sync frames
received on channel B in the odd communication cycle. If transmission of sync frames is enabled by
SUCC1.TXSY the value is incremented by one. The value is updated during the NIT of each odd
communication cycle.
11-8
VSBE
0-Fh
Valid synch frames channel B, even communication cycle. Holds the number of valid sync frames
received and transmitted on channel B in the even communication cycle. If transmission of sync frames
is enabled by SUCC1.TXSY the value is incremented by one. The value is updated during the NIT of
each even communication cycle.
7-4
VSAO
0-Fh
Valid synch frames channel A, odd communication cycle. Holds the number of valid sync frames
received and transmitted on channel A in the odd communication cycle. If transmission of sync frames
is enabled by SUCC1.TXSY the value is incremented by one. The value is updated during the NIT of
each odd communication cycle.
3-0
VSAE
0-Fh
Valid synch frames channel A, even communication cycle. Holds the number of valid sync frames
received and transmitted on channel A in the even communication cycle. If transmission of sync frames
is enabled by SUCC1.TXSY the value is incremented by one. The value is updated during the NIT of
each even communication cycle.
NOTE: The bit fields VSBO, VSBE, VSAO, VSAE are only valid if the respective channel is
assigned to the communication controller by SUCC1.CCHA or SUCC1.CCHB.
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23.19.2.4.8 Symbol Window and NIT Status (SWNIT)
Symbol window related status information. Updated by the communication controller at the end of the
symbol window for each channel. During startup the status data is not updated. This register is reset when
the Communication Controller leaves CONFIG state or enters STARTUP state.
Figure 23-146 and Table 23-127 illustrate this register.
Figure 23-146. Symbol Window and NIT Status Register (SWNIT) [offset_CC = 124h]
31
16
Reserved
R-0
15
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
12
SBNB
SENB
SBNA
SENA
MTSB
MTSA
TCSB
SBSB
SESB
TCSA
SBSA
SESA
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 23-127. Symbol Window and NIT Status Register (SWNIT) Field Descriptions
Bit
31-12
11
10
9
8
7
6
5
4
3
1206
Field
Reserved
Value
0
SBNB
Description
Reads return 0. Writes have no effect.
Slot boundary violation during NIT channel B.
0
No slot boundary violation is detected.
1
Slot boundary violation during NIT is detected on channel B.
SENB
Syntax error during NIT channel B.
0
No syntax error is detected.
1
Syntax error during NIT is detected on channel B.
SBNA
Slot boundary violation during NIT channel A.
0
No slot boundary violation is detected.
1
Slot boundary violation during NIT is detected on channel A.
SENA
Syntax error during NIT channel A.
0
No syntax error is detected.
1
Syntax error during NIT is detected on channel A.
MTSB
MTS Received on Channel B. Media Access Test symbol received on channel B during the last symbol
window. Updated by the communication controller for each channel at the end of the symbol window.
When this bit is set to 1, also interrupt flag SIR.MTSB is set to 1.
0
No MTS symbol is received on channel B.
1
MTS symbol is received on channel B.
MTSA
MTS Received on Channel A. Media Access Test symbol received on channel A during the last symbol
window. Updated by the communication controller for each channel at the end of the symbol window.
When this bit is set to 1, also interrupt flag SIR.MTSB is set to 1.
0
No MTS symbol is received on channel A.
1
MTS symbol is received on channel A.
TCSB
Transmission conflict in symbol window channel B.
0
No transmission conflict is detected.
1
Transmission conflict in symbol window is detected on channel B.
SBSB
Slot boundary violation in symbol window channel B.
0
No slot boundary violation is detected.
1
Slot boundary violation during symbol window is detected on channel B.
SESB
Syntax error in symbol window channel B.
0
No syntax error is detected.
1
Syntax error during symbol window is detected on channel B.
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Table 23-127. Symbol Window and NIT Status Register (SWNIT) Field Descriptions (continued)
Bit
Field
2
TCSA
1
0
Value
Description
Transmission conflict in symbol window channel A.
0
No transmission conflict is detected.
1
Transmission conflict in symbol window is detected on channel A.
SBSA
Slot boundary violation in symbol window channel A.
0
No slot boundary violation is detected.
1
Slot boundary violation during symbol window is detected on channel A.
SESA
Syntax error in symbol window channel A.
0
No syntax error is detected.
1
Syntax error during symbol window is detected on channel A.
23.19.2.4.9 Aggregated Channel Status (ACS)
The aggregated channel status provides the host with an accrued status of channel activity for all
communication slots regardless of whether they are assigned for transmission or subscribed for reception.
The aggregated channel status also includes status data from the symbol phase and the network idle
time. The status data is updated (set) after each slot and aggregated until it is reset by the host. During
startup the status data is not updated. A flag is cleared by writing a 1 to the corresponding bit position.
Writing a 0 has no effect on the flag. This register is reset when the Communication Controller leaves
CONFIG state or enters STARTUP state.
Figure 23-147 and Table 23-128 illustrate this register.
Figure 23-147. Aggregated Channel Status Register (ACS) [offset_CC = 128h]
31
16
Reserved
R-0
15
12
11
10
9
8
4
3
2
1
0
Reserved
13
SBVB
CIB
CEDB
SEDB
VFRB
7
Reserved
5
SBVA
CIA
CEDA
SEDA
VFRA
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23-128. Aggregated Channel Status Register (ACS) Field Descriptions
Bit
31-13
12
11
10
Field
Reserved
Value
0
SBVB
Description
Reads return 0. Writes have no effect.
Slot boundary violation on channel B. One or more slot boundary violations were observed on channel
B at any time during the observation period (static or dynamic slots including symbol window and NIT).
0
No slot boundary violation is observed.
1
Slot boundary violation(s) is observed on channel B.
CIB
Communication indicator channel B. One or more valid frames were received on channel B in slots that
also contained any additional communication during the observation period, that is, one or more slots
received a valid frame AND had any combination of either syntax error OR content error OR slot
boundary violation.
0
No valid frame(s) is received in slots containing any additional communication.
1
Valid frame(s) is received on channel B in slots containing any additional communication.
CEDB
Content error detected on channel B. One or more frames with a content error were received on
channel B in any static or dynamic slot during the observation period.
0
No frame with content error is received.
1
Frame(s) with content error is received on channel B.
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Table 23-128. Aggregated Channel Status Register (ACS) Field Descriptions (continued)
Bit
Field
9
SEDB
8
7-5
4
3
2
1
0
1208
Value
Syntax error detected on channel B. One or more syntax errors in static or dynamic slots including
symbol window and NIT were observed on channel B.
0
No syntax error is observed.
1
Syntax error(s) is observed on channel B.
VFRB
Reserved
Description
Valid frame received on channel B. One or more valid frames were received on channel B in any static
or dynamic slot during the observation period. Reset is under control of the host.
0
No valid frame is received.
1
Valid frame(s) is received on channel B.
0
Reads return 0. Writes have no effect.
SBVA
Slot boundary violation on channel A. One or more slot boundary violations were observed on channel
A at any time during the observation period (static or dynamic slots including symbol window and NIT).
0
No slot boundary violation is observed.
1
Slot boundary violation(s) is observed on channel A.
CIA
Communication indicator channel A. One or more valid frames were received on channel A in slots that
also contained any additional communication during the observation period, that is, one or more slots
received a valid frame AND had any combination of either syntax error OR content error OR slot
boundary violation.
0
No valid frame(s) is received in slots containing any additional communication.
1
Valid frame(s) is received on channel A in slots containing any additional communication.
CEDA
Content error detected on channel A. One or more frames with a content error were received on
channel A in any static or dynamic slot during the observation period.
0
No frame with content error is received.
1
Frame(s) with content error is received on channel A.
SEDA
Syntax error detected on channel A. One or more syntax errors in static or dynamic slots including
symbol window and NIT were observed on channel A.
0
No syntax error is observed.
1
Syntax error(s) is observed on channel A.
VFRA
Valid frame received on channel A. One or more valid frames were received on channel A in any static
or dynamic slot during the observation period.
0
No valid frame is received.
1
Valid frame(s) is received on channel A.
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23.19.2.4.10 Even Sync ID Registers (ESID[1-15])
Registers ESID1 to ESID15 hold the frame IDs of the sync frames received in even communication
cycles, assorted in ascending order, with register ESID1 holding the lowest received sync frame ID. If the
node transmits a sync frame in an even communication cycle by itself, register ESID1 holds the respective
sync frame ID as configured in message buffer 0. The value is updated during the NIT of each even
communication cycle. This register is reset when the Communication Controller leaves CONFIG state or
enters STARTUP state.
Figure 23-148 and Table 23-129 illustrate this register.
Figure 23-148. Even Sync ID Registers (ESIDn) [offset_CC = 130h-168h]
31
16
Reserved
R-0
15
14
RXEB
RXEA
13
Reserved
10
9
EID
0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 23-129. Even Sync ID Registers (ESIDn) Field Descriptions
Bit
31-16
15
14
13-10
9-0
Field
Reserved
Value
0
RXEB
Reads return 0. Writes have no effect.
Received even sync ID on channel B. A sync frame corresponding to the stored even sync ID was
received on channel B.
0
Sync frame is not received on channel B.
1
Sync frame is received on channel B.
RXEA
Reserved
Description
Received even sync ID on channel A. A sync frame corresponding to the stored even sync ID was
received on channel A.
0
Sync frame is not received on channel A.
1
Sync frame is received on channel A.
0
Reads return 0. Writes have no effect.
EID
Even Sync ID. Sync frame ID even communication cycle.
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23.19.2.4.11 Odd Sync ID Registers (OSID[1-15])
Registers OSID1 to OSID15 hold the frame IDs of the sync frames received in odd communication cycles,
assorted in ascending order, with register OSID1 holding the lowest received sync frame ID. If the node
transmits a sync frame in an odd communication cycle by itself, register OSID1 holds the respective sync
frame ID as configured in message buffer 0. The value is updated during the NIT of each odd
communication cycle. This register is reset when the Communication Controller leaves CONFIG state or
enters STARTUP state.
Figure 23-149 and Table 23-130 illustrate this register.
Figure 23-149. Odd Sync ID Registers (OSIDn) [offset_CC = 170h-1A8h]
31
16
Reserved
R-0
15
14
RXOB
RXOA
13
Reserved
10
9
OID
0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 23-130. Odd Sync ID Registers (OSIDn) Field Descriptions
Bit
31-16
15
14
13-10
9-0
1210
Field
Reserved
Value
0
RXOB
OID
Reads return 0. Writes have no effect.
Received odd sync ID on channel B. A sync frame corresponding to the stored even sync ID was
received on channel B.
0
Sync frame is not received on channel B.
1
Sync frame is received on channel B.
RXOA
Reserved
Description
Received odd sync ID on channel A. A sync frame corresponding to the stored even sync ID was
received on channel A.
0
Sync frame is not received on channel A.
1
Sync frame is received on channel A.
0
Reads return 0. Writes have no effect.
Odd Sync ID. Sync frame ID odd communication cycle.
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23.19.2.4.12 Network Management Vector Registers (NMV[1-3])
The three network management registers hold the accrued NM vector (configurable 0-12 bytes). The
accrued NM vector is generated by the communication controller by bit-wise ORing each NM vector
received (valid frames with PPI = 1) on each channel.
The communication controller updates the NM vector at the end of each communication cycle as long as
the communication controller is either in NORMAL_ACTIVE or NORMAL_PASSIVE state.
NMVn-bytes exceeding the configured NM vector length are not valid.
Figure 23-150 illustrates these registers and Table 23-131 shows the assignment of the data bytes to the
network management vector.
Figure 23-150. Network Management Registers (NMVn) [offset_CC = 1B0h-1B8h]
31
16
NMI
R-0
15
0
NMI
R-0
LEGEND: R = Read only; -n = value after reset
Table 23-131. Assignment of Data Bytes to Network Management Vector
Bit
Word
NMV1
31
24
Data3
23
16
15
8
7
0
Data2
Data1
Data0
NMV2
Data7
Data6
Data5
Data4
NMV3
Data11
Data10
Data9
Data8
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23.19.2.5 Message Buffer Control Registers
23.19.2.5.1 Message RAM Configuration (MRC)
The message RAM Configuration register defines the number of message buffers assigned to the static
segment, dynamic segment, and FIFO. The register can be written during DEFAULT_CONFIG or CONFIG
state only.
Figure 23-151 and Table 23-132 illustrate this register.
Figure 23-151. Message RAM Configuration Register (MRC) [offset_CC = 300h]
31
27
26
25
24
23
16
Reserved
SPLM*
SEC*
LCB*
R-0
R-1
R-0
R/W-80h
15
8
7
0
FFB*
FDB*
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; *These bits can be updated in DEFAULT_CONFIG or CONFIG state
only
Table 23-132. Message RAM Configuration Register (MRC) Field Descriptions
Bit
31-27
26
25-24
23-16
15-8
Field
Reserved
Value
0
SPLM
0
Only message buffer 0 is locked against reconfiguration.
1
Both message buffers 0 and 1 are locked against reconfiguration.
SEC
Secure Buffers. Not evaluated when the communication controller is in DEFAULT_CONFIG or
CONFIG state.
0
Reconfiguration of message buffers enabled with numbers < FFBh enabled
Exception: In nodes configured for sync frame transmission or for single slot mode operation
message buffer 0 (and if SPLM = 1, also message buffer 1) is always locked
1h
Reconfiguration of message buffers with numbers < FDB and with numbers FFB locked and
transmission of message buffers for static segment with numbers FDB are disabled.
2h
Reconfiguration of all message buffers is locked.
3h
Reconfiguration of all message buffers locked and transmission of message buffers for static
segment with numbers FDB are disabled.
LCB
Last configured buffer.
0-7Fh
Number of message buffers is LCB + 1.
≥ 80h
No message buffer is configured.
FFB
First buffer of FIFO.
All message buffers are assigned to the FIFO.
0-7Fh
Message buffers from FFB to LCB are assigned to the FIFO.
≥ 80h
No message buffer is assigned to the FIFO.
FDB
First dynamic buffer.
0
1212
Reads return 0. Writes have no effect.
Sync Frame Payload Multiplex. This bit is only evaluated if the node is configured as sync node
(SUCC1.TXSY = 1) or for single slot mode operation (SUCC1.TSM = 1). When this bit is set to 1
message buffers 0 and 1 are dedicated for sync frame transmission with different payload data on
channel A and B. When this bit is set to 0, sync frames are transmitted from message buffer 0 with
the same payload data on both channels. Note that the channel filter configuration for message
buffer 0 resp. message buffer 1 has to be chosen accordingly.
0
7-0
Description
No group of pure static buffers are configured.
0-7Fh
Message buffers 0 to FDB - 1 are reserved for static segment.
≥ 80h
No dynamic buffers are configured.
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NOTE: In case the node is configured as sync node (SUCC1.TXSY = 1) or for single slot mode
operation (SUCC1.TSM = 1), message buffer 0 resp. 1 is reserved for sync frames or single
slot frames and have to be configured with the node-specific key slot ID. In case the node is
neither configured as sync node nor for single slot operation, message buffer 0 resp. 1 is
treated like all other message buffers.
Table 23-133. Buffer Configuration
Message Buffer 0
↓ Static Buffers
Message Buffer 1
...
↓ Static + Dynamic Buffers
← FDB
↓ FIFO
← FFB
FIFO configured: FBB > FDB
No FIFO configured: FFB
≥ 128
← LCB
LCB ≥ FDB,
LCB ≥ FFB
Message Buffer N-1
Message Buffer N
The programmer must ensure that the configuration defined by FDB, FFB, and LCB is valid.
NOTE: The communication controller does not check for erroneous configurations.
NOTE: Maximum Number of Header Sections
The maximum number of header sections is 128. This means a maximum of 128 message
buffers can be configured. The maximum length of the data sections is 254 bytes. The length
of the data section may be configured different for each message buffer. In case two or more
message buffers are assigned to slot 1 by use of cycle filtering, all of them must be located
either in the "Static Buffers" or at the beginning of the "Static + Dynamic Buffers" section.
The FlexRay protocol specification requires that each node has to send a frame in its key
slot. Therefore at least message buffer 0 is reserved for transmission in the key slot. Due to
this requirement a maximum number of 127 message buffers can be assigned to the FIFO.
Nevertheless, a non protocol conform configuration without a transmission slot in the static
segment would still be operational. The payload length configured and the length of the data
sections need to be configured identical for all message buffers belonging to the FIFO via
WRHS2.PLC and WRHS3.DP. When the communication controller is not in
DEFAULT_CONFIG or CONFIG state reconfiguration of message buffers belonging to the
FIFO is locked.
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23.19.2.5.2 FIFO Rejection Filter (FRF)
The FIFO rejection filter defines a user specified sequence of bits with which channel, frame ID, and cycle
count of the incoming frames are compared. Together with the FIFO rejection filter mask (FRFM), this
register determines whether a message is rejected by the FIFO. The FRF register can be written during
DEFAULT_CONFIG or CONFIG state only.
Figure 23-152 and Table 23-134 illustrate this register.
Figure 23-152. FIFO Rejection Filter Register (FRF) [offset_CC = 304h]
31
25
15
13
24
23
Reserved
RNF*
RSS*
22
CYF*
R-0
R-1
R-1
R/W-0
12
16
2
1
0
Reserved
FID*
CH*
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; *These bits can be updated in DEFAULT_CONFIG or CONFIG state
only
Table 23-134. FIFO Rejection Filter Register (FRF) Field Descriptions
Bit
31-25
24
23
Field
Reserved
Value
0
RNF
CYF
15-13
Reserved
12-2
FID
1-0
CH
Reads return 0. Writes have no effect.
Reject null frames. If this bit is set, received null frames are not stored in the FIFO.
0
Null frames are stored in the FIFO.
1
Reject all null frames.
RSS
22-16
Description
Reject in static segment. If this bit is set, the FIFO is used only for the dynamic segment.
0
FIFO also used in static segment.
1
Reject messages in static segment.
Cycle counter filter. The 7-bit cycle counter filter determines the cycle set to which the frame ID
FIFO rejection filter and the channel FIFO rejection filter are applied. In cycles not belonging to the
cycle set specified by CYF, all frames are rejected. For details about the configuration of the cycle
counter filter.
0
0-7FFh
Reads return 0. Writes have no effect.
Frame ID filter. A frame ID filter value of zero means that no frame ID is rejected.
Channel filter.
Note: If reception on both channels is configured, also in the static segment both frames (from
channel A and B) are always stored in the FIFO, even if they are identical.
1214
0
Receive on both channels.
1h
Receive only on channel B.
2h
Receive only on channel A.
3h
No reception.
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23.19.2.5.3 FIFO Rejection Filter Mask (FRFM)
The FIFO rejection filter mask specifies which of the corresponding frame ID filter bits are relevant for
rejection filtering. If a bit is set, it indicates that the state of the corresponding bit in the FRF register will
not be considered for rejection filtering. The FRFM register can be written during DEFAULT_CONFIG or
CONFIG state only.
Figure 23-153 and Table 23-135 illustrate this register.
Figure 23-153. FIFO Rejection Filter Mask Register (FRFM) [offset_CC = 308h]
31
16
Reserved
R-0
15
13
12
2
1
0
Reserved
MFID*
Reserved
R-0
R/W-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; *These bits can be updated in DEFAULT_CONFIG or CONFIG state
only
Table 23-135. FIFO Rejection Filter Mask Register (FRFM) Field Descriptions
Bit
Field
31-13
Reserved
12-2
MFID
1-0
Reserved
Value
0
Description
Reads return 0. Writes have no effect.
Mask Frame ID Filter
0
Corresponding frame ID filter bit is used for rejection filtering.
1
Ignore corresponding frame ID filter bit.
0
Reads return 0. Writes have no effect.
23.19.2.5.4 FIFO Critical Level (FCL)
The communication controller accepts modifications of the register in DEFAULT_CONFIG or CONFIG
state only.
Figure 23-154 and Table 23-136 illustrate this register.
Figure 23-154. FIFO Critical Level Register (FCL) [offset_CC = 30Ch]
31
16
Reserved
R-0
15
8
7
0
Reserved
CL*
R-0
R/W-81h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; *These bits can be updated in DEFAULT_CONFIG or CONFIG state
only
Table 23-136. FIFO Critical Level Register (FCL) Field Descriptions
Bit
Field
31-8
Reserved
7-0
CL
Value
0
Description
Reads return 0. Writes have no effect.
Critical Level. When the receive FIFO fill level FSR.RFFL is equal or greater than the critical level
configured by CL, the receive FIFO critical level flag FSR.RFCL is set. If CL is programmed to values
greater than 128, bit FSR.RFCL is never set. When FSR.RFCL changes from 0 to 1, bit SIR.RFCL is
set to 1, and if enabled, an interrupt is generated.
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23.19.2.6 Message Buffer Status Registers
23.19.2.6.1 Message Handler Status (MHDS)
A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect on the flag. A
hardware reset will also clear the register.
Figure 23-155 and Table 23-137 illustrate this register.
Figure 23-155. Message Handler Status (MHDS) [offset_CC = 310h]
31
30
24
23
22
16
Rsvd
MBU
Rsvd
MBT
R-0
R-0
R-0
R-0
15
14
8
Rsvd
FMB
R-0
R-0
7
6
CRAM MFMB
R-1
R/W-0
5
4
3
FMBD PTFB2 PTFB1
R/W-0
R/W-0
R/W-0
2
1
0
PMR
POBF
PIBF
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23-137. Message Handler Status (MHDS) Field Descriptions
Bit
Field
31
Reserved
30-24
MBU
Value
0
0-7Fh
Description
Reads return 0. Writes have no effect.
Message buffer updated. Number of the message buffer that was updated last by the
communication controller. For this message buffer, the respective ND and/or MBC flag in the new
data register (NDAT[1-4]) and the message buffer status changed register (MBSC[1-4]) are also
set.
Note: MBU are reset when the communication controller leaves CONFIG state or enters
STARTUP state.
23
22-16
Reserved
MBT
0
0-7Fh
Reads return 0. Writes have no effect.
Message buffer transmitted. Number of the last successfully transmitted message buffer. If the
message buffer is configured for single-shot mode, the respective TXR flag in the Transmission
request register (TXRQ[1-4]) was reset.
Note: MBT are reset when the communication controller leaves CONFIG state or enters
STARTUP state.
15
14-8
7
6
5
4
3
1216
Reserved
FMB
0
0-7Fh
CRAM
Reads return 0. Writes have no effect.
Faulty message buffer. A parity error occurred when reading from a message buffer or when
transferring data from Input Buffer or Transient Buffer 1,2 to the message buffer referenced by
FMB(6-0). This value is only valid when one of the flags PIBF, PMR, PTBF1, PTBF2, and flag
FMBD is set. Is not updated while flag FMBD is set.
Clear all internal RAMs. Signals that execution of the controller host interface command
CLEAR_RAMS is ongoing (all bits of all internal RAM blocks are written to 0). The bit is set by
hardware reset or by the controller host interface command CLEAR_RAMS.
0
No execution of the controller host interface command CLEAR_RAMS.
1
Execution of the controller host interface command CLEAR_RAMS is ongoing.
MFMB
Multiple faulty message buffers detected.
0
No additional faulty message buffer.
1
Another faulty message buffer was detected while flag FMBD is set.
FMBD
Faulty message buffer detected.
0
No faulty message buffer.
1
Message buffer referenced by FMB(6-0) holds faulty data due to a parity error.
PTBF2
Parity error transient buffer RAM B.
0
No parity error.
1
Parity error occurred when reading transient buffer RAM B.
PTBF1
Parity error transient buffer RAM A.
0
No parity error.
1
Parity error occurred when reading transient buffer RAM A.
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Table 23-137. Message Handler Status (MHDS) Field Descriptions (continued)
Bit
Field
2
PMR
1
0
Value
Description
Parity error message RAM.
0
No parity error.
1
Parity error occurred when reading message RAM.
POBF
Parity error output buffer RAM 1, 2.
0
No parity error.
1
Parity error occurred when message handler read output buffer RAM 1,2.
PIBF
Parity error input buffer RAM 1, 2.
0
No parity error.
1
Parity error occurred when message handler read input buffer RAM 1,2.
NOTE: When one of the flags PIBF, POBF, PMR, PTBF1, PTBF2 changes from 0 to 1, the PERR
flag in the Error Interrupt Register (EIR) is set to 1.
23.19.2.6.2 Last Dynamic Transmit Slot (LDTS)
The register is reset when the communication controller leaves CONFIG state or enters STARTUP state
Figure 23-156 and Table 23-138 illustrate this register.
Figure 23-156. Last Dynamic Transmit Slot (LDTS) [offset_CC = 314h]
31
27
26
16
Reserved
LDTB
R-0
R-0
15
11
10
0
Reserved
LDTA
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 23-138. Last Dynamic Transmit Slot (LDTS) Field Descriptions
Bit
Field
31-27
Reserved
26-16
LDTB
15-11
Reserved
10-0
LDTA
Value
0
Description
Reads return 0. Writes have no effect.
Last Dynamic Transmission Channel B. Value of Slot Counter B at the time of the last frame
transmission on channel A in the dynamic segment of this node. It is updated at the end of the dynamic
segment and is reset to 0, if no frame was transmitted during the dynamic segment.
0
Reads return 0. Writes have no effect.
Last Dynamic Transmission Channel A. Value of Slot Counter A at the time of the last frame
transmission on channel A in the dynamic segment of this node. It is updated at the end of the dynamic
segment and is reset to 0, if no frame was transmitted during the dynamic segment.
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23.19.2.6.3 FIFO Status Register (FSR)
The register is reset when the communication controller leaves CONFIG state, enters STARTUP state, or
by CHI command CLEAR_RAMS..
Figure 23-157 and Table 23-139 illustrate this register.
Figure 23-157. FIFO Status Register (FSR) [offset_CC = 318h]
31
16
Reserved
R-0
15
2
1
0
RFFL
8
7
Reserved
3
RFO
RFCL
RFNE
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 23-139. FIFO Status Register (FSR) Field Descriptions
Bit
Field
31-16
Reserved
15-8
RFFL
7-3
Reserved
2
1
0
1218
Value
0
0-7Fh
0
RFO
Description
Reads return 0. Writes have no effect.
Receive FIFO Fill Level. Number of FIFO buffers filled with new data not yet read by the Host.
Reads return 0. Writes have no effect.
Receive FIFO Overrun. The flag is set by the communication controller when a receive FIFO
overrun is detected. When a receive FIFO overrun occurs, the oldest message is overwritten with
the actual received message. In addition, interrupt flag RFO in the Error Interrupt Register (EIR) is
set. The flag is cleared by the next FIFO read access issued by the Host.
0
No receive FIFO overrun is detected.
1
A receive FIFO overrun has been detected.
RFCL
Receive FIFO Critical Level. This flag is set when the receive FIFO fill level RFFL is equal or
greater than the critical level as configured by CL in the FIFO Critical Level register (FCL). The flag
is cleared by the communication controller as soon as RFFL drops below FCL.CL. When RFCL
changes from 0 to 1, the RFCL flag in the Status Interrupt register (SIR) is set to 1, and if enabled,
an interrupt is generated.
0
Receive FIFO is below critical level.
1
Receive FIFO critical level is reached.
RFNE
Receive FIFO Not Empty. This flag is set by the communication controller when a received valid
frame (data or null frame depending on rejection mask) was stored in the FIFO. In addition,
interrupt flag RFNE in the Status Interrupt register (SR) is set. The bit is reset after the Host has
read all message from the FIFO.
0
Receive FIFO is empty.
1
Receive FIFO is not empty.
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23.19.2.6.4 Message Handler Constraints Flags (MHDF)
Some constraints exist for the Message Handler regarding VBUSclk frequency, Message RAM
configuration, and FlexRay bus traffic. In order to simplify software development, constraints violations are
reported by setting flags in the MHDF.
A flag is cleared by writing a 1 to the corresponding bit position. Writing 0 has no effect on the flag. A
hardware reset will also clear the register. The register is reset when the communication controller leaves
CONFIG state, enters STARTUP state, or by CHI command CLEAR_RAMS.
Figure 23-158 and Table 23-140 illustrate this register.
Figure 23-158. Message Handler Constraints Flags (MHDF) [offset_CC = 31Ch]
31
16
Reserved
R-0
15
8
7
6
5
4
3
2
1
0
Reserved
9
WAHP
TNSA
TNSB
TBFB
TBFA
FNFB
FNFA
SNUB
SNUA
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23-140. Message Handler Constraint Flags (MHDF) Field Descriptions
Bit
31-9
8
7
6
5
4
3
2
Field
Reserved
Value
0
WAHP
Description
Reads return 0. Writes have no effect.
Write attempt to header partition. This flag is set by the communication controller when the message
handler tries to write message data into the header partition of the Message RAM due to faulty
configuration of a message buffer. The write attempt is not executed, to protect the header partition
from unintended write accesses.
0
No write attempt to header partition.
1
Write attempt to header partition.
TNSA
Transmission Not Started Channel A. This flag is set by the CC when the Message Handler was not
ready to start a scheduled transmission on channel A at the action point of the configured slot.
0
No transmission is not started on channel A.
1
Transmission is not started on channel A.
TNSB
Transmission Not Started Channel B. This flag is set by the CC when the Message Handler was not
ready to start a scheduled transmission on channel B at the action point of the configured slot.
0
No transmission is not started on channel B.
1
Transmission is not started on channel B.
TBFB
Transient buffer access failure B. This flag is set by the communication controller when a read or write
access to TBF B requested by PRT B could not complete within the available time.
0
No TBF B access failure.
1
TBF B access failure.
TBFA
Transient buffer access failure A. This flag is set by the communication controller when a read or write
access to TBF A requested by PRT A could not complete within the available time.
0
No TBF A access failure.
1
TBF A access failure.
FNFB
Find sequence not finished channel B. This flag is set by the communication controller when the
Message Handler, due to overload condition, was not able to finish a find sequence (scan of Message
RAM for matching message buffer) with respect to channel B.
0
No find sequence is not finished for channel B.
1
Find sequence is not finished for channel B.
FNFA
Find sequence not finished channel A. This flag is set by the communication controller when the
Message Handler, due to overload condition, was not able to finish a find sequence (scan of Message
RAM for matching message buffer) with respect to channel A.
0
No find sequence is not finished for channel A.
1
Find sequence is not finished for channel A.
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Table 23-140. Message Handler Constraint Flags (MHDF) Field Descriptions (continued)
Bit
Field
1
SNUB
0
Value
Description
Status not updated channel B. This flag is set by the communication controller when the Message
Handler, due to overload condition, was not able to update a message buffer's status MBS with respect
to channel B.
0
No overload condition occurred when updating MBS for channel B.
1
MBS for channel B is not updated.
SNUA
Status not updated channel A. This flag is set by the communication controller when the Message
Handler, due to overload condition, was not able to update a message buffer's status MBS with respect
to channel A.
0
No overload condition occurred when updating MBS for channel A.
1
MBS for channel A is not updated.
NOTE: When one of the flags SNUA, SNUB, FNFA, FNFB, TBFA, TBFB, WAHP changes from 0 to
1, interrupt flag MHF in the Error Interrupt Register (EIR) is set to 1.
1220
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23.19.2.6.5 Transmission Request Registers (TXRQ[1-4])
These four registers reflect the state of the TXR flags of all configured message buffers. The flags are
evaluated for transmit buffers only. If the number of configured message buffers is less than 128, the
remaining TXR flags have no meaning.
Figure 23-162 through Figure 23-159 and Table 23-141 illustrate these registers.
Figure 23-159. Transmission Request Register 1 (TXRQ1) [offset_CC = 320h]
31
16
TXR[31:16]
R-0
15
0
TXR[15:0]
R-0
LEGEND: R = Read only; -n = value after reset
Figure 23-160. Transmission Request Register 2 (TXRQ2) [offset_CC = 324h]
31
16
TXR[63:48]
R-0
15
0
TXR[47:32]
R-0
LEGEND: R = Read only; -n = value after reset
Figure 23-161. Transmission Request Register 3 (TXRQ3) [offset_CC = 328h]
31
16
TXR[95:80]
R-0
15
0
TXR[79:64]
R-0
LEGEND: R = Read only; -n = value after reset
Figure 23-162. Transmission Request Register 4 (TXRQ4) [offset_CC = 32Ch]
31
16
TXR[127:112]
R-0
15
0
TXR[111:96]
R-0
LEGEND: R = Read only; -n = value after reset
Table 23-141. Transmission Request Registers (TXRQn) Field Descriptions
Bit
127-0
Field
Value
TXR[n]
Description
Transmission request.
0
The respective message buffer is not ready for transmission.
1
If the flag is set, the respective message buffer is ready for transmission. Respectively, transmission of
this message buffer is in progress. In single-shot mode the flags are reset after transmission has
completed.
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23.19.2.6.6 New Data Registers (NDAT[1-4])
The four registers reflect the state of the ND flags of all configured message buffers. ND flags
corresponding to transmit buffers have no meaning. If the number of configured message buffers is less
than 128, the remaining ND flags have no meaning. The registers are reset when the communication
controller leaves CONFIG state or enters STARTUP state.
Figure 23-166 through Figure 23-163 and Table 23-142 illustrate these registers.
Figure 23-163. New Data Register 1 (NDAT1) [offset_CC = 330h]
31
16
ND[31:16]
R-0
15
0
ND[15:0]
R-0
LEGEND: R = Read only; -n = value after reset
Figure 23-164. New Data Register 2 (NDAT2) [offset_CC = 334h]
31
16
ND[63:48]
R-0
15
0
ND[47:32]
R-0
LEGEND: R = Read only; -n = value after reset
Figure 23-165. New Data Register 3 (NDAT3) [offset_CC = 338h]
31
16
ND[95:80]
R-0
15
0
ND[79:64]
R-0
LEGEND: R = Read only; -n = value after reset
Figure 23-166. New Data Register 4 (NDAT4) [offset_CC = 33Ch]
31
16
ND[127:112]
R-0
15
0
ND[111:96]
R-0
LEGEND: R = Read only; -n = value after reset
1222
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Table 23-142. New Data Registers (NDATn) Field Descriptions
Bit
Field
127-0
ND[n]
Value
Description
New data.
0
The flags are reset when the header section of the corresponding message buffer is reconfigured or
when the data section has been transferred to the output buffer.
1
The flags are set when a valid received data frame matches the message buffer's filter configuration,
independent of the payload length received or the payload length configured for that message buffer.
The flags are not set after reception of null frames except for message buffers belonging to the receive
FIFO.
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23.19.2.6.7 Message Buffer Status Changed Registers (MBSC[1-4])
The four registers reflect the state of the MBC flags of all configured message buffers. If the number of
configured message buffers is less than 128, the remaining MBC flags have no meaning.
Figure 23-170 through Figure 23-167 and Table 23-143 illustrate these registers.
Figure 23-167. Message Buffer Status Changed Register 1 (MBSC1) [offset_CC = 340h]
31
16
MBS[31:16]
R-0
15
0
MBS[15:0]
R-0
LEGEND: R = Read only; -n = value after reset
Figure 23-168. Message Buffer Status Changed Register 2 (MBSC2) [offset_CC = 344h]
31
16
MBS[63:48]
R-0
15
0
MBS[47:32]
R-0
LEGEND: R = Read only; -n = value after reset
Figure 23-169. Message Buffer Status Changed Register 3 (MBSC3) [offset_CC = 348h]
31
16
MBS[95:80]
R-0
15
0
MBS[79:64]
R-0
LEGEND: R = Read only; -n = value after reset
Figure 23-170. Message Buffer Status Changed Register 4 (MBSC4) [offset_CC = 34Ch]
31
16
MBS[127:112]
R-0
15
0
MBS[111:96]
R-0
LEGEND: R = Read only; -n = value after reset
Table 23-143. Message Buffer Status Changed Register (MBSCn) Field Descriptions
Bit
127-0
1224
Field
Value
MBS[n]
Description
Message buffer status changed.
0
A flag is reset when the header section of the corresponding message buffer is reconfigured or when it
has been transferred to the Output Buffer.
1
The flag is set whenever the Message Handler changes one of the status flags VFRA, VFRB, SEOA,
SEOB, CEOA, CEOB, SVOA, SVOB, TCIA, TCIB, ESA, ESB, MLST, FTA, FTB in the header section
(see Message Buffer Status (MBS)Message Buffer Status (MBS)) of the respective message buffer.
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23.19.2.7 Identification Registers
23.19.2.7.1 Core Release Register (CREL)
Figure 23-171 and Table 23-144 illustrate this register.
Table 23-145 shows the release coding in register CREL.
Figure 23-171. Core Release Register (CREL) [offset_CC = 3F0h]
31
28
27
20
19
16
REL
STEP
YEAR
R-release info
R-release info
R-release info
15
8
7
0
MON
DAY
R-release info
R-release info
LEGEND: R = Read only; -n = value after reset
Table 23-144. Core Release Register (CREL) Field Descriptions
Bit
Field
Value
Description
31-28
REL
27-20
STEP
0-FFh
19-16
YEAR
0-Fh
15-8
MON
0-FFh
Design Time Stamp, Month. Two digits, BCD-coded.
7-0
DAY
0-FFh
Design Time Stamp, Day. Two digits, BCD-coded.
0-Fh
Core Release. One digit, BCD-coded.
Step of Core Release. Two digits, BCD-coded.
Design Time Stamp, Year. One digit, BCD-coded.
Table 23-145. Release Coding
Release
Step
Sub-Step
Core Release Register
Contents
Name
1
0
0
1006 0519
Revision 1.0.0
1
0
1
1016 1211
Revision 1.0.1
1
0
2
10271031
Revision 1.0.2
1
0
3
10390206
Revision 1.0.3
23.19.2.7.2 Endian Register (ENDN)
Figure 23-172 and Table 23-146 illustrate this register.
Figure 23-172. Endian Register (ENDN) [offset_CC = 3F4h]
31
16
ETV
R-8765h
15
0
ETV
R-4321h
LEGEND: R = Read only; -n = value after reset
Table 23-146. Endian Register (ENDN) Field Descriptions
Bit
Field
Description
31-0
ETV
Endianness Test Value. The Endianness test value is 87654321h.
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23.19.2.8 Input Buffer
Double buffer structure consisting of input buffer host and input buffer shadow. While the host can write to
input buffer host, the transfer to the message RAM is done from input buffer shadow. The input buffer
holds the header and data sections to be transferred to the selected message buffer in the message RAM.
It is used to configure the message buffers in the message RAM and to update the data sections of
transmit buffers.
When updating the header section of a message buffer in the Message RAM from the Input Buffer, the
Message Buffer Status as described in Message Buffer Status (MBS), Message Buffer Status (MBS) is
automatically reset to zero.
The header sections of message buffers belonging to the receive FIFO can only be (re)configured when
the communication controller is in DEFAULT_CONFIG or CONFIG state. For those message buffers only
the payload length configured and the data pointer need to be configured by bits PLC of the Write Header
Section 2 (WRHS2) and by bits DP of Write Header Section 3 (WRHS3). All information required for
acceptance filtering is taken from the FIFO rejection filter and the FIFO rejection filter mask.
23.19.2.8.1 Write Data Section Registers (WRDS[1-64])
Holds the data words to be transferred to the data section of the addressed message buffer. The data
words (DWn) are written to the message RAM in transmission order from DW1 (byte0, byte1) to DWPL
(DWPL= number of data words as defined by the payload length configured in PLC of the Write Header
Section 2 (WRHS2)).
Figure 23-173 and Table 23-147 illustrate this register.
Figure 23-173. Write Data Section Registers (WRDSn) [offset_CC = 400h-4FCh]
31
16
MD
R/W-0
15
0
MD
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 23-147. Write Data Section Registers (WRDSn) Field Descriptions
Bit
31-0
Field
MD
Value
0-FFFF FFFFh
Description
Message data.
Note: DW127 is located on WRDS64.MD[15:0]. In this case, WRDS64.MD[31:16] is unused
(no valid data).The input buffer RAMs are initialized to 0 when leaving hardware reset or
by the controller host interface command CLEAR_RAMS.
MD(31-24) = DW 2n, byte 4n-1
MD(23-16) = DW 2n, byte 4n-2
MD(15-8) = DW 2n-1, byte 4n-3
MD(7-0) = DW 2n-1, byte 4n-4
1226
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23.19.2.8.2 Write Header Section 1 (WRHS1)
Figure 23-174 and Table 23-148 illustrate this register.
Figure 23-174. Write Header Section Register 1 (WRHS1) [offset_CC = 500h]
31
30
29
28
27
26
25
24
23
22
16
Reserved
MBI
TXM
PPIT
CFG
CHB
CHA
Rsvd
CYC
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
R/W-0
11
10
15
0
Reserved
FID
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23-148. Write Header Section Register 1 (WRHS1) Field Descriptions
Bit
31-30
29
28
27
26
25-24
Field
Reserved
Value
0
MBI
Reads return 0. Writes have no effect.
Message buffer interrupt. This bit enables the receive/transmit interrupt for the corresponding
message buffer. After a dedicated receive buffer has been updated by the message handler, flag
RXI and/or MBSI in the status interrupt register are set. After successful transmission the TXI flag
in the status interrupt register is set.
0
The corresponding message buffer interrupt is enabled.
1
The corresponding message buffer interrupt is disabled.
TXM
Transmission mode. This bit is used to select the transmission mode.
0
Continuous mode
1
Single-shot mode
PPIT
Payload preamble indicator transmit. This bit is used to control the state of the Payload Preamble
Indicator in transmit frames. If the bit is set in a static message buffer, the respective message
buffer holds network management information. If the bit is set in a dynamic message buffer, the
first two bytes of the payload segment may be used for message ID filtering by the receiver.
Message ID filtering of received FlexRay frames is not supported by the FlexRay module, but can
be done by the host CPU.
0
Payload Preamble Indicator is not set.
1
Payload Preamble Indicator is set.
CFG
CHB, CHA
Description
Message buffer configuration bit. This bit is used to configure the corresponding buffer as Transmit
buffer or as receive buffer. For message buffers belonging to the receive FIFO the bit is not
evaluated.
0
The corresponding buffer is configured as Receive buffer.
1
The corresponding buffer is configured as Transmit buffer.
0-3h
Channel filter control.
The 2-bit channel filtering field associated with each buffer serves as a filter for receive buffers and
as a control field for transmit buffers. See Table 23-149 for bit descriptions.
Note: If a message buffer is configured for the dynamic segment and both bits of the
channel filtering field are set to 1, no frames are transmitted resp. received frames are
ignored (same function as CHA = CHB = 0)
23
Reserved
22-16
CYC
15-11
Reserved
10-0
FID
0
0-7Fh
0
0-7FFh
Reads return 0. Writes have no effect.
Cycle code. The 7-bit cycle code determines the cycle set used for cycle counter filtering.
Reads return 0. Writes have no effect.
Frame ID.
Frame ID of the selected message buffer. The frame ID defines the slot number for transmission /
reception of the respective message.
Note: Message buffers with frame ID = 0 are considered not valid.
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Table 23-149. Channel Filter Control Bit Descriptions
CHB
CHA
Transmit Buffer
transmit frame on
Receive Buffer
store frame received from
0
0
no transmission
ignore frame
0
1
channel A
channel A
1
0
channel B
channel B
1
both channels
(static segment only)
channel A or B
(store first semantically valid frame, static segment only)
1
23.19.2.8.3 Write Header Section 2 (WRHS2)
Figure 23-175 and Table 23-150 illustrate this register.
Figure 23-175. Write Header Section Register 2 (WRHS2) [offset_CC = 504h]
31
23
22
16
Reserved
PLC
R-0
R/W-0
15
11
10
0
Reserved
CRC
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23-150. Write Header Section Register 2 (WRHS2) Field Descriptions
Bit
Field
31-23
Reserved
22-16
PLC
15-11
Reserved
10-0
CRC
1228
Value
0
0-7Fh
0
0-7FFh
Description
Reads return 0. Writes have no effect.
Payload length configured. Length of data section (number of 2-byte words) as configured by the
host. During static segment the static frame data length as configured by SFDL in the MHD
configuration register defines the payload length for all static frames. If the payload length
configured by PLC is shorter than this value padding bytes are inserted to ensure that frames have
proper physical length. The padding pattern is logical zero.
Reads return 0. Writes have no effect.
Header CRC. Receive Buffer: configuration not required. Transmit buffer: Header CRC calculated
and configured by the host. For calculation of the header CRC the payload length of the frame
send on the bus has to be considered. In static segment the payload length of all frames is
configured by MHDC.SFDL.
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23.19.2.8.4 Write Header Section 3 (WRHS3)
Figure 23-176 and Table 23-151 illustrate this register.
Figure 23-176. Write Header Section Register 3 (WRHS3) [offset_CC = 508h]
31
16
Reserved
R-0
15
11
10
0
Reserved
DP
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23-151. Write Header Section Register 3 (WRHS3) Field Descriptions
Bit
Field
31-11
Reserved
10-0
DP
Value
0
1-7FFh
Description
Reads return 0. Writes have no effect.
Data pointer. Pointer to the first 32-bit word of the data section of the addressed message buffer in
the message RAM.
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23.19.2.8.5 Input Buffer Command Mask (IBCM)
Configures how the message buffer in the message RAM selected by the input buffer command request
register is updated. When IBF host and IBF shadow are swapped, also mask bits LHSH, LDSH, and
STXRH are swapped with bits LHSS, LDSS, and STXRS to keep them attached to the respective input
buffer transfer.
Figure 23-177 and Table 23-152 illustrate this register.
Figure 23-177. Input Buffer Command Mask Register (IBCM) [offset_CC = 510h]
31
19
18
17
16
Reserved
STXRS
LDSS
LHSS
R-0
R-0
R-0
R-0
15
2
1
0
Reserved
3
STXRH
LDSH
LHSH
R-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23-152. Input Buffer Command Mask Register (IBCM) Field Descriptions
Bit
31-19
18
17
16
15-3
2
1
0
1230
Field
Reserved
Value
0
STXRS
Reads return 0. Writes have no effect.
Set transmission request shadow.
0
Reset TXR flag.
1
Set TXR flag, transmit buffer released for transmission (operation ongoing or finished).
LDSS
Load data section shadow.
0
Data section is not updated.
1
Data section is selected for transfer from input buffer to the message RAM (transfer ongoing or
finished).
LHSS
Reserved
Description
Load header section shadow.
0
Header section is not updated.
1
Header section is selected for transfer from input buffer to the message RAM (transfer ongoing or
finished)
0
Reads return 0. Writes have no effect.
STXRH
Set transmission request host. If this bit is set to 1, the transmission request flag TXR for the selected
message buffer is set in the transmission request registers to release the message buffer for
transmission. In single-shot mode the flag is cleared by the communication controller after transmission
has completed. The flags is evaluated for transmit buffers only.
0
Reset transmission request flag.
1
Set transmission request flag; transmit buffer released for transmission.
LDSH
Load data section host
0
Data section is not updated.
1
Data section is selected for transfer from input buffer to the message RAM.
LHSH
Load header section host
0
Header section is not updated.
1
Header section is selected for transfer from input buffer to the message RAM.
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23.19.2.8.6 Input Buffer Command Request (IBCR)
When the host writes the number of a target message buffer in the message RAM to IBRH in the input
buffer command request register, IBF host and IBF shadow are swapped. In addition the message buffer
numbers stored under IBRH and IBRS are also swapped.
With this write operation the IBSYS bit in the input buffer command request register is set to 1. The
message handler then starts to transfer the contents of IBF shadow to the message buffer in the message
RAM selected by IBRS.
While the message handler transfers the data from IBF shadow to the target message buffer in the
message RAM, the host may configure the next message in the IBF host. After the transfer between IBF
shadow and the message RAM has completed, the IBSYS bit is set back to 0 and the next transfer to the
message RAM may be started by the host by writing the respective target message buffer number to
IBRH.
If a write access to IBRH occurs while IBSYS is 1, IBSYH is set to 1. After completion of the ongoing data
transfer from IBF shadow to the message RAM, IBF host and IBF shadow are swapped, IBSYH is reset to
0. IBSYS remains set to 1, and the next transfer to the message RAM is started. In addition the message
buffer numbers stored under IBRH and IBRS are also swapped.
Any write access to an Input Buffer Register while both IBSYS and IBSYH are set will cause the error flag
IIBA in the Error Interrupt Register (EIR) to be set. In this case the Input Buffer will not be changed.
Figure 23-178 and Table 23-153 illustrate this register.
Figure 23-178. Input Buffer Command Request Register (IBCR) [offset_CC = 514h]
31
30
23
22
16
IBSYS
Reserved
IBRS
R-0
R-0
R-0
15
14
7
6
0
IBSYH
Reserved
IBRH
R-0
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; *These bits can be updated in DEFAULT_CONFIG or CONFIG state
only
Table 23-153. Input Buffer Command Request Register (IBCR) Field Descriptions
Bit
Field
31
IBSYS
30-23
Reserved
22-16
IBRS
15
Value
Input buffer busy shadow. Set to 1 after writing IBRH. When the transfer between IBF shadow and
the message RAM has completed, IBSYS is set back to 0.
0
Transfer between IBF shadow and message RAM is completed.
1
Transfer between IBF shadow and message RAM is in progress.
0
Reads return 0. Writes have no effect.
0-7Fh
IBSYH
14-7
Reserved
6-0
IBRH
Description
Input buffer request shadow. Number of the target message buffer actually updated / lately
updated.
Input buffer busy host. Set to 1 by writing IBRH while IBSYS is still 1. After the ongoing transfer
between IBF shadow and the message RAM has completed, the IBSYH is set back to 0.
0
No request is pending.
1
Request while transfer between IBF shadow and message RAM is in progress.
0
Reads return 0. Writes have no effect.
0-7Fh
Input buffer request host. Selects the target message buffer in the Message RAM for data transfer
from Input Buffer.
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23.19.2.9 Output Buffer
Double buffer structure consisting of output buffer host and output buffer shadow. While the host can read
from output buffer host, the transfer from the message RAM is done to output buffer shadow. The output
buffer holds the header and data sections of requested message buffers transferred from the message
RAM. Used to read out message buffers from the message RAM.
23.19.2.9.1 Read Data Section Registers (RDDS[1-64])
Holds the data words read from the data section of the addressed message buffer. The data words (DWn)
are read from the message RAM in reception order from DW1 (byte0, byte1) to DWPL (DWPL= number of
data words as defined by the payload length configured in bits PLC of the Read Header Section 2
(RDHS2)).
Figure 23-179 and Table 23-154 illustrate this register.
Figure 23-179. Read Data Section Registers (RDDSn) [offset_CC = 600h-6FCh]
31
16
MD
R/W-0
15
0
MD
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 23-154. Read Data Section Registers (RDDSn) Field Descriptions
Bit
31-0
Field
MD
Value
0-FFFF FFFFh
Description
Message data.
Note: DW127 is located on RDDS64.MD[15:0]. In this case, RDDS64.MD[31:16] is unused
(no valid data).The input buffer RAMs are initialized to 0 when leaving hardware reset or
by the controller host interface command CLEAR_RAMS.
MD(31-24) = DW 2n, byte 4n-1
MD(23-16) = DW 2n, byte 4n-2
MD(15-8) = DW 2n-1, byte 4n-3
MD(7-0) = DW 2n-1, byte 4n-4
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23.19.2.9.2 Read Header Section Register 1 (RDHS1)
Figure 23-180 and Table 23-155 illustrate this register.
Figure 23-180. Read Header Section Register 1 (RDHS1) [offset_CC = 700h]
31
30
29
28
27
26
25
24
23
22
16
Reserved
MBI
TXM
PPIT
CFG
CHB
CHA
Rsvd
CYC
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
R/W-0
11
10
15
0
Reserved
FID
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23-155. Read Header Section Register 1 (RDHS1) Field Descriptions
Bit
31-30
29
28
27
26
Field
Reserved
Value
0
MBI
0
The corresponding message buffer interrupt is enabled.
1
The corresponding message buffer interrupt is disabled.
Transmission mode. This bit is used to select the transmission mode.
0
Continuous mode
1
Single-shot mode
PPIT
Payload preamble indicator transmit.
0
Payload Preamble Indicator is not set.
1
Payload Preamble Indicator is set.
CFG
CHB, CHA
23
Reserved
Reads return 0. Writes have no effect.
Message buffer interrupt.
TXM
25-24
Description
Message buffer configuration bit.
0
The corresponding buffer is configured as Receive buffer.
1
The corresponding buffer is configured as Transmit buffer.
Channel filter control.
See Table 23-149 for bit descriptions.
22-16
CYC
15-11
Reserved
10-0
FID
0
0-7Fh
0
0-7FFh
Reads return 0. Writes have no effect.
Cycle code. The 7-bit cycle code determines the cycle set used for cycle counter filtering.
Reads return 0. Writes have no effect.
Frame ID.
Frame ID of the selected message buffer.
Note: Message buffers with frame ID = 0 are considered not valid.
NOTE: In case the message buffer read from the message RAM belongs to the receive FIFO, FID,
CHA, and CHB were updated from the received frame while CYC, CFG, PPIT, TXM, and
MBI are reset to zero.
For bit description, see also Section 23.19.2.8.2.
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23.19.2.9.3 Read Header Section Register 2 (RDHS2)
Figure 23-181 and Table 23-156 illustrate this register.
Figure 23-181. Read Header Section Register 2 (RDHS2) [offset_CC = 704h]
31
30
24
23
22
16
Rsvd
PLR
Rsvd
PLC
R-0
R-0
R-0
R-0
15
11
10
0
Reserved
CRC
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23-156. Read Header Section Register 2 (RDHS2) Field Descriptions
Bit
Field
31
Reserved
30-24
PLR
Value
0
0-7Fh
Description
Reads return 0. Writes have no effect.
Payload length received. Payload length value updated from received frame (exception: if
message buffer belongs to the receive FIFO PLR is also updated from received null frames).
When a message is stored into a message buffer the following behavior with respect to payload
length received and payload length configured is implemented:
PLR > PLC: The payload data stored in the message buffer is truncated to the payload length
configured if PLC even or else truncated to PLC + 1.
PLR VCLK Period = 40ns; C2TDELAY = 07h;
> tC2TDELAY = 360 ns
When the chip select signal becomes active, the slave has to prepare data transfer within 360 ns.
Note: If phase = 1, the delay between SPICS falling edge to the first edge of SPICLK will
have an additional 0.5 SPICLK period delay. This delay is as per the SPI protocol.
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Table 25-27. SPI Delay Register (SPIDELAY) Field Descriptions (continued)
Bit
23-16
Field
Value
Description
T2CDELAY
0-FFh
Transmit-end-to-chip-select-inactive-delay. See Figure 25-46 for an example. T2CDELAY is used
only in master mode. It defines a hold time for the slave device that delays the chip select
deactivation by a multiple of VCLK cycles after the last bit is transferred.
The hold time value is calculated as follows:
tT2CDELAY = (T2CDELAY +1) × VCLK Period
Example: VCLK = 25 MHz -> VCLK Period = 40ns; T2CDELAY = 03h;
> tT2CDELAY = 160 ns
After the last data bit (or parity bit) is being transferred the chip select signal is held active for 160
ns.
Note: If phase = 0, then between the last edge of SPICLK and rise-edge of SPICS there will
be an additional delay of 0.5 SPICLK period. This is as per the SPI protocol.
Both C2TDELAY and T2CDELAY counters do not have any dependency on the SPIENA pin
value. Even if the SPIENA pin is asserted by the slave, the master will continue to delay the start
of SPICLK until the C2TDELAY counter overflows.
Similarly, even if the SPIENA pin is deasserted by the slave, the master will continue to hold the
SPICS pins active until the T2CDELAY counter overflows. In this way, it is assured that the setup
and hold times of the SPICS pins are determined by the delay timers alone. To achieve better
throughput, it should be ensured that these two timers are kept at the minimum possible values.
15-8
T2EDELAY
0-FFh
Transmit-data-finished to ENA-pin-inactive time-out. T2EDELAY is used in master mode only. It
defines a time-out value as a multiple of SPI clock before SPIENA signal has to become inactive
and after SPICS becomes inactive. SPICLK depends on which data format is selected. If the slave
device is missing one or more clock edges, it becomes de-synchronized. In this case, although the
master has finished the data transfer, the slave is still waiting for the missed clock pulses and the
ENA signal is not disabled.
The T2EDELAY defines a time-out value that triggers the DESYNC flag, if the SPIENA signal is
not deactivated in time. The DESYNC flag is set to indicate that the slave device did not de-assert
its SPIENA pin in time to acknowledge that it received all bits of the sent word. See Figure 25-47
for an example of this condition.
Note: DESYNC is also set if the SPI detects a de-assertion of SPIENA before the end of the
transmission.
The time-out value is calculated as follows:
tT2EDELAY = T2EDELAY/SPIclock
Example: SPIclock = 8 Mbit/s; T2EDELAY = 10h;
> tT2EDELAY = 2 µs
The slave device has to disable the ENA signal within 2 µs, otherwise DESYNC is set and an
interrupt is asserted (if enabled).
7-0
C2EDELAY
0-FFh
Chip-select-active to ENA-signal-active time-out. C2EDELAY is used only in master mode and it
applies only if the addressed slave generates an ENA signal as a hardware handshake response.
C2EDELAY defines the maximum time between when the SPI activates the chip-select signal and
the addressed slave has to respond by activating the ENA signal. C2EDELAY defines a time-out
value as a multiple of SPI clocks. The SPI clock depends on whether data format 0 or data format
1 is selected. See Figure 25-48 for an example of this condition.
Note: If the slave device does not respond with the ENA signal before the time-out value is
reached, the TIMEOUT flag in the SPIFLG register is set and a interrupt is asserted (if
enabled).
If a time-out occurs, the SPI clears the transmit request of the timed-out buffer, sets the TIMEOUT
flag for the current buffer, and continues with the transfer of the next buffer in the sequence that is
enabled.
The timeout value is calculated as follows:
tC2EDELAY = C2EDELAY/SPIclock
Example: SPIclock = 8 Mbit/s; C2EDELAY = 30h;
> tC2EDELAY = 6 ms
The slave device has to activate the ENA signal within 6 ms after the SPI has activated the chip
select signal (SPICS), otherwise the TIMEOUT flag is set and an interrupt is asserted (if enabled).
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Figure 25-45. Example: tC2TDELAY= 8 VCLK Cycles
SPICS
SPICLK
SPISOMI
VCLK
tC2TDELAY
Figure 25-46. Example: tT2CDELAY= 4 VCLK Cycles
SPICS
SPICLK
SPISOMI
VCLK
tT2CDELAY
Figure 25-47. Transmit-Data-Finished-to-ENA-Inactive-Timeout
SPICS
SPIENA
SPICLK
SPISOMI
tT2EDELAY
Figure 25-48. Chip-Select-Active-to-ENA-Signal-Active-Timeout
SPICS
SPIENA
SPICLK
SPISOMI
tC2EDELAY
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25.9.20 SPI Default Chip Select Register (SPIDEF)
Figure 25-49. SPI Default Chip Select Register (SPIDEF) [offset = 4Ch]
31
16
Reserved
R-0
15
8
7
0
Reserved
CSDEF
R-0
R/W-FFh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25-28. SPI Default Chip Select Register (SPIDEF) Field Descriptions
Bit
Field
31-8
Reserved
7-0
CDEF
Value
0
0-FFh
Description
Reads return 0. Writes have no effect.
Chip select default pattern. Master-mode only.
The CSDEF bits are output to the SPICS pins when no transmission is being performed. It
allows the user to set a programmable chip-select pattern that deselects all of the SPI slaves.
1380
0
SPICS is cleared to 0 when no transfer is active.
1
SPICS is set to 1 when no transfer is active.
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25.9.21 SPI Data Format Registers (SPIFMT)
Figure 25-50. SPI Data Format Registers (SPIFMT[3:0]) [offset = 5Ch-50h]
31
24
WDELAY
R/WP-0
23
22
21
20
19
18
17
16
PARPOL
PARITYENA
WAITENA
SHIFTDIR
HDUPLEX_
ENAx
DIS_CS_
TIMERS
POLARITY
PHASE
R/WP-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
15
8
7
5
4
0
PRESCALE
Reserved
CHARLEN
R/WP-0
R-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 25-29. SPI Data Format Registers (SPIFMT) Field Descriptions
Bit
Field
31-24 WDELAY
Value
Description
0-FFh
Delay in between transmissions for data format x (x= 0,1,2,3).Idle time that will be applied
at the end of the current transmission if the bit WDEL is set in the current buffer. The
delay to be applied is equal to:
WDELAY × PVCLK + 2 × PVCLK
P VCLK -> Period of VCLK.
23
22
PARPOL
Parity polarity: even or odd. PARPOLx can be modified in privilege mode only. It can be
used for data format x (x= 0,1,2,3).
0
An even parity flag is added at the end of the transmit data stream.
1
An odd parity flag is added at the end of the transmit data stream.
PARITYENA
Parity enable for data format x.
No parity generation/ verification is performed for this data format.
21
20
0
A parity bit is transmitted at the end of each transmitted word. At the end of a transfer the
parity generator compares the received parity bit with the locally-calculated parity flag. If
the parity bits do not match, the RXERR flag is set in the corresponding control field. The
parity type (even or odd) can be selected via the PARPOL bit.
1
Note: If an uncorrectable error flag is set in a slave-mode SPI, then the wrong parity
bit will be transmitted to indicate to the master that there has been some issue with
the data parity. The SPISOMI pins will be forced to transmit all 0s, and the parity bit
will be transmitted as 1 if even parity is selected and as 0 if odd parity is selected
(using the PARPOLx bit of this register). This behavior occurs regardless of an
uncorrectable parity error on either TXRAM or RXRAM.
WAITENA
The master waits for the ENA signal from slave for data format x. WAITENA is valid in
master mode only. WAITENA enables a flexible SPI network where slaves with ENA
signal and slaves without ENA signal can be mixed. WAITENA defines, for each
transferred word, whether the addressed slave generates the ENA signal or not.
0
The SPI does not wait for the ENA signal from the slave and directly starts the transfer.
1
Before the SPI starts the data transfer it waits for the ENA signal to become low. If the
ENA signal is not pulled down by the addressed slave before the internal time-out counter
(C2EDELAY) overflows, then the master aborts the transfer and sets the TIMEOUT error
flag.
SHIFTDIR
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Shift direction for data format x. With bit SHIFTDIRx, the shift direction for data format x
(x=0,1,2,3) can be selected.
0
MSB is shifted out first.
1
LSB is shifted out first.
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Table 25-29. SPI Data Format Registers (SPIFMT) Field Descriptions (continued)
Bit
Field
19
HDUPLEX_ENAx
Value
Description
Half Duplex transfer mode enable for Data Format x. This bit controls the I/O function of
SOMI/SIMO lines for a specific requirement where in the case of Master mode, TX pin SIMO will act as an RX pin, and in the case of Slave mode, RX pin - SIMO will act as a
TX pin.
0
Normal Full Duplex transfer.
1
If MASTER = 1, SPISIMO pin will act as an RX pin (No TX possible) If MASTER = 0,
SPISIMO pin will act as a TX pin (No RX possible).
For all normal operations, HDUPLEX_ENAx bits should always remain 0. It is intended for
the usage when the SPISIMO pin is used for both TX and RX operations at different
times.
18
17
DIS CS TIMERS
Disable chip-select timers for this format. The C2TDELAY and T2CDELAY timers are by
default enabled for all the data format registers. Using this bit, these timers can be
disabled for a particular data format, if they are not required. When a master is handling
multiple slaves, with varied set-up hold requirement, the application can selectively
choose to include or not include the chip-select delay timers for any slaves.
0
Both C2TDELAY and T2CDELAY counts are inserted for the chip selects.
1
No C2TDELAY or T2CDELAY is inserted in the chip select timings.
POLARITY
SPI data format x clock polarity. POLARITYx defines the clock polarity of data format x.
The following restrictions apply when switching clock phase and/or polarity:
• In 3-pin/4-pin with SPIENA pin configuration of a slave SPI, the clock phase and
polarity cannot be changed on-the-fly between two transfers. The slave should be reset
and reconfigured if clock phase/polarity needs to be switched. In summary, SPI format
switching is not fully supported in slave mode.
• Even while using chip select pins, the polarity of SPICLK can be switched only while
the slave is not selected by a valid chip select. The master SPI should ensure that
while switching SPICLK polarity, it has deselected all of its slaves. Otherwise, the
switching of SPICLK polarity may be incorrectly treated as a clock edge by some
slaves.
16
15-8
0
If POLARITYx is cleared to 0, the SPI clock signal is low-inactive, that is, before and after
data transfer the clock signal is low.
1
If POLARITYx is set to 1, the SPI clock signal is high-inactive, that is, before and after
data transfer the clock signal is high.
PHASE
SPI data format x clock delay. PHASEx defines the clock delay of data format x.
0
If PHASEx is cleared to 0, the SPI clock signal is not delayed versus the transmit/receive
data stream. The first data bit is transmitted with the first clock edge and the first bit is
received with the second (inverse) clock edge.
1
If PHASEx is set to 1, the SPI clock signal is delayed by a half SPI clock cycle versus the
transmit/receive data stream. The first transmit bit has to output prior to the first clock
edge. The master and slave receive the first bit with the first edge.
PRESCALE
SPI data format x prescaler. PRESCALEx determines the bit transfer rate of data format x
if the SPI is the network master. PRESCALEx is use to derive SPICLK from VCLK. If the
SPI is configured as slave, PRESCALEx does not need to be configured. The clock rate
for data format x can be calculated as:
BRFormatx = VCLK / (PRESCALEx + 1)
Note: When PRESCALEx is cleared to 0, the SPI clock rate defaults to VCLK/2.
7-5
Reserved
0
4-0
CHARLEN
0-1Fh
1382
Reads return 0. Writes have no effect.
SPI data format x data-word length. CHARLENx defines the word length of data format x.
Legal values are 0x02 (data word length = 2 bit) to 10h (data word length = 16). Illegal
values, such as 00 or 1Fh are not allowed; their effect is indeterminate.
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25.9.22 Interrupt Vector 0 (INTVECT0)
NOTE: The TG interrupt is not available in MibSPI in compatibility mode. Therefore, there is no
possibility to access this register in compatibility mode.
Figure 25-51. Interrupt Vector 0 (NTVECT0) [offset = 60h]
31
16
Reserved
R-0
15
6
5
1
0
Reserved
INTVECT0
SUSPEND0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 25-30. Transfer Group Interrupt Vector 0 (INTVECT0)
Bit
Field
31-6
Reserved
5-1
INTVECT0
Value
0
Description
Reads return 0. Writes have no effect.
INTVECT0. Interrupt vector for interrupt line INT0.
Returns the vector of the pending interrupt at interrupt line INT0. If more than one interrupt is
pending, INTVECT0 always references the highest prior interrupt source first.
Note: This field reflects the status of the SPIFLG register in vector format. Any updates to
the SPIFLG register will automatically cause updates to this field.
0
There is no pending interrupt.
1h + x
Transfer group x (x = 0 to 15) has a pending interrupt. SUSPEND0 reflects the type of interrupt
(suspend or finished).
11h
Error Interrupt pending. The lower half of SPIFLG contains more details about the type of error.
13h
The pending interrupt is a Receive Buffer Overrun interrupt.
12h
SPI mode: The pending interrupt is a Receive Buffer Full interrupt.
Mib mode: Reserved. This bit combination should not occur.
14h
SPI mode: The pending interrupt is a Transmit Buffer Empty interrupt.
Mib mode: Reserved. This bit combination should not occur.
All Other
SPI mode: Reserved. These bit combinations should not occur.
Combinations
0
SUSPEND0
Transfer suspended / Transfer finished interrupt flag.
Every time INTVECT0 is read by the host, the corresponding interrupt flag of the referenced
transfer group is cleared and INTVECT0 is updated with the vector coming next in the priority
chain.
0
The interrupt type is a transfer finished interrupt. In other words, the buffer array referenced by
INTVECT0 has asserted an interrupt because all of data from the transfer group has been
transferred.
1
The interrupt type is a transfer suspended interrupt. In other words, the transfer group referenced
by INTVECT0 has asserted an interrupt because the buffer to be transferred next is in suspend-towait mode.
NOTE: Reading from the INTVECT0 register when Transmit Empty is indicated does not clear the
TXINTFLG flag in the SPI Flag Register (SPIFLG). Writing a new word to the SPIDATx
register clears the Transmit Empty interrupt.
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NOTE: In multi-buffer mode, INTVECT0 contains the interrupt for the highest priority transfer group.
A read from INTVECT0 automatically causes the next-highest priority transfer group's
interrupt status to get loaded into INTVECT0 and its corresponding SUSPEND flag to get
loaded into SUSPEND0. The transfer group with the lowest number has the highest priority,
and the transfer group with the highest number has the lowest priority.
Reading the INTVECT0 register when the RXOVRN interrupt is indicated in multi-buffer
mode does not clear the RXOVRN flag and hence does not clear the vector. The RXOVRN
interrupt vector may be cleared in multi-buffer mode either by write-clearing the RXOVRN
flag in the SPI Flag Register (SPIFLG) or by reading the RXRAM Overrun Buffer Address
Register (RXOVRN_BUF_ADDR).
25.9.23 Interrupt Vector 1 (INTVECT1)
NOTE: The TG interrupt is not available in SPI in compatibility mode compatibility mode. Therefore,
there is no possibility to access this register in compatibility mode.
Figure 25-52. Interrupt Vector 1 (INTVECT1) [offset = 64h]
31
16
Reserved
R-0
15
6
5
1
0
Reserved
INTVECT1
SUSPEND1
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 25-31. Transfer Group Interrupt Vector 1 (INTVECT1)
Bit
Field
31-6
Reserved
5-1
INTVECT1
Value
0
Description
Reads return 0. Writes have no effect.
INTVECT1. Interrupt vector for interrupt line INT1.
Returns the vector of the pending interrupt at interrupt line INT1. If more than one interrupt is
pending, INTVECT1 always references the highest prior interrupt source first.
Note: This field reflects the status of the SPIFLG register in vector format. Any updates to
the SPIFLG register will automatically cause updates to this field.
0
There is no pending interrupt. SPI mode only.
11h
Error Interrupt pending. The lower half of SPIINT1 contains more details about the type of error.
SPI mode only.
13h
The pending interrupt is a Receive Buffer Overrun interrupt. SPI mode only.
12h
The pending interrupt is a Receive Buffer Full interrupt. SPI mode only.
14h
The pending interrupt is a Transmit Buffer Empty interrupt. SPI mode only.
All Other
Reserved. These bit combinations should not occur. SPI mode only.
Combinations
0
SUSPEND1
Transfer suspended / Transfer finished interrupt flag.
Every time INTVECT1 is read by the host, the corresponding interrupt flag of the referenced
transfer group is cleared and INTVECT1 is updated with the vector coming next in the priority
chain.
1384
0
The interrupt type is a transfer finished interrupt. In other words, the buffer array referenced by
INTVECT1 has asserted an interrupt because all of data from the transfer group has been
transferred.
1
The interrupt type is a transfer suspended interrupt. In other words, the transfer group referenced
by INTVECT1 has asserted an interrupt because the buffer to be transferred next is in suspend-towait mode.
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NOTE: Reading from the INTVECT1 register when Transmit Empty is indicated does not clear the
TXINTFLG flag in the SPI Flag Register (SPIFLG). Writing a new word to the SPIDATx
register clears the Transmit Empty interrupt.
NOTE: In multi-buffer mode, INTVECT1 contains the interrupt for the highest priority transfer group.
A read from INTVECT1 automatically causes the next-highest priority transfer group's
interrupt status to get loaded into INTVECT1 and its corresponding SUSPEND flag to get
loaded into SUSPEND1. The transfer group with the lowest number has the highest priority,
and the transfer group with the highest number has the lowest priority.
Reading the INTVECT1 register when the RXOVRN interrupt is indicated in multi-buffer
mode does not clear the RXOVRN flag and hence does not clear the vector. The RXOVRN
interrupt vector may be cleared in multi-buffer mode either by write-clearing the RXOVRN
flag in the SPI Flag Register (SPIFLG) or by reading the RXOVERN_BUF_ADDR register.
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25.9.24 SPI Pin Control Register 9 (SPIPC9)
SPIPC9 only applies to SPI2.
Figure 25-53. SPI Pin Control Register 9 (SPIPC9) [offset = 68h]
31
25
24
23
17
16
Reserved
SOMISRS0
Reserved
SIMOSRS0
R-0
R/W-0
R-0
R/W-0
15
11
10
9
Reserved
12
SOMISRS0
SIMOSRS0
CLKSRS
8
Reserved
0
R-0
R/W-0
R/W-0
R/W-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25-32. SPI Pin Control Register 9 (SPIPC9) Field Descriptions
Bit
31-25
24
Field
Reserved
Value
0
SOMISRS0
Description
Reads return the value that was last written. Writes have no effect.
SPI2 SOMI[0] slew control. This bit controls between the fast or slow slew mode.
Note: Duplicate Control Bits for SPI2 SOMI[0]. Bit 24 is not physically implemented. It is a
mirror of bit 11. Any write to bit 24 will be reflected on bit 11. When bit 24 and bit 11 are
simultaneously written, the value of bit 11 will control the SPI2 SOMI[0] pin. The read value
of bit 24 always reflects the value of bit 11.
23-17
16
Reserved
0
Fast mode is enabled; the normal output buffer is used for this pin.
1
Slow mode is enabled; slew rate control is used for this pin.
0
Reads return the value that was last written. Writes have no effect.
SIMOSRS0
SPI2 SIMO[0] slew control. This bit controls between the fast or slow slew mode.
Note: Duplicate Control Bits for SPI2 SIMO[0]. Bit 16 is not physically implemented. It is a
mirror of bit 10. Any write to bit 16 will be reflected on bit 10. When bit 16 and bit 10 are
simultaneously written, the value of bit 10 will control the SPI2 SIMO[0] pin. The read value
of bit 16 always reflects the value of bit 10.
15-12
11
10
9
8-0
1386
Reserved
0
Fast mode is enabled; the normal output buffer is used for this pin.
1
Slow mode is enabled; slew rate control is used for this pin.
0
Reads return 0. Writes have no effect.
SOMISRS0
SPI2 SOMI[0] slew control. This bit controls between the fast or slow slew mode.
0
Fast mode is enabled; the normal output buffer is used for this pin.
1
Slow mode is enabled; slew rate control is used for this pin.
SIMOSRS0
SPI2 SIMO[0] slew control. This bit controls between the fast or slow slew mode.
0
Fast mode is enabled; the normal output buffer is used for this pin.
1
Slow mode is enabled; slew rate control is used for this pin.
CLKSRS
Reserved
SPI2 CLK slew control. This bit controls between the fast or slow slew mode.
0
Fast mode is enabled; the normal output buffer is used for this pin.
1
Slow mode is enabled; slew rate control is used for this pin.
0
Reads return the value that was last written. Writes have no effect.
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25.9.25 Parallel/Modulo Mode Control Register (SPIPMCTRL)
NOTE: Do not configure MODCLKPOLx and MMODEx bits since this device does not support
modulo mode.
NOTE: The bits of this register are used in conjunction with the SPIFMTx registers. Each byte of this
register corresponds to one of the SPIFMTx registers.
1. Byte0 (Bits 7:0) are used when SPIFMT0 register is selected by DFSEL[1:0] = 00 in the
control field of a buffer.
2. Byte1 (Bits 15:8) are used when SPIFMT1 register is selected by DFSEL[1:0] = 01 in the
control field of a buffer.
3. Byte2 (Bits 23:16) are used when SPIFMT2 register is selected by DFSEL[1:0] = 10 in the
control field of a buffer.
4. Byte3 (Bits 31:24) are used when SPIFMT3 register is selected by DFSEL[1:0] = 11 in the
control field of a buffer.
Figure 25-54. Parallel/Modulo Mode Control Register (SPIPMCTRL) [offset = 6Ch]
31
30
29
28
26
25
24
Reserved
MODCLKPOL3
MMODE3
PMODE3
R-0
R/WP-0
R/WP-0
R/WP-0
23
22
21
20
18
17
16
Reserved
MODCLKPOL2
MMODE2
PMODE2
R-0
R/WP-0
R/WP-0
R/WP-0
15
14
13
12
10
9
8
Reserved
MODCLKPOL1
MMODE1
PMODE1
R-0
R/WP-0
R/WP-0
R/WP-0
7
6
5
4
2
1
0
Reserved
MODCLKPOL0
MMODE0
PMODE0
R-0
R/WP-0
R/WP-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 25-33. SPI Parallel/Modulo Mode Control Register (SPIPMCTRL) Field Descriptions
Bit
31-30
29
28-26
Field
Reserved
Value
0
MODCLKPOL3
Reads return 0. Writes have no effect.
Modulo mode SPICLK polarity. This bit determines the polarity of the SPICLK in modulo
mode only. If the MMODE3 bits are 000, this bit will be ignored.
0
Normal SPICLK in all the modes.
1
Polarity of the SPICLK will be inverted if Modulo mode is selected.
MMODE3
These bits determine whether the SPI/MibSPI operates with 1, 2, 4, 5, or 6 data lines (if
modulo option is supported by the module).
0
Normal single data line mode - default (PMODE3 should be set to 00)
1h
2-data line mode (PMODE3 should be set to 00)
2h
3-data line mode (PMODE3 should be set to 00)
3h
4-data line mode (PMODE3 should be set to 00)
4h
5-data line mode (PMODE3 should be set to 00)
5h
6-data line mode (PMODE3 should be set to 01)
6h-7h
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Table 25-33. SPI Parallel/Modulo Mode Control Register (SPIPMCTRL) Field Descriptions (continued)
Bit
25-24
23-22
21
20-18
Field
Value
PMODE3
Reserved
Parallel mode bits determine whether the SPI/MibSPI operates with 1, 2, 4, or 8 data lines.
0
Normal operation/1-data line (MMODE3 should be set to 000)
1h
2-data line mode (MMODE3 should be set to 000)
2h
4-data line mode (MMODE3 should be set to 000)
3h
8-data line mode (MMODE3 should be set to 000)
0
Reads return 0. Writes have no effect.
MODCLKPOL2
Modulo mode SPICLK polarity. This bit determines the polarity of the SPICLK in modulo
mode only. If the MMODE2 bits are 000, this bit will be ignored.
0
Normal SPICLK in all the modes.
1
Polarity of the SPICLK will be inverted if Modulo mode is selected.
MMODE2
These bits determine whether the SPI/MibSPI operates with 1, 2, 4, 5, or 6 data lines (if
modulo option is supported by the module).
0
1-data line Mode - default (PMODE2 should be set to 00)
1h
2-data line Mode (PMODE2 should be set to 00)
2h
3-data line mode (PMODE2 should be set to 00)
3h
4-data line mode (PMODE2 should be set to 00)
4h
5-data line mode (PMODE2 should be set to 00)
5h
6-data line mode (PMODE2 should be set to 01)
6h-7h
17-16
15-14
13
12-10
PMODE2
Reserved
7-6
Parallel mode bits determine whether the SPI/MibSPI operates with 1, 2, 4, or 8 data lines.
Normal operation/1-data line (MMODE2 should be set to 000)
1h
2-data line mode (MMODE2 should be set to 000)
2h
4-data line mode (MMODE2 should be set to 000)
3h
8-data line mode (MMODE2 should be set to 000)
0
Reads return 0. Writes have no effect.
MODCLKPOL1
Modulo mode SPICLK polarity. This bit determines the polarity of the SPICLK in modulo
mode only. If the MMODE1 bits are 000, this bit will be ignored.
0
Normal SPICLK in all the modes.
1
Polarity of the SPICLK will be inverted if Modulo mode is selected.
MMODE1
These bits determine whether the SPI/MibSPI operates with 1, 2, 4, 5, or 6 data lines (if
modulo option is supported by the module).
0
1-data line mode - default (PMODE1 should be set to 00)
1h
2-data line mode (PMODE1 should be set to 00)
2h
3-data line mode (PMODE1 should be set to 00)
3h
4-data line mode (PMODE1 should be set to 00)
4h
5-data line mode (PMODE1 should be set to 00)
5h
6-data line mode (PMODE1 should be set to 01)
5
1388
PMODE1
Reserved
Reserved
0
6h-7h
9-8
Description
Reserved
Parallel mode bits determine whether the SPI/MibSPI operates with 1, 2, 4, or 8 data lines.
0
Normal operation/1-data line (MMODE1 should be set to 000)
1h
2-data line mode (MMODE1 should be set to 000)
2h
4-data line mode (MMODE1 should be set to 000)
3h
8-data line mode (MMODE1 should be set to 000)
0
Reads return 0. Writes have no effect.
MODCLKPOL0
Modulo mode SPICLK polarity. This bit determines the polarity of the SPICLK in modulo
mode only. If the MMODE0 bits are 000, this bit will be ignored.
0
Normal SPICLK in all the modes.
1
Polarity of the SPICLK will be inverted if Modulo mode is selected.
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Table 25-33. SPI Parallel/Modulo Mode Control Register (SPIPMCTRL) Field Descriptions (continued)
Bit
Field
4-2
MMODE0
Value
These bits determine whether the SPI/MibSPI operates with 1, 2, 4, 5, or 6 data lines (if
modulo option is supported by the module).
0
1-data line mode - default (PMODE0 should be set to 00)
1h
2-data line mode (PMODE0 should be set to 00)
2h
3-data line mode (PMODE0 should be set to 00)
3h
4-data line mode (PMODE0 should be set to 00)
4h
5-data line mode (PMODE0 should be set to 00)
5h
6-data line mode (PMODE0 should be set to 01)
6h-7h
1-0
PMODE0
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Description
Reserved
Parallel mode bits determine whether the SPI/MibSPI operates with 1, 2, 4, or 8 data lines.
0
Normal operation/1-data line (MMODE0 should be set to 000)
1h
2-data line mode (MMODE0 should be set to 000)
2h
4-data line mode (MMODE0 should be set to 000)
3h
8-data line mode (MMODE0 should be set to 000)
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25.9.26 Multi-buffer Mode Enable Register (MIBSPIE)
NOTE: Accessibility of Multi-Buffer RAM
The multi-buffer RAM is not accessible unless the MSPIENA bit set to 1. The only exception
to this is in test mode, where, by setting RXRAMACCESS to 1, the multi-buffer RAM can be
fully accessed for both read and write.
Figure 25-55. Multi-buffer Mode Enable Register (MIBSPIE) [offset = 70h]
31
17
16
Reserved
RXRAM_ACCESS
R-0
R/WP-0
15
1
0
Reserved
MSPIENA
R-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 25-34. Multi-buffer Mode Enable Register (MIBSPIE) Field Descriptions
Bit
31-17
16
Field
Value
Reserved
0
RXRAM ACCESS
Description
Reads return 0. Writes have no effect.
Receive-RAM access control. During normal operating mode of SPI, the receive data/status
portion of multi-buffer RAM is read-only. To enable testing of receive RAM, direct read/write
access is enabled by setting this bit.
0
The RX portion of multi-buffer RAM is not writable by the CPU.
1
The whole of multi-buffer RAM is fully accessible for read/write by the CPU.
Note: The RX RAM ACCESS bit remains 0 after reset and it should remain cleared to 0 at
all times, except when testing the RAM. SPI should be given a local reset by using the
nRESET (SPIGCR0[0]) bit after RAM testing is performed so that the multi-buffer RAM
gets re-initialized.
15-1
Reserved
0
MSPIENA
0
Reads return 0. Writes have no effect.
Multi-buffer mode enable. After power-up or reset, MSPIENA remains cleared, which means
that the SPI runs in compatibility mode by default. If multi-buffer mode is desired, this register
should be configured first after configuring the SPIGCR0 register. If MSPIENA is not set to 1,
the multi-buffer mode registers are not writable.
0
The SPI runs in compatibility mode, that is, in this mode the MibSPI is fully code-compliant to
the standard device SPI. No multi-buffered-mode features are supported.
1
The SPI is configured to run in multi-buffer mode.
NOTE: Accessibility of Registers
Registers from this offset address onwards are not accessible in SPI compatibility mode.
They are accessible only in the multi-buffer mode.
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25.9.27 TG Interrupt Enable Set Register (TGITENST)
The register TGITENST contains the TG interrupt enable flags for transfer-finished and for transfersuspended events. Each of the enable bits in the higher half-word and the lower half-word of TGITENST
belongs to one TG.
The register map shown in Figure 25-56 and Table 25-35 represents a super-set device with the
maximum number of TGs (16) assumed. The actual number of bits available varies per device.
Figure 25-56. TG Interrupt Enable Set Register (TGITENST) [offset = 74h]
31
16
SETINTENRDY[15:0]
R/W-0
15
0
SETINTENSUS[15:0]
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 25-35. TG Interrupt Enable Set Register (TGITENST) Field Descriptions
Bit
31-16
Field
Value
SETINTENRDY[n]
Description
TG interrupt set (enable) when transfer finished. Bit 16 corresponds to TG0, bit 17 corresponds
to TG1, and so on.
0
Read: The TGx-completed interrupt is disabled. This interrupt does not get generated when
TGx completes.
Write: A write of 0 to this bit has no effect.
1
Read: The TGx-completed interrupt is enabled. The interrupt gets generated when TGx
completes.
Write: Enable the TGx-completed interrupt. The interrupt gets generated when TGx completes.
15-0
SETINTENSUS[n]
TG interrupt set (enabled) when transfer suspended. Bit 0 corresponds to TG0, bit 1
corresponds to TG1, and so on.
0
Read: The TGx-completed interrupt is disabled. This interrupt does not get generated when
TGx is suspended.
Write: A write of 0 to this bit has no effect.
1
Read: The TGx-completed interrupt is enabled. The interrupt gets generated when TGx is
suspended.
Write: Enable the TGx-completed interrupt. The interrupt gets generated when TGx is
suspended.
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25.9.28 TG Interrupt Enable Clear Register (TGITENCR)
The register TGITENCR is used to clear the interrupt enables for the TG-completed interrupt and the TGsuspended interrupts.
The register map shown in Figure 25-57 and Table 25-36 represents a super-set device with the
maximum number of TGs (16) assumed. The actual number of bits available varies per device.
Figure 25-57. TG Interrupt Enable Clear Register (TGITENCR) [offset = 78h]
31
16
CLRINTENRDY[15:0]
R/W-0
15
0
CLRINTENSUS[15:0]
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 25-36. TG Interrupt Enable Clear Register (TGITENCR) Field Descriptions
Bit
31-16
Field
Value
CLRINTENRDY[n]
Description
TG interrupt clear (disabled) when transfer finished. Bit 16 corresponds to TG0, bit 17
corresponds to TG1, and so on.
0
Read: The TGx-completed interrupt is disabled. This interrupt does not get generated when
TGx completes.
Write: A write of 0 to this bit has no effect.
1
Read: The TGx-completed interrupt is enabled. The interrupt gets generated when TGx
completes.
Write: Disable the TGx-completed interrupt. The interrupt does not get generated when TGx
completes.
15-0
CLRINTENSUS[n]
TG interrupt clear (disabled) when transfer suspended. Bit 0 corresponds to TG0, bit 1
corresponds to TG1, and so on.
0
Read: The TGx-completed interrupt is disabled. This interrupt does not get generated when
TGx is suspended.
Write: A write of 0 to this bit has no effect.
1
Read: The TGx-completed interrupt is enabled. The interrupt gets generated when TGx is
suspended.
Write: Disable the TGx-completed interrupt. The interrupt does not get generated when TGx is
suspended.
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25.9.29 Transfer Group Interrupt Level Set Register (TGITLVST)
The register TGITLVST sets the level of interrupts for transfer completed interrupt and for transfer
suspended interrupt to level 1.
The register map shown in Figure 25-58 andTable 25-37 represents a super-set device with the maximum
number of TGs (16) assumed. The actual number of bits available varies per device.
Figure 25-58. Transfer Group Interrupt Level Set Register (TGITLVST) [offset = 7Ch]
31
16
SETINTLVLRDY[15:0]
R/W-0
15
0
SETINTLVLSUS[15:0]
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 25-37. Transfer Group Interrupt Level Set Register (TGITLVST) Field Descriptions
Bit
31-16
Field
Value
SETINTLVLRDY[n]
Description
Transfer-group completed interrupt level set. Bit 16 corresponds to TG0, bit 17 corresponds to
TG1, and so on.
0
Read: The TGx-completed interrupt is set to INT0.
Write: A write of 0 to this bit has no effect.
1
Read: The TGx-completed interrupt is set to INT1.
Write: Set the TGx-completed interrupt to INT1.
15-0
SETINTLVLSUS[n]
Transfer-group suspended interrupt level set. Bit 0 corresponds to TG0, bit 1 corresponds to
TG1, and so on.
0
Read: The TGx-suspended interrupt is set to INT0.
Write: A write of 0 to this bit has no effect.
1
Read: The TGx-suspended interrupt is set to INT1.
Write: Set the TGx-suspended interrupt to INT1.
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25.9.30 Transfer Group Interrupt Level Clear Register (TGITLVCR)
The register TGITLVCR clears the level of interrupts for transfer completed interrupt and for transfer
suspended interrupt to level 0.
The register map shown in Figure 25-59 and Table 25-38 represents a super-set device with the
maximum number of TGs (16) assumed. The actual number of bits available varies per device.
Figure 25-59. Transfer Group Interrupt Level Clear Register (TGITLVCR) [offset = 80h]
31
16
CLRINTLVLRDY[15:0]
R/W-0
15
0
CLRINTLVLSUS[15:0]
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 25-38. Transfer Group Interrupt Level Clear Register (TGITLVCR) Field Descriptions
Bit
31-16
Field
Value
CLRINTLVLRDY[n]
Description
Transfer-group completed interrupt level clear. Bit 16 corresponds to TG0, bit 17 corresponds to
TG1, and so on.
0
Read: The TGx-completed interrupt is set to INT0.
Write: A write of 0 to this bit has no effect.
1
Read: The TGx-completed interrupt is set to INT1.
Write: Clear the TGx-completed interrupt to INT0.
15-0
CLRINTLVLSUS[n]
Transfer group suspended interrupt level clear. Bit 0 corresponds to TG0, bit 1 corresponds to
TG1, and so on.
0
Read: The TGx-suspended interrupt is set to INT0.
Write: A write of 0 to this bit has no effect.
1
Read: The TGx-suspended interrupt is set to INT1.
Write: Clear the TGx-suspended interrupt to INT0.
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25.9.31 Transfer Group Interrupt Flag Register (TGINTFLG)
The TGINTFLG register comprises the transfer group interrupt flags for transfer-completed interrupts
(INTFLGRDYx) and for transfer-suspended interrupts (INTFLGSUSx). Each of the interrupt flags in the
higher half-word and the lower half-word of TGINTFLG belongs to one TG.
The register map shown in Figure 25-60 and Table 25-39 represents a super-set device with the
maximum number of TGs (16) assumed. The actual number of bits available varies per device.
Figure 25-60. Transfer Group Interrupt Flag Register (TGINTFLG) [offset = 84h]
31
16
INTFLGRDY[15:0]
R/W1C-0
15
0
INTFLGSUS[15:0]
R/W1C-0
LEGEND: R/W = Read/Write; W1C = Write 1 to clear; -n = value after reset
Table 25-39. Transfer Group Interrupt Flag Register (TGINTFLG) Field Descriptions
Bit
31-16
Field
Value
INTFLGRDY[
n]
Description
Transfer-group interrupt flag for a transfer-completed interrupt. Bit 16 corresponds to TG0, bit 17
corresponds to TG1, and so on.
Note: Read Clear Behavior. Reading the interrupt vector registers TGINTVECT0 or TGINTVECT1
automatically clears the interrupt flag bit INTFLGRDYx referenced by the vector number given by
INTVECT0/INTVECT1 bits, if the SUSPEND[0:1] bit in the vector registers is 0.
0
Read: No transfer-completed interrupt occurred since last clearing of the INTFLGRDYx flag.
Write: A write of 0 to this bit has no effect.
1
Read: A transfer finished interrupt from transfer group x occurred. No matter whether the interrupt is
enabled or disabled (INTENRDYx = don't care) or whether the interrupt is mapped to INT0 or INT1,
INTFLGRDYx is set right after the transfer from TGx is finished.
Write: The corresponding bit flag is cleared.
15-0
INTFLGSUS[
n]
Transfer-group interrupt flag for a transfer-suspend interrupt. Bit 0 corresponds to TG0, bit 1
corresponds to TG1, and so on.
Note: Read Clear Behavior. Reading the interrupt vector registers TGINTVECT0 or TGINTVECT1
automatically clears the interrupt flag bit INTFLGSUSx referenced by the vector number given by
INTVECT0/INTVECT1 bits, if the SUSPEND[0:1] bit in the corresponding vector registers is 1.
0
Read: No transfer-suspended interrupt occurred since the last clearing of the INTFLGSUSx flag.
Write: A write of 0 to this bit has no effect.
1
Read: A transfer-suspended interrupt from TGx occurred. No matter whether the interrupt is enabled or
disabled (INTENSUSx = don't care) or whether the interrupt is mapped to INT0 or INT1, INTFLGSUSx
is set right after the transfer from transfer group x is suspended.
Write: The corresponding bit flag is cleared.
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25.9.32 Tick Count Register (TICKCNT)
One of the trigger sources for TGs is an internal periodic time trigger. This time trigger is called a tick
counter and is basically a down-counter with a preload/reload value. Every time the tick counter detects an
underflow it reloads the initial value and toggles the trigger signal provided to the TGs.
The trigger signal, shown in Figure 25-61 as a square wave, illustrates the different trigger event types for
the TGs (for example, rising edge, falling edge, and both edges).
Figure 25-61. Tick Counter Operation
Tick counter
Trigger signal
Counter reload
This register is shown in Figure 25-62 and described in Table 25-40.
Figure 25-62. Tick Count Register (TICKCNT) [offset = 90h]
31
30
TICKENA
RELOAD
29
CLKCTRL
28
27
Reserved
16
R/W-0
R/S-0
R/W-0
R-0
15
0
TICKVALUE
R/W-0
LEGEND: R/W = Read/Write; R = Read only; S = Set; -n = value after reset
Table 25-40. Tick Count Register (TICKCNT) Field Descriptions
Bit
Field
31
TICKENA
Value
Description
Tick counter enable.
0
The internal tick counter is disabled. The counter value remains unchanged.
Note: When the tick counter is disabled, the trigger signal is forced low.
1
30
RELOAD
The internal tick counter is enabled and is clocked by the clock source selected by CLKCTRL.
When TICKENA goes from 0 to 1, the tick counter is automatically loaded with the contents of
TICKVALUE.
Pre-load the tick counter. RELOAD is a set-only bit; writing a 1 to it reloads the tick counter with
the value stored in TICKVALUE. Reading RELOAD always returns a 0.
Note: When the tick counter is reloaded by the RELOAD bit, the trigger signal is not
toggled.
29-28
CLKCTRL
27-16
Reserved
15-0
TICKVALUE
1396
Tick counter clock source control. CLKCTRL defines the clock source that is used to clock the
internal tick counter.
0
SPICLK of data word format 0 is selected as the clock source of the tick counter.
1h
SPICLK of data word format 1 is selected as the clock source of the tick counter.
2h
SPICLK of data word format 2 is selected as the clock source of the tick counter.
3h
SPICLK of data word format 3 is selected as the clock source of the tick counter.
0
Reads return 0. Writes have no effect.
0-FFFFh
Initial value for the tick counter. TICKVALUE stores the initial value for the tick counter. The tick
counter is loaded with the contents of TICKVALUE every time an underflow condition occurs and
every time the RELOAD flag is set by the host.
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25.9.33 Last TG End Pointer (LTGPEND)
Figure 25-63. Last TG End Pointer (LTGPEND) [offset = 94h]
31
15
29
28
24
23
16
Reserved
TG_IN_SERVICE
Reserved
R-0
R-0
R-0
14
8
7
0
Rsvd
LPEND
Reserved
R-0
R/W-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25-41. Last TG End Pointer (LTGPEND) Field Descriptions
Bit
Field
31-29
Reserved
28-24
TG_IN_SERVICE
Value
0
Description
Reads return 0. Writes have no effect.
The TG number currently being serviced by the sequencer. These bits indicate the current
TG that is being serviced. This field can generally be used for code debugging.
0
No TG is being serviced by the sequencer.
1h
TG0 is being serviced by the sequencer.
:
10h
:
TG15 is being serviced by the sequencer.
Note: The number of transfer groups varies by device.
11h-1Fh
23-15
Reserved
14-8
LPEND
0
0-7Fh
Invalid values.
Reads return 0. Writes have no effect.
Last TG end pointer. Usually the TG end address (PEND) is inherently defined by the start
value of the starting pointer of the subsequent TG (PSTART). The TG ends one word
before the next TG starts (PEND[x] = PSTART[x+1] - 1). For a full configuration of MibSPI,
the last TG has no subsequent TG, that is, no end address is defined. Therefore, LPEND
has to be programmed to specify explicitly the end address of the last TG.
Note: When using all 8 transfer groups, program the LPEND bits to define the end of
the last transfer group. When using less than 8 transfer groups, leave the LPEND bits
programmed to point to the end of the buffer and create a dummy transfer group that
defines the end of your last intentional transfer group and occupies all the remaining
buffer space.
7-0
Reserved
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0
Reads return 0. Writes have no effect.
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25.9.34 TGx Control Registers (TGxCTRL)
Each TG can be configured via one dedicated control register. The register description shows one control
register (x) that is identical for all TGs. For example, the control register for TG2 is named TG2CTRL and
is located at base address + 98h + 4 × 2. The actual number of available control registers varies by
device.
Figure 25-64. MibSPI TG Control Registers (TGxCTRL) [offsets = 98h-D4h]
31
30
29
28
TGENA
ONESHOT
PRST
TGTD
Reserved
R/W-0
R/W-0
R/W-0
R-0
R-0
23
15
27
20
24
19
16
TRIGEVT
TRIGSRC
R/W-0
R/W-0
14
8
7
6
0
Rsvd
PSTART
Rsvd
PCURRENT
R-0
R/W-0
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25-42. TG Control Registers (TGxCTRL) Field Descriptions
Bit
Field
31
TGENA
Value
Description
TGx enable.
If the correct event (TRIGEVTx) occurs at the selected source (TRIGSRCx), a group transfer is
initiated if no higher-priority TG is in active-transfer mode or if one or more higher-priority TGs are
in transfer-suspend mode.
Disabling a TG while a transfer is ongoing will finish the ongoing word transfer but not the whole
group transfer.
30
29
0
TGx is disabled.
1
TGx is enabled.
ONESHOTx
Single transfer for TGx.
0
TGx initiates a transfer every time a trigger event occurs and TGENA is set.
1
A transfer from TGx will be performed only once (one shot) after a valid trigger event at the
selected trigger source. After the transfer is finished the TGENAx control bit will be cleared and
therefore no additional transfer can be triggered before the host enables the TG again. This one
shot mode ensures that after one group transfer the host has enough time to read the received
data and to provide new transmit data.
PRSTx
TGx pointer reset mode. Configures the way to resolve trigger events during an ongoing transfer.
This bit is meaningful only for level-triggered TGs. Edge-triggered TGs cannot be restarted before
their completion by another edge. The PRST bit will have no effect on this behavior.
Note: When the PRST bit is set, if the buffer being transferred at the time of a new trigger
event is a LOCK, CSHOLD or NOBRK buffer, then only after finishing those transfers, the
TG will be restarted. This means that even if the TG is retriggered, the TG will only be
restarted after finishing the transfer of the first non-LOCK or non-CSHOLD buffer. In the
case of the NOBRK buffer, after completing the ICOUNT number of transfers, the TG will be
restarted from its PSTART.
This means that TX control fields such as LOCK and CSHOLD, and DMA control fields such as
NOBRK have higher priority over anything else. They have the capability to delay the restart of the
TG even if it is retriggered when PRST is 1.
28
1398
0
If a trigger event occurs during a transfer from TGx, the event is ignored and is not stored
internally. The TGx transfer has priority over additional trigger events.
1
The TGx pointer (PCURRENTx) will be reset to the start address (PSTARTx) when a valid trigger
event occurs at the selected trigger source while a transfer from the same TG is ongoing. Every
trigger event resets PCURRENTx no matter whether the concerned TG is in transfer mode or not.
The trigger events have priority over the ongoing transfer.
TGTDx
TG triggered.
0
TGx has not been triggered or is no longer waiting for service.
1
TGx has been triggered and is either currently being serviced or waiting for servicing.
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Table 25-42. TG Control Registers (TGxCTRL) Field Descriptions (continued)
Bit
Field
27-24
Reserved
23-20
TRIGEVTx
Value
0
Description
Reads return 0. Writes have no effect.
Type of trigger event. A level-triggered TG can be stopped by de-activating the level trigger.
However, the following restrictions apply.
• Deactivating the level trigger for a TG during a NOBRK transfer does not stop the transfers until
all of the ICOUNT number of buffers are transferred for the NOBRK buffer. Once a NOBRK
buffer is prefetched, the trigger event loses control over the TG until the NOBRK buffer transfer
is completed.
• Once the transfer of a buffer with CSHOLD or LOCK bit set starts, deactivating the trigger level
does not stop the transfer until the sequencer completes the transfer of the next non-CSHOLD
or non-LOCK buffer in the same TG.
• Once the last buffer in a TG is pre-fetched, de-activating the trigger level does not stop the
transfer group until the last buffer transfer is completed. This means even if the trigger level is
deactivated at the beginning of the penultimate (one-before-last) buffer transfer, the sequencer
continues with the same TG until it is completed.
0
never
Never trigger TGx. This is the default value after reset.
1h
rising
edge
A rising edge (0 to 1) at the selected trigger source (TRIGSRCx) initiates a transfer for
TGx
2h
falling
edge
A falling edge (1 to 0) at the selected trigger source (TRIGSRCx) initiates a transfer for
TGx
3h
both
edges
Rising and falling edges at the selected trigger source (TRIGSRCx) initiates a transfer
for TGx
4h
Rsvd
Reserved
5h
highactive
While the selected trigger source (TRIGSRCx) is at a logic-high level (1), the group
transfer is continued and at the end of one group, transfer is restarted at the beginning.
If the logic level changes to low (0) during an ongoing group transfer, the whole group
transfer will be stopped.
6h
lowactive
7h
always
Note: If ONESHOTx is set, the transfer is performed only once.
While the selected trigger source (TRIGSRCx) is at a logic-low level (0), the group
transfer is continued and at the end of one group, transfer is restarted at the beginning.
If the logic level changes to high (1) during an ongoing group transfer, the whole group
transfer will be stopped.
Note: If ONESHOTx is set, the transfer is performed only once.
A repetitive group transfer will be performed.
Note: By setting the TRIGSRC to 0, the TRIGEVT to 7h (ALWAYS), and the
ONESHOTx bit to 1, software can trigger this TG. Upon setting the TGENA bit, the
TG is immediately triggered.
Note: If ONESHOTx is set, the transfer is performed only once.
8h-Fh
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Reserved
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Table 25-42. TG Control Registers (TGxCTRL) Field Descriptions (continued)
Bit
Field
19-16
Value
TRIGSRCx
Description
Trigger source. After reset, the trigger sources of all TGs are disabled.
0
Disabled
1h
EXT0
External trigger source 0. The actual source varies per device (for example, HET I/O
channel, event pin).
2h
EXT1
External trigger source 1. The actual source varies per device (for example, HET I/O
channel, event pin).
3h
EXT2
External trigger source 2. The actual source varies per device (for example, HET I/O
channel, event pin).
4h
EXT3
External trigger source 3. The actual source varies per device (for example, HET I/O
channel, event pin).
5h
EXT4
External trigger source 4. The actual source varies per device (for example, HET I/O
channel, event pin).
6h
EXT5
External trigger source 5. The actual source varies per device (for example, HET I/O
channel, event pin).
7h
EXT6
External trigger source 6. The actual source varies per device (for example, HET I/O
channel, event pin).
8h
EXT7
External trigger source 7. The actual source varies per device (for example, HET I/O
channel, event pin).
9h
EXT8
External trigger source 8. The actual source varies per device (for example, HET I/O
channel, event pin).
Ah
EXT9
External trigger source 9. The actual source varies per device (for example, HET I/O
channel, event pin).
Bh
EXT10
External trigger source 10. The actual source varies per device (for example, HET I/O
channel, event pin).
Ch
EXT11
External trigger source 11. The actual source varies per device (for example, HET I/O
channel, event pin).
Dh
EXT12
External trigger source 12. The actual source varies per device (for example, HET I/O
channel, event pin).
Eh
EXT13
External trigger source 13. The actual source varies per device (for example, HET I/O
channel, event pin).
Fh
15
Reserved
0
14-8
PSTARTx
0-7Fh
TICK
Internal periodic event trigger. The tick counter can initiate periodic group transfers.
Reads return 0. Writes have no effect.
TG start address. PSTARTx stores the start address of the corresponding TG. The corresponding
end address is inherently defined by the subsequent TG start address minus 1 (PENDx[TGx] =
PSTARTx[TGx+1]-1). PSTARTx is copied into PCURRENTx when:
• The TG is enabled
• The end of the TG is reached during a transfer
• A trigger event occurs while PRST is set to 1
7
6-0
Reserved
0
PCURRENTx
0-7Fh
Reads return 0. Writes have no effect.
Pointer to current buffer. PCURRENT is read-only. PCURRENTx stores the address (0...127) of
the buffer that corresponds to this TG. If the TG switches from active-transfer mode to suspend-towait mode, PCURRENTx contains the address of the currently suspended word. After the TG
resumes from suspend-to-wait mode, the next buffer will be transferred; that is, no buffer data is
transferred because of suspend-to-wait mode.
NOTE: Register bits vary by device
TG0 has the highest priority and TG15 has the lowest priority. Under the following conditions,
a lower-priority TG cannot be interrupted by a higher-priority TG:
1. When there is a CSHOLD or LOCK buffer, until the completion of the next buffer
transfer that is a non-CSHOLD or non-LOCK buffer.
2. An entire sequence of words transferred for a NOBRK DMA buffer.
3. Once the last word in a TG is pre-fetched.
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25.9.35 DMA Channel Control Register (DMAxCTRL)
Each DMA channel can be configured via one dedicated control register. The register description below
shows one exemplary control register that is identical for all DMA channels; for example, the control
register for DMA channel 0 is named DMA0CTRL. The MibSPI supports up to 8 bidirectional DMA
channels.
The number of bidirectional DMA channels varies by device. The number of DMA channels and hence the
number of DMA channel control registers may vary.
Figure 25-65. DMA Channel Control Register (DMAxCTRL) [offset = D8h-F4h]
31
30
24
23
20
19
16
ONESHOT
BUFID
RXDMA_MAP
TXDMA_MAP
R/W-0
R/W-0
R/W-0
R/W-0
15
14
13
RXDMAENA
TXDMAENA
NOBRK
12
ICOUNT
8
R/W-0
R/W-0
R/W-0
R/W-0
7
6
5
Reserved
COUNT_BIT17
COUNT
R-0
R-0
R-0
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25-43. DMA Channel Control Register (DMAxCTRL) Field Descriptions
Bit
Field
31
ONESHOT
Value
Description
Auto-disable of DMA channel after ICOUNT + 1 transfers.
Note: This ONESHOT applies to the DMA channel identified by x and will autodisable
based on ICOUNTx.
0
The length of the block transfer is fully controlled by the DMA controller. The enable bits
RXDMAENAx and TXDMAENAx are not modified by the MibSPI.
1
ONESHOT allows a block transfer of defined length (ICOUNTx + 1), mainly controlled by
the MibSPI and not by the DMA controller. After ICOUNTx + 1 transfers, the enable bits
RXDMAENAx and TXDMAENAx are automatically cleared by the MibSPI, hence no more
DMA requests are generated. In conjunction with NOBRKx, a burst transfer can be initiated
without any other transfer through another buffer.
30-24
BUFIDx
0-7Fh
Buffer utilized for DMA transfer. BUFIDx defines the buffer that is utilized for the DMA
transfer. In order to synchronize the transfer with the DMA controller with the NOBRK
condition the "suspend to wait until..." modes must be used.
23-20
RXDMA_MAPx
0-Fh
Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA
controller. One request line for receive data and the other for request line for transmit data.
RXDMA_MAPx defines the number of the physical DMA Request line that is connected to
the receive path of the MibSPI DMA channel.
If RXDMAENAx and TXDMAENAx are both set to 1, then RXDMA_MAPx shall differ from
TXDMA_MAPx and shall differ from any other used physical DMA Request line. Otherwise,
unexpected interference may occur.
19-16
TXDMA_MAPx
0-Fh
Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA
controller. One request line for receive data and the other for request line for transmit data.
TXDMA_MAPx defines the number of the physical DMA Request line that is connected to
the transmit path of the MibSPI DMA channel.
If RXDMAENAx and TXDMAENAx are both set to 1, then TXDMA_MAPx shall differ from
RXDMA_MAPx and shall differ from any other used physical DMA Request line. Otherwise,
unexpected interference may occur.
15
RXDMAENAx
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Receive data DMA channel enable.
0
No DMA request upon new receive data.
1
The physical DMA channel for the receive path is enabled. The first DMA request pulse is
generated after the first transfer from the referenced buffer (BUFIDx) is finished. The buffer
should be configured in as "skip until RXEMPTY is set" or "suspend to wait until RXEMPTY
is set" in order to ensure synchronization between the DMA controller and the MibSPI
sequencer.
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Table 25-43. DMA Channel Control Register (DMAxCTRL) Field Descriptions (continued)
Bit
Field
14
TXDMAENAx
13
Value
Description
Transmit data DMA channel enable.
0
No DMA request upon new transmit data.
1
The physical DMA channel for the transmit path is enabled. The first DMA request pulse is
generated right after setting TXDMAENAx to load the first transmit data. The buffer should
be configured in the as "skip until TXFULL is set" or "suspend to wait until TXFULL is set" in
order to ensure synchronization between the DMA controller and the MibSPI sequencer.
NOBRKx
Non-interleaved DMA block transfer. This bit is available in master mode only.
Note: Special Conditions during a NOBRK Buffer Transfer. If a NOBRK DMA buffer is
currently being serviced by the sequencer, then it is not allowed to be disabled
prematurely.
During a NOBRK transfer, the following operations are not allowed:
•
•
•
•
Clearing the NOBRKx bit to 0
Clearing the RXDMAENAx to 0 (if it is already 1)
Clearing the TXDMAENAx to 0 (if it is already 1)
Clearing the BUFMODE[2:0] bits in TXRAM to 000
Note: Any attempts to perform these actions during a NOBRK transfer will produce
unpredictable results.
0
DMA transfers through the buffer referenced by BUFIDx are interleaved by data transfers
from other active buffers or TGs. Every time the sequencer checks the DMA buffer, it
performs one transfer and then steps to the next buffer.
1
NOBRKx ensures that ICOUNTx + 1 data transfers are performed from the buffer
referenced by BUFIDx without a data transfer from any other buffer. The sequencer remains
at the DMA buffer until ICOUNTx + 1 transfers have been processed. For example, this can
be used to generate a burst transfer to one device without disabling the chip select signal
in-between (the concerned buffer has to be configured with CSHOLD = 1). Another example
would be to have a defined block data transfer in slave mode, synchronous to the master
SPI.
Note: Triggering of higher priority TGs or enabling of higher priority DMA channels
will not interrupt a NOBRK block transfer.
12-8
ICOUNTx
0-1Fh
Initial count of DMA transfers. ICOUNTx is used to preset the transfer counter COUNTx.
Every time COUNTx hits 0, it is reloaded with ICOUNTx. The real number of transfers
equals ICOUNTx plus 1.
If ONESHOTx is set, ICOUNTx defines the number of DMA transfers that are performed
before the MibSPI automatically disables the DMA channels. If NOBRKx is set, ICOUNTx
defines the number of DMA transfers that are performed in one sequence without a transfer
from any other buffer. If ONESHOTx and NOBRKx are not set, ICOUNTx should be 0.
Note: See Section 25.9.36 (ICOUNT) and Section 25.9.37 (DMACNTLEN) about how to
increase the ICOUNT to a 16-bit value. With this extended capability, MibSPI can
transfer a block of up to 65535 (65K) words without interleaving (if NOBRK is used) or
without deasserting the chip select between the buffers (if CSHOLD is used).
7
Reserved
6
COUNT_BIT17x
5-0
COUNTx
0
Reads return 0. Writes have no effect.
The 17th bit of the COUNT field of DMAxCOUNT register.
0-3Fh
Actual number of remaining DMA transfers. This field contains the actual number of DMA
transfers that remain, until the DMA channel is disabled, if ONESHOTx is set.
Note: If the TX and RX DMA requests are enabled, the COUNT register will be
decremented when the RX has been serviced.
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25.9.36 DMAxCOUNT Register (ICOUNT)
NOTE: These registers are used only if the LARGE COUNT bit in the DMACNTLEN register is set.
The number of bidirectional DMA channels varies by device. The number of DMA channels
and hence the number of DMA registers varies by device.
Figure 25-66. DMAxCOUNT Register (ICOUNT) [offset = F8h-114h]
31
16
ICOUNTx
R/W-0
15
0
COUNTx
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25-44. MibSPI DMAxCOUNT Register (ICOUNT) Field Descriptions
Bit
Field
Value
Description
31-16
ICOUNTx
0-FFFFh
Initial number of DMA transfers. ICOUNTx is used to preset the transfer counter COUNTx.
Every time COUNTx hits 0, it is reloaded with ICOUNTx. The real number of transfer equals
ICOUNTx plus 1. If ONESHOTx is set, ICOUNTx defines the number of DMA transfers that are
performed before the MibSPI automatically disables the corresponding DMA channel. If
NOBRKx is set, ICOUNTx defines the number of DMA transfers that are performed in one
sequence without a transfer from any other buffer.
15-0
COUNTx
0-FFFFh
Actual number of remaining DMA transfers. COUNTx Contains the actual number of DMA
transfers that remain, until the DMA channel is disabled, if ONESHOTx is set. Since the real
counter value is always ICOUNTx +1, the 17th bit of COUNTx is available on DMACTRLx[6] bit.
Note: Usage Tip for Block Transfer Using a Single DMA Request. It is possible to use the
multi-buffer RAM to transfer chunks of data to/from an external SPI. A DMA Controller
can be used to handle the data in bursts. Suppose a chunk of 64 bytes of data needs to
be transferred and a single DMA request needs to be generated at the end of transferring
the 64 bytes. This can be easily achieved by configuring a TG register for the 64 buffer
locations and using the DMAxCTRL/DMAxCOUNT registers to configure the last buffer
(64th) of the TG as the BUFID and enable RXDMA (NOBRK = 0). At the end of the transfer
of the 64th buffer, a DMA request will be generated on the selected DMA request
channel. The DMA controller can do a burst read of all 64 bytes from RXRAM and/or then
do a burst write to all 64 bytes to the TXRAM for the next chunk.
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25.9.37 DMA Large Count (DMACNTLEN)
Figure 25-67. DMA Large Count Register (DMACNTLEN) [offset = 118h]
31
16
Reserved
R-0
15
1
0
Reserved
LARGE_COUNT
R-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 25-45. MibSPI DMA Large Count Register (DMACNTLEN) Field Descriptions
Bit
31-1
0
Field
Value
Reserved
0
LARGE_COUNT
Description
Reads return 0. Writes have no effect.
Select either the 16-bit DMAxCOUNT counters or the smaller counters in DMAxCTRL.
0
Select the DMAxCTRL counters. Writes to the DMAxCTRL register will modify the ICOUNT
value. Reading ICOUNT and COUNT can be done from the DMAxCTRL register. The
DMAxCOUNT register should not be used since any write to this register will be overwritten by
a subsequent write to the DMAxCTRL register to set the TXDMAENA or RXDMAENA bits.
1
Select the DMAxCOUNT counters. Writes to the DMAxCTRL register will not modify the
ICOUNT value. The ICOUNT value must be written to in the DMAxCOUNT register before the
RXDMAENA or TXDMAENA bits are set in the DMAxCTRL register. The DMAxCOUNT register
should be used for reading COUNT or ICOUNT.
25.9.38 Multi-buffer RAM Uncorrectable Parity Error Control Register (UERRCTRL)
Figure 25-68. Multi-buffer RAM Uncorrectable Parity Error Control Register (UERRCTRL)
[offset = 120h]
31
16
Reserved
R-0
15
9
8
7
4
3
0
Reserved
PTESTEN
Reserved
EDEN
R-0
R/WP-0
R-0
R/WP-5h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 25-46. Multi-buffer RAM Uncorrectable Parity Error Control Register (UERRCTRL)
Field Descriptions
Bit
Field
31-9
Reserved
8
PTESTEN
7-4
Reserved
3-0
EDEN
Value
0
Description
Reads return 0. Writes have no effect.
Parity memory test enable. This bit maps the parity bits corresponding to multi-buffer RAM
locations into the peripheral RAM frame to make them accessible by the CPU. See
Section 25.11 for further details about parity memory testing.
0
Parity bits are not memory-mapped.
1
Parity bits are memory-mapped.
0
Reads return 0. Writes have no effect.
Error detection enable. These bits enable parity error detection.
5h
All Other Values
Parity error detection logic (default) is disabled.
Parity error detection logic is enabled.
Note: It is recommended to write a 1010 to enable error detection, to guard against a
soft error from disabling parity error detect
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25.9.39 Multi-buffer RAM Uncorrectable Parity Error Status Register (UERRSTAT)
Figure 25-69. Multi-buffer RAM Uncorrectable Parity Error Status Register (UERRSTAT)
[offset = 124h]
31
16
Reserved
R-0
15
1
0
Reserved
2
EDFLG1
EDFLG0
R-0
R/W1C-0
R/W1C-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear; -n = value after reset
Table 25-47. Multi-buffer RAM Uncorrectable Parity Error Status Register (UERRSTAT)
Field Descriptions
Bit
Field
31-2
Reserved
1
EDFLG1
Value
0
Description
Reads return 0. Writes have no effect.
Uncorrectable parity error detection flag. This flag indicates if a parity error occurred in the RXRAM.
Note: Reading the UERRADDR1 register clears the EDFLG1 bit.
0
Read: No error has occurred.
Write: Writing a 0 to this bit has no effect.
1
Read: An error was detected and the address is captured in the UERRADDR1 register.
Write: The bit is cleared to 0.
0
EDFLG0
Uncorrectable parity error detection flag. This flag indicates if a parity error occurred in the TXRAM.
Note: Reading the UERRADDR0 register clears the EDFLG0 bit.
0
Read: No error has occurred.
Write: Writing a 0 to this bit has no effect.
1
Read: An error was detected and the address is captured in the UERRADDR0 register.
Write: The bit is cleared to 0.
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25.9.40 RXRAM Uncorrectable Parity Error Address Register (UERRADDR1)
Figure 25-70. RXRAM Uncorrectable Parity Error Address Register (UERRADDR1) [offset = 128h]
31
16
Reserved
R-0
15
10
9
0
Reserved
OVERADDR1
R-0
R/C-x
LEGEND: R = Read only; C = Clear; -n = value after reset
Table 25-48. RXRAM Uncorrectable Parity Error Address Register (UERRADDR1) Field Descriptions
Bit
Field
31-10 Reserved
9-0
OVERADDR1
Value
0
200h-3FFh
Description
Reads return 0. Writes have no effect.
Uncorrectable parity error address for RXRAM. This register holds the address where a
parity error is generated while reading RXRAM. Only the CPU or DMA can read from
RXRAM locations. The address captured is byte-aligned. This error address is frozen from
being updated until it is read by the CPU. The offset address of RXRAM varies from 200h3FFh.
The register does not clear its contents during or after module-level reset, system-level
reset or even power-on reset.
A read operation to this register clears its contents to the default value 200h. After a
power-on reset the contents will be unpredictable. A read operation can be performed
after power-up to keep the register at its default value, if required. However, the contents
of this register are meaningful only when EDFLG1 is set to 1.
Note: A read of the UERRADDR1 register will clear EDFLG1 in the UERRSTAT
register. However, in emulation mode when the SUSPEND signal is high, a read
from the UERRADDR1 register does not clear EDFLG1.
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25.9.41 TXRAM Uncorrectable Parity Error Address Register (UERRADDR0)
Figure 25-71. TXRAM Uncorrectable Parity Error Address Register (UERRADDR0) [offset = 12Ch]
31
16
Reserved
R-0
15
9
8
0
Reserved
UERRADDR0
R-0
R/C-x
LEGEND: R = Read only; C = Clear; -n = value after reset
Table 25-49. TXRAM Uncorrectable Parity Error Address Register (UERRADDR0) Field Descriptions
Bit
Field
31-9
Reserved
8-0
UERRADDR0
Value
0
0-1FFh
Description
Reads return 0. Writes have no effect.
Uncorrectable parity error address for TXRAM. This register holds the address where a
parity error is generated while reading from TXRAM. The TXRAM can be read either by
CPU or by the MibSPI sequencer logic for transmission. The address captured is bytealigned. This error address is frozen from being updated until it is read by the CPU. The
offset address of TXRAM varies from 0-1FFh.
The register does not clear its contents during or after module-level reset, system-level
reset, or even power-on reset.
A read operation to this register clears its contents to all 0s. After a power-on reset, the
contents of this register will be unpredictable. A read operation can be performed after
power-up to clear the this register's contents, if required. However, the contents of this
register are meaningful only when EDFLG0 is set to 1.
Note: A read from the UERRADDR0 register will clear EDFLG0 in the UERRSTAT
register. However, in emulation mode when the SUSPEND signal is high, a read
from the UERRADDR0 register does not clear EDFLG0.
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25.9.42 RXRAM Overrun Buffer Address Register (RXOVRN_BUF_ADDR)
In multi-buffer mode, if a particular RXRAM location is written by the MibSPI sequencer logic after the
completion of a new transfer when that location already contains valid data, the RX_OVR bit will be set to
1 while the data is being written. The RXOVRN_BUF_ADDR register captures the address of the RXRAM
location for which a receiver overrun condition occurred.
Figure 25-72. RXRAM Overrun Buffer Address Register (RXOVRN_BUF_ADDR) [offset = 130h]
31
16
Reserved
R-0
15
10
9
0
Reserved
RXOVRN_BUF_ADDR
R-0
R-200h
LEGEND: R = Read only; -n = value after reset
Table 25-50. RXRAM Overrun Buffer Address Register (RXOVRN_BUF_ADDR) Field Descriptions
Bit
Field
31-10 Reserved
9-0
RXOVRN_BUF_ADDR
Value
Description
0
Reads return 0. Writes have no effect.
200h-3FCh
Address in RXRAM at which an overwrite occurred. This address value will show only
the offset address of the RAM location in the multi-buffer RAM address space. Refer
to the device-specific data sheet for the actual absolute address of RXRAM.
This word-aligned address can vary from 200h-3FCh. Contents of this register are
valid only when any of the INTVECT0 or INTVECT1 and SPIFLG registers show an
RXOVRN error vector while in multi-buffer mode. If there are multiple overrun errors,
then this register holds the address of first overrun address until it is read.
Note: Reading this register clears the RXOVRN interrupt flag in the SPIFLG
register and the TGINTVECTx.
Note: Receiver overrun errors in multi-buffer mode can be completely avoided
by using the SUSPEND until RXEMPTY feature, which can be programmed into
each buffer of any TG. However, using the SUSPEND until RXEMPTY feature will
make the sequencer wait until the current RXRAM location is read by the VBUS
master before it can start the transfer for the same buffer location again. This
may affect the overall throughput of the SPI transfer. By enabling the interrupt
on RXOVRN in multi-buffer mode, the user can rely on interrupts to know if a
receiver overrun has occurred. The address of the overrun in RXRAM is
indicated in this RXOVRN_BUF_ADDR register.
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25.9.43 I/O-Loopback Test Control Register (IOLPBKTSTCR)
This register controls test mode for I/O pins. It also controls whether loop-back should be digital or analog.
In addition, it contains control bits to induce error conditions into the module. These are to be used only for
module testing.
All of the control/status bits in this register are valid only when the IOLPBKTSTENA field is set to Ah.
Figure 25-73. I/O-Loopback Test Control Register (IOLPBKTSTCR) [offset = 134h]
31
25
23
21
24
Reserved
SCS_FAIL_
FLG
R-0
R/W1C-0
20
19
18
17
16
Reserved
CTRL_
BITERR
CTRL_
DESYNC
CTRL_
PARERR
CTRL_
TIMEOUT
CTRL_
DLENERR
R-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
12
11
15
7
8
Reserved
IOLPBKTSTENA
R-0
R/WP-0
2
1
0
Reserved
6
5
ERR_SCS_PIN
3
CTRL_SCS_
PIN_ERR
LPBKTYPE
RXPENA
R-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear; WP = Write in privilege mode only; -n = value after reset
Table 25-51. I/O-Loopback Test Control Register (IOLPBKTSTCR) Field Descriptions
Bit
Field
31-25 Reserved
24
Value
0
SCS FAIL FLG
Description
Reads return 0. Writes have no effect.
Bit indicating a failure on SPICS pin compare during analog loopback.
0
Read: No miscompares occurred on any of the eight chip select pins (vs. the internal
chip select number CSNR during transfers).
Write: Writing a 0 to this bit has no effect.
1
Read: A comparison between the internal CSNR field and the analog looped-back
value of one or more of the SPICS pins failed. A stuck-at fault is detected on one of the
SPICS pins. Comparison is done only on the pins that are configured as functional and
during transfer operation.
Write: This flag bit is cleared.
23-21 Reserved
20
19
18
17
0
CTRL BITERR
Controls inducing of BITERR during I/O loopback test mode.
0
Do not interfere with looped-back data.
1
Induces bit errors by inverting the value of the incoming data during loopback.
CTRL DESYNC
Controls inducing of the desync error during I/O loopback test mode.
0
Do not cause a desync error.
1
Induce a desync error by forcing the incoming SPIENA pin (if functional) to remain 0
even after the transfer is complete. This forcing will be retained until the kernel reaches
the idle state.
CTRL PARERR
Controls inducing of the parity errors during I/O loopback test mode.
0
Do not cause a parity error.
1
Induce a parity error by inverting the polarity of the parity bit.
CTRL TIMEOUT
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Reads return 0. Writes have no effect.
Controls inducing of the timeout error during I/O loopback test mode.
0
Do not cause a timeout error.
1
Induce a timeout error by forcing the incoming SPIENA pin (if functional) to remain 1
when transmission is initiated. The forcing will be retained until the kernel reaches the
idle state.
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Table 25-51. I/O-Loopback Test Control Register (IOLPBKTSTCR) Field Descriptions (continued)
Bit
Field
16
CTRL DLENERR
Value
Description
Controls inducing of the data length error during I/O loopback test mode.
0
Do not cause a data-length error.
1
Induce a data-length error.
Master mode: The SPIENA pin (if functional) is forced to 1 when the module starts
shifting data.
Slave mode: The incoming SPICS pin (if functional) is forced to 1 when the module
starts shifting data.
15-12 Reserved
11-8
0
IOLPBKSTENA
7-6
Reserved
5-3
ERR SCS PIN
Module I/O loopback test enable key.
Ah
Enable I/O loopback test mode.
All Other Values
Disable I/O loopback test mode.
0
0
Select SPICS[0] for injecting error.
1h
Select SPICS[1] for injecting error.
7h
1
0
Reads return 0. Writes have no effect.
Inject error on chip-select pin number x. The value in this field is decoded as the
number of the chip select pin on which to inject an error. During analog loopback, if
CTRL SCS PIN ERR bit is set to 1, then the chip select pin selected by this field is
forced to the opposite of its value in the CSNR.
:
2
Reads return 0. Writes have no effect.
CTRL SCS PIN
ERR
:
Select SPICS[7] for injecting error.
Enable/disable the injection of an error on the SPICS pins. The individual SPICS pins
can be chosen using the ERR SCS PIN field.
0
Disable the SPICS error-inducing logic.
1
Enable the SPICS error-inducing logic.
LPBK TYPE
Module I/O loopback type (analog/digital). See Figure 25-22 for the different types of
loopback modes.
0
Enable Digital loopback when IOLPBKTSTENA = 1010.
1
Enable Analog loopback when IOLPBKTSTENA = 1010.
RXPENA
Enable analog loopback through the receive pin.
Note: This bit is valid only when LPBK TYPE = 1, which chooses analog
loopback mode.
1410
0
Analog loopback is through the transmit pin.
1
Analog loopback is through the receive pin.
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25.9.44 SPI Extended Prescale Register 1 (EXTENDED_PRESCALE1 for SPIFMT0 and
SPIFMT1)
This register provides an extended Prescale values for SPICLK generation to be able to interface with
much slower SPI Slaves. This is an extension of SPIFMT0 and SPIFMT1 registers. For example,
EPRESCALE_FMT1[7:0] of EXTENDED_PRESCALE1 and PRESCALE1 of SPIFMT1 register will always
reflect the same contents. Similarly, EPRESCALE_FMT0[7:0] and PRESCALE0 of SPIFMT0 reflect the
same contents.
Figure 25-74. SPI Extended Prescale Register 1 (EXTENDED_PRESCALE1 for SPIFMT0 and
SPIFMT1) [offset = 138h]
31
27
26
16
Reserved
EPRESCALE_FMT1
R-0
R/WP-0
15
11
10
0
Reserved
EPRESCALE_FMT0
R-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 25-52. SPI Extended Prescale Register 1 (EXTENDED_PRESCALE1) Field Descriptions
Bit
Field
31-27 Reserved
26-16 EPRESCALE_FMT1
Value
0
0-7FFh
Description
Reads return 0. Writes have no effect.
EPRESCALE_FMT1. Extended Prescale value for SPIFMT1. EPRESCALE_FMT1
determines the bit transfer rate of data format 1 if the SPI/MibSPI is the network master.
EPRESCALE_FMT1 is use to derive SPICLK from VCLK. If the SPI is configured as
slave, EPRESCALE_FMT1 does not need to be configured. These
EPRESCALE_FMT1[7:0] bits and PRESCALE1 bits of SPIFMT1 register will point to the
same physically implemented register. The clock rate for data format 1 can be calculated
as:
BRFormat1 = VCLK / (EPRESCALE_FMT1 + 1)
Write: This register field should be written if a SPICLK prescaler of more VCLK/256 is
required. This field provides a prescaler of up to VCLK/2048 for SPICLK. Writing to this
register field will also get reflected in the PRESCALE1 bits of SPIFMT1 register.
Read: Reading this field will reflect the PRESCALE value based on the last written
register field, that is, EXTENDED_PRESCALE1[26:16] or SPIFMT1[15:8] register.
Note: If Extended Prescaler is required, it should be ensured that
EXTENDED_PRESCALE1 register is programmed after SPIFMT1 register is
programmed. This is to ensure that the final SPICLK prescale value is controlled by
EXTENDED_PRESCALE1 register when a prescale of more 256 is intended on
SPICLK. Writing to PRESCALE1 field of SPIFMT1 will automatically clear
EPRESCALE_FMT1[10:8] bits to 000 so that the integrity of PRESCALE value is
maintained.
15-11 Reserved
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Reads return 0. Writes have no effect.
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Table 25-52. SPI Extended Prescale Register 1 (EXTENDED_PRESCALE1) Field Descriptions (continued)
Bit
10-0
Field
Value
Description
EPRESCALE_FMT0
0-7FFh
EPRESCALE_FMT0. Extended Prescale value for SPIFMT0. EPRESCALE_FMT0
determines the bit transfer rate of data format 0 if the SPI/MibSPI is the network master.
EPRESCALE_FMT0 is use to derive SPICLK from VCLK. If the SPI is configured as
slave, EPRESCALE_FMT0 does not need to be configured. These
EPRESCALE_FMT0[7:0] bits and PRESCALE0 bits of SPIFMT0 register will point to the
same physically implemented register. The clock rate for data format 0 can be calculated
as:
BRFormat0 = VCLK / (EPRESCALE_FMT0 + 1)
Write: This register field should be written if a SPICLK prescaler of more VCLK/256 is
required. This field provides a prescaler of up to VCLK/2048 for SPICLK. Writing to this
register field will also get reflected in the PRESCALE0 bits of SPIFMT0 register.
Read: Reading this field will reflect the PRESCALE value based on the last written
register field, that is, EXTENDED_PRESCALE0[10:0] or SPIFMT0[15:8] register.
Note: If Extended Prescaler is required, it should be ensured that
EXTENDED_PRESCALE1 register is programmed after SPIFMT0 register is
programmed. This is to ensure that the final SPICLK prescale value is controlled by
EXTENDED_PRESCALE1 register when a prescale of more 256 is intended on
SPICLK. Writing to PRESCALE0 field of SPIFMT0 will automatically clear
EPRESCALE_FMT0[10:8] bits to 000 so that the integrity of PRESCALE value is
maintained.
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25.9.45 SPI Extended Prescale Register 2 (EXTENDED_PRESCALE2 for SPIFMT2 and
SPIFMT3)
This register provides an extended Prescale values for SPICLK generation to be able to interface with
much slower SPI Slaves. This is an extension of SPIFMT2 and SPIFMT3 registers. For example,
EPRESCALE_FMT3[7:0] of EXTENDED_PRESCALE2 and PRESCALE3 of SPIFMT3 register will always
reflect the same contents. Similarly, EPRESCALE_FMT2[7:0] and PRESCALE2 of SPIFMT2 reflect the
same contents.
Figure 25-75. SPI Extended Prescale Register 2 (EXTENDED_PRESCALE2 for SPIFMT2 and
SPIFMT3) [offset = 13Ch]
31
27
26
16
Reserved
EPRESCALE_FMT3
R-0
R/WP-0
15
11
10
0
Reserved
EPRESCALE_FMT2
R-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 25-53. SPI Extended Prescale Register 2 (EXTENDED_PRESCALE2) Field Descriptions
Bit
Field
31-27 Reserved
26-16 EPRESCALE_FMT3
Value
0
0-7FFh
Description
Reads return 0. Writes have no effect.
EPRESCALE_FMT3. Extended Prescale value for SPIFMT3. EPRESCALE_FMT3
determines the bit transfer rate of data format 3 if the SPI/MibSPI is the network master.
EPRESCALE_FMT3 is use to derive SPICLK from VCLK. If the SPI is configured as
slave, EPRESCALE_FMT3 does not need to be configured. These
EPRESCALE_FMT3[7:0] bits and PRESCALE3 bits of SPIFMT3 register will point to the
same physically implemented register. The clock rate for data format 1 can be calculated
as:
BRFormat3 = VCLK / (EPRESCALE_FMT3 + 1)
Write: This register field should be written if a SPICLK prescaler of more VCLK/256 is
required. This field provides a prescaler of up to VCLK/2048 for SPICLK. Writing to this
register field will also get reflected in the PRESCALE3 bits of SPIFMT3 register.
Read: Reading this field will reflect the PRESCALE value based on the last written
register field, that is, EXTENDED_PRESCALE3[26:16] or SPIFMT3[15:8] register.
Note: If Extended Prescaler is required, it should be ensured that
EXTENDED_PRESCALE2 register is programmed after SPIFMT3 register is
programmed. This is to ensure that the final SPICLK prescale value is controlled by
EXTENDED_PRESCALE2 register when a prescale of more 256 is intended on
SPICLK. Writing to PRESCALE3 field of SPIFMT3 will automatically clear
EPRESCALE_FMT3[10:8] bits to 000 so that the integrity of PRESCALE value is
maintained.
15-11 Reserved
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Reads return 0. Writes have no effect.
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Table 25-53. SPI Extended Prescale Register 2 (EXTENDED_PRESCALE2) Field Descriptions (continued)
Bit
10-0
Field
Value
Description
EPRESCALE_FMT2
0-7FFh
EPRESCALE_FMT2. Extended Prescale value for SPIFMT2. EPRESCALE_FMT2
determines the bit transfer rate of data format 2 if the SPI/MibSPI is the network master.
EPRESCALE_FMT2 is use to derive SPICLK from VCLK. If the SPI is configured as
slave, EPRESCALE_FMT2 does not need to be configured. These
EPRESCALE_FMT2[7:0] bits and PRESCALE2 bits of SPIFMT2 register will point to the
same physically implemented register. The clock rate for data format 0 can be calculated
as:
BRFormat2 = VCLK / (EPRESCALE_FMT2 + 1)
Write: This register field should be written if a SPICLK prescaler of more VCLK/256 is
required. This field provides a prescaler of up to VCLK/2048 for SPICLK. Writing to this
register field will also get reflected in the PRESCALE2 bits of SPIFMT2 register.
Read: Reading this field will reflect the PRESCALE value based on the last written
register field, that is, EXTENDED_PRESCALE2[10:0] or SPIFMT2[15:8] register.
Note: If Extended Prescaler is required, it should be ensured that
EXTENDED_PRESCALE2 register is programmed after SPIFMT2 register is
programmed. This is to ensure that the final SPICLK prescale value is controlled by
EXTENDED_PRESCALE2 register when a prescale of more 256 is intended on
SPICLK. Writing to PRESCALE2 field of SPIFMT2 will automatically clear
EPRESCALE_FMT2[10:8] bits to 000 so that the integrity of PRESCALE value is
maintained.
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25.10 Multi-Buffer RAM
The multi-buffer RAM is used for holding transit and received data, control and status information. The
multi-buffer RAM contains two banks of up to 128 32-bit words for a maximum configuration. One bank
(TXRAM) contains entries for transmit data (replicating the SPIDAT1 register). The other bank (RXRAM)
contains received data (replicating the SPIBUF register). The buffers can be partitioned into multiple TGs,
each containing a programmable number of buffers. Each of the buffers can be subdivided into 16-bit
transmit field, 16-bit receive field, 16-bit control field, and 16-bit status field, as displayed in Figure 25-76.
A 4-bit parity field per word is also included in each bank of RAM.
Figure 25-76. Multi-Buffer RAM Configuration
TXRAM Bank
35
Buffer 0
1
2
3
...
126
127
RXRAM Bank
32 31
16 15
Control0
Transmit0
Parity0
Parity1
Control1
Transmit1
Parity2
Control2
Transmit2
Parity3
Control3
Transmit3
Parity126
Parity127
Optional
Control126
Control127
Transmit126
Transmit127
0 35
Parity0
Parity1
Parity2
Parity3
32 31
Parity126
Parity127
16 15
Status0
Status1
Status2
Status3
Receive0
Receive1
Receive2
Receive3
Status126
Status127
Receive126
Receive127
0
Optional
All fields can be read and written with 8-bit, 16-bit, or 32-bit accesses.
The transmit fields can be written and read in the address range 000h to 1FFh. The transmit words
contain data and control fields.
The receive RAM fields are read-only and can be accessed through the address range 200h to 3FCh. The
receive words contain data and status fields.
The chip select number (CSNR) bit field of the control field for a given word is mirrored into the
corresponding receive-buffer status field after transmission.
The Parity is automatically calculated and copied to Parity location
NOTE: Please refer to the specific device datasheet for the actual number of transmit and receive
buffers.
Write to unimplemented buffer is overwriting the corresponding implemented buffer. In
MIBSPI, if the RAM SIZE specified is 32 buffers, write to 33rd buffer overwrites 1st buffer,
write to 34th buffer overwrites 2st buffer and so on.
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25.10.1 Multi-Buffer RAM Auto Initialization
When the MIBSPI is out of reset mode, auto initialization of multi-buffer RAM starts. The application code
must check for BUFINITACTIVE bit to be 0 (Multi-buffer RAM initialization is complete) before configuring
multi-buffer RAM.
Besides the default auto initialization after reset, the auto-initialization sequence can also be done by:
1. Enable the global hardware memory initialization key by programming a value of 1010b to the bits [3:0]
of the MINITGCR register of the System module.
2. Set the control bit for the multi-buffer RAM in the MSINENA System module register. This bit is devicespecific for each memory that support auto-initialization. Please refer to the device datasheet to identify
the control bit for the multi-buffer RAM. This starts the initialization process. The BUFINITACTIVE bit
will get set to reflect that the initialization is ongoing.
3. When the memory initialization is completed, the corresponding status bit in the MINISTAT register will
be set. Also, the BUFINITACTIVE bit will get cleared.
4. Disable the global hardware memory initialization key by programming a value of 0101 to the bits [3:0]
of the MINITGCR register of the System module.
Please refer to the Architecture chapter for more details on the memory auto-initialization process.
NOTE: During Auto Initialization process, all the Multi-buffer mode registers (except MIBSPIE) will
be reset to their default values. So, it should be ensured that Auto Initialization is completed
before configuring the Multi-buffer mode registers.
25.10.2 Multi-Buffer RAM Register Summary
This section describes the multi-buffer RAM control and transmit-data fields of each word of TXRAM, and
the status and receive-data fields of each word of RXRAM. The base address for multi-buffer RAM is
FF0E 0000h for MibSPI1 RAM, FF0C 000h for MibSPI3 RAM, and FF0A 0000h for MibSPI5 RAM.
Table 25-54. Multi-Buffer RAM Register Summary
Offset
1416
Acronym
Register Description
Base + 0h-1FFh
TXRAM
Multi-Buffer RAM Transmit Data Register
Section 25.10.3
Base + 200h-3FFh
RXRAM
Multi-Buffer RAM Receive Buffer Register
Section 25.10.4
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25.10.3 Multi-Buffer RAM Transmit Data Register (TXRAM)
Each word of TXRAM is a transmit-buffer register.
NOTE: Writing to only the control fields, bits 28 through 16, does not initiate any SPI transfer in
master mode. This feature can be used to set up SPICLK phase or polarity before actually
starting the transfer by only updating the DFSEL bit field to select the required phase and
polarity combination.
Figure 25-77. Multi-Buffer RAM Transmit Data Register (TXRAM)
[offset = RAM Base + 0h-1FFh]
31
28
27
26
BUFMODE
29
CSHOLD
LOCK
WDEL
25
DFSEL
24
23
CSNR
16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
15
0
TXDATA
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 25-55. Multi-Buffer RAM Transmit Data Register (TXRAM) Field Descriptions
Bit
31-29
Field
Value
BUFMODE
Description
Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word.
When one of the "skip" modes is selected, the sequencer checks the buffer status every time it
reads from this buffer. If the current buffer status (TXFULL, RXEMPTY) does not match, the buffer
is skipped without a data transfer.
When one of the "suspend" modes is selected, the sequencer checks the buffer status when it
reads from this buffer. If TXFULL and/or RXEMPTY do not match, the sequencer waits until a
match occurs. No data transfer is initiated until the status condition of this buffer changes.
28
0
disabled. The buffer is disabled.
1h
skip single-transfer mode. Skip this buffer until the corresponding TXFULL flag is set (new
transmit data is available).
2h
skip overwrite-protect mode. Skip this buffer until the corresponding RXEMPTY flag is set (new
receive data can be stored in RXDATA without data loss).
3h
skip single-transfer overwrite-protect mode. Skip this buffer until both of the corresponding
TXFULL and RXEMPTY flags are set. (new transmit data available and previous data received by
the host).
4h
continuous mode. Initiate a transfer each time the sequencer checks this buffer. Data words are
retransmitted if the buffer has not been updated. Receive data is overwritten, even if it has not
been read.
5h
suspend single-transfer mode. Suspend-to-wait until the corresponding TXFULL flag is set (the
sequencer stops at the current buffer until new transmit data is written in the TXDATA field).
6h
suspend overwrite-protect mode. Suspend-to-wait until the corresponding RXEMPTY flag is set
(the sequencer stops at the current buffer until the previously-received data is read by the host.
7h
suspend single-transfer overwrite-protect mode. Suspend-to-wait until the corresponding
TXFULL and RXEMPTY flags are set (the sequencer stops at the current buffer until new transmit
data is written into the TXDATA field and the previously-received data is read by the host).
CSHOLD
Chip select hold mode. The CSHOLD bit is supported in master mode only, it is ignored in slave
mode. CSHOLD defines the behavior of the chip select line at the end of a data transfer.
0
The chip select signal is deactivated at the end of a transfer after the T2CDELAY time has passed.
If two consecutive transfers are dedicated to the same chip select this chip select signal will be
deactivated for at least 2VCLK cycles before it is activated again.
1
The chip select signal is held active at the end of a transfer until a control field with new data and
control information is loaded into SPIDAT1. If the new chip select number equals the previous one,
the active chip select signal is extended until the end of transfer with CSHOLD cleared, or until the
chip-select number changes.
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Table 25-55. Multi-Buffer RAM Transmit Data Register (TXRAM) Field Descriptions (continued)
Bit
Field
27
LOCK
26
Value
Description
Lock two consecutive buffer words. Do not allow interruption by TGs with higher priority.
0
Any higher-priority TG can begin at the end of the current transaction.
1
A higher-priority TG cannot occur until after the next unlocked buffer word is transferred.
WDEL
Enable the delay counter at the end of the current transaction.
Note: The WDEL bit is supported in master mode only. In slave mode, this bit is ignored.
0
No delay will be inserted. However, SPICS pins will still be de-activated for at least for 2VCLK
cycles if CSHOLD = 0.
Note: The duration for which the SPICS pin remains deactivated also depends upon the
time taken to supply a new word after completing the shift operation (in compatibility
mode). If TXBUF is already full, then the SPICS pin will be deasserted for at least two VCLK
cycles (if WDEL = 0).
1
25-24
23-16
DFSEL
CSNR
After a transaction, WDELAY of the corresponding data format will be loaded into the delay
counter. No transaction will be performed until the WDELAY counter overflows. The SPICS pins
will be de-activated for at least (WDELAY + 2) × VCLK_Period duration.
Data word format select.
0
Data word format 0 is selected.
1h
Data word format 1 is selected.
2h
Data word format 2 is selected.
3h
Data word format 3 is selected.
0-FFh
Chip select (CS) number. CSNR defines the chip select pins that will be activated during the data
transfer. CSNR is a bit-mask that controls all chip select pins. See Table 25-56.
Note: If your MibSPI has less than 8 chip select pins, all unused upper bits will be 0. For
example, MiBSPI3 has 6 chip select pins, if you write FFh to CSNR, the actual number
stored in CSNR is 3Fh.
15-0
TXDATA
0-7FFFh
Transfer data. When written, these bits are copied to the shift register if it is empty. If the shift
register is not empty, then they are held in TXBUF.
SPIEN must be set to 1 before this register can be written to. Writing a 0 to SPIEN forces the
lower 16 bits of TXDATA to 0.
A write to this register (or to the TXDATA field only) drives the contents of the CSNR field on the
SPICS pins, if the pins are configured as functional pins (automatic chip select, see Section 25.2).
When this register is read, the contents of TXBUF, which holds the latest data written, will be
returned.
Note: Regardless of the character length, the transmit data should be right-justified before
writing to the SPIDAT1 register.
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Table 25-56. Chip Select Number Active
CSNR
Value
Chip Select Active:
CS[5] (1) CS[4] (1) CS[3] (1) CS[2] (1) CS[1] (1)
0h
No chip select pin is active.
1h
x
2h
x
3h
x
4h
x
5h
x
6h
x
x
x
x
7h
(1)
CS[0]
8h
x
9h
x
Ah
x
x
x
x
x
x
Bh
x
Ch
x
x
x
Dh
x
x
Eh
x
x
x
Fh
x
x
x
x
x
10h
x
11h
x
12h
x
13h
x
14h
x
x
15h
x
x
16h
x
x
x
17h
x
x
x
18h
x
x
19h
x
x
1Ah
x
x
x
x
x
x
x
x
x
x
x
1Bh
x
x
1Ch
x
x
x
x
1Dh
x
x
x
1Eh
x
x
x
x
1Fh
x
x
x
x
x
x
x
CSNR
Value
Chip Select Active:
CS[5] (1) CS[4] (1) CS[3] (1) CS[2] (1) CS[1] (1)
20h
x
21h
x
22h
x
x
23h
x
x
24h
x
x
25h
x
x
26h
x
x
x
27h
x
x
x
28h
x
x
CS[0]
x
29h
x
x
2Ah
x
x
x
x
x
x
x
2Bh
x
x
2Ch
x
x
x
x
2Dh
x
x
x
2Eh
x
x
x
x
2Fh
x
x
x
x
30h
x
x
31h
x
x
32h
x
x
33h
x
x
34h
x
x
x
35h
x
x
x
36h
x
x
x
x
37h
x
x
x
x
38h
x
x
x
39h
x
x
x
3Ah
x
x
x
x
x
x
x
x
x
x
x
x
x
x
3Bh
x
x
x
3Ch
x
x
x
x
x
3Dh
x
x
x
x
3Eh
x
x
x
x
x
3Fh
x
x
x
x
x
x
x
x
If your MibSPI does not have this chip select pin, this bit is 0.
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25.10.4 Multi-Buffer RAM Receive Buffer Register (RXRAM)
Each word of RXRAM is a receive-buffer register.
Figure 25-78. Multi-Buffer RAM Receive Buffer Register (RXRAM)
[offset = RAM Base + 200h-3FFh]
31
30
29
28
27
26
25
24
RXEMPTY
RXOVR
TXFULL
BITERR
DESYNC
PARITYERR
TIMEOUT
DLENERR
RS-1
RC-0
R-0
RC-0
RC-0
RC-0
RC-0
RC-0
23
16
LCSNR
R-0
15
0
RXDATA
R/W-0
LEGEND: R/W = Read/Write; R = Read only; C = Clear; S = Set; -n = value after reset
Table 25-57. Multi-Buffer Receive Buffer Register (RXRAM) Field Descriptions
Bit
Field
31
RXEMPTY
Value
Description
Receive data buffer empty. When the host reads the RXDATA field or the entire RXRAM register,
it automatically sets the RXEMPTY flag. When a data transfer is completed, the received data is
copied into RXDATA, and the RXEMPTY flag is cleared.
0
New data has been received and copied into RXDATA.
1
No data has been received since the last read of RXDATA.
This flag gets set to 1 under the following conditions:
• Reading the RXDATA field of the RXRAM register
• Writing a 1 to clear the RXINTFLG bit in the SPI Flag Register (SPIFLG)
Write-clearing the RXINTFLG bit before reading RXDATA indicates the received data is being
ignored. Conversely, RXINTFLG can be cleared by reading the RXDATA field of RXRAM (or the
entire register).
30
RXOVR
Receive data buffer overrun. When a data transfer is completed and the received data is copied
into RXBUF while it is already full, RXOVR is set. Overruns always occur to RXBUF, not to
RXRAM; the contents of RXRAM are overwritten only after it is read by the Peripheral (VBUSP)
master (CPU, DMA, or other host processor).
If enabled, the RXOVRN interrupt is generated when RXBUF is overwritten, and reading either SPI
Flag Register (SPIFLG) or SPIVECTx shows the RXOVRN condition. Two read operations from
the RXRAM register are required to reach the overwritten buffer word (one to read RXRAM, which
then transfers RXDATA into RXRAM for the second read).
Note: This flag is cleared to 0 when the RXDATA field of the RXRAM register is read.
Note: A special condition under which RXOVR flag gets set. If both RXRAM and RXBUF are
already full and while another buffer receive is underway, if any errors such as TIMEOUT,
BITERR, and DLEN_ERR occur, then RXOVR in RXBUF and SPI Flag Register (SPIFLG)
registers will be set to indicate that the status flags are getting overwritten by the new
transfer. This overrun should be treated like a normal receive overrun.
29
1420
0
No receive data overrun condition occurred since last read of the data field.
1
A receive data overrun condition occurred since last read of the data field.
TXFULL
Transmit data buffer full. This flag is a read-only flag. Writing into the SPIDAT0 or SPIDAT1 field
while the TX shift register is full will automatically set the TXFULL flag. Once the word is copied to
the shift register, the TXFULL flag will be cleared. Writing to SPIDAT0 or SPIDAT1 when both
TXBUF and the TX shift register are empty does not set the TXFULL flag.
0
The transmit buffer is empty; SPIDAT0/SPIDAT1 is ready to accept a new data.
1
The transmit buffer is full; SPIDAT0/SPIDAT1 is not ready to accept new data.
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Table 25-57. Multi-Buffer Receive Buffer Register (RXRAM) Field Descriptions (continued)
Bit
Field
28
BITERR
Value
Description
Bit error. There was a mismatch of internal transmit data and transmitted data.
Note: This flag is cleared to 0 when the RXDATA field of the RXRAM register is read.
27
0
No bit error occurred.
1
A bit error occurred. The SPI samples the signal of the transmit pins (master: SIMOx, slave:
SOMIx) at the receive point (one-half clock cycle after the transmit point). If the sampled value
differs from the transmitted value, a bit error is detected and the BITERR flag is set. Possible
reasons for a bit error include noise, an excessively high bit rate, capacitive load, or another
master/slave trying to transmit at the same time.
DESYNC
Desynchronization of slave device. This bit is valid in master mode only.
The master monitors the ENA signal coming from the slave device and sets the DESYNC flag if
ENA is deactivated before the last reception point or after the last bit is transmitted plus tT2EDELAY. If
DESYNCENA is set, an interrupt is asserted. Desynchronization can occur if a slave device
misses a clock edge coming from the master.
Note: In the Compatibility Mode MibSPI, under some circumstances it is possible for a
desync error detected for the previous buffer to be visible in the current buffer. This is
because the receive completion flag/interrupt is generated when the buffer transfer is
completed. But desynchronization is detected after the buffer transfer is completed. So, if
the VBUS master reads the received data quickly when an RXINT is detected, then the
status flag may not reflect the correct desync condition. In multi-buffer mode, the desync
flag is always guaranteed to be for the current buffer.
Note: This flag is cleared to 0 when the RXDATA field of the RXRAM register is read.
26
0
No slave desynchronization is detected.
1
A slave device is desynchronized.
PARITYERR
Parity error. The calculated parity differs from the received parity bit.
If the parity generator is enabled (selected individually for each buffer) an even or odd parity bit is
added at the end of a data word. During reception of the data word, the parity generator calculates
the reference parity and compares it to the received parity bit. If a mismatch is detected, the
PARITYERR flag is set.
Note: This flag is cleared to 0 when the RXDATA field of the RXRAM register is read.
25
0
No parity error is detected.
1
A parity error occurred.
TIMEOUT
Time-out because of non-activation of SPIENA pin.
The SPI generates a time-out when the slave does not respond in time by activating the ENA
signal after the chip select signal has been activated. If a time-out condition is detected, the
corresponding chip select is deactivated immediately and the TIMEOUT flag is set. In addition, the
TIMEOUT flag in the status field of the corresponding buffer and in the SPI Flag Register
(SPIFLG) is set.
Note: This bit is valid only in master mode.
Note: This flag is cleared to 0 when the RXDATA field of the RXRAM register is read.
24
0
No SPIENA pin time-out occurred.
1
An SPIENA signal time-out occurred.
DLENERR
Data length error flag.
Note: This flag is cleared to 0 when the RXDATA field of the RXRAM register is read.
23-16
LCSNR
15-0
RXDATA
0
No data-length error occurred.
1
A data length error occurred.
0-FFh
Last chip select number. LCSNR in the status field is a copy of CSNR in the corresponding control
field. It contains the chip select number that was activated during the last word transfer.
0-FFFFh
SPI receive data. This is the received word, transferred from the receive shift-register at the end of
a transfer. Regardless of the programmed character length and the direction of shifting, the
received data is stored right-justified in the register.
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25.11 Parity Memory
The parity portion of multi-buffer RAM is not accessible by the CPU during normal operating modes.
However, each read or write operation to the control/data/status portion of the multi-buffer RAM causes
reads/writes to the parity portion as well.
• Each write to the multi-buffer RAM (either from the Peripheral interface or by the MibSPI itself) causes
a write operation to the parity portion of RAM simultaneously to update the equivalent parity bits.
• Each read operation from the multi-buffer RAM (either from the Peripheral interface or by the MibSPI
itself) causes a read operation from the parity portion of the RAM for parity comparison purpose.
• Reads/Writes to multi-buffer RAM can either be caused by any CPU/DMA accesses or by the
sequencer logic of MibSPI itself.
• Incase of Parity error ESM module is notified to generate MIBSPI Parity ESM interrupt. User can check
the error status and address location captured in the UERRSTAT and UERRADDRx registers
respectively.
For testing the parity portion of the multi-buffer RAM, which is a 4-bit field per word address (1 bit per
byte), a separate parity memory test mode is available. Parity memory test mode can be enabled and
disabled by the PTESTEN bit in the UERRCTRL register.
During the parity test mode, the parity locations are addressable at the address between
RAM_BASE_ADDR + 0x400h and RAM_BASE_ADDR + 0x7FFh. Each location corresponds,
sequentially, to each TXRAM word, then to each RXRAM word. See Figure 25-79 for a diagram of the
memory map of parity memory during normal operating mode and during parity test mode.
During parity test mode, after writing the data/control portion of the RAM, the parity locations can be
written with incorrect parity bits to intentionally cause parity errors.
See the device-specific data sheet to get the actual base address of the multi-buffer RAM.
NOTE: The RX_RAM_ACCESS bit can also be set to 1 during the parity test mode to be enable
writes to RXRAM locations. Both parity RAM testing and RXRAM testing can be done
together.
There are 4 bits of parity corresponding to each of the 32-bit multi-buffer locations. Individual bits in the
parity memory are byte-addressable in parity test mode. See the example in Figure 25-80 for further
details.
NOTE: Polarity of the parity (odd/even) varies by device. In some devices, a control register in the
system module can be used to select odd or even parity.
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Figure 25-79. Memory Map for Parity Locations During Normal and Test Mode
Memory Map During Normal Operation
(Parity locations are not accessible by CPU)
Address
3
BASE+0x000h
0 31
Parity0
TXBUF0
Parity1
Parity126
TXBUF1
.
.
.
TXBUF126
Parity127
TXBUF127
.
.
BASE+0x1FFh
3
BASE+0x200h
0 31
Address
BASE+0x000h
0
31
TXBUF0
TXBUF1
.
.
.
TXBUF126
BASE+0x1FFh
TXBUF127
BASE+0x200h
RXBUF0
0
Parity0
RXBUF0
Parity1
Parity126
RXBUF1
.
.
.
RXBUF126
Parity127
RXBUF127
.
.
BASE+0x3FFh
0
Memory Map During Parity Test Mode
(Parity locations are accessible by CPU)
RXBUF1
.
.
.
RXBUF126
BASE+0x3FFh
RXBUF127
Multi-Buffer RAM
Multi-Buffer RAM
31 24 16
BASE+0x400h
8
0
TX Parity0
TX Parity1
TX Parity126
BASE+0x5FFh
TX Parity127
BASE+0x600h
RX Parity0
RX Parity1
RX Parity126
BASE+0x7FFh
RX Parity127
Parity Memory
* BASE - Base Address of Multi-Buffer RAM
Refer to specific Device Data sheet
for the actual value of BASE.
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25.11.1 Example of Parity Memory Organization
Suppose TXBUF5 (6th location in TXRAM) in the multi-buffer RAM is written with a value of A001_AA55.
If the polarity of the parity is set to odd, the corresponding parity location parity5 will get updated with
equivalent parity of 1011 in its field.
During parity-memory test mode, these bits can be individually byte addressed. The return data will be a
byte adjusted with actual parity bit in the LSB of the byte. If a word is read from the word-boundary
address of parity locations, then each bit of the 4-bit parity is byte-adjusted and a 32-bit word is returned.
0s will be padded into the parity bits to get each byte. See Figure 25-80 for a diagram.
Figure 25-80. Example of Memory-Mapped Parity Locations During Test Mode
3
0 31
1 0 1 1
BASE+014h
0
A001AA55
TXBUF5
Parity5
Memory organization during normal mode
31
BASE+014h
0
A001AA55
TXBUF5
31
BASE+ 400h + 014h
0000000
24
16
1 0000000
0 0000000
8
0
1 0000000
1
Parity5
Parity memory locations during test mode (memory mapped)
1 Shadedareas indicate reads return 0, writes have no effect. These registers are not physically present.
NOTE: Read Access to Parity Memory Locations
Parity memory locations can be read even without entering into parity memory test mode.
Their address remains as in memory test mode. It is only to enter parity-memory test mode
to enable write access to the parity memory locations.
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25.12 MibSPI Pin Timing Parameters
The pin timings of SPI can be classified based on its mode of operation. In each mode, different
configurations like Phase and Polarity affect the pin timings.
The pin directions are based on the mode of operation.
Master mode SPI:
• SPICLK (SPI Clock) - Output
• SPISIMO (SPI Slave In Master Out) - Output
• SPICS (SPI Slave Chip Selects) - Output
• SPISOMI (SPI Slave Out Master In) - Input
• SPIENA (SPI slave ready Enable) - Input
Slave mode SPI:
• SPICLK - Input
• SPISIMO - Input
• SPICS - Input
• SPISOMI - Output
• SPIENA - Output
NOTE: All the timing diagrams given below are with Phase = 0 and Polarity = 0. unless explicitly
stated otherwise.
25.12.1 Master Mode Timings for SPI/MibSPI
Figure 25-81. SPI/MibSPI Pins During Master Mode 3-pin Configuration
VCLK
Write to SPIDAT
SPICLK
SPISIMO
SPISOMI
* Dotted vertical lines indicate the receive edges
Figure 25-82. SPI/MibSPI Pins During Master Mode 4-pin with SPICS Configuation
VCLK
Write to SPIDAT
SPICS
SPICLK
SPISIMO
SPISOMI
* Dotted vertical lines indicate the receive edges
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Figure 25-83. SPI/MibSPI Pins During Master Mode 4-pin with SPIENA Configuration
VCLK
Write to SPIDAT
SPIENA
SPICLK
SPISIMO
SPISOMI
* De-activation of SPIENA pin is controlled by the Slave.
* Dotted vertical lines indicate the receive edges
Figure 25-84. SPI/MibSPI Pins During Master/Slave Mode with 5-pin Configuration
VCLK
Master
Write to SPIDAT
SPICS
SPICLK
SPISIMO
Slave
Write to SPIDAT
SPIENA
SPISOMI
* Dotted vertical lines indicate the receive edges for the Master
* ENABLE_HIGHZ is cleared to 0 in Slave SPI
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25.12.2 Slave Mode Timings for SPI/MibSPI
Figure 25-85. SPI/MibSPI Pins During Slave Mode 3-pin Configuration
Write to SPIDAT
VCLK
SPICLK
SPISOMI
SPISIMO
* Dotted vertical lines indicate the receive edges
Figure 25-86. SPI/MibSPI Pins During Slave Mode 4-pin with SPIENA Configuration
Write to SPIDAT
SPIENA
VCLK
SPICLK
* Diagram shows a relationship between the SPIENA from Slave and SPICLK from Master
Figure 25-87. SPI/MibSPI Pins During Slave Mode in 5-pin Configuration - (Single Slave)
SPICS
Write to SPIDAT
VCLK
SPIENA
SPICLK
* ENABLE_HIGHZ is cleared to 0 in Slave SPI
* Diagram shows relationship between the SPICS from a Master to SPIENA from Slave SPI when SPIENA
is configured in Push-Pull mode
Figure 25-88. SPI/MibSPI Pins During Slave Mode in 5-pin Configuration - (Single/Multi Slave)
SPICS
Write to SPIDAT
VCLK
SPIENA
SPICLK
* ENABLE_HIGHZ is set to 1 in Slave SPI
* Diagram shows relationship between the SPICS from a Master to SPIENA from Slave SPI when SPIENA
is configured in High-Impedance mode
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25.12.3 Master Mode Timing Parameter Details
In case of Master, the module drives out SPICLK. It also drives out the Transmit data on SPISIMO with
respect to its internal SPICLK. In case of Master mode, the RX data on the SPISOMI pin is registered with
respect to SPICLK received through the input buffer from the I/O pad.
If the chip select pin is functional, then the Master will drive out the SPICS pins before starting the
SPICLK. If the SPIENA pin is functional, then the Master will wait for an active low from the Slave on the
input pin to start the SPICLK.
25.12.4 Slave Mode Timing Parameter Details
In case of Slave mode, the module will drive only the SPISOMI and SPIENA pins. All other pins are inputs
to it. The RX data on the SPISIMO pin will be registered with respect to the SPICLK pin. The Slave will
use the SPICS pin to drive out the SPIENA pin if both are functional. If 4-pin with SPIENA is configured,
then the Slave will drive out an active-low signal on the SPIENA pin when new data is written to the TX
Shift Register. Irrespective of 4-pin with SPIENA or 5-pin configuration, the Slave will deassert the
SPIENA pin after the last bit is received. If ENABLE_HIGHZ (SPIINT0.24) bit is 0, the de-asserted value of
the SPIENA pin will be 1. Otherwise, it will depend upon the internal pull up or pull down resistor (if
implemented) depending upon the Specification of the Chip.
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Chapter 26
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Serial Communication Interface (SCI)/
Local Interconnect Network (LIN) Module
This chapter describes the serial communication interface (SCI) / local interconnect network (LIN) module.
The SCI/LIN is compliant to the LIN 2.1 protocol specified in the LIN Specification Package. This module
can be configured to operate in either SCI (UART) or LIN mode.
NOTE: This chapter describes a superset implementation of the LIN/SCI module that includes
features and functionality that require DMA. Since not all devices have DMA capability,
consult your device-specific datasheet to determine applicability of these features and
functions to your device being used.
Topic
...........................................................................................................................
26.1
26.2
26.3
26.4
26.5
26.6
26.7
26.8
26.9
26.10
26.11
26.12
26.13
26.14
Introduction and Features ................................................................................
SCI Communication Formats ............................................................................
SCI Interrupts .................................................................................................
SCI DMA Interface ...........................................................................................
SCI Configurations ..........................................................................................
SCI Low-Power Mode ......................................................................................
LIN Communication Formats ............................................................................
LIN Interrupts .................................................................................................
LIN DMA Interface ...........................................................................................
LIN Configurations.........................................................................................
Low-Power Mode ...........................................................................................
Emulation Mode ............................................................................................
SCI/LIN Control Registers ...............................................................................
GPIO Functionality.........................................................................................
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26.1 Introduction and Features
The SCI/LIN module can be programmed to work either as an SCI or as a LIN. The core of the module is
an SCI. The SCI’s hardware features are augmented to achieve LIN compatibility.
The SCI module is a universal asynchronous receiver-transmitter that implements the standard nonreturn
to zero format. The SCI can be used to communicate, for example, through an RS-232 port or over a Kline.
The LIN standard is based on the SCI (UART) serial data link format. The communication concept is
single-master/multiple-slave with a message identification for multi-cast transmission between any network
nodes.
Throughout the chapter Compatibility Mode refers to SCI Mode functionary of SCI/LIN Module. The initial
part of the chapter explains about the SCI functionality and later part about the LIN functionality. Though
the register are common for LIN and SCI, the register descriptions has notes to identify the register / bit
usage in different modes.
26.1.1 SCI Features
The following are the features of the SCI module:
• Standard universal asynchronous receiver-transmitter (UART) communication
• Supports full- or half-duplex operation
• Standard nonreturn to zero (NRZ) format
• Double-buffered receive and transmit functions in compatibility mode
• Supports two individually enabled interrupt lines: level 0 and level 1
• Configurable frame format of 3 to 13 bits per character based on the following:
– Data word length programmable from one to eight bits
– Additional address bit in address-bit mode
– Parity programmable for zero or one parity bit, odd or even parity
– Stop programmable for one or two stop bits
• Asynchronous or isosynchronous communication modes
• Two multiprocessor communication formats allow communication between more than two devices
• Sleep mode is available to free CPU resources during multiprocessor communication and then wake
up to receive an incoming message
• The 24-bit programmable baud rate supports 224 different baud rates provide high accuracy baud rate
selection
• At 100MHz Peripheral Clock, 3.125 Mbits/s is the Max Baud Rate achievable
• Capability to use Direct Memory Access (DMA) for transmit and receive data
• Five error flags and Seven status flags provide detailed information regarding SCI events
• Two external pins: LINRX and LINTX
• Multi-buffered receive and transmit units
NOTE: SCI/LIN module does not support UART hardware flow control. This feature can be
implemented in software using a general purpose I/O pin.
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26.1.2 LIN Features
The following are the features of the LIN module:
• Compatibility with LIN 1.3, 2.0 and 2.1protocols
• Configurable Baud Rate up to 20 Kbits/s
• Two external pins: LINRX and LINTX.
• Multi-buffered receive and transmit units
• Identification masks for message filtering
• Automatic master header generation
– Programmable synchronization break field
– Synchronization field
– Identifier field
• Slave automatic synchronization
– Synchronization break detection
– Optional baud rate update
– Synchronization validation
• 231 programmable transmission rates with 7 fractional bits
• Wakeup on LINRX dominant level from transceiver
• Automatic wakeup support
– Wakeup signal generation
– Expiration times on wakeup signals
• Automatic bus idle detection
• Error detection
– Bit error
– Bus error
– No-response error
– Checksum error
– Synchronization field error
– Parity error
• Capability to use Direct Memory Access (DMA) for transmit and receive data.
• 2 Interrupt lines with priority encoding for:
– Receive
– Transmit
– ID, error, and status
• Support for LIN 2.0 checksum
• Enhanced synchronizer finite state machine (FSM) support for frame processing
• Enhanced handling of extended frames
• Enhanced baud rate generator
• Update wakeup/go to sleep
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26.1.3 Block Diagram
The SCI/LIN module contains core SCI block with added sub-blocks to support LIN protocol.
Three Major components of the SCI Module are:
• Transmitter
• Baud Clock Generator
• Receiver
Transmitter (TX) contains two major registers to perform the double- buffering:
• The transmitter data buffer register (SCITD) contains data loaded by the CPU to be transferred to the
shift register for transmission.
• The transmitter shift register (SCITXSHF) loads data from the data buffer (SCITD) and shifts data onto
the LINTX pin, one bit at a time.
Baud Clock Generator
• A programmable baud generator produces either a baud clock scaled from VBUSP CLK.
Receiver (RX) contains two major registers to perform the double- buffering:
• The receiver shift register (SCIRXSHF) shifts data in from the LINRX pin one bit at a time and transfers
completed data into the receive data buffer.
• The receiver data buffer register (SCIRD) contains received data transferred from the receiver shift
register
The SCI receiver and transmitter are double-buffered, and each has its own separate enable and interrupt
bits. The receiver and transmitter may each be operated independently or simultaneously in full duplex
mode.
To ensure data integrity, the SCI checks the data it receives for breaks, parity, overrun, and framing
errors. The bit rate (baud) is programmable to over 16 million different rates through a 24-bit baud-select
register. Figure 26-1 shows the detailed SCI block diagram.
The SCI/LIN module is based on the standalone SCI with the addition of an error detector (parity
calculator, checksum calculator, and bit monitor), a mask filter, a synchronizer, and a multi-buffered
receiver and transmitter. The SCI interface, the DMA control subblocks and the baud generator are
modified as part of the hardware enhancements for LIN compatibility. Figure 26-2 shows the SCI/LIN
block diagram.
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Figure 26-1. Detailed SCI Block Diagram
TRANSMITTER
SCITXSHF
Shift register
Address bit†
LINTX
TX EMPTY
SCIFLR.11
1
TXWAKE
SCIFLR.10
VCLK
Peripheral
8
TXRDY
SCIFLR.8
Transmit buffer
SCITD
Baud clock
generator
TX INT ENA
SCISETINT.8
TX INT
TXENA
SCIGCR1.25
CLOCK
SCIGCR1.5
SCI
Baud rate
registers
SCIBAUD
RECEIVER
SCIRXSHF
Shift register
BRKDT
SCIFLR.0
RXENA
SCIGCR1.24
8
RXWAKE
SCIFLR.12
Receive buffer
SCIRD
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WAKEUP
SCIFLR.1
LINRX
BRKDT INT ENA
SCISETINT.0
ERR INT
WAKEUP INT ENA
SCISETINT.1
PE OE FE
SCIFLR24:26
RXRDY
SCIFLR.9
RX INT ENA
SCISETINT.9
RX INT
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Figure 26-2. SCI/LIN Block Diagram
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26.2 SCI Communication Formats
The SCI module can be configured to meet the requirements of many applications. Because
communication formats vary depending on the specific application, many attributes of the SCI/LIN are user
configurable. The list below describes these configuration options:
• SCI Frame format
• SCI Timing modes
• SCI Baud rate
• SCI Multiprocessor modes
26.2.1 SCI Frame Formats
The SCI uses a programmable frame format. All frames consist of the following:
• One start bit
• One to eight data bits
• Zero or one address bit
• Zero or one parity bit
• One or two stop bits
The frame format for both the transmitter and receiver is programmable through the bits in the SCIGCR1
register. Both receive and transmit data is in nonreturn to zero (NRZ) format, which means that the
transmit and receive lines are at logic high when idle. Each frame transmission begins with a start bit, in
which the transmitter pulls the SCI line low (logic low). Following the start bit, the frame data is sent and
received least significant bit first (LSB).
An address bit is present in each frame if the SCI is configured to be in address-bit mode but is not
present in any frame if the SCI is configured for idle-line mode. The format of frames with and without the
address bit is illustrated in Figure 26-3.
A parity bit is present in every frame when the PARITY ENA bit is set. The value of the parity bit depends
on the number of one bits in the frame and whether odd or even parity has been selected via the PARITY
ENA bit. Both examples in Figure 26-3 have parity enabled.
All frames include one stop bit, which is always a high level. This high level at the end of each frame is
used to indicate the end of a frame to ensure synchronization between communicating devices. Two stop
bits are transmitted if the STOP bit in SCIGCR1 register is set. The examples shown in Figure 26-3 use
one stop bit per frame.
Figure 26-3. Typical SCI Data Frame Formats
Idle-line mode
Start
0
(LSBit)
1
2
3
4
5
6
7
Parity
(MSBit)
6
7
(MSBit)
Stop
Address bit mode
Start
0
(LSBit)
1
2
3
4
5
Addr
Parity
Stop
Address bit
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26.2.2 SCI Timing Mode
The SCI can be configured to use asynchronous or isosynchronous timing using TIMING MODE bit in
SCIGCR1 register.
26.2.2.1 Asynchronous Timing Mode
The asynchronous timing mode uses only the receive and transmit data lines to interface with devices
using the standard universal asynchronous receiver- transmitter (UART) protocol.
In the asynchronous timing mode, each bit in a frame has a duration of 16 SCI baud clock periods. Each
bit therefore consists of 16 samples (one for each clock period). When the SCI is using asynchronous
mode, the baud rates of all communicating devices must match as closely as possible. Receive errors
result from devices communicating at different baud rates.
With the receiver in the asynchronous timing mode, the SCI detects a valid start bit if the first four samples
after a falling edge on the LINRX pin are of logic level 0. As soon as a falling edge is detected on LINRX,
the SCI assumes that a frame is being received and synchronizes itself to the bus.
To prevent interpreting noise as Start bit SCI expects LINRX line to be low for at least four contiguous SCI
baud clock periods to detect a valid start bit. The bus is considered idle if this condition is not met. When a
valid start bit is detected, the SCI determines the value of each bit by sampling the LINRX line value
during the seventh, eighth, and ninth SCI baud clock periods. A majority vote of these three samples is
used to determine the value stored in the SCI receiver shift register. By sampling in the middle of the bit,
the SCI reduces errors caused by propagation delays and rise and fall times and data line noises.
Figure 26-4 illustrates how the receiver samples a start bit and a data bit in asynchronous timing mode.
The transmitter transmits each bit for a duration of 16 SCI baud clock periods. During the first clock period
for a bit, the transmitter shifts the value of that bit onto the LINTX pin. The transmitter then holds the
current bit value on LINTX for 16 SCI baud clock periods.
Figure 26-4. Asynchronous Communication Bit Timing
Majority
vote
Falling edge
detected
1 2 3 4 5 6 7 8 9 10 11 1213 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 161 2 3 4 5
LINRX
Start bit
LSB of data
16 SCI baud clock periods/bit
26.2.2.2 Isosynchronous Timing Mode
In isosynchronous timing mode, each bit in a frame has a duration of exactly 1 baud clock period and
therefore consists of a single sample. With this timing configuration, the transmitter and receiver are
required to make use of the SCICLK pin to synchronize communication with other SCI. This mode is not
supported on this device because SCICLK pin is not available.
26.2.3 SCI Baud Rate
The SCI/LIN has an internally-generated serial clock determined by the peripheral VCLK and the
prescalers P and M in this register. The SCI uses the 24-bit integer prescaler P value of the BRS register
to select the required baud rates. The additional 4-bit fractional divider M refines the baud rate selection.
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In asynchronous timing mode, the SCI generates a baud clock according to the following formula:
VCLK Frequency
SCICLK Frequency = ---------------------------------------------------M
P + 1 + -----16
SCICLK Frequency
---------------------------------------------------------16
Asynchronous baud value =
For P = 0,
Asynchronous baud value =
VCLK Frequency
------------------------------------------------32
(41)
26.2.3.1 Superfractional Divider, SCI Asynchronous Mode
The superfractional divider is available in SCI asynchronous mode (idle-line and address-bit mode).
Building on the 4-bit fractional divider M (BRS[27:24]), the super fractional divider uses an additional 3-bit
modulating value, illustrated in Table 26-2. The bits with a 1 in the table will have an additional VCLK
period added to their Tbit. If the character length is more than 10, then the modulation table will be a rolledover version of the original table (Table 26-1), as shown in Table 26-2.
The baud rate will vary over a data field to average according to the BRS[30:28] value by a “d” fraction of
the peripheral internal clock: 0 16
20 --> 20
28 --> 28
44 --> 44
4
8 --> 8
10 --> 10
14 --> 14
22 --> 22
8
4 --> 4
5 --> 5
7 --> 7
11 --> 11
16
2 --> 2
2.5 --> 3
3.5 --> 4
5.5 --> 6
Example: For a 16-bit port and with data of 16-bit, the last transfer has to be padded with eight 0s. This
effectively results in a transfer of 48 bits instead of 40. However the whole transfer is completed in 3
RTPCLK cycles.
For a detailed description of the representation of the packet on the RTP port pins, please refer to
Section 31.2.5.
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31.2.2 Direct Data Mode (DDM)
In this mode, data is written directly by the CPU or other master to a dedicated capture register
(RTPDDMW). The data is then transferred from the capture register to the FIFO. In a different
configuration the module traces the data on read operations on the RAM directly into the FIFOs. In Direct
Data Mode, no information other than the actual data is transmitted. The address of the written data can
only be determined by the order of writes or reads by the CPU or other master. This mode is especially
useful if a block of data on consecutive addresses has to be transmitted.
The transfer size (8, 16, or 32 bit) is programmable, but cannot be dynamically changed. Data not
written/read in the correct transfer size will be truncated/extended. For example, if the transfer size is
programmed to 16 bits and a 32-bit write operation is performed, the data written to the FIFO will be 32-bit
wide, however only the upper 16 bits of the FIFO will be transmitted. If an 8-bit operation is performed, bits
8-15 of the FIFO will be indeterminate, so the upper 8 bits of the data transmitted are dependent on the
previous contents of the FIFO RAM.
When the module is configured in Direct Data Mode (TM_DDM = 1) to trace write operations (DDM_RW =
1) to the RTPDDMW register, the programming of the trace regions for all FIFOs will be ignored and data
tracing, when accessing the addresses defined by the regions, will not occur. If the module is configured in
read mode (DDM_RW = 0), and if the read access to a RAM block falls into a valid trace region, the data
will be traced into the corresponding FIFO for this RAM block. Since no address information is transmitted
in Direct Data Mode, the executing program has to make sure that one FIFO is completely empty
(RTPGSR), before new data is traced into the next FIFO.
NOTE: Direct Data Mode read operation is not supported on devices with a Cortex-R4 CPU, due to
the bus protocol of the TCM interface and certain performance enhancements (for example,
data packing) implemented in the core.
31.2.2.1 Packet Format in Direct Data Mode
In Direct Data Mode write or read operations, only the data written to the RTPDDMW register or the data
read from RAM, and therefore captured into the FIFO, will be transmitted. The packet length is
programmable (8, 16, or 32 bits). Figure 31-4 illustrates this format.
Figure 31-4. Packet Format in Direct Data Mode
8, 16, or 32 bit
WR_DATA[xx:0]
31.2.3 Trace Regions
To limit the amount of data to be trace, two trace regions per RAM or peripheral are implemented. These
can be programmed to specific start addresses and block sizes. Depending on the device configuration
(number of RAM blocks), not all regions might be implemented. Trace regions are used in Trace Mode for
read or write trace and in Direct Data Mode for read trace. In Direct Data Mode write configuration, the
data has to be written directly to RTPDDMW.
The RAM and peripherals start at fixed addresses in the devices memory map. With this the start address
of a region does not need to be specified with its full 32-bit address. For RAM regions, only the lower 18bit need to be programmed. The peripheral address frame covers a wider range and the start address
needs to be programmed with the lower 24-bit.
The trace regions do not support a programmable end address; however, a block size needs to be
specified for each region. The block size can be chosen from as low as 256 Bytes up to 256 kBytes
(128 kBytes for peripherals).
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31.2.3.1 Inverse Trace Regions
The RTP can be configured to trace accesses which fall into, or are made outside of the specified regions.
This can be accomplished by the INV_RGN bit. If this bit is 0, all access which are made inside a region
are traced. If the bit is 1, all accesses outside the region are traced. The INV_RGN bit affects all regions
of the RTP (see RTPGLBCTRL).
There are certain restrictions when using INV_RGN = 1:
• In this mode up to 2 regions can be excluded from tracing accesses to a particular RAM.
• Inverse trace regions with one or both regions of a RAM programmed with blocksize = 0 is not
supported. If only one address range should be excluded from the trace, either the address range has
to be covered by both regions (for example, excluding 1kB range with two 512B regions), or both
regions have to be programmed with the same start address and region size. If the whole RAM should
be traced, inverse region mode should not be used, instead the 2 regions could be programmed to
cover the entire address range with INV_RGN = 0.
• Both regions have to define the same access rights (bits CPU_DMA and RW; see Section 31.4.4) for
accesses outside of the region of each RAM block, otherwise the result is undefined.
• Peripheral trace in inverse region mode is not supported. The 16 MByte peripheral address range
cannot be covered entirely by the 17 bit address definition of the RTP protocol.
31.2.3.2 Overlapping Trace Regions
When in INV_RGN = 0 mode with both regions overlapping and an access is done into the overlapping
address range, both regions will be checked for their access rights and if one or both is satisfied, the
access will be traced. In the case that both regions would allow the data to be traced, there will still be
only one entry into the FIFO.
If accesses to peripherals are done within overlapping regions, the REG bit in the protocol will be 0,
denoting Region 1 (see Section 31.2.1.1).
Figure 31-5. Example for Trace Region Setup
4GB Address
Space
2 Trace Regions
• Region 1
– starts at 0x08001000 with size of 1kB
– CPU write access are traced
• Region 2
0x08003800
– starts at 0x08003800 with size of 2kB
– CPU and other master write accesses are traced
0x080013FF
0x08001000
RTPRAM1REG1 = 0x33001000
2kB
Region 2
1kB
Region 1
0x08000000
RTPRAM1REG2 = 0x74003800
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31.2.3.3 Cortex-R4 Specifics
Due to the bus system used on Cortex-R4, special considerations have to be taken into account.
Figure 31-1 shows the block diagram of the RTP connected to the Cortex-R4 RAM interface.
Both interfaces to RAM0 and RAM1 are 64-bit wide. RAM0 and RAM1 are building a consecutive address
range, where the 64-bit addresses 00, 10h, 20h, ... reside in RAM0 and 08h, 18h, 28h, ... reside in RAM1.
Considerations/Restrictions
• To trace a certain address range, the regions of both RAM0 (Section 31.4.4) and RAM1
(Section 31.4.5) need to be set up for the same start address and region size. Otherwise only every
other 64-bit access will be traced.
• Direct Data Mode read operation is not supported on Cortex-R4. This is because the CPU uses 64-bit
accesses for read operations even though the intended accesses is sub-64-bit wide. Since Direct Data
Mode only supports 32-bit data transfers and the Cortex-R4 RAM interface does not provide
information about which byte out of the 64-bit is accessed with the read operation, the RTP cannot
determine the correct data value.
• If the RAM is protected by ECC, only 64-bit write accesses can be traced. Every 64-bit word in the
RAM is protected by a corresponding 8-bit ECC checksum. When a sub-64-bit write access is
performed, the Cortex-R4 has to do a read-modify-write operation of the 64-bit word to be modified in
order to calculate the corresponding checksum and then write it back to memory. External hardware
can still determine which portion of the 64-bit word has been modified, since the other bytes in this
word did not change.
31.2.4 Overflow/Empty Handling
In case the application does RAM accesses faster than the FIFO can be emptied via the external pin
interface, the FIFO can overflow. The user can choose whether the program execution/data transfer
should be suspended, or an overflow should be signaled in the status bits of the next, to be transmitted,
message of this particular FIFO. If program execution is resumed, the data will be lost. The overflow will
not be signaled in the message that is already in the serializer and being transmitted when the overflow
occurs.
NOTE: The status information will only be transmitted in Trace Mode, since the Direct Data Mode
packet does not contain any status information.
When an overflow in a FIFO occurs, the corresponding bit in RTPGSR will be set.
Figure 31-6. FIFO Overflow Handling
overflow
CTRL
CTRL
00
CTRL
00
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31.2.5 Signal Description
RTPCLK
This clock signal is used to clock out the data of the serializer. Depending on the CONTCLK bit,
the clock can be suspended between packets or it can be free running. The RTPCLK frequency
can be adjusted by the PRESCALER bits (see Section 31.4.1).
RTPSYNC
The module provides a packet-sync signal. This signal will go high on the rising edge of RTPCLK
and will be valid for one RTPCLK cycle to synchronize external hardware to the data stream. The
RTPSYNC pulse will be generated for each new packet.
RTPENA
This signal is an input and can be used by external hardware to stop the data transmission
between packets. When the RTPENA signal goes high, the RTP will finish the current packet
transmission and then stop. Once the signal is pulled low again, the RTP will resume the transfer
if data is still present in the serializer or FIFOs. The RTPENA signal does not have to be used for
proper module operation. It can be used in GIO mode if the external hardware cannot generate
this signal. Overflows of the external system cannot be handled in this case.
RTPDATA[15:0]
These pins are used to do the actual data transfer. Data changes with the rising edge of RTPCLK.
The port can be configured for different widths (PW[1:0]). The minimum port width supported is 2
pins. See Table 31-9 which pins are used for the port.
Figure 31-7 shows an example of multiple packet transmissions in Trace Mode with an interruption
between packets because of RTPENA pulled high.
Figure 31-7. RTP Packet Transfer with Sync Signal
RTPENA
RTPCLK
RTPSYNC
RTPDATA
Packet1
Packet2
Packet4
Packet3
Packet1
Packet2
Figure 31-8 shows an example of a 4-bit data port with 8-bit write data (A5h) written into RAM1 (address
12345h) with no overflow in trace mode.
Figure 31-8. Packet Format in Trace Mode
RTPCLK
RTPSYNC
1786
RTPDATA[0]
DEST[1]
SIZE[1]
ADDR[15] ADDR[11]
ADDR[7]
ADDR[3]
DATA[7]
DATA[3]
RTPDATA[1]
DEST[0]
SIZE[0]
ADDR[14] ADDR[10]
ADDR[6]
ADDR[2]
DATA[6]
DATA[2]
RTPDATA[2]
STAT[1]
ADDR[17] ADDR[13] ADDR[9]
ADDR[5]
ADDR[1]
DATA[5]
DATA[1]
RTPDATA[3]
STAT[0]
ADDR[16] ADDR[12] ADDR[8]
ADDR[4]
ADDR[0]
DATA[4]
DATA[0]
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31.2.6 Data Rate
The module is configurable to support different RTPCLK frequencies. Please see the device datasheet for
the maximum supported frequency. HCLK will be prescaled to achieve the desired RTPCLK frequency.
The prescaler supports prescale values from 1 to 8 (Section 31.4.1).
The effective bandwidth depends on the configuration of the module and the average data width
transmitted in the packets.
31.3 GIO Function
Pins which are not used for RTP functionality can be used as normal GIO pins. If pins should be used in
functional mode or GIO mode, they can be programmed in RTPPC0. The direction of the pins can be
chosen in RTPPC1.
Module pins can have either an internal pullup or active pulldown that makes it possible to leave the pins
unconnected externally when configured as inputs. The pins can be programmed to have the active pull
capability by writing a 0 to the corresponding bit in the RTPPC7 register. Writing a 1 to the corresponding
bit disables the active pull functionality of the pin. A pull up can be configured by writing 1 to the
corresponding bit in the RTPPC8 register. Writing 0 will activate the pulldown capability. The
pullup/pulldown is deactivated when a bidirectional pin is configured as an output.
The GIO pin can be configured to include an open drain functionality when they are configured as output
pins. This is done by writing a 1 into the corresponding bit of the RTPPC6 register. When the open drain
functionality is enabled, a zero written to the data output register (RTPPC3) forces the pin to a low output
voltage (VOL or lower), whereas writing a 1 to the data output register (RTPPC3) forces the pin to a high
impedance state. The open drain functionality is disabled when the pin is configured as an input pin.
31.4 Control Registers
This section describes the RTP module registers. The registers support 8-bit, 16-bit, and 32-bit writes. The
base address of the RTP module registers is FFFF FA00h.
Table 31-6. RTP Module Registers
Offset
Acronym
Register Description
00h
RTPGLBCTRL
RTP Global Control Register
Section 31.4.1
Section
04h
RTPTRENA
RTP Trace Enable Register
Section 31.4.2
08h
RTPGSR
RTP Global Status Register
Section 31.4.3
0Ch, 10h
RTPRAM1REG
RTP RAM 1 Trace Region Register
Section 31.4.4
14h, 18h
RTPRAM2REG
RTP RAM 2 Trace Region Register
Section 31.4.5
24h, 28h
RTPPERREG
RTP Peripheral Trace Region Register
Section 31.4.6
2Ch
RTPDDMW
RTP Direct Data Mode Write Register
Section 31.4.7
34h
RTPPC0
RTP Pin Control 0 Register
Section 31.4.8
38h
RTPPC1
RTP Pin Control 1 Register
Section 31.4.9
3Ch
RTPPC2
RTP Pin Control 2 Register
Section 31.4.10
40h
RTPPC3
RTP Pin Control 3 Register
Section 31.4.11
44h
RTPPC4
RTP Pin Control 4 Register
Section 31.4.12
48h
RTPPC5
RTP Pin Control 5 Register
Section 31.4.13
4Ch
RTPPC6
RTP Pin Control 6 Register
Section 31.4.14
50h
RTPPC7
RTP Pin Control 7 Register
Section 31.4.15
54h
RTPPC8
RTP Pin Control 8 Register
Section 31.4.16
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31.4.1 RTP Global Control Register (RTPGLBCTRL)
The configuration of the module can be changed with this register. Figure 31-9 and Table 31-7 illustrate
this register.
Figure 31-9. RTP Global Control Register (RTPGLBCTRL) [offset = 00h]
31
25
24
Reserved
R-0
15
23
19
TEST
R/WP-0
14
13
12
18
16
Reserved
PRESCALER
R-0
R/WP-7h
11
10
Reserved
DDM_WIDTH
DDM_RW
TM_DDM
9
PW
R-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
7
6
5
4
RESET
CONTCLK
HOVF
INV_RGN
ON/OFF
R/WP-0
R/WP-0
R/WP-0
R/WP-0
R/WP-5h
8
3
0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 31-7. RTP Global Control Register (RTPGLBCTRL) Field Descriptions
Bit
31-25
24
Field
Reserved
Value
0
TEST
Description
Read returns 0. Writes have no effect.
By setting the bit, the FIFO RAM will be mapped into the SYSTEM Peripheral frame starting at
address FFF8 3000h. Each FIFO will start at a 1k boundary. Each FIFO entry will be aligned to
a 128 bit boundary. See Table 31-8 for a listing of the FIFOs and their corresponding
addresses.
User and privilege mode (read):
0
The FIFO RAM is not accessible in the memory map.
1
The FIFO RAM is mapped to address FFF8 3000h.
Privilege mode (write):
18-16
0
Disables mapping of the FIFO RAM.
1
Enables mapping of the FIFO RAM into address FFF8 3000h.
PRESCALER
The prescaler divides HCLK down to the desired RTPCLK frequency. The maximum RTPCLK
frequency specified in the device datasheet must not be exceeded. No dynamic change of
RTPCLK is supported. The module should be switched off by the ON/OFF bits in this register
before changing the prescaler.
User and privilege mode read, privilege mode write:
15-14
Reserved
13-12
DDM_WIDTH
0
The prescaler is HCLK/1.
1h
The prescaler is HCLK/2.
2h
The prescaler is HCLK/3.
3h
The prescaler is HCLK/4.
4h
The prescaler is HCLK/5.
5h
The prescaler is HCLK/6.
6h
The prescaler is HCLK/7.
7h
The prescaler is HCLK/8.
0
Read returns 0. Writes have no effect.
Direct data mode word size width. This bit field configures the number of bits that will be
transmitted in Direct Data Mode.
User and privilege mode read, privilege mode write:
1788
0
The word size width is 8 bits.
1h
The word size width is 16 bits.
2h
The word size width is 32 bits.
3h
Reserved
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Table 31-7. RTP Global Control Register (RTPGLBCTRL) Field Descriptions (continued)
Bit
Field
11
DDM_RW
Value
Description
Direct Data Mode
User and privilege mode (read):
0
Read tracing in Direct Data Mode is enabled.
1
Write tracing in Direct Data Mode to DDMW register is enabled.
Privilege mode (write):
10
0
Enable read tracing in Direct Data Mode. The RW bits in the RTPRAMxREGy registers to be
ignored.
1
Write tracing in Direct Data Mode to DDMW register is enabled. The RW bits in the
RTPRAMxREGy registers to be ignored (Section 31.4.4).
TM_DDM
Trace Mode or Direct Data Mode
User and privilege mode (read):
0
Module is configured in Trace Mode.
1
Module is configured in Direct Data Mode.
Privilege mode (write):
9-8
7
0
Configure module to Trace Mode.
1
Configure module to Direct Data Mode.
PW
Port width. This bit field configures the RTP to the desired port width. Pins that are not used for
functional mode can be used as GIO pins. See Table 31-9 for which pins are used for the port.
0
The RTP is 2 pins wide.
1h
The RTP is 4 pins wide.
2h
The RTP is 8 pins wide.
3h
The RTP is 16 pins wide.
RESET
This bit resets the state machine and the registers to their reset value. This reset ensures that
no data left in the FIFOs is shifted out after switching on the module with the ON/OFF bit.
User and privilege mode (read):
0
The RTP module is out of reset.
1
The RTP module is in reset.
Privilege mode (write):
6
0
Do not reset the module.
1
Reset the module.
CONTCLK
Continuous RTPCLK enable.
User and privilege mode (read):
0
The RTPCLK is stopped between transmissions.
1
The RTPCLK is free running.
Privilege mode (write):
5
0
Stop RTPCLK between transmissions.
1
Configure RTPCLK as free running.
HOVF
Halt on overflow. This bit indicates whether the CPU or DMA is halted while only one location in
the FIFO is empty in Trace Mode or Direct Data Mode (read).
User and privilege mode (read):
0
The current data transfer to the FIFO will not be suspended in case of a full FIFO.
1
The current data transfer to the FIFO will be suspended in case of a full FIFO.
Privilege mode (write):
0
The halt on FIFO overflow will be disabled. The data transfer will not be suspended and will be
discarded. Data written to the RTPDDMW register will overwrite the RTPDDMW register.
1
The halt on FIFO overflow will be enabled. Data written to the already full FIFO will be written
once the FIFO is emptied again. The data transfer to the FIFO will be suspended and signaled
to the CPU or other master while there is still data to be shifted out. When there is an empty
FIFO location again, the transfer of the data to the FIFO will be finished.
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Table 31-7. RTP Global Control Register (RTPGLBCTRL) Field Descriptions (continued)
Bit
4
Field
Value
Description
INV_RGN
Trace inside or outside of defined trace regions.
User and privilege mode (read):
0
Accesses inside the trace regions are traced.
1
Accesses outside the trace regions are traced.
Privilege mode (write):
3-0
0
Allow tracing of accesses inside the regions set in RTPRAMxREGy
1
Allow tracing of accesses outside the regions set in RTPRAMxREGy (Section 31.4.4)
ON/OFF
ON/Off switch.
User and privilege mode (read):
Ah
Tracing of data is enabled.
All Others
Tracing of data is disabled.
Privilege mode (write):
Ah
Enable Tracing of data. If there is any previous captured data remaining, it will be shifted out.
All Others
Disable tracing of data. If there is still data left in the shift register, it will be shifted out before
disabling the shift operations. The data captured in the FIFO remains there until the ON/OFF
bits are set to Ah.
NOTE: It is recommended to write 5h to disable the module to prevent a soft error from
enabling the module inadvertently by a single bit flip.
Table 31-8. FIFO Corresponding Addresses
FIFO
Address
1
FFF8 3000h
2
FFF8 3400h
4
FFF8 3C00h
Table 31-9. Pins Used for Data Communication
1790
Port Width (PW)
Pins Used
00
RTPDATA[1:0]
01
RTPDATA[3:0]
10
RTPDATA[7:0]
11
RTPDATA[15:0]
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31.4.2 RTP Trace Enable Register (RTPTRENA)
This register enables/disables tracing of the different RAM blocks or the peripherals individually.
Figure 31-10 and Table 31-10 illustrate this register.
Figure 31-10. RTP Trace Enable Register (RTPTRENA) [offset = 04h]
31
25
24
23
22
16
Reserved
ENA4
Reserved
R-0
R/WP-0
R-0
15
9
8
7
1
0
Reserved
ENA2
Reserved
ENA1
R-0
R/WP-0
R-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 31-10. RTP Trace Enable Register (RTPTRENA) Field Descriptions
Bit
31-25
24
Field
Reserved
Value
0
ENA4
Description
Read returns 0. Writes have no effect.
Enable tracing for peripherals. This bit enables tracing into FIFO4 in trace mode (read/write) or direct
data mode (read) operations. In Direct Data Mode write operations, this bit will be ignored and tracing
into FIFO4 will be disabled.
User and privilege mode (read):
0
Tracing is disabled.
1
Tracing is enabled.
Privilege mode (write):
23-9
8
Reserved
0
Disable tracing. If RTPGLBCTRL.ON/OFF = Ah, data already captured in FIFO4 will still be transmitted
(Section 31.4.1).
1
Enable tracing.
0
Read returns 0. Writes have no effect.
ENA2
Enable tracing for RAM block 2. This bit enables tracing into FIFO2 in Trace Mode (read/write) or Direct
Data Mode (read) operations. In Direct Data Mode write operations, this bit will be ignored and tracing
into FIFO2 will be disabled.
User and privilege mode (read):
0
Tracing is disabled.
1
Tracing is enabled.
Privilege mode (write):
7-1
0
Reserved
0
Disable tracing. If RTPGLBCTRL.ON/OFF = Ah, data already captured in FIFO2 will still be transmitted.
1
Enable tracing.
0
Read returns 0. Writes have no effect.
ENA1
Enable tracing for RAM block 1. This bit enables tracing into FIFO1 in Trace Mode (read/write) or Direct
Data Mode (read) operations. In Direct Data Mode write operations, this bit will be ignored and tracing
into FIFO1 will be disabled.
User and privilege mode (read):
0
Tracing is disabled.
1
Tracing is enabled.
Privilege mode (write):
0
Disable tracing. If RTPGLBCTRL.ON/OFF = Ah, data already captured in FIFO1 will still be transmitted.
1
Enable tracing.
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31.4.3 RTP Global Status Register (RTPGSR)
This register provides status information of the module. Figure 31-11 and Table 31-11 illustrate this
register.
Figure 31-11. RTP Global Status Register (RTPGSR) [offset = 08h]
31
16
Reserved
R-0
15
12
11
10
9
8
Reserved
13
EMPTYSER
EMPTYPER
Reserved
EMPTY2
EMPTY1
R-0
R-1
R-1
R-0
R-1
R-1
7
3
2
1
0
Reserved
4
OVFPER
Reserved
OVF2
OVF1
R-0
R/W1CP-0
R-0
R/W1CP-0
R/W1CP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 31-11. RTP Global Status Register (RTPGSR) [offset = 08h] Field Descriptions
Bit
31-13
12
11
Field
Reserved
0
EMPTYSER
Reserved
9
EMPTY2
Reserved
3
OVFPER
Read returns 0. Writes have no effect.
0
Serializer holds data that is shifted out.
1
Serializer is empty.
Peripheral FIFO empty. This bit determines if there are entries left in the FIFO.
0
FIFO4 contains entries.
1
FIFO4 is empty.
0
Read returns 0. Writes have no effect.
RAM block 2 FIFO empty. This bit determines if there are entries left in the FIFO.
0
FIFO2 contains entries.
1
FIFO2 is empty.
EMPTY1
7-4
Description
Serializer empty. This bit determines if there is data left in the serializer.
EMPTYPER
10
8
Value
RAM block 1 FIFO empty. This bit determines if there are entries left in the FIFO.
0
FIFO1 contains entries.
1
FIFO1 is empty.
0
Read returns 0. Writes have no effect.
Overflow peripheral FIFO. This flag indicates that FIFO4 had all locations full and another attempt to
write data to it occurred. The bit will not be cleared automatically if the FIFO is emptied again. The bit
will stay set until the CPU clears it.
User and privilege mode (read):
0
No overflow occurred.
1
An overflow occurred.
Privilege mode (write):
2
1792
Reserved
0
Writing a zero to this bit has no effect.
1
The bit is cleared.
0
Read returns 0. Writes have no effect.
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Table 31-11. RTP Global Status Register (RTPGSR) [offset = 08h] Field Descriptions (continued)
Bit
Field
1
OVF2
Value
Description
Overflow RAM block 2 FIFO. This flag indicates that FIFO2 had all locations full and another attempt
to write data to it occurred. The bit will not be cleared automatically if the FIFO is emptied again. The bit
will stay set until the CPU clears it.
User and privilege mode (read):
0
No overflow occurred.
1
An overflow occurred.
Privilege mode (write):
0
0
Writing a zero to this bit has no effect.
1
The bit is cleared.
OVF1
Overflow RAM block 1 FIFO. This flag indicates that FIFO1 had all locations full and another attempt
to write data to it occurred. The bit will not be cleared automatically if the FIFO is emptied again. The bit
will stay set until the CPU clears it.
User and privilege mode (read):
0
No overflow occurred.
1
An overflow occurred.
Privilege mode (write):
0
Writing a zero to this bit has no effect.
1
The bit is cleared.
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31.4.4 RTP RAM 1 Trace Region [1:2] Register (RTPRAM1REG[1:2])
Figure 31-12 and Table 31-12 illustrate these registers.
Figure 31-12. RTP RAM 1 Trace Region [1:2] Register (RTPRAM1REG[1:2]) [offset = 0Ch, 10h]
31
30
29
28
27
24
23
18
17
16
Rsvd
CPU_DMA
RW
BLOCKSIZE
Reserved
STARTADDR
R-0
R/WP-0
R/WP-0
R/WP-0
R-0
R/WP-0
15
0
STARTADDR
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 31-12. RTP RAM 1 Trace Region [1:2] Register (RTPRAM1REG[1:2]) Field Descriptions
Bit
Field
31
Reserved
30-29
Value
0
CPU_DMA
Description
Read returns 0. Writes have no effect.
CPU and/or other master access. This bit field indicates if read or write operations are traced
either coming from the CPU and/or from the other master.
User and privilege mode read, privilege mode write:
28
0
Read or write operations are traced when coming from the CPU and the other master.
1h
Read or write operations are traced only when coming from the CPU.
2h
Read or write operations are traced only when coming from the other master.
3h
Reserved
RW
Read/Write. This bit indicates if read or write operations are traced in Trace Mode or Direct
Data Mode (read operation). If configured for write in Direct Data Mode (RTPGLBCTRL), the
data captured will be discarded. A write operation in Direct Data Mode has to be directly to the
RTPDDMW register instead of to RAM. Depending on the INV_RGN bit setting, accesses into
or outside the region will be traced.
User and privilege mode (read):
0
Read operations will be captured.
1
Write operations will be captured.
Privilege mode (write):
27-24
0
Trace read accesses.
1
Trace write accesses.
BLOCKSIZE
These bits define the length of the trace region. Depending on the setting of INV_RGN
(Section 31.4.1), accesses inside or outside the region defined by the start address and
blocksize will be traced. If all bits of BLOCKSIZE are 0, the region is disabled and no data will
be captured.
Region size (in bytes):
0
0
1h
256
2h
512
3h
1K
4h
2K
Ah
128K
Bh
256K
Ch-Fh
23-18
Reserved
17-0
STARTADDR
1794
0
0-3 FFFFh
Reserved
Read returns 0. Writes have no effect.
These bits define the starting address of the address region that should be traced. The start
address has to be a multiple of the block size chosen. If the start address is not a multiple of
the block size, the start of the region will begin at the next lower block size boundary.
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31.4.5 RTP RAM 2 Trace Region [1:2] Register (RTPRAM2REG[1:2])
Figure 31-13 and Table 31-13 illustrate these registers.
Figure 31-13. RTP RAM 2 Trace Region [1:2] Register (RTPRAM2REG[1:2]) [offset = 14h, 18h]
31
30
29
28
27
24
23
18
17
16
Rsvd
CPU_DMA
RW
BLOCKSIZE
Reserved
STARTADDR
R-0
R/WP-0
R/WP-0
R/WP-0
R-0
R/WP-0
15
0
STARTADDR
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 31-13. RTP RAM 2 Trace Region [1:2] Register (RTPRAM2REG[1:2]) Field Descriptions
Bit
Field
31
Reserved
30-29
Value
0
CPU_DMA
Description
Read returns 0. Writes have no effect.
CPU and/or other master access. This bit field indicates if read or write operations are traced
either coming from the CPU and/or from the other master.
User and privilege mode read, privilege mode write:
28
0
Read or write operations are traced when coming from the CPU and the other master.
1h
Read or write operations are traced only when coming from the CPU.
2h
Read or write operations are traced only when coming from the other master.
3h
Reserved
RW
Read/Write. This bit indicates if read or write operations are traced in Trace Mode or Direct
Data Mode (read operation). If configured for write in Direct Data Mode (RTPGLBCTRL), the
data captured will be discarded. A write operation in Direct Data Mode has to be directly to the
RTPDDMW register instead of to RAM. Depending on the INV_RGN bit setting, accesses into
or outside the region will be traced.
User and privilege mode (read):
0
Read operations will be captured.
1
Write operations will be captured.
Privilege mode (write):
27-24
0
Trace read accesses.
1
Trace write accesses.
BLOCKSIZE
These bits define the length of the trace region. Depending on the setting of INV_RGN
(Section 31.4.1), accesses inside or outside the region defined by the start address and
blocksize will be traced. If all bits of BLOCKSIZE are 0, the region is disabled and no data will
be captured.
Region size (in bytes):
0
0
1h
256
2h
512
3h
1K
4h
2K
Ah
128K
Bh
256K
Ch-Fh
23-18
Reserved
17-0
STARTADDR
0
0-3 FFFFh
Reserved
Read returns 0. Writes have no effect.
These bits define the starting address of the address region that should be traced. The start
address has to be a multiple of the block size chosen. If the start address is not a multiple of
the block size, the start of the region will begin at the next lower block size boundary.
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31.4.6 RTP Peripheral Trace Region [1:2] Registers (RTPPERREG[1:2])
FIFO4 is dedicated for tracing the peripheral accesses. Since the peripheral frame is 16 Mbytes, the start
address has to be defined as a 24-bit value. However, only bits 16 to 0 will be transmitted in the protocol.
Bit REG (Section 31.2.1.1) in the protocol will be 0 if there was an access to the range defined by
RTPPERREG1. REG will be 1 if the access was into the range defined by RTPPERREG2. Figure 31-14
and Table 31-14 illustrate these registers.
Figure 31-14. RTP Peripheral Trace Region [1:2] Register (RTPPERREG[1:2]) [offset = 24h, 28h]
31
30
29
28
27
24
23
16
Rsvd
CPU_DMA
RW
BLOCKSIZE
STARTADDR
R-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
15
0
STARTADDR
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 31-14. RTP Peripheral Trace Region [1:2] Register (RTPPERREG[1:2]) Field Descriptions
Bit
Field
31
Reserved
30-29
Value
0
CPU_DMA
Description
Read returns 0. Writes have no effect.
CPU and/or other master access. This bit field indicates if read or write operations are traced
either coming from the CPU and/or from the other master.
User and privilege mode read, privilege mode write:
28
0
Read or write operations are traced when coming from the CPU and the other master.
1h
Read or write operations are traced only when coming from the CPU.
2h
Read or write operations are traced only when coming from the other master.
3h
Reserved
RW
Read/Write. This bit indicates if read or write operations are traced in Trace Mode or Direct
Data Mode (read operation). If configured for write in Direct Data Mode (RTPGLBCTRL), the
data captured will be discarded. A write operation in Direct Data Mode has to be directly to the
RTPDDMW register instead of to RAM. Depending on the INV_RGN bit setting, accesses into
or outside the region will be traced.
User and privilege mode (read):
0
Read operations will be captured.
1
Write operations will be captured.
Privilege mode (write):
27-24
0
Trace read accesses.
1
Trace write accesses.
BLOCKSIZE
These bits define the length of the trace region. Depending on the setting of INV_RGN
(Section 31.4.1), accesses inside or outside the region defined by the start address and
blocksize will be traced. If all bits of BLOCKSIZE are 0, the region is disabled and no data will
be captured.
Region size (in bytes):
0
0
1h
256
2h
512
3h
1K
4h
2K
Ah
128K
Bh
256K
Ch-Fh
23-0
1796
STARTADDR
Reserved
0-FF FFFFh These bits define the starting address of the address region that should be traced. The start
address has to be a multiple of the block size chosen. If the start address is not a multiple of
the block size, the start of the region will begin at the next lower block size boundary.
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31.4.7 RTP Direct Data Mode Write Register (RTPDDMW)
The CPU has to write data to this register if the module is used in Direct Data Mode write configuration.
Figure 31-15 and Table 31-15 illustrate this register.
Figure 31-15. RTP Direct Data Mode Write Register (RTPDDMW) [offset = 2Ch]
31
16
DATA
R/W-0
15
0
DATA
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 31-15. RTP Direct Data Mode Write Register (RTPDDMW) Field Descriptions
Bit
Field
Value
31-0
DATA
0-FFFF FFFFh
Description
This register must be written to in a Direct Data Mode write operation to store the data into
FIFO1. Data written must be right-aligned. If the FIFO is full, the reaction depends on the
setting of the HOVF bit (Section 31.4.1). If the bit is set, the master writing the data will be waitstated. If the bit is cleared, previous data written to the register will be overwritten.
Reads of this register always return 0.
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31.4.8 RTP Pin Control 0 Register (RTPPC0)
This register configures the RTP pins as functional or GIO pins. Once the pin is configured in functional
mode, it overrides the settings in the RTPPC1 register. Writing to RTPPC3, RTPPC4 and RTPPC5 will
have no effect for pins configured as functional pins. Figure 31-16 and Table 31-16 illustrate this register.
Figure 31-16. RTP Pin Control 0 Register (RTPPC0) [offset = 34h]
31
18
17
16
Reserved
19
ENAFUNC
CLKFUNC
SYNCFUNC
R-0
R/W-0
R/W-0
R/W-0
15
0
DATAFUNC[15:0]
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 31-16. RTP Pin Control 0 Register (RTPPC0) Field Descriptions
Bit
Field
31-19
Reserved
18
ENAFUNC
Value
0
Description
Read returns 0. Writes have no effect.
Functional mode of RTPENA pin.
User and privilege mode (read):
0
Pin is used in GIO mode.
1
Pin is used in functional mode.
User and privilege mode (write):
17
0
Configure pin to GIO mode.
1
Configure pin to functional mode.
CLKFUNC
Functional mode of RTPCLK pin.
User and privilege mode (read):
0
Pin is used in GIO mode.
1
Pin is used in functional mode.
User and privilege mode (write):
16
0
Configure pin to GIO mode.
1
Configure pin to functional mode.
SYNCFUNC
Functional mode of RTPSYNC pin.
User and privilege mode (read):
0
Pin is used in GIO mode.
1
Pin is used in functional mode.
User and privilege mode (write):
15-0
0
Configure pin to GIO mode.
1
Configure pin to functional mode.
DATAFUNC[n]
Functional mode of RTPDATA[15:0] pins. These bits define whether the pins are used in
functional mode or in GIO mode. Each bit [n] represents a single pin.
User and privilege mode (read):
0
Pin is used in GIO mode.
1
Pin is used in functional mode.
User and privilege mode (write):
1798
0
Configure pin to GIO mode.
1
Configure pin to functional mode.
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31.4.9 RTP Pin Control 1 Register (RTPPC1)
Once the pin is configured in functional mode (RTPPC0, Section 31.4.8), configuring the corresponding bit
in RTPPC1 to 0 will not disable the output driver. Figure 31-17 and Table 31-17 illustrate this register.
Figure 31-17. RTP Pin Control 1 Register (RTPPC1) [offset = 38h]
31
18
17
16
Reserved
19
ENADIR
CLKDIR
SYNCDIR
R-0
R/W-0
R/W-0
R/W-0
15
0
DATADIR[15:0]
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 31-17. RTP Pin Control 1 Register (RTPPC1) Field Descriptions
Bit
Field
31-19
Reserved
18
ENADIR
Value
0
Description
Read returns 0. Writes have no effect.
Direction of RTPENA pin. This bit defines whether the pin is used as input or output in GIO mode.
This bit has no effect when the pin is configured in functional mode.
User and privilege mode (read):
0
Pin is used as input.
1
Pin is used as output.
User and privilege mode (write):
17
0
Configure pin to input mode.
1
Configure pin to output mode.
CLKDIR
Direction of RTPCLK pin. This bit defines whether the pin is used as input or output in GIO mode. This
bit has no effect when the pin is configured in functional mode.
User and privilege mode (read):
0
Pin is used as input.
1
Pin is used as output.
User and privilege mode (write):
16
0
Configure pin to input mode.
1
Configure pin to output mode.
SYNCDIR
Direction of RTPSYNC pin. This bit defines whether the pin is used as input or output in GIO mode.
This bit has no effect when the pin is configured in functional mode.
User and privilege mode (read):
0
Pin is used as input.
1
Pin is used as output.
User and privilege mode (write):
15-0
0
Configure pin to input mode.
1
Configure pin to output mode.
DATADIR[n]
Direction of RTPDATA[15:0] pins. These bits define whether the pins are used as input or output in
GIO mode. These bits have no effect when the pins are configured in functional mode. Each bit [n]
represents a single pin.
User and privilege mode (read):
0
Pin is used as input.
1
Pin is used as output.
User and privilege mode (write):
0
Configure pin to input mode.
1
Configure pin to output mode.
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31.4.10 RTP Pin Control 2 Register (RTPPC2)
This register represents the input value of the pins if when in GIO or functional mode. Figure 31-18 and
Table 31-18 illustrate this register.
Figure 31-18. RTP Pin Control 2 Register (RTPPC2) [offset = 3Ch]
31
18
17
16
Reserved
19
ENAIN
CLKIN
SYNCIN
R-0
R-x
R-x
R-x
15
0
DATAIN[15:0]
R-x
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 31-18. RTP Pin Control 2 Register (RTPPC2) Field Descriptions
Bit
31-19
18
Field
Reserved
Value
0
ENAIN
Description
Read returns 0. Writes have no effect.
RTPENA input. This bit reflects the state of the pin in all modes. Writes to this bit have no effect.
User and privilege mode (read):
17
0
The pin is at logic low (0) (input voltage is V IL or lower).
1
The pin is at logic high (1) (input voltage is V IH or higher).
CLKIN
RTPCLK input. This bit reflects the state of the pin in all modes. Writes to this bit have no effect.
User and privilege mode (read):
16
0
The pin is at logic low (0) (input voltage is V
1
The pin is at logic high (1) (input voltage is V IH or higher).
SYNCIN
IL
or lower).
RTPSYNC input. This bit reflects the state of the pin in all modes. Writes to this bit have no effect.
User and privilege mode (read):
15-0
0
The pin is at logic low (0) (input voltage is V
1
The pin is at logic high (1) (input voltage is V IH or higher).
DATAIN[n]
IL
or lower).
RTPDATA[15:0] input. These bits reflect the state of the pins in all modes. Each bit [n] represents a
single pin. Writes to this bit have no effect.
User and privilege mode (read):
1800
0
The pin is at logic low (0) (input voltage is V
1
The pin is at logic high (1) (input voltage is V IH or higher).
IL
or lower).
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31.4.11 RTP Pin Control 3 Register (RTPPC3)
The bits in this register define the state of the pins when configured in GIO mode as output pins. Once a
pin is configured in functional mode (RTPPC0), changing the state of the corresponding bit in RTPPC3 will
not affect the pin's state. Figure 31-19 and Table 31-19 illustrate this register.
Figure 31-19. RTP Pin Control 3 Register (RTPPC3) [offset = 40h]
31
18
17
16
Reserved
19
ENAOUT
CLKOUT
SYNCOUT
R-0
R/W-0
R/W-0
R/W-0
15
0
DATAOUT[15:0]
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 31-19. RTP Pin Control 3 Register (RTPPC3) Field Descriptions
Bit
Field
31-19
Reserved
18
ENAOUT
Value
0
Description
Read returns 0. Writes have no effect.
RTPENA output. This pin sets the output state of the RTPENA pin.
User and privilege mode (read):
0
The pin is configured to output logic low (0) (output voltage is V OL or lower).
1
The pin is configured to output logic high (1) (output voltage is V
OH
or higher).
User and privilege mode (write):
17
0
Set pin to logic low (0) (output voltage is V OL or lower).
1
Set pin to logic high (1) (output voltage is V
CLKOUT
OH
or higher).
RTPCLK output. This pin sets the output state of the RTPCLK pin.
User and privilege mode (read):
0
The pin is configured to output logic low (0) (output voltage is V OL or lower).
1
The pin is configured to output logic high (1) (output voltage is V
OH
or higher).
User and privilege mode (write):
16
0
Set pin to logic low (0) (output voltage is V OL or lower).
1
Set pin to logic high (1) (output voltage is V
SYNCOUT
OH
or higher).
RTPSYNC output. This pin sets the output state of the RTPSYNC pin.
User and privilege mode (read):
0
The pin is configured to output logic low (0) (output voltage is V
1
The pin is configured to output logic high (1) (output voltage is V OH or higher).
OL
or lower).
User and privilege mode (write):
15-0
0
Set pin to logic low (0) (output voltage is V OL or lower).
1
Set pin to logic high (1) (output voltage is V
DATAOUT[n]
OH
or higher).
RTPDATA[15:0] output. These bits set the output state of the RTPDATA[15:0] pins. Each bit [n]
represents a single pin.
User and privilege mode (read):
0
The pin is configured to output logic low (0) (output voltage is V
1
The pin is configured to output logic high (1) (output voltage is V
OL
or lower).
OH
or higher).
User and privilege mode (write):
0
Set pin to logic low (0) (output voltage is V OL or lower).
1
Set pin to logic high (1) (output voltage is V
OH
or higher).
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31.4.12 RTP Pin Control 4 Register (RTPPC4)
This register provides the option to set pins to a logic 1 level without influencing the state of other pins. It
eliminates the read-modify-write operation necessary with RTPPC3. Once the pin is configured in
functional mode (RTPPC0), setting the corresponding bit to one in RTPPC4 will not affect the pin's state.
Figure 31-20 and Table 31-20 illustrate this register.
Figure 31-20. RTP Pin Control 4 Register (RTPPC4) [offset = 44h]
31
18
17
16
Reserved
19
ENASET
CLKSET
SYNCSET
R-0
R/W-0
R/W-0
R/W-0
15
0
DATASET[15:0]
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 31-20. RTP Pin Control 4 Register (RTPPC4) Field Descriptions
Bit
Field
31-19
Reserved
18
ENASET
Value
0
Description
Read returns 0. Writes have no effect.
Sets the output state of RTPENA pin to logic high. Value in the ENASET bit sets the data output
control register bit to 1, regardless of the current value in the ENAOUT bit .
User and privilege mode (read):
0
The pin is configured to output a logic low (0) (output voltage is V OL or lower).
1
The pin is configured to output logic high (1) (output voltage is V
OH
or higher).
User and privilege mode (write):
17
0
Writing a zero to this bit has no effect.
1
Set pin to logic high (1) (output voltage is V
CLKSET
OH
or higher).
Sets the output state of RTPCLK pin to logic high. Value in the CLKSET bit sets the data output
control register bit to 1, regardless of the current value in the CLKOUT bit.
User and privilege mode (read):
0
The pin is configured to output a logic low (0) (output voltage is V OL or lower).
1
The pin is configured to output logic high (1) (output voltage is V
OH
or higher).
User and privilege mode (write):
16
0
Writing a zero to this bit has no effect.
1
Set pin to logic high (1) (output voltage is V
SYNCSET
OH
or higher).
Sets output state of RTPSYNC pin logic high. Value in the SYNCSET bit sets the data output control
register bit to 1, regardless of the current value in the SYNCOUT bit.
User and privilege mode (read):
0
The pin is configured to output a logic low (0) (output voltage is V OL or lower).
1
The pin is configured to output logic high (1) (output voltage is V
OH
or higher).
User and privilege mode (write):
15-0
0
Writing a zero to this bit has no effect.
1
Set pin to logic high (1) (output voltage is V
DATASET[n]
OH
or higher).
Sets output state of RTPDATA[15:0] pins to logic high. Value in the DATAxSET bit sets the data
output control register bit to 1, regardless of the current value in the DATAxOUT bit. Each bit [n]
represents a single pin.
User and privilege mode (read):
0
The pin is configured to output a logic low (0) (output voltage is V OL or lower).
1
The pin is configured to output logic high (1) (output voltage is V
OH
or higher).
User and privilege mode (write):
1802
0
Writing a zero to this bit has no effect.
1
Set pin to logic high (1) (output voltage is V
OH
or higher).
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31.4.13 RTP Pin Control 5 Register (RTPPC5)
This register provides the option to set pins to a logic 0 level without influencing the state of other pins. It
eliminates the read-modify-write operation necessary with RTPPC3. Once the pin is configured in
functional mode (RTPPC0), setting the corresponding bit to one in RTPPC5 will not affect the pinstate.
Figure 31-21 and Table 31-21 illustrate this register.
Figure 31-21. RTP Pin Control 5 Register (RTPPC5) [offset = 48h]
31
18
17
16
Reserved
19
ENACLR
CLKCLR
SYNCCLR
R-0
R/W-0
R/W-0
R/W-0
15
0
DATACLR[15:0]
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 31-21. RTP Pin Control 5 Register (RTPPC5) Field Descriptions
Bit
Field
31-19
Reserved
18
ENACLR
Value
0
Description
Read returns 0. Writes have no effect.
Sets the output state of RTPENA pin to logic low. Value in the ENASET bit sets the data output
control register bit to 0, regardless of the current value in the ENAOUT bit .
User and privilege mode (read):
0
The pin is configured to output a logic low (0) (output voltage is V OL or lower).
1
The pin is configured to output logic high (1) (output voltage is V
OH
or higher).
User and privilege mode (write):
17
0
Writing a zero to this bit has no effect.
1
Set pin to logic low (0) (output voltage is V OL or lower).
CLKCLR
Sets output state of RTPCLK pin to logic low. Value in the CLKCLR bit sets the data output control
register bit to 0, regardless of the current value in the CLKOUT bit
User and privilege mode (read):
0
The pin is configured to output a logic low (0) (output voltage is V OL or lower).
1
The pin is configured to output logic high (1) (output voltage is V
OH
or higher).
User and privilege mode (write):
16
0
Writing a zero to this bit has no effect.
1
Set pin to logic low (0) (output voltage is V OL or lower).
SYNCCLR
Sets output state of RTPSYNC pin logic low. Value in the SYNCCLR bit clears the data output
control register bit to 0, regardless of the current value in the SYNCOUT bit.
User and privilege mode (read):
0
The pin is configured to output a logic low (0) (output voltage is V OL or lower).
1
The pin is configured to output logic high (1) (output voltage is V
OH
or higher).
User and privilege mode (write):
15-0
0
Writing a zero to this bit has no effect.
1
Set pin to logic low (0) (output voltage is V OL or lower).
DATACLR[n]
Sets output state of RTPDATA[15:0] pins to logic low. Value in the DATAxCLR bit clears the data
output control register bit to 0, regardless of the current value in the DATAxOUT bit. Each bit [n]
represents a single pin.
User and privilege mode (read):
0
The pin is configured to output a logic low (0) (output voltage is V OL or lower).
1
The pin is configured to output logic high (1) (output voltage is V
OH
or higher).
User and privilege mode (write):
0
Writing a zero to this bit has no effect.
1
Set pin to logic low (0) (output voltage is V OL or lower).
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31.4.14 RTP Pin Control 6 Register (RTPPC6)
These bits configure the pins in push-pull or open-drain functionality. If configured to be open-drain, the
module only drives a logic low level on the pin. An external pull-up resistor needs to be connected to the
pin to pull it high when the pin is in high-impedance mode. Figure 31-22 and Table 31-22 illustrate this
register.
Figure 31-22. RTP Pin Control 6 Register (RTPPC6) [offset = 4Ch]
31
18
17
16
Reserved
19
ENAPDR
CLKPDR
SYNCPDR
R-0
R/W-0
R/W-0
R/W-0
15
0
DATAPDR[15:0]
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 31-22. RTP Pin Control 6 Register (RTPPC6) Field Descriptions
Bit
Field
31-19
Reserved
18
ENAPDR
Value
0
Description
Read returns 0. Writes have no effect.
RTPENA Open drain enable. This bit enables open-drain functionality on the pin if it is configured as
GIO output (RTPPC0[18]=0; RTPPC1[18]=1). If the pin is configured as a functional pin
(RTPPC0[18]=1), the open-drain functionality is disabled.
User and privilege mode (read):
0
Pin behaves as normal push/pull pin.
1
Pin operates in open drain mode.
User and privilege mode (write):
17
0
Configures the pin as push/pull.
1
Configures the pin as open drain.
CLKPDR
RTPCLK Open drain enable. This bit enables open-drain functionality on the pin if it is configured as
GIO output (RTPPC0[17]=0; RTPPC1[17]=1). If the pin is configured as functional pin (RTPPC0[17]=1),
the open-drain functionality is disabled.
User and privilege mode (read):
0
Pin behaves as normal push/pull pin.
1
Pin operates in open drain mode.
User and privilege mode (write):
16
0
Configures the pin as push/pull.
1
Configures the pin as open drain.
SYNCPDR
RTPSYNC Open drain enable. This bit enables open-drain functionality on the pin if it is configured as
GIO output (RTPPC0[16]=0; RTPPC1[16]=1). If pin is configured as functional pin (RTPPC0[16]=1), the
open-drain functionality is disabled.
User and privilege mode (read):
0
Pin behaves as normal push/pull pin.
1
Pin operates in open drain mode.
User and privilege mode (write):
1804
0
Configures the pin as push/pull.
1
Configures the pin as open drain.
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Table 31-22. RTP Pin Control 6 Register (RTPPC6) Field Descriptions (continued)
Bit
15-0
Field
Value
DATAPDR[n]
Description
RTPDATA[15:0] Open drain enable. These bits enable open-drain functionality on the pins, if they are
configured as GIO output (RTPPC0[15:0]=0; RTPPC1[15:0]=1). If the pins are configured as functional
pins (RTPPC0[15:0]=1), the open-drain functionality is disabled. Each bit [n] represents a single pin.
User and privilege mode (read):
0
Pin behaves as normal push/pull pin.
1
Pin operates in open drain mode.
User and privilege mode (write):
0
Configures the pin as push/pull.
1
Configures the pin as open drain.
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31.4.15 RTP Pin Control 7 Register (RTPPC7)
The bits in register control the pullup/down functionality of a pin. The internal pullup/down can be enabled
or disabled by this register. The reset configuration of these bits is device implementation dependent.
Please consult the device datasheet this information. Figure 31-23 and Table 31-23 illustrate this register.
Figure 31-23. RTP Pin Control 7 Register (RTPPC7) [offset = 50h]
31
18
17
16
Reserved
19
ENADIS
CLKDIS
SYNCDIS
R-0
R/W-x
R/W-x
R/W-x
15
0
DATADIS[15:0]
R/W-x
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 31-23. RTP Pin Control 7 Register (RTPPC7) Field Descriptions
Bit
Field
31-19
Reserved
18
ENADIS
Value
0
Description
Read returns 0. Writes have no effect.
RTPENA Pull disable. This bit removes the internal pullup/pulldown functionality from the pin, when it
is configured as an input pin (RTPPC1[18]=0).
User and privilege mode (read):
0
Pullup/pulldown functionality is enabled.
1
Pullup/pulldown functionality is disabled.
User and privilege mode (write):
17
0
Enables pullup/pulldown functionality.
1
Disables pullup/pulldown functionality.
CLKDIS
RTPCLK Pull disable. This bit removes the internal pullup/pulldown functionality from the pin, when it
is configured as an input pin (RTPPC1[17]=0).
User and privilege mode (read):
0
Pullup/pulldown functionality is enabled.
1
Pullup/pulldown functionality is disabled.
User and privilege mode (write):
16
0
Enables pullup/pulldown functionality.
1
Disables pullup/pulldown functionality.
SYNCDIS
RTPSYNC Pull disable. This bit removes the internal pullup/pulldown functionality from the pin, when
configured as an input pin (RTPPC1[16]=0).
User and privilege mode (read):
0
Pullup/pulldown functionality is enabled.
1
Pullup/pulldown functionality is disabled.
User and privilege mode (write):
15-0
0
Enables pullup/pulldown functionality.
1
Disables pullup/pulldown functionality.
DATADIS[n]
RTPDATA[15:0] Pull disable. This bit removes the internal pullup/pulldown functionality from the pins,
when configured as input pins (RTPPC1[15:0]=0). Each bit [n] represents a single pin.
User and privilege mode (read):
0
Pullup/pulldown functionality is enabled.
1
Pullup/pulldown functionality is disabled.
User and privilege mode (write):
1806
0
Enables pullup/pulldown functionality.
1
Disables pullup/pulldown functionality.
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31.4.16 RTP Pin Control 8 Register (RTPPC8)
These bits control if the internal pullup or pulldown is configured on the input pin. Figure 31-24 and
Table 31-24 illustrate this register.
Figure 31-24. RTP Pin Control 8 Register (RTPPC8) [offset = 54h]
31
18
17
16
Reserved
19
ENAPSEL
CLKPSEL
SYNCPSEL
R-0
R/W-1
R/W-1
R/W-1
15
0
DATAPSEL[15:0]
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 31-24. RTP Pin Control 8 Register (RTPPC8) Field Descriptions
Bit
Field
31-19
Reserved
18
ENAPSEL
Value
0
Description
Read returns 0. Writes have no effect.
RTPENA Pull select. This bit configures pullup or pulldown functionality, if RTPPC7[18]=0.
User and privilege mode (read):
0
Pulldown functionality is enabled.
1
Pullup functionality is enabled.
User and privilege mode (write):
17
0
Enables pulldown functionality.
1
Enables pullup functionality.
CLKPSEL
RTPCLK Pull select. This bit configures pullup or pulldown functionality, if RTPPC7[17]=0.
User and privilege mode (read):
0
Pulldown functionality is enabled.
1
Pullup functionality is enabled.
User and privilege mode (write):
16
0
Enables pulldown functionality.
1
Enables pullup functionality.
SYNCPSEL
RTPSYNC Pull select. This bit configures pullup or pulldown functionality, if RTPPC7[16]=0.
User and privilege mode (read):
0
Pulldown functionality is enabled.
1
Pullup functionality is enabled.
User and privilege mode (write):
15-0
0
Enables pulldown functionality.
1
Enables pullup functionality.
DATAPSEL[n]
RTPDATA[15:0] Pull select. These bits configure pullup or pulldown functionality, if
RTPPC7[15:0]=0. Each bit [n] represents a single pin.
User and privilege mode (read):
0
Pulldown functionality is enabled.
1
Pullup functionality is enabled.
User and privilege mode (write):
0
Enables pulldown functionality.
1
Enables pullup functionality.
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Chapter 32
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eFuse Controller
This chapter describes the eFuse controller.
Topic
32.1
32.2
32.3
32.4
1808
...........................................................................................................................
Overview........................................................................................................
Introduction ...................................................................................................
eFuse Controller Testing .................................................................................
eFuse Controller Registers ..............................................................................
eFuse Controller
Page
1809
1809
1809
1812
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32.1 Overview
Electrically programmable fuses (eFuses) are used to configure the device after deassertion of PORRST.
The eFuse values are read and loaded into internal registers as part of the power-on-reset sequence. The
eFuse values are protected with single bit error correction, double bit error detection (SECDED) codes.
These fuses are programmed during the initial factory test of the device. The eFuse controller is designed
so that the state of the eFuses cannot be changed once the device is packaged.
32.2 Introduction
The eFuse controller automatically reads the values of the eFuses and shifts them into registers during the
power-on reset sequence. No action is required from the application code. However, in a safety critical
application, the user code should check to see if a correctable or an uncorrectable error was detected
during the reset sequence and then preform a self-test on the eFuse controller ECC logic.
32.3 eFuse Controller Testing
32.3.1 eFuse Controller Connections to ESM
There are three connections from the eFuse controller to the Error Signaling Module (ESM). If an
uncorrectable error occurs during the loading of the eFuse values after reset, a group three, channel one
error and a group one channel 40 error are sent to the ESM. The group three error will cause the ERROR
pin to go low. If during the eFuse loading a correctable error occurs, only a group one channel 40 error is
sent to the ESM. If an error occurs during the eFuse controller self test, then a group one channel 41 error
and a group one channel 40 error are sent to the ESM. After reset, by default, the group one errors do not
affect the ERROR pin. If the software enables the appropriate bit in the appropriate ESM Influence Error
Pin Set/Status Register (ESMIEPSRn) while the group one error is set, the ERROR pin will go low.
Table 32-1. ESM Signals Set by eFuse Controller
Self Test
ESM Signal
Uncorrected Load
Failure
Group 3 Channel 1
X
Group 1 Channel 40
X
Correctable Load
Error
eFuse Self Test
X
X
eFuse stuck at 0 Test
Version a:
with Error pin
Version b:
without Error pin
X
Group 1 Channel 41
X
X
X
32.3.2 Checking for eFuse Errors After Power Up
For safety critical systems, it is required that you check the status of the eFuse controller after a device
reset. A suggested flow chart for checking the eFuse controller after device reset is shown in Figure 32-1.
Failures during the eFuse self test can be grouped into three levels of severity. Depending on the safety
critical application, the error handling for each error type may be different.
32.3.2.1 Class 1 Error
A class 1 error of the eFuse controller means that there was a failure during the autoload sequence. The
values read from the eFuses cannot be relied on. All device operation is suspect. A class 1 error is
indicated by a signal to group 3 channel 1 of the ESM. This will cause the ERROR pin to go active low.
32.3.2.2 Class 2 Errors
A class 2 error is an indication that the safety checks of the eFuse controller did not work. These are also
serious errors because you can no longer guarantee that a more severe error did not occur.
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32.3.2.3 Class 3 Error
A class 3 error indicates that there was a single bit failure reading the eFuses that was corrected by ECC
bits. Proper operation is still likely, but the system is now at a higher risk for a future non-correctable error.
When a correctable error occurs, ESM group 1, channel 40 will be set. In the suggested flow chart shown
in Figure 32-1 below, the single bit error is determined by directly reading the eFuse error status register,
and not depending on the integrity of the connections between the eFuse controller and the ESM.
32.3.2.4 Stuck at Zero Test
The purpose of the stuck at zero test is to verify that the eFuse controller could signal the ESM if an
autoload error did occur. It basically verifies the path through the eFuse controller and to the ESM. This is
done by writing a special instruction to the eFuse controller boundary register, then verifying that the
proper bits are set in the eFuse controller pins register. Upon successful completion of this test ESM
group 1 channel 41 and ESM group 3 channel 1 will be set. This will force the ERROR pin low.
• Version A
– Write boundary register (address 0xFFF8C01C) with 0x003FC000 to set the error signals.
– Read pins register (address 0xFFF8C02C) and verify that bits 14, 12, 11 and 10 are set.
– Write boundary register (address 0xFFF8C01C) with 0x003C0000, to clear the error signals.
– Verify that ESM group 1 channel 41 and group 3 channel 1 are set, then clear them.
If the system cannot support a test which causes the ERROR pin to go low, then the stuck at zero test can
be modified as follows:
• Version B
– Write boundary register (address 0xFFF8C01C) with 0x003BC000.
– Read pins register (address 0xFFF8C02C) and verify that bits 14, 12, and 11 are set.
– Write boundary register (address 0xFFF8C01C) with 0x003C0000, to clear the error signals.
– Verify that ESM group 1 channel 41 is set, then clear it.
This alternate method provides less test coverage because the path from the uncorrectable error signal
from the eFuse controller to the ESM is not specifically tested. However, even if this path is broken,
reading the five eFuse error status bits will indicate that an error occurred.
32.3.2.5 eFuse ECC Logic Self Test
The eFuse controller self test performs extensive validation of the ECC logic in the eFuse controller. This
test should only be performed once for every device PORRST cycle. Perform the self test by following
these steps:
• Write 0x00000258 to the self test cycles register (EFCSTCY) at address 0xFFF8C048.
• Write 0x5362F97F to the self test signature register (EFCSTSIG) at address 0xFFF8C04C.
• Write 0x0000200F to the boundary register at address 0xFFF8C01C. This triggers the self test. The
test takes 610 VCLK cycles to complete. The application can poll bit 15 of the pins register at address
0xFFF8C02C to wait for the test to complete.
• Check ESM group 1 channels 40 and 41 for any errors, neither should be set.
• Verify that bits 4 to 0 of the eFuse Error Status register at address 0xFFF8C03C are zero.
1810
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Figure 32-1. eFuse Self Test Flow Chart
eFuse Controller
Test
Is ESM group 3
channel 1 set?
Class 1
error
routine
Y
N
Test bits 4-0 of
eFuse Error
status register
Are all 5 bits
zero?
N
Y
Run stuck
at zero test
Are the 5 bits =
0x15?
N
Stuck at zero
test pass?
Y
Run eFuse
self test
N
Did self test
pass?
Y
Run eFuse
self test
Did self test
pass?
Y
N
Y
Class 3
error
routine
N
Class 2
error
routine
PASS
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32.4 eFuse Controller Registers
All registers in the eFuse Controller module are 32-bit, word-aligned; 8-bit, 16-bit and 32-bit accesses are
allowed. Table 32-2 provides a quick reference to each of these registers. Specific bit descriptions are
discussed in the following subsections. The base address for the control registers is FFF8 C000h.
Table 32-2. eFuse Controller Registers
Offset
Acronym
Register Description
1Ch
EFCBOUND
EFC Boundary Control Register
Section 32.4.1
Section
2Ch
EFCPINS
EFC Pins Register
Section 32.4.2
3Ch
EFCERRSTAT
EFC Error Status Register
Section 32.4.3
48h
EFCSTCY
EFC Self Test Cycles Register
Section 32.4.4
4Ch
EFCSTSIG
EFC Self Test Signature Register
Section 32.4.5
32.4.1 EFC Boundary Control Register (EFCBOUND)
Figure 32-2 and Table 32-3 describe the EFCBOUND register. The eFuse Boundary Control Register is
used to test the connections between the eFuse controller and the ESM module. The eFuse Boundary
Control Register is also used to initiate an eFuse controller ECC self-test.
Figure 32-2. EFC Boundary Control Register (EFCBOUND) [offset = 1Ch]
31
24
Reserved
R-0
23
21
20
19
18
17
16
Reserved
22
EFC Self Test
Error
EFC Single Bit
Error
EFC Instruction
Error
EFC Autoload
Error
Self Test
Error OE
Single Bit
Error OE
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
12
15
14
13
Instruction
Error OE
Autoload
Error OE
EFC ECC Selftest
Enable
Reserved
R/W-0
R/W-0
R/W-0
R-0
7
4
8
3
0
Reserved
Input Enable
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after power-on reset (nPORRST)
Table 32-3. EFC Boundary Register (EFCBOUND) Field Descriptions
Bit
31-22
21
20
1812
Field
Reserved
Value
0
EFC Self Test Error
Description
Read returns 0. Writes have no effect.
This bit drives the self test error signal when bit 17 (Self Test Error OE) is high. This signal
is attached to ESM error Group 1, Channel 41.
0
Drives the self test error signal low, if Self Test OE is high.
1
Drives the self test error signal high, if Self Test OE is high.
EFC Single Bit Error
This bit drives the single bit error signal when bit 16 (Single bit Error OE) is high. This signal
is attached to ESM error Group 1, Channel 40.
0
Drives the self test error signal low, if Single Bit Error OE is high.
1
Drives the self test error signal high, if Single Bit Error OE is high.
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Table 32-3. EFC Boundary Register (EFCBOUND) Field Descriptions (continued)
Bit
Field
19
EFC Instruction Error
18
17
16
15
14
13
Value
This bit drives the instruction error signal when bit 15 (Instruction Error OE) is high. This
signal is used to denote an error occurred during e-fuse programming. This signal is not
attached to the ESM.
0
Drives the Instruction Error signal low, if Instruction Error OE is high.
1
Drives the Instruction Error signal high, if Instruction Error OE is high.
EFC Autoload Error
This bit drives the Autoload Error signal when bit 14 (Autoload Error OE) is high. This signal
is attached to ESM error Group 3, Channel 1.
0
Drives the Autoload Error signal low, if Autoload Error OE is high.
1
Drives the Autoload Error signal high, if Autoload Error OE is high.
Self Test Error OE
The Self Test Error Output Enable bit determines if the EFC Self Test signal comes from the
eFuse controller or from bit 21 of the boundary register.
0
EFC Self Test Error comes from eFuse controller.
1
EFC Self Test Error comes from the boundary register.
Single Bit Error OE
The single bit error output enable signal determines if the EFC Single Bit Error signal comes
from the eFuse controller or from bit 20 of the boundary register.
0
EFC Single Bit Error comes from eFuse controller.
1
EFC Single Bit Error comes from the boundary register.
Instruction Error OE
The instruction error output enable signal determines if the EFC Instruction Error signal
comes from the eFuse controller or from bit 19 of the boundary register.
0
EFC Instruction Error comes from eFuse controller.
1
EFC Instruction Error comes from the boundary register.
Autoload Error OE
The autoload error output enable signal determines if the EFC Autoload Error signal comes
from the eFuse controller or from bit 18 of the boundary register.
0
EFC Autoload Error comes from eFuse controller.
1
EFC Autoload Error comes from the boundary register.
EFC ECC Selftest
Enable
12-4
Reserved
3-0
Input Enable
Description
The eFuse Controller ECC Selftest Enable bit starts the selftest of the ECC logic if the four
input enable bits (EFCBOUND[3:0) are all 1s.
0
No action
1
Start ECC selftest if EFCBOUND[3:0] are Fh.
0
Read returns 0. Writes have no effect.
The eFuse Controller ECC Selftest Enable bit starts the selftest of the ECC logic if the four
input enable bits (EFCBOUND[3:0) are all 1s.
Fh
All others
ECC selftest can be started if EFC ECC Selftest Enable, bit 13, is set
ECC selftest cannot be started.
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32.4.2 EFC Pins Register (EFCPINS)
Figure 32-3 and Figure 32-3 describe the EFCPINS register.
Figure 32-3. EFC Pins Register (EFCPINS) [offset = 2Ch]
31
16
Reserved
R-0
15
14
13
12
11
10
EFC Selftest
Done
EFC Selftest
Error
Reserved
EFC Single Bit
Error
EFC Instruction
Error
EFC Autoload
Error
9
Reserved
8
R-0
R-0
R-0
R-x
R-0
R-x
R-x
7
0
Reserved
R-x
LEGEND: R = Read only; -n = value after power-on reset (nPORRST); x = Indeterminate
Table 32-4. EFC Pins Register (EFCPINS) Field Descriptions
Bit
31–16
15
14
Name
Reserved
12
EFC Single Bit Error
9-0
1814
Reads return zeros, writes have no effect.
0
EFC ECC selftest is not complete.
1
EFC ECC selftest is complete.
This bit indicates the pass/fail status of the EFC ECC Selftest once the EFC Selftest Done
bit (bit 15) is set.
0
EFC ECC Selftest passed.
1
EFC ECC Selftest failed.
0
Reads return zeros. Do NOT write a 1 to this bit.
This bit indicates if a single bit error was corrected by the ECC logic during the autoload
after reset.
0
No single bit error was detected.
1
A single bit error was detected and corrected.
EFC Instruction Error
This bit indicates an error occurred during a factory test or program operation. This bit
should not be set from normal use.
0
No instruction error detected.
1
An error occurred during a factory test or program operation.
EFC Autoload Error
Reserved
Description
This bit can be polled to determine when the EFC ECC selftest is complete
EFC Selftest Error
Reserved
10
0
EFC Selftest Done
13
11
Value
This bit indicates that some non-correctable error occurred during the autoload sequence
after reset. This bit also sets ESM group 3, channel 1.
0
The autoload function completed successfully.
1
There were non-correctable errors during the autoload sequence.
0-1
After reset, these bits are indeterminate and reads return either a 1 or 0.
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32.4.3 EFC Error Status Register (EFCERRSTAT)
Figure 32-4 and Table 32-5 describe the EFCERRSTAT register.
Figure 32-4. EFC Error Status Register (EFCERRSTAT) [offset = 3Ch]
31
8
Reserved
R-0
7
6
5
4
0
Reserved
Instruc Done
Error Code
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after power-on reset (nPORRST)
Table 32-5. EFC Error Status Register (EFCERRSTAT) Field Descriptions
Bit
31–6
5
4-0
Name
Value
Reserved
0
Instruc Done
Description
Reads return zeros, writes have no effect.
Instruction done. Used to indicate that the eFuse self test has completed
0
The eFuse controller is still executing.
1
The eFuse controller has completed executing.
Error Code
The error status of the last instruction executed by the eFuse Controller
0
No error.
5h
An uncorrectable (multibit) error was detected during the power-on autoload sequence.
15h
At least one single bit error was detected and corrected during the power-on autoload
sequence.
18h
The signature generated by the ECC self-test logic did not match the golden signature
written in the EFCSTSIG register. The EDAC circuitry might have a fault.
All other
values
All other values are reserved for e-fuse system tests and are not expected to occur in
normal system use.
32.4.4 EFC Self Test Cycles Register (EFCSTCY)
Figure 32-5 and Table 32-6 describe the EFCSTCY register.
Figure 32-5. EFC Self Test Cycles Register (EFCSTCY) [offset = 48h]
31
16
Cycles
R/W-0
15
0
Cycles
R/W-0
LEGEND: R/W = Read/Write; -n = value after power-on reset (nPORRST)
Table 32-6. EFC Self Test Cycles Register (EFCSTCY) Field Descriptions
Bit
Name
Description
31–0
Cycles
This register is used to determine the number of cycles to run the eFuse controller ECC logic self test. It is
recommended to use a value of 600 (0x00000258).
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32.4.5 EFC Self Test Signature Register (EFCSTSIG)
Figure 32-6 and Table 32-7 describe the EFCSTSIG register.
Figure 32-6. EFC Self Test Cycles Register (EFCSTSIG) [offset = 4Ch]
31
16
Signature
R/W-0
15
0
Signature
R/W-0
LEGEND: R/W = Read/Write; -n = value after power-on reset (nPORRST)
Table 32-7. EFC Self Test Cycles Register (EFCSTSIG) Field Descriptions
Bit
31–0
1816
Name
Description
Signature
This register is used to hold the expected signature for the eFuse ECC logic self test. It is recommended to
write a value of 0x5362F97F to this register and a value of 600 (0x00000258) to the EFCSTCY register. If
after running the eFuse ECC logic self test, the calculated signature does not match the expected
signature in the EFCSTSIG register, then a value of 18h is stored in the EFCERRSTAT register.
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Revision History
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Figure 1-1: Added MIBSPI5_CLK signal ............................................................................................. 96
Figure 1-1: Deleted EMIF_RnW signal ............................................................................................... 96
Chapter 2: Architecture ............................................................................................................... 98
Table 2-1: Rearranged sequence of terms ......................................................................................... 100
Table 2-2: Changed table. Added Access Mode column ......................................................................... 102
Section 2.2.3.2: In fourth paragraph, corrected starting address of bank 7 ECC from 0xF0200000 to 0xF010 0000 .... 109
Table 2-6: Changed table. Corrected value in Valid RINFO Register Value column ......................................... 111
Table 2-7: Changed NHET2 RAM Address Range End to 0xFF45FFFF ....................................................... 114
Table 2-7: Added Ethernet RAM (CPPI Memory Slave) .......................................................................... 114
Table 2-7: Deleted table footnote (3). Subsequent footnotes renumbered ..................................................... 114
Section 2.3.1: Updated third sentence in second paragraph. Changed to minimum of 32 peripheral clock (VCLK)
cycles .................................................................................................................................... 115
Table 2-8: Updated Description of Debug reset. Changed DBG RST bit to WDRST bit ..................................... 115
Table 2-8: Updated Description of Watchdog reset ............................................................................... 115
Table 2-9: Changed Description of LF LPO and HF LPO ........................................................................ 118
Figure 2-4: Added SEL_GIO_PIN field to CLKTEST register .................................................................... 123
Table 2-12: Changed signals on ECLK ............................................................................................. 123
Section 2.4.5: Added Embedded Trace Macrocell (ETM-R4) subsection. Subsequent subsections, figures, and tables
renumbered ............................................................................................................................. 124
Section 2.5.1: Updated paragraph ................................................................................................... 127
Table 2-31: Changed Description of bits for Value = 0 (Read) to enabled ..................................................... 136
Section 2.5.1.13: Added second paragraph to NOTE ............................................................................. 137
Figure 2-18: Changed bit 10 to Reserved........................................................................................... 137
Table 2-32: Changed bit 10 to Reserved ........................................................................................... 137
Figure 2-19: Corrected register bit name for bits 4, 3, 2, 1, and 0 ............................................................... 139
Figure 2-19: Changed bit 10 to Reserved........................................................................................... 139
Table 2-33: Changed bit 10 to Reserved ........................................................................................... 139
Figure 2-20: Changed bit 10 to Reserved........................................................................................... 140
Table 2-34: Changed bit 10 to Reserved ........................................................................................... 141
Table 2-35: Changed Description of GHVSRC bit. Removed "on wakeup" .................................................... 143
Table 2-41: Updated MSTGENA and MINITGENA values to Ah for MSIENA = 1 ............................................ 149
Table 2-44: Corrected Description of PLLMUL bit. Value = 0h is ×1, Value = 100h is ×2 ................................... 152
Figure 2-33: Corrected register bit fields ............................................................................................ 155
Table 2-47: Changed table to reflect updated register bit fields ................................................................. 155
Figure 2-34: Corrected register bit fields ............................................................................................ 155
Table 2-48: Changed table to reflect updated register bit fields ................................................................. 155
Table 2-49: Changed Description of OSCFRQCONFIGCNT bit. Writes have no effect ...................................... 156
Table 2-50: Changed Description of SEL_GIO_PIN and SEL_ECP_PIN bits ................................................. 159
Figure 2-37: Updated reset value of DFTWRITE and DFTREAD bits to 2h.................................................... 161
Figure 2-39: Corrected register bit name for bits 19-16 ........................................................................... 163
Table 2-53: Changed Description of PLL1_FBSLIP_FILTER_ COUNT and PLL1_FBSLIP_FILTER_ KEY bits .......... 163
Section 2.5.1.43: Changed paragraph............................................................................................... 171
Section 2.5.1.43: Added NOTE....................................................................................................... 171
Section 2.5.1.44: Changed NOTE ................................................................................................... 172
Table 2-63: Added Note to VCLK2R and VCLKR bits ............................................................................ 172
Table 2-64: Deleted Note from the ECPDIV bit .................................................................................... 173
Section 2.5.1.47: Added NOTE....................................................................................................... 174
Section 2.5.1.48: Updated paragraph. (Clarified description of how system exception status bits behave through
reset) ..................................................................................................................................... 175
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Figure 2-53: Updated Read/Write value of bits 14, 13, 5, 4, and 3 to R/WC-X* ...............................................
Figure 2-53: Changed Reserved bits to 2-0 ........................................................................................
Figure 2-53: Deleted MPMODE bit ..................................................................................................
Table 2-67: Changed Description of PORST and EXTRST bits .................................................................
Table 2-67: Changed Description of WDRST bit. Added (DBGRST) ...........................................................
Table 2-67: Changed Reserved bits to 2-0 .........................................................................................
Table 2-67: Deleted MPMODE bit ...................................................................................................
Figure 2-55: Updated Read/Write value of FBSLIP, RFSLIP, and OSCFAIL bits to R/W1C-n ..............................
Figure 2-55: Changed LEGEND .....................................................................................................
Table 2-69: Changed Description of FBSLIP, RFSLIP, and OSCFAIL bits ....................................................
Section 2.5.2: Updated paragraph ...................................................................................................
Figure 2-62: Changed bits 10-8 and 4-0 to Reserved .............................................................................
Table 2-77: Changed bits 10-8 and 4-0 to Reserved ..............................................................................
Table 2-77: Changed Value column of Reserved bits 15-0 to 109h.............................................................
Table 2-77: Changed Description of VCLKA4S bit for Value = 8h-Fh ..........................................................
Figure 2-63: Changed register bit names for bits 13-8 and bits 3-0 .............................................................
Table 2-78: Changed register bit names for bits 13-8 and bits 3-0 ..............................................................
Table 2-78: Changed Description of PLL1_RFSLIP_FILTER_COUNT and PLL1_RFSLIP_FILTER_KEY bits ...........
Section 2.5.2.7: Changed paragraph ................................................................................................
Figure 2-65: Corrected register bit fields ............................................................................................
Table 2-80: Changed table to reflect updated register bit fields .................................................................
Section 2.5.2.8: Changed paragraph ................................................................................................
Figure 2-66: Corrected register bit fields ............................................................................................
Table 2-81: Changed table to reflect updated register bit fields .................................................................
Table 2-82: Changed Description of DIEIDL2 bit. Added last sentence ........................................................
Table 2-83: Changed Description of DIEIDH2 bit. Added last sentence ........................................................
Section 2.5.3: Updated paragraph ...................................................................................................
Figure 2-73: Changed register bit name to PS[7-0]QUAD[3-0]PROTSET......................................................
Table 2-89: Changed register bit name to PS[7-0]QUAD[3-0]PROTSET ......................................................
Table 2-89: Corrected register names in Description of PROTSET bit for Value = 1 (Write) ................................
Figure 2-74: Changed register bit name to PS[15-8]QUAD[3-0]PROTSET ....................................................
Table 2-90: Changed register bit name to PS[15-8]QUAD[3-0]PROTSET .....................................................
Table 2-90: Corrected register names in Description of PROTSET bit for Value = 1 (Write) ................................
Figure 2-75: Changed register bit name to PS[23-16]QUAD[3-0]PROTSET...................................................
Table 2-91: Changed register bit name to PS[23-16]QUAD[3-0]PROTSET ...................................................
Table 2-91: Corrected register names in Description of PROTSET bit for Value = 1 (Write) ................................
Figure 2-76: Changed register bit name to PS[31-24]QUAD[3-0]PROTSET...................................................
Table 2-92: Changed register bit name to PS[31-24]QUAD[3-0]PROTSET ...................................................
Table 2-92: Corrected register names in Description of PROTSET bit for Value = 1 (Write) ................................
Figure 2-77: Changed register bit name to PS[7-0]QUAD[3-0]PROTCLR .....................................................
Table 2-93: Changed register bit name to PS[7-0]QUAD[3-0]PROTCLR ......................................................
Table 2-93: Corrected register names in Description of PROTCLR bit for Value = 1 (Write) ................................
Figure 2-78: Changed register bit name to PS[15-8]QUAD[3-0]PROTCLR ....................................................
Table 2-94: Changed register bit name to PS[15-8]QUAD[3-0]PROTCLR .....................................................
Table 2-94: Corrected register names in Description of PROTCLR bit for Value = 1 (Write) ................................
Figure 2-79: Changed register bit name to PS[23-16]QUAD[3-0]PROTCLR ..................................................
Table 2-95: Changed register bit name to PS[23-16]QUAD[3-0]PROTCLR ...................................................
Table 2-95: Corrected register names in Description of PROTCLR bit for Value = 1 (Write) ................................
Figure 2-80: Changed register bit name to PS[31-24]QUAD[3-0]PROTCLR ..................................................
Table 2-96: Changed register bit name to PS[31-24]QUAD[3-0]PROTCLR ...................................................
Table 2-96: Corrected register names in Description of PROTCLR bit for Value = 1 (Write) ................................
Chapter 3: Power Management Module (PMM) .................................................................................
Figure 3-2: Added MIBSPI5_CLK signal ............................................................................................
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Section 3.3.5.1: Changed steps 2 and 3 in first paragraph ....................................................................... 208
Section 3.3.5.1: Changed step 2 in second paragraph ........................................................................... 208
Section 3.3.5.2: Changed paragraph to include registers......................................................................... 209
Section 3.3.8.3: Changed paragraph ................................................................................................ 210
Table 3-1: Corrected acronym for PDCLKDISREG, PDCLKDISSETREG, and PDCLKDISCLRREG registers ........... 211
Figure 3-18: Updated Read/Write value of LCMPE bits to R/W1CP-0 .......................................................... 226
Figure 3-20: Changed bits 18-16 to MCMPE ....................................................................................... 228
Figure 3-20: Updated Read/Write value of MCMPE bits to R/W1CP-0 ......................................................... 228
Section 3.4.20: Deleted first paragraph ............................................................................................. 230
Chapter 4: I/O Multiplexing and Control Module (IOMM) ..................................................................... 231
Section 4.2: Deleted second bullet................................................................................................... 232
Section 4.4.2: Deleted subsection Master ID Check. Subsequent subsection renumbered ................................. 236
Section 4.5: Updated paragraph to include base address ........................................................................ 237
Section 4.5.3: Changed paragraph .................................................................................................. 239
Figure 4-6: Updated Read/Write value of KICK0 bits to R/W-0 .................................................................. 239
Figure 4-6: Changed LEGEND ....................................................................................................... 239
Section 4.5.4: Changed paragraph .................................................................................................. 239
Figure 4-7: Updated Read/Write value of KICK1 bits to R/W-0 .................................................................. 239
Figure 4-7: Changed LEGEND ....................................................................................................... 239
Table 4-8: Changed Description of ADDR_ERR and PROT_ERR bits ......................................................... 240
Section 4.5.6: Changed paragraph .................................................................................................. 241
Figure 4-12: Changed FAULT_ADDR bits to 8-0 .................................................................................. 243
Figure 4-12: Added Reserved bits 31-9 ............................................................................................. 243
Table 4-12: Added Reserved bits 31-9 .............................................................................................. 243
Table 4-12: Changed FAULT_ADDR bits to 8-0 ................................................................................... 243
Table 4-13: Changed Description of FAULT_TYPE bit for Value = 4h, 8h, and 10h.......................................... 244
Table 4-16: Corrected Control Register at address FFFF EB34h for Alternate Function 2 GIOB[2] Selection Bit to
PINMMR9[18] ........................................................................................................................... 246
Table 4-16: Corrected Control Register at address FFFF EB48h for Selection Bit PINMMR14[17] Alternate Function 1 to
RESERVED ............................................................................................................................. 246
Chapter 5: F021 Flash Module Controller........................................................................................ 250
Section 5.1.2: Added definition for ATCM........................................................................................... 251
Table 5-1: Updated footnote 2. XOR of all the address and data bits .......................................................... 254
Table 5-1: Updated format ............................................................................................................ 254
Section 5.4.1: Updated paragraph. Corrected starting address of flash ECC to 0xF0400000 ............................... 257
Figure 5-1: Changed figure ........................................................................................................... 257
Figure 5-2: Added BX_NUM_Sectors and BX_Sector_Size. Deleted Bx bits .................................................. 258
Table 5-4: Changed table. ............................................................................................................ 258
Section 5.4.2.4: Deleted table. Subsequent tables renumbered ................................................................. 260
Section 5.4.2.5: Added Deliberate ECC Errors for FMC ECC Checking subsection. Subsequent figures renumbered . 260
Section 5.6.2: Updated second paragraph.......................................................................................... 261
Table 5-8: Updated Description of test modes ..................................................................................... 261
Section 5.6.2.1: Updated eighth sentence in second paragraph. Changed ECC_MUL_ERR to ERR_PRF_FLG ........ 262
Section 5.6.2.3: Deleted last sentence in first paragraph ......................................................................... 263
Section 5.6.2.3: Updated third paragraph ........................................................................................... 263
Section 5.6.2.3: Deleted fourth paragraph .......................................................................................... 263
Section 5.6.2.4: Updated first and second paragraphs............................................................................ 263
Section 5.6.2.4: Deleted second and fourth paragraphs .......................................................................... 263
Section 5.6.2.4: Deleted ECC Malfunction Test Logic figure. Subsequent figures renumbered ............................. 263
Section 5.6.2.5: Added NOTE ........................................................................................................ 263
Section 5.6.2.5: Updated second paragraph ....................................................................................... 263
Section 5.6.2.6: Updated second sentence in second paragraph. Corrected the value. ..................................... 264
Section 5.6.2.6: Deleted last sentence in fourth paragraph ...................................................................... 264
Section 5.6.2.6: Updated first sentence in fourth paragraph. Changed ECC_MUL_ERR to B1_UNC_ERR .............. 264
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Section 5.6.2.6: Updated steps in fifth paragraph.................................................................................. 264
Table 5-9: Updated Name of test modes ........................................................................................... 265
Table 5-9: Updated test mode 7. Changed ECC_MUL_ERR to B1_UNC_ERR .............................................. 265
Table 5-10: Updated Name of test modes .......................................................................................... 266
Table 5-10: Updated test mode 1. Deleted D_MUL_ERR ........................................................................ 266
Table 5-10: Updated test mode 1. Changed ERR_MUL_FLG to ERR_PRF_FLG ............................................ 266
Table 5-10: Updated test mode 1. Deleted EE_D_MUL_ERR ................................................................... 266
Table 5-10: Updated test mode 1. Changed EE_ERR_MUL_FLG to EE_ERR_PRF_FLG .................................. 266
Table 5-10: Updated test mode 3. Changed EE_MAL_ERR to EE_CME ...................................................... 266
Table 5-10: Updated test mode 4. Changed EE_COM_MAL_GOOD to EE_CMG and EE_MAL_ERR to EE_CME .... 266
Table 5-11: Updated Name of test modes .......................................................................................... 267
Table 5-14: Changed Description of EDACMODE bit ............................................................................. 270
Figure 5-13: Corrected bit 3 to D_COR_ERR ...................................................................................... 275
Table 5-19: Changed Description of D_COR_ERR bit ............................................................................ 275
Table 5-24: Changed Description of PROTL1DIS bit ............................................................................. 281
Table 5-26: Changed Description of BUSY bit for Value = 1. (The corresponding bank is busy) ........................... 282
Section 5.7.22: Added paragraph .................................................................................................... 290
Table 5-34: Changed Description of EMU_DMSW bit ............................................................................ 290
Section 5.7.23: Added paragraph .................................................................................................... 290
Table 5-35: Changed Description of EMU_DLSW bit ............................................................................. 290
Section 5.7.24: Added paragraph .................................................................................................... 291
Table 5-36: Changed Description of EMU_ECC bit ............................................................................... 291
Section 5.7.25: Added paragraph .................................................................................................... 292
Table 5-37: Changed Description of EMU_ADDR bit ............................................................................. 292
Section 5.7.26: Deleted second paragraph ......................................................................................... 293
Table 5-38: Updated Description of DIAG_MODE bit ............................................................................. 293
Table 5-39: Changed Description of RAW_DATA bits ............................................................................ 295
Table 5-40: Changed Description of RAW_DATA bits ............................................................................ 295
Table 5-41: Changed Description of RAW_ECC bits .............................................................................. 296
Section 5.7.30: Deleted paragraph .................................................................................................. 297
Figure 5-39: Corrected name of FSM_SECTOR register figure heading ....................................................... 299
Table 5-45: Corrected name of FSM_SECTOR register table heading ......................................................... 299
Section 5.7.35: Changed paragraph ................................................................................................. 301
Table 5-47: Updated Description of Reserved bits 31-20. (Reads return 050h.) .............................................. 301
Table 5-47: Changed Description of EE_EDACMODE bit ........................................................................ 301
Figure 5-46: Corrected bit 3 to EE_D_COR_ERR ................................................................................. 306
Table 5-52: Changed Description of EE_CMG bit ................................................................................. 306
Table 5-52: Added Description for bit 4, EE_CME................................................................................. 306
Chapter 6: Tightly-Coupled RAM (TCRAM) Module ........................................................................... 309
Figure 6-1: Deleted ATCM block. .................................................................................................... 310
Figure 6-1: Deleted interface signals to TCRAMW1 and TCRAMW2 ........................................................... 310
Section 6.4: Updated paragraph to include INIT_DOMAIN register ............................................................. 313
Section 6.7: Updated paragraph to clarify base addresses for even and odd RAM ECC .................................... 314
Table 6-1: Added Power Domain Enable Register (INIT_DOMAIN REG) ...................................................... 314
Table 6-2: Updated Description of EMU_TRACE_DIS bit. Tracing of read data to RAM Trace Port (RTP) module during
emulation mode access ............................................................................................................... 315
Table 6-2: Updated Note in ADDR_PARITY_DISABLE bit ....................................................................... 315
Table 6-5: Changed Reserved bits to 31-1 ......................................................................................... 317
Figure 6-7: Updated Read/Write value of bits to R/W1CP-0 ..................................................................... 318
Figure 6-7: Updated LEGEND to include W1CP ................................................................................... 318
Section 6.7.6: Added NOTE .......................................................................................................... 319
Table 6-8: Changed Description of UNCORRECTABLE_ERROR_ADDRESS bit ............................................ 320
Table 6-9: Changed Description of TRIGGER bit .................................................................................. 321
Section 6.7.11: Added subsection ................................................................................................... 323
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Chapter 7: Programmable Built-In Self-Test (PBIST) Module................................................................
Section 7.3.1: Changed step 6. Deleted ROM interface clock ...................................................................
Section 7.3.1: Changed step 12. Deleted ROM clock .............................................................................
Section 7.5: Changed second paragraph (write 1h) ...............................................................................
Section 7.5.3: Updated paragraph to remove bit [1] ...............................................................................
Section 7.5.3: Deleted PACT1 bullet ................................................................................................
Figure 7-5: Deleted bit [1] .............................................................................................................
Table 7-4: Deleted bit [1] ..............................................................................................................
Section 7.6.1: Changed step 5. Deleted ROM interface clock ...................................................................
Section 7.6.1: Changed step 12. Deleted ROM clock .............................................................................
Section 7.6.2: Changed step 5. Deleted ROM interface clock ...................................................................
Section 7.6.2: Changed step 11. Deleted ROM clock .............................................................................
Chapter 8: CPU Self-Test Controller (STC) Module ............................................................................
Section 8.4.3: Changed NOTE .......................................................................................................
Section 8.4.4: Changed NOTE .......................................................................................................
Section 8.4.5: Changed NOTE .......................................................................................................
Section 8.4.6: Changed NOTE .......................................................................................................
Section 8.4.7: Changed NOTE .......................................................................................................
Section 8.4.10: Changed paragraph. (RS_CNT bit in STCGCR0 to 1 to restart the self-test.) ..............................
Chapter 9: CPU Compare Module for Cortex-R4F (CCM-R4F) ...............................................................
Section 9.2: Added last sentences about the signals compared by the CCM-R4F ...........................................
Section 9.4: Updated paragraph to include base address ........................................................................
Chapter 10: Oscillator and PLL ....................................................................................................
Section 10.1: Changed second paragraph..........................................................................................
Section 10.3: Changed second paragraph in bullet 1 .............................................................................
Section 10.4: Changed frequency and frequency range in second paragraph ................................................
Section 10.4.1: Changed frequency and frequency range in first paragraph ..................................................
Section 10.4.1: Changed frequency formulas in table.............................................................................
Section 10.4.2: Corrected third bullet in second paragraph to clock source 5 .................................................
Section 10.4.6: Changed frequency in first paragraph ............................................................................
Section 10.5: Updated third paragraph. Changed f(HCLK) to f(GCLK) .................................................................
Table 10-1: Updated Frequency Limit value to f(GCLK) for fPLL CLK ..................................................................
Table 10-2: Updated formula for NF .................................................................................................
Section 10.5: Changed AVCLK to VCLK2 in NOTE ...............................................................................
Section 10.5.2.1: Changed table of step 2. Updated lock phase time formula to (512 × TOSCIN) .............................
Section 10.5.2.2: Added formula to last sentence of second paragraph: TEnable = 150 × TOSCIN ..............................
Section 10.5.2.2: Deleted table .......................................................................................................
Section 10.5.2.3: Added formula to last sentence of paragraph: TODPLL = 3 × TOSCIN ...........................................
Section 10.5.2.3: Deleted table .......................................................................................................
Section 10.5.2.3: Changed AVCLK to VCLK2 in NOTE ..........................................................................
Table 10-3: Changed table title. Changed table format ...........................................................................
Table 10-3: Updated lock phase time formula to (512 × TOSCIN) ..................................................................
Section 10.5.4: Changed first sentence in first paragraph ........................................................................
Section 10.5.4: Added last sentence to step 3 in both paragraphs ..............................................................
Section 10.6.1: Added second sentence ............................................................................................
Section 10.6.2: Added second sentence ............................................................................................
Section 10.6.3: Added second sentence ............................................................................................
Figure 10-11: Corrected symbols in figure ..........................................................................................
Figure 10-11: Changed PF block to CP .............................................................................................
Section 10.8: Changed step 2, second sentence ..................................................................................
Section 10.8: Changed step 3, second sentence ..................................................................................
Section 10.8: Changed step 5 ........................................................................................................
Section 10.8: Changed step 6 ........................................................................................................
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Section 10.8: Changed step 7 ........................................................................................................
Section 10.8: Changed step 8 ........................................................................................................
Chapter 11: Dual-Clock Comparator (DCC) Module ...........................................................................
Section 11.4: Updated paragraph to include base addresses....................................................................
Figure 11-12: Updated Read/Write value of DONE and ERR bits to R/W1CP-0 ..............................................
Figure 11-12: Updated LEGEND to include W1CP ................................................................................
Table 11-8: Corrected table title ......................................................................................................
Table 11-11: Corrected table title ....................................................................................................
Table 11-11: Changed Description of KEY bit for Value = Any other value ....................................................
Chapter 12: Error Signaling Module (ESM) ......................................................................................
Chapter 12: Changed paragraph .....................................................................................................
Section 12.1.2: Changed first paragraph ............................................................................................
Figure 12-1: Deleted footnote ........................................................................................................
Table 12-1: Changed table ............................................................................................................
Figure 12-2: Moved error_group2 signal path ......................................................................................
Figure 12-3: Deleted Memory mapped register interface signal path ...........................................................
Figure 12-3: Deleted CPU clock (GCLK) signal path ..............................................................................
Section 12.2.2: Deleted third sentence in first paragraph .........................................................................
Section 12.2.2: Added Example 6. Subsequent example renumbered .........................................................
Section 12.4: Changed titles of Set/Status registers. ..............................................................................
Section 12.4: Changed titles of Clear/Status registers. ...........................................................................
Figure 12-17: Updated Read/Write value of bits to R/W1CP-X/0 ................................................................
Figure 12-18: Updated Read/Write value of bits to R/W1CP-0 ..................................................................
Figure 12-19: Updated Read/Write value of bits to R/W1CP-X/0 ................................................................
Table 12-14: Changed Description of INTOFFL bit for values 21h to 60h .....................................................
Figure 12-24: Updated reset value of LTCP bit to 3FFFh ........................................................................
Table 12-16: Changed Description of LTCP bit. ...................................................................................
Figure 12-26: Updated Read/Write value of bits to R/W1CP-X/0 ................................................................
Table 12-20: Changed Description of IEPCLR bit. (corresponding set bit in the ESMIEPSR4) .............................
Table 12-22: Changed Description of INTENCLR bit. (corresponding set bit in the ESMIESR4) ...........................
Figure 12-33: Updated Read/Write value of bits to R/W1CP-X/0 ................................................................
Chapter 13: Real-Time Interrupt (RTI) Module ..................................................................................
Equation 24: Corrected first eqution (if RTICPUCy ≠ 0) ..........................................................................
Figure 13-3: Added register bit numbers for DMA and INT requests ...........................................................
Section 13.2.5.1: Changed first paragraph .........................................................................................
Figure 13-18: Updated Read/Write value of bits to R/WP-0 ......................................................................
Figure 13-18: Updated LEGEND to include WP ...................................................................................
Table 13-8: Changed Description of CPUC0 bit when CPUC0 = 0 .............................................................
Table 13-13: Changed Description of CPUC1 bit when CPUC1 = 0 ............................................................
Figure 13-38: Updated Read/Write value of bits to R/W1CP-0 ..................................................................
Figure 13-41: Updated Read/Write value of bits to R/W1CP-0 ..................................................................
Chapter 14: Cyclic Redundancy Check (CRC) Controller Module ..........................................................
Section 14.1.2: Updated NOTE. (Added cross-reference) ........................................................................
Figure 14-3: Changed MCRC Controller to CRC Controller ......................................................................
Figure 14-4: Changed MCRC Controller to CRC Controller ......................................................................
Section 14.2.11.1: Added subsection ................................................................................................
Section 14.4: Updated paragraph to include base address ......................................................................
Table 14-7: Added last sentence in Description of CH1_TRACEEN bit ........................................................
Table 14-8: Updated Description of all bits .........................................................................................
Table 14-9: Updated Description of all bits .........................................................................................
Figure 14-14: Updated Read/Write value of bits to R/W1CP-0 ..................................................................
Figure 14-14: Updated LEGEND to include W1CP ................................................................................
Table 14-10: Updated Description of all bits ........................................................................................
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Chapter 15: Vectored Interrupt Manager (VIM) Module ....................................................................... 515
Section 15.4: Added NOTE ........................................................................................................... 523
Section 15.8: Updated paragraphs .................................................................................................. 530
Table 15-1: Deleted Reserved address locations .................................................................................. 530
Figure 15-13: Corrected reset value of Interrupt Vector Table offset bits 15-9 ................................................ 532
Table 15-4: Corrected table title ...................................................................................................... 532
Table 15-4: Corrected Description of Interrupt Vector Table offset bits. Reads are always FFF8 2xxxh .................. 532
Section 15.8.8: Corrected subsection title .......................................................................................... 535
Section 15.8.8: Updated LEGEND to include WP ................................................................................. 535
Table 15-9: Corrected table title ...................................................................................................... 535
Section 15.8.9: Corrected subsection title .......................................................................................... 536
Section 15.8.9: Updated Read/Write value of bits to R/W1CP-0 ................................................................ 536
Section 15.8.9: Updated LEGEND to include W1CP .............................................................................. 536
Table 15-10: Corrected table title .................................................................................................... 536
Section 15.8.10: Corrected subsection title ......................................................................................... 537
Section 15.8.10: Updated LEGEND to include WP ................................................................................ 537
Table 15-11: Corrected table title .................................................................................................... 537
Section 15.8.11: Corrected subsection title ......................................................................................... 538
Section 15.8.11: Updated LEGEND to include WP ................................................................................ 538
Table 15-12: Corrected table title .................................................................................................... 538
Section 15.8.12: Corrected subsection title ......................................................................................... 539
Section 15.8.12: Updated LEGEND to include WP ................................................................................ 539
Table 15-13: Corrected table title .................................................................................................... 539
Section 15.8.13: Corrected subsection title ......................................................................................... 540
Section 15.8.13: Updated LEGEND to include WP ................................................................................ 540
Table 15-14: Corrected table title .................................................................................................... 540
Section 15.8.17: Corrected subsection title ......................................................................................... 543
Figure 15-38: Corrected figure title .................................................................................................. 543
Table 15-19: Corrected table title .................................................................................................... 543
Table 15-19: Updated Description of Value = 5Fh to Interrupt request 95. .................................................... 543
Chapter 16: Direct Memory Access Controller (DMA) Module .............................................................. 545
Chapter 16: Global: Changed index pointer to offset value ...................................................................... 545
Section 16.2.1: Added last sentence to paragraph ................................................................................ 547
Section 16.2.2: Changed second bullet ............................................................................................. 547
Section 16.2.3: Deleted last sentence in second paragraph ..................................................................... 548
Figure 16-5: Updated figure (changed Index Pointer to Offset Value) .......................................................... 549
Section 16.2.7: Added last two paragraphs ......................................................................................... 557
Table 16-2: Added table. Subsequent tables renumbered ....................................................................... 557
Section 16.2.9: Deleted fifth bullet (Bus error (BER) interrupt)................................................................... 559
Section 16.2.9: Added fifth bullet (External imprecise error on read) ........................................................... 559
Section 16.2.9: Added sixth bullet (External imprecise error on write) .......................................................... 559
Section 16.2.9: Changed NOTE. Deleted BER references ....................................................................... 559
Figure 16-14: MPU and PAR error signals corrected. Deleted BERA error signal. Added SCR block ..................... 560
Figure 16-15: Corrected to Frame Transfer. ........................................................................................ 560
Figure 16-15: Changed output of OR gate to FTCA ............................................................................... 560
Figure 16-15: Changed footnote. Deleted BER reference ........................................................................ 560
Section 16.2.12Changed fourth paragraph ......................................................................................... 561
Section 16.2.16: Updated second sentence in first paragraph ................................................................... 565
Section 16.2.17: Changed second paragraph ...................................................................................... 565
Section 16.3: Changed paragraph. Added base address for control packets .................................................. 566
Section 16.3: Deleted second NOTE ................................................................................................ 566
Table 16-8: Deleted BER Interrupt Mapping Register (BERMAP), BERA Interrupt Channel Offset Register
(BERAOFFSET), and BERB Interrupt Channel Offset Register (BERBOFFSET). Subsequent subsections, figures, and
tables renumbered ..................................................................................................................... 566
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Figure 16-19 to Figure 16-28: Updated register bit names to clarify that each register bit number corresponds to one
channel number ........................................................................................................................ 568
Table 16-11 to Table 16-20: Updated bit Descriptions to clarify register bit number corresponding to channel number 568
Figure 16-35 to Figure 16-51: Updated register bit names to clarify that each register bit number corresponds to one
channel number ........................................................................................................................ 568
Table 16-27 to Table 16-43: Updated bit Descriptions to clarify register bit number corresponding to channel number 568
Table 16-10: Updated Description of DMA_RES bit. (Writing a zero to this bit has no effect.) .............................. 568
Table 16-21: Updated Value column for all bits. Added 20h-3Fh = Reserved ................................................. 575
Table 16-22: Updated Value column for all bits. Added 20h-3Fh = Reserved ................................................. 576
Table 16-23: Updated Value column for all bits. Added 20h-3Fh = Reserved ................................................. 577
Table 16-24: Updated Value column for all bits. Added 20h-3Fh = Reserved ................................................. 578
Table 16-33: Changed Description of LFSINTENA bit = 1h to channel is enabled ........................................... 584
Table 16-38: Changed Description of BTCINTDIS bit for Value = 0 (Read). Channel is disabled .......................... 586
Table 16-38: Changed Description of BTCINTDIS bit for Value = 1 (Read). Channel is enabled........................... 586
Table 16-39: Updated Description of GINT bit. Deleted BER references....................................................... 587
Figure 16-48: Updated Read/Write value of bits to R/W1CP-0 .................................................................. 587
Figure 16-49: Updated Read/Write value of bits to R/W1CP-0 .................................................................. 588
Figure 16-50: Updated Read/Write value of bits to R/W1CP-0 .................................................................. 588
Figure 16-51: Updated Read/Write value of bits to R/W1CP-0 .................................................................. 589
Section 16.3.1.35: Added paragraph ................................................................................................ 589
Section 16.3.1.35: Deleted BER Interrupt Flag Register (BERFLAG) figure and BER Interrupt Flag Register (BERFLAG)
Field Descriptions table. Subsequent figures and tables renumbered .......................................................... 589
Table 16-44: Updated Value column of FTCA bit. Added 11h-3Fh = Reserved ............................................... 590
Table 16-45: Updated Value column of LFSA bit. Added 11h-3Fh = Reserved ............................................... 590
Table 16-46: Updated Value column of HBCA bit. Added 11h-3Fh = Reserved .............................................. 592
Table 16-47: Updated Value column of BTCA bit. Added 11h-3Fh = Reserved ............................................... 592
Table 16-48: Updated Value column of FTCB bit. Added 11h-3Fh = Reserved ............................................... 594
Table 16-49: Updated Value column of LFSB bit. Added 11h-3Fh = Reserved ............................................... 594
Table 16-50: Updated Value column of HBCB bit. Added 11h-3Fh = Reserved .............................................. 596
Table 16-51: Updated Value column of BTCB bit. Added 11h-3Fh = Reserved ............................................... 596
Figure 16-69: Updated Read/Write value of EDFLAG bit to R/W1C-0 .......................................................... 605
Figure 16-69: Updated LEGEND to include W1C.................................................................................. 605
Table 16-62: Corrected Value column of INT2AB and INT2ENA bits ........................................................... 606
Figure 16-71: Updated Read/Write value of bits to R/W1C-0 .................................................................... 608
Figure 16-71: Updated LEGEND to include W1C.................................................................................. 608
Table 16-63: Changed Description of bits. Added 0 (Write) = No effect ........................................................ 608
Table 16-64: Updated Description of STARTADDRESS bit. Added last sentence ............................................ 609
Table 16-65: Updated Description of ENDADDRESS bit. Added last two sentences ........................................ 609
Table 16-65: Added Note ............................................................................................................. 609
Table 16-66: Updated Description of STARTADDRESS bit. Added last sentence ............................................ 610
Table 16-67: Updated Description of ENDADDRESS bit. Added last two sentences ........................................ 610
Table 16-67: Added Note ............................................................................................................. 610
Table 16-68: Updated Description of STARTADDRESS bit. Added last sentence ............................................ 611
Table 16-69: Updated Description of ENDADDRESS bit. Added last two sentences ........................................ 611
Table 16-69: Added Note ............................................................................................................. 611
Table 16-70: Updated Description of STARTADDRESS bit. Added last sentence ............................................ 612
Table 16-71: Updated Description of ENDADDRESS bit. Added last two sentences ........................................ 612
Table 16-71: Added Note ............................................................................................................. 612
Table 16-75: Updated Value column and Description of CHAIN bit ............................................................. 615
Table 16-75: Changed Description of TTYPE bit. (A request triggers).......................................................... 615
Chapter 17: External Memory Interface (EMIF) ................................................................................. 619
Figure 17-1: Corrected pin names ................................................................................................... 621
Figure 17-1: Deleted EMIF_RNW pin ............................................................................................... 621
Table 17-3: Deleted EMIF_RNW pin ................................................................................................ 623
1824
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Revision History
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Figure 17-18: Updated reset value of RR bit to 60h ............................................................................... 657
Figure 17-24: Changed bit 1 to LT_MASK_SET ................................................................................... 663
Figure 17-25: Changed bit 1 to LT_MASK_CLR ................................................................................... 664
Figure 17-27: Corrected pin names .................................................................................................. 667
Chapter 18: Parameter Overlay Module (POM) ................................................................................. 675
Section 18.1: Deleted last two sentences in second paragraph ................................................................. 676
Section 18.1.2: Added subsection. Subsequent subsection renumbered ...................................................... 676
Figure 18-3: Updated LEGEND to include WP ..................................................................................... 680
Figure 18-6: Updated Read/Write value of TO bit to R/W1CP-0................................................................. 682
Figure 18-6: Updated LEGEND to include W1CP ................................................................................. 682
Table 18-5: Changed Description of TO bit ......................................................................................... 682
Figure 18-7: Updated LEGEND to include WP ..................................................................................... 683
Chapter 19: Analog To Digital Converter (ADC) Module ..................................................................... 695
Section 19.1: Changed first bullet .................................................................................................... 696
Section 19.1: Added third bullet in second paragraph............................................................................. 696
Figure 19-1: Changed bottom box to ADC2 ........................................................................................ 696
Section 19.2.3: Updated third and fifth sentences in third paragraph ........................................................... 698
Section 19.3.3: Added last sentence (reference) to fourth paragraph .......................................................... 700
Figure 19-4: Corrected register bit 20-16 name in ADG1BUFFER to G1_CHID .............................................. 702
Figure 19-5: Updated figure to show Reserved bits ............................................................................... 703
Figure 19-5: Corrected register bit 15 names in ADG1BUFFER and ADG2BUFFER ........................................ 703
Figure 19-10: Corrected Offset Address and register name for ADEVSR. ..................................................... 706
Section 19.7.3: Corrected register names in first sentence. (ADMAGINTENASET and ADMAGINTENACLR) ........... 712
Section 19.11.5: Changed paragraph ............................................................................................... 730
Figure 19-22: Changed bit 2 to Reserved and R-0 ................................................................................ 730
Figure 19-23: Added figure. Subsequent figures renumbered ................................................................... 730
Table 19-10: Deleted Bit column ..................................................................................................... 731
Table 19-10: Changed Description of EV_DATA_FMT bit. (This field is only applicable when the ADC module is
configured to be a 12-bit ADC module.) ............................................................................................. 731
Table 19-10: Corrected bit 2 name to EV_8BIT .................................................................................... 731
Table 19-10: Changed Description of EV_8BIT bit. (This bit is only applicable when the ADC module is configured to be a
10-bit ADC module.) ................................................................................................................... 731
Table 19-10: Changed Description of FRZ_EV bit. (The Event Group conversion is kept frozen while the Group1 or
Group2 conversion is active,) ......................................................................................................... 731
Table 19-10: Changed Description of FRZ_EV bit. Corrected ADEVST register to ADEVSR register ..................... 731
Section 19.11.6: Changed paragraph ............................................................................................... 733
Figure 19-24: Changed bit 2 to Reserved and R-0 ................................................................................ 733
Figure 19-25: Added figure. Subsequent figures renumbered ................................................................... 733
Table 19-11: Deleted Bit column ..................................................................................................... 734
Table 19-11: Changed Description of G1_DATA_FMT bit. (This field is only applicable when the ADC module is
configured to be a 12-bit ADC module.) ............................................................................................. 734
Table 19-11: Corrected bit 2 name to G1_8BIT .................................................................................... 734
Table 19-11: Changed Description of G1_8BIT bit. (This bit is only applicable when the ADC module is configured to be a
10-bit ADC module.) ................................................................................................................... 734
Table 19-11: Changed Description of FRZ_G1 bit. (The Group1 conversion is kept frozen while the Event Group or
Group2 conversion is active,) ......................................................................................................... 734
Table 19-11: Changed Description of FRZ_G1 bit. Corrected ADG1ST register to ADG1SR register ..................... 734
Section 19.11.7: Changed paragraph ............................................................................................... 736
Figure 19-26: Changed bit 2 to Reserved and R-0 ................................................................................ 736
Figure 19-26: Changed bit 0 to FRZ_G2 ............................................................................................ 736
Figure 19-27: Added figure. Subsequent figures renumbered ................................................................... 736
Table 19-12: Deleted Bit column ..................................................................................................... 737
Table 19-12: Changed Description of G2_DATA_FMT bit. (This field is only applicable when the ADC module is
configured to be a 12-bit ADC module.) ............................................................................................. 737
Table 19-12: Corrected bit 2 name to G2_8BIT .................................................................................... 737
SPNU499C – March 2018
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1825
Revision History
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Table 19-12: Changed Description of G2_8BIT bit. (This bit is only applicable when the ADC module is configured to be a
10-bit ADC module.) ................................................................................................................... 737
Table 19-12: Changed Description of FRZ_G2 bit. (The Group2 conversion is kept frozen while the Event Group or
Group1 conversion is active,) ......................................................................................................... 737
Table 19-12: Changed Description of FRZ_G2 bit. Corrected ADG2ST register to ADG2SR register ..................... 737
Table 19-25: Updated Value column and changed Description for DMA_EV_END bit ....................................... 750
Table 19-26: Updated Value column and changed Description for DMA_G1_END bit ....................................... 752
Table 19-27: Updated Value column and changed Description for DMA_G2_END bit ....................................... 754
Table 19-33: Changed last bullet in Description of EV_END bit ................................................................. 760
Table 19-34: Changed last bullet in Description of G1_END bit ................................................................. 761
Table 19-35: Changed last bullet in Description of G2_END bit ................................................................. 762
Table 19-36: Changed Reserved bits to 31-24 and EV_SEL bits to 23-0 ...................................................... 763
Table 19-37: Changed Reserved bits to 31-24 and G1_SEL bits to 23-0 ...................................................... 764
Table 19-38: Changed Reserved bits to 31-24 and G2_SEL bits to 23-0 ...................................................... 765
Section 19.11.34: Changed paragraph .............................................................................................. 766
Figure 19-55: Added figure. Subsequent figures renumbered ................................................................... 766
Table 19-39: Deleted Bit column ..................................................................................................... 766
Table 19-39: Changed Description of ADCALR bit ................................................................................ 766
Table 19-41: Changed Description of LAST_CONV bit for Value = 1. (A level higher than or equal to the midpoint
reference voltage) ...................................................................................................................... 767
Section 19.11.37: Changed paragraph .............................................................................................. 768
Table 19-42: Deleted Bit column ..................................................................................................... 768
Table 19-42: Changed Value column range of the EV_CHID bit to 1h-1Fh .................................................... 768
Section 19.11.38: Changed paragraph .............................................................................................. 769
Figure 19-61: Corrected register bit names ......................................................................................... 769
Table 19-43: Deleted Bit column ..................................................................................................... 769
Table 19-43: Changed Value column range of the G1_CHID bit to 1h-1Fh .................................................... 769
Section 19.11.39: Changed paragraph .............................................................................................. 770
Figure 19-63: Corrected register bit names ......................................................................................... 770
Table 19-44: Deleted Bit column ..................................................................................................... 770
Table 19-44: Changed Value column range of the G2_CHID bit to 1h-1Fh .................................................... 770
Section 19.11.40: Added first paragraph ............................................................................................ 771
Figure 19-64: Added figure. Subsequent figures renumbered ................................................................... 771
Figure 19-65: Added figure. Subsequent figures renumbered ................................................................... 771
Table 19-45: Added table. Subsequent tables renumbered ...................................................................... 771
Section 19.11.41: Added first paragraph ............................................................................................ 772
Figure 19-66: Added figure. Subsequent figures renumbered ................................................................... 772
Figure 19-67: Added figure. Subsequent figures renumbered ................................................................... 772
Table 19-46: Added table. Subsequent tables renumbered ...................................................................... 772
Section 19.11.42: Added first paragraph ............................................................................................ 773
Figure 19-68: Added figure. Subsequent figures renumbered ................................................................... 773
Figure 19-69: Added figure. Subsequent figures renumbered ................................................................... 773
Table 19-47: Added table. Subsequent tables renumbered ...................................................................... 773
Section 19.11.54: Changed paragraph .............................................................................................. 781
Figure 19-81: Added figure. Subsequent figures renumbered ................................................................... 781
Table 19-59: Deleted Bit column ..................................................................................................... 782
Table 19-59: Changed Description of MAG_THRx bit ............................................................................ 782
Section 19.11.55: Changed paragraph .............................................................................................. 783
Figure 19-83: Added figure. Subsequent figures renumbered ................................................................... 783
Table 19-60: Deleted Bit column ..................................................................................................... 783
Chapter 20: High-End Timer (N2HET) Module .................................................................................. 791
Section 20.2.5.4: Changed first sentence ........................................................................................... 811
Table 20-9: Changed Pull Control and Input Buffer = Enabled when device is under reset ................................. 823
Section 20.2.6: Corrected second bulleted item ................................................................................... 824
1826
Revision History
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Revision History
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Section 20.2.9: Updated first paragraph ............................................................................................ 828
Section 20.3.2: Added Hardware Angle Generator (HWAG) subsection. Subsequent figures and tables renumbered .. 833
Figure 20-56: Changed format ....................................................................................................... 856
Table 20-16: Updated Description of PPF and TO bits ........................................................................... 856
Table 20-17: Updated Description of LRPFC and HRPFC bits .................................................................. 858
Table 20-23: Updated Description of Write = 1. (Interrupt will be disabled.) ................................................... 861
Table 20-26: Changed Description of HETPRY bit ................................................................................ 864
Section 20.5: Added HWAG Registers section. Subsequent section, figures, and tables renumbered .................... 882
Table 20-73: Added cross references to instruction descriptions ................................................................ 898
Table 20-73: Added OR instruction .................................................................................................. 898
Table 20-73: Corrected sub-opcodes for ADC, ADD, and XOR instructions ................................................... 898
Table 20-74: Added SUB to Set/Reset column for Zero flag (Z) ................................................................. 899
Figure 20-121: Corrected register bit name for bit 6 (Init flag) ................................................................... 910
Section 20.6.3.8: Updated Description of CNT instruction. The data field [D31:7] is incremented unconditionally on each
execution of the instruction ........................................................................................................... 924
Table 20-87: Changed registers in Source and Destination(s) columns to register A, B, R, S, or T ........................ 941
Section 20.6.3.19: Updated Description of RCNT instruction. For example, choosing M = 100 allows the input period to be
expressed as a percentage (%) of the reference period .......................................................................... 956
Chapter 21: High-End Timer Transfer Unit (HTU) Module .................................................................... 969
Section 21.2: Updated third bullet in fifth paragraph. Added per request....................................................... 972
Section 21.2: Added fourth bullet in fifth paragraph ............................................................................... 972
Section 21.2.4.1: Updated first sentence in third paragraph ..................................................................... 979
Section 21.2.4.1: Updated fourth sentence in seventh paragraph. If the signal frequency would increase, then a wrong
pair [22,23] could be read ............................................................................................................. 980
Section 21.2.5: Updated second paragraph ........................................................................................ 981
Figure 21-13: Changed position of third rising edge in waveform ............................................................... 983
Section 21.4: Updated paragraph to include base addresses.................................................................... 986
Table 21-24: Corrected bit range of the Reserved bit to 31-10 and the INTTYPE0 bit to 9-8 ............................... 996
Table 21-25: Corrected bit range of the Reserved bit to 31-10 and the INTTYPE1 bit to 9-8 ............................... 997
Figure 21-31: Changed 2 LSBs to 0 ............................................................................................... 1002
Table 21-31: Updated Description of STARTADDRESS1 bit. Added last sentence ......................................... 1002
Figure 21-32: Changed 2 LSBs to 0 ............................................................................................... 1002
Table 21-32: Updated Description of ENDADDRESS1 bit. Added last sentences........................................... 1002
Table 21-33: Updated Description of CPNUM bit ................................................................................ 1003
Table 21-39: Updated Description of CPNUM0 and CPNUM1 bits ............................................................ 1008
Figure 21-40: Changed 2 LSBs to 0 ............................................................................................... 1011
Table 21-40: Updated Description of STARTADDRESS0 bit. Added last sentence ......................................... 1011
Figure 21-41: Changed 2 LSBs to 0 ............................................................................................... 1011
Table 21-41: Updated Description of ENDADDRESS0 bit. Added last sentences........................................... 1011
Section 21.5: Updated second paragraph to include base addresses ........................................................ 1012
Section 21.5.7: Updated paragraph ................................................................................................ 1018
Table 21-49: Corrected table title ................................................................................................... 1018
Chapter 22: General-Purpose Input/Output (GIO) Module .................................................................. 1021
Section 22.2: Corrected register names in second paragraph to GIOOFF1 and GIOOFF2 ................................ 1023
Figure 22-3: Moved figure location. Subsequent figures renumbered ......................................................... 1025
Section 22.3.1: Changed description of Data direction in first bullet ........................................................... 1025
Section 22.3.1: Changed description of Open drain in sixth bullet ............................................................. 1025
Section 22.3.1: Changed description of Pull select in eighth bullet ............................................................ 1026
Section 22.4.2: Changed last sentence ............................................................................................ 1028
Section 22.5: Changed third and fourth paragraph............................................................................... 1029
Table 22-1: Updated Offset column ................................................................................................ 1029
Table 22-1: Deleted GIODIN[C-H], GIODOUT[C-H], GIODSET[C-H], GIODCLR[C-H], GIOPDR[C-H], GIOPULDIS[C-H],
and GIOPSL[C-H] ..................................................................................................................... 1029
Section 22.5.1: Chnaged third sentence ........................................................................................... 1030
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Section 22.5.2: Changed paragraph ............................................................................................... 1031
Section 22.5.3: Changed paragraph ............................................................................................... 1032
Section 22.5.4: Changed paragraph ............................................................................................... 1033
Section 22.5.4.1: Changed NOTE. Deleted first sentence ...................................................................... 1033
Table 22-5: Updated Description of Read = 1 and Write = 1 for all bits ....................................................... 1033
Table 22-6: Updated Description of Read = 1 and Write = 1 for all bits ....................................................... 1034
Section 22.5.5: Changed paragraph ............................................................................................... 1035
Section 22.5.5: Added NOTE ....................................................................................................... 1035
Table 22-7: Updated Description of Read = 1 and Write = 1 for all bits ....................................................... 1035
Table 22-8: Updated Description of Write = 1 for all bits ........................................................................ 1037
Section 22.5.6: Added second sentence .......................................................................................... 1038
Figure 22-12: Updated Read/Write value of bits to R/W1C-0................................................................... 1038
Figure 22-12: Updated LEGEND to include W1C ................................................................................ 1038
Table 22-22: Changed Pull Control = Enabled when device is under reset .................................................. 1047
Chapter 23: FlexRay Module ...................................................................................................... 1048
Figure 23-28: Updated figure to include where interrupts are sent ............................................................ 1104
Figure 23-29: Updated title .......................................................................................................... 1106
Section 23.19.1: Updated first paragraph to include base address ............................................................ 1108
Section 23.19.1: Updated third paragraph to include base address of Transfer Configuration RAM ..................... 1108
Figure 23-32: Updated Read/Write value of bits to R/W1S-0 ................................................................... 1111
Figure 23-32: Updated LEGEND ................................................................................................... 1111
Figure 23-33: Updated Read/Write value of bits to R/W1S-0 ................................................................... 1111
Figure 23-33: Updated LEGEND ................................................................................................... 1111
Figure 23-34: Updated Read/Write value of IDLE bit to R/W1C-1 ............................................................. 1114
Figure 23-34: Updated LEGEND ................................................................................................... 1114
Section 23.19.1.12: Updated register bit names to reflect corresponding message buffer number ....................... 1119
Section 23.19.1.12: Updated Read/Write value of bits to R/W1C-0 ........................................................... 1119
Section 23.19.1.12: Updated LEGEND ............................................................................................ 1119
Table 23-29: Combined Transfer to System Memory Occurred (TSMO[1-4]) Field Descriptions tables into a single
table .................................................................................................................................... 1120
Section 23.19.1.13: Updated register bit names to reflect corresponding message buffer number ....................... 1121
Section 23.19.1.13: Updated Read/Write value of bits to R/W1C-0 ........................................................... 1121
Section 23.19.1.13: Updated LEGEND ............................................................................................ 1121
Table 23-30: Combined Transfer to Communication Controller Occurred (TCCO[1-4]) Field Descriptions tables into a
single table. ............................................................................................................................ 1122
Section 23.19.1.15: Corrected NOTE .............................................................................................. 1124
Figure 23-52: Updated Read/Write value of bits to R/W1C-0................................................................... 1125
Figure 23-52: Updated LEGEND ................................................................................................... 1125
Figure 23-53: Corrected register bit name for bits 10-8 and bits 6-4 .......................................................... 1127
Figure 23-54: Corrected register bit name for bits 10-8 and bits 6-4 .......................................................... 1128
Section 23.19.1.18: Updated register bit names to reflect corresponding message buffer number ....................... 1129
Section 23.19.1.19: Updated register bit names to reflect corresponding message buffer number ....................... 1133
Section 23.19.1.20: Updated register bit names to reflect corresponding message buffer number ....................... 1137
Section 23.19.1.21: Updated register bit names to reflect corresponding message buffer number ....................... 1141
Section 23.19.1.22: Updated register bit names to reflect corresponding message buffer number ....................... 1145
Section 23.19.1.23: Updated register bit names to reflect corresponding message buffer number ....................... 1149
Table 23-85: Updated register bit name for TSO bits 13-0. Corrected Value column for TSO bit ......................... 1153
Section 23.19.2: Added last paragraph to include base address .............................................................. 1155
Table 23-87: Updated table to add subsection cross-reference to Transmission Request Registers, New Data Registers,
and Message Buffer Status Changed Registers.................................................................................. 1156
Section 23.19.2.2.5: Updated paragraph .......................................................................................... 1175
Section 23.19.2.2.6: Updated paragraph .......................................................................................... 1177
Section 23.19.2.3.1: Corrected ALLOW_COLDSTART description after table ............................................... 1187
Section 23.19.2.3.1: Corrected RESET_STATUS_INDICATORS description after table ................................... 1187
1828
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Table 23-121: Corrected Value column for CCFC bit. ...........................................................................
Table 23-131: Updated table format ...............................................................................................
Table 23-132: Corrected Value column for SEC bit ..............................................................................
Table 23-134: Corrected Value column for CH bit ...............................................................................
Figure 23-154: Corrected Reset value of CL bit to 81h..........................................................................
Figure 23-155: Updated Read/Write value of POBF bit to R/W-0 ..............................................................
Table 23-146: Deleted Value column ..............................................................................................
Table 23-148: Corrected Value column for CHB, CHA bit ......................................................................
Table 23-149: Updated table. Changed order of CHA and CHB columns ....................................................
Chapter 24: Controller Area Network (DCAN) Module .......................................................................
Equation 36: Corrected maximum tolerance of equation for condition I .......................................................
Equation 37: Updated equation .....................................................................................................
Equation 38: Updated equation .....................................................................................................
Section 24.3.2.3: Changed tq = 1 µs ...............................................................................................
Equation 39: Updated equation .....................................................................................................
Equation 40: Updated equation .....................................................................................................
Table 24-2: Updated Description of DLC, Value = 0-8: Data Frame has 0-8 data bytes ...................................
Section 24.5.2: Changed first paragraph in NOTE. Added: At address 0x0000, message object number 64 is
located..................................................................................................................................
Section 24.16: Changed subsection ...............................................................................................
Section 24.17: Updated first paragraph to include base addresses ...........................................................
Table 24-6: Added Core Release Register ........................................................................................
Figure 24-20: Updated Read/Write value of PER bit to R/C-0 ..................................................................
Table 24-9: Updated Description of REC bit (Values from 0 to 127) ..........................................................
Table 24-11: Corrected Value column range of Int1ID and Int0ID bits to 1h-40h ............................................
Table 24-13: Corrected Value column range of Message Number bit to 1h-FFh ............................................
Table 24-13: Updated Description of Message Number bit. Only values 1h-40h are valid. Values 41h-FFh are
invalid ...................................................................................................................................
Section 24.17.8: Added subsection. Subsequent subsections, figures, and tables renumbered ..........................
Figure 24-27: Corrected register bit name to ABO_TIME .......................................................................
Table 24-15: Corrected register bit name to ABO_TIME ........................................................................
Table 24-21: Corrected Value column range of Message Number bit to 1h-40h ............................................
Table 24-24: Updated Description of EoB bit .....................................................................................
Section 24.17.24: Changed sixth paragraph ......................................................................................
Section 24.17.30: Changed first paragraph in NOTE. Writable only if Init bit of CAN Control Register is set ...........
Section 24.17.31: Changed first paragraph in NOTE. Writable only if Init bit of CAN Control Register is set ...........
Table 24-31: Changed the Func Bit description for Value = 1. (as an input to receive CAN data) ........................
Chapter 25: Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin Option (MibSPIP) ....
Chapter 25: Global: Changed SPISCS to SPICS ................................................................................
Section 25.1: Changed third and seventh bullets in second paragraph .......................................................
Section 25.2: Changed first sentence in second paragraph ....................................................................
Section 25.2: Added NOTE..........................................................................................................
Table 25-1: Changed SPIENA enabled description in Slave Mode ............................................................
Figure 25-6: Corrected figure title ..................................................................................................
Figure 25-6: Corrected bits D11-D8 to 1110 ......................................................................................
Figure 25-7: Corrected figure title ..................................................................................................
Section 25.2.9: Updated first two paragraphs.....................................................................................
Section 25.2.11.2: Added subsection The CSHOLD Bit in Slave Mode (Multi-buffered Mode) ............................
Section 25.2.12: Changed sixth sentence. Added T2EDELAY .................................................................
Section 25.2.13: Changed second sentence. Added C2EDELAY .............................................................
Section 25.8.1: Changed second sentence .......................................................................................
Section 25.8.1: Changed second sentence .......................................................................................
Section 25.9: Updated paragraph to include base addresses ..................................................................
Section 25.9: Global: Updated all VBUSPCLK signals to VCLK ...............................................................
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Table 25-7: Added SPIPC9 at address offset 68h ............................................................................... 1349
Table 25-9: Updated second bullet in Description of SPIEN bit. Added SPIDAT0 and SPIDAT1 ......................... 1351
Table 25-9: Changed Description of CLKMOD bit for Value = 1. (SPIENA is an input.) .................................... 1351
Figure 25-30: Updated Read/Write value of RXINTFLG, RXOVRNINTFLG, BITERRFLG, DESYNCFLG, PARERRFLG,
TIMEOUTFLG, and DLENERRFLG bits to R/W1C .............................................................................. 1355
Figure 25-30: Updated LEGEND to include W1C ................................................................................ 1355
Table 25-12: Corrected bit 2 name to PARERRFLG............................................................................. 1355
Table 25-14: Corrected Description of SIMODIR0 bit............................................................................ 1359
Table 25-20: Updated Description of all bits to clarify that bit is a pull control disable ...................................... 1368
Table 25-21: Updated Description of CLKPSEL, ENAPSEL, and SCSPSEL bits. 1 = Pull up ............................. 1369
Table 25-22: Changed Description of TXDATA bit. Added last Note .......................................................... 1371
Section 25.9.16: Added NOTE ...................................................................................................... 1372
Table 25-23: Updated Description of CSNR and TXDATA bits ................................................................ 1372
Table 25-24: Added table. Subsequent tables renumbered .................................................................... 1374
Table 25-25: Corrected Description of RXEMPTY bit. (SPIBUF to RXDATA) ................................................ 1375
Table 25-27: Corrected Value column for all bits to 0-FFh ...................................................................... 1377
Table 25-27: Updated Description of C2TDELAY bit. Deleted first NOTE .................................................... 1377
Table 25-27: Updated Description of T2CDELAY bit. Deleted first and third NOTE......................................... 1377
Figure 25-49: Updated reset value of CSDEF bit to FFh ........................................................................ 1380
Table 25-29: Updated formula in Description of PRESCALE bit. (PRESCALEx + 1) ....................................... 1381
Section 25.9.24: Added subsection. Subsequent subsections, figures, and tables renumbered .......................... 1386
Table 25-35: Updated bit Descriptions to clarify register bit number corresponding to TG number ....................... 1391
Table 25-36: Updated bit Descriptions to clarify register bit number corresponding to TG number ....................... 1392
Table 25-36: Changed Description of CLRINTENRDY and CLRINTENSUS bits for Value = 1 (Write). The interrupt does
not get generated ..................................................................................................................... 1392
Table 25-37: Updated bit Descriptions to clarify register bit number corresponding to TG number ....................... 1393
Table 25-38: Updated bit Descriptions to clarify register bit number corresponding to TG number ....................... 1394
Table 25-38: Changed Description of CLRINTLVLRDY and CLRINTLVLSUS bits for Value = 1 (Write). Clear the TGx
interrupt INT0 .......................................................................................................................... 1394
Table 25-39: Updated bit Descriptions to clarify register bit number corresponding to TG number ....................... 1395
Table 25-40: Changed Description of TICKENA bit for Value = 1. Deleted second sentence ............................. 1396
Table 25-40: Corrected Value column of CLKCTRL bit ......................................................................... 1396
Table 25-41: Changed Note in LPEND bit ........................................................................................ 1397
Table 25-43: Updated Description of ONESHOT bit. Added Note ............................................................. 1401
Table 25-43: Updated Description of ICOUNTx bit. Added last sentence to second paragraph ........................... 1401
Figure 25-73: Updated Read/Write value of SCS_FAIL_FLG bit to R/W1C .................................................. 1409
Figure 25-73: Updated LEGEND to include W1C ................................................................................ 1409
Figure 25-74: Changed format ...................................................................................................... 1411
Figure 25-75: Changed format ...................................................................................................... 1413
Table 25-53: Corrected Description of EPRESCALE_FMT3 bit ................................................................ 1413
Section 25.10.2: Updated paragraph to include base addresses .............................................................. 1416
Section 25.10.3: Added NOTE ...................................................................................................... 1417
Table 25-55: Updated Description of CSHOLD and TXDATA bits ............................................................. 1417
Table 25-55: Updated Description of CSNR bit................................................................................... 1417
Table 25-56: Added table. Subsequent tables renumbered .................................................................... 1419
Table 25-57: Corrected bits descriptions (SPIBUF to RXRAM) ................................................................ 1420
Section 25.12.3: Deleted table from subsection .................................................................................. 1428
Section 25.12.4: Deleted table from subsection .................................................................................. 1428
Chapter 26: Serial Communication Interface (SCI)/Local Interconnect Network (LIN) Module ..................... 1429
Section 26.4.1: Changed third paragraph ......................................................................................... 1446
Section 26.4.2: Changed second sentence in second paragraph .............................................................. 1446
Section 26.5: Updated both paragraphs ........................................................................................... 1447
Section 26.5: Updated procedure in second paragraph ......................................................................... 1447
Section 26.5.1.1: Updated first and last paragraphs ............................................................................. 1447
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Revision History
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Section 26.5.1.2: Updated paragraph .............................................................................................. 1448
Section 26.5.2.1: Updated first and last paragraphs ............................................................................. 1448
Section 26.5.2.1: Changed number 2 in second paragraph to Transmit Interrupt ........................................... 1448
Section 26.5.2.2: Updated paragraph .............................................................................................. 1448
Section 26.10: Updated paragraph ................................................................................................. 1469
Section 26.10: Updated procedure ................................................................................................. 1469
Section 26.10.1.1: Updated first and last paragraphs............................................................................ 1469
Section 26.10.1.2: Updated paragraph ............................................................................................ 1470
Section 26.10.2.1: Updated first and last paragraphs............................................................................ 1470
Section 26.10.2.1: Changed number 2 in second paragraph to Transmit Interrupt .......................................... 1470
Section 26.10.2.2: Updated paragraph ............................................................................................ 1471
Section 26.13: Updated second paragraph to include base address .......................................................... 1474
Table 26-11: Updated Value column of COMM MODE bit, SCI mode 0 = Idle-line mode is used.; 1 = Address-bit mode is
used .................................................................................................................................... 1476
Table 26-15: Updated Description of SET RX DMA bit .......................................................................... 1482
Figure 26-31: Corrected SCICLEARINT register bit name for bit 30. (CLR PBE INT) ...................................... 1485
Table 26-27: Corrected bit name in Note to SET TX INT ....................................................................... 1507
Figure 26-48: Corrected SCIPIO6 register bit names for bits 2 and 1 (PDR) ................................................ 1513
Figure 26-58: Updated Read/Write value of MBR bit to R/WL-0DACh ........................................................ 1520
Section 26.14.2: Changed first bullet............................................................................................... 1523
Table 26-48: Changed Pull Control = Enabled when device is under reset .................................................. 1524
Chapter 27: Serial Communication Interface (SCI) Module ................................................................. 1525
Section 27.1.1: Changed seventh bullet (deleted isosynchronous mode) .................................................... 1526
Section 27.1.2: Changed Baud Clock Generator bullet to VCLK ............................................................... 1526
Figure 27-1: Changed signals to SCITX and SCIRX............................................................................. 1527
Equation 56: Updated equation. Changed VBUSPCLK to VCLK .............................................................. 1530
Equation 57: Updated equation. Changed VBUSPCLK to VCLK .............................................................. 1530
Section 27.3.4: Updated first sentence in second paragraph ................................................................... 1535
Section 27.5: Updated both paragraphs ........................................................................................... 1537
Section 27.5: Updated procedure in second paragraph ......................................................................... 1537
Section 27.5.1: Updated last paragraph ........................................................................................... 1537
Section 27.5.2: Updated last paragraph ........................................................................................... 1538
Section 27.5.2: Changed number 2 in second paragraph to Transmit Interrupt ............................................. 1538
Section 27.7: Updated paragraph to include base address ..................................................................... 1540
Equation 58: Updated equation. Changed VBUSPLCK to VCLK .............................................................. 1558
Equation 59: Updated equation. Changed VBUSPLCK to VCLK .............................................................. 1558
Section 27.7.22: Deleted first sentence in paragraph. Moved NOTE .......................................................... 1568
Section 27.8.2: Changed first bullet ................................................................................................ 1570
Table 27-33: Changed Pull Control = Enabled when device is under reset .................................................. 1571
Chapter 28: Inter-Integrated Circuit (I2C) Module ............................................................................ 1572
Section 28.6: Updated paragraph to include base address ..................................................................... 1588
Section 28.6: Deleted NOTE ........................................................................................................ 1588
Figure 28-15: Updated Read/Write value of SDIR, NACKSNT, SCD, RXRDY, ARDY, NACK, and AL bits to R/W1C0 ......................................................................................................................................... 1591
Figure 28-15: Updated LEGEND to include W1C ................................................................................ 1591
Table 28-7: Changed fourth paragraph in Description of XSMT bit ............................................................ 1591
Section 28.6.21: Changed paragraph .............................................................................................. 1605
Section 28.6.22: Changed paragraph .............................................................................................. 1606
Section 28.6.23: Changed paragraph .............................................................................................. 1606
Table 28-32: Updated Description of SDAPDR and SCLPDR bits. 0 = disabled; 1 = enabled ............................ 1606
Table 28-32: Updated Description of SDAPDR and SCLPDR bits. 0 = enabled; 1 = disabled ............................ 1606
Section 28.6.24: Changed paragraph .............................................................................................. 1607
Section 28.6.25: Changed paragraph .............................................................................................. 1607
Table 28-35: Changed Pull Control = Enabled when device is under reset .................................................. 1608
SPNU499C – March 2018
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Chapter 29: EMAC/MDIO Module.................................................................................................
Figure 29-7: Added figure. Subsequent figures renumbered ...................................................................
Figure 29-8: Added figure. Subsequent figures renumbered ...................................................................
Figure 29-9: Added figure. Subsequent figures renumbered ...................................................................
Figure 29-28: Changed default value of REV bit to 0007 0105h ...............................................................
Table 29-25: Changed Value column of REV bit to 0007 0105h ...............................................................
Table 29-68: Changed Description of GMIIEN bit ................................................................................
Chapter 30: Data Modification Module (DMM) .................................................................................
Figure 30-22: Updated Read/Write value of all bits to R/WP-0 .................................................................
Figure 30-22: Updated LEGEND to includ e WP .................................................................................
Table 30-22: Changed Description of all bits to Privilege mode (write) .......................................................
Figure 30-23: Updated Read/Write value of all bits to R/WP-0 .................................................................
Figure 30-23: Updated LEGEND to include WP ..................................................................................
Table 30-23: Changed Description of all bits to Privilege mode (write) .......................................................
Figure 30-24: Updated Read/Write value of all bits to R/WP-0 .................................................................
Figure 30-24: Updated LEGEND to include WP ..................................................................................
Figure 30-25: Updated Read/Write value of all bits to R/WP-0 .................................................................
Figure 30-25: Updated LEGEND to include WP ..................................................................................
Table 30-25: Changed Description of all bits to Privilege mode (write) .......................................................
Figure 30-26: Updated Read/Write value of all bits to R/WP-0 .................................................................
Figure 30-26: Updated LEGEND to include WP ..................................................................................
Table 30-26: Changed Description of all bits to Privilege mode (write) .......................................................
Figure 30-27: Updated Read/Write value of all bits to R/WP-0 .................................................................
Figure 30-27: Updated LEGEND to include WP ..................................................................................
Table 30-27: Changed Description of all bits to Privilege mode (write) .......................................................
Table 30-27: Changed Description of CLKCLR and SYNCCLR bits. Corrected bits to CLKOUT and SYNCOUT ......
Figure 30-28: Updated Read/Write value of all bits to R/WP-0 .................................................................
Figure 30-28: Updated LEGEND to include WP ..................................................................................
Table 30-28: Changed Description of all bits to Privilege mode (write) .......................................................
Figure 30-29: Updated Read/Write value of all bits to R/WP-x .................................................................
Figure 30-29: Updated LEGEND to include WP ..................................................................................
Table 30-29: Changed Description of all bits to Privilege mode (write) .......................................................
Figure 30-30: Updated Read/Write value of all bits to R/WP-1 .................................................................
Figure 30-30: Updated LEGEND to include WP ..................................................................................
Table 30-30: Changed Description of all bits to Privilege mode (write) .......................................................
Chapter 31: RAM Trace Port (RTP) ..............................................................................................
Figure 31-11: Updated Read/Write value of OVFPER, OVF2, and OVF1 bits to R/W1CP-0 ..............................
Table 31-16: Updated Description of bits 15-0 ...................................................................................
Table 31-17: Updated Description of bits 15-0 ...................................................................................
Table 31-18: Updated Description of bits 15-0 ...................................................................................
Table 31-19: Updated Description of DATAOUT bits 15-0 ......................................................................
Table 31-20: Updated Description of DATASET bits 15-0 ......................................................................
Table 31-21: Updated Description of ENACLR bit ...............................................................................
Table 31-21: Updated Description of DATACLR bits 15-0 ......................................................................
Table 31-22: Updated Description of DATAPDR bits 15-0 ......................................................................
Table 31-23: Updated Description of DATADIS bits 15-0 .......................................................................
Table 31-24: Updated Description of DATAPSEL bits 15-0.....................................................................
Chapter 32: eFuse Controller .....................................................................................................
Section 32.4: Changed all register LEGENDs. Value of reset n changed from "after reset" to "after power-on reset
(nPORRST)" ...........................................................................................................................
Figure 32-3: Updated Read/Write value of Reserved bits 9-0 to R-x ..........................................................
Table 32-4: Changed Description of Reserved bits 9-0 .........................................................................
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