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DRV8305-Q1
SLVSD12D – MAY 2015 – REVISED JULY 2019
DRV8305-Q1 Three-Phase Automotive Smart Gate Driver With Three Integrated Current
Shunt Amplifiers and Voltage Regulator
1 Features
3 Description
•
•
The DRV8305-Q1 device is a gate driver IC for threephase motor-drive applications. The device provides
three high-accuracy half-bridge drivers, each capable
of driving a high-side and low-side N-channel
MOSFET. A charge pump driver supports 100% duty
cycle and low-voltage operation for cold crank
situations. The device can tolerate load dump
voltages up to 45-V.
1
•
•
•
•
•
•
•
•
•
•
•
•
AEC-Q100 qualified for automotive applications
Ambient operating temperature ranges:
– Temperature grade 0 (E): –40°C to +150°C
– Temperature grade 1 (Q): –40°C to +125°C
4.4-V to 45-V operating voltage
1.25-A and 1-A Peak gate drive currents
Smart gate drive architecture (IDRIVE & TDRIVE)
Programmable high- and low-side slew-rate
control
Charge-pump gate driver for 100% duty cycle
Three integrated current-shunt amplifiers
Integrated 50-mA LDO (3.3-V and 5-V option)
3-PWM or 6-PWM input control up to 200 kHz
Single PWM-mode commutation capability
Serial Peripheral Interface (SPI) for device
settings and fault reporting
Thermally-enhanced 48-Pin HTQFP
Protection features:
– Fault diagnostics and MCU watchdog
– Programmable dead-time control
– MOSFET shoot-through prevention
– MOSFET VDS overcurrent monitors
– Gate-driver fault detection
– Reverse battery-protection support
– Limp home-mode support
– Overtemperature warning and shutdown
The DRV8305-Q1 device includes three bidirectional
current-shunt amplifiers for accurate low-side current
measurements that support variable gain settings and
an adjustable offset reference.
The DRV8305-Q1 device has an integrated voltage
regulator to support an MCU or other system power
requirements. The voltage regulator can be interfaced
directly with a LIN physical interface to allow lowsystem standby and sleep currents.
The gate driver uses automatic handshaking when
switching to prevent current shoot through. The VDS
of both the high-side and low-side MOSFETs is
accurately sensed to protect the external MOSFETs
from overcurrent conditions. The SPI provides
detailed fault reporting, diagnostics, and device
configurations such as gain options for the current
shunt amplifier, individual MOSFET overcurrent
detection, and gate-drive slew-rate control.
Device Options:
• DRV8305NQ: Grade 1 with voltage reference
• DRV83053Q: Grade 1 with 3.3-V, 50-mA LDO
• DRV83055Q: Grade 1 with 5-V, 50-mA LDO
• DRV8305NE: Grade 0 with voltage reference
2 Applications
•
•
•
Device Information
Three-phase BLDC and PMSM motors
Automotive fuel and water pumps
Automotive fans and blowers
PART NUMBER
DRV8305-Q1
PACKAGE
HTQFP (48)
(1)
BODY SIZE (NOM)
7.00 mm × 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
4.4 to 45 V
MCU
PWM
SPI
DRV8305-Q1
Automotive
3-Phase
Brushless
Gate Driver
Gate Drive
LDO
Sense
Shunt Amps
nFAULT
50-mA LDO
Shunt Amps
N-Channel MOSFETs
EN_GATE
M
Protection
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRV8305-Q1
SLVSD12D – MAY 2015 – REVISED JULY 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
7
1
1
1
2
4
6
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 7
Thermal Information .................................................. 7
Electrical Characteristics........................................... 8
SPI Timing Requirements (Slave Mode Only) ........ 14
Typical Characteristics ............................................ 15
Detailed Description ............................................ 16
7.1
7.2
7.3
7.4
7.5
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
16
17
18
33
35
7.6 Register Maps ......................................................... 37
8
Application and Implementation ........................ 45
8.1 Application Information............................................ 45
8.2 Typical Application .................................................. 46
9
Power Supply Recommendations...................... 50
9.1 Power Supply Consideration in Generator Mode ... 50
9.2 Bulk Capacitance ................................................... 50
10 Layout................................................................... 52
10.1 Layout Guidelines ................................................. 52
10.2 Layout Example .................................................... 52
11 Device and Documentation Support ................. 53
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
53
53
53
53
53
53
12 Mechanical, Packaging, and Orderable
Information ........................................................... 53
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (September 2017) to Revision D
Page
•
Added content to the VREG pin description........................................................................................................................... 5
•
Added ESD classification levels to the ESD Ratings table .................................................................................................... 6
•
Added the VREG Reference Voltage Input (DRV8305N) section ....................................................................................... 48
•
Added the Power Supply Consideration in Generator Mode section ................................................................................... 50
Changes from Revision B (May 2016) to Revision C
Page
•
Added transient specification for GHx, SLx, SPx, and SNx ................................................................................................... 6
•
Changed SPx and SNx rating from -2 V to -3 V..................................................................................................................... 6
•
Changed the test condition for the VAVDD_UVLO, VVCPH_UVFL, VVCPH_UVLO2, and VVCP_LSD_UVLO2 parameters in the
Electrical Characteristics table ............................................................................................................................................ 11
•
Changed the maximum VAVDD_UVLO and VPVDD_UVLO2 parameters in the Electrical Characteristics table ............................. 11
•
Moved the External Components table from the Pin Configuration and Functions section to the Feature Description
section .................................................................................................................................................................................. 18
•
Added the description for latch fault reset methods to the Undervoltage Warning (UVFL), Undervoltage Lockout
(UVLO), and Overvoltage (OV) Protection section............................................................................................................... 32
•
Changed the description of FLIP_OTSD register bit in the IC Operation Register Description ........................................... 42
•
Added the Receiving Notification of Documentation Updates section ................................................................................. 53
Changes from Revision A (March 2016) to Revision B
•
2
Page
Changed from PRODUCT PREVIEW to Production Data and released full data sheet........................................................ 1
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DRV8305-Q1
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SLVSD12D – MAY 2015 – REVISED JULY 2019
Changes from Original (May 2015) to Revision A
Page
•
Device preview datasheet updated with preliminary electrical characteristics and functional descriptions ........................... 1
•
Updated the y-axis units to µA for Figure 4.......................................................................................................................... 15
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3
DRV8305-Q1
SLVSD12D – MAY 2015 – REVISED JULY 2019
www.ti.com
5 Pin Configuration and Functions
VCPH
VCP_LSD
37
38
CP2H
39
PVDD
CP2L
40
41
CP1L
42
VDRAIN
CP1H
43
44
GND
45
WAKE
DVDD
46
47
48
VREG
PHP Package
48-Pin HTQFP
Top View
EN_GATE
1
36
GHA
INHA
2
35
SHA
INLA
3
34
SLA
INHB
4
33
GLA
INLB
5
32
GLB
INHC
6
31
SLB
INLC
7
30
SHB
nFAULT
8
29
GHB
nSCS
9
28
GHC
SDI
10
27
SHC
SDO
11
26
SLC
SCLK
12
25
GLC
21
SN2
24
20
SP3
SP1
19
SN3
23
18
SO3
SN1
17
SO2
22
16
SO1
SP2
15
14
GND
AVDD
13
PWRGD
PowerPAD
(GND)
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
EN_GATE
1
I
Enable gate
Enables the gate driver and current shunt amplifiers; internal
pulldown.
INHA
2
I
Bridge PWM input
PWM input signal for bridge A high-side.
INLA
3
I
Bridge PWM input
PWM input signal for bridge A low-side.
INHB
4
I
Bridge PWM input
PWM input signal for bridge B high-side.
INLB
5
I
Bridge PWM input
PWM input signal for bridge B low-side.
INHC
6
I
Bridge PWM input
PWM input signal for bridge C high-side.
INLC
7
I
Bridge PWM input
PWM input signal for bridge C low-side.
nFAULT
8
OD
Fault indicator
When low indicates a fault has occurred; open drain;
external pullup to MCU power supply needed (1 kΩ to 10
kΩ).
nSCS
9
I
SPI chip select
Select/enable for SPI; active low.
SDI
10
I
SPI input
SPI input signal.
SDO
11
O
SPI output
SPI output signal.
SCLK
12
I
SPI clock
SPI clock signal.
PWRGD
13
OD
Power good
VREG and MCU watchdog fault indication; open drain;
external pullup to MCU power supply needed (1 kΩ to 10
kΩ).
GND
14, 45
P
Device ground
Must be connected to ground.
AVDD
15
P
Analog regulator
5-V internal analog supply regulator; bypass to GND with a
6.3-V, 1-µF ceramic capacitor.
SO1
16
O
Current amplifier output
Output of current sense amplifier 1.
SO2
17
O
Current amplifier output
Output of current sense amplifier 2.
SO3
18
O
Current amplifier output
Output of current sense amplifier 3.
4
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DRV8305-Q1
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SLVSD12D – MAY 2015 – REVISED JULY 2019
Pin Functions (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
SN3
19
I
Current amplifier negative input
Negative input of current sense amplifier 3.
SP3
20
I
Current amplifier positive input
Positive input of current sense amplifier 3.
SN2
21
I
Current amplifier negative input
Negative input of current sense amplifier 2.
SP2
22
I
Current amplifier positive input
Positive input of current sense amplifier 2.
SN1
23
I
Current amplifier negative input
Negative input of current sense amplifier 1.
SP1
24
I
Current amplifier positive input
Positive input of current sense amplifier 1.
GLC
25
O
Low-side gate driver
Low-side gate driver output for half-bridge C.
SLC
26
I
Low-side source connection
Low-side source connection for half-bridge C.
SHC
27
I
High-side source connection
High-side source connection for half-bridge C.
GHC
28
O
High-side gate driver
High-side gate driver output for half-bridge C.
GHB
29
O
High-side gate driver
High-side gate driver output for half-bridge B.
SHB
30
I
High-side source connection
High-side source connection for half-bridge B.
SLB
31
I
Low-side source connection
Low-side source connection for half-bridge B.
GLB
32
O
Low-side gate driver
Low side gate driver output for half-bridge B.
GLA
33
O
Low-side gate driver
Low-side gate driver output for half-bridge A.
SLA
34
I
Low-side source connection
Low-side source connection for half-bridge A.
SHA
35
I
High-side source connection
High-side source connection for half-bridge A.
GHA
36
O
High-side gate driver
High-side gate driver output for half-bridge A.
VCP_LSD
37
P
Low-side gate driver regulator
Internal voltage regulator for low-side gate driver; connect 1µF capacitor to GND.
VCPH
38
P
High-side gate driver regulator
Internal charge pump for high-side gate driver; connect 2.2µF capacitor to PVDD.
CP2H
39
P
CP2L
40
P
Charge pump flying capacitor
Flying capacitor for charge pump; connect 0.047-µF
capacitor between CP2H and CP2L.
PVDD
41
P
Power supply
Device power supply; minimum 4.7-µF ceramic capacitor to
GND.
CP1L
42
P
CP1H
43
P
Charge pump flying capacitor
Flying capacitor for charge pump; connect 0.047-µF
capacitor between CP1H and CP1L.
VDRAIN
44
P
High-side drain
High-side MOSFET drain connection; common for all three
half bridges.
DVDD
46
P
Digital regulator
3.3-V internal digital-supply regulator; bypass to GND with a
6.3-V, 1-µF ceramic capacitor.
WAKE
47
I
Wake up from sleep control pin
High voltage tolerant input pin to wake-up device from
SLEEP; pin cannot be used to disable LDO; driver needs to
be enabled and disabled separately.
VREG
GND
48
P
VREG/VREF
Dual purpose pin based on part number; also supplies
internal amplifier reference voltage and SDO pullup.
VREG: 3.3-V or 5-V, 50-mA LDO; connect 1-µF to GND.
VREF: Reference voltage; LDO disabled.
If PVDD voltage is lower than VREF pin voltage, there is a
current path from VREF to PVDD through the internal LDO.
The current must be limited to 50 mA by the system.
PPAD
P
Device ground
Must be connected to ground.
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SLVSD12D – MAY 2015 – REVISED JULY 2019
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6 Specifications
6.1 Absolute Maximum Ratings
over operating temperature range with respect to GND (unless otherwise noted) (1)
Power supply pin voltage (PVDD)
MIN
MAX
UNIT
–0.3
45
V
Power supply pin voltage ramp rate (PVDD)
0
2
V/µs
High-side charge pump pin voltage (VCPH)
–0.3
PVDD + 12
V
Low-side regulator pin voltage (VCP_LSD)
–0.3
12
V
Charge pump 1 positive switching pin voltage (CP1H)
PVDD – 1.5
PVDD + 12
V
Charge pump 2 positive switching pin voltage (CP2H)
PVDD – 3
PVDD + 12
V
–0.3
PVDD
V
Charge pump negative switching pin voltage (CPxL)
High-side gate driver pin voltage (GHx)
–5
57
V
–0.3
15
V
Low-side gate driver pin voltage (GLx)
–3
12
V
High-side gate driver source voltage (SHx)
–5
45
V
Transient 200-ns high-side gate driver source voltage (SHx)
–7
45
V
High-side gate driver source voltage (SHx)
–5
PVDD + 5
V
Low-side gate driver source voltage (SLx)
–3
5
V
Gate-to-source voltage difference (GHx-SHx), (GLx-SLx)
Transient 200-ns low-side gate driver source voltage (SLx)
–5
5
V
Drain pin voltage (VDRAIN)
–0.3
45
V
Control pin voltage (INHx, INLx, EN_GATE, SCLK, SDI, SCS, SDO, nFAULT, PWRGD)
–0.3
5.5
V
Wake pin voltage (WAKE)
–0.3
45
V
Sense amplifier voltage (SPx, SNx)
–3
5
V
Transient 200-ns sense amplifier voltage (SPx, SNx)
–5
5
V
Sense amplifier output pin voltage (SOx)
–0.3
5.5
V
Externally applied reference voltage, DRV8305N (VREG)
–0.3
5.5
V
0
100
µA
Internal digital regulator voltage (DVDD)
–0.3
3.6
V
Internal analog regulator voltage (AVDD)
Externally applied reference sink current, DRV8305N (VREG)
–0.3
5.5
V
Open drain pins sink current (nFAULT, PWRGD)
0
7
mA
Wake pin sink current (WAKE) – limit current with external resistor
0
1
mA
DRV8305xQPHPQ1
–40
150
°C
DRV8305xEPHPQ1 (2) (3)
–40
175
°C
–55
150
°C
Junction temperature, TJ
Storage temperature, Tstg
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
IC is designed to be operational up to TJ = 175°C. Internal overtemperature shutdown will be disabled by default on the
DRV8305xEPHPQ1.
Because lifetime degrades exponentially at higher temperatures, operation between TJ = 150°C to 175°C must be limited to transient
and infrequent events. For transient events between TJ = 150°C to 175°C for a total of 10 hours over lifetime, no degradation in lifetime
is expected. Contact TI for lifetime impact if the use case requires TJ = 150°C to 175°C greater than 10 hours.
6.2 ESD Ratings
V(ESD)
(1)
6
Electrostatic
discharge
VALUE
UNIT
Human-body model (HBM), per AEC Q100-002 (1)
HBM Classification Level 2
±2000
V
Charged-device model (CDM), per AEC Q100-011
CDM Classification Level C4A
±500
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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SLVSD12D – MAY 2015 – REVISED JULY 2019
6.3 Recommended Operating Conditions
over operating temperature range (unless otherwise noted)
MIN
MAX
UNIT
PVDD
Power supply voltage
4.4
45
PVDD
Power supply voltage for voltage regulator operation
4.3
45
V
VCPH
Charge pump external load current
0
30
mA
VCP_LSD
Low-side regulator external load current
0
30
mA
IGATE
Total average gate drive current (HS + LS)
0
30
mA
fgate
Operating switching frequency of gate driver
0
200
kHz
VREG
Voltage regulator external load current (regulator enabled device options)
0
50
mA
CO_OPA
Maximum external capacitive load on shunt amplifier output (without
external resistor)
0
60
pF
InFAULT
nFAULT sink current (nFAULT = 0.3 V)
TA
TJ
V
0
7
mA
Operating ambient temperature, DRV8305xQPHPQ1
–40
125
°C
Operating ambient temperature, DRV8305xEPHPQ1
–40
150
°C
Operating junction temperature, DRV8305xQPHPQ1
–40
150
°C
Operating junction temperature, DRV8305xEPHPQ1
–40
175
°C
6.4 Thermal Information
DRV8305-Q1
THERMAL METRIC
(1)
PHP (HTQFP)
UNIT
48 PINS
RθJA
Junction-to-ambient thermal resistance
26.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
12.9
°C/W
RθJB
Junction-to-board thermal resistance
7.6
°C/W
ψJT
Junction-to-top characterization parameter
0.3
°C/W
ψJB
Junction-to-board characterization parameter
7.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.6
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
PVDD = 4.4 to 45 V, DRV8305xQ: TJ = –40°C to 150°C, DRV8305xE: TJ = –40°C to 175°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLIES (PVDD, DVDD, AVDD)
4.4
45
V
4.3
45
V
VPVDD
PVDD operating voltage
IPVDD_Operating
PVDD operating supply
current
EN_GATE = HIGH; VREG no load;
outputs HI-Z
20
mA
IPVDD_Standby
PVDD standby supply
current
EN_GATE = LOW; VREG no load
5
mA
IPVDD_Sleep
PVDD sleep supply current
VAVDD
Internal regulator voltage
VDVDD
Internal regulator voltage
Voltage regulator (VREG) operational
EN_GATE = LOW; Sleep Mode;
TJ = –40 to 150 °C
60
EN_GATE = LOW; Sleep Mode;
TJ = 150 to 175 °C
200
μA
250
uA
5.15
V
PVDD = 5.3 to 45 V
4.85
5
PVDD = 4.4 to 5.3 V
PVDD – 0.4
PVDD
V
3.3
V
VOLTAGE REGULATOR (3.3-V or 5-V VREG)
PVDD = 5.4 to 45 V
VVREG
VREG DC output voltage
PVDD = 4.4 to 5.3 V; 5-V VREG
PVDD = 4.4 to 5.3 V; 3.3-V VREG
VLineReg
VLoadReg
Line regulation
Load regulation
VREG × 0.97
VREG VREG × 1.03
V
PVDD – 0.4
PVDD
V
VREG × 0.97
VREG VREG × 1.03
V
5.3 V ≤ VIN ≤ 12 V; IO = 1 mA
20
100 μA ≤ IOUT ≤ 50 mA; 5-V VREG
50
150
mV
100 μA ≤ IOUT ≤ 50 mA; 3.3-V VREG
30
100
mV
mV
LOGIC-LEVEL INPUTS (INHx, INLx, EN_GATE, SCLK, nSCS)
VIL
Input logic low voltage
0
0.8
V
VIH
Input logic high voltage
2
5
V
RPD
Internal pulldown resistor
To GND
100
kΩ
CONTROL OUTPUTS (nFAULT, SDO, PWRGD)
VOL
Output logic low voltage
nFAULT; SDO; PWRGD; IO = 5 mA
VOH
Output logic high voltage
SDO; IO = 5 mA
IOH
Output logic high leakage
VO = 3.3 V
0.5
VREG – 0.9
V
V
–1
1
μA
HIGH VOLTAGE TOLERANT LOGIC INPUT (WAKE)
VIL_WAKE
Output logic low voltage
1.1
1.45
V
VIH_WAKE
Output logic high voltage
1.46
1.8
V
10.7
V
GATE DRIVE OUTPUT (GHx, GLx)
VGHS
VGLS
High-side gate driver Vgs
voltage
Low-side gate driver Vgs
voltage
VPVDD = 8 to 45 V; IGATE < 30 mA
9
10
VPVDD = 5.5 to 8 V; IGATE < 10 mA
7
10.7
V
VPVDD = 4.4 to 5.5 V; IGATE < 5 mA
5
9
V
VPVDD = 8 to 45 V; IGATE < 30 mA
9
10.7
V
VPVDD = 5.5 to 8 V; IGATE < 10 mA
9
10.7
V
VPVDD = 4.4 to 5.5 V; IGATE < 5 mA
8
10.7
V
10
PEAK CURRENT DRIVE TIMES (GHx, GLx)
tDRIVE
8
TDRIVEP = 00; TDRIVEN = 00
220
ns
Peak sink or source current TDRIVEP = 01; TDRIVEN = 01
drive time
TDRIVEP = 10; TDRIVEN = 10
440
ns
880
ns
TDRIVEP = 11; TDRIVEN = 11
1780
ns
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Electrical Characteristics (continued)
PVDD = 4.4 to 45 V, DRV8305xQ: TJ = –40°C to 150°C, DRV8305xE: TJ = –40°C to 175°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
HIGH-SIDE PEAK CURRENT GATE DRIVE (GHx)
IDRIVEP_HS
IDRIVEN_HS
High-side peak source
current
High-side peak sink current
IDRIVEP_HS = 0000
0.01
A
IDRIVEP_HS = 0001
0.02
A
IDRIVEP_HS = 0010
0.03
A
IDRIVEP_HS = 0011
0.04
A
IDRIVEP_HS = 0100
0.05
A
IDRIVEP_HS = 0101
0.06
A
IDRIVEP_HS = 0110
0.07
A
IDRIVEP_HS = 0111
0.125
A
IDRIVEP_HS = 1000
0.25
A
IDRIVEP_HS = 1001
0.5
A
IDRIVEP_HS = 1010
0.75
A
IDRIVEP_HS = 1011
1
A
IDRIVEP_HS = 1100, 1101, 1110,
1111
0.05
A
IDRIVEN_HS = 0000
0.02
A
IDRIVEN_HS = 0001
0.03
A
IDRIVEN_HS = 0010
0.04
A
IDRIVEN_HS = 0011
0.05
A
IDRIVEN_HS = 0100
0.06
A
IDRIVEN_HS = 0101
0.07
A
IDRIVEN_HS = 0110
0.08
A
IDRIVEN_HS = 0111
0.25
A
IDRIVEN_HS = 1000
0.5
A
IDRIVEN_HS = 1001
0.75
A
IDRIVEN_HS = 1010
1
A
IDRIVEN_HS = 1011
1.25
A
IDRIVEN_HS = 1100, 1101, 1110,
1111
0.06
A
IDRIVEP_LS = 0000
0.01
A
IDRIVEP_LS = 0001
0.02
A
IDRIVEP_LS = 0010
0.03
A
IDRIVEP_LS = 0011
0.04
A
IDRIVEP_LS = 0100
0.05
A
IDRIVEP_LS = 0101
0.06
A
IDRIVEP_LS = 0110
0.07
A
IDRIVEP_LS = 0111
0.125
A
IDRIVEP_LS = 1000
0.25
A
IDRIVEP_LS = 1001
0.5
A
IDRIVEP_LS = 1010
0.75
A
IDRIVEP_LS = 1011
1
A
0.05
A
LOW-SIDE PEAK CURRENT GATE DRIVE (GLx)
IDRIVEP_LS
Low-side peak source
current
IDRIVEP_LS = 1100, 1101, 1110,
1111
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Electrical Characteristics (continued)
PVDD = 4.4 to 45 V, DRV8305xQ: TJ = –40°C to 150°C, DRV8305xE: TJ = –40°C to 175°C (unless otherwise noted)
PARAMETER
IDRIVEN_LS
Low-side peak sink current
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IDRIVEN_LS = 0000
0.02
A
IDRIVEN_LS = 0001
0.03
A
IDRIVEN_LS = 0010
0.04
A
IDRIVEN_LS = 0011
0.05
A
IDRIVEN_LS = 0100
0.06
A
IDRIVEN_LS = 0101
0.07
A
IDRIVEN_LS = 0110
0.08
A
IDRIVEN_LS = 0111
0.25
A
IDRIVEN_LS = 1000
0.5
A
IDRIVEN_LS = 1001
0.75
A
IDRIVEN_LS = 1010
1
A
IDRIVEN_LS = 1011
1.25
A
IDRIVEN_LS = 1100, 1101, 1110,
1111
0.06
A
PASSIVE GATE PULLDOWN (GHx, GLx)
RSLEEP_PD
Gate pulldown resistance,
sleep mode
EN_GATE = LOW; GHx to GND;
1000
Ω
EN_GATE = LOW; GLx to GND;
500
Ω
RSTANDBY_PD
Gate pulldown resistance,
standby mode
EN_GATE = LOW; GHx to GND;
1000
Ω
EN_GATE = LOW; GLx to GND;
500
Ω
mA
ACTIVE GATE PULLDOWN (GHx, GLx)
IHOLD
Gate pulldown current,
holding
EN_GATE = HIGH;
GHx to SHx; GLx to SLx
50
ISTRONG
Gate pulldown current,
strong
EN_GATE = HIGH;
GHx to SHx; GLx to SLx
1.25
A
tpd_lf-O
Positive input falling to
GHS_x falling
PVDD = 12 V; CL = 1 nF; 50% to 50%
200
ns
tpd_lr-O
Positive input rising to
GHS_x rising
PVDD = 12 V; CL = 1 nF; 50% to 50%
200
ns
td_min
Minimum dead time after
hand shaking
280
ns
DEAD_TIME = 000
35
ns
DEAD_TIME = 001
52
ns
DEAD_TIME = 010
88
ns
DEAD_TIME = 011
440
ns
DEAD_TIME = 100
880
ns
DEAD_TIME = 101
1760
ns
DEAD_TIME = 110
3520
ns
DEAD_TIME = 111
GATE TIMING
Dead time in addition to
td_min
tdtp
5280
ns
tPD_MATCH
Propagation delay matching
between high-side and lowside
50
ns
tDT_MATCH
Dead-time matching
50
ns
10
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Electrical Characteristics (continued)
PVDD = 4.4 to 45 V, DRV8305xQ: TJ = –40°C to 150°C, DRV8305xE: TJ = –40°C to 175°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CURRENT SHUNT AMPLIFIER
GCSA
GERR
tSETTLING
VIOS
VVREF_ERR
Current sense amplifier
gain
Current sense amplifier
gain error
Current sense amplifier
settling time
DC input offset
Reference buffer error (DC)
GAIN_CSx = 00
10
V/V
GAIN_CSx = 01
19.9
V/V
GAIN_CSx = 10
39.8
V/V
GAIN_CSx = 11
78.8
V/V
Input differential > 0.025 V;
TJ = –40 to 150 °C
–3.5
3.5
%
Input differential > 0.025 V;
TJ = 150 to 175 °C
–4
4
%
Settling time to 1%; no blanking;
GCSA = 10; Vstep = 0.46 V
300
ns
Settling time to 1%; no blanking;
GCSA = 20; Vstep = 0.46 V
600
ns
Settling time to 1%; no blanking;
GCSA = 40; Vstep = 0.46 V
1.2
µs
Settling time to 1%; no blanking;
GCSA = 80; Vstep = 0.46 V
2.4
µs
GCSA = 10; input shorted; RTI
–4
4
mV
Internal or external VREF;
VREF_SCALE = 01
–3
3
%
Internal or external VREF;
VREF_SCALE = 10
–4
4
%
Internal or external VREF;
VREF_SCALE = 11
–10
10
%
VDRIFTOS
Input offset error drift
GCSA = 10; input shorted; RTI
IBIAS
Input bias current
VIN_COM = 0; SOx open
IOFFSET
Input bias current offset
IBIAS (SNx-SPx); VIN_COM = 0;
SOx open
VIN_COM
Common input mode range
–0.15
0.15
V
VIN_DIFF
Differential input range
–0.48
0.48
V
CMRR
Common mode rejection
ration
10
µV/C
100
1
µA
µA
External input resistance matched;
DC; GCSA = 10
60
80
dB
External input resistance matched;
20 kHz; GCSA = 10
60
80
dB
150
dB
DC ( 5.3 V
0.3
VSLEW
Output slew rate
GCSA = 10; RL = 0 Ω; CL = 60 pF
5.2
IVO
Output short circuit current
SOx shorted to ground
UGB
Unity gain bandwidth
product
GCSA = 10
20 kHz; GCSA = 10
90
dB
4.7
V
10
V/µs
20
mA
2
MHz
VOLTAGE PROTECTION
VAVDD_UVLO
VVREG_UV
VVREG_UV_DGL
AVDD undervoltage fault
VREG undervoltage fault
AVDD falling, relative to GND
3.7
V
VREG_UV_LEVEL = 00
VREG × 0.9
V
VREG_UV_LEVEL = 01
VREG × 0.8
V
VREG_UV_LEVEL = 10
VREG × 0.7
V
VREG_UV_LEVEL = 11
VREG × 0.7
V
2
µs
VREG undervoltage
monitor deglitch time
3.3
1.5
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Electrical Characteristics (continued)
PVDD = 4.4 to 45 V, DRV8305xQ: TJ = –40°C to 150°C, DRV8305xE: TJ = –40°C to 175°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Undervoltage protection
warning, PVDD
PVDD falling
7.7
8.1
V
PVDD rising
7.9
8.3
V
VPVDD_UVLO1
Undervoltage protection
lock out, PVDD
PVDD falling
4.1
V
4.3
V
VPVDD_UVLO2
Undervoltage protection
fault, PVDD
PVDD falling
4.2
4.4
V
PVDD rising
4.4
4.7
V
VPVDD_OVFL
Overvoltage protection
warning, PVDD
PVDD falling
33.5
36
V
PVDD rising
32.5
35
V
VVCPH_UVFL
Charge pump undervoltage
protection warning, VCPH
8
V
VVCPH_UVLO2
Charge pump undervoltage
protection fault, VCPH
VPVDD_UVFL
PVDD rising
VCPH falling, relative to PVDD
VCPH falling, relative to PVDD,
SET_VCPH_UV = 0
4.6
5.3
V
VCPH falling, relative to PVDD,
SET_VCPH_UV = 1
4.3
5
V
VVCP_LSD_UVLO2
Low-side regulator
undervoltage fault,
VCP_LSD
VCP_LSD falling, relative to GND
6.4
7.5
V
VVCPH_OVLO
Charge pump overvoltage
protection fault, VCPH
Relative to PVDD
14
18
V
VVCPH_OVLO_ABS
Charge pump overvoltage
protection fault, VCPH
Relative to GND
60
V
TEMPERATURE PROTECTION
OTW_CLR
Junction temperature-to
clear overtemperature
(OTW) warning (1)
100
130
150
°C
OTW_SET
Junction temperature for
overtemperature (OTW)
warning (1)
135
160
185
°C
OTSD_CLR
Junction temperature-toclear overtemperature
shutdown (OTSD) (1)
125
155
180
°C
OTSD_SET (2)
Junction temperature for
overtemperature shutdown
(OTSD) (1)
160
185
210
°C
TEMP_FLAG1
Junction temperature flag
setting 1 (1)
105
°C
TEMP_FLAG2
Junction temperature flag
setting 2 (1)
125
°C
TEMP_FLAG3
Junction temperature flag
setting 3 (1)
135
°C
TEMP_FLAG4
Junction temperature flag
setting 4 (1)
185
°C
PROTECTION CONTROL
tpd,E-L
Delay, error event to all
gates low
TBLANK = 00; TVDS = 00
1
µs
tpd,E-SD
Delay, error event to
nFAULTx low
TBLANK = 00; TVDS = 00
1
µs
(1)
(2)
12
Specified by design.
Overtemperature shutdown (OTSD) is disabled by default for DRV8305xEPHPQ1 and may only be re-enabled through control register.
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Electrical Characteristics (continued)
PVDD = 4.4 to 45 V, DRV8305xQ: TJ = –40°C to 150°C, DRV8305xE: TJ = –40°C to 175°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FET CURRENT PROTECTION (VDS SENSING)
VDS_TRIP
tVDS
Drain-source voltage
protection limit
VDS sense deglitch time
tBLANK
VDS sense blanking time
tWARN_PULSE
nFAULT pin warning pulse
length
VDS_LEVEL = 00000
0.06
V
VDS_LEVEL = 00001
0.068
V
VDS_LEVEL = 00010
0.076
V
VDS_LEVEL = 00011
0.086
V
VDS_LEVEL = 00100
0.097
V
VDS_LEVEL = 00101
0.109
V
VDS_LEVEL = 00110
0.123
V
VDS_LEVEL = 00111
0.138
V
VDS_LEVEL = 01000
0.155
V
VDS_LEVEL = 01001
0.175
V
VDS_LEVEL = 01010
0.197
V
VDS_LEVEL = 01011
0.222
V
VDS_LEVEL = 01100
0.25
V
VDS_LEVEL = 01101
0.282
V
VDS_LEVEL = 01110
0.317
V
VDS_LEVEL = 01111
0.358
V
VDS_LEVEL = 10000
0.403
V
VDS_LEVEL = 10001
0.454
V
VDS_LEVEL = 10010
0.511
V
VDS_LEVEL = 10011
0.576
V
VDS_LEVEL = 10100
0.648
V
VDS_LEVEL = 10101
0.73
V
VDS_LEVEL = 10110
0.822
V
VDS_LEVEL = 10111
0.926
V
VDS_LEVEL = 11000
1.043
V
VDS_LEVEL = 11001
1.175
V
VDS_LEVEL = 11010
1.324
V
VDS_LEVEL = 11011
1.491
V
VDS_LEVEL = 11100
1.679
V
VDS_LEVEL = 11101
1.892
V
VDS_LEVEL = 11110
2.131
V
VDS_LEVEL = 11111
2.131
V
TVDS = 00
0
µs
TVDS = 01
1.75
µs
TVDS = 10
3.5
µs
TVDS = 11
7
µs
TBLANK = 00
0
µs
TBLANK = 01
1.75
µs
TBLANK = 10
3.5
µs
TBLANK = 11
7
µs
56
µs
2
V
PHASE SHORT PROTECTION
VSNSOCP_TRIP
Phase short protection limit
Fixed voltage
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6.6 SPI Timing Requirements (Slave Mode Only)
MIN
tSPI_READY
SPI read after power on
tCLK
Minimum SPI clock period
tCLKH
PVDD > VPVDD_UVLO1
NOM
MAX
5
10
UNIT
ms
100
ns
Clock high time
40
ns
tCLKL
Clock low time
40
ns
tSU_SDI
SDI input data setup time
20
ns
tHD_SDI
SDI input data hold time
30
ns
tD_SDO
SDO output data delay time, CLK high to SDO valid
tHD_SDO
SDO output hold time
40
ns
tSU_SCS
SCS setup time
50
ns
tHD_SCS
SCS hold time
50
ns
tHI_SCS
SCS minimum high time before SCS active low
tACC
SCS access time, SCS low to SDO out of high impedance
10
ns
tDIS
SCS disable time, SCS high to SDO high impedance
10
ns
CL = 20 pF
20
400
ns
tSU_SCS
tHI_SCS
ns
tHD_SCS
SCS
tCLK
SCLK
tCLKH
tCLKL
MSB In
(Must Be Valid)
SDI
tSU_SDI
SDO
LSB
tHD_SDI
MSB Out (Is Valid)
Z
tD_SDO
tACC
LSB
tHD_SDO
Z
tDIS
Figure 1. SPI Slave Mode Timing Definition
14
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6.7 Typical Characteristics
6
30
5.9
25
TA = 40°C
TA = 25°C
TA = 125°C
5.7
Supply Current (mA)
Supply Current (mA)
5.8
5.6
5.5
5.4
20
15
10
5.3
TA = 40°C
TA = 25°C
TA = 125°C
5
5.2
5.1
0
0
10
20
30
PVDD (V)
40
50
0
10
D001
Figure 2. Standby Current
20
30
PVDD (V)
40
50
D002
Figure 3. Operating Current
12
200
180
10
140
8
120
VCPH (V)
Supply Current (µA)
160
100
80
6
4
60
40
TA = 40°C
TA = 25°C
TA = 125°C
20
TA = 40°C
TA = 25°C
TA = 125°C
2
0
0
0
10
20
30
PVDD (V)
40
50
0
D003
Figure 4. Sleep Current
10
20
30
PVDD (V)
40
50
D004
Figure 5. VCPH Voltage
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7 Detailed Description
7.1 Overview
The DRV8305-Q1 is a 4.4-V to 45-V automotive gate driver IC for three-phase motor driver applications. This
device reduces external component count in the system by integrating three half-bridge drivers, charge pump,
three current shunt amplifiers, an uncommited 3.3-V or 5-V, 50-mA LDO, and a variety of protection circuits. The
DRV8305-Q1 provides overcurrent, shoot-through, overtemperature, overvoltage, and undervoltage protection.
Fault conditions are indicated by the nFAULT pin and specific fault information can be read back from the SPI
registers. The protection circuits are highly configurable to allow adaptation to different applications and support
limp home operation.
The gate driver uses a tripler charge pump to generate the appropriate gate-to-source voltage bias for the
external, high-side N-channel power MOSFETs during low supply conditions. A regulated 10-V LDO derived from
the charge pump supplies the gate-to-source voltage bias for the low-side N-channel MOSFET. The high-side
and low-side peak gate drive currents are adjustable through the SPI registers to finely tune the switching of the
external MOSFETs without the need for external components. An internal handshaking scheme is used to
prevent shoot-through and minimize the dead time when transitioning between MOSFETs in each half-bridge.
Multiple input methods are provided to accommodate different control schemes including a 1-PWM mode which
integrates a six-step block commutation table for BLDC motor control.
VDS sensing of the external power MOSFETs allows for the DRV8305-Q1 to detect overcurrent conditions and
respond appropriately. Integrated blanking and deglitch timers are provided to prevent false trips related to
switching or transient noise. Individual MOSFET overcurrent conditions are reported through the SPI status
registers and nFAULT pin. A dedicated VDRAIN pin is provided to accurately sense the drain voltage of the highside MOSFET.
The three internal current shunt amplifiers allow for the implementation of common motor control schemes that
require sensing of the half-bridge currents through a low-side current shunt resistor. The amplifier gain, reference
voltage, and blanking are adjustable through the SPI registers. A calibration method is providing to minimize
inaccuracy related to offset voltage.
Three versions of the DRV8305-Q1 are available with separate part numbers for the different devices options:
• DRV8305NQ: VREG pin has the internal LDO disabled and is only used as a voltage reference input for the
amplifiers and SDO pullup. Grade 1.
• DRV83053Q: VREG is a 3.3-V, 50-mA LDO output pin. Grade 1.
• DRV83055Q: VREG is a 5-V, 50-mA LDO output pin. Grade 1.
• DRV8305NE: VREG pin has the internal LDO disabled and is only used as a voltage reference input for the
amplifiers and SDO pullup. Grade 0.
16
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7.2 Functional Block Diagram
DVDD
DVDD
AVDD
VCP_LSD
AVDD
CP2H CP2L
CP1H CP1L
VCP_LSD
VCPH
DVDD
LDO
AVDD
LDO
Low Side
Gate Drive
LDO
VCPH
High Side Gate Drive
2-Stage Charge Pump
PVDD
WAKE
PVDD
VREG
VREG/VREF
VDRAIN
VREG
LDO
VDRAIN
PWRGD
VDRAIN
VCPH
GH_A
+
HS
VDS
-
SH_A
EN_GATE
VCP_LSD
GL_A
LS
+
INH_A
VDS
-
SL_A
INL_A
Phase A Pre-Driver
Core Logic
INH_B
INL_B
VDRAIN
Digital
Inputs
and
Outputs
VCPH
GH_B
Control
+
HS
VDS
-
SH_B
Configuration
INH_C
PVDD
VCP_LSD
GL_B
LS
+
INL_C
VDS
Timing
-
SL_B
nFAULT
Phase B Pre-Driver
Protection
VDRAIN
PVDD
VCPH
GH_C
VREG
+
HS
VDS
-
SCLK
SH_C
VCP_LSD
nSCS
GL_C
+
SPI
LS
VDS
-
SDI
SDO
SL_C
Thermal
Sensor
Voltage
Monitoring
SO1
Phase C Pre-Driver
VREG
Current
Sense
Amplifier 1
Ref/k
VREG
Current
Sense
Amplifier 2
Ref/k
VREG
Ref/k
GND
GND
SP1
SN2
AVDD
SO2
SO3
SN1
AVDD
SP2
SN3
AVDD
Current
Sense
Amplifier 3
SP3
PowerPAD
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7.3 Feature Description
Table 1 lists the recommended values of the external components for the DRV8305-Q1.
Table 1. External Components
(1)
(2)
COMPONENT
PIN 1
PIN 2
RECOMMENDED
CPVDD
PVDD
GND
4.7-µF ceramic capacitor rated for PVDD (1)
CAVDD
AVDD
GND
1-µF ceramic capacitor rated for 6.3 V (1)
CDVDD
DVDD
GND
1-µF ceramic capacitor rated for 6.3 V (1)
CVCPH
VCPH
PVDD
2.2-µF ceramic capacitor rated for 16 V (1)
CVCP_LSD
VCP_LSD
GND
1-µF ceramic capacitor rated for 16 V (1)
CCP1
CP1H
CP1L
0.047-µF ceramic capacitor rated for PVDD (1)
CCP2
CP2H
CP2L
0.047-µF ceramic capacitor rated for PVDD × 2 (1)
CVREG
VREG
GND
1-µF ceramic capacitor rated for 6.3 V (1)
RVDRAIN
VDRAIN
PVDD
100-Ω series resistor between VDRAIN and HS MOSFET DRAIN
RnFAULT
nFAULT
VCC (2)
1-10 kΩ pulled up the MCU power supply
RPWRGD
PWRGD
VCC (2)
1-10 kΩ pulled up the MCU power supply
The effective capacitance of ceramic capacitors varies with DC operating voltage and temperature. As a rule of thumb, expect the
effective capacitance to decrease by as much as 50% at the extremes of the operating voltage. The system designer must review the
capacitor characteristics and select the component accordingly.
VCC is not a pin on the DRV8305-Q1, but a VCC supply voltage pullup is required for open-drain output nFAULT; nFAULT may be
pulled up to DVDD.
7.3.1 Integrated Three-Phase Gate Driver
The DRV8305-Q1 is a completely integrated three-phase gate driver. It provides three N-channel MOSFET halfbridge gate drivers, multiple input modes, high-side and low-side gate drive supplies, and a highly configurable
gate drive architecture. The DRV8305-Q1 is designed to support automotive applications by incorporating a wide
operating voltage range, wide temperature range, and array of protection features. The configurability of device
allows for it to be used in a broad range of applications.
7.3.2 INHx/INLx: Gate Driver Input Modes
The DRV8305-Q1 can be operated in three different inputs modes to support various commutation schemes.
• Table 2 shows the truth table for the 6-PWM input mode. This mode allows for each half-bridge to be placed
in one of three states, either High, Low, or Hi-Z, based on the inputs.
Table 2. 6-PWM Truth Table
18
INHx
INLx
GHx
GLx
1
1
L
L
1
0
H
L
0
1
L
H
0
0
L
L
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6-PWM
INHA
MCU PWM
INLA
MCU PWM
INHB
MCU PWM
INLB
MCU PWM
INHC
MCU PWM
INLC
MCU PWM
Figure 6. 6-PWM Mode
•
Table 3 shows the truth table for the 3-PWM input mode. This mode allows for each half-bridge to be placed
in one of two states, either High or Low, based on the inputs. The three high-side inputs (INHx) are used to
control the state of the half-bridge with the complimentary low-side signals being generated internally. Dead
time can be adjusted through the internal setting (DEAD_TIME) in the SPI registers. In this mode all activity
on INLx is ignored.
Table 3. 3-PWM Truth Table
INHx
INLx
GHx
1
X
H
GLx
L
0
X
L
H
3-PWM
INHA
MCU PWM
INLA
INHB
MCU PWM
INLB
INHC
MCU PWM
INLC
Figure 7. 3-PWM Mode
•
Table 4 and Table 5 show the truth tables for the 1-PWM input mode. The 1-PWM mode uses an internally
stored 6-step block commutation table to control the outputs of the three half-bridge drivers based on one
PWM and three GPIO inputs. This mode allows the use of a lower cost microcontroller by requiring only one
PWM resource. The PWM signal is applied on pin INHA (PWM_IN) to set the duty cycle of the half-bridge
outputs along with the three GPIO signals on pins INLA (PHC_0), INHB (PHC_1), INLB (PHC_2) that serve to
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set the value of a three bit register for the commutation table. The PWM may be operated from 0-100% duty
cycle. The three bit register is used to select the state for each half-bridge for a total of eight states including
an align and stop state.
An additional and optional GPIO, INHC (DWELL) can be used to facilitate the insertion of dwell states or
phase current overlap states between the six commutation steps. This may be used to reduce acoustic noise
and improve motion through the reduction of abrupt current direction changes when switching between states.
INHC must be high when the state is changed and the dwell state will exist until INHC is taken low. If the
dwell states are not being used, the INHC pin can be tied low.
In 1-PWM mode all activity on INLC is ignored.
1 PWM
INHA
³3:0´
MCU PWM
INLA
³67$7(0"
MCU GPIO
INHB
³67$7(1"
MCU GPIO
INLB
³67$7(2"
MCU GPIO
INHC
³':(//"
MCU GPIO
(optional)
INLC
Figure 8. 1-PWM Mode
The method of freewheeling can be selected through an SPI register (COMM_OPTION). Diode freewheeling
is when the phase current is carried by the body diode of the external power MOSFET during periods when
the MOSFET is reverse biased (current moving from source to drain). In active freewheeling, the power
MOSFET is enabled during periods when the MOSFET is reverse biased. This allows the system to improve
efficiency due to the typically lower impedance of the MOSFET conduction channel as compared to the body
diode. Table 4 shows the truth table for active freewheeling. Table 5) shows the truth table for diode
freewheeling.
Table 4. 1-PWM Active Freewheeling
STATE
INLA:INHB:INLB:INHC
GHA
GLA
GHB
GLB
AB
0110
PWM
!PWM
LOW
HIGH
LOW
LOW
AB_CB
0101
PWM
!PWM
LOW
HIGH
PWM
!PWM
CB
0100
LOW
LOW
LOW
HIGH
PWM
!PWM
CB_CA
1101
LOW
HIGH
LOW
HIGH
PWM
!PWM
CA
1100
LOW
HIGH
LOW
LOW
PWM
!PWM
CA_BA
1001
LOW
HIGH
PWM
!PWM
PWM
!PWM
BA
1000
LOW
HIGH
PWM
!PWM
LOW
LOW
BA_BC
1011
LOW
HIGH
PWM
!PWM
LOW
HIGH
BC
1010
LOW
LOW
PWM
!PWM
LOW
HIGH
BC_AC
0011
PWM
!PWM
PWM
!PWM
LOW
HIGH
AC
0010
PWM
!PWM
LOW
LOW
LOW
HIGH
AC_AB
0111
PWM
!PWM
LOW
HIGH
LOW
HIGH
Align
1110
PWM
!PWM
LOW
HIGH
LOW
HIGH
Stop
0000
LOW
LOW
LOW
LOW
LOW
LOW
20
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Table 5. 1-PWM Diode Freewheeling
INLA:INHB:INLB:INHC
GHA
GLA
GHB
GLB
GHC
GLC
AB
STATE
0110
PWM
LOW
LOW
HIGH
LOW
LOW
AB_CB
0101
PWM
LOW
LOW
HIGH
PWM
LOW
CB
0100
LOW
LOW
LOW
HIGH
PWM
LOW
CB_CA
1101
LOW
HIGH
LOW
HIGH
PWM
LOW
CA
1100
LOW
HIGH
LOW
LOW
PWM
LOW
CA_BA
1001
LOW
HIGH
PWM
LOW
PWM
LOW
BA
1000
LOW
HIGH
PWM
LOW
LOW
LOW
BA_BC
1011
LOW
HIGH
PWM
LOW
LOW
HIGH
BC
1010
LOW
LOW
PWM
LOW
LOW
HIGH
BC_AC
0011
PWM
LOW
PWM
LOW
LOW
HIGH
AC
0010
PWM
LOW
LOW
LOW
LOW
HIGH
AC_AB
0111
PWM
LOW
LOW
HIGH
LOW
HIGH
Align
1110
PWM
LOW
LOW
HIGH
LOW
HIGH
Stop
0000
LOW
LOW
LOW
LOW
LOW
LOW
7.3.3 VCPH Charge Pump: High-Side Gate Supply
The DRV8305-Q1 uses a charge pump to generate the proper gate-to-source voltage bias for the high-side Nchannel MOSFETs. Similar to the often used bootstrap architecture, the charge pump generates a floating supply
voltage used to enable the MOSFET. When enabled, the gate of the external MOSFET is connected to VCPH
through the internal gate drivers. The charge pump of the DRV8305-Q1 regulates the VCPH supply to PVDD +
10-V in order to support both standard and logic level MOSFETs. As opposed to a bootstrap architecture, the
charge pump supports 0 to 100% duty cycle operation by eliminating the need to refresh the bootstrap capacitor.
The charge pump also removes the need for bootstrap capacitors to be connected to the switch-node of the halfbridge.
In order to support automotive cold crank transients on the battery which require the system to be operational to
as low as 4.4 V, a regulated triple charge pump scheme is used to create sufficient VGS to drive standard and
logic level MOSFETs during the low voltage transient. Between 4.4 to 18 V the charge pump regulates the
voltage in a tripler mode. Beyond 18 V and until the max operating voltage, it switches over to a doubler mode in
order to improve efficiency. The charge pump is disabled until EN_GATE is set high to reduce unneeded power
consumption by the IC. After EN_GATE is set high, the device will go through a power up sequence to enable
the gate drivers and gate drive supplies. 1 ms should be allocated after EN_GATE is set high to allow the charge
pump to reach its regulation voltage.
The charge pump is continuously monitored for undervoltage and overvoltage conditions to prevent underdriven
or overdriven MOSFET scenarios. If an undervoltage or overvoltage condition is detected the appropriate actions
is taken and reported through the SPI registers.
7.3.4 VCP_LSD LDO: Low-Side Gate Supply
The DRV8305-Q1 uses a linear regulator to generate the proper gate-to-source voltage vias for the low-side Nchannel MOSFETs. The linear regulator generates a fixed 10-V supply voltage with respect to GND. When
enabled, the gate of the external MOSFET is connected to VCPH_LSD through the internal gate drivers. In order
to support automotive cold crank transients the input voltage for the VCP_LSD linear regulator is taken from the
VCPH charge pump. This allows the DRV8305-Q1 to provide sufficient VGS to drive standard and logic level
MOSFETs during the low voltage transient.
The low-side regulator is disabled until EN_GATE is set high to reduce unneeded power consumption by the IC.
After EN_GATE is set high, the device will go through a power up sequence for the gate drivers and gate drive
supplies. 1 ms should be allocated after EN_GATE is set high to allow the low-side regulator to reach its
regulation voltage. The VCP_LSD regulator is continuously monitored for undervoltage conditions to prevent
underdriven MOSFET scenarios. If an undervoltage condition is detected the appropriate actions is taken and
reported through the SPI registers.
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7.3.5 GHx/GLx: Half-Bridge Gate Drivers
The DRV8305-Q1 gate driver uses a complimentary push-pull topology for both the high-side and the low-side
gate drivers. Both the high-side (GHx to SHx) and the low-side (GLx to SLx) are implemented as floating gate
drivers in order to tolerate switching transients from the half-bridges. The high-side and low-side gate drivers use
a highly adjustable current control scheme in order to allow the DRV8305-Q1 to adjust the VDS slew rate of the
external MOSFETs without the need for additional components. The scheme also incorporates a mechanism for
detecting issues with the gate drive output to the power MOSFETs during operation. This scheme and its
application benefits are outlined below as well as in the Understanding IDRIVE and TDRIVE in TI Motor Gate
Drivers application report.
VCPH
INHx
GHx
Level Shifters
INLx
SHx
Logic
VCP_LSD
Level Shifters
GLx
SLx
Figure 9. DRV8305-Q1 Gate Driver Architecture
7.3.5.1 Smart Gate Drive Architecture: IDRIVE
The first component of the gate drive architecture implements adjustable current control for the gates of the
external power MOSFETs. This feature allows the gate driver to control the VDS slew rate of the MOSFETs by
adjusting the gate drive current. This is realized internally to reduce the need for external components inline with
the gates of the MOSFETs. The DRV8305-Q1 provides 12 adjustable source and sink current levels for the highside (the high-sides of all three phases share the same setting) and low-side gate drivers (the low-sides of all
three phases share the same settings). The gate drive levels are adjustable through the SPI registers in both the
standby and operating states. This flexibility allows the system designer to tune the performance of the driver for
different operating conditions through software alone.
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The gate drivers are implemented as temperature compensated, constant current sources up to the 80-mA
(sink)/70-mA (source) current settings in order to maintain the accuracy required for precise slew rate control.
The current source architecture helps eliminate the temperature, process, and load-dependent variation
associated with internal and external series limiting resistors. Beyond that, internal switches are adjusted to
create the desired settings up to the 1.25-A (sink)/1-A (source) settings. For higher currents, internal series
switches are used to minimize the power losses associated with mirroring such large currents.
Control of the gate current during the MOSFET Miller region is a key component for adjusting the MOSFET VDS
rise and fall times. MOSFET VDS slew rates are a critical parameter for optimizing emitted radiations, energy and
duration of diode recovery spikes, dV/dt related turn on leading to shoot-through, and voltage transients related
to parasitics.
When a MOSFET is enhanced, three different charges must be supplied to the MOSFET gate. The MOSFET
drain to source voltage will slew primarily during the Miller region. By controlling the rate of charge to the
MOSFET gate (gate drive current strength) during the Miller region, it is possible to optimize the VDS slew rate
for the reasons mentioned.
1. QGS = Gate-to-source charge
2. QGD = Gate-to-drain charge (Miller charge)
3. Remaining QG
Drain
Gate
CGD
Level
Shifter
CGS
Source
Figure 10. MOSFET Charge Example
7.3.5.2 Smart Gate Drive Architecture: TDRIVE
The DRV8305-Q1 gate driver uses an integrated state machine (TDRIVE) in the gate driver to protect against
excessive current on the gate drive outputs, shoot-through in the external MOSFET, and dV/dt turn on due to
switching on the phase nodes. The TDRIVE state machine allows for the design of a robust and efficient motor
drive system with minimal overhead.
The state machine incorporates internal handshaking when switching from the low to the high-side external
MOSFET or vice-versa. The handshaking is designed to prevent the external MOSFETs from entering a period
of cross conduction, also known as shoot-through. The internal handshaking uses the VGS monitors of the
DRV8305-Q1 to determine when one MOSFET has been disabled and the other can be enabled. This allows the
gate driver to insert an optimized dead time into the system without the risk of cross conduction. Any dead time
added externally through the MCU or SPI register will be inserted after the handshake process.
The state machine also incorporates a gate drive timer to ensure that under abnormal circumstances such as a
short on the MOSFET gate or the inadvertent turn on of a MOSFET VGS clamp, the high peak current through
the DRV8305-Q1 and MOSFET is limited to a fixed duration. This concept is visualized in the figure below. First,
the DRV8305-Q1 receives a command to enable or disable the MOSFET through INHx or INLx inputs. Second,
the gate driver is enabled and a strong current is applied to the MOSFET gate and the gate voltage begins to
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change. If the gate voltage has not changed to the desired level after the tDRIVE period (indicating a short circuit
or overcurrent condition on the MOSFET gate), the DRV8305-Q1 signals a gate drive fault and the gate drive is
disabled to help protect the external MOSFET and DRV8305-Q1. If the MOSFET does successfully enable or
disable, after the tDRIVE period the DRV8305-Q1 will enable a lower hold current to ensure the MOSFET remains
enabled or disabled and improve efficiency of the gate drive.
Select a tDRIVE time that is longer than the time needed to charge or discharge the gate capacitances of the
external MOSFETs. The TDRIVE SPI registers should be configured so that the MOSFET gates are charged
completely within tDRIVE during normal operation. If tDRIVE is too low for a given MOSFET, then the MOSFET may
not turn on completely. It is suggested to tune these values in-system with the required external MOSFETs to
determine the best possible setting for the application. A good starting value is a tDRIVE period that is 2x the
expected rise or fall times of the external MOSFET gates. Note that TDRIVE will not increase the PWM time and
will simply terminate if a PWM command is received while it is active.
tDRIVE_HS
tDRIVE_HS
INHx
GHx Voltage
Gate Off
IDRIVE
GHx Current
IHOLD
IDRIVE
ISTRONG
tDEAD TIME
ISTRONG
tDEAD TIME
INLx
GLx Voltage
Gate Off
IHOLD
GLx Current
IDRIVE
IDRIVE
IHOLD
ISTRONG
tDRIVE_LS
tDRIVE_LS
Figure 11. TDRIVE Gate Drive State Machine
7.3.5.3 CSAs: Current Shunt Amplifiers
The DRV8305-Q1 includes three high performance low-side current shunt amplifiers for accurate current
measurement utilizing low-side shunt resistors in the external half-bridges. They are commonly used to measure
the motor phase current to implement overcurrent protection, external torque control, or external commutation
control through the application MCU.
The current shunt amplifiers have the following features:
• Each of the three current sense amplifiers can be programmed and calibrated independently.
• Can provide output bias up to 2.5 V to support bidirectional current sensing.
• May be used for either individual or total current shunt sensing.
• Four programmable gain settings through SPI registers (10, 20, 40 and 80 V/V).
• Reference voltage for output bias provided from voltage regulator VREG for DRV83053Q and DRV83055Q.
• Reference voltage for output bias provided from externally applied voltage on VREG pin for DRV8305NQ and
DRV8305NE.
• Programmable output bias scaling. The scaling factor k can be programmed through SPI registers (1/2 or
1/4).
• Programmable blanking time (delay) of the amplifier outputs. The blanking time is implemented from any
rising or falling edge of gate drive outputs. The blanking time is applied to all three current sense amplifiers
equally. In case the current sense amplifiers are already being blanked when another gate driver rising or
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falling edge is seen, the blanking interval will be restarted at the edge. Note that the blanking time options do
not include delay from internal amplifier loading or delays from the trace or component loads on the amplifier
output. The programmable blanking time may be overridden to have no delay (default value).
Minimize DC offset and drift through temperature with DC calibrating through SPI register. When DC
calibration is enabled, device will short input of current shunt amplifier and disconnect the load. DC calibrating
can be done at anytime, even when the MOSFET is switching because the load is disconnected. For best
result, perform the DC calibrating during switching off period when no load is present to reduce the potential
noise impact to the amplifier.
The output of current shunt amplifier can be calculated as:
VVREF
VO
G u SNX SPX
k
where
•
•
•
•
•
•
VREF is the reference voltage from the VREG pin.
G is the gain setting of the amplifier.
k = 2, 4, or 8
SNx and SPx are the inputs of channel x.
SPx should connect to the low-side (ground) of the sense resistor for the best common mode rejection.
SNx should connect to the high-side (LS MOSFET source) of the sense resistor.
(1)
Figure 12 shows current amplifier simplified block diagram.
DC_CAL(SPI)
SN
400 k
S4
200 k
S3
100 k
S2
50 k
S1
AVDD
5k
±
100
S5
SO
DC_CAL(SPI)
5k
+
SP
DC_CAL(SPI)
50 k
S1
100 k
S2
200 k
S3
400 k
S4
AVDD
VREF
VREF/k
±
k = 2, 4, 8
+
Figure 12. Current Shunt Amplifier Simplified Block Diagram
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7.3.6 DVDD and AVDD: Internal Voltage Regulators
The DRV8305-Q1 has two internal regulators, DVDD and AVDD, that power internal circuitry. These regulators
cannot be used to drive external loads and may not be supplied externally.
DVDD is the voltage regulator for the internal logic circuits and is maintained at a value of 3.3 V through the
entire operating range of the device. DVDD is derived from the PVDD power supply. DVDD should be bypassed
externally with a 1-µF capacitor to GND.
AVDD is the voltage regulator that provides the voltage rail for the internal analog circuit blocks including the
current sense amplifiers and is maintained at a value 5 V. AVDD is derived from the PVDD voltage power supply.
AVDD should be bypassed externally with a 1-µF capacitor to GND.
Because the allowed PVDD operating range of the device permits operation below the nominal value of AVDD,
this regulator operates in two regimes: namely a linear regulating regime and a dropout region. In the dropout
region, the AVDD will simply track the PVDD voltage minus a voltage drop.
If the device is expected to operate within the dropout region, take care while selecting current sense amplifier
components and settings to accommodate the reduced voltage rail.
7.3.7 VREG: Voltage Regulator Output
The DRV8305-Q1 integrates a 50-mA, LDO voltage regulator (VREG) that is dedicated for driving external loads
such as an MCU directly. The VREG regulator also supplies the reference for the SDO output of the SPI bus and
the voltage reference for the amplifier output bias. The three different DRV8305-Q1 device versions provide
different configurations for the VREG output. For the DRV83053Q, the VREG output is regulated at 3.3 V. For
the DRV83055Q, the VREG output is regulated at 5 V. For the DRV8305NQ and DRV8305NE, the VREG
voltage regulator is disabled (VREG pin used for reference voltage) and the reference voltage for SDO and the
amplifier output bias must be supplied from an external supply to the VREG pin.
The DRV8305-Q1 VREG voltage regulator also features a PWRGD pin to protect against brownouts on
externally driven devices. The PWRGD pin is often tied to the reset pin of a microcontroller to ensure that the
microcontroller is always reset when the VREG output voltage is outside of its recommended operation area.
When the voltage output of the VREG regulator drops or exceeds the set threshold (programmable).
• The PWRGD pin will go low for a period of 56 µs.
• After the 56-µs period has expired, the VREG voltage will be checked and PWRGD will be held low until the
VREG voltage has recovered.
The voltage regulator also has undervoltage protection implemented for both the input voltage (PVDD) and
output voltage (VREG).
7.3.8 Protection Features
7.3.8.1 Fault and Warning Classification
The DRV8305-Q1 integrates extensive error detection and monitoring features. These features allow the design
of a robust system that can protect against a variety of system related failure modes. The DRV8305-Q1 classifies
error events into two categories and takes different device actions dependent on the error classification.
The first error class is a Warning. There are several types of conditions that are classified as warning only.
Warning errors are report only and the DRV8305-Q1 will take no other action effecting the gate drivers or other
blocks. When a warning condition occurs it will be reported in the corresponding SPI status register bit and on
the nFAULT pin with a repeating 56-µs pulse low followed by a 56-µs pulse high. A warning error can be cleared
by an SPI read to the corresponding status register bit. The same warning will not be reported through the
nFAULT pin again unless that warning or condition passes and then reoccurs.
• A warning error is reported on the nFAULT pin with a repeating 56-µs pulse low followed by a 56-µs pulse
high.
• The warning is reported on the nFAULT pin until a SPI read to the corresponding status register.
• The SPI read will clear the nFAULT report, but the SPI register will remain asserted until the condition has
passed.
• The nFAULT pin will report a new warning if the condition clears and then occurs again.
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The second error class is a Fault. Fault errors will trigger a shutdown of the gate driver with its major blocks and
are reported by holding nFAULT low with the corresponding status register asserted. Fault errors are latched
until the appropriate recovery sequence is performed.
• A fault error is reported by holding the nFAULT pin low and asserting the FAULT bit in register 0x1.
• The error type will also be asserted in the SPI registers.
• A fault error is a latched fault and must be cleared with the appropriate recovery sequence.
• If a fault occurs during a warning error, the fault error will take precendence, latch nFAULT low and shutdown
the gate driver.
• The output MOSFETs will be placed into their high impedance state in a fault error event.
• To recover from a fault type error, the condition must be removed and the CLR_FLTs bit asserted in register
0x9, bit D1 or an EN_GATE reset pulse issued.
• The CLR_FLTS bit self clears to 0 after fault status reset and nFAULT pin is released.
There are two exceptions to the fault and warning error classes. The first exception is the temperature flag
warnings (TEMP_FLAGX). A Temperature Flag warning will not trigger any action on the nFAULT pin and the
corresponding status bit will be updated in real time. See the overtemperature section for additional information.
The second exception is the MCU Watchdog and VREG Undervoltage (VREG_UV) faults. These are reported on
the PWRGD pin to protect the system from lock out and brownout conditions. See their corresponding sections
for additional information.
Note that nFAULT is an open-drain signal and must be pulled up through an external resistor.
7.3.8.2 MOSFET Shoot-Through Protection (TDRIVE)
DRV8305-Q1 integrates analog handshaking and digital dead time to prevent shoot-through in the external
MOSFETs.
• An internal handshake through analog comparators is performed between each high-side and low-side
MOSFET switching transaction (see Smart Gate Drive Architecture: TDRIVE). The handshake monitors the
voltage between the gate and source of the external MOSFET to ensure the device has reached its cutoff
threshold before enabling the opposite MOSFET.
• A minimum dead time (digital) of 40 ns is always inserted after each successful handshake. This digital dead
time is programmable through the DEAD_TIME SPI setting in register 0x7, bits D6-D4 and is in addition to the
time taken for the analog handshake.
7.3.8.3 MOSFET Overcurrent Protection (VDS_OCP)
To protect the system and external MOSFET from damage due to high current events, VDS overcurrent monitors
are implemented in the DRV8305-Q1.
The VDS sensing is implemented for both the high-side and low-side MOSFETs through the pins below:
• High-side MOSFET: VDS measured between VDRAIN and SHx pins.
• Low-side MOSFET: VDS measured between SHx and SLx pins.
Based on the RDS(on) of the power MOSFETs and the maximum allowed IDS, a voltage threshold can be
calculated, which when exceeded, triggers the VDS overcurrent protection feature. The voltage threshold level
(VDS_LEVEL) is programmable through the SPI VDS_LEVEL setting in register 0xC, bits D7-D3 and may be
changed during gate driver operation if needed.
The VDS overcurrent monitors implement adjustable blanking and deglitch times to prevent false trips due to
switching voltage transients. The VDS blanking time (tBLANK) is inserted digitally and programmable through the
SPI TBLANK setting in register 0x7, bits D3-D2. The tBLANK time is inserted after each switch ON transistion
(LOW to HIGH) of the output gate drivers is commanded. During the tBLANK time, the VDS comparators are not
being monitored in order to prevent false trips when the MOSFET first turns ON. After the tBLANK time expires the
overcurrent monitors will begin actively watching for an overcurrent event.
The VDS deglitch time (tVDS) is inserted digitally and programmable through the SPI TVDS setting in register 0x7,
bits D1-D0. The tVDS time is a delay inserted after the VDS sensing comparators have tripped to when the
protection logic is informed that a VDS event has occurred. If the overcurrent event does not persist through tVDS
delay then it will be ignored by the DRV8305-Q1.
Note that the dead time and blanking time are overlapping timers as shown in Figure 13.
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INx_x
Gx_x
tDead
tBLANK
1
Input Signal
2
Output Slew
3
Expiration of Blanking
1
tdeglitch
2
3
Figure 13. VDS Deglitch and Blank Diagram
The DRV8305-Q1 has three possible responses to a VDS overcurrent event. This response is set through the SPI
VDS_MODE setting in register 0xC, bits D2-D0.
• VDS Latched Shutdown Mode:
When a VDS overcurrent event occurs, the device will pull all gate drive outputs low in order to put all six
external MOSFETs into high impedance mode. The fault will be reported on the nFAULT pin with the specific
MOSFET in which the overcurrent event was detected in reported through the SPI status registers.
• VDS Report Only Mode:
In this mode, the device will take no action related to the gate drivers. When the overcurrent event is detected
the fault will be reported on the nFAULT pin with the specific MOSFET in which the overcurrent event was
detected in reported through the SPI status registers. The gate drivers will continue to operate normally.
• VDS Disabled Mode:
The device ignores all the VDS overcurrent event detections and does not report them.
7.3.8.3.1 MOSFET dV/dt Turn On Protection (TDRIVE)
The DRV8305-Q1 gate driver implements a strong pulldown scheme during turn on of the opposite MOSFET for
preventing parasitic dV/dt turn on. Parasitic dV/dt turn on can occur when charge couples into the gate of the
low-side MOSFET during a switching event. If the charge induces enough voltage to cross the threshold of the
low-side MOSFET shoot-through can occur in the half-bridge. To prevent this the Smart Gate Drive Architecture:
TDRIVE state machine turns on a strong pulldown during switching. After the switching event has completed, the
gate driver switches back to a lower hold off pulldown to improve efficiency.
7.3.8.3.2 MOSFET Gate Drive Protection (GDF)
The DRV8305-Q1 uses a multilevel scheme to protect the external MOSFET from VGS voltages that could
damage it. The first stage uses integrated VGS clamps that will turn on when the GHx voltage exceeds the SHx
voltage by a value that could be damaging to the external MOSFETs.
The second stage relies on the TDRIVE state machine to detect when abnormal conditions are present on the
gate driver outputs. After the TDRIVE timer has expired the gate driver performs a check of the gate driver
outputs against the commanded input. If the two do not match a gate drive fault (FETXX_VGS) is reported. This
can be used to detected gate short to ground or gate short to supply event. The TDRIVE timer is adjustable for
the high-side and low-side gate drive outputs through the TDRIVEN setting in register 0x5, bits D9-D8 and the
TDRIVEP setting in register 0x6, bits D9-D8. The gate fault detection through TDRIVE can be disabled through
the DIS_GDRV_FAULT setting in register 0x9, bit D8.
The third stage uses undervoltage monitors for the low-side gate drive regulator (VCP_LSD_UVLO2) and highside gate drive charge pump (VCPH_UVLO2) and an overvoltage monitor for high-side charge pump
(VCPH_OVLO). These monitors are used to detect if any of the power supplies to the gate drivers have
encountered an abnormal condition.
7.3.8.4 Low-Side Source Monitors (SNS_OCP)
In additional to the VDS monitors across each MOSFET, the DRV8305-Q1 directly monitors the voltage on the
SLx pins with respect to ground. If high current events such phase shorts cause the SLx pin voltage to exceed 2
V, the DRV8305-Q1 will shutdown the gate driver, put the external MOSFETs into a high impedance state, and
report a SNS_OCP fault error on the nFAULT pin and corresponding SPI status bit in register 0x2, bits D2-D0.
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7.3.8.5 Fault and Warning Operating Modes
Table 6. Fault and Warning Operating Modes (1)
NAME
PVDD Undervoltage
Fault (PVDD_UVLO)
CONDITION
PVDD < VPVDD_UVLO1
GATE DRIVE OUTPUTS
GATE DRIVE SUPPLIES
INTERNAL LOGIC
PL
D
D
DEVICE ACTION
-
PVDD < VPVDD_UVLO2
PL
D
E
SPI
nFAULT Latch
PVDD Undervoltage
Warning (PVDD_UVFL)
PVDD < VPVDD_UVFL
E
E
E
SPI
nFAULT Toggle
PVDD Overvoltage
Warning (PVDD_OVFL)
PVDD > VPVDD_OVFL
E
E
E
SPI
nFAULT Toggle
Charge Pump Undervoltage
Warning (VCPH_UVFL)
VCPH < VVCPH_UVFL
E
E
E
SPI
nFAULT Toggle
Charge Pump Undervoltage
Fault (VCPH_UVLO2)
VCPH < VVCPH_UVLO2
PL
D
E
SPI
nFAULT Latch
LS Gate Supply Undervoltage
Fault (VCP_LSD_UVLO2)
VCP_LSD < VVCP_LSD_UVLO2
PL
D
E
SPI
nFAULT Latch
VCPH > VVCPH_OVLO
PL
D
E
SPI
nFAULT Latch
VCPH > VVCPH_OVLO_ABS
PL
D
E
SPI
nFAULT Latch
AVDD Undervoltage
Fault (AVDD_UVLO)
AVDD < VAVDD_UVLO
PL
D
E
SPI
nFAULT Latch
Temperature Flag
Warning (TEMP_FLAGX)
TJ > TTEMP_FLAGX
E
E
E
SPI
Overtemperature Warning
(OTW)
TJ > TOTW
E
E
E
SPI
nFAULT Toggle
Overtemperature Shutdown
Fault (OTSD)
TJ > TOTSD
PL
D
E
SPI
nFAULT Latch
Latched Shutdown
VDS > VVDS_LEVEL
PL
E
E
SPI
nFAULT Latch
Report Only
VDS > VVDS_LEVEL
E
E
E
SPI
nFAULT Toggle
Disabled
VDS > VVDS_LEVEL
E
E
E
-
Charge Pump Overvoltage
Fault (VCPH_OVLO)
MOSFET Overcurrent
Fault (VDS_OCP)
LS Overcurrent
Fault (SNS_OCP)
SLx > VSNS_OCP
PL
E
E
SPI
nFAULT Latch
Gate Drive Fault
(GDF)
See TDRIVE
PL
D
E
SPI
nFAULT Latch
MCU Watchdog
Fault (WD_FAULT)
tINTERVAL > tWD_DLY
PL
E
E
SPI
PWRGD
nFAULT Latch
VREG Undervoltage
Fault (VREG_UV)
VREG < VVREG_UV
PL
E
E
SPI
PWRGD
nFAULT Latch
(1)
E - Enabled, PL = Pulled Low, D = Disabled
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7.3.9 Undervoltage Warning (UVFL), Undervoltage Lockout (UVLO), and Overvoltage (OV) Protection
The DRV8305-Q1 implements undervoltage and overvoltage monitors on its system supplies to protect the
system, prevent brownout conditions, and prevent unexpected device behavior. Undervoltage is monitored for on
the PVDD, AVDD, VREF, VCPH, and VCP_LSD power supplies. Overvoltage is monitored for on the PVDD and
VCPH power supplies. The values for the various undervoltage and overvoltage levels are provided in the
Electrical Characteristics table under the voltage protection section.
The monitors for the main power supply, PVDD, incorporates several additional features:
• Undervoltage warning (PVDD_UVFL) level. Device operation is not impacted, report only indication.
• PVDD_UVFL is warning type error indicated on the nFAULT pin and the PVDD_UVFL status bit in register
0x1, bit D7.
• Independent UVLO levels for the gate driver (PVDD_UVLO2) and VREG LDO regulator (PVDD_UVLO1).
PVDD_UVLO2 will trigger a shutdown of the gate driver.
• PVDD_UVLO2 is a fault type error indicated on the nFAULT pin and corresponding status bit in register 0x3,
bit D10.
• PVDD_UVLO2 may be disabled through the DIS_VPVDD_UVLO setting in register 0x9, bit D9. The fault will
still be reported in the status bit in register 0x3, bit D10.
• Overvoltage detection to monitor for load dump or supply pumping conditions. Device operation is not
impacted, report only indication.
• PVDD_OV is a warning type error indicated on the nFAULT pin and the PVDD_OV bit in register 0x1, bit D6.
The monitors for the high-side charge pump supply, VCPH, and low-side supply (VCP_LSD) incorporate several
additional features:
• VCPH relative (VCPH_OVLO) and absolute overvoltage (VCPH_OVLO_ABS) detection. The DRV8305-Q1
monitors VCPH for overvoltage conditions with respect to PVDD and GND.
• VCPH_OVLO and VCPH_OVLO_ABS are fault type errors reported on nFAULT and the corresponding status
bit in register 0x3, bits D1-D0.
• VCPH undervoltage (VCPH_UVLO2) is monitored to prevent underdriven MOSFET conditions.
VCPH_UVLO2 will trigger a shutdown of the gate driver.
• VCPH_UVLO2 is a fault type error indicated on the nFAULT pin and corresponding status bit in register 0x3,
bit D2.
• VCP_LSD undervoltage (VCP_LSD_UVLO2) is monitored to prevent underdriven MOSFET conditions.
VCP_LSD_UVLO2 will trigger a shutdown of the gate driver.
• VCP_LSD_UVLO2 is a fault type error indicated on the nFAULT pin and corresponding status bit in register
0x3, bit D4.
• Undervoltage protection for VCPH and VCP_LSD may not be disabled in the operating state.
7.3.9.1 Overtemperature Warning (OTW) and Shutdown (OTSD) Protection
A multi-level temperature detection circuit is implemented in the DRV8305-Q1.
• Flag Level 1 (TEMP_FLAG1): Level 1 overtemperature flag. No warning reported on nFAULT. Real-time flag
indicated in SPI register 0x1, bit D3.
• Flag Level 2 (TEMP_FLAG2): Level 2 overtemperature flag. No warning reported on nFAULT. Real-time flag
indicated in SPI register 0x1, bit D2.
• Flag Level 3 (TEMP_FLAG3): Level 3 overtemperature flag. No warning reported on nFAULT. Real-time flag
indicated in SPI register 0x1, bit D1.
• Flag Level 4 (TEMP_FLAG4): Level 4 overtemperature flag. No warning reported on nFAULT. Real-time flag
indicated in SPI register 0x1, bit D8.
• Warning Level (OTW): Overtemperature warning only. Warning reported on nFAULT. Real-time flag indicated
in SPI register 0x1, bit D0.
• Fault Level (OTSD): Overtemperature fault and latched shut down of the device. Fault reported on nFAULT
and in SPI register 0x3, bit D8.
SPI operation is still available and register settings will be retained in the device during OTSD operation as long
as PVDD is within operation range. An OTSD fault can be cleared when the device temperature has dropped
below the fault level and a CLR_FLTS is issued.
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7.3.9.2 Reverse Supply Protection
The DRV8305-Q1 is designed to support an external reverse supply protection scheme. The VCPH high-side
charge pump is able to supply an external load up to 10 mA. This feature allows implementation of an external
reverse battery protection scheme using a MOSFET and a BJT. The MOSFET gate and BJT can be driven
through VCPH with a current limiting resistor. The current limiting resistor must be sized not to exceed the
maximum external load on VCPH.
The VDRAIN sense pin may also be protected against reverse supply conditions by use of a current limiting
resistor. The current limit resistor must be sized not to exceed the maximum current load on the VDRAIN pin.
100 Ω is recommended between VDRAIN and the drain of the external high-side MOSFET.
Supply
Reverse Polarity
MOSFET
VCPH
PVDD
Optional
Filtering or
Switch
VDRAIN
Motor
Power Stage
Figure 14. Typical Scheme for Reverse Battery Protection Using VCPH
7.3.9.3 MCU Watchdog
The DRV8305-Q1 incorporates an MCU watchdog function to ensure that the external controller that is
instructing the device is active and not in an unknown state. The MCU watchdog function may be enabled by
writing a 1 to the WD_EN setting in the SPI register 0x9, bit D3. The default setting for the device is with the
watchdog disabled. When the watchdog is enabled, an internal timer starts to countdown to the interval set by
the WD_DLY setting in the SPI register 0x9, bits D6-D5. To restart the watchdog timer, the address 0x1 (status
register) must be read by the controller within the interval set by the WD_DLY setting. If the watchdog timer is
allowed to expire without the address 0x1 being read, a watchdog fault will be enabled.
Response to a watchdog fault is as follows:
• A latched fault occurs on the DRV8305-Q1 and the gate drivers are put into a safe state. An appropriate
recovery sequence must then be performed.
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•
•
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The PWRGD pin is taken low for 56 µs and then back high in order to reset the controller or indicate the
watchdog fault.
The nFAULT pin is asserted low, the WD_EN bit is cleared, and the WD_FAULT set high in register 0x3, bit
D9.
It is recommended to read the status registers as part of the recovery or power-up routine in order to
determine whether a WD_FAULT had previously occurred.
Note that the watchdog fault results in a clearing of the WD_EN setting and it will have to be set again to resume
watchdog functionality.
7.3.9.4 VREG Undervoltage (VREG_UV)
The DRV8305-Q1 has an undervoltage monitor on the VREG output regulator to ensure the external controller
does not experience a brownout condition. The undervoltage monitor will signal a fault if the VREG output drops
below a set threshold from its set point. The VREG output set point is configured for two different levels, 3.3 V or
5 V, depending on the DRV8305-Q1 device options (DRV83053Q and DRV83055Q). The VREG undervoltage
level can be set through the SPI setting VREG_UV_LEVEL in register 0xB, bits D1-D0. The VREG undervoltage
monitor can be disabled through the SPI setting DIS_VREG_PWRGD in register 0xB, bit D2.
Response to a VREG undervoltage fault is as follows:
• A latched fault occurs on the DRV8305-Q1 and the gate drivers are put into a safe state. An appropriate
recovery sequence must then be performed.
• The PWRGD is taken low until the undervoltage condition is removed and for at least a minimum of 56 µs.
• The nFAULT pin is asserted low and the VREG_UV bit set high in register 0x3, bit D6.
• The fault can be cleared after the VREG undervoltage condition is removed with CLR_FLTS or an EN_GATE
reset pulse.
Note that the VREG undervoltage monitor is disabled on the no regulator (VREF) device option (DRV8305NQ
and DRV8305NE).
7.3.9.5 Latched Fault Reset Methods
A latched fault can be cleared after the fault condition is removed by either setting the CLR_FLTS register bit in
register 0x09 to 1 or by issuing an EN_GATE reset pulse to the DRV8305-Q1. The CLR_FLTS register bit will
automatically reset back to 0 have the fault has been cleared.
The secondary method through the EN_GATE pin requires a high-low-high pulse on the pin to clear the latched
fault. The low duration of the pulse should be greater than or equal to 1µs.
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7.4 Device Functional Modes
7.4.1 Power Up Sequence
The DRV8305-Q1 has an internal state machine to ensure proper power up and power down sequencing of the
device. When PVDD power is applied the device will remain inactive until PVDD cross the digital logic threshold.
At this point, the digital logic will become active, VREG will enable (if 3.3-V or 5-V device option is used), the
passive gate pulldowns will enable, and nFAULT will be driven low to indicate that the device has not reached
the VPVDD_UVLO2 threshold. nFAULT will remain driven low until PVDD crosses the PVDD_UVLO threshold. At this
point the device will enter its standby state.
PVDD_UVLO2
PVDD
Logic
Threshold
Power Up
Complete
nFAULT
(Active Low)
X
Logic Reset
Figure 15. Power-Up Sequence
7.4.2 Standby State
After the power up sequence is completed and the PVDD voltage is above VPVDD_UVLO2 threshold, the DRV8305Q1 will indicate successful and fault free power up of all circuits by releasing the nFAULT pin. At this point the
DRV8305-Q1 will enter its standby state and be ready to accept inputs from the external controller. The
DRV8305-Q1 will remain in or re-enter its standby state anytime EN_GATE = LOW or a fault type error has
occured. In this state the major gate driver blocks are disabled, but the passive gate pulldowns are still active to
maintain the external MOSFETs in their high-impedence state. It is recommended, but not required to perform all
device configurations through SPI in the standby state.
7.4.3 Operating State
After reaching the standby state and then taking EN_GATE from LOW to HIGH, the DRV8305-Q1 will enter its
operating state. The operating state enables the major gate driver and current shunt amplifier blocks for normal
operation. 1 ms should be allowed after EN_GATE is taken HIGH to allow the charge pump supply for the highside gate drivers to reach its steady state operating point. If at any point in its operating state a fault type error
occurs, the DRV8305-Q1 will immediately re-enter the standby state.
7.4.4
Sleep State
The sleep state can be entered by issuing a sleep command through the SLEEP bit in SPI register 0x9, bit D2
with the device in its standby state (EN_GATE = LOW). The device will not respond to a sleep command in its
operating state. After the sleep command is received, the gate drivers and output regulator (VREG) will safely
power down after a programmable delay set in the SPI register 0xB, bits D4-D3. The device can then only be
enabled through the WAKE pin which is a high-voltage tolerant input pin. For the DRV8305-Q1 to be brought out
of sleep, the WAKE pin must be at a voltage greater than 3 V. This allows the wake pin to be driven, for
example, directly by the battery through a switch, through the inhibit pin (INH) on a standard LIN interface, or
through standard digital logic. The WAKE pin will only react to a wake up command if PVDD > VPVDD_UVLO2. After
the DRV8305-Q1 is out of SLEEP mode, all activity on the WAKE pin is ignored. The sleep state erases all
values in the SPI control registers and it is not recommended to write through SPI in the sleep state.
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Device Functional Modes (continued)
7.4.5 Limp Home or Fail Code Operation
The DRV8305-Q1 enables the adoption of secondary limp-home or fail code software through configurable fault
mode handling. The following device features may be configured during the operating state without stopping the
motor.
• IDRIVE Gate Current Output (IDRIVEN_HS, IDRIVEP_HS, IDRIVEN_LS, IDRIVEP_LS): All four IDRIVEX
settings may be adjusted during normal operation without issue. This features allows the software to change
the slew rate, switching characteristics of the external MOSFETs on the fly if required without having to stop
the motor rotation. The IDRIVEX settings are located in the SPI registers 0x5 (high-side) and 0x6 (low-side).
• VDS Fault Mode (VDS_MODE): The VDS overcurrent monitors may be changed from latched shutdown
(VDS_MODE = b'000) or report only (VDS_MODE = b'001) modes to disabled (VDS_MODE = b'010) mode to
allow operation of the external MOSFETs past normal operating conditions. This is the only VDS_MODE
change allowed in the operating state. The VDS_MODE setting is located in the SPI register 0xC, bits D2-D0.
• VDS Comparator Thresholds (VDS_LEVEL): The VDS overcurrent monitor threshold (VDS_LEVEL) may be
changed at any time during operation to allow for higher than standard operating currents. The VDS_LEVEL
setting is located in the SPI register 0xC.
• VGS Fault Mode (DIS_GDRV_FAULT): The VGS fault detection monitors can be disabled through the SPI
register 0x9, bit D8. Reporting in SPI will also be disabled as a result.
• SNS_OCP Fault Mode (DIS_SNS_OCP): The sense amplifier overcurrent monitors can be disabled through
the SPI register 0x9, bit D4. Reporting in SPI will also be disabled as a result.
• PVDD Undervoltage Lockout (DIS_VPVDD_UVLO2): The main power supply undervoltage lockout can be
disabled through the SPI register 0x9, but D9. Reporting in SPI will also be disabled as a result.
• OTSD Overtemperature Shutdown (FLIP_OTS): The overtemperature shutdown can be disabled through the
SPI register 0x9, bit D10. Reporting in SPI will also be disabled as a result. The OTS overtemperature
shutdown is disabled by default on the Grade 0, DRV8305xE device.
Unpowered System
PVDD < VPVDD_UVLO1
Sleep
PVDD > VPVDD_UVLO2
PVDD < VPVDD_UVLO1
NO
WAKE > WAKE_VIH
WAKE >
WAKE_VIH
YES
Sleep = 1 through SPI
Operating
Standby
EN_GATE = High
EN_GATE = Low
Figure 16. Operating States
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7.5 Programming
7.5.1 SPI Communication
7.5.1.1 SPI
The DRV8305-Q1 uses a SPI to set device configurations, operating parameters, and read out diagnostic
information. The DRV8305-Q1 SPI operates in slave mode. The SPI input data (SDI) word consists of a 16-bit
word with a 5-bit command and 11 bits of data. The SPI output data (SDO) word consists of 11 bits of register
data with the first 5 bits (MSB) as don't cares.
A
•
•
•
•
•
•
•
•
•
valid frame must meet following conditions:
CPOL (clock polarity) = 0 and CPHA (clock phase) = 1.
SCLK must be low when nSCS transitions.
Full 16 SCLK cycles.
Data is always propagated on the rising edge of SCLK.
Data is always captured on the falling edge of SCLK.
MSB is shifted in and out first.
When nSCS is high, SCLK and SDI are ignored and SDO is high impedance.
nSCS should be taken high for at least 500 ns between frames.
If the data sent to SDI is less than or greater than 16 bits it is considered a frame error and the data will be
ignored.
7.5.1.2 SPI Format
SCS
1
2
3
4
X
15
16
SCLK
SDI
MSB
LSB
SDO
MSB
LSB
Receive
Latch Points
Figure 17. SPI Slave Mode Timing Diagram
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Programming (continued)
The SPI input data (SDI) control word is 16 bits long and consists of the following format:
• 1 read or write bit W [15]
• 4 address bits A [14:11]
• 11 data bits D [10:0]
The SPI output data (SDO) word response word is 11 bits long (first 5 bits are don't cares). It contains the
content of the register being accessed.
The MSB of the SDI word (W0) is the read/write bit. When W0 = 0, the input data is a write command. When W0
= 1, the input data is a read command.
For a write command: The response word is the data currently in the register being written.
For a read command: The response word is the data currently in the register being read.
Table 7. SPI Input Data Control Word Format
R/W
ADDRESS
DATA
Word Bit
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Command
W0
A3
A2
A1
A0
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Table 8. SPI Output Data Response Word Format
DATA
Word Bit
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Command
X
X
X
X
X
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
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7.6 Register Maps
Table 9. Register Map
ADDRESS
NAME
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0x1
Warnings &
Watchdog Reset
FAULT
RSVD
TEMP_FLAG4
PVDD_UVFL
PVDD_OVFL
VDS_STATUS
VCPH_UVFL
TEMP_FLAG1
TEMP_FLAG2
TEMP_FLAG3
OTW
0x2
OV/VDS
Faults
VDS_HA
VDS_LA
VDS_HB
VDS_LB
VDS_HC
VDS_LC
SNS_C_OCP
SNS_B_OCP
SNS_A_OCP
0x3
IC
Faults
PVDD_UVLO2
WD_FAULT
OTSD
RSVD
VREG_UV
AVDD_UVLO
VCPH_OVLO
VCPH_OVLO
_ABS
0x4
VGS
Faults
VGS_HA
VGS_LA
VGS_HB
VGS_LB
VGS_HC
VGS_LC
0x5
HS Gate Drive
Control
RSVD
TDRIVEN
IDRIVEN_HS
IDRIVEP_HS
0x6
LS Gate Drive
Control
RSVD
TDRIVEP
IDRIVEN_LS
IDRIVEP_LS
0x7
Gate Drive
Control
RSVD
COMM_OPTION
PWM_MODE
0x8
Reserved
0x9
IC Operation
FLIP_OTSD
DIS_PVDD
_UVLO2
DIS_GDRV
_FAULT
0xA
Shunt Amplifier
Control
DC_CAL_CH3
DC_CAL_CH2
DC_CAL_CH1
0xB
Voltage
Regulator Control
RSVD
0xC
VDS Sense
Control
RSVD
VCP_LSD
_UVLO2
RSVD
VCPH_UVLO2
RSVD
DEAD_TIME
TBLANK
TVDS
RSVD
VREF_SCALE
RSVD
EN_SNS
_CLAMP
WD_DLY
CS_BLANK
DIS_SNS_OCP
WD_EN
GAIN_CS3
RSVD
GAIN_CS2
SLEEP_DLY
VDS_LEVEL
SLEEP
DIS_VREG
_PWRGD
CLR_FLTS
SET_VCPH_UV
GAIN_CS1
VREG_UV_LEVEL
VDS_MODE
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7.6.1 Status Registers
The status registers are used to report device warnings, fault conditions, and provide a means to prevent timing
out of the watchdog timer. Status registers are read only registers.
7.6.1.1 Warning and Watchdog Reset (Address = 0x1)
Table 10. Warning and Watchdog Reset Register Description
BIT
R/W
NAME
DEFAULT
DESCRIPTION
10
R
FAULT
0x0
Fault indication
9
R
RSVD
0x0
-
8
R
TEMP_FLAG4
0x0
Temperature flag setting for approximately 175°C
7
R
PVDD_UVFL
0x0
PVDD undervoltage flag warning
6
R
PVDD_OVFL
0x0
PVDD overvoltage flag warning
5
R
VDS_STATUS
0x0
Real time OR of all VDS overcurrent monitors
4
R
VCHP_UVFL
0x0
Charge pump undervoltage flag warning
3
R
TEMP_FLAG1
0x0
Temperature flag setting for approximately 105°C
2
R
TEMP_FLAG2
0x0
Temperature flag setting for approximately 125°C
1
R
TEMP_FLAG3
0x0
Temperature flag setting for approximately 135°C
0
R
OTW
0x0
Overtemperature warning
7.6.1.2 OV/VDS Faults (Address = 0x2)
Table 11. OV/VDS Faults Register Description
BIT
R/W
NAME
DEFAULT
DESCRIPTION
10
R
VDS_HA
0x0
VDS overcurrent fault for high-side MOSFET A
9
R
VDS_LA
0x0
VDS overcurrent fault for low-side MOSFET A
8
R
VDS_HB
0x0
VDS overcurrent fault for high-side MOSFET B
7
R
VDS_LB
0x0
VDS overcurrent fault for low-side MOSFET B
6
R
VDS_HC
0x0
VDS overcurrent fault for high-side MOSFET C
5
R
VDS_LC
0x0
VDS overcurrent fault for low-side MOSFET C
4:3
R
RSVD
0x0
-
2
R
SNS_C_OCP
0x0
Sense C overcurrent fault
1
R
SNS_B_OCP
0x0
Sense B overcurrent fault
0
R
SNS_A_OCP
0x0
Sense A overcurrent fault
38
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7.6.1.3 IC Faults (Address = 0x3)
Table 12. IC Faults Register Description
BIT
R/W
NAME
DEFAULT
DESCRIPTION
10
R
PVDD_UVLO2
0x0
PVDD undervoltage 2 fault
9
R
WD_FAULT
0x0
Watchdog fault
8
R
OTSD
0x0
Overtemperature fault
7
R
RSVD
0x0
-
6
R
VREG_UV
0x0
VREG undervoltage fault
5
R
AVDD_UVLO
0x0
AVDD undervoltage fault
4
R
VCP_LSD_UVLO2
0x0
Low-side gate supply fault
3
R
RSVD
0x0
-
2
R
VCPH_UVLO2
0x0
High-side charge pump undervoltage 2 fault
1
R
VCPH_OVLO
0x0
High-side charge pump overvoltage fault
0
R
VCPH_OVLO_ABS
0x0
High-side charge pump overvoltage ABS fault
7.6.1.4 VGS Faults (Address = 0x4)
Table 13. Gate Driver VGS Faults Register Description
BIT
R/W
NAME
DEFAULT
DESCRIPTION
10
R
VGS_HA
0x0
VGS gate drive fault for high-side MOSFET A
9
R
VGS_LA
0x0
VGS gate drive fault for low-side MOSFET A
8
R
VGS_HB
0x0
VGS gate drive fault for high-side MOSFET B
7
R
VGS_LB
0x0
VGS gate drive fault for low-side MOSFET B
6
R
VGS_HC
0x0
VGS gate drive fault for high-side MOSFET C
5
R
VGS_LC
0x0
VGS gate drive fault for low-side MOSFET C
4:0
R
RSVD
0x0
-
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7.6.2 Control Registers
Control registers are used to set the device parameters for DRV8305-Q1. The default values are shown in bold.
• Control registers are read/write registers
• Do not clear on register read, CLR_FLTs, or EN_GATE resets
• Cleared to default values on power up
• Cleared to default values when the device enters SLEEP mode
7.6.2.1
HS Gate Drive Control (Address = 0x5)
Table 14. HS Gate Driver Control Register Description
BIT
R/W
NAME
DEFAULT
DESCRIPTION
10
R/W
RSVD
0x0
-
9:8
R/W
TDRIVEN
0x3
High-side gate driver peak source time
b'00 - 220 ns
b'01 - 440 ns
b'10 - 880 ns
b'11 - 1780 ns
7:4
R/W
IDRIVEN_HS
0x4
High-side gate driver peak sink current
b'0000 - 20 mA
b'0100 - 60 mA
b'1000 - 0.50 A
b'1100 - 60 mA
3:0
R/W
IDRIVEP_HS
0x4
- 30 mA
- 70 mA
- 0.75 A
- 60 mA
b'0010
b'0110
b'1010
b'1110
- 40 mA
- 80 mA
- 1.00 A
- 60 mA
b'0011
b'0111
b'1011
b'1111
- 50 mA
- 0.25 A
- 1.25 A
- 60 mA
- 30 mA
- 70 mA
- 0.75 A
- 50 mA
b'0011
b'0111
b'1011
b'1111
- 40 mA
- 0.125 A
- 1.00 A
- 50 mA
- 40 mA
- 80 mA
- 1.00 A
- 60 mA
b'0011
b'0111
b'1011
b'1111
- 50 mA
- 0.25 A
- 1.25 A
- 60 mA
- 30 mA
- 70 mA
- 0.75 A
- 50 mA
b'0011
b'0111
b'1011
b'1111
- 40 mA
- 0.125 A
- 1.00 A
- 50 mA
High-side gate driver peak source current
b'0000 - 10 mA
b'0100 - 50 mA
b'1000 - 0.25 A
b'1100 - 50 mA
7.6.2.2
b'0001
b'0101
b'1001
b'1101
b'0001
b'0101
b'1001
b'1101
- 20 mA
- 60 mA
- 0.50 A
- 50 mA
b'0010
b'0110
b'1010
b'1110
LS Gate Drive Control (Address = 0x6)
Table 15. LS Gate Driver Control Register Description
BIT
R/W
NAME
DEFAULT
DESCRIPTION
10
R/W
RSVD
0x0
-
9:8
R/W
TDRIVEP
0x3
Low-side gate driver peak source time
b'00 - 220 ns
b'01 - 440 ns
b'10 - 880 ns
b'11 - 1780 ns
7:4
R/W
IDRIVEN_LS
0x4
Low-side gate driver peak sink current
b'0000 - 20 mA
b'0100 - 60 mA
b'1000 - 0.50 A
b'1100 - 60 mA
3:0
R/W
IDRIVEP_LS
0x4
- 30 mA
- 70 mA
- 0.75 A
- 60 mA
b'0010
b'0110
b'1010
b'1110
Low-side gate driver peak source current
b'0000 - 10 mA
b'0100 - 50 mA
b'1000 - 0.25 A
b'1100 - 50 mA
40
b'0001
b'0101
b'1001
b'1101
b'0001
b'0101
b'1001
b'1101
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- 20 mA
- 60 mA
- 0.50 A
- 50 mA
b'0010
b'0110
b'1010
b'1110
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7.6.2.3
SLVSD12D – MAY 2015 – REVISED JULY 2019
Gate Drive Control (Address = 0x7)
Table 16. Gate Drive Control Register Description
BIT
R/W
NAME
DEFAULT
DESCRIPTION
10
R/W
VCPH_FREQ
0x0
Reduce charge pump frequency center and spread
b'0 - Center = 518 kHz, Spread = 438 kHz - 633 kHz
b'1 - Center = 452 kHz, Spread = 419 kHz - 491 kHz
9
R/W
COMM_OPTION
0x1
Rectification control (PWM_MODE = b'10 only)
b'0 - diode freewheeling
b'1 - active freewheeling
8:7
R/W
PWM_MODE
0x0
PWM Mode
b'00 - PWM with 6 independent inputs
b'01 - PWM with 3 independent inputs
b'10 - PWM with one input
b'11 - PWM with 6 independent inputs
6:4
R/W
DEAD_TIME
0x1
Dead time
b'000 - 35 ns
b'011 - 440 ns
b'110 - 3520 ns
3:2
R/W
TBLANK
0x1
VDS sense blanking
b'00 - 0 µs
b'01 - 1.75 µs
b'10 - 3.5 µs
b'11 - 7 µs
1:0
R/W
TVDS
0x2
VDS sense deglitch
b'00 - 0 µs
b'01 - 1.75 µs
b'10 - 3.5 µs
b'11 - 7 µs
b'001 - 52 ns
b'100 - 880 ns
b'111 - 5280 ns
b'010 - 88 ns
b'101 - 1760 ns
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IC Operation (Address = 0x9)
Table 17. IC Operation Register Description
BIT
R/W
NAME
DEFAULT
DESCRIPTION
10
R/W
FLIP_OTSD
0x0
OTSD control setting
DRV8305xQ
b'0 - Enable OTSD
b'1 - Disable OTSD
DRV8305xE
b'0 - Disable OTSD (1)
b'1 - Enable OTSD
9
R/W
DIS_PVDD_UVLO2
0x0
Disable PVDD_UVLO2 fault and reporting
b'0 - PVDD_UVLO2 enabled
b'1 - PVDD_UVLO2 disabled
8
R/W
DIS_GDRV_FAULT
0x0
Disable gate drive fault and reporting
b'0 - Gate driver fault enabled
b'1 - Gate driver fault disabled
7
R/W
EN_SNS_CLAMP
0x0
Enable sense amplifier clamp
b'0 - Sense amplifier clamp is not enabled
b'1 - Sense amplifier clamp is enabled, limiting output to ~3.3 V
6:5
R/W
WD_DLY
0x1
Watchdog delay
b'00 - 10 ms
b'01 - 20 ms
b'10 - 50 ms
b'11 - 100 ms
4
R/W
DIS_SNS_OCP
0x0
Disable SNS overcurrent protection fault and reporting
b'0 - SNS OCP enabled
b'1 - SNS OCP disabled
3
R/W
WD_EN
0x0
Watchdog enable
b'0 - Watch dog disabled
b'1 - Watch dog enabled
2
R/W
SLEEP
0x0
Put device into sleep mode
b'0 - Device awake
b'1 - Device asleep
1
R/W
CLR_FLTS
0x0
Clear faults
b'0 - Normal operation
b'1 - Clear faults
0
R/W
SET_VCPH_UV
0x0
Set charge pump undervoltage threshold level
b'0 - 4.9 V
b'1 - 4.6 V
(1)
42
Overtemperature shutdown (OTSD) is disabled by default for DRV8305xEPHPQ1 and may only be re-enabled through this control bit.
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7.6.2.5
SLVSD12D – MAY 2015 – REVISED JULY 2019
Shunt Amplifier Control (Address = 0xA)
Table 18. Shunt Amplifier Control Register Description
BIT
R/W
NAME
DEFAULT
DESCRIPTION
10
R/W
DC_CAL_CH3
0x0
DC calibration of CS amplifier 3
b'0 - Normal operation
b'1 - DC calibration mode
9
R/W
DC_CAL_CH2
0x0
DC calibration of CS amplifier 2
b'0 - Normal operation
b'1 - DC calibration mode
8
R/W
DC_CAL_CH1
0x0
DC calibration of CS amplifier 1
b'0 - Normal operation
b'1 - DC calibration mode
7:6
R/W
CS_BLANK
0x0
Current shunt amplifier blanking time
b'00 - 0 ns
b'01 - 500 ns
b'10 - 2.5 µs
b'11 - 10 µs
5:4
R/W
GAIN_CS3
0x0
Gain of CS amplifier 3
b'00 - 10 V/V
b'01 - 20 V/V
b'10 - 40 V/V
b'11 - 80 V/V
3:2
R/W
GAIN_CS2
0x0
Gain of CS amplifier 2
b'00 - 10 V/V
b'01 - 20 V/V
b'10 - 40 V/V
b'11 - 80 V/V
1:0
R/W
GAIN_CS1
0x0
Gain of CS amplifier 1
b'00 - 10 V/V
b'01 - 20 V/V
b'10 - 40 V/V
b'11 - 80 V/V
7.6.2.6
Voltage Regulator Control (Address = 0xB)
Table 19. Voltage Regulator Control Register Description
BIT
R/W
NAME
DEFAULT
DESCRIPTION
10
R/W
RSVD
0x0
-
9:8
R/W
VREF_SCALE
0x1
VREF Scaling
b'00 - RSVD
b'01 - k = 2
b'10 - k = 4
b'11 - k = 8
7:5
R/W
RSVD
0x0
-
4:3
R/W
SLEEP_DLY
0x1
Delay to power down VREG after SLEEP
b'00 - 0 µs
b'01 - 10 µs
b'10 - 50 µs
b'11 - 1 ms
2
R/W
DIS_VREG_PWRGD
0x0
Disable VREG undervoltage fault and reporting
b'0 - VREG_UV enabled
b'1 - VREG_UV disabled
0:1
R/W
VREG_UV_LEVEL
0x2
VREG undervoltage set point
b'00 - VREG x 0.9
b'01 - VREG x 0.8
b'10 - VREG x 0.7
b'11 - VREG x 0.7
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VDS Sense Control (Address = 0xC)
Table 20. VDS Sense Control Register Description
BIT
R/W
NAME
DEFAULT
DESCRIPTION
10:8
R
RSVD
0x0
These bits are reserved for internal use for revision ID.
7:3
R/W
VDS_LEVEL
0x19
VDS comparator threshold
b'00000
b'00100
b'01000
b'01100
b'10000
b'10100
b'11000
b'11100
2:0
44
R/W
VDS_MODE
0x0
- 0.060
- 0.097
- 0.155
- 0.250
- 0.403
- 0.648
- 1.043
- 1.679
V
V
V
V
V
V
V
V
b'00001 - 0.068 V
b'00101 - 0.109 V
b'01001 - 0.175 V
b'01101 - 0.282 V
b'10001 - 0.454 V
b'10101 - 0.730 V
b'11001 - 1.175 V
b'11101 - 1.892 V
b'00010
b'00110
b'01010
b'01110
b'10010
b'10110
b'11010
b'11110
- 0.076 V
- 0.123 V
- 0.197V
- 0.317 V
- 0.511 V
- 0.822 V
- 1.324 V
- 2.131 V
b'00011
b'00111
b'01011
b'01111
b'10011
b'10111
b'11011
b'11111
- 0.086
- 0.138
- 0.222
- 0.358
- 0.576
- 0.926
- 1.491
- 2.131
V
V
V
V
V
V
V
V
VDS mode
b'000 - Latched shut down when overcurrent detected
b'001 - Report only when overcurrent detected
b'010 - VDS protection disabled (no overcurrent sensing or reporting)
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DRV8305-Q1 is a gate driver IC designed to drive a 3-phase BLDC motor in combination with external
power MOSFETs. The device provides a high level of integration with three half-bridge gate drivers, three current
shunt amplifiers, adjustable slew rate control, logic LDO, and a suite of protection features.
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8.2 Typical Application
The following design is a common application of the DRV8305-Q1.
PVDD
4.7µF
PVDD
1 µF
2.2 µF
1 µF
PVDD
24
23
22
21
13
10 k
27
26
25
GL_A
GL_B
1 µF
34.8 k
GL_B
34.8 k
SL_A
GL_A
GL_C
SL_A
SN1
GH_C
1000 pF
SH_C
SP1
SL_B
SN2
1000 pF
SP2
SL_C
SN3
1000 pF
0.1 µF
SH_B
GH_B
4.99 k
SL_B
CSENSE
28
SH_C
5m
29
VCC
SH_B
0.1 µF
30
SH_A
4.99 k
31
GH_C
VCC
34.8 k
32
SH_A
4.99 k
33
GH_B
VCC
BSENSE
GL_C
34
1 µF
1 µF
SCLK
35
GH_A
GH_A
SP3
SL_C
GL_C
SP1
SL_C
SN1
SH_C
SDO
SP2
SDI
SN2
GH_C
SP3
nSCS
36
5m
GH_B
VCC
PVDD
PVDD
37
VCP_LSD
38
39
CP2H
VCPH
41
40
CP2L
PVDD
42
CP1L
CP1H
43
44
VDRAIN
46
45
GND
DVDD
nFAULT
PWRGD
12
SH_B
20
11
INLC
SN3
10
SPI
DRV8305
SO3
9
SL_B
19
GPIO
GL_B
INHC
SO2
8
INLB
18
7
10 k
SL_A
GL_A
17
6
PWR_PAD (0) - GND
INHB
SO1
5
VCC
INLA
AVDD
4
GH_A
SH_A
16
3
PWM
INHA
GND
2
EN_GATE
15
1
GPIO
WAKE
48
VREG
POWER
47
1 µF
VCC
14
MCU
5m
0.047 µF
0.1 µF
0.047 µF
ASENSE
100
VCC
PVDD
VCC
34.8 k
0.01 µF
0.1 µF
+
470 µF
+
470 µF
SP1
SP2
SN1
SP3
SN2
1 µF
SN3
GPIO
4.99 k
ADC
ASENSE
0.1 µF
PVDDSENSE
PVDDSENSE
BSENSE
CSENSE
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Figure 18. Typical Application Schematic
46
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8.2.1 Design Requirements
Table 21. Design Parameters
DESIGN PARAMETER
Supply voltage
REFERENCE
VALUE
PVDD
12 V
MR
0.5 Ω
Motor winding inductance
ML
0.28 mH
Motor poles
MP
16 poles
Motor rated RPM
MRPM
2000 RPM
Number of MOSFETs switching
NSW
6
Switching frequency
fSW
45 kHz
IDRIVEP
IDRIVEP
50 mA
IDRIVEN
Motor winding resistance
IDRIVEN
60 mA
MOSFET QG
Qg
36 nC
MOSFET QGD
QGD
9 nC
RDS(on)
4.1 mΩ
MOSFET RDS(on)
Target full-scale current
IMAX
30 A
Sense resistor
RSENSE
0.005 Ω
VDS trip level
VDS_LVL
0.197 V
Amplifier bias
VBIAS
1.65 V
Amplifier gain
Gain
10 V/V
8.2.2 Detailed Design Procedure
8.2.2.1 Gate Drive Average Current
The gate drive supply (VCP) of the DRV8305-Q1 is capable of delivering up to 30 mA (RMS) of current to the
external power MOSFETs. The charge pump directly supplies the high-side N-channel MOSFETs and a 10-V
LDO powered from VCP supplies the low-side N-channel MOSFETs. The designer can determine the
approximate RMS load on the gate drive supply through the following equation.
Gate Drive RMS Current = MOSFET Qg × Number of Switching MOSFETs × Switching Frequency
(2)
Example: 36 nC (QG) × 6 (NSW) × 45 kHz (fSW) = 9.72 mA
Note that this is only a first-order approximation.
8.2.2.2 MOSFET Slew Rates
The rise and fall times of the external power MOSFET can be adjusted through the use of the DRV8305-Q1
IDRIVE setting. A higher IDRIVE setting will charge the MOSFET gate more rapidly where a lower IDRIVE
setting will charge the MOSFET gate more slowly. System testing requires fine tuning to the desired slew rate,
but a rough first-order approximation can be calculated as shown in the following.
MOSFET Slew Rate = MOSFET QGD / IDRIVE Setting
(3)
Example: 9 nC (QGD) / 50 mA (IDRIVEP) = 180 ns
8.2.2.3 Overcurrent Protection
The DRV8305-Q1 provides overcurrent protection for the external power MOSFETs through the use of VDS
monitors for both the high-side and low-side MOSFETs. These are intended for protecting the MOSFET in
overcurrent conditions and are not for precise current regulation.
The overcurrent protection works by monitoring the VDS voltage drop of the external MOSFETs and comparing it
against the internal VDS_LEVEL set through the SPI registers. The high-side VDS is measured across the
VDRAIN and SH_X pins. The low-side VDS is measured across the SH_X and SL_X pins. If the VDS voltage
exceeds the VDS_LEVEL value, the DRV8305-Q1 will take action according to the VDS_MODE register.
The overcurrent trip level can be determined with the MOSFET RDS(on) and the VDS_LEVEL setting.
Overcurrent Trip = VDS Level (VDS_LVL) / MOSFET RDS(on) (RDS(on))
(4)
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Example: 0.197 V (VDS_LVL) / 4.1 mΩ (RDS(ON)) = 48 A
8.2.2.4 Current Sense Amplifiers
The DRV8305-Q1 provides three bidirectional low-side current shunt amplifiers. These can be used to sense the
current flowing through each half-bridge. If individual half-bridge sensing is not required, a single current shunt
amplifier can be used to measure the sum of the half-bridge current. Use this simple procedure to correctly
configure the current shunt amplifiers.
1. Determine the peak current that the motor will demand (IMAX). This demand depends on the motor
parameters and the application requirements. IMAX in this example is 14 A.
2. Determine the available voltage output range for the current shunt amplifiers. This will be the ± voltage
around the amplifier bias voltage (VBIAS). In this case VBIAS = 1.65 V and a valid output voltage is 0 to 3.3
V. This gives an output range of ±1.65 V.
3. Determine the sense resistor value and amplifier gain settings. The sense resistor value and amplifier gain
have common tradeoffs. The larger the sense resistor value, the better the resolution of the half-bridge
current. This comes at the cost of additional power dissipated from the sense resistor. A larger gain value
allows for the use of a smaller resolution, but at the cost of increased noise in the output signal and a longer
settling time. This example uses a 5-mΩ sense resistor and the minimum gain setting of the DRV8305-Q1
(10 V/V). These values allow the current shunt amplifiers to measure ±33 A across the sense resistor.
8.2.3 VREG Reference Voltage Input (DRV8305N)
For the DRV8305N, the VREG pin is used for a reference voltage of current sense amplifier and SDO pullup as
described in VREG: Voltage Regulator Output. The internal LDO is disabled, but the LDO physically exists in the
device, and there is a current path from the VREG pin to the PVDD pin through the internal LDO. The reference
current specified in the data sheet flows to the device if PVDD voltage (VPVDD) is higher than VREG pin voltage
(VVREG). In case VVREG is higher than VPVDD during power up/down sequence, TI recommends to limit the current
by adding a resistor to VREG pin so that the current does not exceed 50 mA. As shown in Figure 19, a 330-Ω
resistor helps limit the current to approximately 15 mA when VVREG = 5 V and VPVDD = 0 V. For VVREG = 3.3 V, TI
recommends to use 220 Ω.
VPVDD
VPVDD < VVREG at
power up/down
PVDD
DRV830 5N
interna l LDO
AVDD
Resistor to
limit curren t
disable d
VVREG
330
VREG
Curren t Sense
Power Sup ply IC
1 …F
SOx
SDO
Figure 19. VREG Reference Voltage Input
48
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SLVSD12D – MAY 2015 – REVISED JULY 2019
8.2.4 Application Curves
Figure 20. Gate Drive 20% Duty Cycle
Figure 21. Gate Drive 80% Duty Cycle
Figure 22. Motor Spinning 1000 RPM
Figure 23. Motor Spinning 2000 RPM
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9 Power Supply Recommendations
9.1 Power Supply Consideration in Generator Mode
When the motor shaft of BLDC or PMSM motor is turned by an external force, the motor windings will generate a
voltage on the motor inputs. This condition is known as generator mode or motor back-drive. In the generator
mode, a positive voltage can be observed on SHx pins of the device. If there is a switch between VDRAIN and
PVDD (SWVDRAIN in Figure 24 ), and the following conditions exist in the system, the absolute maximum voltage
of VCPH with respect to PVDD must be reviewed:
• Generator mode
• SWVDRAIN is off
• PVDD and VCPH are low voltage (for example, PVDD = 0 V)
If SHx voltage (VSHx) exceeds the VCPH voltage, the VCPH voltage starts following VSHx because of the device
internal diodes D1 and D2 (or D3). If the VCPH-PVDD voltage exceeds the absolute maximum voltage of
DRV8305-Q1, the ESD diode D4 starts conducting, and results in a big current from SHx to PVDD through the
diodes D2, D1, and D4. To avoid this condition, TI recommends to add an external diode DVDRAIN_PVDD between
VDRAIN and PVDD.
SW VDR AIN
12-V Batte ry
Optiona l
PVDD
VCPH
DVDR AIN_PVDD
DRV830 5-Q1
ESD
VDRAIN
D4
D1
GHx
Level
shifter
INHx
D2
exte rnal
force
D3
SHx
VSHx
M
VCP_LSD
GLx
Level
shifter
INL x
SLx
GND
Figure 24. Power Supply Consideration in Generator Mode
9.2 Bulk Capacitance
Having appropriate local bulk capacitance is an important factor in motor drive system design. It is generally
beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size.
The amount of local capacitance needed depends on a variety of factors, including the:
• Highest current required by the motor system
• Power supply’s capacitance and ability to source or sink current
50
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Bulk Capacitance (continued)
•
•
•
•
Amount of parasitic inductance between the power supply and motor system
Acceptable voltage ripple
Type of motor used (brushed DC, brushless DC, stepper)
Motor braking method
The inductance between the power supply and motor drive system will limit the rate that current can change from
the power supply. If the local bulk capacitance is too small, the system will respond to excessive current
demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor
voltage remains stable and high current can be quickly supplied.
The data sheet generally provides a recommended value, but system-level testing is required to determine the
appropriate-sized bulk capacitor.
Parasitic Wire
Inductance
Motor Drive System
Power Supply
VM
+
+
Motor Driver
±
GND
Local
Bulk Capacitor
IC Bypass
Capacitor
Figure 25. Example Setup of Motor Drive System With External Power Supply
The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases
when the motor transfers energy to the supply.
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10 Layout
10.1 Layout Guidelines
Use the following layout recommendations when designing a PCB for the DRV8305-Q1.
• The DVDD and AVDD 1-μF bypass capacitors should connect directly to the adjacent GND pin to minimize
loop impedance for the bypass capacitor.
• The CP1 and CP2 0.047-μF flying capacitors should be placed directly next to the DRV8305-Q1 charge pump
pins.
• The VCPH 2.2-μF and VCP_LSD 1-μF bypass capacitors should be placed close to their corresponding pins
with a direct path back to the DRV8305-Q1 PVDD for VCPH and GND for VCP_LSD.
• The PVDD 4.7-μF bypass capacitor should be placed as close as possible to the DRV8305-Q1 PVDD supply
pin.
• Use the proper footprint as shown in the mechanical drawing.
• Minimize the loop length for the high-side and low-side gate drivers. The high-side loop is from the DRV8305Q1 GH_X to the power MOSFET and returns through SH_X. The low-side loop is from the DRV8305-Q1
GL_X to the power MOSFET and returns through SL_X.
• The VDRAIN pin is used to sense the DRAIN voltage of the high-side MOSFETs for the VDS overcurrent
monitors. It should route through the 100-Ω series resistor directly to the MOSFET DRAIN, ideally at the
midpoint of the half-bridge connections in order to get the most accurate sense point.
10.2 Layout Example
PVDD
4.7 µF
PVDD
2.2 µF
100
VCC
1 µF
0.047 µF
1 µF
0.047 µF
2
INHA
3
INLA
4
48
47
46
45
44
43
42
41
40
39
38
37
DVDD
GND
VDRAIN
CP1H
CP1L
PVDD
CP2L
CP2H
VCPH
VCP_LSD
5m
GH_A
35
34
INHB
GL_A
33
5
INLB
GL_B
32
6
INHC
SL_B
31
7
INLC
SH_B
30
8
nFAULT
GH_B
29
9
nSCS
GH_C
28
10
SDI
SH_C
27
11
SDO
SL_C
26
5m
24
23
22
21
20
19
18
17
16
15
14
13
1000 pF
1000 pF
10 k
1000 pF
S
D
S
S
D
OUTA
D
S
D
G
D
D
G
D
S
D
S
D
S
S
D
OUTB
D
S
D
G
D
25
VCC
1 µF
S
S
SP1
SN1
SP2
SN2
SP3
SN3
SO3
SO2
GL_C
SO1
SCLK
PWRGD
12
G
D
36
SL_A
DRV8305
D
D
S
SH_A
PWR_PAD (0) - GND
AVDD
10 k
EN_GATE
GND
VCC
VREG
1
WAKE
1 µF
5m
Legend
Top Layer
D
G
D
S
D
S
D
S
S
D
S
D
S
D
G
D
OUTC
Via
Copyright © 2016, Texas Instruments Incorporated
Figure 26. Layout Recommendation
52
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SLVSD12D – MAY 2015 – REVISED JULY 2019
11 Device and Documentation Support
11.1 Documentation Support
See the following documents for additional information.
• Texas Instruments, Automotive 12 V 200 W (20 A) BLDC Motor Drive Reference Design
• Texas Instruments, Automotive Two-Axis Power Seat Drive Reference Design
• Texas Instruments, PowerPAD™ Thermally Enhanced Package application report
• Texas Instruments, PowerPAD™ Made Easy application report
• Texas Instruments, Sensored 3-Phase BLDC Motor Control Using MSP430 application report
• Texas Instruments, Understanding IDRIVE and TDRIVE in TI Motor Gate Drivers application report
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
(4/5)
(6)
DRV83053QPHPQ1
ACTIVE
HTQFP
PHP
48
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
DRV83053Q
DRV83053QPHPRQ1
ACTIVE
HTQFP
PHP
48
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
DRV83053Q
DRV83055QPHPQ1
ACTIVE
HTQFP
PHP
48
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
DRV83055Q
DRV83055QPHPRQ1
ACTIVE
HTQFP
PHP
48
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
DRV83055Q
DRV8305NEPHPQ1
ACTIVE
HTQFP
PHP
48
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 150
DRV8305NE
DRV8305NEPHPRQ1
ACTIVE
HTQFP
PHP
48
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 150
DRV8305NE
DRV8305NQPHPQ1
ACTIVE
HTQFP
PHP
48
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
DRV8305NQ
DRV8305NQPHPRQ1
ACTIVE
HTQFP
PHP
48
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
DRV8305NQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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