DRV8312, DRV8332
SLES256F – MAY 2010 – REVISED MAY 2022
DRV83x2 Three-Phase PWM Motor Driver
1 Features
3 Description
•
The DRV83x2 are high-performance, integrated threephase motor drivers with an advanced protection
system.
•
•
•
•
•
•
•
•
•
•
High-Efficiency Power Stage (up to 97%) With Low
RDS(on) MOSFETs (80 mΩ at TJ = 25°C)
Operating Supply Voltage up to 50 V
(70-A Absolute Maximum)
DRV8312 (Power Pad Down): up to 3.5-A
Continuous Phase Current (6.5-A Peak)
DRV8332 (Power Pad Up): up to 8-A Continuous
Phase Current (13-A Peak)
Independent Control of Three Phases
PWM Operating Frequency up to 500 kHz
Integrated Self-Protection Circuits Including
Undervoltage, Overtemperature, Overload, and
Short Circuit
Programmable Cycle-by-Cycle Current Limit
Protection
Independent Supply and Ground Pins for Each
Half Bridge
Intelligent Gate Drive and Cross Conduction
Prevention
No External Snubber or Schottky Diode is
Required
2 Applications
•
•
•
•
•
BLDC Motors
Three-Phase Permanent Magnet Synchronous
Motors
Inverters
Half Bridge Drivers
Robotic Control Systems
PVDD
GVDD
GVDD_B
OTW
FAULT
PWM_A
OUT_A
GND_A
PWM_B
GND_B
GND
GVDD
OUT_B
PVDD_B
AGND
BST_B
VREG
NC
M3
NC
M2
GND
M1
Device Information
(1)PART
GND_C
OUT_C
RESET_B
PVDD_C
GVDD_C
NUMBER
PACKAGE
BODY SIZE (NOM)
DRV8312
HTSSOP (44)
14.00 mm × 6.10 mm
DRV8332
HSSOP (36)
15.90 mm × 11.00 mm
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
GND
PWM_C
RESET_C
VDD
The DRV83x2 have unique independent supply and
ground pins for each half-bridge. These pins make
it possible to provide current measurement through
external shunt resistor and support half bridge drivers
with different power supply voltage requirements.
BST_A
PVDD_A
RESET_A
OC_ADJ
The DRV83x2 require two power supplies, one at
12 V for GVDD and VDD, and another up to 50 V
for PVDD. The DRV83x2 can operate at up to 500kHz switching frequency while still maintaining precise
control and high efficiency. The devices also have an
innovative protection system safeguarding the device
against a wide range of fault conditions that could
damage the system. These safeguards are shortcircuit protection, overcurrent protection, undervoltage
protection, and two-stage thermal protection. The
DRV83x2 have a current-limiting circuit that prevents
device shutdown during load transients such as motor
start-up. A programmable overcurrent detector allows
adjustable current limit and protection level to meet
different motor requirements.
GVDD_A
M
Controller
Because of the low RDS(on) of the power MOSFETs
and intelligent gate drive design, the efficiency of
these motor drivers can be up to 97%. This high
efficiency the use of smaller power supplies and
heatsinks, and the devices are good candidates for
energy-efficient applications.
BST_C
GVDD_C
Simplified Application Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRV8312, DRV8332
www.ti.com
SLES256F – MAY 2010 – REVISED MAY 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings........................................ 6
6.2 ESD Ratings............................................................... 6
6.3 Recommended Operating Conditions.........................6
6.4 Thermal Information....................................................7
6.5 Dissipation Ratings..................................................... 7
6.6 Power Deratings (DRV8312)...................................... 7
6.7 Electrical Characteristics.............................................8
6.8 Typical Characteristics................................................ 9
7 Detailed Description......................................................10
7.1 Overview................................................................... 10
7.2 Functional Block Diagram......................................... 10
7.3 Feature Description...................................................10
7.4 Device Functional Modes..........................................13
8 Application and Implementation.................................. 16
8.1 Application Information............................................. 16
8.2 Typical Applications.................................................. 16
9 Power Supply Recommendations................................23
9.1 Bulk Capacitance...................................................... 23
9.2 System Power-Up and Power-Down Sequence....... 23
9.3 System Design Recommendations...........................24
10 Layout...........................................................................25
10.1 Layout Guidelines................................................... 25
10.2 Layout Example...................................................... 25
10.3 Thermal Considerations..........................................29
11 Device and Documentation Support..........................30
11.1 Related Links.......................................................... 30
11.2 Trademarks............................................................. 30
11.3 Electrostatic Discharge Caution.............................. 30
11.4 Glossary.................................................................. 30
12 Mechanical, Packaging, and Orderable
Information.................................................................... 30
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (July 2014) to Revision F (May 2022)
Page
• Updated the Programming-Resistor Values and OC Threshold table...............................................................11
Changes from Revision D (January 2014) to Revision E (July 2014)
Page
• Added ESD Ratings table, Features Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section..........................................................................................................................1
Changes from Revision C (October 2013) to Revision D (January 2014)
Page
• Changed GND_A, GND_B, and GND_C pins description to remove text "requires close decoupling capacitor
to ground"........................................................................................................................................................... 4
• Changed M2 pin description From: Mode selection pin......................................................................................4
• Added the THERMAL INFORMATION table.......................................................................................................7
• Added text to the Overcurrent (OC) Protection section - "It is important to note..." ......................................... 11
• Added text to the Overcurrent (OC) Protection section - "The values in Table 7-2 show typical..." ................. 11
Changes from Revision B (September 2013) to Revision C (October 2013)
Page
• Changed text in the Overcurrent (OC) Protection section From: "cause the device to shutdown immediately."
To: "cause the device to shutdown."................................................................................................................. 11
• Changed Changed text in the Overcurrent (OC) Protection section From: " RESET_B, and / or must be
asserted." To: ", and must be asserted"............................................................................................................ 11
• Changed paragraph in the DEVICE RESET "A rising-edge transition..."......................................................... 13
Changes from Revision A (July 2013) to Revision B (September 2013)
Page
• Changed the description of pin M3 From: AGND connection is recommended To: VREG connection is
recommended.....................................................................................................................................................4
2
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SLES256F – MAY 2010 – REVISED MAY 2022
Changes from Revision * (May 2010) to Revision A (July 2013)
Page
• Changed text in the OC_ADJ Pin section From: "For accurate control of the oevercurrent protection..." To:
"For accurate control of the overcurrent protection..."...................................................................................... 24
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SLES256F – MAY 2010 – REVISED MAY 2022
5 Pin Configuration and Functions
GVDD_C
1
44
VDD
NC
NC
PWM_C
2
43
3
42
4
41
5
40
RESET_C
RESET_B
M1
M2
M3
VREG
AGND
GND
OC_ADJ
PWM_B
RESET_A
PWM_A
6
39
7
38
8
37
FAULT
NC
NC
OTW
GVDD_B
9
36
10
35
11
34
12
33
13
32
14
31
15
30
16
29
17
28
18
27
19
26
20
25
21
24
22
23
GVDD_C
BST_C
NC
PVDD_C
PVDD_C
OUT_C
GND_C
GND
GND
NC
NC
BST_B
PVDD_B
OUT_B
GND_B
GND_A
OUT_A
PVDD_A
PVDD_A
NC
BST_A
GVDD_A
DRV8312: 44-pin TSSOP power pad down DDW package. This package contains a thermal pad that is located on the bottom side of
the device for dissipating heat through PCB.
Figure 5-1. DV8312 HTSSOP (DDW) (Top View)
GVDD_B
1
36
GVDD_A
OTW
2
35
BST_A
FAULT
3
34
PVDD_A
PWM_A
4
33
OUT_A
RESET_A
5
32
GND_A
PWM_B
6
31
GND_B
OC_ADJ
7
30
OUT_B
GND
8
29
PVDD_B
AGND
9
28
BST_B
VREG
10
27
NC
M3
11
26
NC
M2
12
25
GND
M1
13
24
GND
RESET_B
14
23
GND_C
RESET_C
15
22
OUT_C
PWM_C
16
21
PVDD_C
VDD
17
20
BST_C
GVDD_C
18
19
GVDD_C
DRV8332: 36-pin PSOP3 DKD package. This package contains a thick heat slug that is located on the top side of the device for
dissipating heat through heatsink.
Figure 5-2. DRV8332 HSSOP (DKD) (Top View)
Table 5-1. Pin Functions
PIN
NAME
4
DRV8312
DRV8332
I/O TYPE (1)
DESCRIPTION
AGND
12
9
P
Analog ground
BST_A
24
35
P
High side bootstrap supply (BST), external capacitor to OUT_A required
BST_B
33
28
P
High side bootstrap supply (BST), external capacitor to OUT_B required
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Table 5-1. Pin Functions (continued)
PIN
NAME
DRV8312
DRV8332
BST_C
I/O TYPE (1)
DESCRIPTION
43
20
P
High side bootstrap supply (BST), external capacitor to OUT_C required
13, 36, 37
8
P
Ground
GND_A
29
32
P
Power ground for half-bridge A
GND_B
30
31
P
Power ground for half-bridge B
GND_C
38
23
P
Power ground for half-bridge C
GVDD_A
23
36
P
Gate-drive voltage supply
GVDD_B
22
1
P
Gate-drive voltage supply
GVDD_C
1, 44
18, 19
P
Gate-drive voltage supply
M1
8
13
I
Mode selection pin
M2
9
12
I
Reserved mode selection pin. AGND connection is recommended
M3
10
11
I
Reserved mode selection pin, VREG connection is recommended
NC
3, 4, 19, 20, 25,
34, 35, 42
26, 27
-
No connection pin. Ground connection is recommended
OC_ADJ
14
7
O
Analog overcurrent programming pin, requires resistor to AGND
OTW
21
2
O
Overtemperature warning signal, open-drain, active-low. An internal pullup resistor
to VREG (3.3 V) is provided on output. Level compliance for 5-V logic can be
obtained by adding external pullup resistor to 5 V
OUT_A
28
33
O
Output, half-bridge A
OUT_B
31
30
O
Output, half-bridge B
OUT_C
39
22
O
Output, half-bridge C
PVDD_A
26, 27
34
P
Power supply input for half-bridge A requires close decoupling capacitor to ground.
PVDD_B
32
29
P
Power supply input for half-bridge B requires close decoupling capacitor to gound.
PVDD_C
40, 41
21
P
Power supply input for half-bridge C requires close decoupling capacitor to ground.
PWM_A
17
4
I
Input signal for half-bridge A
PWM_B
15
6
I
Input signal for half-bridge B
PWM_C
5
16
I
Input signal for half-bridge C
RESET_A
16
5
I
Reset signal for half-bridge A, active-low
RESET_B
7
14
I
Reset signal for half-bridge B, active-low
RESET_C
6
15
I
Reset signal for half-bridge C, active-low
FAULT
18
3
O
Fault signal, open-drain, active-low. An internal pullup resistor to VREG (3.3 V)
is provided on output. Level compliance for 5-V logic can be obtained by adding
external pullup resistor to 5 V
VDD
2
17
P
Power supply for digital voltage regulator requires capacitor to ground for
decoupling.
VREG
11
10
P
Digital regulator supply filter pin requires 0.1-μF capacitor to AGND.
THERMAL PAD
--
N/A
T
Solder the exposed thermal pad at the bottom of the DRV8312DDW package to
the landing pad on the PCB. Connect the landing pad through vias to large ground
plate for better thermal dissipation.
N/A
--
T
Mount heatsink with thermal interface to the heat slug on the top of the
DRV8332DKD package to improve thermal dissipation.
GND
HEAT SLUG
(1)
I = input, O = output, P = power, T = thermal
Mode Selection Pins
MODE PINS
DESCRIPTION
M3
M2
M1
1
0
0
Three-phase or three half bridges with cycle-by-cycle current limit
1
0
1
Three-phase or three half bridges with OC latching shutdown (no cycle-by-cycle current limit)
0
x
x
Reserved
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range unless otherwise noted(1)
MIN
MAX
UNIT
VDD to GND
–0.3
13.2
V
GVDD_X to GND
–0.3
13.2
V
PVDD_X to GND_X (2)
–0.3
70
V
(2)
–0.3
70
V
BST_X to GND_X (2)
–0.3
80
V
Transient peak output current (per pin), pulse width limited by internal overcurrent protection circuit
16
A
Transient peak output current for latch shut down (per pin)
20
A
OUT_X to GND_X
VREG to AGND
–0.3
4.2
V
GND_X to GND
–0.3
0.3
V
GND to AGND
–0.3
0.3
V
PWM_X, RESET_X to GND
–0.3
VREG + 0.5
V
OC_ADJ, M1, M2, M3 to AGND
–0.3
4.2
V
FAULT, OTW to GND
–0.3
7
V
9
mA
Continuous sink current ( FAULT, OTW)
Operating junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–55
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 6.3 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
These are the maximum allowed voltages for transient spikes. Absolute maximum DC voltages are lower.
6.2 ESD Ratings
V(ESD)
(1)
Electrostatic discharge
Charged Device Model (HBM) ESD Stress Voltage
(1)
VALUE
UNIT
±1500
V
Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safe
manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
6
MIN
NOM
MAX
UNIT
0
50
52.5
V
Supply for logic regulators and gate-drive circuitry
10.8
12
13.2
V
VDD
Digital regulator supply voltage
10.8
12
13.2
V
IO_PULSE
Pulsed peak current per output pin (could be limited by thermal)
15
A
IO
Continuous current per output pin (DRV8332)
FSW
PWM switching frequency
ROCP_CBC
OC programming resistor range in cycle-by-cycle current limit modes
ROCP_OCL
OC programming resistor range in OC latching shutdown modes
CBST
Bootstrap capacitor range
33
tON_MIN
Minimum PWM pulse duration, low side, for charging the Bootstrap capacitor
TA
Operating ambient temperature
PVDD_X
Half bridge X (A, B, or C) DC supply voltage
GVDD_X
8
kHz
22
200
kΩ
19
200
kΩ
220
nF
85
°C
50
–40
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A
500
ns
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6.4 Thermal Information
THERMAL METRIC
DRV8312
DRV8332
DDW
PACKAGE
DKD
PACKAGE
44 PINS
36 PINS
RθJA
Junction-to-ambient thermal resistance
24.5
13.3
(with heat sink)
RθJC(top)
Junction-to-case (top) thermal resistance
7.8
0.4
RθJB
Junction-to-board thermal resistance
5.5
13.3
ψJT
Junction-to-top characterization parameter
0.1
0.4
ψJB
Junction-to-board characterization parameter
5.4
13.3
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.2
N/A
UNIT
°C/W
6.5 Dissipation Ratings
PARAMETER
DRV8312
DRV8332
1.1 °C/W
0.9 °C/W
RθJA, junction-to-ambient thermal resistance
25 °C/W
This device is not intended to be used
without a heatsink. Therefore, RθJA is not
specified. See the Thermal Information
section.
Exposed power pad / heat slug area
34 mm2
80 mm2
RθJC, junction-to-case (power pad / heat slug)
thermal resistance
6.6 Power Deratings (DRV8312)
(1)PACKAGE
TA = 25°C
POWER
RATING
DERATING
FACTOR
ABOVE TA =
25°C
TA = 70°C POWER
RATING
TA = 85°C POWER
RATING
TA = 125°C POWER
RATING
44-PIN TSSOP (DDW)
5.0 W
40.0 mW/°C
3.2 W
2.6 W
1.0 W
(1)
Based on EVM board layout
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6.7 Electrical Characteristics
TA = 25°C, PVDD = 50 V, GVDD = VDD = 12 V, fSw = 400 kHz, unless otherwise noted. All performance is in accordance with
recommended operating conditions unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2.95
3.3
3.65
9
12
mA
2.5
mA
1
mA
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
VREG
Voltage regulator, only used as a reference node
VDD = 12 V
Idle, reset mode
V
IVDD
VDD supply current
IGVDD_X
Gate supply current per half-bridge
IPVDD_X
Half-bridge X (A, B, or C) idle current
Reset mode
0.7
MOSFET drain-to-source resistance, low side (LS)
TJ = 25°C, GVDD = 12 V
80
mΩ
MOSFET drain-to-source resistance, high side (HS)
TJ = 25°C, GVDD = 12 V
80
mΩ
VF
Diode forward voltage drop
TJ = 25°C - 125°C, IO = 5 A
1
V
tR
Output rise time
Resistive load, IO = 5 A
14
ns
tF
Output fall time
Resistive load, IO = 5 A
14
ns
tPD_ON
Propagation delay when FET is on
Resistive load, IO = 5 A
38
ns
tPD_OFF
Propagation delay when FET is off
Resistive load, IO = 5 A
38
ns
tDT
Dead time between HS and LS FETs
Resistive load, IO = 5 A
5.5
ns
8.5
V
Operating, 50% duty cycle
10.5
Reset mode
1.7
Operating, 50% duty cycle
8
OUTPUT STAGE
RDS(on)
I/O PROTECTION
Vuvp,G
Gate supply voltage GVDD_X undervoltage
protection threshold
Vuvp,hyst (1)
Hysteresis for gate supply undervoltage event
OTW(1)
Overtemperature warning
OTWhyst (1)
Hysteresis temperature to reset OTW event
OTSD(1)
Overtemperature shut down
OTEOTWdifferential (1)
0.8
115
125
V
135
°C
25
°C
150
°C
OTE-OTW overtemperature detect temperature
difference
25
°C
OTSDHYST (1)
Hysteresis temperature for FAULT to be released
following an OTSD event
25
°C
IOC
Overcurrent limit protection
Resistor—programmable, nominal, ROCP = 27 kΩ
9.7
A
Overcurrent response time
Time from application of short condition to Hi-Z of
affected FET(s)
250
ns
IOCT
STATIC DIGITAL SPECIFICATIONS
VIH
High-level input voltage
PWM_A, PWM_B, PWM_C, M1, M2, M3
2
3.6
V
VIH
High-level input voltage
RESET_A, RESET_B, RESET_C
2
3.6
V
VIL
Low-level input voltage
PWM_A, PWM_B, PWM_C, M1, M2, M3,
RESET_A, RESET_B, RESET_C
0.8
V
llkg
Input leakage current
100
μA
kΩ
-100
OTW / FAULT
RINT_PU
Internal pullup resistance, OTW to VREG, FAULT to
VREG
VOH
High-level output voltage
VOL
Low-level output voltage
(1)
8
Internal pullup resistor only
External pullup of 4.7 kΩ to 5 V
IO = 4 mA
20
26
35
2.95
3.3
3.65
4.5
5
0.2
0.4
V
V
Specified by design
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6.8 Typical Characteristics
Normalized RDS(on) / (RDS(on) at 12 V)
100
90
Efficiency (%)
80
70
60
50
40
30
20
10
0
0
50 100 150 200 250 300 350 400 450 500
1.10
1.08
1.06
1.04
1.02
1.00
0.98
0.96
8.0
8.5
9.0
9.5
Switching Frequency (kHz)
10.0 10.5
11.0
11.5
12
Gate Drive (V)
Full Bridge Load: 5
A; PVDD = 50 V; Tc
= 75°C
TJ = 25°C
Figure 6-2. Normalized RDS(on) vs Gate Drive
1.6
6
1.4
5
4
1.2
Current (A)
Normalized RDS(on) / (RDS(on) at 25oC)
Figure 6-1. Efficiency vs Switching Frequency
(DRV8332)
1.0
0.8
2
1
0.6
0.4
–40 –20
3
0
0
20
40
60
80
–1
100 120 140
0
0.2
0.4
o
0.6
0.8
1
1.2
Voltage (V)
TJ – Junction Temperature – C
TJ = 25°C
GVDD = 12 V
Figure 6-4. Drain To Source Diode Forward
On Characteristics
Figure 6-3. Normalized RDS(on) vs Junction
Temperature
100
Output Duty Cycle (%)
90
80
70
60
50
40
30
20
10
0
0
10
20
30
40
50
60
70
80
90 100
Input Duty Cycle (%)
FS = 500 kHz; TC = 25°C
Figure 6-5. Output Duty Cycle vs Input Duty Cycle
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7 Detailed Description
7.1 Overview
The DRV83x2 devices have three high-current half-H bridge outputs that are controlled by the six inputs PWM_x
and RESET_x. When RESET_A is low, OUT_A becomes high-impedance, allowing current to flow through the
internal body diodes of the high-side and low-side FETs. When RESET_A is high and PWM_A is low, OUT_A
is driven low with its low-side FET enabled. When RESET_A is high and PWM_A is high, OUT_A is driven high
with its high-side FET enabled. Likewise is true for B and C.
7.2 Functional Block Diagram
VDD
4
Undervoltage
Protection
OTW
Internal Pullup
Resistors to VREG
FAULT
M1
Protection
and
I/O Logic
M2
M3
4
VREG
VREG
Power
On
Reset
AGND
Temp.
Sense
GND
RESET_A
Overload
Protection
RESET_B
Isense
OC_ADJ
RESET_C
GVDD_C
BST_C
PVDD_C
PWM_C
PWM
Rcv.
Ctrl.
Timing
Gate
Drive
OUT_C
GND_C
GVDD_B
BST_B
PVDD_B
PWM_B
PWM
Rcv.
Ctrl.
Timing
Gate
Drive
OUT_B
GND_B
GVDD_A
BST_A
PVDD_A
PWM_A
PWM
Rcv.
Ctrl.
Timing
Gate
Drive
OUT_A
GND_A
7.3 Feature Description
7.3.1 Error Reporting
The FAULT and OTW pins are both active-low, open-drain outputs. Their function is for protection-mode
signaling to a PWM controller or other system-control device.
10
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Any fault resulting in device shutdown, such as overtemperatue shut down, overcurrent shut-down, or
undervoltage protection, is signaled by the FAULT pin going low. Likewise, OTW goes low when the device
junction temperature exceeds 125°C (see Table 7-1).
Table 7-1. Protection Mode Signal Descriptions
FAULT
OTW
DESCRIPTION
0
0
Overtemperature warning and (overtemperature shut down or overcurrent shut down or undervoltage
protection) occurred
0
1
Overcurrent shut-down or GVDD undervoltage protection occurred
1
0
Overtemperature warning
1
1
Device under normal operation
TI recommends monitoring the OTW signal using the system microcontroller and responding to an OTW
signal by reducing the load current to prevent further heating of the device resulting in device overtemperature
shutdown (OTSD).
To reduce external component count, an internal pullup resistor to internal VREG (3.3 V) is provided on both
FAULT and OTW outputs. Level compliance for 5-V logic can be obtained by adding external pullup resistors to
5 V (see the Electrical Characteristics section of this data sheet for further specifications).
7.3.2 Device Protection System
The DRV83x2 contain advanced protection circuits carefully designed to facilitate system integration and ease of
use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions such as
short circuits, overcurrent, overtemperature, and undervoltage. The DRV83x2 respond to a fault by immediately
setting the half bridge outputs in a high-impedance (Hi-Z) state and asserting the FAULT pin low. In situations
other than overcurrent or overtemperature, the device automatically recovers when the fault condition has been
removed or the gate supply voltage has increased. For highest possible reliability, reset the device externally
no sooner than 1 second after the shutdown when recovering from an overcurrent shut down (OCSD) or OTSD
fault.
7.3.2.1 Bootstrap Capacitor Undervoltage Protection
When the device runs at a low switching frequency (for example, less than 10 kHz with a 100-nF bootstrap
capacitor), the bootstrap capacitor voltage might not be able to maintain a proper voltage level for the high-side
gate driver. A bootstrap capacitor undervoltage protection circuit (BST_UVP) will prevent potential failure of
the high-side MOSFET. When the voltage on the bootstrap capacitors is less than the required value for
safe operation, the DRV83x2 will initiate bootstrap capacitor recharge sequences (turn off high side FET for
a short period) until the bootstrap capacitors are properly charged for safe operation. This function may also
be activated when PWM duty cycle is too high (for example, less than 20 ns off time at 10 kHz). Note that
bootstrap capacitor might not be able to be charged if no load or extremely light load is presented at output
during BST_UVP operation, so it is recommended to turn on the low side FET for at least 50 ns for each PWM
cycle to avoid BST_UVP operation if possible.
For applications with lower than 10 kHz switching frequency and not to trigger BST_UVP protection, a larger
bootstrap capacitor can be used (for example, 1-uF capacitor for 800-Hz operation). When using a bootstrap
capacitor larger than 220 nF, it is recommended to add 5 ohm resistors between 12V GVDD power supply and
GVDD_X pins to limit the inrush current on the internal bootstrap diodes.
7.3.2.1.1 Overcurrent (OC) Protection
The DRV83x2 have independent, fast-reacting current detectors with programmable trip threshold (OC
threshold) on all high-side and low-side power-stage FETs. There are two settings for OC protection through
mode selection pins: cycle-by-cycle (CBC) current limiting mode and OC latching (OCL) shut down mode.
In CBC current limiting mode, the detector outputs are monitored by two protection systems. The first protection
system controls the power stage in order to prevent the output current from further increasing, that is, it performs
a CBC current-limiting function rather than prematurely shutting down the device. This feature can effectively
limit the inrush current during motor start-up or transient without damaging the device. During short to power and
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short to ground conditions, since the current limit circuitry might not be able to control the current to a proper
level, a second protection system triggers a latching shutdown, resulting in the related half bridge being set in
the high-impedance (Hi-Z) state. Current limiting and overcurrent protection are independent for half-bridges A,
B, and C, respectively.
Figure 7-1 illustrates cycle-by-cycle operation with high side OC event and Figure 7-2 shows cycle-by-cycle
operation with low side OC. Dashed lines are the operation waveforms when no CBC event is triggered and solid
lines show the waveforms when CBC event is triggered. In CBC current limiting mode, when low side FET OC is
detected, the device will turn off the affected low side FET and keep the high side FET at the same half bridge off
until next PWM cycle; when high side FET OC is detected, the device will turn off the affected high side FET and
turn on the low side FET at the half bridge until next PWM cycle.
It is important to note that if the input to a half bridge is held to a constant value when an over current event
occurs in CBC, then the associated half bridge will be in a HI-Z state upon the over current event ending. Cycling
IN_X will allow OUT_X to resume normal operation.
In OC latching shut down mode, the CBC current limit and error recovery circuits are disabled and an
overcurrent condition will cause the device to shutdown. After shutdown, RESET_A, RESET_B, and RESET_C
must be asserted to restore normal operation after the overcurrent condition is removed.
For added flexibility, the OC threshold is programmable using a single external resistor connected between the
OC_ADJ pin and AGND pin. See Table 7-2 for information on the correlation between programming-resistor
value and the OC threshold.
The values in Table 7-2 show typical OC thresholds for a given resistor. Assuming a fixed resistance on
the OC_ADJ pin across multiple devices, a 20% device-to-device variation in OC threshold measurements is
possible. Therefore, this feature is designed for system protection and not for precise current control.
12
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Table 7-2. Programming-Resistor Values and OC
Threshold
(1)
OC-ADJUST RESISTOR
VALUES (kΩ)
MAXIMUM CURRENT BEFORE
OC OCCURS (A)
19(1)
13.2
22
11.6
24
10.7
27
9.7
30
8.8
36
7.4
Recommended to use in OC Latching Mode Only
It should be noted that a properly functioning overcurrent detector assumes the presence of a proper inductor
or power ferrite bead at the power-stage output. Short-circuit protection is not ensured with a direct short at the
output pins of the power stage.
7.3.2.2 Overtemperature Protection
The DRV83x2 have a two-level temperature-protection system that asserts an active-low warning signal ( OTW)
when the device junction temperature exceeds 125°C (nominal) and, if the device junction temperature exceeds
150°C (nominal), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the
high-impedance (Hi-Z) state and FAULT being asserted low. OTSD is latched in this case and RESET_A,
RESET_B, and RESET_C must be asserted low to clear the latch.
7.3.2.3 Undervoltage Protection (UVP) and Power-On Reset (POR)
The UVP and POR circuits of the DRV83x2 fully protect the device in any power-up / down and brownout
situation. While powering up, the POR circuit resets the overcurrent circuit and ensures that all circuits are fully
operational when the GVDD_X and VDD supply voltages reach 9.8 V (typical). Although GVDD_X and VDD are
independently monitored, a supply voltage drop below the UVP threshold on any VDD or GVDD_X pin results in
all half-bridge outputs immediately being set in the high-impedance (Hi-Z) state and FAULT being asserted low.
The device automatically resumes operation when all supply voltage on the bootstrap capacitors have increased
above the UVP threshold.
7.3.2.4 Device Reset
Three reset pins are provided for independent control of half-bridges A, B, and C. When RESET_X is asserted
low, two power-stage FETs in half-bridges X are forced into a high-impedance (Hi-Z) state.
A rising-edge transition on reset input allows the device to resume operation after a shut-down fault. That is,
when half-bridge X has OC shutdown in CBC mode, a low to high transition of RESET_X pin will clear the fault
and FAULT pin. When an OTSD or OC shutdown in Latching mode occurs, all three RESET_A, RESET_B, and
RESET_C need to have a low to high transition to clear the fault and reset FAULT signal.
7.4 Device Functional Modes
7.4.1 Different Operational Modes
The DRV83x2 support two different modes of operation:
•
•
Three-phase (3PH) or three half bridges (HB) with CBC current limit
Three-phase or three half bridges with OC latching shutdown (no CBC current limit)
Because each half bridge has independent supply and ground pins, a shunt sensing resistor can be inserted
between PVDD to PVDD_X or GND_X to GND (ground plane). A high side shunt resistor between PVDD and
PVDD_X is recommended for differential current sensing because a high bias voltage on the low side sensing
could affect device operation. If low side sensing has to be used, a shunt resistor value of 10 mΩ or less or
sense voltage 100 mV or less is recommended.
Figure 8-1 and Figure 8-4 show the three-phase application examples, and Figure 8-5 shows how to connect to
DRV83x2 with some simple logic to accommodate conventional 6 PWM inputs control.
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We recommend using a complementary control scheme for switching phases to prevent circulated energy
flowing inside the phases and to make current limiting feature active all the time. Complementary control scheme
also forces the current flowing through sense resistors all the time to have a better current sensing and control of
the system.
Figure 8-6 shows six steps trapezoidal scheme with hall sensor control and Figure 8-7 shows six steps
trapezoidal scheme with sensorless control. The hall sensor sequence in real application might be different
than the one we showed in Figure 8-6 depending on the motor used. Please check motor manufacture datasheet
for the right sequence in applications. In six step trapezoidal complementary control scheme, a half bridge with
larger than 50% duty cycle will have a positive current and a half bridge with less than 50% duty cycle will have
a negative current. For normal operation, changing PWM duty cycle from 50% to 100% will adjust the current
from 0 to maximum value with six steps control. It is recommended to apply a minimum 50 ns to 100 ns PWM
pulse at each switching cycle at lower side to properly charge the bootstrap cap. The impact of minimum pulse
at low side FET is pretty small, for example, the maximum duty cycle is 99.9% with 100 ns minimum pulse on
low side. RESET_X pin can be used to get channel X into high impedance mode. If you prefer PWM switching
one channel but hold low side FET of the other channel on (and third channel in Hi-Z) for 2-quadrant mode, OT
latching shutdown mode is recommended to prevent the channel with low side FET on stuck in Hi-Z during OC
event in CBC mode.
The DRV83x2 can also be used for sinusoidal waveform control and field oriented control. Please check TI
website MCU motor control library for control algorithms.
CBC with High Side OC
During T_OC Period
PVDD
Current Limit
Load
Current
PWM_HS
PWM_HS
Load
PWM_LS
PWM_LS
GND_X
T_HS T_OC T_LS
Dashed line: normal operation; solid line: CBC event
Figure 7-1. Cycle-by-Cycle Operation With High-Side OC
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During T_OC Period
CBC with Low Side OC
PVDD
Current Limit
Load
Current
PWM_HS
PWM_HS
Load
PWM_LS
PWM_LS
T_LS T_OC T_HS
GND_X
Dashed line: normal operation; solid line: CBC event
Figure 7-2. Cycle-by-Cycle Operation With Low-Side OC
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
The DRV83x2 devices are typically used to drive 3-phase brushless DC motors.
8.2 Typical Applications
8.2.1 Three-Phase Operation
GVDD
PVDD
1 mF
DRV8332
330 mF
3.3
1000 mF
GVDD_B
1mF
GVDD_A
10 nF
BST_A
OTW
100 nF
PVDD_A
FAULT
PWM_A
OUT_A
RESET_A
GND_A
Loc
Rsense_A
100nF
M
Rsense_B
Controller
(MSP430
C2000 or
Stellaris MCU)
PWM_B
GND_B
Loc
Roc_adj
OUT_B
OC_ADJ
1
GND
PVDD_B
AGND
BST_B
VREG
NC
M3
NC
100 nF
100nF
100 nF
M2
GND
M1
GND
Rsense_x £ 10 mW
or
Vsense < 100 mV
Rsense_C
RESET_B
GND_C
RESET_C
OUT_C
PVDD_C
PWM_C
GVDD
BST_C
VDD
47 mF
Loc
100 nF
100nF
1 mF
GVDD_C
PVDD
GVDD_C
1mF
Figure 8-1. DRV8332 Application Diagram for Three-Phase Operation Schematic
8.2.1.1 Design Requirements
This section describes the design considerations.
Table 8-1. Design Parameters
DESIGN PARAMETER
Motor voltage
16
REFERENCE
EXAMPLE VALUE
PVDD_x
24V
Motor current (peak and RMS)
IPVDD
6A peak, 3A RMS
Overcurrent threshold
OCTH
OC_ADJ = 27kΩ, 9.7A
Overcurrent behavior
OC
M1 = 0, cycle-by-cycle
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8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Motor Voltage
BLDC motors are typically rated for a certain voltage. Higher voltages generally have the advantage of causing
current to change faster through the inductive windings, which allows for higher RPMs. Lower voltages allow for
more accurate control of phase currents.
8.2.1.2.2 Current Requirement of 12 V Power Supply
The DRV83x2 require a 12-V power supply for GVDD and VDD pins. The total supply current is pretty low at
room temp (less than 50 mA), but the current could increase significantly when the device temperature goes too
high (for example, above 125°C), especially at heavy load conditions due to substrate current collection by 12-V
guard rings. So it is recommended to design the 12-V power supply with current capability at least 5-10% of your
load current and no less than 100 mA to assure the device performance across all temperature range.
8.2.1.2.3 Voltage of Decoupling Capacitor
The voltage of the decoupling capacitors should be selected in accordance with good design practices.
Temperature, ripple current, and voltage overshoot must be considered. The high frequency decoupling
capacitor should use ceramic capacitor with X5R or better rating. For a 50-V application, a minimum voltage
rating of 63 V is recommended.
8.2.1.2.4 Overcurrent Threshold
When choosing the resistor value for OC_ADJ, consider the peak current allowed under normal system
behavior, the resistor tolerance, and the fact that the Table 7-2 currents have a ±10% tolerance. For example,
if 6A is the highest system current allowed across all normal behavior, a 27kΩ OC_ADJ resistor with 10%
tolerance is a reasonable choice, as it would set the OCTH to approximately 8A–12A.
8.2.1.2.5 Sense Resistor
For optimal performance, it is important for the sense resistor to be:
• Surface-mount
• Low inductance
• Rated for high enough power
• Placed closely to the motor driver
The power dissipated by the sense resistor equals IRMS 2 x R. For example, if peak motor current is 3A, RMS
motor current is 2 A, and a 0.05Ω sense resistor is used, the resistor will dissipate 2A2 x 0.05Ω = 0.2W. The
power quickly increases with higher current levels.
Resistors typically have a rated power within some ambient temperature range, along with a de-rated power
curve for high ambient temperatures. When a PCB is shared with other components generating heat, margin
should be added. It is always best to measure the actual sense resistor temperature in a final system, along with
the power MOSFETs, as those are often the hottest components.
Because power resistors are larger and more expensive than standard resistors, it is common practice to use
multiple standard resistors in parallel, between the sense node and ground. This distributes the current and heat
dissipation.
8.2.1.2.6 Output Inductor Selection
For normal operation, inductance in motor (assume larger than 10 µH) is sufficient to provide low di/dt output
(for example, for EMI) and proper protection during overload condition (CBC current limiting feature). So no
additional output inductors are needed during normal operation.
However during a short condition, the motor (or other load) could be shorted, so the load inductance might not
present in the system anymore; the current in short condition can reach such a high level that may exceed
the abs max current rating due to extremely low impendence in the short circuit path and high di/dt before oc
detection circuit kicks in. So a ferrite bead or inductor is recommended to use the short-circuit protection feature
in DRV83x2. With an external inductor or ferrite bead, the current will rise at a much slower rate and reach a
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lower current level before oc protection starts. The device will then either operate CBC current limit or OC shut
down automatically (when current is well above the current limit threshold) to protect the system.
For a system that has limited space, a power ferrite bead can be used instead of an inductor. The current rating
of ferrite bead has to be higher than the RMS current of the system at normal operation. A ferrite bead designed
for very high frequency is NOT recommended. A minimum impedance of 10 Ω or higher is recommended at 10
MHz or lower frequency to effectively limit the current rising rate during short circuit condition.
The TDK MPZ2012S300A and MPZ2012S101A (with size of 0805 inch type) have been tested in our system to
meet short circuit conditions in the DRV8312. But other ferrite beads that have similar frequency characteristics
can be used as well.
For higher power applications, such as in the DRV8332, there might be limited options to select suitable ferrite
bead with high current rating. If an adequate ferrite bead cannot be found, an inductor can be used.
The inductance can be calculated as:
Loc _ min =
PVDD × Toc _ delay
Ipeak - Iave
(1)
where
•
•
Toc_delay = 250 ns
Ipeak = 15 A (below abs max rating).
Because an inductor usually saturates quickly after reaching its current rating, it is recommended to use an
inductor with a doubled value or an inductor with a current rating well above the operating condition.
8.2.1.3 Application Curves
Figure 8-2. Three-Phase BLDC Commutation With
Current Shown for 1 Phase
18
Figure 8-3. Input and Output Functionality
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8.2.2 DRV8312 Application Diagram for Three-Phase Operation
1mF
DRV8312
GVDD
GVDD_B
330 mF
GVDD_A
PVDD
100 nF
1mF
OTW
BST_A
3.3
NC
10 nF
1000 mF
NC
NC
PVDD_A
FAULT
PVDD_A
PWM_A
RESET_A
Controller
(MSP430
C2000 or
Stellaris MCU)
Loc
OUT_A
GND_A
PWM_B
GND_B
OC_ADJ
OUT_B
Rsense_A
100nF
M
Rsense_B
Loc
Roc_adj
1
GND
PVDD_B
AGND
BST_B
VREG
NC
M3
NC
100 nF
100nF
100 nF
M2
GND
M1
GND
Rsense_x £ 10 mW
or
Vsense < 100 mV
Rsense_C
GVDD
47 mF
1mF
RESET_B
GND_C
RESET_C
OUT_C
PWM_C
PVDD_C
NC
PVDD_C
NC
NC
VDD
GVDD_C
Loc
100nF
PVDD
BST_C
GVDD_C
100 nF
1mF
Figure 8-4. DRV8312 Application Diagram for Three-Phase Operation Schematic
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8.2.3 Control Signal Logic With Conventional 6 PWM Input Scheme
PVDD
Controller
PWM_AH
PWM_BH
PWM_CH
PWM_A
PWM_B
PWM_C
MOTOR
OUT_A
OUT_B
RESET_A
OUT_C
PWM_AL
RESET_B
PWM_BL
RESET_C
PWM_CL
GND_A
GND_B
GND_C
Figure 8-5. Control Signal Logic With Conventional 6 PWM Input Schematic
20
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8.2.4 Hall Sensor Control With 6 Steps Trapezoidal Scheme
S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
Hall Sensor H1
Hall Sensor H2
Hall Sensor H3
Phase Current A
Phase Current B
Phase Current C
PWM_A
PWM_B
PWM_C
RESET_A
RESET_B
RESET_C
360
o
PWM= 100%
360
o
PWM=75%
Figure 8-6. Hall Sensor Control With 6 Steps Trapezoidal Scheme Schematic
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8.2.5 Sensorless Control With 6 Steps Trapezoidal Scheme
S1
Back EMF (Vab)
Back EMF (Vbc)
Back EMF (Vca)
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
0V
0V
0V
Phase A
Current and Voltage
Va
Ia
0A
0V
Phase B
Current and Voltage
Vb
Ib
0A
0V
Vc
Phase C
Current and Voltage
Ic
0A
0V
PWM_A
PWM_B
PWM_C
RESET_A
RESET_B
RESET_C
360
o
PWM= 100%
360
o
PWM= 75%
Figure 8-7. Sensorless Control With 6 Steps Trapezoidal Scheme Schematic
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9 Power Supply Recommendations
9.1 Bulk Capacitance
Having appropriate local bulk capacitance is an important factor in motor drive system design. It is generally
beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size.
The amount of local capacitance needed depends on a variety of factors, including:
• The highest current required by the motor system.
• The power supply’s capacitance and ability to source current.
• The amount of parasitic inductance between the power supply and motor system.
• The acceptable voltage ripple.
• The type of motor used (Brushed DC, Brushless DC, Stepper).
• The motor braking method.
The inductance between the power supply and motor drive system will limit the rate current can change from the
power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands
or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage
remains stable and high current can be quickly supplied.
The datasheet generally provides a recommended value, but system-level testing is required to determine the
appropriate sized bulk capacitor.
Power Supply
Parasitic Wire
Inductance
Motor Drive System
VM
+
+
±
Motor
Driver
GND
Local
Bulk Capacitor
IC Bypass
Capacitor
Figure 9-1. Example Setup of Motor Drive System With External Power Supply
The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases
when the motor transfers energy to the supply.
9.2 System Power-Up and Power-Down Sequence
9.2.1 Powering Up
The DRV83x2 do not require a power-up sequence. The outputs of the H-bridges remain in a high impedance
state until the gate-drive supply voltage GVDD_X and VDD voltage are above the undervoltage protection
(UVP) voltage threshold (see the Electrical Characteristics section of this data sheet). Although not specifically
required, holding RESET_A, RESET_B, and RESET_C in a low state while powering up the device is
recommended. This allows an internal circuit to charge the external bootstrap capacitors by enabling a weak
pulldown of the half-bridge output.
9.2.2 Powering Down
The DRV83x2 do not require a power-down sequence. The device remains fully operational as long as the
gate-drive supply (GVDD_X) voltage and VDD voltage are above the UVP voltage threshold (see the Electrical
Characteristics section of this data sheet). Although not specifically required, it is a good practice to hold
RESET_A, RESET_B and RESET_C low during power down to prevent any unknown state during this transition.
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9.3 System Design Recommendations
9.3.1 VREG Pin
The VREG pin is used for internal logic and should not be used as a voltage source for external circuitries. The
capacitor on VREG pin should be connected to AGND.
9.3.2 VDD Pin
The transient current in VDD pin could be significantly higher than average current through VDD pin. A low
resistive path to GVDD should be used. A 22-µF to 47-µF capacitor should be placed on VDD pin beside the
100-nF to 1-µF decoupling capacitor to provide a constant voltage during transient.
9.3.3 OTW Pin
OTW reporting indicates the device approaching high junction temperature. This signal can be used with MCU to
decrease system power when OTW is low in order to prevent OT shut down at a higher temperature.
No external pull up resistor or 3.3V power supply is needed for 3.3V logic. The OTW pin has an internal pullup
resistor connecting to an internal 3.3V to reduce external component count. For 5V logic, an external pull up
resistor to 5V is needed.
9.3.4 FAULT Pin
The FAULT pin reports any fault condition resulting in device shut down. No external pull up resistor or 3.3V
power supply is needed for 3.3V logic. The FAULT pin has an internal pullup resistor connecting to an internal
3.3V to reduce external component count. For 5V logic, an external pull upresistor to 5V is needed.
9.3.5 OC_ADJ Pin
For accurate control of the overcurrent protection, the OC_ADJ pin has to be connected to AGND through an OC
adjust resistor.
9.3.6 PWM_X and RESET_X Pins
It is recommanded to connect these pins to either AGND or GND when they are not used, and these pins only
support 3.3V logic.
9.3.7 Mode Select Pins
Mode select pins (M1, M2, and M3) should be connected to either VREG (for logic high) or AGND for logic low. It
is not recommended to connect mode pins to board ground if 1-Ω resistor is used between AGND and GND.
24
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10 Layout
10.1 Layout Guidelines
10.1.1 PCB Material Recommendation
•
FR-4 Glass Epoxy material with 2 oz. copper on both top and bottom layer is recommended for improved
thermal performance (better heat sinking) and less noise susceptibility (lower PCB trace inductance).
10.1.2 Ground Plane
•
•
•
•
Because of the power level of these devices, it is recommended to use a big unbroken single ground plane
for the whole system / board.
The ground plane can be easily made at bottom PCB layer.
In order to minimize the impedance and inductance of ground traces, the traces from ground pins should
keep as short and wide as possible before connected to bottom ground plane through vias.
Multiple vias are suggested to reduce the impedance of vias. Try to clear the space around the device as
much as possible especially at bottom PCB side to improve the heat spreading.
10.1.3 Decoupling Capacitor
•
High frequency decoupling capacitors (100 nF) should be placed close to PVDD_X pins and with a short
ground return path to minimize the inductance on the PCB trace.
10.1.4 AGND
•
•
•
AGND is a localized internal ground for logic signals. A 1-Ω resistor is recommended to be connected
between GND and AGND to isolate the noise from board ground to AGND.
There are other two components are connected to this local ground: 0.1-µF capacitor between VREG to
AGND and Roc_adj resistor between OC_ADJ and AGND.
Capacitor for VREG should be placed close to VREG and AGND pins and connected without vias.
10.2 Layout Example
10.2.1 Current Shunt Resistor
•
If current shunt resistor is connected between GND_X to GND or PVDD_X to PVDD, make sure there is
only one single path to connect each GND_X or PVDD_X pin to shunt resistor, and the path is short and
symmetrical on each sense path to minimize the measurement error due to additional resistance on the trace.
An example of the schematic and PCB layout of DRV8312 are shown in Figure 10-1, Figure 10-2, and Figure
10-3.
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10.2.1.1
OA1
2
R20
GND
0.0
0603
1
5
R18
+3.3V
V-
R32
4
-IN
V+
+2.5V
3
+IN
15.4K
0603
OPA365AIDBV
33 1/8W
0805
C25
C19
SOT23-DBV
C23
0.1ufd/16V
0603
R28
220pfd/50V
0603
220pfd/50V
0603
619
0603
GND
GND
OA2
2
GND
0.0
0603
5
R19
+3.3V
HTSSOP44-DDW
GND
41
2
3
C31
C32
47ufd/16V
M
1.0ufd/16V
0603
GND
C37
0.1ufd/100V
0805
0.1ufd/100V
0805
GND
OUT_C
Orange
39
Orange
2
R38
R39
10.0K
0603
499
0603
L2
1000pfd/100V
0603
GND
GND
38
OUTC
6
IS-IhbC
7
37
R50
0.01 1W
1206
36
2
RSTB
M1
STUFF OPTION
GND
C50
RSTC
IS-TOTAL
GND
8
1
C58
1000pfd/50V
0603
R41
30.1K
0603
R25
3
1
220pfd/50V
0603
30ohms/6A
0805
GND
3
220pfd/50V
0603
10.2K
0603
C36
4
5
1
10.2K
0603
PVDD
40
C26
C20
619
0603
R24
42
GND
+
15.4K
0603
R29
GND
43
1.0ufd/16V
0603
+2.5V
3
+IN
SOT23-DBV
0.1ufd/16V
0603
44
C30
V+
IS-IhbC
931
0603
R49
VOUT
C24
U1
1
GVDD
U1
R33
4
-IN
OPA365AIDBV
33 1/8W
0805
PowerPad
1
V-
C57
1000pfd/50V
0603
R40
30.1K
0603
R21
IS-TOTAL
931
0603
R48
VOUT
35
9
2
R51
34
10
3
11
R52
R53
0.01 1W
1206
0.01 1W
1206
IS-IhbA -IhbB
33
0.005 1W
1206
IS
GND
C33
0.1ufd/16V
0603
32
R36
PVDD
12
C42
C43
13
0.1ufd/100V
0805
0.1ufd/100V
0805
1.0 1/4W
0805
GND
R37
S1
14
31
15
30
OUT_B
Orange
OUT_A
Orange
28
16
17
Orange
Orange
26
1000pfd/100V
0603
GND
GND
OUTB
19
20
L4
OUTA
R44
10.0K
0603
PVDD
18
C45
C46
0.1ufd/100V
0805
0.1ufd/100V
0805
R45
499
0603
25
24
22
C34
499
0603
L3
30ohms/6A
0805
27
21
GVDD
10.0K
0603
C56
29
Orange
2
1
Orange
R43
30ohms/6A
0805
0603
47K
3
GND
GND
GND
C55
1000pfd/100V
0603
GND
23
STUFF OPTION
DRV8312DDW
OA3
HTSSOP44-DDW
1.0ufd/16V
0603
GND
2
R22
0.0
0603
GND
5
R63
33 1/8W
0805
C35
V+
R23
Product Folder Links: DRV83120.0DRV8332
0603
3
1
5
+3.3V
+2.5V
15.4K
0603
220pfd/50V
0603
R30
V-
-IN
4
619
0603
VOUT
V+
C59
1000pfd/50V
0603
220pfd/50V
0603
Copyright © 2022 Texas Instruments Incorporated
OA4
+IN
R16
30.1K
0603
3
GND
R34
OPA365AIDBV
C39
C27
C21
SOT23-DBV
2
GND
33 1/8W
0805
+IN
IS-IhbA
931
0603
R54
OPA365AIDBV
R64
R35
4
VOUT
C29
GND
0603
-IN
V-
0.1ufd/16V
0603
1.0ufd/16V
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GND
1
+3.3V
GVDD
26
ROUTED GROUND
(SHIELDED FROM GND PLANE)
ADC-Vhb2
R42
SOT23-DBV
R55
931
0603
IS-IhbB
DRV8312, DRV8332
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SLES256F – MAY 2010 – REVISED MAY 2022
C37
T3
T4
T2
C33
T1
C43
C46
T1: PVDD decoupling capacitors C37, C43, and C46 should be placed very close to PVDD_X pins and ground return path.
T2: VREG decoupling capacitor C33 should be placed very close to VREG abd AGND pins.
T3: Clear the space above and below the device as much as possible to improve the thermal spreading.
T4: Add many vias to reduce the impedance of ground path through top to bottom side. Make traces as wide as possible for ground path such as GND_X path.
Figure 10-2. Printed Circuit Board – Top Layer
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B1
B1: Do not block the heat transfer path at bottom side. Clear as much space as possible for better heat spreading.
Figure 10-3. Printed Circuit Board – Bottom Layer
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10.3 Thermal Considerations
The thermally enhanced package provided with the DRV8332 is designed to interface directly to heat sink using
a thermal interface compound in between, (that is, Ceramique from Arctic Silver, TIMTronics 413, and so on).
The heat sink then absorbs heat from the ICs and couples it to the local air. It is also a good practice to connect
the heatsink to system ground on the PCB board to reduce the ground noise.
RθJA is a system thermal resistance from junction to ambient air. As such, it is a system parameter with the
following components:
• RθJC (the thermal resistance from junction to case, or in this example the power pad or heat slug)
• Thermal grease thermal resistance
• Heat sink thermal resistance
The thermal grease thermal resistance can be calculated from the exposed power pad or heat slug area and the
thermal grease manufacturer's area thermal resistance (expressed in °C-in2/W or °C-mm2/W). The approximate
exposed heat slug size is as follows:
• DRV8332, 36-pin PSOP3 …… 0.124 in2 (80 mm2)
The thermal resistance of a thermal pad is considered higher than a thin thermal grease layer and is not
recommended. Thermal tape has an even higher thermal resistance and should not be used at all. Heat sink
thermal resistance is predicted by the heat sink vendor, modeled using a continuous flow dynamics (CFD)
model, or measured.
Thus the system RθJA = RθJC + thermal grease resistance + heat sink resistance.
See the TI application report, IC Package Thermal Metrics (SPRA953), for more thermal information.
10.3.1 Thermal Via Design Recommendation
Thermal pad of the DRV8312 is attached at bottom of device to improve the thermal capability of the device.
The thermal pad has to be soldered with a very good coverage on PCB in order to deliver the power specified in
the datasheet. The figure below shows the recommended thermal via and land pattern design for the DRV8312.
For additional information, see TI application report, PowerPad Made Easy (SLMA004) and PowerPad Layout
Guidelines (SLOA120).
Figure 10-4. DRV8312 Thermal Via Footprint
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11 Device and Documentation Support
11.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 11-1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
DRV8312
Click here
Click here
Click here
Click here
Click here
DRV8332
Click here
Click here
Click here
Click here
Click here
11.2 Trademarks
All trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.4 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
30
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
DRV8312DDW
ACTIVE
HTSSOP
DDW
44
35
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
DRV8312
DRV8312DDWR
ACTIVE
HTSSOP
DDW
44
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
DRV8312
DRV8332DKD
ACTIVE
HSSOP
DKD
36
29
RoHS & Green
NIPDAU
Level-4-260C-72 HR
-40 to 85
DRV8332
DRV8332DKDR
ACTIVE
HSSOP
DKD
36
500
RoHS & Green
NIPDAU
Level-4-260C-72 HR
-40 to 85
DRV8332
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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