DRV8328
SLVSFF3C – DECEMBER 2021 – REVISED OCTOBER 2022
DRV8328 4.5 to 60 V Three-phase BLDC Gate Driver
1 Features
3 Description
•
The DRV8328 family of devices is an integrated
gate driver for three-phase applications. The devices
provide three half-bridge gate drivers, each capable
of driving high-side and low-side N-channel power
MOSFETs. The device generates the correct gate
drive voltages using an internal charge pump and
enhances the high-side MOSFETs using a bootstrap
circuit. A trickle charge pump is included to support
100% duty cycle. The Gate Drive architecture
supports peak gate drive currents up to 1-A source
and 2-A sink. The DRV8328 can operate from a single
power supply and supports a wide input supply range
of 4.5 to 60 V.
•
•
•
•
•
•
•
•
•
•
•
2 Applications
•
•
•
•
•
•
•
•
Brushless-DC (BLDC) Motor Modules and PMSM
Cordless Garden and Power Tools, Lawnmowers
Appliances Fans and Pumps
Servo Drives
E-Bikes, E-Scooters, and E-Mobility
Cordless Vacuum Cleaners
Drones
Industrial & Logistics Robots, and RC Toys
The 6x and 3x PWM modes allow for simple
interfacing to controller circuits. The device has
integrated accurate 3.3-V LDO that can be used
to power external controller and can be used as
reference for CSA. The configuration settings for the
device are configurable through hardware (H/W) pins.
A low-power sleep mode is provided to achieve
low quiescent current by shutting down most of
the internal circuitry. Internal protection functions
are provided for undervoltage lockout, GVDD fault,
MOSFET overcurrent, MOSFET short circuit, and
overtemperature. Fault conditions are indicated on
nFAULT pin.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
DRV8328ARUY
WQFN (28)
4.00 mm × 4.00 mm
DRV8328BRUY
WQFN (28)
4.00 mm × 4.00 mm
DRV8328CRUY
WQFN (28)
4.00 mm × 4.00 mm
DRV8328DRUY
WQFN (28)
4.00 mm × 4.00 mm
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
LDO out
4.5- to 60-V (65-V abs max)
3.3V up to 80mA
6x / 3x PWM
DRV8328
PWM input
nSLEEP
Charge Pump
HW
Bootstrap
architecture
MCU
nFAULT
LDO Regulator
A
Gate Drive
N-Channel
MOSFETs
•
•
•
3 Phase Pre-Driver
•
65-V Three Phase Half-Bridge Gate Driver
– Drives 3 High-Side and 3 Low-Side N-Channel
MOSFETs (NMOS)
– 4.5 to 60-V Operating Voltage Range
– Supports 100% PWM Duty Cycle with Trickle
Charge pump
Bootstrap based Gate Driver Architecture
– 1000-mA Maximum Peak Source Current
– 2000-mA Maximum Peak Sink Current
Hardware interface provides simple configuration
Ultra-low power sleep mode 6.3-V ceramic capacitor between
the AVDD and GND pins. This regulator can source up to 80 mA externally. TI
PWR-O
recommends a capacitor voltage rating at least twice the normal operating voltage of
the pin.
AVDD
-
19
BSTA
5
5
O
Bootstrap output pin. Connect capacitor between BSTA and SHA
BSTB
9
9
O
Bootstrap output pin. Connect capacitor between BSTB and SHB
BSTC
13
13
O
Bootstrap output pin. Connect capacitor between BSTC and SHC
CPH
3
3
PWR
CPL
2
2
PWR
DT
27
-
I
Gate drive deadtime setting. Connect a resistor of value between 10 kΩ to 390 kΩ
between DT and GND to adjust deadtime between 100 ns to 2000 ns. If pin is left floating
or connected to GND fixed value of 55 ns deadtime is inserted.
DRVOFF
-
18
I
Independent driver shutdown path. Pulling DRVOFF high turns off all external MOSFETs
by putting the gate drivers into the pull-down state. This signal bypasses and overrides
the digital core of the DRV8328.
GHA
7
7
O
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
Charge pump switching node. Connect a X5R or X7R, PVDD-rated ceramic capacitor
between the CPH and CPL pins. TI recommends a capacitor voltage rating at least twice
the normal operating voltage of the pin.
GHB
11
11
O
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHC
15
15
O
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GLA
8
8
O
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLB
12
12
O
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLC
16
16
O
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GND
28
28
PWR
Device ground.
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SLVSFF3C – DECEMBER 2021 – REVISED OCTOBER 2022
Table 6-1. Pin Functions—28-Pin DRV8328 Devices (continued)
PIN
NO.
TYPE
NAME
DRV8328A
DRV8328B
DRV8328C
DRV8328D
GVDD
4
4
INHA
20
INHB
19
INHC
18
INLA
23
INLB
22
INLC
21
LSS
17
nFAULT
24
nSLEEP
25
DESCRIPTION
Gate driver power supply output. Connect a X5R or X7R, 30-V rated ceramic ≥ 10-uF
PWR-O local capacitance between the GVDD and GND pins. TI recommends a capacitor value of
>10x CBSTx and voltage rating at least twice the normal operating voltage of the pin.
22
I
High-side gate driver control input. This pin controls the output of the high-side gate
driver.
I
High-side gate driver control input. This pin controls the output of the high-side gate
driver.
I
High-side gate driver control input. This pin controls the output of the high-side gate
driver.
25
I
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
24
I
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
23
I
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
PWR
Low side source pin, connect all sources of the external low-side MOSFETs here. This pin
is the sink path for the low-side gate driver.
21
20
17
27
OD
26
I
Fault indicator output. This pin is pulled logic low during a fault condition and requires an
external pull-up resistor to 3.3V to 5.0V.
Sleep mode entry pin. When this pin is pulled logic low the device goes to a low-power
sleep mode. An 1 to 1.2-µs low pulse can be used to reset fault conditions without
entering sleep mode .
Gate driver power supply input. Connect to the bridge power supply. Connect a X5R
or X7R, 0.1-µF, >2x PVDD-rated ceramic and >10-uF local capacitance between the
PVDD and GND pins. TI recommends a capacitor voltage rating at least twice the normal
operating voltage of the pin.
PVDD
1
1
PWR
SHA
6
6
I/O
High-side source pin. Connect to the high-side power MOSFET source. This pin is an
input for the VDS monitor and the output for the high-side gate driver sink.
SHB
10
10
I/O
High-side source pin. Connect to the high-side power MOSFET source. This pin is an
input for the VDS monitor and the output for the high-side gate driver sink.
SHC
14
14
I/O
High-side source pin. Connect to the high-side power MOSFET source. This pin is an
input for the VDS monitor and the output for the high-side gate driver sink.
VDSLVL
26
-
Thermal Pad
I
PWR
VDS monitor trip point setting.
Must be connected to GND
PWR = power, I = input, O = output, NC = no connection, OD = open-drain output
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SLVSFF3C – DECEMBER 2021 – REVISED OCTOBER 2022
7 Specification
7.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Power supply pin voltage
PVDD
-0.3
65
V
Bootstrap pin voltage
BSTx
-0.3
80
V
Bootstrap pin voltage
BSTx with respect to SHx
-0.3
20
V
Bootstrap pin voltage
BSTx with respect to GHx
-0.3
20
V
Charge pump pin voltage
CPL, CPH
-0.3
VGVDD
V
Gate driver regulator pin voltage
GVDD
-0.3
20
V
Analog regulator pin voltage
AVDD
-0.3
4
V
Logic pin voltage (nSLEEP)
nSLEEP
-0.3
65
V
Logic pin voltage
DRVOFF, DT, INHx, INLx, nFAULT,
VDSLVL
-0.3
6
V
High-side gate drive pin voltage
GHx
-8
80
V
Transient 500-ns high-side gate drive pin voltage
GHx
-10
80
V
High-side gate drive pin voltage
GHx with respect to SHx
-0.3
20
V
High-side source pin voltage
SHx
-8
70
V
Transient 500-ns high-side source pin voltage
SHx
-10
72
V
Low-side gate drive pin voltage
GLx with respect to LSS
-0.3
20
V
GLx with respect to LSS
-1
Transient 500-ns low-side gate drive pin
voltage(2)
Low-side gate drive pin voltage
GLx with respect to GVDD
Transient 500-ns low-side gate drive pin voltage
GLx with respect to GVDD
Low-side source sense pin voltage
LSS
Transient 500-ns low-side source sense pin voltage
LSS
-1
20
V
0.3
V
1
V
1
V
-10
8
V
Internally
Limited
Internally
Limited
A
-0.3
5.5
V
-1
1
V
Gate drive current
GHx, GLx
Current sense amplifer reference input pin voltage
CSAREF
Shunt amplifier input pin voltage
SN, SP
Transient 500-ns shunt amplifier input pin voltage
SN, SP
-10
8
V
Shunt amplifier output pin voltage
SO
-0.3 VCSAREF + 0.3
V
Junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–65
150
°C
(1)
(2)
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime
Supports upto 5A for 500 nS when GLx-LSS is negative
7.2 ESD Ratings Comm
VALUE
V(ESD)
(1)
(2)
6
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
±750
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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SLVSFF3C – DECEMBER 2021 – REVISED OCTOBER 2022
7.3 Recommended Operating Conditions
over operating temperature range (unless otherwise noted)
MIN
VPVDD
Power supply voltage
VPVDD_RAMP
Power supply voltage ramp rate at power
PVDD
up
VPVDD_RAMP
Power supply voltage ramp rate during
operation
PVDD
VBST
Bootstrap pin voltage with respect to
SHx
nSLEEP = High, INHx is switching
IAVDD (1)
Regulator external load current
ITRICKLE
Trickle charge pump external load
current
VIN
Logic input voltage
DRVOFF, INHx, INLx, nSLEEP
VIN
Logic input voltage
DT, VDSLVL
fPWM
PWM frequency
INHx, INLx
VOD
Open drain pullup voltage
nFAULT
IOD
Open drain output current
IGS (1)
Total average gate-drive current (Low
Side and High Side Combined)
VCSAREF
Current sense amplifier reference
voltage
CSAREF
ISO
Shunt amplifier output current
SO
VSHSL
Slew Rate on SHx pins
CBSTx
Capacitor between BSTx and SHx
CGVDD
Capacitor between GVDD and GND
TA
Operating ambient temperature
–40
TJ
Operating junction temperature
–40
(1)
(2)
PVDD
NOM
MAX
4.5
UNIT
60
V
30
V/us
4
V/us
20
V
AVDD
80
mA
BSTx
2
µA
0
5.5
V
0
3.4
V
0
200
kHz
5.5
V
nFAULT
-10
mA
IGHx, IGLx
30
mA
5.5
V
4
2.8
5
mA
4
V/ns
4.7 (2)
µF
130
µF
125
°C
150
°C
Power dissipation and thermal limits must be observed
Current flowing through boot diode (DBOOT) needs to be limited for CBSTx > 4.7µF.
7.4 Thermal Information 1pkg
DRV8329
THERMAL
METRIC(1)
REE (WQFN)
UNIT
36
RθJA
Junction-to-ambient thermal resistance
37.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
25.2
°C/W
RθJB
Junction-to-board thermal resistance
15.8
°C/W
ΨJT
Junction-to-top characterization parameter
0.4
°C/W
ΨJB
Junction-to-board characterization parameter
15.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
4.5
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SLVSFF3C – DECEMBER 2021 – REVISED OCTOBER 2022
7.5 Electrical Characteristics
4.5 V ≤ VPVDD ≤ 60 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical limits apply for TA = 25°C, VPVDD = 24 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLIES (AVDD, PVDD, GVDD)
IPVDDQ
IPVDDS
IPVDD
PVDD standby mode current
PVDD active mode current
VPVDD =24V, nSLEEP = 0, TA = 25°C
1
µA
nSLEEP = LOW
2
µA
VPVDD = 24 V; nSLEEP = HIGH, INHx =
INLX = LOW, DRVOFF = HIGH
2
4
mA
nSLEEP = HIGH, INHx = INLX = LOW,
DRVOFF = HIGH
3
5.5
mA
VPVDD = 24 V, nSLEEP = HIGH, INHx
= INLX = Switching@20kHz, No FETs
connected
4
7
mA
nSLEEP = HIGH, INHx = INLX =
Switching@20kHz, No FETs connected
5
10
mA
VPVDD = 8 V, nSLEEP = HIGH, INHx =
INLX = LOW, No FETs connected
5
10
mA
VPVDD = 24 V, nSLEEP = HIGH, INHx =
INLX = LOW, No FETs connected
5
7
mA
5
10
16
µA
ILBSx
Bootstrap pin leakage current
VBSTx = VSHx = 60V, VGVDD = 0V,
nSLEEP = LOW
ILBS_TRAN
Bootstrap pin active mode transient
leakage current
INLx = INHx = Switching@20kHz, No
FETs connected
60
115
300
µA
INHx = HIGH, INLx = LOW, INLy
= INLz = HIGH, nSLEEP = HIGH,
VPVDD = VSHX = VGVDD = 12V, VBSTx VSHx = 5V
135
200
280
µA
INHx = HIGH, INLx = LOW, INLy
= INLz = HIGH, nSLEEP = HIGH,
Bootstrap pin active mode leakage static VPVDD = VSHX = VGVDD = 12V, VBSTx VSHx = 7V
source current
70
105
145
µA
INHx = LOW, INLx = LOW, INLy = INLz =
HIGH, nSLEEP = HIGH, VPVDD = VSHX =
VGVDD = 12V, VBSTx - VSHx = 5V
25
50
90
µA
INHx = LOW, INLx = LOW, INLy = INLz =
HIGH, nSLEEP = HIGH, VPVDD = VSHX =
VGVDD = 12V, VBSTx - VSHx = 7V
16
28
50
µA
10
40
90
µA
14
45
91
µA
INHx = INLx = LOW, VBSTx - VSHx
= 15, VSHx = 0 to 60V, nSLEEP =
HIGH, DRVOFF = LOW
80
145
210
µA
INHx = INLx = LOW, VBSTx - VSHx
= 11, VSHx = 0 to 60V, nSLEEP =
HIGH, DRVOFF = LOW
15
20
30
µA
INHx = High, INLx = LOW, VBSTx VSHx = 15, VSHx = 0 to 60V, nSLEEP =
HIGH, DRVOFF = LOW
80
145
210
µA
INHx = HIGH, INLx = LOW, VBSTx VSHx = 11, VSHx = 0 to 60V, nSLEEP =
HIGH, DRVOFF = LOW
13
25
35
µA
ILBS_DC_SRC
ILBS_DC_SINK
ILSHx
8
PVDD sleep mode current
INHx = LOW, INLx = LOW, INLy = INLz =
HIGH, nSLEEP = HIGH, VPVDD = VSHX =
Bootstrap pin active mode leakage static VGVDD = 12V, VBSTx - VSHx = 12V
sink current
INHx = High, INLx = LOW, INLy = INLz =
HIGH, nSLEEP = HIGH, VPVDD = VSHX =
VGVDD = 12V, VBSTx - VSHx = 12V
Source pin leakage current
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SLVSFF3C – DECEMBER 2021 – REVISED OCTOBER 2022
4.5 V ≤ VPVDD ≤ 60 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical limits apply for TA = 25°C, VPVDD = 24 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1
2
ms
nSLEEP = High to Active mode (Outputs
Ready). CGVDD = 100 uF, CAVDD = 10
uF, CBSTx = 10 uF
10
15
ms
VPVDD = 12V, nSLEEP = HIGH to
Active mode (Outputs Ready), DRVOFF
= LOW, CGVDD = 10 uF
1
2
ms
0.05
0.1
ms
nSLEEP = HIGH to Active
mode (Outputs Ready), DRVOFF =
LOW, CGVDD = 10 uF, CBSTx = 1 uF
Turnon time (nSLEEP)
tWAKE
Turnon time (DRVOFF)
DRVOFF = LOW to Active mode
(Outputs Ready), nSLEEP = High
tSLEEP
Turnoff time
nSLEEP = LOW to Sleep mode
tRST
Minimum Reset Pulse Time
nSLEEP = LOW period to reset faults
1
VPVDD ≥ 40 V, IGS = 10 mA, TJ= 25°C
11.8
22 V ≤VPVDD ≤ 40 V, IGS = 30 mA, TJ=
25°C
VGVDD_RT
GVDD Gate driver regulator voltage
(Room Temperature)
20
us
1.2
us
13
15
V
11.8
13
15
V
8 V ≤VPVDD ≤ 22 V, IGS = 30 mA, TJ=
25°C
11.8
13
15
V
6.75 V ≤VPVDD ≤ 8 V, IGS = 10 mA, TJ=
25°C
11.8
13
14.5
V
2*VPVDD
-1
13.5
V
VPVDD ≥ 40 V, IGS = 10 mA
11.5
15.5
V
22 V ≤VPVDD ≤ 40 V, IGS = 30 mA
11.5
15.5
V
8 V ≤VPVDD ≤ 22 V; IGS = 30 mA
11.5
15.5
V
6.75 V ≤VPVDD ≤ 8 V, IGS = 10 mA
11.5
14.5
V
2*VPVDD
- 1.4
13.5
V
4.5 V ≤VPVDD ≤ 6.75 V, IGS = 10 mA, TJ=
25°C
VGVDD
GVDD Gate driver regulator voltage
4.5 V ≤VPVDD ≤ 6.75 V, IGS = 10 mA
VAVDD_RT
VAVDD
AVDD Analog regulator voltage (Room
Temperature)
AVDD Analog regulator voltage
UNIT
VPVDD ≥ 6 V, 0 mA ≤ IAVDD ≤ 30 mA, TJ=
25°C
3.26
3.3
3.33
V
VPVDD ≥ 6 V, 30 mA ≤ IAVDD ≤ 80 mA, TJ=
25°C
3.2
3.3
3.4
V
VPVDD ≤ 6 V, 0 mA ≤ IAVDD ≤ 50 mA, TJ=
25°C
3.13
3.3
3.46
V
VPVDD ≥ 6 V, 0 mA ≤ IAVDD ≤ 80 mA
3.2
3.3
3.4
V
VPVDD ≤ 6 V, 0 mA ≤ IAVDD ≤ 50 mA
3.125
3.3
3.5
V
DRVOFF
0.8
V
INLx, INHx pins
0.8
V
LOGIC-LEVEL INPUTS (DRVOFF, INHx, INLx, nSLEEP etc)
VIL
Input logic low voltage
VIH
Input logic high voltage
VHYS
Input hysteresis
IIL
Input logic low current
IIH
Input logic high current
DRVOFF
2.2
V
INLx, INHx pins
2.2
V
DRVOFF
200
400
650
mV
INLx, INHx pins
45
240
350
mV
VPIN (Pin Voltage) = 0 V;
-1
0
1
µA
nSLEEP, VPIN (Pin Voltage) = 65 V;
3
6.5
10
µA
nSLEEP, VPIN (Pin Voltage) = 5 V;
3
6
10
µA
Other pins, VPIN (Pin Voltage) = 5 V;
7
20
35
µA
RPD_DRVOFF Input pulldown resistance
DRVOFF To GND
100
200
300
kΩ
RPD_nSLEEP
Input pulldown resistance
nSLEEP To GND
500
800
1500
kΩ
RPD
Input pulldown resistance
All other pins To GND
150
250
350
kΩ
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SLVSFF3C – DECEMBER 2021 – REVISED OCTOBER 2022
4.5 V ≤ VPVDD ≤ 60 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical limits apply for TA = 25°C, VPVDD = 24 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FOUR-LEVEL INPUTS (GAIN)
VL1
Input level 1 voltage
Tied to GND
VL2
Input level 2 voltage
50 kΩ +/- 5% tied to GND
VL3
Input level 3 voltage
200 kΩ +/- 5% tied to GND
VL4
Input level 4 voltage
HiZ or Connect to AVDD
RPU
Input pullup resistance
GAIN To AVDD
0.18*AV
DD
V
0.48*AV 0.5*AVD
DD
D
0.52*AV
DD
V
0.82*AV 0.833*AV
DD
DD
0.85*AV
DD
V
0
AVDD
80
100
V
120
kΩ
OPEN-DRAIN OUTPUTS (nFAULT etc)
VOL
Output logic low voltage
IOD = 5 mA
IOZ
Output logic high current
VOD = 5 V
COD
Output capacitance
VOD = 5 V
-1
0.4
V
1
µA
30
pF
GATE DRIVERS (GHx, GLx, SHx, SLx)
VGSHx_LO
High-side gate drive low level voltage
IGLx = -100 mA; VGVDD = 12V; No FETs
connected
0.05
0.11
0.24
V
VGSHx_HI
High-side gate drive high level voltage
(VBSTx - VGHx)
IGHx = 100 mA; VGVDD = 12V; No FETs
connected
0.28
0.44
0.82
V
VGSLx_LO
Low-side gate drive low level voltage
IGLx = -100 mA; VGVDD = 12V; No FETs
connected
0.05
0.11
0.27
V
VGSLx_HI
Low-side gate drive high level voltage
(VGVDD - VGHx)
IGHx = 100 mA; VGVDD = 12V; No FETs
connected
0.28
0.44
0.82
V
INHx = HIGH, INLx = LOW, INLy = INLz
= HIGH, VPVDD >15V, VGVDD ≥11.5V
8.4
9.6
11.1
V
INHx = HIGH, INLx = LOW, INLy = INLz
= HIGH, VGVDD ≥11.5V
7.5
8.3
9
V
INHx = HIGH, INLx = LOW, INLy = INLz
= HIGH, 7V ≥VGVDD ≥ 8V
5.7
6.5
7.6
V
High-side pullup switch resistance
IGHx = 100 mA; VGVDD= 12V
2.7
4.5
8.4
Ω
High-side pulldown switch resistance
IGHx = 100 mA; VGVDD = 12V
0.5
1.1
2.4
Ω
Low-side pullup switch resistance
IGLx = 100 mA; VGVDD = 12V
2.7
4.5
8.3
Ω
Low-side pulldown switch resistance
IGLx = 100 mA; VGVDD = 12V
0.5
1.1
2.8
Ω
IDRIVEP_HS
High-side peak source gate current
VGSHx = 12V
550
1000
1575
mA
IDRIVEN_HS
High-side peak sink gate current
VGSHx = 0V
1150
2000
2675
mA
IDRIVEP_LS
Low-side peak source gate current
VGSLx = 12V
550
1000
1575
mA
IDRIVEN_LS
Low-side peak sink gate current
VGSLx = 0V
1150
2000
2675
mA
RPD_LS
Low-side passive pull down
GLx to LSS
80
100
120
kΩ
RPDSA_HS
High-side semiactive pull down
GHx to SHx, VGSHx = 2V
8
10
12.5
kΩ
VGSH_100_PH
RDS(ON)_PU_
HS
RDS(ON)_PD_
HS
RDS(ON)_PU_
LS
RDS(ON)_PD_
LS
High-side gate drive voltage in steady
state with 100 % duty cycle (GHx- SHx)
GATE DRIVERS TIMINGS
tPDR_LS
Low-side rising propagation delay
INLx to GLx rising, VGVDD > 8V
70
100
145
ns
tPDF_LS
Low-side falling propagation delay
INLx to GLx falling, VGVDD > 8V
70
100
135
ns
tPDR_HS
High-side rising propagation delay
INHx to GHx rising, VGVDD = VBSTx VSHx > 8V
65
100
145
ns
tPDF_HS
High-side falling propagation delay
INHx to GHx falling, VGVDD = VBSTx VSHx > 8V
70
100
140
ns
10
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4.5 V ≤ VPVDD ≤ 60 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical limits apply for TA = 25°C, VPVDD = 24 V
PARAMETER
tPD_MATCH_P
H
TEST CONDITIONS
Matching propagation delay per phase
tPD_MATCH_P Matching propagation delay phase to
phase
H_PH
tPW_MIN
Minimum input pulse width on INHx,
INLx that changes the output on GHx,
GLx
tDEAD
Gate drive dead time configurable range
tDEAD
Gate drive dead time
MIN
TYP
MAX
GLx turning ON to GLx turning OFF,
VGVDD = VBSTx - VSHx > 8V; SHx = 0V
to 60V, No load on GHx and GLx
-25
±4
25
ns
GLx turning OFF to GHx turning ON,
VGVDD = VBSTx - VSHx > 8V; SHx = 0V
to 60V, No load on GHx and GLx
-28
±4
28
ns
GHx turning ON to GHx turning OFF,
VGVDD = VBSTx - VSHx > 8V; SHx = 0V
to 60V, No load on GHx and GLx
-25
±4
25
ns
GHx turning OFF to GLx turning ON,
VGVDD = VBSTx - VSHx > 8V; SHx = 0V
to 60V, No load on GHx and GLx
-25
±4
25
ns
GHx turning ON to GHy turning ON,
VGVDD = VBSTx - VSHx > 8V; SHx = 0V
to 60V, No load on GHx and GLx
-10
±4
10
ns
GLx turning ON to GLy turning ON,
VGVDD = VBSTx - VSHx > 8V; SHx = 0V
to 60V, No load on GHx and GLx
-10
±4
10
ns
GHx turning OFF to GHy turning OFF,
VGVDD = VBSTx - VSHx > 8V; SHx = 0V to
60V, No load on GHx and GLx
-15
±4
15
ns
GLx turning OFF to GLy turning OFF,
VGVDD = VBSTx - VSHx > 8V; SHx = 0V
to 60V, No load on GHx and GLx
-10
±4
10
ns
18
32
45
ns
2000
ns
90
ns
50
DT pin floating
35
DT pin connected to GND
25
55
80
ns
10 kΩ between DT pin and GND
75
100
140
ns
1350
2000
2650
ns
IBOOT = 100 µA
0.8
V
IBOOT = 100 mA
1.6
V
5.5
9
Ω
4.92
5
5.05
V/V
9.9
10
10.1
V/V
390 kΩ between DT pin and GND
55
UNIT
BOOTSTRAP DIODES
VBOOTD
Bootstrap diode forward voltage
RBOOTD
Bootstrap dynamic resistance
(ΔVBOOTD/ΔIBOOT)
IBOOT = 100 mA and 50 mA
4.5
CURRENT SHUNT AMPLIFIERS (SNx, SOx, SPx, CSAREF)
CSAGAIN = Tied to GND
ACSA
ACSA_ERR
Sense amplifier gain
Sense amplifier gain error
CSAGAIN = 50kΩ ±5% tied to GND
CSAGAIN = 200kΩ ±5% tied to GND
19.75
20
20.2
V/V
CSAGAIN =Hi-Z;
39.6
40
40.6
V/V
TJ = 25℃
-1.5
1.5
%
-20
20 ppm/℃
ACSA_ERR_D Sense amplifier gain error temperature
drift
RIFT
NL
Non linearity Error
0.01
0.05
%
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4.5 V ≤ VPVDD ≤ 60 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical limits apply for TA = 25°C, VPVDD = 24 V
PARAMETER
tSET
Settling time to ±1%
tSET
Settling time to ±1%
TYP
MAX
VSTEP = 1.6 V, ACSA = 5 V/V, CLOAD =
500pF
TEST CONDITIONS
0.6
1
µs
VSTEP = 1.6 V, ACSA = 10 V/V, CLOAD =
500pF
0.6
1.1
µs
VSTEP = 1.6 V, ACSA = 20 V/V, CLOAD =
500pF
0.7
1.2
µs
VSTEP = 1.6 V, ACSA = 40 V/V, CLOAD =
500pF
0.8
1.7
µs
VSTEP = 1.6 V, ACSA = 5 V/V, CLOAD =
60pF
0.3
0.5
µs
VSTEP = 1.6 V, ACSA = 10 V/V, CLOAD =
60pF
0.3
0.5
µs
VSTEP = 1.6 V, ACSA = 20 V/V, CLOAD =
60pF
0.3
0.65
µs
VSTEP = 1.6 V, ACSA = 40 V/V, CLOAD =
60pF
0.3
0.8
µs
3
5
7
MHz
ACSA = 10 V/V, CLOAD = 60-pF, small
signal -3 dB
2.5
4.8
6.6
MHz
ACSA = 20 V/V, CLOAD = 60-pF, small
signal -3 dB
2
4
5.4
MHz
ACSA = 40 V/V, CLOAD = 60-pF, small
signal -3 dB
1.75
3
4.2
MHz
ACSA = 5 V/V, CLOAD = 60-pF, small
signal -3 dB
BW
Bandwidth
tSR
Output slew rate
MIN
VSTEP = 1.6 V, ACSA = 5 V/V, CLOAD =
60-pF, low to high transition
12
V/µs
VSTEP = 1.6 V, ACSA = 10 V/V, CLOAD =
60-pF, low to high transition
13
V/µs
VSTEP = 1.6 V, ACSA = 20 V/V, CLOAD =
60-pF, low to high transition
11
V/µs
VSTEP = 1.6 V, ACSA = 40 V/V, CLOAD =
60-pF, low to high transition
11
V/µs
VSWING
Output voltage range
VCSAREF = 3
0.25
VSWING
Output voltage range
VCSAREF = 5.5
VSWING
Output voltage range
VCOM
Common-mode input range
VDIFF
Differential-mode input range
UNIT
VCSAREF = 3 to 5.5 V
2.75
V
0.25
5.25
V
0.25
VCSAREF
- 0.25
V
-0.15
0.15
V
-0.3
0.3
V
-1.5
1.5
mV
VOFF
Input offset voltage
VSP = VSN = GND; TJ = -40℃,
CSA_VREF = 0
VOFF
Input offset voltage
VSP = VSN = GND; TJ = 25℃,
CSA_VREF = 0
-1.2
1.2
mV
VOFF
Input offset voltage
VSP = VSN = GND; TJ = 175℃,
CSA_VREF= 0
-1.5
1.5
mV
VOFF
Input offset voltage
VSP = VSN = GND
-1.5
VOFF_DRIFT
Input drift offset voltage
VSP = VSN = GND
VBIAS
Output voltage bias ratio
VSP = VSN = GND
0.122
VBIAS_ACC
Output voltage bias ratio accuracy
VSP = VSN = GND
-1.2
IBIAS
Input bias current
VSP = VSN = GND, VCSAREF = 3V to
5.5V
IBIAS_OFF
Input bias current offset
ISP – ISN
ICSASRC
SO ouput sink current capability
12
mV
10
µV/℃
0.125
0.128
V
1.2
%
100
µA
-1
5
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8
7
1
µA
11
mA
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4.5 V ≤ VPVDD ≤ 60 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical limits apply for TA = 25°C, VPVDD = 24 V
PARAMETER
ICSASRC
SO ouput source current capability
CMRR
Common-mode rejection ratio
PSRR
Power-supply rejection ratio (CSAREF)
PSRR
TEST CONDITIONS
MIN
TYP
MAX
2
3.7
6.6
UNIT
mA
DC
80
dB
20 kHz
65
dB
CSAREF to SOx, DC, Differential
80
dB
CSAREF to SOx, 20 kHz, Differential
70
dB
Power-supply rejection ratio (CSAREF)
CSAREF to SOx, 20 kHz, Single Ended
40
dB
ICSA_SUP
Supply current for CSA
VCSAREF = 3.V to 5.5V
1.5
2.1
mA
TCMREC
Common mode recovery time
0.6
0.7
us
CLOAD
Maximum load capacitance
VOFF_OUT
10
Output offset error
nF
ACSA = 5 V/V
-3
3
mV
ACSA = 10 V/V
-4
4
mV
ACSA = 20 V/V
-5
5
mV
ACSA = 40 V/V
-6
6
mV
PROTECTION CIRCUITS
VPVDD_UV
PVDD undervoltage lockout threshold
VPVDD_UV_H
PVDD undervoltagelockout hysteresis
YS
VPVDD rising
4.3
4.4
4.5
VPVDD falling
4
4.1
4.25
Rising to falling threshold
225
265
325
mV
10
20
30
µs
AVDD rising
2.7
2.85
3.0
AVDD falling
2.5
2.65
2.8
Rising to falling threshold
170
200
250
mV
7
12
22
µs
VGVDD rising
7.3
7.5
7.8
V
VGVDD falling
6.4
6.7
6.9
V
Rising to falling threshold
800
900
1000
mV
5
10
15
µs
VBSTx- VSHx; VBSTx rising
3.9
4.45
5
V
tPVDD_UV_DG PVDD undervoltage deglitch time
VAVDD_POR
AVDD supply POR threshold
VAVDD_POR_
AVDD POR hysteresis
HYS
tAVDD_POR_D
G
AVDD POR deglitch time
VGVDD_UV
GVDD undervoltage threshold
VGVDD_UV_H
GVDD undervoltage hysteresis
YS
tGVDD_UV_DG GVDD undervoltage deglitch time
VBST_UV
Bootstrap undervoltage threshold
VBST_UV_HYS Bootstrap undervoltage hysteresis
V
V
VBSTx- VSHx; VBSTx falling
3.7
4.2
4.8
V
Rising to falling threshold
150
220
285
mV
4
6
µs
2.5
V
tBST_UV_DG
Bootstrap undervoltage deglitch time
2
VDS_LVL_RNG
VDS overcurrent protection threshold
linear range
0.1
VDS_DIS
VDS overcurrent protection disable
resistor
VDS_LVL
VDS overcurrent protection threshold
Reference
VDSLVL pin to GVDD
VDSLVL = 100 kΩ to GVDD
VDSLVL = 0.1V
VDSLVL pin = 2.5V
LSS to GND pin = 0.5V
70
100
500
kΩ
3
4.2
5.5
V
0.065
0.1
0.145
2.2
2.5
2.8
V
VSENSE_LVL
VSENSE overcurrent protection threshold
0.48
0.5
0.52
V
tDS_BLK
VDS overcurrent protection blanking time
0.5
1
2.7
µs
tDS_DG
VDS and VSENSE overcurrent protection
deglitch time
1.5
3
5
µs
3
5
7
µs
0.5
1.5
2.2
µs
7
14
21
µs
tSD_SINK_DIG DRVOFF peak sink current duration
tSD_DIG
DRVOFF digital shutdown delay
tSD
DRVOFF analog shutdown delay
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4.5 V ≤ VPVDD ≤ 60 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical limits apply for TA = 25°C, VPVDD = 24 V
PARAMETER
TOTSD
Thermal shutdown temperature
THYS
Thermal shutdown hysteresis
14
TEST CONDITIONS
TJ rising;
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MIN
TYP
MAX
UNIT
160
170
187
°C
16
20
23
°C
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8.5
8.25
8
7.75
7.5
7.25
7
6.75
6.5
6.25
6
5.75
5.5
5.25
5
14
-40 C
25 C
150 C
13.5
13
12.5
GVDD Voltage (V)
Active Current (mA)
7.6 Typical Characteristics
10
-40 C
25 C
150 C
9
8.5
8
5
10
15
20 25 30 35 40
PVDD Voltage (V)
45
50
55
60
0
Figure 7-1. Supply Current over PVDD Voltage
3.34
3.31
3.3
3.29
3.28
10
15
20 25 30 35 40
PVDD Voltage (V)
45
50
55
60
2500
High Side Source
High Side Sink
Low Side Source
Low Side Sink
2250
Peak Current (mA)
3.32
5
Figure 7-2. GVDD Voltage over PVDD Voltage
-40 C
25 C
150 C
3.33
AVDD Voltage (V)
11
10.5
9.5
0
3.27
2000
1750
1500
1250
1000
3.26
3.25
0
8
16
24
32
40
48
56
Load Current (mA)
64
72
-20
0
20
40
60
80
100
Junction Temperature ()
120
140
Figure 7-5. Bootstrap Diode Resistance over
Junction Temperature
-20
0
20
40
60
80
100
Junction Temperature (C)
120
140
Figure 7-4. Driver Peak Current over Junction
Temperature
Bootstrap Diode Forward Voltage Drop (V)
9
8.75
8.5
8.25
8
7.75
7.5
7.25
7
6.75
6.5
6.25
6
5.75
5.5
-40
750
-40
80
Figure 7-3. AVDD Voltage over Load Current
Bootstrap Diode Resistance ()
12
11.5
0.65
0.625
0.6
0.575
0.55
0.525
0.5
0.475
0.45
0.425
0.4
-40
-20
0
20
40
60
80
100
Junction Temperature (C)
120
140
Figure 7-6. Bootstrap Diode Forward Voltage Drop
over Junction Temperature
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8 Detailed Description
8.1 Overview
The DRV8328 family of devices is an integrated three-phase gate driver supporting an input voltage range of
4.5-V to 60-V. These devices decrease system component count, cost, and complexity by integrating three
independent half-bridge gate drivers, trickle charge pump, and a charge pump with linear regulator for the supply
voltages of the high-side and low-side gate drivers. DRV8328 also integrates an accurate low voltage regulator
(AVDD) capable of supporting 3.3 V at 80 mA output. A hardware interface allows for simple configuration of the
motor driver and control of the motor.
The gate drivers support external N-channel high-side and low-side power MOSFETs and can drive up to 1-A
source, 2-A sink peak gate drive currents with a 30-mA average output current. A bootstrap circuit with capacitor
generates the supply voltage of the high-side gate drive and a trickle charge pump is employed to support 100%
duty cycle. The supply voltage of the low-side gate driver is generated using a charge pump with linear regulator
GVDD from the PVDD power supply that regulates to 12 V.
In addition to the high level of device integration, the DRV8328 family of devices provides a wide range of
integrated protection features. These features include power supply undervoltage lockout (PVDDUV), regulator
undervoltage lockout (GVDDUV), Bootstrap Voltage undervoltage lockout (BSTUV), VDS overcurrent monitoring
(OCP), Sense resistor overcurrent monitoring (SEN_OCP) and overtemperature shutdown (TSD). Fault events
are indicated by the nFAULT pin.
The DRV8328 is available in 0.4-mm pitch, 5 × 4 mm 36-pin QFN surface-mount packages.
16
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8.2 Functional Block Diagram
PVDD
0.1 μF
bulk
+
Power
GVDD
PVDD
GVDD
>10 μF
Trickle
CP
BSTA
VCP
Charge
Pump
CPH
470 nF
HS
GHA
HS
CPL
SHA
GVDD
80 mA
AVDD**
LS
GLA
LS
3.3-V LDO
LSS
1 μF
GVDD
Trickle
CP
BSTB
nSLEEP
HS
GHB
HS
INHA
PVDD
SHB
INLA
GVDD
LS
Digital
+
Control
-
Control
Inputs
INLB
GLB
LS
INHB
LSS
GVDD
INHC
Trickle
CP
BSTC
INLC
HS
PVDD
GHC
HS
SHC
DT*
GVDD
LS
RDT
nFAULT
GLC
LS
LSS
Outputs
DRVOFF**
LSS
RSENSE
+
-
RSENSE
0.5
VDSLVL*
VDS
3x LS, 3x HS
VDS Comp
VSENSE OCP
GND
+
* DRV8328A, DRV8318B only
** DRV8328C, DRV8328D only
Thermal Pad
Figure 8-1. Block Diagram of DRV8328
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8.3 Feature Description
Table 8-1 lists the recommended values of the external components for the gate driver and the buck regulator.
Table 8-1. DRV8328 External Components
(1)
COMPONENTS
PIN 1
PIN 2
RECOMMENDED
CPVDD1
PVDD
PGND
X5R or X7R, 0.1-µF, >2x PVDD-rated capacitor
CPVDD2
PVDD
PGND
≥ 10 µF, >2x PVDD-rated capacitor
CCP
CPH
CPL
X5R or X7R, 470-nF, PVDD-rated capacitor
CGVDD
GVDD
GND
X5R or X7R, ≥10-uF, 25V-rated capacitor
CAVDD
AVDD
AGND
X5R or X7R, ≥1-µF, 6.3-V capacitor
CBSTx
BSTx
SHx
X5R or X7R, 1-µF (typical), 25V-rated capacitor
RnFAULT
VCC(1)
nFAULT
Pullup resistor (10 kΩ)
RDT
DT
AGND
Hardware interface resistor. Refer to Deadtime and
Cross-Conduction Prevention for the details.
The VCC pin is not a pin on the DRV8328 , but a VCC supply voltage pullup is required for the open-drain output, nFAULT. This pin
can also be pulled up to AVDD.
8.3.1 Three BLDC Gate Drivers
The DRV8328 family of devices integrates three half-bridge gate drivers, each capable of driving high-side and
low-side N-channel power MOSFETs. A charge pump is used to generate the GVDD to supply the correct gate
bias voltage across a wide operating voltage range. The low side gate outputs are driven directly from GVDD,
while the high side gate outputs are driven using a bootstrap circuit with an integrated diode. An internal trickle
charge pump provides support for 100% duty cycle operation. The half-bridge gate drivers can be used in
combination to drive a three-phase motor or separately to drive other types of loads.
8.3.1.1 PWM Control Modes
The DRV8328 provides two different PWM control modes to support various commutation and control methods.
The PWM control modes are supported in different device variants (see Table 5-1)
8.3.1.1.1 6x PWM Mode
In 6x PWM mode, each half-bridge supports three output states: low, high, or high-impedance (Hi-Z). The
corresponding INHx and INLx signals control the output state as listed in Table 8-2.
Table 8-2. 6x PWM Mode Truth Table
18
INLx
INHx
GLx
GHx
SHx
0
0
L
L
Hi-Z
0
1
L
H
H
1
0
H
L
L
1
1
L
L
Hi-Z
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8.3.1.1.2 3x PWM Mode
In 3x PWM mode, the INHx pin controls each half-bridge and supports two output states: low or high. The INLx
pin is used to put the half bridge in the Hi-Z state. If the Hi-Z state is not required, tie all INLx pins to logic high.
The corresponding INHx and INLx signals control the output state as listed in Table 8-3.
Table 8-3. 3x PWM Mode Truth Table
INLx
INHx
GLx
GHx
SHx
0
1
X
L
L
Hi-Z
0
H
L
L
1
1
L
H
H
8.3.1.2 Device Hardware Interface
The DRV8328 utilize a hardware interface to configure different device settings. These hardware configurable
inputs are DT and VDSLVL. General fault information is reported on the nFAULT pin.
•
•
The DT pin configures the gate drive dead time. The dead time can adjusted by changing the resistor value
from the DT pin to GND.
The VDSLVL pin configures the voltage threshold of the VDS overcurrent monitors. The voltage applied to the
VDSLVL pin is directly used as reference for the VDS comparator
For more information on the hardware interface, see Section 8.3.3.
VDSLVL
Hardware
Interface
DT
RDT
Figure 8-2. Hardware Interface
8.3.1.3 Gate Drive Architecture
The gate driver device use a complimentary, push-pull topology for both the high-side and low-side drivers. This
topology allows for both a strong pullup and pulldown of the external MOSFET gates. The low side gate drivers
are supplied directly from the GVDD regulator supply. The operating mode of GVDD depends on the voltage of
PVDD, when the PVDD >18V, the GVDD voltage is generated by an LDO, whereas PVDD < 18V, the GVDD
voltage is generated by a charge pump. For the high-side gate drivers a bootstrap diode and capacitor are
used to generate the floating high-side gate voltage supply. The bootstrap diode is integrated and an external
bootstrap capacitor is used between BSTx and SHx pins. To support 100% duty cycle control, a trickle charge
pump is integrated into the device. The trickle charge pump is connected to the BSTx node to prevent voltage
drop due to the leakage currents of the driver and external MOSFET.
The high-side gate driver has a semi-active pulldown and low side gate has passive pulldown to help prevent the
external MOSFET from turning ON during sleep state or when the power supply is disconnected.
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CGVDD
GVDD
PVDD
CPVDD2
Trickle
Charge
Pump
CPVDD1
CPH
CCP
Charge
Pump
DBSTx
VBAT
BSTx
CPL
CBSTx
INHx
GHx
Level
Shifters
Digital
Core
RPDSA_LS
Semi-active
pull-down
INLx
SHx
GVDD
GLx
Level
Shifters
RPD_LS
LSS
GND
GND
Figure 8-3. Gate Driver Block Diagram
8.3.1.3.1 Propagation Delay
The propagation delay time (tpd) is measured as the time between an input logic edge to a detected output
change. This time has two parts consisting of the digital propagation delay, and the delay through the analog
gate drivers.
To support multiple control modes and dead time insertion, a small digital delay is added as the input command
propagates through the device. Lastly, the analog gate drivers have a small delay that contributes to the overall
propagation delay of the device.
8.3.1.3.2 Deadtime and Cross-Conduction Prevention
In the DRV8328, high- and low-side inputs operate independently, with an exception to prevent cross conduction
when the high and low side of the same half-bridge are turned ON at same time. The device turns OFF high- and
low- side output to prevent shoot through when high- and low-side inputs are logic high at same time.
The DRV8328 also provides dead time insertion to prevent both external MOSFETs of each half-bridge from
switching on at the same time. In devices with a DT pin, deadtime can be linearly adjusted between 100 ns and
2000 ns by connecting s resistor between DT and ground. When the DT pin is left floating or connected to GND,
a fixed deadtime of 55 ns (typical value) is inserted. The value of the resistor can be calculated using following
equation.
RDT kΩ =
20
Deadtime ns
− 10 kΩ
5
(1)
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INHx/INLx Inputs
INHx
INLx
GHx/GLx outputs
GHx
GLx
DT
DT
Cross
Conduction
Prevention
Figure 8-4. Cross Conduction Prevention and Deadtime Insertion
8.3.2 AVDD Linear Voltage Regulator
A 3.3-V, 80-mA linear regulator is available for use by external circuitry. The output of the LDO is fixed to 3.3-V.
This regulator can provide the supply voltage for a low-power MCU or other circuitry with low supply current
needs. The output of the AVDD regulator should be bypassed near the AVDD pin with a X5R or X7R, 1-µF, 6.3-V
ceramic capacitor routed back to the AGND pin.
PVDD
REF
+
±
AVDD
3.3-V, 80 mA
1 …F
AGND
Figure 8-5. AVDD Linear Regulator Block Diagram
The power dissipated in the device by the AVDD linear regulator can be calculated as follows: P = (VPVDDVAVDD) x IAVDD
For example, at a VPVDD of 24 V, drawing 20 mA out of AVDD results in a power dissipation as shown in
Equation 2.
P
24 V 3.3 V u 20 mA
414 mW
(2)
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8.3.3 Pin Diagrams
Figure 8-6 shows the input structure for the logic level pins, INHx and INLx. The input can be driven with a
voltage or external resistor.
AVDD
STATE
RESISTANCE
INPUT
VIH
Tied to AVDD
Logic High
VIL
Tied to AGND
Logic Low
RPD
Figure 8-6. Logic-Level Input Pin Structure
Figure 8-7 shows the structure of the open-drain output pin, nFAULT. The open-drain output requires an external
pullup resistor to function correctly.
AVDD
RPU
STATE
STATUS
No Fault
Inactive
OUTPUT
Fault
Active
Active
Inactive
Figure 8-7. Open-Drain Output Pin Structure
8.3.4 Gate Driver Shutdown Sequence (DRVOFF)
When DRVOFF is driven high, the gate driver goes into shutdown, overriding signals on inputs pins INHx and
INLx. DRVOFF bypasses the digital control logic inside the device, and is connected directly to the gate driver
output (see Figure 8-8). This pin provides a mechanism for externally monitored faults to disable the gate driver
by directly bypassing an external controller or the internal control logic. When the DRV8328 detects that the
DRVOFF pin is driven high, it disables the gate driver and puts it into pulldown mode (see Figure 8-9). The
gate driver shutdown sequence proceeds as shown in Figure 8-9. When the gate driver initiates the shutdown
sequence, the active driver pulldown is applied at ISINK current for the tSD_SINK_DIG time, after which the gate
driver moves to passive pulldown mode.
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PVDD
OFF
DRVOFF
OFF
GHA
GHB
OFF
A
GHC
Digital
Gate
Driver
B
OFF
C
GLA
OFF
GLB
OFF
GLC
GND
Figure 8-8. DRV8328 DRVOFF Gate Driver Output State
INHx (INLx)
High
GHx-SHx
(GLx-LSS)
tSD_DIG
DRVOFF pin
tSD_SINK_DIG
tSD
Predriver
Current
ISOURCE/ISINK
ISINK
Passive (RPD_LS) and Semiactive
PullDown (RPDSA_HS)
Figure 8-9. Gate Driver Shutdown Seqeunce
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8.3.5 Gate Driver Protective Circuits
The DRV8328 are protected against PVDD undervoltage and overvoltage, AVDD power-on reset, bootstrap
undervoltage, GVDD undervoltage, MOSFET VDS and VSENSE overcurrent events.
Table 8-4. Fault Action and Response
FAULT
CONDITION
PVDD
undervoltage
(PVDD_UV)
VPVDD < VPVDD_UV
AVDD POR
(AVDD_POR)
CONFIGURATION
REPORT
GATE DRIVER
LOGIC
RECOVERY
-
nFAULT
Disabled1
Disabled
Automatic:
VPVDD > VPVDD_UV
VAVDD < VAVDD_POR
-
nFAULT
Disabled1
Disabled
Automatic:
VAVDD > VAVDD_POR
GVDD
undervoltage
(GVDD_UV)
VGVDD < VGVDD_UV
-
nFAULT
Pulled Low 2
Active
Latched:
nSLEEP Reset Pulse
BSTx
undervoltage
(BST_UV)
VBSTx - VSHx < VBST_UV and
INHx = High
-
nFAULT
Pulled Low 2
Active
Latched:
nSLEEP Reset Pulse
VDS overcurrent
(VDS_OCP)
0.1V < VVDSLVL < 2.5V
nFAULT
Pulled Low 2
Active
VDS > VDS_LVL
Latched:
nSLEEP Reset Pulse
None
Active
Active
No action
VSENSE
overcurrent
(SEN_OCP)
nFAULT
Pulled Low 2
Active
VSP > VSENSE_LVL
Latched:
nSLEEP Reset Pulse
None
Active
Active
No action
Thermal
shutdown
(OTSD)
TJ > TOTSD
nFAULT
Pulled Low 2
Active
Latched:
nSLEEP Reset Pulse
VDSLVL pin 100kΩ
tied to GVDD
VDSLVL pin 100kΩ
tied to GVDD
-
1. Disabled: Passive pull down for GLx and semiactive pull down for GHx
2. Pulled Low: GHx and GLx are actively pulled low by the gate driver
8.3.5.1 PVDD Supply Undervoltage Lockout (PVDD_UV)
If at any time the power supply voltage on the PVDD pin falls below the VPVDD_UV threshold for longer than the
tPVDD_UV_DG time, the device detects a PVDD undervoltage event. After detecting the undervoltage condition, the
gate driver is disabled, the charge pump is disabled, the internal digital logic is disabled, and the nFAULT pin is
driven low. Normal operation starts again (the gate driver becomes operable and the nFAULT pin is released)
when the PVDD pin rises above VPVDD_UV.
8.3.5.2 AVDD Power on Reset (AVDD_POR)
If at any time the supply voltage on the AVDD pin falls below the VAVDD_POR threshold for longer than the
tAVDD_POR_DG time, the device enters an inactive state, disabling the gate driver, the charge pump, and the
internal digital logic, and nFAULT is driven low. Normal operation (digital logic operational) requires nSLEEP to
be asserted high and AVDD to exceed VAVDD_POR level.
8.3.5.3 GVDD Undervoltage Lockout (GVDD_UV)
If at any time the voltage on the GVDD pin falls lower than the VGVDD_UV threshold voltage for longer than the
tGVDD_UV_DG time, the device detects a GVDD undervoltage event. After detecting the GVDD_UV undervoltage
event, all of the gate driver outputs are driven low to disable the external MOSFETs, the charge pump is disabled
and nFAULT pin is driven low. After the GVDD_UV condition is cleared, the fault state remains latched and can
be cleared through an nSLEEP pin reset pulse (tRST)
Note
After the GVDD_UV fault is cleared through an nSLEEP pin reset pulse, the nFAULT pin is held low
until the GVDD capacitor is refreshed by the charge pump. After the GVDD capacitor is charged, the
nFAULT pin is automatically released. The duration that the nFAULT pin is low after the fault is cleared
will not exceed tWAKE time.
24
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8.3.5.4 BST Undervoltage Lockout (BST_UV)
If at any time the voltage across BSTx and SHx pins falls lower than the VBST_UV threshold voltage for longer
than the tBST_UV_DG time, the device detects a BST undervoltage event. Afer detecting the BST_UV event, all of
the gate driver outputs are driven low to disable the external MOSFETs, and nFAULT pin is driven low. After the
BST_UV condition is cleared, the fault state remains latched and can be cleared through an nSLEEP pin reset
pulse (tRST).
8.3.5.5 MOSFET VDS Overcurrent Protection (VDS_OCP)
The device has adjustable VDS voltage monitors to detect overcurrent or short-circuit conditions on the external
power MOSFETs. A MOSFET overcurrent event is sensed by monitoring the VDS voltage drop across the
external MOSFET RDS(on). The high-side VDS monitors measure between the PVDD and SHx pins and the lowside VDS monitors measure between the SHx and LSS pins. If the voltage across external MOSFET exceeds
the VDS_LVL threshold for longer than the tDS_DG deglitch time, a VDS_OCP event is recognized. Afer detecting
the VDS overcurrent event, all of the gate driver outputs are driven low to disable the external MOSFETs and
nFAULT pin is driven low. The VDS threshold can be set between 0.1 V to 2.5 V by applying a voltage on the
VDSLVL pin. VDS OCP can be disabled by connecting VDSLVL to GVDD through a 100 kΩ resistor. After the
VDS_OCP condition is cleared, the fault state remains latched and can be cleared through the nSLEEP pin reset
pulse (tRST).
PVDD
VDS
+
–
+
VDS
–
+
VDS
–
VVDS_OCP
+
VDS
–
VVDS_OCP
PVDD
GHx
SHx
GLx
LSS
GND
Figure 8-10. DRV8328 VDS Monitors
8.3.5.6 VSENSE Overcurrent Protection (SEN_OCP)
Overcurrent is also monitored by sensing the voltage drop across the external current sense resistor between
the LSS and GND pins. If at any time the voltage on the LSS input exceeds the VSEN_OCP threshold for longer
than the tDS_DEG deglitch time, a SEN_OCP event is recognized. Afer detecting the SEN_OCP overcurrent
event, all of the gate driver outputs are driven low to disable the external MOSFETs and the nFAULT pin is
driven low. The VSENSE threshold is fixed at 0.5 V and deglitch time is fixed to 3 µs. After the SEN_OCP
condition is cleared, the fault state remains latched and can be cleared through an nSLEEP pin reset pulse
(tRST). SEN_OCP can be disabled by connecting VDSLVL to GVDD through a 100 kΩ resistor.
8.3.5.7 Thermal Shutdown (OTSD)
If the die temperature exceeds the trip point of the thermal shutdown limit (TOTSD), an OTSD event is recognized.
After detecting the OTSD overtemperature event, all of the gate driver outputs are driven low to disable the
external MOSFETs, charge pump is disabled and nFAULT pin is driven low. After OTSD condition is cleared, the
fault state remains latched and can be cleared through an nSLEEP pin reset pulse (tRST)
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8.4 Device Functional Modes
8.4.1 Gate Driver Functional Modes
8.4.1.1 Sleep Mode
The nSLEEP pin manages the state of the DRV8328. When the nSLEEP pin is low, the device goes to a
low-power sleep mode. In sleep mode, all gate drivers are disabled, all external MOSFETs are disabled, the
GVDD regulator is disabled and the AVDD regulator is disabled. The tSLEEP time must elapse after a falling edge
on the nSLEEP pin before the device goes to sleep mode. The device comes out of sleep mode automatically if
the nSLEEP pin is pulled high. The tWAKE time must elapse before the device is ready for inputs.
Note
During power up and power down of the device through the nSLEEP pin, the nFAULT pin is held
low as the internal regulators are not active. After the regulators have been active, the nFAULT pin is
automatically released. The duration that the nFAULT pin is low does not exceed the tSLEEP or tWAKE
time.
8.4.1.2 Operating Mode
When the nSLEEP pin is high and the VPVDD voltage is greater than the VPVDD_UV voltage, the device goes
to operating mode. The tWAKE time must elapse before the device is ready for inputs. In this mode the GVDD
regulator and AVDD regulator are active.
8.4.1.3 Fault Reset (nSLEEP Reset Pulse)
In the case of device latched faults, the DRV8328 goes into a partial shutdown state to help protect the external
power MOSFETs and system.
When the fault condition clears, the device can be re-enabled by issuing a reset pulse to the nSLEEP pin. The
nSLEEP reset pulse (tRST) consists of a high-to-low-to-high transition on the nSLEEP pin. The reset pulse has
no effect on any of the regulators, device settings, or other functional blocks as long as the low period of the
sequence falls within the t RST time window. If the pulse is longer than the tRST time window, the device will start a
complete shutdown sequence.
Note
If the user wants to put the device into sleep state after latched fault event, the inputs INHx and INLx
needs to be pulled low prior to driving the nSLEEP pin. If the inputs INHx and INLx are not driven low,
then the fault is reset after nSLEEP is driven low for the tRST time and there can be pulses on gate
driver outputs GHx and GLx prior to device entering sleep. The duration of pulses on GHx and GLx
can be of duration tSLEEP if INHx and INLx are not pulled low.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The DRV8328 family of devices is primarily used in applications for three-phase brushless DC motor control. The
design procedures in the Section 9.2 section highlight how to use and configure the DRV8328 family of devices.
9.2 Typical Application
9.2.1 Three Phase Brushless-DC Motor Control
In this application, the DRV8328 is used to drive a three-phase Brushless-DC motor.
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PVDD
PVDD
GVDD
>10 uF
>10 uF
0.1 uF
PVDD
CPH
470 nF
BSTA
CBSTA RGHA
>1uF
CPL
GHA
AVDD**
SHA
RGLA
AVDD
GLA
DRV8328
INHA
PVDD
BSTB
INLA
INHB
CBSTB
RGHB
GHB
PWM
MCU
INLB
SHB
INHC
RGLB
GLB
INLC
ADC
DRVOFF**
PVDD
Analog Input
(0.1 to 2.5V)
BSTC
VDSLVL*
CBSTC
RGHC
GHC
DT*
RDT
SHC
RGLC
GLC
LSS
GND
RSENSE
IN+
*DRV8328A, DRV8328B
**DRV8328C, DRV8328D
IN-
R
–
OUT
+
AVDD
IN-
R
IN+
R
R
VREF
R
R
+
Current Sense Amplifier 1x
–
Figure 9-1. DRV8328 Application Diagram
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The DRV8328 is designed to implement one external CSA. If three external CSAs are used, please see
Implementing 3 External CSAs using DRV8328.
9.2.1.1 Detailed Design Procedure
Section 9.2.1.1 lists the example input parameters for the system design.
Table 9-1. Design parameters
DESIGN PARAMETERS
REFERENCE
EXAMPLE VALUE
Supply voltage
VPVDD
24 V
Motor peak current
IPEAK
20 A
PWM Frequency
fPWM
20 kHz
MOSFET VDS Slew Rate
SR
120 V/us
MOSFET input gate capacitance
QG
108 nC
MOSFET input gate capacitance
QGD
14 nC
Dead time
tdead
200 ns
Overcurrent protection
IOCP
30 A
9.2.1.1.1 Motor Voltage
Brushless-DC motors are typically rated for a certain voltage (for example 18-V, 24-V or 36-V). The DRV8328
allows for a range of possible operating voltages from 4.5-V to 60-V.
9.2.1.1.2 Bootstrap Capacitor and GVDD Capacitor Selection
The bootstrap capacitor must be sized to maintain the bootstrap voltage above the undervoltage lockout for
normal operation. Equation 3 calculates the maximum allowable voltage drop across the bootstrap capacitor:
¿8$56: = 8)8&& F 8$116& F 8$5678
(3)
=12 V – 0.85 V – 4.45 V = 6.7 V
where
• VGVDD is the supply voltage of the gate drive
• VBOOTD is the forward voltage drop of the bootstrap diode
• VBSTUV is the threshold of the bootstrap undervoltage lockout
In this example the allowed voltage drop across bootstrap capacitor is 6.7 V. It is generally recommended that
ripple voltage on both the bootstrap capacitor and GVDD capacitor should be minimized as much as possible.
Many of commercial, industrial, and automotive applications use ripple value between 0.5 V to 1 V.
The total charge needed per switching cycle can be estimated with Equation 4:
QTOT = QG +
ILBS_TRAN
fSW
(4)
=54 nC + 115 μA/20 kHz = 54 nC + 5.8 nC = 59.8nC
where
• QG is the total MOSFET gate charge
• ILBS_TRAN is the bootstrap pin leakage current
• fSW is the is the PWM frequency
The minimum bootstrap capacitor can then be estimated as below assuming 1V of ΔVBSTx:
%$56_/+0 = 3616W¿8
(5)
$56:
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= 59.8 nC / 1 V = 59.8 nF
The calculated value of minimum bootstrap capacitor is 59.8 nF. It should be noted that, this value of
capacitance is needed at full bias voltage. In practice, the value of the bootstrap capacitor must be greater
than calculated value to allow for situations where the power stage may skip pulse due to various transient
conditions. It is recommended to use a 100 nF bootstrap capacitor in this example. It is also recommenced to
include enough margin and place the bootstrap capacitor as close to the BSTx and SHx pins as possible.
%)8&& R 10 × %$56:
(6)
= 10*100 nF= 1 μF
For this example application, choose a 1-µF CGVDD capacitor. Choose a capacitor with a voltage rating at
least twice the maximum voltage that it will be exposed to because most ceramic capacitors lose significant
capacitance when biased. This value also improves the long-term reliability of the system.
Note
For higher power system requiring 100% duty cycle support for longer duration it is recommended to
use CBSTx of ≥1μF and CGVDD of ≥10 μF.
9.2.1.1.3 Gate Drive Current
Selecting an appropriate gate drive current is essential when turning on or off power MOSFETs gates to
switch motor current. The amount of gate drive current and input capacitance of the MOSFETs determines the
drain-to-source voltage slew rate (VDS). Gate drive current can be sourced from GVDD into the MOSFET gate
(ISOURCE) or sunk from the MOSFET gate into SHx or LSS (ISINK).
Using too high of a gate drive current can turn on MOSFETs too quickly which may cause excessive ringing,
dV/dt coupling, or cross-conduction from switching large amounts of current. If parasitic inductances and
capacitances exist in the system, voltage spiking or ringing may occur which can damage the MOSFETs or
DRV8328 device.
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PVDD
PVDD
VINHx
VGHx
GVDD
INHx
I
GHx
HS
HS
VDS
SHx
PHASE
VGLx
CGD
GVDD
INLx
GLx
LS
LS
LSS
Figure 9-2. Effects of high gate drive current
On the other hand, using too low of a gate drive current causes long VDS slew rates. Turning on the MOSFETs
too slowly may heat up the MOSFETs due to RDS,on switching losses.
The relationship between gate drive current IGATE, MOSFET gate-to-drain charge QGD, and VDS slew rate
switching time trise,fall are described by the following equations:
V
SRDS = t DS
rise, fall
(7)
Qgd
IGATE = t
rise, fall
(8)
It is recommend to evaluate at lower gate drive currents and increase gate drive current settings to avoid
damage from unintended operation during initial evaluation.
9.2.1.1.4 Gate Resistor Selection
The slew rate of the SHx connection will be dependent on the rate at which the gate of the external MOSFETs is
controlled. The pull-up/pull-down strength of the DRV8328 is fixed internally, hence the slew rate of gate voltage
can be controlled with an external series gate resistor. In some applications, the gate charge of the MOSFET,
which is the load on gate driver device, is significantly larger than the gate driver peak output current capability.
In such applications, external gate resistors can limit the peak output current of the gate driver. External gate
resistors are also used to dampen ringing and noise.
The specific parameters of the MOSFET, system voltage, and board parasitics will all affect the final SHx slew
rate, so generally selecting an optimal value or configuration of external gate resistor is an iterative process.
To lower the gate drive current, a series resistor RGATE can be placed on the gate drive outputs to control the
current for the source and sink current paths. A single gate resistor will have the same gate path for source and
sink gate current, so larger RGATE values will yield similar SHx slew rates. Note that gate drive current varies by
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PVDD voltage, junction temperature, and process variation of the device. Gate resistor values can be estimated
with +/-30% accuracy using the Gate Resistor Calculator.
PVDD
PVDD
GVDD
INHx
RGATE
GHx
HS
HS
SHx
GVDD
INLx
GLx
LS
LSS
RGATE
LS
RSINK
Figure 9-3. Gate driver outputs with series resistors
Typically, it is recommended to have the sink current be twice the source current to implement a strong pulldown
from gate to the source to ensure the MOSFET stays off while the opposite FET is switching. This can be
implemented discretely by providing a separate path through a resistor for the source and sink currents by
placing a diode and sink resistor (RSINK) in parallel to the source resistor (RSOURCE). Using the same value of
source and sink resistors results in half the equivalent resistance for the sink path. This yields twice the gate
drive sink current compared to the source current, and SHx will slew twice as fast when turning off the MOSFET.
PVDD
PVDD
GVDD
INHx
GHx
HS
SHx
GVDD
INLx
LS
GLx
LSS
RSOURCE
HS
RSINK
RSOURCE
LS
RSINK
Figure 9-4. Gate driver outputs with separate source and sink current paths
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9.2.1.1.5 System Considerations in High Power Designs
Higher power system designs can require design and application considerations that are not regarded in lower
power system designs. It is important to combat the volatile nature of higher power systems by implementing
troubleshooting guidelines, external components and circuits, driver product features, or layout techniques. For
more information, please visit the System Design Considerations for High-Power Motor Driver Applications
application note.
9.2.1.1.5.1 Capacitor Voltage Ratings
Use capacitors with voltage ratings that are 2x the supply voltage (PVDD, GVDD, AVDD, etc). Capacitors can
experience up to half the rated capacitance due to poor DC voltage rating performance.
For example, since the bootstrap voltage is around 12 to 13-V with respect to SHx (BSTx-SHx) then the
BSTx-SHx capacitor should be rated for 25-V or greater.
9.2.1.1.5.2 External Power Stage Components
External components in the power stage are not required by design but are helpful in suppressing transients,
managing inductor coil energy, mitigating supply pumping, dampening phase ringing, or providing strong gate-tosource pulldown paths. These components are used for system tuning and debuggability so the BLDC motor
system is robust while avoiding damage to the DRV8328 device or external MOSFETs.
Figure 9-5 shows examples of power stage components that can be optimally placed in the design.
PVDD
PVDD
GVDD
INHx
RSOURCE
GHx
HS
RPD
HS
CBULK
RSINK
SHx
RSNUB
CSNUB
PHASE
CHSD_LSS
CSNUB
GVDD
INLx
RSOURCE
GLx
LS
LSS
RSINK
RPD
LS
RSNUB
DGS
Figure 9-5. Optional external power stage components
Some examples of issues and external components that can resolve those issues are found in Table 9-2:
Table 9-2. Common issues and resolutions for power stage debugging
Issue
Resolution
Component(s)
Gate drive current required is too large,
resulting in very fast MOSFET VDS slew rate
Series resistors required for gate drive
current adjustability
0-100 Ω series resistors (RGATE/RSOURCE)
at gate driver outputs (GHx/GLx), optional
sink resistor (RSINK) and diode in parallel
with gate resistor for adjustable sink current
Ringing at phase’s switch node (SHx)
resulting in high EMI emissions
RC snubbers placed in parallel to each
HS/LS MOSFET to dampen oscillations
Resistor (RSNUB) and Capacitor (CSNUB)
placed parallel to the MOSFET, calculate
RC values based on ringing frequency using
Proper RC Snubber Design for Motor Drivers
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Table 9-2. Common issues and resolutions for power stage debugging (continued)
Issue
Resolution
Component(s)
Negative transients at low-side source (LSS)
below minimum specification
HS drain to LS source capacitor to suppress
negative bouncing
0.01uF-1uF, VM-rated capacitor from
PVDD-LSS (CHSD_LSS) placed near LS
MOSFET’s source
Negative transient at low-side gate (GLx)
below minimum specification
Gate-to-ground Zener diode to clamp
negative voltage
GVDD voltage rated Zener diode (DGS)
with anode connected to GND and cathode
connected to GLx
Extra protection required to ensure MOSFET External gate-to-source pulldown resistors
is turned off if gate drive signals are Hi-Z
(after series gate resistors)
10 kΩ to 100 kΩ resistor (RPD) connected
from gate to source for each MOSFET
9.2.1.1.5.3 Parallel MOSFET Configuration
If higher MOSFET continuous drain current ratings are required for the motor, parallel MOSFETs can be used for
higher current capability. However, this requires special schematic and layout design requirements to switch both
MOSFETs simultaneously because one MOSFET may turn on faster than the other due to process variation.
It is recommended to place the MOSFETs close together with a common gate signal that splits as close as
possible to the MOSFETs gates. If gate resistance is required, calculate the equivalent resistance required for
the equivalently rated MOSFET, and place the gate resistors as close as possible to the MOSFET’s gate input to
dampen any coupling into the gate driver.
For more information, please visit the Driving Parallel MOSFETs application brief.
9.2.1.1.6 Dead Time Resistor Selection
Dead time insertion is available in the DRV8328 via a resistor (RDT) from the DT pin to ground as shown in
Figure 9-6. The ranges of dead time in the DRV8328 is 100 ns to 2000 ns when RDT is tied to GND from the DT
pin. A linear interpolation of the resistance value is used to set the appropriate dead time.
RDT
DT
Figure 9-6. Dead time resistor
Dead time (in nanoseconds) can be calculated from the dead time resistor calculation in Equation 1.
Dead time can also be implemented from the PWM inputs generated by an MCU. If dead time is inserted at the
PWM inputs and the DRV8328, then the driver output PWM dead time is the larger of the two dead times. For
instance, if 200 ns dead time is inserted at the MCU inputs and 50 ns dead time is inserted in the DRV8328 via
the DT pin, then the output driver PWM dead time will be 200 ns.
9.2.1.1.7 VDSLVL Selection
VDSLVL is an analog voltage used to directly set the VDS overcurrent threshold for overcurrent protection. It can
be sourced directly from an analog voltage source (such as a digital-to-analog converter) or divided down from a
voltage rail (such as a resistor divider from AVDD) as shown in Figure 9-7.
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Vin
R1
VDSLVL
R2
Figure 9-7. Resistor divider to set VDSLVL from a voltage rail
Equation 9 and Equation 10 can be used to set the required VDSLVL voltage using a resistor divider from a
voltage source to establish an overcurrent limit given the RDS,on of the MOSFETs used:
VVDSLVL = IOC × Rds on
where:
•
•
•
•
•
(9)
R1
Vin
R2 = VVDSLVL − 1
(10)
VVDSLVL = VDSLVL voltage
IOCP = VDS overcurrent limit
RDS,on = MOSFET on-resistance
VIN = voltage source for VDSLVL voltage divider
R1/R2 = resistor ratio for setting VDSLVL
For example, if a resistor divider from AVDD is used to set an overcurrent trip threshold of 30-A and the
MOSFET RDS(ON) = 10mΩ, then VDSLVL = 0.3V.
In some applications, there will be a difference between battery voltage (VBAT) to directly drive motor power
and PVDD voltage to power the DRV8328. Because high-side VDS monitoring is referenced from PVDD-SHx,
VDSLVL needs to be selected appropriately to accommodate for the difference in VBAT and PVDD.
Equation 11 helps select an appropriate VDSLVL if there is a difference between PVDD and VDSLVL:
VDSLVL = VBAT − PVDD + IOC*RDS ON
(11)
For instance, if VBAT = 24.0 V, PVDD = 23.3 V, Rdson = 10-mΩ, and I_OC = 30-A, then VDSLVL should equal
1.0V to detect a 30-A overcurrent event across the high-side FET and a 100-A overcurrent event across the
low-side FET.
9.2.1.1.8 AVDD Power Losses
An integrated LDO
in the DRV8328C and DRV8328D
can supply 3.3-V (up to 80-mA) as power rails for external ICs or supply the pullup voltages for resistors and
switches. The power loss from AVDD with respect to PVDD, AVDD voltage, and AVDD current is PAVDD = (VPVDD
- VAVDD) x IAVDD.
Higher power losses occur due larger dropout from PVDD to 3.3 V or increased AVDD load current.
9.2.1.1.9 Power Dissipation and Junction Temperature Losses
To calculate the junction temperature of the DRV8328 from power losses, use Equation 12. Note that the thermal
resistance θJA depends on PCB configurations such as the ambient temperature, numbers of PCB layers,
copper thickness on top and bottom layers, and the PCB area.
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℃
T J ℃ = Ploss W × θ JA W
+ TA ℃
(12)
The table below shows summary of equations for calculating each loss in the DRV8328.
Table 9-3. DRV8328 Power Losses
Loss type
Equation
Standby power
Pstandby = VPVDD x IPVDDS
GVDD CP mode (PVDD < 18V)
PLDO = 2 x VPVDD x IGVDD - VGVDD x IGVDD
GVDD LDO mode (PVDD > 18V)
PLDO = (VPVDD - VGVDD) x IGVDD
AVDD LDO
PLDO = (VPVDD - VAVDD) x IAVDD
9.2.2 Application Curves
Figure 9-8. Device Powerup with PVDD
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Figure 9-9. Device Powerup with nSLEEP
Figure 9-10. GVDD voltage threshold (PVDD = 4.5 V)
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Figure 9-11. GVDD voltage threshold (PVDD = 20V)
Figure 9-12. AVDD powerup
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Figure 9-13. DRVOFF operation
Figure 9-14. Driver operation at 100% duty cycle
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Figure 9-15. Driver PWM operation, 20 kHz, 50% duty cycle, zoomed
Figure 9-16. Driver dead time of 100 ns (DT = 10 kΩ to GND)
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Figure 9-17. Driver dead time of 2000 ns (DT = 390 kΩ to GND)
Figure 9-18. Current sense amplifier operation (GAIN = 40 V/V)
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10 Power Supply Recommendations
The DRV8328 family of devices is designed to operate from an input voltage supply (PVDD) range from 4.5
V to 60 V. A 10-µF and 0.1-µF ceramic capacitor rated for PVDD must be placed as close to the device as
possible. In addition, a bulk capacitor must be included on the PVDD pin but can be shared with the bulk bypass
capacitance for the external power MOSFETs. Additional bulk capacitance is required to bypass the external
half-bridge MOSFETs and should be sized according to the application requirements.
10.1 Bulk Capacitance Sizing
Having appropriate local bulk capacitance is an important factor in motor drive system design. It is generally
beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size. The
amount of local capacitance depends on a variety of factors including:
• The highest current required by the motor system
• The power supply's type, capacitance, and ability to source current
• The amount of parasitic inductance between the power supply and motor system
• The acceptable supply voltage ripple
• Type of motor (brushed DC, brushless DC, stepper)
• The motor startup and braking methods
The inductance between the power supply and motor drive system will limit the rate current can change from the
power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands
or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage
remains stable and high current can be quickly supplied.
The data sheet provides a recommended minimum value, but system level testing is required to determine the
appropriate sized bulk capacitor.
Parasitic Wire
Inductance
Motor Drive System
Power Supply
VM
+
+
Motor Driver
±
GND
Local
Bulk Capacitor
IC Bypass
Capacitor
Figure 10-1. Motor Drive Supply Parasitics Example
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11 Layout
11.1 Layout Guidelines
Bypass the PVDD pin to the PGND pin using a low-ESR ceramic bypass capacitor with a recommended value of
0.1 µF. Place this capacitor as close to the PVDD pin as possible with a thick trace or ground plane connected to
the PGND pin. Additionally, bypass the PVDD pin using a bulk capacitor rated for PVDD. This component can be
electrolytic. This capacitance must be at least 10 µF.
Additional bulk capacitance is required to bypass the high current path on the external MOSFETs. This bulk
capacitance should be placed such that it minimizes the length of any high current paths through the external
MOSFETs. The connecting metal traces should be as wide as possible, with numerous vias connecting PCB
layers. These practices minimize inductance and let the bulk capacitor deliver high current.
Place a low-ESR ceramic capacitor between the CPL and CPH pins. This capacitor should be 470 nF, rated for
PVDD, and be of type X5R or X7R.
The bootstrap capacitors (BSTx-SHx) should be placed closely to device pins to minimize loop inductance for
the gate drive paths.
The dead time resistor (RDT) should be placed as close as possible to the DT pin.
Bypass the AVDD pin to the AGND pin with a 1-µF low-ESR ceramic capacitor rated for 6.3 V and of type X5R or
X7R. Place this capacitor as close to the pin as possible and minimize the path from the capacitor to the AGND
pin.
Minimize the loop length for the high-side and low-side gate drivers. The high-side loop is from the GHx pin of
the device to the high-side power MOSFET gate, then follows the high-side MOSFET source back to the SHx
pin. The low-side loop is from the GLx pin of the device to the low-side power MOSFET gate, then follows the
low-side MOSFET source back to the PGND pin.
When designing higher power systems, physics in the PCB layout can cause parasitic inductances,
capacitances, and impedances that deter the performance of the system as shown in Figure 11-1.
Understanding the parasitics that are present in a higher power motor drive system can help designers mitigate
their effects through good PCB layout. For more information, please visit the System Design Considerations for
High-Power Motor Driver Applications and Best Practices for Board Layout of Motor Drivers application notes.
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LP
PVDD
LP
PVDD
RP
CP
GVDD
INHx
LP
RGATE
GHx
HS
CBULK
LP
ESL ESR
HS
LP
LP
SHx
RSNUB
CSNUB
PHASE
LP
CP
CSNUB
GVDD
INLx
LS
GLx
LSS
LP
RGATE
LP
LS
LP
RPDIFF
RSNUB
LP
LP
SNx
CP
LP
Figure 11-1. Parasitics in the PCB of a BLDC motor driver powerstage
Gate drive traces (BSTx, GHx, SHx, GLx, LSS) should be at least 15-20mil wide and as short as possible to the
MOSFET gates to minimize parasitic inductances and impedances. This helps supply large gate drive currents,
turn MOSFETs on efficiently, and improves VGS and VDS monitoring. If a shunt resistor is used to monitor the
low-side current from LSS to GND, ensure the shunt resistor selected is wide to minimize inductance introduced
at the low-side source LSS.
TI recommends connecting all non-power stage circuitry (including the thermal pad) to GND to reduce parasitic
effects and improve power dissipation from the device. Ensure grounds are connected through net-ties or wide
resistors to reduce voltage offsets and maintain gate driver performance.
The device thermal pad should be soldered to the PCB top-layer ground plane. Multiple vias should be used to
connect to a large bottom-layer ground plane. The use of large metal planes and multiple vias helps dissipate
the heat that is generated in the device.
To improve thermal performance, maximize the ground area that is connected to the thermal pad ground across
all possible layers of the PCB. Using thick copper pours can lower the junction-to-air thermal resistance and
improve thermal dissipation from the die surface.
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11.2 Layout Example
DRV8328 Layout
Figure 11-2. Layout of DRV8328 device
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Power Stage Layout
Figure 11-3. Layout of inverter power stage
11.3 Thermal Considerations
The DRV8328 has thermal shutdown (TSD) to protect against overtemperature. A die temperature in excess of
150°C (minimally) disables the device until the temperature drops to a safe level.
Any tendency of the device to enter thermal shutdown is an indication of excessive power dissipation, insufficient
heatsinking, or too high an ambient temperature.
11.3.1 Power Dissipation
The DRV8328 integrates a variety of circuits that contribute to total power losses. These power losses include
standby power losses, GVDD power losses, and AVDD power losses.
At start-up and fault conditions, this current is much higher than normal running current; remember to take these
peak currents and their duration into consideration.
The maximum amount of power that the device can dissipate depends on ambient temperature and heatsinking.
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Device Nomenclature
The following figure shows a legend for interpreting the complete device name:
12.2 Documentation Support
12.2.1 Related Documentation
•
•
•
•
•
•
•
•
•
Refer to the application note Power Delivery in Cordless Power Tools Using DRV8329
Refer to the application note System Design Considerations for High-Power Motor Driver Applications
Refer to the E2E FAQ How to Conduct a BLDC Schematic Review and Debug
Refer to the application note Best Practices for Board Layout of Motor Drivers
Refer to the application note QFN and SON PCB Attachment
Refer to the application note Cut-Off Switch in High-Current Motor-Drive Applications
Refer to the application note Hardware design considerations for an efficient vacuum cleaner using a BLDC
motor
Refer to the application note Hardware Design Considerations for an Electric Bicycle Using a BLDC Motor
Refer to the application note Sensored 3-Phase BLDC Motor Control Using MSP430
12.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
12.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.5 Community Resources
12.6 Trademarks
All trademarks are the property of their respective owners.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
REE0036A
WQFN - 0.8 mm max height
SCALE 3.300
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
A
B
PIN 1 INDEX AREA
5.1
4.9
C
0.8 MAX
SEATING PLANE
0.05
0.00
0.08
2X 2.8
2.8
2.6
(0.1) TYP
11
18
4X (0.41)
32X 0.4
19
10
2X
3.6
SYMM
3.8
3.6
1
28
36X
PIN 1 ID
36
29
SYMM
36X
0.5
0.3
0.25
0.15
0.1
0.05
C A B
4226725/A 04/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
REE0036A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(3.8)
2X (2.8)
(2.7)
29
36
36X (0.6)
32X (0.2)
1
28
32X (0.4)
37
(4.8)
SYMM
(3.7)
2X (3.6)
2X (0.625)
2X (0.975)
10
19
(R0.05) TYP
11
( 0.2) TYP
18
2X (1.1)
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
NON SOLDER MASK
DEFINED
(PREFERRED)
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4226725/A 04/2021
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
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EXAMPLE STENCIL DESIGN
REE0036A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(3.8)
2X (2.8)
6X (1.19)
36
29
36X (0.6)
1
28
36X (0.2)
6X
(1.05)
32X (0.4)
2X (3.6)
SYMM
(4.8)
2X (1.25)
10
19
(R0.05)
TYP
11
18
2X (0.7)
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
75% PRINTED SOLDER COVERAGE BY AREA
SCALE:20X
4226725/A 04/2021
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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PACKAGE OPTION ADDENDUM
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8-Apr-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
DRV8328ARUYR
ACTIVE
WQFN
RUY
28
5000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
DRV
8328A
Samples
DRV8328BRUYR
ACTIVE
WQFN
RUY
28
5000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
DRV
8328B
Samples
DRV8328CRUYR
ACTIVE
WQFN
RUY
28
5000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
DRV
8328C
Samples
DRV8328DRUYR
ACTIVE
WQFN
RUY
28
5000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
DRV
8328D
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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