DRV8411
SLVSGI0B – SEPTEMBER 2022 – REVISED JULY 2023
DRV8411 Dual H-Bridge Motor Driver with Current Regulation
1 Features
3 Description
•
Dual H-bridge motor driver, can drive – One bipolar stepper motor
– One or two brushed DC motors
– Solenoids and other inductive loads
Low ON-resistance: HS + LS = 400 mΩ (Typical,
25°C)
Wide Power Supply Voltage Range
– 1.65 to 11 V
Pin-to-pin compatible with -
The DRV8411 is a dual H-bridge motor driver that can
drive one or two DC brush motors, one stepper motor,
solenoids, or other inductive loads. The tripler charge
pump allows the device to operate down to 1.65 V
to accommodate 1.8-V supply rails and low-battery
conditions. The charge pump integrates all capacitors
and allows for 100% duty cycle operation. The inputs
and outputs can be paralleled to drive high current
brush DC motors with half the RDS(ON).
– DRV8833: 360-mΩ/bridge
– DRV8833C: 1735-mΩ/bridge
– DRV8847: 1000-mΩ/bridge
– DRV8410: 800-mΩ/bridge
– DRV8411A: 400-mΩ/bridge
High output current capability: 4-A Peak
PWM control interface
Supports 1.8-V, 3.3-V, and 5-V logic inputs
Integrated current regulation
Low-power sleep mode
– ≤ 40 nA at VVM = 5 V, TJ = 25°C
Small package and footprint
The device implements current regulation by
comparing an internal refernce voltage to the voltage
on the xISEN pins, which is proportional to motor
current through an external sense resistor. The ability
to limit current can significantly reduce large currents
during motor startup and stall conditions.
•
•
•
•
•
•
•
•
•
•
– 16-pin HTSSOP with PowerPAD™, 5.0×4.4 mm
– 16-pin Thin-SOT with PowerPAD™, 4.2×2.0
mm
– 16-Pin WQFN with PowerPAD™, 3.0×3.0 mm
Integrated protection features
– VM undervoltage lockout (UVLO)
– Auto-retry overcurrent protection (OCP)
– Thermal shutdown (TSD)
– Fault Indication Pin (nFAULT)
A low-power sleep mode achieves ultra-low quiescent
current draw by shutting down most of the
internal circuitry. Internal protection features include
undervoltage, overcurrent, and overtemperature.
The DRV8411 is part of a family of devices which
come in pin-to-pin, scalable RDS(ON) options to
support various loads with minimal design changes.
See Section 5 for information on the devices in this
family. View our full portfolio of brushed motor drivers
on ti.com.
Device Information(1)
PART NUMBER
DRV8411
2 Applications
Battery-Powered Toys
POS Printers
Video Security Cameras
Office Automation Machines
Gaming Machines
Robotics
Electronic Smart Locks
General purpose solenoid loads
(1)
BODY SIZE (NOM)
5.00 mm × 6.40 mm
WQFN (16)
3.00 mm × 3.00 mm
Thin-SOT (16)
4.20 mm × 2.00 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
1.65 V to 11 V
DRV841x
PWM
BDC
Controller
•
•
•
•
•
•
•
•
PACKAGE
HTSSOP (16)
nSLEEP
nFAULT
Stepper
Stepper or
Brushed DC
Motor Driver
BDC
Current Regula on
Protecon
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRV8411
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SLVSGI0B – SEPTEMBER 2022 – REVISED JULY 2023
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison......................................................... 3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information....................................................5
7.5 Electrical Characteristics.............................................6
7.6 Timing Diagrams......................................................... 7
8 Typical Characteristics................................................... 8
9 Detailed Description......................................................10
9.1 Overview................................................................... 10
9.2 Functional Block Diagram......................................... 10
9.3 External Components................................................11
9.4 Feature Description...................................................11
9.5 Device Functional Modes..........................................16
9.6 Pin Diagrams............................................................ 17
10 Application and Implementation................................ 18
10.1 Application Information........................................... 18
11 Power Supply Recommendations..............................35
11.1 Bulk Capacitance.................................................... 35
11.2 Power Supply and Logic Sequencing..................... 35
12 Layout...........................................................................36
12.1 Layout Guidelines................................................... 36
12.2 Layout Example...................................................... 36
13 Device and Documentation Support..........................38
13.1 Documentation Support.......................................... 38
13.2 Receiving Notification of Documentation Updates..38
13.3 Community Resources............................................38
13.4 Trademarks............................................................. 38
14 Mechanical, Packaging, and Orderable
Information.................................................................... 39
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (October 2022) to Revision B (July 2023)
Page
• Update BODY SIZE (NOM) in Device Information table.................................................................................... 1
Changes from Revision * (September 2022) to Revision A (October 2022)
Page
• Change device status from "Advanced Information" to "Production Data."........................................................1
2
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5 Device Comparison
Table 5-1. Device Comparison Table
Device Name
Supply
Voltage (V)
RDS(on)
(mΩ)
Overcurrent
Protection limit
(A)
DRV8410
1.65 to 11
800
2.5
DRV8411
1.65 to 11
400
DRV8411A
1.65 to 11
400
4
Current
Regulation
CurrentSense
Feedback
Direct Pin-to-Pin
Replacement
Pin-to-Pin
Replacement with
Modifications
External Shunt
Resistor
External
Amplifier
DRV8833,
DRV8833C
DRV8847
N/A
DRV8833,
DRV8833C,
DRV8847
Internal current mirror (IPROPI)
GND
BOUT2
5
12
BISEN
6
BOUT1
nFAULT
AISEN
1
VM
AOUT2
2
11
NC
BOUT2
3
7
10
BIN2
BISEN
4
8
9
BIN1
AIN2
13
Thermal
Pad
13
4
12
NC
11
GND
10
VM
9
NC
Thermal
Figure 6-1. PWP or DYZ Package 16-Pin HTSSOP
Top View
Pad
8
AOUT2
BIN2
NC
AIN1
14
14
3
7
AISEN
BIN1
AIN2
nSLEEP
15
15
2
6
AOUT1
nFAULT
AIN1
AOUT1
16
5
1
BOUT1
nSLEEP
16
6 Pin Configuration and Functions
Figure 6-2. RTE Package 16-Pin WQFN Top View
Table 6-1. Pin Functions
PIN
RTE
PWP,
DYZ
TYPE(1)
AIN1
14
16
I
H-bridge control input for full bridge A (AOUT1, AOUT2). See Section 9.4.1. Internal pulldown
resistor.
AIN2
13
15
I
H-bridge control input for full bridge A (AOUT1, AOUT2). See Section 9.4.1. Internal pulldown
resistor.
AISEN
1
3
O
Full bridge A (AOUT1, AOUT2) sense. Connect this pin to a current sense resistor for full bridge
A. Connect this pin to the GND pin if current regulation is not required. See Section 9.4.2.
AOUT1
16
2
O
Bridge A output 1
AOUT2
2
4
O
Bridge A output 2
BIN1
7
9
I
H-bridge control input for full bridge B (BOUT1, BOUT2). See Section 9.4.1. Internal pulldown
resistor.
BIN2
8
10
I
H-bridge control input for full bridge B (BOUT1, BOUT2). See Section 9.4.1. Internal pulldown
resistor.
BISEN
4
6
O
Full bridge B (BOUT1, BOUT2) sense. Connect this pin to a current sense resistor for full bridge
A. Connect this pin to the GND pin if current regulation is not required. See Section 9.4.2.
BOUT1
5
7
O
Bridge B output 1
BOUT2
3
5
O
Bridge B output 2
NAME
DESCRIPTION
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Table 6-1. Pin Functions (continued)
PIN
RTE
PWP,
DYZ
TYPE(1)
11
13
PWR
9, 12
11, 14
—
Not connected
nFAULT
6
8
OD
Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for
open-drain operation. See Section 9.4.3.
nSLEEP
15
1
I
Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. See .
Internal pulldown resistor.
PAD
—
—
—
VM
10
12
PWR
NAME
GND
NC
(1)
4
DESCRIPTION
Device ground. Connect to system ground.
Thermal pad. Connect to system ground.
1.65-V to 11-V power supply input. Connect a 0.1-µF bypass capacitor to ground, as well as
sufficient Bulk Capacitance rated for VM.
PWR = power, I = input, O = output, NC = no connection, OD = open-drain
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7 Specifications
7.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Power supply pin voltage
VM
-0.5
12
V
Power supply transient voltage ramp
VM
0
2
V/µs
Current sense pin voltage
AISEN, BISEN
-0.6
0.6
V
Logic pin voltage
nSLEEP, AIN1, AIN2, BIN1, BIN2
-0.3
5.75
V
Open-drain output pin voltage
nFAULT
0.3
5.75
V
Output pin voltage
AOUT1, AOUT2, BOUT1, BOUT2
-VSD
VVM+VSD
V
Output current
AOUT1, AOUT2, BOUT1, BOUT2
Internally
Limited
Internally
Limited
A
Ambient temperature, TA
–40
125
°C
Junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
UNIT
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
V
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±2000 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±500
V may actually have higher performance.
7.3 Recommended Operating Conditions
over operating temperature range (unless otherwise noted)
MIN
NOM
MAX
Power supply voltage
VM
VIN
Logic input voltage
nSLEEP, AIN1, AIN2, BIN1, BIN2
0
5.5
V
fPWM
PWM frequency
AIN1, AIN2, BIN1, BIN2
0
100
kHz
VOD
Open drain pullup voltage
nFAULT
0
5.5
IOD
Open drain output current
nFAULT
0
5
IOUT (1)
Peak output current
OUTx
0
IOCP,min
A
TA
Operating ambient temperature
–40
125
°C
TJ
Operating junction temperature
–40
150
°C
(1)
1.65
UNIT
VVM
11
V
V
mA
Power dissipation and thermal limits must be observed
7.4 Thermal Information
THERMAL
METRIC(1)
DEVICE
DEVICE
PWP (HTSSOP)
RTE (WQFN)
PINS
PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
45.1
49.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
43.7
50.9
°C/W
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THERMAL METRIC(1)
DEVICE
DEVICE
PWP (HTSSOP)
RTE (WQFN)
PINS
PINS
19.9
23.5
°C/W
UNIT
RθJB
Junction-to-board thermal resistance
ΨJT
Junction-to-top characterization parameter
2.6
1.7
°C/W
ΨJB
Junction-to-board characterization parameter
19.9
23.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
4.9
10.8
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
1.65 V ≤ VVM ≤ 11 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27 °C and VVM = 5 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
4
40
nA
3.5
mA
100
μs
POWER SUPPLIES (VM)
IVMQ
VM sleep mode current
nSLEEP = 0 V, VVM = 5 V, TJ = 27°C
IVM
VM active mode current
xIN1 = 3.3 V, xIN2 = 0 V, VVM = 5 V
tWAKE
Turnon time
Sleep mode to active mode delay
tSLEEP
Turnoff time
Active mode to sleep mode delay
1.6
5
μs
LOGIC-LEVEL INPUTS (nSLEEP, AIN1, AIN2, BIN1, BIN2)
VIL
Input logic low voltage
VIH
Input logic high voltage
VHYS_nSLEEP nSLEEP Input hysteresis
0
0.4
V
1.45
5.5
V
100
mV
50
mV
VHYS_logic
Logic Input hysteresis (except nSLEEP)
IIL
Input logic low current
VxINx = 0 V
IIH,nSLEEP
Input logic high current
VnSLEEP = 5 V
IIH
Input logic high current
VxINx = 5 V
RPD,nSLEEP
Input pulldown resistance
500
kΩ
RPD
Input pulldown resistance
100
kΩ
tDEGLITCH
Input logic deglitch
50
ns
-1
20
1
µA
14
µA
70
µA
OPEN-DRAIN OUTPUTS (nFAULT)
VOL
Output logic low voltage
IOD = 5 mA
IOZ
Output logic high current
VOD = 5 V
-1
0.3
V
1
µA
DRIVER OUTPUTS (AOUT1, AOUT2, BOUT1, BOUT2)
RHS_DS(ON)
High-side MOSFET on resistance
IOUTx = 0.2 A
200
mΩ
RLS_DS(ON)
Low-side MOSFET on resistance
IOUTx = -0.2 A
200
mΩ
VSD
Body diode forward voltage
IOUTx = -0.5 A
1
V
tRISE
Output rise time
VOUTx rising from 10% to 90% of VVM,
VVM = 5 V
100
ns
tFALL
Output fall time
VOUTx falling from 90% to 10% of VVM,
VVM = 5 V
50
ns
tPD
Input to output propagation delay
Input crosses 0.8 V to VOUTx = 0.1×VVM,
IOUTx = 1 A
600
ns
tDEAD
Output dead time
400
ns
CURRENT REGULATION (AISEN, BISEN)
6
VTRIP
xISEN trip voltage
tOFF
Current regulation off time
180
20
µs
tBLANK
Current regulation blanking time
1.8
µs
tDEG
Current regulation deglitch time
1
µs
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200
230
mV
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1.65 V ≤ VVM ≤ 11 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27 °C and VVM = 5 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PROTECTION CIRCUITS
Supply rising
1.6
V
VUVLO
Supply undervoltage lockout (UVLO)
VUVLO_HYS
Supply UVLO hysteresis
Rising to falling threshold
tUVLO
Supply undervoltage deglitch time
VVM falling to OUTx disabled
IOCP
Overcurrent protection trip point
VOCP_ISEN
Overcurrent protection trip point on ISEN
pin
0.6
tOCP
Overcurrent protection deglitch time
4.2
µs
tRETRY
Overcurrent protection retry time
1.6
ms
TTSD
Thermal shutdown temperature
THYS
Thermal shutdown hysteresis
Supply falling
1.3
V
100
mV
10
µs
4
A
153
V
193
18
°C
°C
7.6 Timing Diagrams
xIN1 (V)
tPD
xIN2 (V)
tPD
xOUT1 (V)
tPD
Z
Z
tPD
xOUT2 (V)
Z
Z
90%
90%
xOUTx (V)
10%
10%
tRISE
tFALL
Figure 7-1. Input-to-Output Timing
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8 Typical Characteristics
3
TJ = -40°C
TJ = 27°C
TJ = 85°C
TJ = 125°C
TJ = 150°C
2.8
Active Mode Current (mA)
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
1
2
3
4
5
6
7
VM Supply Voltage (V)
8
9
10
11
Figure 8-1. Active Mode Current
Figure 8-2. Sleep Mode Current
8
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8 Typical Characteristics
350
High-side MOSFET on-resistance (m)
325
300
VVM = 1.65 V
VVM = 3.3 V
VVM = 4.2 V
VVM = 6 V
VVM = 8.4 V
VVM = 11 V
275
250
225
200
175
150
-40
-30
-20
-10
0
10
20
30
40
50
60
70
Temperature (°C)
80
90
100
110
120
130
140
150
100
110
120
130
140
150
Figure 8-3. High-side MOSFET on resistance
350
Low-side MOSFET on resistance (m)
325
300
VVM = 1.65 V
VVM = 3.3 V
VVM = 4.2 V
VVM = 6 V
VVM = 8.4 V
VVM = 11 V
275
250
225
200
175
150
-40
-30
-20
-10
0
10
20
30
40
50
60
70
Temperature (°C)
80
90
Figure 8-4. Low-side MOSFET on resistance
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9 Detailed Description
9.1 Overview
The DRV8411 is a dual H-bridge motor driver for driving two brushed DC motors or one stepper motor from
a 1.65-V to 11-V supply rail. The integrated current regulation feature limits motor current to a predefined
maximum based on xISEN resistors.
Two logic inputs control each H-bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of
400 mΩ (including one high-side and one low-side FET). The input and output pins can be paralleled to support
a single H-bridge driver with half of the RDS(ON) for driving higher currents. A single power input, VM, serves as
both device power and the motor winding bias voltage. The integrated charge pump of the device boosts VM
internally and fully enhances the high-side FETs. Motor speed can be controlled with pulse-width modulation, at
frequencies between 0 to 100 kHz. The device enters a low-power sleep mode by bringing the nSLEEP pin low.
A variety of integrated protection features protect the device in the case of a system fault. These include
undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD).
9.2 Functional Block Diagram
VM
VM
CBULK
10 µF
Charge
Pump
Internal Reference
and Regulators
100 nF
VM
UVLO
AOUT1
AIN1
Gate
Drive
and
OCP
AIN2
From
Microcontroller
BDC
VM
Step
Motor
AOUT2
BIN1
AISEN
ISEN
BIN2
Logic
VM
nSLEEP
BOUT1
VMCU
To
Microcontroller
Gate
Drive
and
OCP
nFAULT
BDC
VM
BOUT2
TSD
BISEN
ISEN
PPAD
10
GND
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9.3 External Components
Table 9-1 lists the recommended values of the external components for the driver.
Table 9-1. DRV8411 External Components
COMPONENT
PIN 1
CVM1
(1)
PIN 2
VM
RECOMMENDED
GND
VM-rated capacitor, 10 µF minimum
0.1-µF, VM rated ceramic capacitor
CVM2
VM
GND
RnFAULT
VEXT(1)
nFAULT
RAISEN
AISEN
GND
Sense resistor, see the Section 9.4.2 for sizing
RBISEN
BISEN
GND
Sense resistor, see the Section 9.4.2 for sizing
Pullup resistor, IOD ≤ 5 mA
VEXT is not a pin on the DRV8411, but a pullup resistor on the VEXT external supply voltage is required for the open-drain output,
nFAULT.
9.4 Feature Description
9.4.1 Bridge Control
The DRV8411 has two identical H-bridge motor drivers. The input pins, AINx and BINx, control the
corresponding outputs, AOUTx and BOUTx, respectively. Table 9-2 shows how the inputs control the H-bridge
outputs.
Table 9-2. H-Bridge Control
nSLEEP
xIN1
xIN2
xOUT1
xOUT2
DESCRIPTION
0
X
X
High-Z
High-Z
Low-power sleep mode
1
0
0
High-Z
High-Z
Coast/ fast decay; H-bridge disabled to High-Z
1
0
1
L
H
Reverse (Current OUT2 → OUT1)
1
1
0
H
L
Forward (Current OUT1 → OUT2)
1
1
1
L
L
Brake; low-side slow decay
The inputs can be set to constant voltages for 100% duty cycle drive, or they can be pulse-width modulated
(PWM) for variable motor speed. When using PWM, switching between driving (forward or reverse) and slowdecay states typically works best. For example, to drive a motor forward with 50% of the maximum RPM, IN1 = 1
and IN2 = 0 during the driving period or PWM "on" time, and IN1 = 1 and IN2 = 1 during the PWM "off" time.
Alternatively, the coast mode (IN1 = 0, IN2 = 0) for fast current decay is also available. To PWM using fast decay,
the PWM signal is applied to one xIN pin while the other is held low, as shown below.
Table 9-3. PWM Control of Motor Speed
xIN1
xIN2
DESCRIPTION
PWM
0
Forward PWM, fast decay
1
PWM
Forward PWM, slow decay
0
PWM
Reverse PWM, fast decay
PWM
1
Reverse PWM, slow decay
Figure 9-1 shows how the motor current flows through the H-bridge. The input pins can be powered before VM is
applied.
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VM
VM
1
1 Forward drive
1 Reverse drive
2 Slow decay (brake)
22 Slow decay (brake)
1
3 High-Z (coast)
OUT1
OUT2
3 High-Z (coast)
OUT1
OUT2
2
2
3
3
Forward
Reverse
Figure 9-1. H-Bridge Current Paths
When an output changes from driving high to driving low, or driving low to driving high, dead time is automatically
inserted to prevent shoot-through. The tDEAD time is the time in the middle when the output is High-Z. If the
output pin is measured during tDEAD, the voltage depends on the direction of current. If the current is leaving the
pin, the voltage is a diode drop below ground. If the current is entering the pin, the voltage is a diode drop above
VM. This diode is the body diode of the high-side or low-side FET.
The propagation delay time (tPD) is measured as the time between an input edge to output change. This time
accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents
noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn
on or turn off times (tRISE and tFALL).
Figure 9-2 below shows the timing of the inputs and outputs of the motor driver.
IN1 (V)
IN2 (V)
OUT1 (V)
tPD
tRISE
tDEAD
tPD
tFALL
tDEAD
tPD
tFALL
tDEAD
tPD
tRISE
tDEAD
OUT2 (V)
Figure 9-2. H-Bridge Timing Diagram
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9.4.1.1 Parallel Bridge Interface
In the parallel bridge interface, the DRV8411 is configured to drive a higher current brushed-DC (BDC) motor by
connecting the driver outputs in parallel to reduce the RDS(ON) by a factor of two. Figure 9-3 shows an example of
how to connect the pins on the device. To use parallel bridge interface operation, connect AIN1 and BIN1 to the
same control signal, IN1, and connect AIN2 and BIN2 to the same control signal, IN2. Similarly, connect AOUT1
and BOUT1 to the same output node, OUT1, and connect AOUT2 and BOUT2 to the same output node, OUT2.
AISEN and BISEN must be connected to the same ground plane.
Current regulation may be used if AISEN and BISEN are connected to the same sense resistor. The voltage of
the xISEN pins will be compared to the internal VTRIP reference (0.2 V) to set the current regulation level.
VM
+
CBULK
10 µF
100 nF
IN1
IN2
VM
DRV841x
AIN1
AIN2
VMCU
AOUT1
AOUT2
BIN1
BIN2
nSLEEP
nFAULT
BDC
nSLEEP
nFAULT
BOUT1
BOUT2
PPAD
GND
NC
NC
OUT1
OUT2
AISEN
BISEN
Figure 9-3. Parallel Mode Connections
This mode can deliver the full functionality of the BDC motor control with all four modes (forward, reverse, coast,
and brake mode). Table 9-4 shows the control interface states in parallel mode.
Table 9-4. Parallel H-Bridge Control
nSLEEP
IN1 (AIN1 &
BIN1)
IN2 (AIN2 &
BIN2)
OUT1
(AOUT1 &
BOUT1
OUT2
(AOUT2 &
BOUT2)
DESCRIPTION
0
X
X
High-Z
High-Z
Low-power sleep mode
1
0
0
High-Z
High-Z
Coast; H-bridge disabled to High-Z
1
0
1
L
H
Reverse (Current OUT2 → OUT1)
1
1
0
H
L
Forward (Current OUT1 → OUT2)
1
1
1
L
L
Brake; low-side slow decay
9.4.2 Current Regulation
The current through the motor windings may be limited, by the current regulation feature of the DRV8411. For
DC motors, current control is used to limit the start-up and stall current of the motor. For stepper motors, current
control is often used when the supply rail rating is higher than the motor voltage rating so the winding current
remains within the motor specification.
The current regulation feature is implemented with a current chopping scheme. The PWM chopping current,
ITRIP, is set by a comparator which compares the voltage across a current sense resistor connected to the xISEN
pins with a reference voltage of 200 mV. Figure 9-4 shows the relevant circuitry for current regulation of a single
H-bridge in DRV8411.
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VM
OCP
VM
VCP, VINT
xOUT1
xIN1
Predrive
DCM
xOUT 2
xIN2
PWM
OCP
xISEN
+
Optional
REF (200mV)
Figure 9-4. Current Regulation Circuit
When the motor current reaches the ITRIP level, the device enforces slow current decay by enabling both
low-side FETs for a duration of tOFF as shown in Figure 9-5.
xINx
tFALL
tRISE
ttPDt
xOUTx (V)
ttBLANKt
ttOFFt
ITRIP
IMOTOR (A)
tDEG
VTRIP
xISEN (V)
Figure 9-5. Current-Regulation Time Periods
After tOFF elapses, the output is re-enabled according to the two inputs for that bridge, xINx. The device drives
current until the motor current reaches the ITRIP level again. The amount of time spent in the drive state depends
on the VM voltage, the back-EMF of the motor, and the inductance of the motor. If the state of the INx control
pins changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the
inputs.
After tOFF elapses, if IOUT is still greater than ITRIP, the H-bridge enters another period of brake/low-side slow
decay for tOFF after a drive time of tBLANK..
The chopping current is calculated in Equation 1.
RSENSE = 0.2 V / ITRIP
(1)
Example: If a 1-Ω sense resistor is used, the chopping current will be 200 mV/1 Ω = 200 mA.
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If current regulation is not required, the xISEN pins should be directly connected to the PCB ground plane.
9.4.3 Protection Circuits
The DRV8411 is fully protected against undervoltage, overcurrent and overtemperature events.
9.4.3.1 Overcurrent Protection (OCP)
An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally.
If this current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable and
the nFAULT pin will assert low. The driver re-enables after the OCP retry period (tRETRY) has passed. nFAULT
becomes high again at this time and normal operation resumes. If the fault condition is still present, the cycle
repeats as shown in Figure 9-6. Please note that only the H-bridge where an overcurrent condition is detected
will be disabled while the other bridge will function normally.
Overshoot due to OCP
deglitch time (tOCP)
IOCP
Motor
Current
tOCP
Time
tRETRY
Figure 9-6. OCP Operation
Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short
to ground, supply, or across the motor winding will all result in an overcurrent shutdown. The xISEN pins also
integrate a separate overcurrent trip threshold specified by VOCP_ISEN for additional protection when the VM
voltage is low or the RSENSE resistance on the xISEN pin is high.
9.4.3.2 Thermal Shutdown (TSD)
If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled and the nFAULT pin asserts
low. Once the die temperature has fallen to a safe level, operation will automatically resume.
Any tendency of the device to enter TSD is an indication of either excessive power dissipation, insufficient
heatsinking, or an ambient temperature outside of the Recommended Operating Conditions.
9.4.3.3 Undervoltage Lockout (UVLO)
Whenever the voltage on the VM pin falls below the UVLO falling threshold voltage, VUVLO, all circuitry in the
device is disabled, the output FETS are disabled, and all internal logic is reset. Normal operation resumes when
the VVM voltage rises above the UVLO rising threshold as shown in Figure 9-7. The nFAULT pin is driven low
during an undervoltage condition and is released after operation starts again.
When VVM is close to 0 V, the internal circuitry may not bias properly, and the open-drain pull-down on the
nFAULT pin may release.
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VUVLO (max) rising
VUVLO (min) rising
VUVLO (max) falling
VUVLO (min) falling
VVM
DEVICE ON
DEVICE OFF
DEVICE ON
nFAULT
Time
Figure 9-7. VM UVLO Operation
9.5 Device Functional Modes
Table 9-5 summarizes the DRV8411 functional modes described in this section.
Table 9-5. Modes of Operation
MODE
CONDITION
H-BRIDGE
INTERNAL CIRCUITS
Active Mode
nSLEEP pin high
Operating
Operating
Low-Power Sleep Mode
nSLEEP pin low
Disabled
Disabled
Fault Mode
Any fault condition met
Disabled
See Table 9-6
9.5.1 Active Mode
After the supply voltage on the VM pin has crossed the undervoltage threshold VUVLO, the nSLEEP pin is high,
and tWAKE has elapsed, the device enters active mode. In this mode, the H-bridge, charge pump, and internal
logic are active and the device is ready to receive inputs.
9.5.2 Low-Power Sleep Mode
The DRV8411 device supports a low power mode to reduce current consumption from the VM pin when the
driver is not active. This mode is entered by setting nSLEEP = logic low and waiting for tSLEEP to elapse.
In sleep mode, the H-bridge, charge pump, internal regulator, and internal logic are disabled and the device
draws minimal current from the supply pin (IVMQ). The device relies on a weak pulldown to ensure all of the
internal MOSFETs remain disabled. If the device is powered up while the nSLEEP pin is low, it immediately
enters sleep mode. After the nSLEEP pin is high for longer than the duration of tWAKE, the device becomes fully
operational.
The following timing diagram shows an example of entering and leaving sleep mode.
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Active Mode
Sleep
Mode
Wakeup
Active Mode
IN1
tSLEEP
tWAKE
IN2
OUT1
Hi-Z
OUT2
Hi-Z
Figure 9-8. Sleep Mode Entry and Wakeup Timing Diagram
9.5.3 Fault Mode
The DRV8411 device enters a fault mode when a fault is encountered. This protects the device and the load on
the outputs. The device behavior in the fault mode is described in Table 9-6 and depends on the fault condition.
The device will leave the fault mode and re-enter the active mode when the recovery condition is met.
Table 9-6. Fault Conditions Summary
FAULT
CONDITION
ERROR REPORT
H-BRIDGE
INTERNAL
CIRCUITS
RECOVERY
VM undervoltage
(UVLO)
VM < VUVLO,falling
nFAULT
Disabled
Disabled
VM > VUVLO,rising
Overcurrent (OCP)
IOUT > IOCP
nFAULT
Disabled
Operating
Automatic retry:
tRETRY
Thermal Shutdown
(TSD)
TJ > TTSD
nFAULT
Disabled
Operating
Automatic: TJ < TTSD
– THYS
9.6 Pin Diagrams
9.6.1 Logic-Level Inputs
Figure 9-9 shows the input structure for the logic-level input pins AIN1, AIN2, BIN1, BIN2, and nSLEEP.
100 k
Figure 9-9. Logic-level input
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10 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
10.1 Application Information
The DRV8411 is used in brushed-DC or stepper motor control as shown in the following applications examples.
10.1.1 Typical Application
The user can configure the DRV8411 for stepper motor, dual BDC, or single BDC motor applications as
described in this section.
10.1.1.1 Stepper Motor Application
Figure 10-1 shows the typical application of the DRV8411 device to drive a stepper motor.
VM
VMCU
DRV841x
AIN1
AIN2
PWM
PWM
PWM
PWM
CBULK
10 µF
Stepper
nSLEEP
VMCU
nFAULT
NC
PPAD
GND
I
+
NC
AOUT1
AOUT2
BIN1
BIN2
O
Microcontroller
(MCU)
VM
100 nF
BOUT1
BOUT2
AISEN
BISEN
RSENSE_B
RSENSE_A
Figure 10-1. Typical Application Schematic of DRV8411 Driving Stepper Motor
10.1.1.1.1 Design Requirements
Table 10-1 lists design input parameters for system design.
Table 10-1. Design Parameters
DESIGN PARAMETER
REFERENCE
EXAMPLE VALUE
Motor supply voltage
VM
11 V
Motor winding resistance
RL
34 Ω/phase
LL
33 mH/phase
ITRIP
500 mA
Motor winding inductance
Target trip current
10.1.1.1.2 Detailed Design Procedure
10.1.1.1.2.1 Stepper Motor Speed
The first step in configuring the DRV8411 requires the desired motor speed and stepping level. The device can
support full- and half-stepping modes using the PWM interface.
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If the target motor speed is too high, the motor does not spin. Ensure that the motor can support the target
speed.
For a desired motor speed (v), microstepping level (nm), and motor full step angle (θstep),
¦step VWHSV V
v(rpm) u nm steps u 360q / rot
Tstep q / step u 60 s / min
(2)
10.1.1.1.2.2 Current Regulation
The trip current (ITRIP) is the maximum current driven through either winding. This setting determines the amount
of torque the stepper motor will produce when operating in full stepping or half stepping control schemes. For an
ITRIP value of 500 mA, the value of the sense resistor (RSENSE_x) is calculated as shown in Equation 3.
RSENSE_A = RSENSE_B = 0.2 V / ITRIP = 0.2 V / 0.5 A = 400 mΩ
(3)
Select the closest available value of 400 mΩ for the sense resistors.
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10.1.1.1.2.3 Stepping Modes
The DRV8411 is used to drive a stepper motor in full-stepping mode or non-circulating half-stepping mode using
the following bridge configurations:
• Full-stepping mode
• Half-stepping mode with slow decay
• Half-stepping mode with fast decay
10.1.1.1.2.3.1 Full-Stepping Operation
In full-stepping mode, the full-bridge operates in either of two modes (forward or reverse mode) with a phase
shift of 90° between the two windings. Full stepping is simplest stepper control mode to implement in firmware
and offers the best performance at high speeds.
The controller applies the PWM input to the AIN1, AIN2, BIN1, and BIN2 pins as shown in Figure 10-2 and the
driver operates only in forward (FRW) and reverse (REV) mode.
90o
Phase
AIN1
AIN2
BIN1
BIN2
AOUT12 FRW
AOUT12 FRW
AOUT12
AOUT12 REV
AOUT12 REV
BOUT12 FRW
BOUT12 FRW
BOUT12
BOUT12 REV
BOUT12 REV
Time
Figure 10-2. Timing Diagram for Full-Stepping
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10.1.1.1.2.3.2 Half-Stepping Operation with Fast Decay
In half-stepping mode, the full-bridge operates in one of the three modes (forward, reverse, or coast mode)
to position the rotor half-way between two full-step positions. The coast state allows the current in the motor
winding to decay quickly to 0 A. This mode is best-used when half-stepping at high speeds.
The controller applies the PWM input to the AIN1, AIN2, BIN1, and BIN2 pins as shown in Figure 10-3, and the
driver operates in forward, reverse, and coast mode.
45o
Phase
AIN1
AIN2
BIN1
COAST
AOUT12 FRW
COAST
COAST
AOUT12 FRW
COAST
COAST
BIN2
AOUT12
AOUT12 REV
AOUT12 REV
BOUT12 FRW
BOUT12 FRW
COAST
BOUT12 REV
COAST
COAST
COAST
BOUT12
BOUT12 REV
Time
Figure 10-3. Timing Diagram for Half-Stepping with Fast Decay
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10.1.1.1.2.3.3 Half-Stepping Operation with Slow Decay
In this half-stepping mode, the driver achieves the 0-A state using the slow decay control state (known as
"brake mode" for BDC driving). Therefore, the full-bridge operates in one of the three modes (forward, reverse,
or brake/slow-decay mode) to position the rotor half-way between two full-step positions. The slow decay state
allows the current in the motor winding to decay slowly to 0 A. This mode is best-used when half-stepping at
slow speeds and may help to reduce stepper noise and vibration.
The controller applies the PWM input to the AIN1, AIN2, BIN1, and BIN2 pins as shown in Figure 10-4, and the
driver operates in forward, reverse, and brake mode.
45o
Phase
AIN1
AIN2
BIN1
BRAKE
AOUT12 FRW
BRAKE
BRAKE
AOUT12 FRW
BRAKE
BRAKE
BIN2
AOUT12
AOUT12 REV
AOUT12 REV
BOUT12 FRW
BOUT12 FRW
BRAKE
BOUT12 REV
BRAKE
BRAKE
BRAKE
BOUT12
BOUT12 REV
Time
Figure 10-4. Timing Diagram for Half-Stepping with Slow Decay
10.1.1.1.3 Application Curves
Ch 1 = AIN1, Ch 2 = AIN2, Ch 3 = BIN1, Ch 4 = BIN2, Ch 5 = AOUT12, Ch 6 = BOUT12, Ch 7 = AOUT12
current, Ch 8 = BOUT12 current
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Figure 10-5. Stepper Motor Full-Step Operation
Figure 10-6. Stepper Motor Half-Step Operation With Fast Decay
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Figure 10-7. Stepper Motor Half-Step Operation With Slow Decay
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10.1.1.2 Dual BDC Motor Application
Figure 10-8 shows the typical application of DRV8411 to drive two BDC motors.
VM
VMCU
100 nF
PWM
PWM
BIN1
BIN2
O
NC
AOUT1
CBULK
10 µF
BDC
AOUT2
nSLEEP
BOUT1
VMCU
BDC
BOUT2
PPAD
GND
Microcontroller
(MCU)
I
VM
DRV841x
AIN1
AIN2
PWM
PWM
+
nFAULT
NC
AISEN
BISEN
RSENSE_B
RSENSE_A
Figure 10-8. Typical Application Schematic of Device Driving Two BDC Motors
10.1.1.2.1 Design Requirements
Table 10-2 lists the design input parameters for system design.
Table 10-2. Design Parameters
REFERENCE
EXAMPLE VALUE
Motor supply voltage
DESIGN PARAMETER
VM
7V
Motor winding resistance
RL
7.8 Ω
Motor winding inductance
LL
500 µH
IRMS
600 mA
ISTART
900 mA
Motor RMS current
Motor start-up current
Target trip current
ITRIP
1A
Trip current reference voltage (internal voltage)
VTRIP
200 mV
10.1.1.2.2 Detailed Design Procedure
10.1.1.2.2.1 Motor Voltage
The motor voltage used in an application depends on the rating of the selected motor and the desired revolutions
per minute (RPM). A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied
to the power FETs. A higher voltage also increases the rate of current change through the inductive motor
windings.
10.1.1.2.2.2 Current Regulation
The trip current (ITRIP) is the maximum current driven through either winding. Because the peak current (start
current) of the motor is 900 mA, the ITRIP current level is selected to be just greater than the peak current. The
selected ITRIP value for this example is 1 A. Therefore, use Equation 4 to select the value of the sense resistors
(RSENSE_A and RSENSE_B) connected to the AISEN and BISEN pins.
RSENSE_A = RSENSE_B = 0.2 V / ITRIP = 0.2 V / 1 A = 200 mΩ
(4)
10.1.1.2.2.3 Sense Resistor
For optimal performance, the sense resistor must:
•
Be a surface mount component
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•
•
•
Have low inductance
Be rated for high enough power
Be placed closely to the motor driver
The power dissipated by the sense resistor equals IRMS 2 × R. In this example, the peak current is 900 mA, the
RMS motor current is 600 mA, and the sense resistor value is 200 mΩ. Therefore, the sense resistors (RSENSE12
and RSENSE34) dissipate 72 mW (600 mA2 × 200 mΩ = 72 mW). The power quickly increases with higher current
levels.
Resistors typically have a rated power within some ambient temperature range, along with a derated power
curve for high ambient temperatures. When a printed circuit board (PCB) is shared with other components
generating heat, margin should be added. For best practice, measure the actual sense resistor temperature in a
final system, along with the power MOSFETs, because those components are often the hottest.
Because power resistors are larger and more expensive than standard resistors, the common practice is to use
multiple standard resistors in parallel, between the sense node and ground. This practice distributes the current
and heat dissipation.
10.1.1.2.3 Application Curves
Ch 1 = AOUT2, Ch 2 = BIN2, Ch 3 = AIN1, Ch 4 = BOUT1, Ch 6 = AIN2, Ch 7 = AOUT12 current, Ch M7 =
BOUT12 current
Figure 10-9. No Current Regulation
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Figure 10-10. Current Regulation
10.1.1.3 Thermal Considerations
10.1.1.3.1 Maximum Output Current
In actual operation, the maximum output current achievable with a motor driver is a function of die temperature.
This, in turn, is greatly affected by ambient temperature and PCB design. Basically, the maximum motor current
will be the amount of current that results in a power dissipation level that, along with the thermal resistance of the
package and PCB, keeps the die at a low enough temperature to stay out of thermal shutdown.
The dissipation ratings given in the data sheet can be used as a guide to calculate the approximate maximum
power dissipation that can be expected to be possible without entering thermal shutdown for several different
PCB constructions. However, for accurate data, the actual PCB design must be analyzed through measurement
or thermal simulation.
10.1.1.3.2 Power Dissipation
Power dissipation in the device is dominated by the DC power dissipated in the output FET resistance, or
RDS(ON). There is additional power dissipated due to PWM switching losses, which are dependent on PWM
frequency, rise and fall times, and VM supply voltages.
The DC power dissipation of one H-bridge can be roughly estimated by Equation 5.
3TOT
+6 ± 5DS(ON) u ,OUT(RMS)2
/6 ± 5DS(ON) u ,OUT(RMS)2
(5)
where
•
•
•
•
PTOT is the total power dissipation
HS - RDS(ON) is the resistance of the high-side FET
LS - RDS(ON) is the resistance of the low-side FET
IOUT(RMS) is the RMS output current being applied to the motor
RDS(ON) increases with temperature, so as the device heats, the power dissipation increases. This must be taken
into consideration when estimating the maximum output current.
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10.1.1.3.3 Thermal Performance
The datasheet-specified junction-to-ambient thermal resistance, RθJA, is primarily useful for comparing various
drivers or approximating thermal performance. However, the actual system performance may be better or worse
than this value depending on PCB stackup, routing, number of vias, and copper area around the thermal
pad. The length of time the driver drives a particular current will also impact power dissipation and thermal
performance. This section considers how to design for steady-state and transient thermal conditions.
The data in this section was simulated using the following criteria:
HTSSOP (PWP package)
•
•
2-layer PCB (size 114.3 x 76.2 x 1.6 mm), standard FR4, 1-oz (35 mm copper thickness) or 2-oz copper
thickness. Thermal vias are only present under the thermal pad (12 vias in 4 x 3 array, 1 mm pitch, 0.2 mm
diameter, 0.025 mm Cu plating).
– Top layer: HTSSOP package footprint and copper plane heatsink. Top layer copper area is varied in
simulation.
– Bottom layer: ground plane thermally connected through vias under the thermal pad for the driver. Bottom
layer copper area varies with top copper area.
4-layer PCB (size 114.3 x 76.2 x 1.6 mm), standard FR4. Outer planes are 1-oz (35 mm copper thickness)
or 2-oz copper thickness. Inner planes are kept at 1-oz. Thermal vias are only present under the thermal pad
(12 vias in 4 x 3 array, 1 mm pitch, 0.2 mm diameter, 0.025 mm Cu plating).
– Top layer: HTSSOP package footprint and copper plane heatsink. Top layer copper area is varied in
simulation.
– Mid layer 1: GND plane thermally connected to thermal pad through vias. The area of the ground plane is
74.2 mm x 74.2 mm.
– Mid layer 2: power plane, no thermal connection. The area of the power plane is 74.2 mm x 74.2 mm.
– Bottom layer: signal layer with small copper pad underneath the driver and thermally connected through
via stitching from the TOP and internal GND plane. Bottom layer thermal pad is the same size as the
package (5 mm x 4.4 mm). Bottom pad size remains constant as top copper plane is varied.
Figure 10-11 shows an example of the simulated board for the HTSSOP package. Table 10-3 shows the
dimensions of the board that were varied for each simulation.
Figure 10-11. HTSSOP PCB model top layer
Table 10-3. Dimension A for 16-pin PWP package
28
Cu area (cm2)
Dimension A (mm)
2
16.43
4
22.23
8
30.59
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Table 10-3. Dimension A for 16-pin PWP package (continued)
Cu area (cm2)
Dimension A (mm)
16
42.37
WQFN (RTE package)
•
•
2-layer PCB (size 114.3 x 76.2 x 1.6 mm), standard FR4, 1-oz (35 mm copper thickness) or 2-oz copper
thickness. Thermal vias are only present under the package footprint (5 vias, 1 mm pitch, 0.2 mm diameter,
0.025 mm Cu plating).
– Top layer: WQFN package footprint and traces.
– Bottom layer: ground plane thermally connected through vias under the package footprint. Bottom layer
copper area is varied in simulation.
4-layer PCB (size 114.3 x 76.2 x 1.6 mm), standard FR4. Outer planes are 1-oz (35 mm copper thickness)
or 2-oz copper thickness. Inner planes are kept at 1-oz. Thermal vias are only present under the package
footprint (5 vias, 1 mm pitch, 0.2 mm diameter, 0.025 mm Cu plating).
– Top layer: WQFN package footprint and traces.
– Mid layer 1: GND plane thermally connected under package footprint through vias. The area of the ground
plane is 74.2 mm x 74.2 mm.
– Mid layer 2: power plane, no thermal connection. The area of the power plane is 74.2 mm x 74.2 mm.
– Bottom layer: signal layer with small copper pad underneath the driver and thermally connected through
via stitching from the TOP and internal GND plane. Bottom layer thermal pad is 1.55 mm x 1.55 mm.
Bottom layer thermal pad is the same size as the package (3 mm x 3 mm). Bottom pad size remains
constant.
Figure 10-12 shows an example of the simulated board for the HTSSOP package. Table 10-4 shows the
dimensions of the board that were varied for each simulation.
Figure 10-12. WQFN PCB model top layer
Table 10-4. Dimension A for 16-pin RTE package
Cu area (cm2)
Dimension A (mm)
2
14.14
4
20.00
8
28.28
16
40.00
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10.1.1.3.3.1 Steady-State Thermal Performance
"Steady-state" conditions assume that the motor driver operates with a constant RMS current over a long
period of time. The figures in this section show how RθJA and ΨJB (junction-to-board characterization parameter)
change depending on copper area, copper thickness, and number of layers of the PCB. More copper area, more
layers, and thicker copper planes decrease RθJA and ΨJB, which indicate better thermal performance from the
PCB layout.
90
4 layer, 2 oz
4 layer, 1 oz
2 layer, 2 oz
2 layer, 1 oz
80
RJA (C/W)
70
60
50
40
30
20
2
4
6
8
10
Copper area (cm2)
12
14
16
Figure 10-13. HTSSOP, PCB junction-to-ambient thermal resistance vs copper area
17
4 layer, 2 oz
4 layer, 1 oz
2 layer, 2 oz
2 layer, 1 oz
16
JB (C/W)
15
14
13
12
11
2
4
6
8
10
Copper area (cm2)
12
14
16
Figure 10-14. HTSSOP, junction-to-board characterization parameter vs copper area
30
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120
2 layer, 2 oz
2 layer, 1 oz
115
110
RJA (C/W)
105
100
95
90
85
80
75
70
2
4
6
8
10
Bottom layer copper area (cm2)
12
14
16
Figure 10-15. WQFN, PCB junction-to-ambient thermal resistance vs copper area
34.5
2 layer, 2 oz
2 layer, 1 oz
34
33.5
33
JB (C/W)
32.5
32
31.5
31
30.5
30
29.5
29
28.5
2
4
6
8
10
Bottom layer copper area (cm2)
12
14
16
Figure 10-16. WQFN, junction-to-board characterization parameter vs copper area
10.1.1.3.3.2 Transient Thermal Performance
The motor driver may experience different transient driving conditions that cause large currents to flow for a
short duration of time. These may include •
•
•
Motor start-up when the rotor is initially stationary.
Fault conditions when there is a supply or ground short to one of the motor outputs, and the overcurrent
protection triggers.
Briefly energizing a motor or solenoid for a limited time, then de-energizing.
For these transient cases, the duration of drive time is another factor that impacts thermal performance in
addition to copper area and thickness. In transient cases, the thermal impedance parameter ZθJA denotes the
junction-to-ambient thermal performance. The figures in this section show the simulated thermal impedances for
1-oz and 2-oz copper layouts for the HTSSOP and WQFN packages. These graphs indicate better thermal
performance with short current pulses. For short periods of drive time, the device die size and package
dominates the thermal performance. For longer drive pulses, board layout has a more significant impact on
thermal performance. Both graphs show the curves for thermal impedance split due to number of layers and
copper area as the duration of the drive pulse duration increases. Long pulses can be considered steady-state
performance.
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100
70
50
40
30
2 layer, 4 cm2
4 layer, 4 cm2
2 layer, 8 cm2
4 layer, 8 cm2
2 layer, 16 cm2
4 layer, 16 cm2
ZJA (C/W)
20
10
7
5
4
3
2
1
0.001 0.002
0.005 0.01
0.02
0.05
0.1
0.2 0.3 0.50.7 1
2 3 4 5 6 78 10
Pulse duration (s)
20 30
50 70 100
200300 500
1000
Figure 10-17. HTSSOP package junction-to-ambient thermal impedance for 1-oz copper layouts
100
70
50
40
30
2 layer, 4 cm2
4 layer, 4 cm2
2 layer, 8 cm2
4 layer, 8 cm2
2 layer, 16 cm2
4 layer, 16 cm2
ZJA (C/W)
20
10
7
5
4
3
2
1
0.001 0.002
0.005 0.01
0.02
0.05
0.1
0.2 0.3 0.50.7 1
2 3 4 5 6 78 10
Pulse duration (s)
20 30
50 70 100
200300 500
1000
Figure 10-18. HTSSOP package junction-to-ambient thermal impedance for 2-oz copper layouts
200
100
2 layer, 4 cm2
2 layer, 8 cm2
2 layer, 16 cm2
70
ZJA (C/W)
50
40
30
20
10
7
5
4
3
2
1
0.001 0.002
0.005 0.01
0.02
0.05
0.1
0.2 0.3 0.50.7 1
2 3 4 5 6 78 10
Pulse duration (s)
20 30
50 70 100
200300 500
1000
Figure 10-19. WQFN package junction-to-ambient thermal impedance for 1-oz copper layouts
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100
70
50
40
2 layer, 4 cm2
2 layer, 8 cm2
2 layer, 16 cm2
30
ZJA (C/W)
20
10
7
5
4
3
2
1
0.001 0.002
0.005 0.01
0.02
0.05
0.1
0.2 0.3 0.50.7 1
2 3 4 5 6 78 10
Pulse duration (s)
20 30
50 70 100
200300 500
1000
Figure 10-20. WQFN package junction-to-ambient thermal impedance for 2-oz copper layouts
10.1.1.4 Multi-Sourcing with Standard Motor Driver Pinout
The devices come in industry standard package footprints in the PWP and RTE packages.
As shown in Section 5, the DRV8410/11/11A devices are pin-to-pin compatible with the DRV8833 and
DRV8833C. Many drivers from other suppliers have footprints similar to DRV8833 and DRV8833C.
•
•
•
•
When replacing a device similar to DRV8833, user should remove the capacitors for the internal regulator
(VINT) and the charge pump (VCP) by setting them as DNP (do not place) in the design files.
The internal voltage reference for current regulation is 200 mV, just like the DRV8833 and DRV8833C.
Because the voltage reference is the same, the system can still use the same xISEN resistor values designed
for DRV8833 or other second source drivers with the same pinout.
DRV841xPWP can use the same footprint as DRV8833 and DRV8833C in the HTSSOP package as shown
in Figure 10-21 and Figure 10-22.
DRV841xRTE are only footprint compatible with DRV8833C and other suppliers in the 3 mm x 3 mm QFN
package.
DRV8833
nSLEEP
AOUT1
RAISEN
RBISEN
1
16
AIN1
2
15
AIN2
AISEN
3
14
VINT
AOUT2
4
13
GND
BOUT2
5
12
VM
BISEN
6
11
VCP
BOUT1
7
10
BIN2
nFAULT
8
9
BIN1
Thermal
Pad
100 nF
GND
CBULK
VMCU
GND
Figure 10-21. DRV8833 Layout Example
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DRV8410/1
nSLEEP
AOUT1
RAISEN
RBISEN
1
16
AIN1
2
15
AIN2
AISEN
3
14
NC
AOUT2
4
13
GND
BOUT2
5
12
VM
BISEN
6
11
NC
BOUT1
7
10
BIN2
nFAULT
8
9
BIN1
Thermal
Pad
DNP
100 nF
GND
DNP
CBULK
VMCU
GND
Figure 10-22. DRV8410/1 Footprint Compatible Layout Example
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11 Power Supply Recommendations
11.1 Bulk Capacitance
Having an appropriate local bulk capacitance is an important factor in motor drive system design. It is generally
beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size.
The amount of local capacitance needed depends on a variety of factors, including:
• The highest current required by the motor system
• The capacitance and ability to source current
• The amount of parasitic inductance between the power supply and motor system
• The acceptable voltage ripple
• The type of motor used (brushed DC, brushless DC, stepper)
• The motor braking method
The inductance between the power supply and the motor drive system limits the rate current can change from
the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands
or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage
remains stable and high current can be quickly supplied.
The data sheet generally provides a recommended value, but system-level testing is required to determine the
appropriate sized bulk capacitor.
Power Supply
Parasitic Wire
Inductance
Motor Drive System
VM
+
+
±
Motor
Driver
GND
Local
Bulk Capacitor
IC Bypass
Capacitor
Figure 11-1. Example Setup of Motor Drive System With External Power Supply
The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases
when the motor transfers energy to the supply.
11.2 Power Supply and Logic Sequencing
There is no specific sequence for powering up the DRV8411. The presence of digital input signals is acceptable
before VM is applied. After VM is applied to the DRV8411, the device begins operation based on the status of
the control pins.
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12 Layout
12.1 Layout Guidelines
Since the DRV8411 device has integrated power MOSFETs capable of driving high current, careful attention
should be paid to the layout design and external component placement. Some design and layout guidelines
are provided below. For more information on layout recommendations, please see the application note Best
Practices for Board Layout of Motor Drivers.
•
•
•
•
•
•
•
Low ESR ceramic capacitors should be utilized for the VM-to-GND. X5R and X7R types are recommended.
The VM power supply capacitor should be placed as close to the device as possible to minimize the loop
inductance.
The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as
close as possible to the device to minimize the loop inductance.
VM, xOUTx, and GND pins carry the high current from the power supply to the outputs and back to ground.
Thick metal routing should be utilized for these traces as is feasible.
GND should connect directly on the PCB ground plane.
The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane
(when available) through thermal vias to maximize the PCB heat sinking.
The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking.
12.2 Layout Example
nSLEEP
RAISEN
RBISEN
1
16
AOUT1
2
15
AISEN
3
14
NC
AOUT2
4
13
GND
BOUT2
5
12
VM
BISEN
6
11
NC
BOUT1
7
10
BIN2
nFAULT
8
9
BIN1
Thermal
Pad
AIN1
AIN2
100 nF
GND
CBULK
VMCU
GND
Figure 12-1. Recommended Layout Example for PWP (HTSSOP) and DYZ (Thin-SOT) Package
36
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nSLEEP
AIN1
AIN2
14
13
16
GND
15
AOUT1
SLVSGI0B – SEPTEMBER 2022 – REVISED JULY 2023
GND
AISEN
1
12
NC
AOUT2
2
Thermal
11
GND
BOUT2
3
Pad
10
VM
BISEN
4
9
NC
RAISEN
7
8
BIN2
6
nFAULT
BIN1
5
GND
BOUT1
RBISEN
100 nF
GND
CBULK
GND
VMCU
Figure 12-2. Recommended Layout Example for RTE (WQFN) Package
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Calculating Motor Driver Power Dissipation application report
• Texas Instruments, PowerPAD™ Made Easy application report application report
• Texas Instruments, PowerPAD™ Thermally Enhanced Package application report
• Texas Instruments, Understanding Motor Driver Current Ratings application report
• Texas Instruments, Best Practices for Board Layout of Motor Drivers application report
13.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Subscribe to updates to register and receive a weekly digest of any product information that
has changed. For change details, review the revision history included in any revised document.
13.3 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.4 Trademarks
All trademarks are the property of their respective owners.
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14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
PWP0016-C01
TM
PowerPAD TSSOP - 1.2 mm max height
SCALE 2.500
SMALL OUTLINE PACKAGE
6.6
TYP
6.2
A
C
PIN 1 INDEX
AREA
0.1 C
SEATING
PLANE
14X 0.65
16
1
2X
5.1
4.9
NOTE 3
4.55
8
9
4.5
4.3
B
16X
SEE DETAIL A
0.30
0.19
0.1
C A B
ALTERNATE THERMAL PAD DIMENSIONS
OPTION
01
02
(0.15) TYP
2X 0.95 MAX
NOTE 5
DIM A
DIM B
(MAX/MIN)
(MAX/MIN)
2.46/1.75
2.5/1.8
2.31/1.75
2.64/1.94
4X (0.3)
8
9
2X 0.23 MAX
NOTE 5
17
DIM B
0.25
GAGE PLANE
16
1
0 -8
1.2 MAX
0.15
0.05
0.75
0.50
DETAIL A
A 20
THERMAL
PAD
TYPICAL
DIM A
4229315/A 12/2022
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ or may not be present.
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EXAMPLE BOARD LAYOUT
PWP0016-C01
TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(3.4)
NOTE 9
(2.5)
16X (1.5)
METAL COVERED
BY SOLDER MASK
SYMM
1
16X (0.45)
16
(1.2) TYP
(R0.05) TYP
SYMM
(2.64)
17
14X (0.65)
( 0.2) TYP
VIA
(5)
NOTE 9
(0.6)
9
8
SOLDER MASK
DEFINED PAD
(1) TYP
SEE DETAILS
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK DETAILS
SOLDER MASK
DEFINED
15.000
4229315/A 12/2022
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
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EXAMPLE STENCIL DESIGN
PWP0016-C01
TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(2.5)
BASED ON
0.125 THICK
STENCIL
16X (1.5)
1
METAL COVERED
BY SOLDER MASK
16
16X (0.45)
(R0.05) TYP
SYMM
(2.64)
BASED ON
0.125 THICK
STENCIL
17
14X (0.65)
9
8
SYMM
(5.8)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
0.125
0.15
0.175
2.80 X 2.95
2.5 X 2.64 (SHOWN)
2.28 X 2.41
2.11 X 2.23
4229315/A 12/2022
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
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PACKAGE OPTION ADDENDUM
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7-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
DRV8411PWPR
ACTIVE
HTSSOP
PWP
16
3000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
(8411, 8411A)
Samples
DRV8411RTER
ACTIVE
WQFN
RTE
16
5000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
8411
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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