DRV8812PWPR

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents DRV8812 SLVS997G – OCTOBER 2009 – REVISED OCTOBER 2015 DRV8812 Dual-Bridge Motor Controller IC 1 Features 3 Description • • The DRV8812 provides an integrated motor driver solution for printers, scanners, and other automated equipment applications. The device has two H-bridge drivers, and can drive a bipolar stepper motor or two DC motors. The output driver block for each consists of N-channel power MOSFET’s configured as full Hbridges to drive the motor windings. The DRV8812 is capable of driving up to 1.6-A of output current (with proper heatsinking, at 24 V and 25°C). 1 • • • • • • 8.2-V to 45-V Operating Supply Voltage Range 1.6-A Maximum Drive Current at 24 V and TA = 25°C Dual H-Bridge Current Control Motor Driver – Drive a Bipolar Stepper or Two DC Motors – Four Level Winding Current Control Multiple Decay Modes – Mixed Decay – Slow Decay – Fast Decay Industry Standard Parallel Digital Control Interface Low Current Sleep Mode Built In 3.3-V Reference Output Small Package and Footprint Protection Features – Overcurrent Protection (OCP) – Thermal Shutdown (TSD) – VM Undervoltage Lockout (UVLO) – Fault Condition Indication Pin (nFAULT) Internal shutdown functions are provided for over current protection, short circuit protection, under voltage lockout and overtemperature. The DRV8812 is available in a 28-pin HTSSOP package with PowerPAD™ and in a 28-pin QFN package PowerPAD™ (Eco-friendly: RoHS & no Sb/Br). Device Information(1) PART NUMBER DRV8812 2 Applications • • • • • • • • • A simple parallel digital control interface is compatible with industry-standard devices. Decay mode is programmable. PACKAGE BODY SIZE (NOM) HTSSOP (28) 9.70 mm x 4.40 mm VQFN (28) 5.00 mm x 5.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Automatic Teller Machines Money Handling Machines Video Security Cameras Printers Scanners Office Automation Machines Gaming Machines Factory Automation Robotics Simplified Schematic 8.2 V to 45 V M 1.6 A ENBL Decay Mode Stepper Stepper Current Lvl Motor Driver nFAULT Current Control - Controller DRV8812 + PHASE + - 1.6 A 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DRV8812 SLVS997G – OCTOBER 2009 – REVISED OCTOBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 5 6.1 6.2 6.3 6.4 6.5 6.6 5 5 5 5 6 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description .............................................. 8 7.1 7.2 7.3 7.4 Overview ................................................................... 8 Functional Block Diagram ......................................... 8 Feature Description................................................... 9 Device Functional Modes........................................ 10 8 Application and Implementation ........................ 13 8.1 Application Information............................................ 13 8.2 Typical Application ................................................. 13 9 Power Supply Recommendations...................... 16 9.1 Bulk Capacitance .................................................... 16 9.2 Power Supply and Logic Sequencing ..................... 16 10 Layout................................................................... 17 10.1 Layout Guidelines ................................................. 17 10.2 Layout Example .................................................... 17 10.3 Thermal Consideration.......................................... 18 11 Device and Documentation Support ................. 19 11.1 11.2 11.3 11.4 11.5 Third-Party Products Disclaimer ........................... Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 19 19 19 19 19 12 Mechanical, Packaging, and Orderable Information ........................................................... 19 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision F (August 2013) to Revision G • 2 Page Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 5 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: DRV8812 DRV8812 www.ti.com SLVS997G – OCTOBER 2009 – REVISED OCTOBER 2015 5 Pin Configuration and Functions PWP Package 28 Pin HTSSOP Top View CP1 CP2 VCP VMA AOUT1 ISENA AOUT2 BOUT2 ISENB BOUT1 VMB AVREF BVREF GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GND (PPAD) GND BI1 BI0 AI1 AI0 BPHASE BENBL AENBL APHASE DECAY nFAULT nSLEEP nRESET V3P3OUT RHD Package 28-Pin VQFN Top View DECAY APHASE AENBL BENBL BPHASE AI0 AI1 22 23 24 25 26 27 28 BI0 BI1 GND CP1 CP2 VCP VMA 1 21 2 20 3 19 GND (PPAD) 4 18 5 17 6 16 7 15 nFAULT nSLEEP nRESET V3P3OUT GND BVREF AVREF 14 13 12 11 10 9 8 VMB BOUT1 ISENB BOUT2 AOUT2 ISENA AOUT1 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: DRV8812 3 DRV8812 SLVS997G – OCTOBER 2009 – REVISED OCTOBER 2015 www.ti.com Pin Functions PIN NAME PWP RHD I/O (1) EXTERNAL COMPONENTS OR CONNECTIONS DESCRIPTION POWER AND GROUND GND 14, 28 3, 17 - Device ground VMA 4 7 - Bridge A power supply VMB 11 14 - Bridge B power supply V3P3OUT 15 18 O 3.3-V regulator output CP1 1 4 IO Charge pump flying capacitor CP2 2 5 IO Charge pump flying capacitor VCP 3 6 IO High-side gate drive voltage Connect a 0.1-μF 16-V ceramic capacitor and a 1-MΩ resistor to VM. AENBL 21 24 I Bridge A enable Logic high to enable bridge A APHASE 20 23 I Bridge A phase (direction) Logic high sets AOUT1 high, AOUT2 low AI0 24 27 I AI1 25 28 I Bridge A current set Sets bridge A current: 00 = 100%, 01 = 71%, 10 = 38%, 11 = 0 BENBL 22 25 I Bridge B enable Logic high to enable bridge B BPHASE 23 26 I Bridge B phase (direction) Logic high sets BOUT1 high, BOUT2 low BI0 26 1 I BI1 27 2 I Bridge B current set Sets bridge B current: 00 = 100%, 01 = 71%, 10 = 38%, 11 = 0 DECAY 19 22 I Decay mode Low = slow decay, open = mixed decay, high = fast decay nRESET 16 19 I Reset input Active-low reset input initializes internal logic and disables the H-bridge outputs nSLEEP 17 20 I Sleep mode input Logic high to enable device, logic low to enter low-power sleep mode AVREF 12 15 I Bridge A current set reference input BVREF 13 16 I Bridge B current set reference input 18 21 OD Fault Logic low when in fault condition (overtemp, overcurrent) Connect to motor supply (8.2-V to 45-V). Both pins must be connected to the same supply, bypassed with a 0.1uF capacitor to GND, and connected to appropriate bulk capacitance. Bypass to GND with a 0.47-μF 6.3-V ceramic capacitor. Can be used to supply VREF. Connect a 0.01-μF 50-V capacitor between CP1 and CP2. CONTROL Reference voltage for winding current set. Can be driven individually with an external DAC for microstepping, or tied to a reference (e.g., V3P3OUT). A 0.01-µF bypass capacitor to GND is recommended. STATUS nFAULT OUTPUT ISENA 6 9 IO Bridge A ground / Isense Connect to current sense resistor for bridge A ISENB 9 12 IO Bridge B ground / Isense Connect to current sense resistor for bridge B AOUT1 5 8 O Bridge A output 1 AOUT2 7 10 O Bridge A output 2 BOUT1 10 13 O Bridge B output 1 BOUT2 8 11 O Bridge B output 2 (1) 4 Connect to motor winding A Connect to motor winding B Directions: I = input, O = output, OZ = tri-state output, OD = open-drain output, IO = input/output Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: DRV8812 DRV8812 www.ti.com SLVS997G – OCTOBER 2009 – REVISED OCTOBER 2015 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) VMx Power supply voltage VMx Power supply ramp rate VREF (1) (2) MIN MAX UNIT –0.3 47 V 1 V/µs Digital pin voltage –0.5 7 V Input voltage –0.3 4 V 0.8 V ISENSEx pin voltage (3) –0.8 Peak motor drive output current, t < 1 μS Internally limited Continuous motor drive output current (4) 0 Continuous total power dissipation A 1.6 A See Thermal Information TJ Operating virtual junction temperature –40 150 °C TA Operating ambient temperature –40 85 °C Tstg Storage temperature –60 150 °C (1) (2) (3) (4) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. Transients of ±1 V for less than 25 ns are acceptable Power dissipation and thermal limits must be observed. 6.2 ESD Ratings V(ESD) (1) (2) Electrostatic discharge VALUE UNIT Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) ±500 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN VM Motor power supply voltage range (1) VREF VREF input voltage (2) IV3P3 V3P3OUT load current (1) (2) NOM MAX UNIT 8.2 45 V 1 3.5 V 1 mA All VM pins must be connected to the same supply voltage. Operational at VREF between 0 V and 1 V, but accuracy is degraded. 6.4 Thermal Information DRV8812 THERMAL METRIC (1) PWP (HTSSOP) RHD (VQFN) UNIT 28 PINS 28 PINS RθJA Junction-to-ambient thermal resistance 38.9 35.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 23.3 25.1 °C/W RθJB Junction-to-board thermal resistance 21.2 8.2 °C/W ψJT Junction-to-top characterization parameter 0.8 0.3 °C/W ψJB Junction-to-board characterization parameter 20.9 8.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 2.6 1.1 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: DRV8812 5 DRV8812 SLVS997G – OCTOBER 2009 – REVISED OCTOBER 2015 www.ti.com 6.5 Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES IVM VM operating supply current VM = 24 V, fPWM < 50 kHz 5 8 mA IVMQ VM sleep mode supply current VM = 24 V 10 20 μA VUVLO VM undervoltage lockout voltage VM rising 7.8 8.2 V V3P3OUT REGULATOR V3P3 V3P3OUT voltage IOUT = 0 to 1 mA, VM = 24 V, TJ = 25°C 3.18 3.30 3.42 V IOUT = 0 to 1 mA 3.10 3.30 3.50 V LOGIC-LEVEL INPUTS VIL Input low voltage VIH Input high voltage 0.6 0.7 V 5.25 V VHYS Input hysteresis IIL Input low current VIN = 0 20 μA IIH Input high current VIN = 3.3 V 100 μA 0.5 V 1 μA 0.8 V ±40 µA 2 0.45 –20 V nFAULT OUTPUT (OPEN-DRAIN OUTPUT) VOL Output low voltage IO = 5 mA IOH Output high leakage current VO = 3.3 V DECAY INPUT VIL Input low threshold voltage For slow decay mode 0 VIH Input high threshold voltage For fast decay mode 2 IIN Input current V H-BRIDGE FETS RDS(ON) HS FET on resistance RDS(ON) LS FET on resistance IOFF Off-state leakage current VM = 24 V, I O = 1 A, TJ = 25°C 0.63 VM = 24 V, IO = 1 A, TJ = 85°C 0.76 VM = 24 V, IO = 1 A, TJ = 25°C 0.65 VM = 24 V, IO = 1 A, TJ = 85°C 0.78 –20 Ω 0.90 Ω Ω 0.90 Ω 20 μA MOTOR DRIVER fPWM Internal PWM frequency tBLANK Current sense blanking time 50 tR Rise time VM = 24 V 100 tF Fall time VM = 24 V 80 tDEAD Dead time tDEG Input deglitch time kHz μs 3.75 360 ns 250 ns 2.9 µs 400 1.3 ns PROTECTION CIRCUITS IOCP Overcurrent protection trip level tTSD Thermal shutdown temperature 1.8 Die temperature 150 5 A 160 180 °C CURRENT CONTROL IREF xVREF input current VTRIP xISENSE trip voltage AISENSE Current sense amplifier gain 6 3 μA xVREF = 3.3 V, 100% current setting 635 660 685 mV xVREF = 3.3 V, 71% current setting 445 469 492 mV xVREF = 3.3 V, 38% current setting 225 251 276 xVREF = 3.3 V Reference only Submit Documentation Feedback –3 5 mV V/V Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: DRV8812 DRV8812 www.ti.com SLVS997G – OCTOBER 2009 – REVISED OCTOBER 2015 6.6 Typical Characteristics 14 7.0 13 6.5 12 IVMQ ( A) IVM (mA) 6.0 5.5 5.0 11 10 9 -40°C 8 25°C 4.5 85°C 125°C 4.0 10 15 20 25 30 35 40 V(VMx) (V) 25°C 85°C 7 125°C 6 45 10 15 -40°C 85°C 30 35 40 45 C002 Figure 2. IVMxQ vs V(VMx) 2000 25°C 125°C 10 V 24 V 1800 RDS(ON) HS + LS (mŸ) 1800 RDS(ON) HS + LS (mŸ) 25 V(VMx) (V) Figure 1. IVMx vs V(VMx) 2000 20 C001 1600 1400 1200 45 V 1600 1400 1200 1000 1000 800 800 10 15 20 25 30 35 V(VMx) (V) 40 45 ±50 C003 ±25 0 25 50 75 100 TA (ƒC) 125 C004 Figure 4. RDS(ON) vs Temperature Figure 3. RDS(ON) vs V(VMx) Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: DRV8812 7 DRV8812 SLVS997G – OCTOBER 2009 – REVISED OCTOBER 2015 www.ti.com 7 Detailed Description 7.1 Overview The DRV8812 is an integrated motor driver solution for a bipolar stepper motor or two brushed DC motors. The device integrates two NMOS H-bridges, current sense, regulation circuitry, and detailed fault detection. The DRV8813 can be powered with a supply voltage between 8.2 V and 45 V and is capable of providing an output current up to 1.6 A full-scale. A PHASE/ENBL interface allows for simple interfacing to the controller circuit. The winding current control allows the external controller to adjust the regulated current that is provided to the motor. The current regulation is highly configurable, with three decay modes of operation. Fast, slow, and mixed decay can be selected depending on the application requirements. A low-power sleep mode is included which allows the system to save power when not driving the motor. 7.2 Functional Block Diagram VM VM CP1 Int. VCC Internal Reference & LS Gate Regs Drive V3P3OUT 0.01mF CP2 VM Charge Pump 3.3V VCP 3.3V 0.1mF Thermal HS Gate Drive Shut down 1MW VM VMA AVREF BVREF AOUT1 + APHASE Step Motor DCM Driver A AENBL Motor - AOUT2 AI0 + ISENA AI1 - BPHASE BENBL BI0 Control VM Logic VMB BI1 DECAY BOUT1 Motor nRESET Driver B BOUT2 nFAULT ISENB GND 8 DCM nSLEEP GND Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: DRV8812 DRV8812 www.ti.com SLVS997G – OCTOBER 2009 – REVISED OCTOBER 2015 7.3 Feature Description 7.3.1 PWM Motor Drivers The DRV8812 contains two H-bridge motor drivers with current-control PWM circuitry. A block diagram of the motor control circuitry is shown in Figure 5. A bipolar stepper motor is shown, but the drivers can also drive two separate DC motors. Figure 5. Motor Control Circuitry Note that there are multiple VM motor power supply pins. All VM pins must be connected together to the motor supply voltage. Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: DRV8812 9 DRV8812 SLVS997G – OCTOBER 2009 – REVISED OCTOBER 2015 www.ti.com 7.4 Device Functional Modes 7.4.1 Bridge Control The xPHASE input pins control the direction of current flow through each H-bridge. The xENBL input pins enable the H-bridge outputs when active high. Table 1 shows the logic. Table 1. H-Bridge Logic xENBL xPHASE xOUT1 xOUT2 0 X Z Z 1 1 H L 1 0 L H 7.4.2 Current Regulation The current through the motor windings is regulated by a fixed-frequency PWM current regulation, or current chopping. When an H-bridge is enabled, current rises through the winding at a rate dependent on the DC voltage and inductance of the winding. Once the current hits the current chopping threshold, the bridge disables the current until the beginning of the next PWM cycle. For stepping motors, current regulation is normally used at all times, and can changing the current can be used to microstep the motor. For DC motors, current regulation is used to limit the start-up and stall current of the motor. The PWM chopping current is set by a comparator which compares the voltage across a current sense resistor connected to the xISEN pins, multiplied by a factor of 5, with a reference voltage. The reference voltage is input from the xVREF pins, and is scaled by a 2-bit DAC that allows current settings of 100%, 71%, 38% of full-scale, plus zero. The full-scale (100%) chopping current is calculated in Equation 1. VREFX ICHOP 5 u RISENSE (1) Example: If a 0.5-Ω sense resistor is used and the VREFx pin is 3.3 V, the full-scale (100%) chopping current will be 3.3 V / (5 x 0.5 Ω) = 1.32 A. Two input pins per H-bridge (xI1 and xI0) are used to scale the current in each bridge as a percentage of the fullscale current set by the VREF input pin and sense resistance. The function of the pins is shown in Table 2. Table 2. H-Bridge Pin Functions xI1 xI0 RELATIVE CURRENT (% FULL-SCALE CHOPPING CURRENT) 1 1 0% (Bridge disabled) 1 0 38% 0 1 71% 0 0 100% Note that when both xI bits are 1, the H-bridge is disabled and no current flows. Example: If a 0.5-Ω sense resistor is used and the VREF pin is 3.3 V, the chopping current will be 1.32 A at the 100% setting (xI1, xI0 = 00). At the 71% setting (xI1, xI0 = 01) the current will be 1.32 A x 0.71 = 0.937 A, and at the 38% setting (xI1, xI0 = 10) the current will be 1.32 A x 0.38 = 0.502 A. If (xI1, xI0 = 11) the bridge will be disabled and no current will flow. 10 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: DRV8812 DRV8812 www.ti.com SLVS997G – OCTOBER 2009 – REVISED OCTOBER 2015 7.4.3 Decay Mode During PWM current chopping, the H-bridge is enabled to drive current through the motor winding until the PWM current chopping threshold is reached. This is shown in Figure 6 as case 1. The current flow direction shown indicates the state when the xENBL pin is high. Once the chopping current threshold is reached, the H-bridge can operate in two different states, fast decay or slow decay. In fast decay mode, once the PWM chopping current level has been reached, the H-bridge reverses state to allow winding current to flow in a reverse direction. As the winding current approaches zero, the bridge is disabled to prevent any reverse current flow. Fast decay mode is shown in Figure 6 as case 2. In slow decay mode, winding current is re-circulated by enabling both of the low-side FETs in the bridge. This is shown in Figure 6 as case 3. Figure 6. Decay Mode The DRV8812 supports fast decay, slow decay and a mixed decay mode. Slow, fast, or mixed decay mode is selected by the state of the DECAY pin - logic low selects slow decay, open selects mixed decay operation, and logic high sets fast decay mode. Note that the DECAY pin sets the decay mode for both H-bridges. Mixed decay mode begins as fast decay, but at a fixed period of time (75% of the PWM cycle) switches to slow decay mode for the remainder of the fixed PWM period. 7.4.4 Blanking Time After the current is enabled in an H-bridge, the voltage on the xISEN pin is ignored for a fixed period of time before enabling the current sense circuitry. This blanking time is fixed at 3.75 μs. Note that the blanking time also sets the minimum on time of the PWM. 7.4.5 nRESET and nSLEEP Operation The nRESET pin, when driven active low, resets the internal logic. It also disables the H-bridge drivers. All inputs are ignored while nRESET is active. Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: DRV8812 11 DRV8812 SLVS997G – OCTOBER 2009 – REVISED OCTOBER 2015 www.ti.com Driving nSLEEP low will put the device into a low power sleep state. In this state, the H-bridges are disabled, the gate drive charge pump is stopped, the V3P3OUT regulator is disabled, and all internal clocks are stopped. In this state all inputs are ignored until nSLEEP returns inactive high. When returning from sleep mode, some time (approximately 1 ms) needs to pass before the motor driver becomes fully operational. 7.4.6 Protection Circuits The DRV8812 is fully protected against undervoltage, overcurrent and overtemperature events. 7.4.6.1 Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this analog current limit persists for longer than the OCP time, all FETs in the H-bridge will be disabled and the nFAULT pin will be driven low. The device will remain disabled until either nRESET pin is applied, or VM is removed and re-applied. Overcurrent conditions on both high and low side devices; i.e., a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Note that overcurrent protection does not use the current sense circuitry used for PWM current control, and is independent of the ISENSE resistor value or VREF voltage. 7.4.6.2 Thermal Shutdown (TSD) If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled and the nFAULT pin will be driven low. Once the die temperature has fallen to a safe level operation will automatically resume. 7.4.6.3 Undervoltage Lockout (UVLO) If at any time the voltage on the VM pins falls below the undervoltage lockout threshold voltage, all circuitry in the device will be disabled and internal logic will be reset. Operation will resume when VM rises above the UVLO threshold. 12 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: DRV8812 DRV8812 www.ti.com SLVS997G – OCTOBER 2009 – REVISED OCTOBER 2015 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The DRV8812 can be used to control a bipolar stepper motor. The PHASE/ENBL interface controls the outputs and current control can be implemented with the internal current regulation circuitry. Detailed fault reporting is provided with the internal protection circuits and nFAULT pin. 8.2 Typical Application DRV8812 CP1 GND CP2 BI1 VCP BI0 VMA AI1 AOUT1 AI0 0.01uF 1MŸ 0.1uF + 0.01uF 400mŸ BPHASE ISENA Stepper Motor - VM 100uF + + AOUT2 BENBL BOUT2 AENBL - 400mŸ ISENB APHASE V3P3OUT BOUT1 DECAY VMB nFAULT AVREF nSLEEP BVREF nRESET 10kŸ V3P3OUT 10kŸ 30kŸ GND PPAD 0.01uF V3P3OUT V3P3OUT 0.47uF Figure 7. Typical Application Schematic Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: DRV8812 13 DRV8812 SLVS997G – OCTOBER 2009 – REVISED OCTOBER 2015 www.ti.com Typical Application (continued) 8.2.1 Design Requirements Table 3. Design Parameters REFERENCE VALUE Supply voltage PARAMETER VM 24 V Motor winding resistance RL 3.9 Ω Motor winding inductance IL 2.9 mH Sense resistor value RSENSE 400 mΩ IFS 1.25 A Target full-scale current 8.2.2 Detailed Design Procedure 8.2.2.1 Current Regulation In a stepper motor, the set full-scale current (IFS) is the maximum current driven through either winding. This quantity depends on the xVREF analog voltage and the sense resistor value (RSENSE). During stepping, IFS defines the current chopping threshold (ITRIP) for the maximum current step. The gain of DRV8812 is set for 5 V/V. xVREF(V) xVREF(V) IFS (A) A v u RSENSE (:) 5 u RSENSE (:) (2) To achieve IFS = 1.25 A with RSENSE of 0.2 Ω, xVREF should be 1.25 V. 8.2.2.2 Decay Modes The DRV8812 supports three different decay modes: slow decay, fast decay, and mixed decay. The current through the motor windings is regulated using a fixed-frequency PWM scheme. This means that after any drive phase, when a motor winding current has hit the current chopping threshold (ITRIP), the DRV8812 will place the winding in one of the three decay modes until the PWM cycle has expired. Afterward, a new drive phase starts. The blanking time, tBLANK, defines the minimum drive time for the current chopping. ITRIP is ignored during tBLANK, so the winding current may overshoot the trip level. 8.2.2.3 Sense Resistor For optimal performance, it is important for the sense resistor to be: • Surface-mount • Low inductance • Rated for high enough power • Placed closely to the motor driver The power dissipated by the sense resistor equals Irms2 x R. For example, if the rms motor current is 2-A and a 100-m Ω sense resistor is used, the resistor will dissipate 2 A ² × 0.1 Ω = 0.4 W. The power quickly increases with greater current levels. Resistors typically have a rated power within some ambient temperature range, along with a de-rated power curve for high ambient temperatures. When a PCB is shared with other components generating heat, margin should be added. It is always best to measure the actual sense resistor temperature in a final system, along with the power MOSFETs, as those are often the hottest components. Because power resistors are larger and more expensive than standard resistors, it is common practice to use multiple standard resistors in parallel, between the sense node and ground. This distributes the current and heat dissipation. 14 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: DRV8812 DRV8812 www.ti.com SLVS997G – OCTOBER 2009 – REVISED OCTOBER 2015 8.2.3 Application Curves Figure 8. DRV8828 Current Limiting Figure 9. DRV8828 Direction Change Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: DRV8812 15 DRV8812 SLVS997G – OCTOBER 2009 – REVISED OCTOBER 2015 www.ti.com 9 Power Supply Recommendations The DRV8812 is designed to operate from an input voltage supply (VMx) range between 8.2 and 45 V. Two 0.1-µF ceramic capacitors rated for VMx must be placed as close as possible to the VMA and VMB pins respectively (one on each pin). In addition to the local decoupling caps, additional bulk capacitance is required and must be sized accordingly to the application requirements. 9.1 Bulk Capacitance Bulk capacitance sizing is an important factor in motor drive system design. It is dependent on a variety of factors including: • Type of power supply • Acceptable supply voltage ripple • Parasitic inductance in the power supply wiring • Type of motor (brushed DC, brushless DC, stepper) • Motor startup current • Motor braking method The inductance between the power supply and motor drive system will limit the rate current can change from the power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands or dumps from the motor with a change in voltage. You should size the bulk capacitance to meet acceptable voltage ripple levels. The data sheet generally provides a recommended value but system level testing is required to determine the appropriate sized bulk capacitor. Parasitic Wire Inductance Motor Drive System Power Supply VM + – Motor Motor Driver Driver + GND Local Bulk Capacitor IC Bypass Capacitor Figure 10. Setup of Motor Drive System With External Power Supply 9.2 Power Supply and Logic Sequencing There is no specific sequence for powering-up the DRV8812. It is okay for digital input signals to be present before VMx is applied. After VMx is applied to the DRV8812, it begins operation based on the status of the control pins. 16 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: DRV8812 DRV8812 www.ti.com SLVS997G – OCTOBER 2009 – REVISED OCTOBER 2015 10 Layout 10.1 Layout Guidelines The VMA and VMB pins should be bypassed to GND using low-ESR ceramic bypass capacitors with a recommended value of 0.1-μF rated for VMx. This capacitor should be placed as close to the VMA and VMB pins as possible with a thick trace or ground plane connection to the device GND pin. The VMA and VMB pins must be bypassed to ground using an appropriate bulk capacitor. This component may be an electrolytic and should be located close to the DRV8812. A low-ESR ceramic capacitor must be placed in between the CPL and CPH pins. TI recommends a value of 0.01-μF rated for VMx. Place this component as close to the pins as possible. A low-ESR ceramic capacitor must be placed in between the VMA and VCP pins. TI recommends a value of 0.1μF rated for 16 V. Place this component as close to the pins as possible. Also, place a 1-MΩ resistor between VCP and VMA. Bypass V3P3 to ground with a ceramic capacitor rated 6.3 V. Place this bypass capacitor as close to the pin as possible 10.2 Layout Example 0.1 µF CP1 GND CP2 BI1 0.01 µF 1 0Ÿ VCP BI0 VMA AI1 AOUT1 AI0 ISENA BPHASE AOUT2 BENBL 0.1 µF RISENA RISENB BOUT2 AENBL ISENB APHASE BOUT1 DECAY VMB nFAULT AVREF nSLEEP + 0.1 µF BVREF nRESET GND V3P3OUT 0.47 µF Figure 11. DRV8812 Layout Example Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: DRV8812 17 DRV8812 SLVS997G – OCTOBER 2009 – REVISED OCTOBER 2015 www.ti.com 10.3 Thermal Consideration 10.3.1 Thermal Protection The DRV8812 has thermal shutdown (TSD) as described above. If the die temperature exceeds approximately 150°C, the device will be disabled until the temperature drops to a safe level. Any tendency of the device to enter TSD is an indication of either excessive power dissipation, insufficient heatsinking, or too high an ambient temperature. 10.3.2 Power Dissipation Power dissipation in the DRV8812 is dominated by the power dissipated in the output FET resistance, or RDS(ON). Average power dissipation when running a stepper motor can be roughly estimated by Equation 3. PTOT 4 u RDS(ON) u IOUT(RMS) 2 (3) where PTOT is the total power dissipation, RDS(ON) is the resistance of each FET, and IOUT(RMS) is the RMS output current being applied to each winding. IOUT(RMS) is equal to the approximately 0.7x the full-scale output current setting. The factor of 4 comes from the fact that there are two motor windings, and at any instant two FETs are conducting winding current for each winding (one high-side and one low-side). The maximum amount of power that can be dissipated in the device is dependent on ambient temperature and heatsinking. Note that RDS(ON) increases with temperature, so as the device heats, the power dissipation increases. This must be taken into consideration when sizing the heatsink. 10.3.3 Heatsinking The PowerPAD™ package uses an exposed pad to remove heat from the device. For proper operation, this pad must be thermally connected to copper on the PCB to dissipate heat. On a multi-layer PCB with a ground plane, this can be accomplished by adding a number of vias to connect the thermal pad to the ground plane. On PCBs without internal planes, copper area can be added on either side of the PCB to dissipate heat. If the copper area is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat between top and bottom layers. For details about how to design the PCB, refer to TI application report SLMA002, "PowerPAD™ Thermally Enhanced Package" and TI application brief SLMA004, "PowerPAD™ Made Easy", available at www.ti.com. In general, the more copper area that can be provided, the more power can be dissipated. 18 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: DRV8812 DRV8812 www.ti.com SLVS997G – OCTOBER 2009 – REVISED OCTOBER 2015 11 Device and Documentation Support 11.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 11.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.3 Trademarks PowerPAD, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 11.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: DRV8812 19 PACKAGE OPTION ADDENDUM www.ti.com 12-Jun-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) DRV8812PWP ACTIVE HTSSOP PWP 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 DRV8812 DRV8812PWPR ACTIVE HTSSOP PWP 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 DRV8812 DRV8812RHDR ACTIVE VQFN RHD 28 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 DRV8812 DRV8812RHDT ACTIVE VQFN RHD 28 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 DRV8812 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 12-Jun-2015 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DRV8812PWPR HTSSOP PWP 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1 DRV8812RHDR VQFN RHD 28 3000 330.0 DRV8812RHDT VQFN RHD 28 250 180.0 12.4 5.3 5.3 1.1 8.0 12.0 Q2 12.4 5.3 5.3 1.1 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DRV8812PWPR HTSSOP PWP 28 2000 350.0 350.0 43.0 DRV8812RHDR VQFN RHD 28 3000 367.0 367.0 35.0 DRV8812RHDT VQFN RHD 28 250 210.0 185.0 35.0 Pack Materials-Page 2 GENERIC PACKAGE VIEW PWP 28 TM PowerPAD TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 4.4 x 9.7, 0.65 mm pitch Images above are just a representation of the package family, actual package may vary. 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