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DRV8842-EP
SLVSCH4 – JULY 2014
DRV8842-EP DC Motor Driver IC
1 Features
2 Applications
•
•
•
•
•
•
•
1
•
•
•
•
•
•
Single H-Bridge Current-Control Motor Driver
– Drives One DC Motor, One Coil of a Stepper
Motor, or Other Actuators
– Five-Bit Winding Current Control Allows Up to
32 Current Levels
– Low MOSFET On-Resistance
5-A Maximum Drive Current at 24 V, 25°C
Built-In 3.3-V Reference Output
Industry-Standard PWM Control Interface
8.2-V to 45-V Operating Supply Voltage Range
Thermally Enhanced Surface Mount Package
Supports Defense, Aerospace, and Medical
Applications
– Controlled Baseline
– One Assembly and Test Site
– One Fabrication Site
– Available in Military (–55°C to 125°C)
Temperature Range
– Extended Product Life Cycle
– Extended Product-Change Notification
– Product Traceability
Printers
Scanners
Office Automation Machines
Gaming Machines
Factory Automation
Robotics
3 Description
The DRV8842-EP provides an integrated motor driver
solution for printers, scanners, and other automated
equipment applications. The device has one H-bridge
driver, and is intended to drive one DC motor, one
coil of a stepper motor, or other loads. The output
driver block consists of N-channel power MOSFETs
configured as an H-bridge. The DRV8842-EP can
supply up to 5-A peak or 3.5-A RMS output current
(with proper heatsinking at 24 V and 25°C).
Separate inputs to independently control each half of
the H-bridge are provided.
Internal shutdown functions are provided for
overcurrent protection, short circuit protection,
undervoltage lockout, and over-temperature.
The DRV8842-EP is available in a 28-pin HTSSOP
package with PowerPAD™ (Eco-friendly: RoHS & no
Sb/Br).
Device Information(1)
ORDER NUMBER
DRV8842MPWPREP
PACKAGE
HTSSOP (28)
BODY SIZE (NOM)
9.70 mm x 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
4 Simplified Schematic
8.2 to 45 V
DRV8842-EP
IN2
VREF
Stepper
Motor Driver
M
5A
±
Current %
+
Controller
IN1
nFAULT
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRV8842-EP
SLVSCH4 – JULY 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
4
4
4
5
6
6
7
Absolute Maximum Ratings .....................................
Handling Ratings.......................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Motor Driver Timing Requirements ...........................
Typical Characteristics ..............................................
8.3 Feature Description................................................... 9
8.4 Device Functional Modes........................................ 12
9
Application and Implementation ........................ 13
9.1 Application Information............................................ 13
9.2 Typical Application .................................................. 13
10 Power Supply Recommendations ..................... 16
10.1 Bulk Capacitance .................................................. 16
10.2 Power Supply and Logic Sequencing .................. 16
11 Layout................................................................... 17
11.1 Layout Guidelines ................................................. 17
11.2 Layout Example .................................................... 17
12 Device and Documentation Support ................. 18
12.1 Trademarks ........................................................... 18
12.2 Electrostatic Discharge Caution ............................ 18
12.3 Glossary ................................................................ 18
Detailed Description .............................................. 8
13 Mechanical, Packaging, and Orderable
Information ........................................................... 18
8.1 Overview ................................................................... 8
8.2 Functional Block Diagram ......................................... 8
5 Revision History
2
DATE
VERSION
NOTES
July 2014
*
Initial Release
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6 Pin Configuration and Functions
PWP PACKAGE
(TOP VIEW)
CP1
CP2
VCP
VM
OUT1
ISEN
OUT2
OUT2
ISEN
OUT1
VM
VREF
VREF
GND
1
2
3
28
4
25
24
27
26
5
6
7
8
23
GND
(PPAD)
22
21
9
20
10
19
11
18
12
17
13
16
14
15
GND
I4
I3
I2
I1
I0
NC
IN1
IN2
DECAY
nFAULT
nSLEEP
nRESET
V3P3OUT
Pin Functions
PIN
NAME
NO.
I/O (1)
DESCRIPTION
EXTERNAL COMPONENTS OR CONNECTIONS
POWER AND GROUND
GND
14
28
4
VM
11
—
Device ground
—
Bridge A power supply
Connect to motor supply (8.2 to 45 V). Both pins must be connected to same
supply.
Bypass to GND with a 0.47-μF, 6.3-V ceramic capacitor. Can be used to supply
VREF.
V3P3OUT
15
O
3.3-V regulator output
CP1
1
IO
Charge pump flying capacitor
CP2
2
IO
Charge pump flying capacitor
VCP
3
IO
High-side gate drive voltage
Connect a 0.1-μF 16-V ceramic capacitor and a 1-MΩ resistor to VM.
IN1
21
I
Input 1
Logic input controls state of OUT1. Internal pulldown.
IN2
20
I
Input 2
Logic input controls state of OUT2. Internal pulldown.
I0
23
I
I1
24
I
I2
25
I
Current set inputs
Sets winding current as a percentage of full-scale. Internal pulldown.
I3
26
I
I4
27
I
DECAY
19
I
Decay mode
Low = slow decay, open = mixed decay,
High = fast decay. Internal pulldown and pullup.
nRESET
16
I
Reset input
Active-low reset input initializes the logic and disables the H-bridge outputs.
Internal pulldown.
nSLEEP
17
I
Sleep mode input
Logic high to enable device, logic low to enter low-power sleep mode. Internal
pulldown.
I
Current set reference input
Reference voltage for winding current set. Both pins must be connected together
on the PCB.
OD
Fault
Logic low when in fault condition (over-temperature, overcurrent)
IO
Bridge ground / Isense
Connect to current sense resistor. Both pins must be connected together on the
PCB.
Connect a 0.01-μF 50-V capacitor between CP1 and CP2.
CONTROL
VREF
12
13
STATUS
nFAULT
18
OUTPUT
ISEN
(1)
6
9
Directions: I = input, O = output, OZ = tri-state output, OD = open-drain output, IO = input/output
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Pin Functions (continued)
PIN
NAME
NO.
I/O (1)
5
OUT1
10
7
OUT2
8
DESCRIPTION
EXTERNAL COMPONENTS OR CONNECTIONS
O
Bridge output 1
Connect to motor winding. Both pins must be connected together on the PCB.
O
Bridge output 2
Connect to motor winding. Both pins must be connected together on the PCB.
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
V(VM)
V(VREF)
TJ
(1)
(2)
(3)
(1) (2)
MIN
MAX
Power supply voltage
–0.3
47
V
Digital pin voltage
–0.5
7
V
Input voltage
–0.3
4
V
ISEN pins
–0.3
0.8
V
Peak motor drive output current, t < 1 μs
Internally limited
A
Continuous motor drive output current (3)
5
A
Continuous total power dissipation
See Thermal Information
Operating virtual junction temperature range
–55
UNIT
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
Power dissipation and thermal limits must be observed.
7.2 Handling Ratings
Tstg
Storage temperature range
V(ESD) (1)
(1)
(2)
(3)
Electrostatic
discharge
MIN
MAX
UNIT
–60
150
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (2)
–500 4000
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (3)
–250 1500
V
Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by assembly line electrostatic discharges into
the device.
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as 1 kV
may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as 250 V
may actually have higher performance.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VM
Motor power supply voltage range (1)
V(VREF)
NOM
MAX
UNIT
8.2
45
V
VREF input voltage (2)
1
3.5
V
IV3P3
V3P3OUT load current
0
1
mA
ƒPWM
Externally applied PWM frequency
0
100
kHz
TJ
Operating virtual junction temperature range
–55
125
°C
(1)
(2)
4
All VM pins must be connected to the same supply voltage.
Operational at V(VREF) between 0 and 1 V, but accuracy is degraded.
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7.4 Thermal Information
DRV8842-EP
THERMAL METRIC (1)
PWP
UNIT
28 PINS
RθJA
Junction-to-ambient thermal resistance (2)
(3)
35.6
RθJC(top)
Junction-to-case (top) thermal resistance
RθJB
Junction-to-board thermal resistance (4)
13.5
ψJT
Junction-to-top characterization parameter (5)
0.4
ψJB
Junction-to-board characterization parameter (6)
13.3
RθJC(bot)
Junction-to-case (bottom) thermal resistance (7)
1.4
(1)
(2)
(3)
(4)
(5)
(6)
(7)
15.6
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
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7.5 Electrical Characteristics
over recommended operating junction temperature range
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLIES
IVM
VM operating supply current
VM = 24 V, ƒPWM < 50 kHz
5
8
mA
IVMQ
VM sleep mode supply current
VM = 24 V
10
20
μA
VUVLO
VM undervoltage lockout voltage
VM rising
7.8
8.4
V
3.3
3.5
V
V3P3OUT REGULATOR
V3P3
V3P3OUT voltage
IOUT = 0 to 1 mA
3.1
LOGIC-LEVEL INPUTS
VIL
Input low voltage
VIH
Input high voltage
2.2
0.6
VHYS
Input hysteresis
0.3
IIL
Input low current
VIN = 0
IIH
Input high current
VIN = 3.3 V
RPD
Internal pulldown resistance
0.7
V
5.25
V
0.45
0.65
V
20
μA
33
100
μA
–20
100
kΩ
nFAULT OUTPUT (OPEN-DRAIN OUTPUT)
VOL
Output low voltage
IO = 5 mA
IOH
Output high leakage current
VO = 3.3 V
0.5
V
1
μA
0.8
V
±40
μA
DECAY INPUT
VIL
Input low threshold voltage
For slow decay (brake) mode
0
VIH
Input high threshold voltage
For fast decay (coast) mode
2
IIN
Input current
RPU
Internal pullup resistance (to 3.3 V)
RPD
Internal pulldown resistance
V
130
kΩ
80
kΩ
H-BRIDGE FETS
RDS(ON)
HS FET on resistance
VM = 24 V, IO = 1 A
RDS(ON)
LS FET on resistance
VM = 24 V, IO = 1 A
IOFF
Off-state leakage current
Ω
0.13
0.17
0.13
0.17
Ω
96
μA
160
180
°C
3
μA
660
685
mV
–79
PROTECTION CIRCUITS
IOCP
Overcurrent protection trip level
tTSD
Thermal shutdown temperature
5
Die temperature
150
A
CURRENT CONTROL
IREF
VREF input current
V(VREF) = 3.3 V
VTRIP
ISENSE trip voltage
V(VREF) = 3.3 V, 100% current setting
Current trip accuracy
(relative to programmed value)
ΔITRIP
AISENSE
Current sense amplifier gain
–3
635
V(VREF) = 3.3 V, 5% current setting
–25%
25%
V(VREF) = 3.3 V, 10% to 34% current setting
–15%
15%
V(VREF) = 3.3 V, 38% to 67% current setting
–10%
10%
V(VREF) = 3.3 V, 71% to 100% current setting
–5%
5%
Reference only
5
V/V
7.6 Motor Driver Timing Requirements
MIN
TYP
MAX
ƒPWM
Internal current control PWM frequency
tBLANK
Current sense blanking time
tR
Rise time
30
220
ns
tF
Fall time
30
220
ns
6
50
UNIT
kHz
μs
3.75
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4.95
9.8
4.9
9.7
IVMQ (PA)
IVM (mA)
7.7 Typical Characteristics
4.85
4.8
4.75
-90
9.6
9.5
-50
-10
30
70
Temperature (qC)
110
150
9.4
-90
-50
-10
30
70
Temperature (qC)
D001
Figure 1. IVM vs Temperature
110
150
D001
D002
Figure 2. IVMQ vs Temperature
130
R D S (O N ) (m : )
120
110
100
90
80
RDS(ON) HS
RDS(ON) LS
70
-65
-25
15
55
Temperature (qC)
95
135
D003
Figure 3. RDS(ON) vs Temperature
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8 Detailed Description
8.1 Overview
The DRV8842-EP provides an integrated motor driver solution for printers, scanners, and other automated
equipment applications. The device has one H-bridge driver, and is intended to drive one DC motor, one coil of a
stepper motor, or other loads. The output driver block consists of N-channel power MOSFETs configured as an
H-bridge. The DRV8842-EP can supply up to 5-A peak or 3.5-A RMS output current (with proper heatsinking at
24 V and 25°C).
8.2 Functional Block Diagram
VM
VM
CP1
Int. VCC
Internal
Reference &
Regs
3.3V
LS Gate
Drive
V3P3OUT
0.01mF
CP2
VM
Charge
Pump
VCP
0.1mF
3.3V
HS Gate
Drive
Thermal
Shut down
1MW
VM
VREF
VM
VREF
VM
IN1
OUT1
IN2
OUT1
I0
+
I1
Step
Motor
DCM
I2
I3
I4
Motor
Driver
Control
Logic
OUT2
+
-
OUT2
DECAY
nRESET
ISEN
nSLEEP
ISEN
nFAULT
GND
8
GND
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8.3 Feature Description
8.3.1 PWM Motor Drivers
The DRV8842-EP contains one H-bridge motor driver with current-control PWM circuitry. Figure 4 shows a block
diagram of the motor control circuitry.
VM
OCP
VM
VCP, VGD
OUT1
Predrive
DCM
OUT2
IN1
IN2
PWM
DECAY
OCP
ISEN
+
I[4:0]
A =5
DAC
5
VREF
Figure 4. Motor Control Circuitry
Note that there are multiple VM, ISEN, OUT, and VREF pins. All like-named pins must be connected together on
the PCB.
8.3.2 Bridge Control
The IN1 and IN2 input pins directly control the state of the OUT1 and OUT2 outputs. Either input can also be
used for PWM control of the load. Table 1 shows the logic.
Table 1. H-Bridge Logic
IN1
IN2
OUT1
OUT2
0
0
L
L
0
1
L
H
1
0
H
L
1
1
H
H
The control inputs have internal pulldown resistors of approximately 100 kΩ.
8.3.3 Current Regulation
The maximum current through the load is regulated by a fixed-frequency PWM current regulation, or current
chopping. When the H-bridge is enabled, current rises through the winding at a rate dependent on the DC
voltage and inductance of the winding. After the current hits the current chopping threshold, the bridge disables
the current until the beginning of the next PWM cycle.
For DC motors, current regulation is used to limit the start-up and stall current of the motor. Speed control is
typically performed by providing an external PWM signal to the IN1 or IN2 input pins.
If the current regulation feature is not needed, it can be disabled by connecting the ISEN pins directly to ground
and the VREF pins to V3P3.
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The PWM chopping current is set by a comparator which compares the voltage across a current sense resistor
connected to the ISEN pins, multiplied by a factor of 5, with a reference voltage. The reference voltage is input
from the VREF pins, and is scaled by a 5-bit DAC that allows current settings of 0% to 100% in an approximately
sinusoidal sequence.
The full-scale (100%) chopping current is calculated in Equation 1.
V(VREF)
ICHOP
5 u RISENSE
(1)
Example:
If using a 0.25-Ω sense resistor and the VREF pins are 2.5 V, the full-scale (100%) chopping current is 2.5 V
/ (5 × 0.25 Ω) = 2 A.
Five input pins (I0 through I4) are used to scale the current in the bridge as a percentage of the full-scale current
set by the VREF input pin and sense resistance. The I0 through I4 pins have internal pulldown resistors of
approximately 100 kΩ. The function of the pins is shown in Table 2.
Table 2. Pin Functions
10
I[4..0]
RELATIVE CURRENT
(% FULL-SCALE CHOPPING CURRENT)
0x00h
0%
0x01h
5%
0x02h
10%
0x03h
15%
0x04h
20%
0x05h
24%
0x06h
29%
0x07h
34%
0x08h
38%
0x09h
43%
0x0Ah
47%
0x0Bh
51%
0x0Ch
56%
0x0Dh
60%
0x0Eh
63%
0x0Fh
67%
0x10h
71%
0x11h
74%
0x12h
77%
0x13h
80%
0x14h
83%
0x15h
86%
0x16h
88%
0x17h
90%
0x18h
92%
0x19h
94%
0x1Ah
96%
0x1Bh
97%
0x1Ch
98%
0x1Dh
99%
0x1Eh
100%
0x1Fh
100%
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8.3.4 Blanking Time
After the current is enabled in an H-bridge, the voltage on the ISEN pin is ignored for a fixed period of time
before enabling the current sense circuitry. This blanking time is fixed at 3.75 μs. Note that the blanking time also
sets the minimum on-time of the PWM.
8.3.5 nRESET and nSLEEP Operation
The nRESET pin, when driven active low, resets the internal logic. It also disables the H-bridge driver. All inputs
are ignored while nRESET is active.
Driving nSLEEP low puts the device into a low-power sleep state. In this state, the H-bridges are disabled, the
gate drive charge pump is stopped, the V3P3OUT regulator is disabled, and all internal clocks are stopped. In
this state, all inputs are ignored until nSLEEP returns inactive high. When returning from sleep mode, some time
(approximately 1 ms) needs to pass before the motor driver becomes fully operational. Note that nRESET and
nSLEEP have internal pulldown resistors of approximately 100 kΩ. These signals need to be driven to logic high
for device operation.
8.3.6 Protection Circuits
The DRV8842-EP is fully protected against undervoltage, overcurrent, and overtemperature events.
8.3.6.1 Overcurrent Protection (OCP)
An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this
analog current limit persists for longer than the OCP time, all FETs in the H-bridge are disabled and the nFAULT
pin is driven low. The device remains disabled until either nRESET pin is applied, or VM is removed and
reapplied.
Overcurrent conditions on both high-side and low-side devices (that is, a short to ground, supply, or across the
motor winding) all result in an overcurrent shutdown. Note that overcurrent protection does not use the current
sense circuitry used for PWM current control, and is independent of the ISENSE resistor value or VREF voltage.
8.3.6.2 Thermal Shutdown (TSD)
If the die temperature exceeds safe limits, all FETs in the H-bridge are disabled and the nFAULT pin is driven
low. After the die temperature has fallen to a safe level, operation automatically resumes.
8.3.6.3 Undervoltage Lockout (UVLO)
If at any time the voltage on the VM pins falls below the UVLO threshold voltage, all circuitry in the device is
disabled and internal logic is reset. Operation resumes when VM rises above the UVLO threshold.
8.3.7 Thermal Protection
The DRV8842-EP has TSD as described in Thermal Shutdown (TSD). If the die temperature exceeds
approximately 150°C, the device is disabled until the temperature drops to a safe level.
Any tendency of the device to enter TSD is an indication of either excessive power dissipation, insufficient
heatsinking, or too high an ambient temperature.
8.3.8 Heatsinking
The PowerPAD™ package uses an exposed pad to remove heat from the device. For proper operation, this pad
must be thermally connected to copper on the PCB to dissipate heat. On a multi-layer PCB with a ground plane,
this can be accomplished by adding a number of vias to connect the thermal pad to the ground plane. On PCBs
without internal planes, copper area can be added on either side of the PCB to dissipate heat. If the copper area
is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat between top and
bottom layers.
For details about how to design the PCB, refer to TI application report SLMA002, PowerPAD™ Thermally
Enhanced Package and TI application brief SLMA004, PowerPAD™ Made Easy, available at www.ti.com.
In general, the more copper area that can be provided, the more power can be dissipated.
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8.4 Device Functional Modes
8.4.1 Decay Mode
During PWM current chopping, the H-bridge is enabled to drive current through the motor winding until it reaches
the PWM current chopping threshold (see Figure 5, case 1). The current flow direction shown indicates the state
when the IN1 pin is high and the IN2 pin is low.
After the chopping current threshold is reached, the H-bridge can operate in two different states, fast decay or
slow decay.
In fast decay mode, after the PWM chopping current level is reached, the H-bridge reverses state to allow
winding current to flow in a reverse direction. As the winding current approaches 0, the bridge is disabled to
prevent any reverse current flow. Figure 5 case 2 shows fast decay mode.
In slow decay mode, winding current is recirculated by enabling both of the low-side FETs in the bridge (see
Figure 5, case 3).
Figure 5. Decay Mode
The DRV8842-EP supports fast decay, slow decay, and a mixed decay mode. Slow, fast, or mixed decay mode
is selected by the state of the DECAY pin. Logic low selects slow decay. Open selects mixed decay operation.
And, logic high sets fast decay mode. The DECAY pin has both an internal pullup resistor of approximately 130
kΩ and an internal pulldown resistor of approximately 80 kΩ. This sets the mixed decay mode if the pin is left
open or undriven.
Mixed decay mode begins as fast decay, but at a fixed period of time (75% of the PWM cycle) switches to slow
decay mode for the remainder of the fixed PWM period.
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9 Application and Implementation
9.1 Application Information
The DRV8842-EP is used in DC motor control. This integrated driver drives up to a 5-A peak with precise
winding current control. The motor is controlled through a PWM interface and device faults are reported through
the nFAULT pin. The following design is a common application of the DRV8842-EP.
9.2 Typical Application
DRV8842-EP
CP1
GND
CP2
I4
VCP
I3
VM
I2
OUT1
I1
ISEN
I0
0.01 µF
1 M
0.1 µF
+
0.01 µF
DC Motor
±
VM
100 µF
+
OUT2
NC
OUT2
IN1
ISEN
IN2
100 m
V3P3OUT
OUT1
DECAY
VM
nFAULT
VREF
nSLEEP
VREF
nRESET
10 k
0.1 µF
27 k
50 k
GND
PPAD
V3P3OUT
V3P3OUT
V3P3OUT
0.47 µF
9.2.1 Design Requirements
Design Parameters
Reference
Example Value
Supply voltage
VM
24 V
Motor winding resistance
RL
13.23 Ω
Motor winding inductance
IL
4.03 mH
Motor type
BDC
Brushed DC motor
Sense resistor
RSENSE
100 mΩ
Full-scale current
IFS
3.5 A
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9.2.2 Detailed Design Procedure
9.2.2.1 Power Dissipation
Average power dissipation in the DRV8842-EP when running a DC motor can be roughly estimated by
Equation 2.
P
2 u RDS(ON) u IOUT
2
where
•
•
•
P is the power dissipation of one H-bridge
RDS(ON) is the resistance of each FET
IOUT is the RMS output current being applied to each winding
(2)
IOUT is equal to the average current drawn by the DC motor. Note that at start-up and fault conditions, this current
is much higher than normal running current; also consider the peak currents and their duration. The factor of 2 is
due to two FETs conducting winding current (one high side and one low side) at any instant.
The maximum amount of power that can be dissipated in the device depends on ambient temperature and
heatsinking.
Note that RDS(ON) increases with temperature, so as the device heats, the power dissipation increases. Take this
into consideration when sizing the heatsink.
9.2.2.2 Current Regulation Considerations
For the DRV8842-EP, the set full-scale current (IFS) is the maximum current that can be driven. This quantity
depends on the VREF analog voltage and the sense resistor value (RSENSE). The gain of DRV8842-EP is set for
5 V/V. This value can be adjusted from 0% to 100% through the use of the relative current bits I[4:0].
V(VREF) (V)
V(VREF) (V)
IFS (A)
A V u RSENSE (:) 5 u RSENSE (:)
(3)
To achieve IFS = 3.5 A with RSENSE of 0.1 Ω, V(VREF) should be 1.75 V, and I[4:0] should be 0x1F.
9.2.2.3 Slow, Fast, and Mixed Decay Modes
The DRV8842-EP supports three different decay modes: slow decay, fast decay, and mixed decay. The current
through the motor winding is regulated using a fixed-frequency PWM scheme. This means that after any drive
phase, when a motor winding current has hit the current chopping threshold (ITRIP), the DRV8842-EP places the
winding in one of the three decay modes until the PWM cycle has expired. After, a new drive phase starts.
The blanking time, TBLANK, defines the minimum drive time for the current chopping. ITRIP is ignored during
TBLANK, so the winding current may overshoot the trip level.
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9.2.3 Application Curves
Figure 6. 25% Duty Cycle, Forward Direction
Figure 7. 75% Duty Cycle, Forward Direction
Figure 8. 25% Duty Cycle, Reverse Direction
Figure 9. 75% Duty Cycle, Reverse Direction
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10 Power Supply Recommendations
The DRV8842-EP is designed to operate from an input voltage supply (VM) range between 8.2 and 45 V. Two
0.1-µF ceramic capacitors rated for VM must be placed as close as possible to the VM pins respectively (one on
each pin). In addition to the local decoupling caps, additional bulk capacitance is required and must be sized
according to the application requirements.
10.1 Bulk Capacitance
Bulk capacitance sizing is an important factor in motor drive system design. It depends on a variety of factors
including:
• Type of power supply
• Acceptable supply voltage ripple
• Parasitic inductance in the power supply wiring
• Type of motor (brushed DC, brushless DC, stepper)
• Motor startup current
• Motor braking method
The inductance between the power supply and motor drive system limits the rate current can change from the
power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or
dumps from the motor with a change in voltage. The designer should size the bulk capacitance to meet
acceptable voltage ripple levels.
The data sheet generally provides a recommended value, but system-level testing is required to determine the
appropriate sized bulk capacitor.
Power Supply
Parasitic Wire
Inductance
Motor Drive System
VM
+
±
+
Motor
Driver
GND
Local
Bulk Capacitor
IC Bypass
Capacitor
Figure 10. Setup of Motor Drive System With External Power Supply
10.2 Power Supply and Logic Sequencing
There is no specific sequence for powering-up the DRV8842-EP. It is okay for digital input signals to be present
before VM is applied. After VM is applied to the DRV8842-EP, the device begins operation based on the status
of the control pins.
16
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11 Layout
11.1 Layout Guidelines
The VM pins should be bypassed to GND using low-ESR ceramic bypass capacitors with a recommended value
of 0.1-μF rated for VM. This capacitor should be placed as close to the VM pins as possible with a thick trace or
ground plane connection to the device GND pin.
The VM pins must be bypassed to ground using an appropriate bulk capacitor. This component may be an
electrolytic and should be located close to the DRV8842-EP.
A low-ESR ceramic capacitor must be placed in between the CPL and CPH pins. TI recommends a value of
0.01-μF rated for VM. Place this component as close to the pins as possible.
A low-ESR ceramic capacitor must be placed in between the VM and VCP pins. TI recommends a value of
0.1-μF rated for 16 V. Place this component as close to the pins as possible. Also, place a 1-MΩ resistor
between VCP and VM.
Bypass V3P3 to ground with a ceramic capacitor rated 6.3 V. Place this bypass capacitor as close to the pin as
possible.
11.2 Layout Example
0.1 µF
CP1
GND
CP2
I4
VCP
I3
VM
I2
OUT1
I1
0.01 µF
1 M
0.1 µF
RISEN
ISEN
I0
OUT2
NC
OUT2
IN1
ISEN
IN2
OUT1
DECAY
VM
nFAULT
VREF
nSLEEP
+
0.1 µF
VREF
nRESET
GND
V3P3OUT
0.47 µF
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12 Device and Documentation Support
12.1 Trademarks
PowerPAD is a trademark of Texas Instruments.
12.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
(4/5)
(6)
DRV8842MPWPREP
ACTIVE
HTSSOP
PWP
28
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-55 to 125
DRV8842EP
V62/14615-01XE
ACTIVE
HTSSOP
PWP
28
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-55 to 125
DRV8842EP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
