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DRV8843
SLVSAS8D – APRIL 2011 – REVISED NOVEMBER 2015
DRV8843 Dual H-Bridge Driver
1 Features
3 Description
•
The DRV8843 provides an integrated dual H-bridge
motor driver solution for printers, scanners, and other
automated equipment applications. The device can
be used to drive one or two brushed DC motors, a
bipolar stepper motor, or other loads. A simple PWM
interface allows easy interfacing to controller circuits.
1
•
•
•
•
•
•
•
•
Dual H-Bridge Motor Driver
– Single/Dual Brushed DC
– Stepper
IN/IN Control Interface
Optional Fixed Frequency Current Regulation
– Two Bit Current control Allows Up to Four
Current Levels
Low MOSFET On-Resistance
– 2.5-A Maximum Drive Current at 24 V
and TA = 25°C
– Combined 400 mΩ RDS(ON) of High-Side and
Low-Side at 24 V and TA = 25°C
8.2-V to 45-V Operating Supply Voltage Range
Low Current Sleep Mode
Built-In 3.3-V Reference Output
Thermally Enhanced Surface Mount Package
Protection Features
– Overcurrent Protection (OCP)
– Thermal Shutdown (TSD)
– Undervoltage Lockout (UVLO)
– Fault Condition Indication Pin (nFAULT)
The output driver block consists of N-channel power
MOSFETs configured as H-bridges. The DRV8843 an
supply up to 2.5-A peak or 1.75-A RMS output
current (with proper heat sinking at 24 V and
TA = 25°C) per H-bridge.
A low-power sleep mode is provided which shuts
down internal circuitry to achieve very low quiescent
current draw. This sleep mode can be set using a
dedicated nSLEEP pin.
Internal protection features are provided for
overtemperature, overcurrent, and undervoltage.
Fault conditions are indicated by a nFAULT pin.
Device Information(1)
PART NUMBER
DRV8843
PACKAGE
HTSSOP (28)
BODY SIZE (NOM)
9.70 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
2 Applications
•
•
•
•
•
•
Printers
Scanners
Office Automation Machines
Gaming Machines
Factory Automation
Robotics
Simplified Schematic
8.2 to 45 V
PWM
Decay Mode
Controller
Current Level
DRV8843
2.5 A
Dual
H-Bridge
Motor Driver
2.5 A
nFAULT
Protection
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRV8843
SLVSAS8D – APRIL 2011 – REVISED NOVEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
5
5
5
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
7.1
7.2
7.3
7.4
Overview ................................................................... 8
Functional Block Diagram ......................................... 8
Feature Description................................................... 9
Device Functional Modes........................................ 10
8
Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Application .................................................. 14
9
Power Supply Recommendations...................... 17
9.1 Bulk Capacitance .................................................... 17
9.2 Power Supply and Logic Sequencing ..................... 17
10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Example .................................................... 18
10.3 Thermal Considerations ........................................ 19
11 Device and Documentation Support ................. 20
11.1
11.2
11.3
11.4
11.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
20
20
20
20
20
12 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
Changes from Revision C (August 2013) to Revision D
•
2
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes section, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section................................................................ 3
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SLVSAS8D – APRIL 2011 – REVISED NOVEMBER 2015
5 Pin Configuration and Functions
PWP Package
28-Pin HTSSOP with PowerPAD™
Top View
CP1
CP2
VCP
VMA
AOUT1
ISENA
AOUT2
BOUT2
ISENB
BOUT1
VMB
AVREF
BVREF
GND
1
28
2
27
3
26
4
25
5
24
6
23
7
GND
(PowerPAD)
8
22
21
9
20
10
19
11
18
12
17
13
16
14
15
GND
BI1
BI0
AI1
AI0
BIN2
BIN1
AIN1
AIN2
DECAY
nFAULT
nSLEEP
nRESET
V3P3OUT
Pin Functions
PIN
NAME
PIN
I/O (1)
EXTERNAL COMPONENTS
OR CONNECTIONS
DESCRIPTION
POWER AND GROUND
GND
14, 28
-
Device ground
VMA
4
-
Bridge A power supply
VMB
11
-
Bridge B power supply
V3P3OUT
15
O
3.3-V regulator output
CP1
1
IO
Charge pump flying capacitor
CP2
2
IO
Charge pump flying capacitor
VCP
3
IO
High-side gate drive voltage
Connect a 0.1-μF 16-V ceramic capacitor and a 1-MΩ
resistor to VM.
AIN1
21
I
Bridge A input 1
Logic input controls state of AOUT1. Internal pulldown.
AIN2
20
I
Bridge A input 2
Logic input controls state of AOUT2. Internal pulldown.
AI0
24
I
Bridge A current set
Sets bridge A current: 00 = 100%,
01 = 71%, 10 = 38%, 11 = 0
Internal pulldown.
Connect to motor supply (8.2 V to 45 V). Both pins must be
connected to the same supply, bypassed with a 0.1-uF
capacitor to GND, and connected to appropriate bulk
capacitance.
Bypass to GND with a 0.47-μF 6.3-V ceramic capacitor. Can
be used to supply VREF.
Connect a 0.01-μF 50-V capacitor between CP1 and CP2.
CONTROL
AI1
25
I
BIN1
22
I
Bridge B input 1
Logic input controls state of BOUT1. Internal pulldown.
BIN2
23
I
Bridge B input 2
Logic input controls state of BOUT2. Internal pulldown.
BI0
26
I
Bridge B current set
Sets bridge B current: 00 = 100%,
01 = 71%, 10 = 38%, 11 = 0
Internal pulldown.
BI1
27
I
DECAY
19
I
Decay mode
Low = slow decay, open = mixed decay,
high = fast decay
Internal pulldown and pullup.
nRESET
16
I
Reset input
Active-low reset input initializes internal logic and disables
the H-bridge outputs. Internal pulldown.
nSLEEP
17
I
Sleep mode input
Logic high to enable device, logic low to enter low-power
sleep mode. Internal pulldown.
AVREF
12
I
Bridge A current set reference input
BVREF
13
I
Bridge B current set reference input
Reference voltage for winding current set. Can be driven
individually with an external DAC for microstepping, or tied
to a reference (e.g., V3P3OUT).
18
OD
Fault
Logic low when in fault condition (overtemp, overcurrent)
STATUS
nFAULT
(1)
Directions: I = input, O = output, OZ = tri-state output, OD = open-drain output, IO = input/output
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Pin Functions (continued)
PIN
NAME
PIN
I/O (1)
EXTERNAL COMPONENTS
OR CONNECTIONS
DESCRIPTION
OUTPUT
ISENA
6
IO
Bridge A ground / Isense
Connect to current sense resistor for bridge A
ISENB
9
IO
Bridge B ground / Isense
Connect to current sense resistor for bridge B
AOUT1
5
O
Bridge A output 1
AOUT2
7
O
Bridge A output 2
BOUT1
10
O
Bridge B output 1
BOUT2
8
O
Bridge B output 2
4
Connect to motor winding A
Connect to motor winding B
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1) (2)
Power supply voltage range
VMx
Power supply ramp rate
VMx
Digital pin voltage range
Input voltage
VREF
ISENSEx pin voltage
(3)
MIN
MAX
UNIT
–0.3
47
V
1
V/µs
–0.5
7
V
–0.3
4
V
–0.8
0.8
V
Peak motor drive output current, t < 1 μS
Internally limited
A
Continuous motor drive output current (4)
0
A
Continuous total power dissipation
2.5
See Thermal Information.
Operating virtual junction temperature range, TJ
–40
150
°C
Operating ambient temperature range, TA
–40
85
°C
Storage Temperature, TSTG
–60
150
°C
(1)
(2)
(3)
(4)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
Transients of ±1 V for less than 25 ns are acceptable.
Power dissipation and thermal limits must be observed.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VM
Motor power supply voltage range (1)
VREF
NOM
MAX
UNIT
8.2
45
VREF input voltage (2)
1
3.5
IV3P3
V3P3OUT load current
0
1
mA
fPWM
Externally applied PWM frequency
0
100
kHz
(1)
(2)
V
V
All VM pins must be connected to the same supply voltage.
Operational at VREF between 0 V and 1 V, but accuracy is degraded.
6.4 Thermal Information
DRV8843
THERMAL METRIC
(1)
PWP (HTSSOP)
UNIT
28 PINS
RθJA
Junction-to-ambient thermal resistance
31.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
15.9
°C/W
RθJB
Junction-to-board thermal resistance
5.6
°C/W
ψJT
Junction-to-top characterization parameter
0.2
°C/W
ψJB
Junction-to-board characterization parameter
5.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.4
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLIES
IVM
VM operating supply current
VM = 24 V, fPWM < 50 kHz
5
8
mA
IVMQ
VM sleep mode supply current
VM = 24 V
10
20
μA
VUVLO
VM undervoltage lockout voltage
VM rising
7.8
8.2
V
3.3
3.4
V
V3P3OUT REGULATOR
V3P3
V3P3OUT voltage
IOUT = 0 to 1 mA
3.2
LOGIC-LEVEL INPUTS
VIL
Input low voltage
VIH
Input high voltage
2.2
0.6
VHYS
Input hysteresis
0.3
IIL
Input low current
VIN = 0
IIH
Input high current
VIN = 3.3 V
RPD
Internal pulldown resistance
0.45
–20
0.7
V
5.25
V
0.6
V
20
μA
100
μA
100
kΩ
nFAULT OUTPUT (OPEN-DRAIN OUTPUT)
VOL
Output low voltage
IO = 5 mA
IOH
Output high leakage current
VO = 3.3 V
0.5
V
1
μA
0.8
V
±40
μA
DECAY INPUT
VIL
Input low threshold voltage
For slow decay (brake) mode
0
VIH
Input high threshold voltage
For fast decay (coast) mode
2
IIN
Input current
RPU
Internal pullup resistance (to 3.3 V)
RPD
Internal pulldown resistance
V
130
kΩ
80
kΩ
H-BRIDGE FETS
HS FET on resistance
RDS(ON)
LS FET on resistance
IOFF
VM = 24 V, IO = 1 A, TJ = 25°C
0.2
VM = 24 V, IO = 1 A, TJ = 85°C
0.25
VM = 24 V, IO = 1 A, TJ = 25°C
0.2
VM = 24 V, IO = 1 A, TJ = 85°C
0.25
Off-state leakage current
–20
0.32
Ω
0.32
20
μA
MOTOR DRIVER
fPWM
Internal current control PWM frequency
50
kHz
tBLANK
Current sense blanking time
tR
Rise time
30
200
ns
tF
Fall time
30
200
ns
160
180
°C
3
μA
μs
3.75
PROTECTION CIRCUITS
IOCP
Overcurrent protection trip level
tTSD
Thermal shutdown temperature
3
Die temperature
150
A
CURRENT CONTROL
IREF
VREF input current
VTRIP
xISENSE trip voltage
AISENSE
Current sense amplifier gain
6
VREF = 3.3 V
–3
xVREF = 3.3 V, 100% current setting
635
660
685
xVREF = 3.3 V, 71% current setting
445
469
492
xVREF = 3.3 V, 38% current setting
225
251
276
Reference only
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5
mV
V/V
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6.6 Typical Characteristics
7
14
6.5
12
IVMQ (PA)
IVM (mA)
6
5.5
10
5
8
-40qC
25qC
85qC
125qC
4.5
4
10
15
20
25
30
V(VMx) (V)
35
40
6
10
45
-40qC
25qC
85qC
125qC
15
Figure 1. IVMx vs V(VMx)
25
30
V(VMx) (V)
35
40
45
D002
Figure 2. IVMxQ vs V(VMx)
750
750
-40qC
25qC
85qC
125qC
700
RDS(ON) HS + LS (m:)
700
RDS(ON) HS + LS (m:)
20
D001
650
600
550
500
450
650
600
550
500
8V
24 V
45 V
450
400
8
13
18
23
28
V(VMx) (V)
33
38
400
-50
43
D003
Figure 3. RDS(ON) vs V(VMx)
-25
0
25
50
TA (qC)
75
100
125
D004
Figure 4. RDS(ON) vs Temperature
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7 Detailed Description
7.1 Overview
The DRV8843 is an integrated motor driver solution for two brushed DC motors or a bipolar stepper motor. The
device integrates two power NMOS H-bridges, current sense and regulation circuitry, protection devices, and a
digital interface.
A simple PWM interface allows for easy interfacing to an external digital controller and requires minimal
resources. The fault indication pin (nFAULT) provides a flag for when the device has entered a fault state.
The current regulation is highly configurable with three modes of operation. Depending on the applications
requirements the device can be configured for fast, slow, or mixed decay. Two bit current level control allows the
device to switch between four different current levels.
A low-power sleep mode is implemented which allows the system to save power when not driving the motor.
7.2 Functional Block Diagram
Vcc
LS Gate
Drive
HS Gate
Drive
Low-Side
LDO
Charge
Pump
VM
VCP
+
3.3V
V3P3OUT
3.3V
3.3V
LDO
VM
Bulk
Capacitor
CP1
Internal
Logic
LDO
AVREF
CP2
VM
AVREF
VMA
LS Gate HS Gate
Drive
Drive
BVREF
Vcc
BVREF
AIN1
AOUT1
AIN2
AI0
Gate
Drive
BDC
Motor
VM
AI1
AOUT2
BIN1
AVREF
BIN2
RSENSE
(optional)
ISENA
ISENA
BI0
LS Gate HS Gate
Drive
Drive
Control
Logic
BI1
VM
VM
Stepper
Motor
VMB
nRESET
BOUT1
nSLEEP
V3P3OUT
Gate
Drive
DECAY
BDC
Motor
VM
nFAULT
BOUT2
BVREF
RSENSE
(optional)
ISENB
Thermal
Sensor
ISENB
GND
8
PPAD
GND
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7.3 Feature Description
7.3.1 PWM Motor Drivers
The DRV8843 contains two H-bridge motor drivers with current-control PWM circuitry. A block diagram of the
motor control circuitry is shown in Figure 5.
VM
OCP
VM
VCP, VGD
AOUT1
Predrive
AIN1
DCM
AIN2
AOUT2
DECAY
PWM
OCP
AISEN
+
AI[1:0]
A=5
DAC
2
AVREF
VM
OCP
VM
VCP, VGD
BOUT1
Predrive
BIN1
DCM
BIN2
BOUT2
PWM
OCP
BISEN
+
BI[1:0]
A =5
DAC
2
BVREF
Figure 5. Motor Control Circuitry
NOTE
There are multiple VM pins. All VM pins must be connected together to the motor supply
voltage.
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7.4 Device Functional Modes
7.4.1 Bridge Control
The AIN1 and AIN2 input pins directly control the state of the AOUT1 and AOUT2 outputs; similarly, the BIN1
and BIN2 input pins directly control the state of the BOUT1 and BOUT2 outputs. Either input can also be used
for PWM control of the load. Table 1 shows the logic.
Table 1. H-Bridge Logic
xIN1
xIN2
xOUT1
0
0
Z
xOUT2
Z
0
1
L
H
1
0
H
L
1
1
L
L
The inputs can also be used for PWM control of the motor speed. When controlling a winding with PWM, when
the drive current is interrupted, the inductive nature of the motor requires that the current must continue to flow.
This is called recirculation current. To handle this recirculation current, the H-bridge can operate in two different
states, fast decay or slow decay. In fast decay mode, the H-bridge is disabled and recirculation current flows
through the body diodes; in slow decay, the motor winding is shorted.
To PWM using fast decay, the PWM signal is applied to one xIN pin while the other is held low; to use slow
decay, one xIN pin is held high.
The control inputs have internal pulldown resistors of approximately 100 kΩ.
Table 2. PWM Function
xIN1
xIN2
FUNCTION
PWM
0
Forward PWM, fast decay
1
PWM
Forward PWM, slow decay
0
PWM
Reverse PWM, fast decay
PWM
1
Reverse PWM, slow decay
Figure 6 shows the current paths in different drive and decay modes.
VM
VM
1 Forward drive
1
xOUT2
xOUT1
1 Reverse drive
1
2 Fast decay
3 Slow decay
xOUT1
2
2
3
3
FORWARD
2 Fast decay
xOUT2
3 Slow decay
REVERSE
Figure 6. Current Paths
10
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7.4.2 Current Regulation
The current through the motor windings is regulated by a fixed-frequency PWM current regulation, or current
chopping. When an H-bridge is enabled, current rises through the winding at a rate dependent on the DC voltage
and inductance of the winding. Once the current hits the current chopping threshold, the bridge disables the
current until the beginning of the next PWM cycle.
For stepping motors, current regulation is normally used at all times, and can changing the current can be used
to microstep the motor. For DC motors, current regulation is used to limit the start-up and stall current of the
motor.
If the current regulation feature is not needed, it can be disabled by connecting the xISENSE pins directly to
ground and connecting the xVREF pins to V3P3.
The PWM chopping current is set by a comparator which compares the voltage across a current sense resistor
connected to the xISEN pins, multiplied by a factor of 5, with a reference voltage. The reference voltage is input
from the xVREF pins, and is scaled by a 2-bit DAC that allows current settings of 100%, 71%, 38% of full-scale,
plus zero.
The full-scale (100%) chopping current is calculated in Equation 1.
VREFX
ICHOP
5 u RISENSE
(1)
Example:
If a 0.25-Ω sense resistor is used and the VREFx pin is 2.5 V, the full-scale (100%) chopping current will be
2.5 V / (5 x 0.25 Ω) = 2 A.
Two input pins per H-bridge (xI1 and xI0) are used to scale the current in each bridge as a percentage of the fullscale current set by the VREF input pin and sense resistance. The xI0 and xI1 pins have internal pulldown
resistors of approximately 100 kΩ. The function of the pins is shown in Table 3.
Table 3. H-Bridge Pin Functions
xI1
xI0
RELATIVE CURRENT
(% FULL-SCALE CHOPPING CURRENT)
1
1
0% (Bridge disabled)
1
0
38%
0
1
71%
0
0
100%
NOTE
When both xI bits are 1, the H-bridge is disabled and no current flows.
Example:
If a 0.25-Ω sense resistor is used and the VREF pin is 2.5 V, the chopping current will
be 2 A at the 100% setting (xI1, xI0 = 00). At the 71% setting (xI1, xI0 = 01) the
current will be 2 A x 0.71 = 1.42 A, and at the 38% setting (xI1, xI0 = 10) the current
will be 2 A x 0.38 = 0.76 A. If (xI1, xI0 = 11) the bridge will be disabled and no current
will flow.
7.4.3 Decay Mode During Current Chopping
During PWM current chopping, the H-bridge is enabled to drive current through the motor winding until the PWM
current chopping threshold is reached. This is shown in Figure 7 as case 1. The current flow direction shown
indicates the state when the xIN1 pin is high and the xIN2 pin is low.
Once the chopping current threshold is reached, the H-bridge can operate in two different states, fast decay or
slow decay.
In fast decay mode, once the PWM chopping current level has been reached, the H-bridge reverses state to
allow winding current to flow in a reverse direction. As the winding current approaches zero, the bridge is
disabled to prevent any reverse current flow. Fast decay mode is shown in Figure 7 as case 2.
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In slow decay mode, winding current is re-circulated by enabling both of the low-side FETs in the bridge. This is
shown in Figure 7 as case 3.
Figure 7. Decay Mode
The DRV8843 supports fast decay, slow decay and a mixed decay mode during current chopping. Slow, fast, or
mixed decay mode is selected by the state of the DECAY pin - logic low selects slow decay, open selects mixed
decay operation, and logic high sets fast decay mode. The DECAY pin has both an internal pullup resistor of
approximately 130-kΩ and an internal pulldown resistor of approximately 80-kΩ. This sets the mixed decay mode
if the pin is left open or undriven. Note that the DECAY pin sets the decay mode for both H-bridges.
Mixed decay mode begins as fast decay, but at a fixed period of time (75% of the PWM cycle) switches to slow
decay mode for the remainder of the fixed PWM period.
7.4.4 Blanking Time
After the current is enabled in an H-bridge, the voltage on the xISEN pin is ignored for a fixed period of time
before enabling the current sense circuitry. This blanking time is fixed at 3.75 μs. Note that the blanking time also
sets the minimum on time of the PWM.
7.4.5 nRESET and nSLEEP Operation
The nRESET pin, when driven active low, resets the internal logic. It also disables the H-bridge drivers. All inputs
are ignored while nRESET is active.
Driving nSLEEP low will put the device into a low power sleep state. In this state, the H-bridges are disabled, the
gate drive charge pump is stopped, the V3P3OUT regulator is disabled, and all internal clocks are stopped. In
this state all inputs are ignored until nSLEEP returns inactive high. When returning from sleep mode, some time
(approximately 1 ms) needs to pass before the motor driver becomes fully operational. Note that nRESET and
nSLEEP have internal pulldown resistors of approximately 100 kΩ. These signals need to be driven to logic high
for device operation.
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7.4.6 Protection Circuits
The DRV8843 is fully protected against undervoltage, overcurrent and overtemperature events.
7.4.6.1 Overcurrent Protection (OCP)
An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this
analog current limit persists for longer than the OCP time, all FETs in the H-bridge will be disabled and the
nFAULT pin will be driven low. The device will remain disabled until either nRESET pin is applied, or VM is
removed and re-applied.
Overcurrent conditions on both high and low side devices; i.e., a short to ground, supply, or across the motor
winding will all result in an overcurrent shutdown. Note that overcurrent protection does not use the current sense
circuitry used for PWM current control, and is independent of the ISENSE resistor value or VREF voltage.
7.4.6.2 Thermal Shutdown (TSD)
If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled and the nFAULT pin will be
driven low. Once the die temperature has fallen to a safe level operation will automatically resume.
7.4.6.3 Undervoltage Lockout (UVLO)
If at any time the voltage on the VM pins falls below the undervoltage lockout threshold voltage, all circuitry in the
device will be disabled and internal logic will be reset. Operation will resume when VM rises above the UVLO
threshold.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DRV8843 can be used to control a bipolar stepper motor. The PWM interface controls the outputs and
current control can be implemented with the internal current regulation circuitry. Detailed fault reporting is
provided with the internal protection circuits and nFAULT pin.
8.2 Typical Application
DRV8843
CP1
GND
CP2
BI1
VCP
BI0
VMA
AI1
AOUT1
AI0
0.01 µF
0.01 µF
0.1 µF
+
1 MΩ
200 mΩ
Stepper Motor
-
VM
100 µF
+
ISENA
BIN2
AOUT2
BIN1
BOUT2
AIN1
ISENB
AIN2
-
+
200 mΩ
V3P3OUT
BOUT1
DECAY
VMB
nFAULT
AVREF
nSLEEP
10 kΩ
0.01 µF
V3P3OUT
10 kΩ
BVREF
GND
nRESET
PPAD
30 kΩ
V3P3OUT
V3P3OUT
0.47 µF
Figure 8. Typical Application Schematic
8.2.1 Design Requirements
Specific parameters for designing a dual brushed DC motor drive system.
Table 4. Design Parameters
REFERENCE
EXAMPLE VALUE
Supply Voltage
DESIGN PARAMETER
VM
24 V
Motor Winding Resistance
RL
3.9 Ω
Motor Winding Inductance
IL
2.9 mH
RSENSE
200 mΩ
IFS
1.25 A
Sense Resistor Value
Target Full-Scale Current
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8.2.2 Detailed Design Procedure
8.2.2.1 Current Regulation
In a stepper motor, the set full-scale current (IFS) is the maximum current driven through either winding. This
quantity depends on the xVREF analog voltage and the sense resistor value (RSENSE). During stepping, IFS
defines the current chopping threshold (ITRIP) for the maximum current step. The gain of DRV8843 is set for 5
V/V.
xVREF(V)
xVREF(V)
IFS (A)
A v u RSENSE (:) 5 u RSENSE (:)
(2)
To achieve IFS = 1.25 A with RSENSE of 0.2 Ω, xVREF should be 1.25 V.
8.2.2.2 Decay Modes
The DRV8843 supports three different decay modes: slow decay, fast decay, and mixed decay. The current
through the motor windings is regulated using a fixed-frequency PWM scheme. This means that after any drive
phase, when a motor winding current has hit the current chopping threshold (ITRIP), the DRV8843 will place the
winding in one of the three decay modes until the PWM cycle has expired. Afterward, a new drive phase starts.
The blanking time, tBLANK, defines the minimum drive time for the current chopping. ITRIP is ignored during tBLANK,
so the winding current may overshoot the trip level.
8.2.2.3 Sense Resistor
For optimal performance, it is important for the sense resistor to be:
• Surface-mount
• Low inductance
• Rated for high enough power
• Placed closely to the motor driver
The power dissipated by the sense resistor equals Irms2 x R. For example, if the rms motor current is 2-A and a
100-m Ω sense resistor is used, the resistor will dissipate 2 A ² × 0.1 Ω = 0.4 W. The power quickly increases
with greater current levels.
Resistors typically have a rated power within some ambient temperature range, along with a de-rated power
curve for high ambient temperatures. When a PCB is shared with other components generating heat, margin
should be added. It is always best to measure the actual sense resistor temperature in a final system, along with
the power MOSFETs, as those are often the hottest components.
Because power resistors are larger and more expensive than standard resistors, it is common practice to use
multiple standard resistors in parallel, between the sense node and ground. This distributes the current and heat
dissipation.
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8.2.3 Application Curves
Figure 10. Direction Change
Figure 9. Current Limiting
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9 Power Supply Recommendations
The DRV8843 is designed to operate from an input voltage supply (VMx) range between 8.2 and 45 V. Two
0.1-µF ceramic capacitors rated for VMx must be placed as close as possible to the VMA and VMB pins
respectively (one on each pin). In addition to the local decoupling caps, additional bulk capacitance is required
and must be sized accordingly to the application requirements.
9.1 Bulk Capacitance
Bulk capacitance sizing is an important factor in motor drive system design. It is dependent on a variety of factors
including:
• Type of power supply
• Acceptable supply voltage ripple
• Parasitic inductance in the power supply wiring
• Type of motor (brushed DC, brushless DC, stepper)
• Motor startup current
• Motor braking method
The inductance between the power supply and motor drive system will limit the rate current can change from the
power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands or
dumps from the motor with a change in voltage. You should size the bulk capacitance to meet acceptable
voltage ripple levels.
The data sheet generally provides a recommended value but system level testing is required to determine the
appropriate sized bulk capacitor.
Parasitic Wire
Inductance
Motor Drive System
Power Supply
VM
+
–
Motor
Motor
Driver
Driver
+
GND
Local
Bulk Capacitor
IC Bypass
Capacitor
Figure 11. Setup of Motor Drive System With External Power Supply
9.2 Power Supply and Logic Sequencing
There is no specific sequence for powering-up the DRV8843. It is okay for digital input signals to be present
before VMx is applied. After VMx is applied to the device, it begins operation based on the status of the control
pins.
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10 Layout
10.1 Layout Guidelines
The VMA and VMB pins should be bypassed to GND using low-ESR ceramic bypass capacitors with a
recommended value of 0.1-μF rated for VMx. This capacitor should be placed as close to the VMA and VMB pins
as possible with a thick trace or ground plane connection to the device GND pin.
The VMA and VMB pins must be bypassed to ground using an appropriate bulk capacitor. This component may
be an electrolytic and should be located close to the DRV8843.
A low-ESR ceramic capacitor must be placed in between the CPL and CPH pins. TI recommends a value of
0.01-μF rated for VMx. Place this component as close to the pins as possible.
A low-ESR ceramic capacitor must be placed in between the VMA and VCP pins. TI recommends a value of 0.1μF rated for 16 V. Place this component as close to the pins as possible. Also, place a 1-MΩ resistor between
VCP and VMA.
Bypass V3P3 to ground with a ceramic capacitor rated 6.3 V. Place this bypass capacitor as close to the pin as
possible
10.2 Layout Example
GND
100 mΩ
GND
0.1 µF
ISENA
VMA
HOMEn
SLEEPn
DIR
ENABLE
AOUT1
AOUT2
DECAY
CP2
RCA
CP1
VM
0.22 µF
VCC
100 mΩ
GND
GND
VCP
VREF
GND
RCB
VGD
VCC
STEP
BOUT1
BOUT2
USM1
RESETn
USM0
SRn
ISENB
VMB
GND
0.22 µF
0.22 µF
VM
0.1 µF
GND
Figure 12. DRV8843 Layout Example
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10.3 Thermal Considerations
10.3.1 Thermal Protection
The DRV8843 has thermal shutdown (TSD) as described in Thermal Shutdown (TSD). If the die temperature
exceeds approximately 150°C, the device will be disabled until the temperature drops to a safe level.
Any tendency of the device to enter TSD is an indication of either excessive power dissipation, insufficient
heatsinking, or too high an ambient temperature.
10.3.2 Power Dissipation
Power dissipation in the DRV8843 is dominated by the power dissipated in the output FET resistance, or
RDS(ON). Average power dissipation of each H-bridge when running a DC motor can be roughly estimated by
Equation 3.
P
2 u RDS(ON) u IOUT
2
where
•
•
•
P is the power dissipation of one H-bridge
RDS(ON) is the resistance of each FET
IOUT is the RMS output current being applied to each winding
(3)
IOUT is equal to the average current drawn by the DC motor. Note that at start-up and fault conditions this current
is much higher than normal running current; these peak currents and their duration also need to be taken into
consideration. The factor of 2 comes from the fact that at any instant two FETs are conducting winding current
(one high-side and one low-side).
The total device dissipation will be the power dissipated in each of the two H-bridges added together.
The maximum amount of power that can be dissipated in the device is dependent on ambient temperature and
heatsinking.
NOTE
RDS(ON) increases with temperature, so as the device heats, the power dissipation
increases. This must be taken into consideration when sizing the heatsink.
10.3.3 Heatsinking
The PowerPAD™ package uses an exposed pad to remove heat from the device. For proper operation, this pad
must be thermally connected to copper on the PCB to dissipate heat. On a multi-layer PCB with a ground plane,
this can be accomplished by adding a number of vias to connect the thermal pad to the ground plane. On PCBs
without internal planes, copper area can be added on either side of the PCB to dissipate heat. If the copper area
is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat between top and
bottom layers.
For details about how to design the PCB, refer to TI application report PowerPAD™ Thermally Enhanced
Package, SLMA002, and TI application brief PowerPAD™ Made Easy, SLMA004, available at www.ti.com.
In general, the more copper area that can be provided, the more power can be dissipated.
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• PowerPAD™ Thermally Enhanced Package, SLMA002
• PowerPAD™ Made Easy, SLMA004
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
DRV8843PWP
ACTIVE
HTSSOP
PWP
28
50
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
DRV8843
DRV8843PWPR
ACTIVE
HTSSOP
PWP
28
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
DRV8843
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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