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DRV8847
SLVSE65B – JULY 2018 – REVISED SEPTEMBER 2019
DRV8847 Dual H-Bridge Motor Driver
1 Features
3 Description
•
The DRV8847 device is a dual H-bridge motor driver
for industrial applications, home appliances, ePOS
printers, and other mechatronic applications. This
device can be used for driving two DC motors, a
bipolar stepper motor, or other loads such as relays.
A simple PWM interface allows easy interface with
the controller. The DRV8847 device operates off a
single power supply and supports a wide input supply
range from 2.7 to 18 V.
1
•
•
•
•
•
•
•
•
•
•
•
Dual H-bridge motor driver
– Single or dual brushed DC motors
– One bipolar stepper motor
– Solenoid loads
2.7-V to 18-V operating voltage range
High output current per H-bridge
– 1-A RMS driver current at TA = 25°C
– 2-A RMS driver current in parallel mode at TA
= 25°C
Low on-state resistance at VM > 5-V
– 1000 mΩ RDS(ON) (HS + LS) at TA = 25°C
Multiple control interface options
– 4-Pin interface
– 2-Pin interface
– Parallel bridge interface
– Independent bridge interface
Current regulation with 20-μs fixed off time
Torque scalar for scaling output current to 50%
Supports 1.8-V, 3.3-V, 5-V logic inputs
Low-power sleep mode
– 1.7-µA Sleep mode supply current at VVM =
12-V, TA = 25°C
I2C Device Variant Available (DRV8847S)
– Detailed diagnostics on I2C registers
– Multi-slave operation support
– Supports standard and fast I2C mode
Small packages and footprints
– 16 Pin TSSOP (no thermal pad)
– 16 Pin HTSSOP PowerPAD™ package
– 16 Pin WQFN thermal package
Built-in protection features
– VM undervoltage lockout
– Overcurrent protection
– Open load detection
– Thermal shutdown
– Fault condition indication pin (nFAULT)
The output stage of the driver consists of N-channel
power MOSFETs configured as two full H-bridges to
drive motor windings or four independent half bridges
(in independent bridge interface). A fixed off time
controls the peak current in the bridge which can
drive a 1-A load (2-A in parallel mode with proper
heat sinking, at 25°C TA).
A low-power sleep mode is provided to achieve a low
quiescent current draw by shutting down much of the
internal circuitry. Additionally, a torque scalar is
provided which dynamically scales the output current
through a digital input pin. This feature lets the
controller decrease the current required for lower
power consumption.
Internal protection functions are provided for
undervoltage-lockout, overcurrent protection on each
FET, short circuit protection, open-load detection, and
overtemperature. Fault conditions are indicated by on
the nFAULT pin. The I2C device variant (DRV8847S)
has detailed diagnostics.
Device Information(1)
PART NUMBER
DRV8847
DRV8847S
Refrigerator damper and ice maker
Washers, dryers and dishwashers
Electronic point-of-sale (ePOS) printers
Stage lighting equipment
Miniature circuit breakers and smart meters
BODY SIZE (NOM)
HTSSOP (16)
5.00 mm × 4.40 mm
TSSOP (16)
5.00 mm × 4.40 mm
WQFN (16)
3.00 mm × 3.00 mm
TSSOP (16)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
2.7 to 18 V
2 Applications
•
•
•
•
•
PACKAGE
Controller
INx
DRV8847
nSLEEP
Dual H-Bridge Driver
1A
nFAULT
Stepper
TRQ
Current Regulation
1A
MODE
Built-in Protection
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRV8847
SLVSE65B – JULY 2018 – REVISED SEPTEMBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
7
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 6
Electrical Characteristics........................................... 7
I2C Timing Requirements ......................................... 8
Typical Characteristics ............................................ 11
Detailed Description ............................................ 14
7.1
7.2
7.3
7.4
7.5
2
1
1
1
3
4
6
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
14
15
17
39
41
7.6 Register Map........................................................... 43
8
Application and Implementation ........................ 48
8.1 Application Information............................................ 48
8.2 Typical Application ................................................. 48
9
Power Supply Recommendations...................... 60
9.1 Bulk Capacitance Sizing ......................................... 60
10 Layout................................................................... 61
10.1
10.2
10.3
10.4
Layout Guidelines .................................................
Layout Example ....................................................
Thermal Considerations ........................................
Power Dissipation .................................................
61
61
63
63
11 Device and Documentation Support ................. 64
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
64
64
64
64
64
64
12 Mechanical, Packaging, and Orderable
Information ........................................................... 64
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SLVSE65B – JULY 2018 – REVISED SEPTEMBER 2019
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (July 2018) to Revision B
Page
•
Changed the Low On-State Resistance to be the indicated value when VM > 5 V............................................................... 1
•
Changed nFAULT pin type to OD/I ........................................................................................................................................ 5
•
Changed VM description to indicate 0.1-uF capacitor should be ceramic ............................................................................. 5
•
Changed digital pin voltage (IN1, IN2, IN3, IN4, TRQ, nSLEEP, nFAULT, SCL, SDA) maximum voltage from 5.5 V
to 5.75 V ................................................................................................................................................................................. 6
•
Changed the Phase node pin voltage specification’s name to Continuous phase node pin voltage .................................... 6
•
Added for ISEN12, ISEN34 specification a footnote stating transients of +- 1V for less than 25 ns are acceptable ........... 6
•
Added for both Peak drive current (OUT1, OUT2, OUT3, OUT4) specifications a footnote stating Power dissipation
and thermal limits must be observed ..................................................................................................................................... 6
•
Changed V(ESD) specification’s value to 4000 V .................................................................................................................. 6
•
Changed the VIL specification to be two specifications based on test conditions VM < 7 V and VM >= 7 V......................... 7
•
Changed the IIH specification’s minimum value to 18 uA for test condition IN1, IN2, IN3, IN4, TRQ, VIN = 5 V and to
10 uA for test condition nSLEEP, VIN = minimum (VM, 5 V) ................................................................................................. 7
•
Added to IOCP specification a minimum value......................................................................................................................... 8
•
Changed pin naming of Block Diagram for DRV8847S figure ............................................................................................. 16
•
Deleted ceramic from CVM1 .................................................................................................................................................. 17
•
Changed the relay or solenoid coils load bullet item for more clarity................................................................................... 24
•
Added sentence to clarify nFAULT pin behavior when open load is detected .................................................................... 36
•
Added sentence to clarify nFAULT pin behavior during power-up ...................................................................................... 39
•
Added an Open Load Implementation section ..................................................................................................................... 53
•
Added a Layout Recommendation of 16-Pin QFN Package for Double Layer Board figure .............................................. 62
Changes from Original (July 2018) to Revision A
Page
•
Changed the data sheet status from Advance Information to Production Data .................................................................... 1
•
Changed pin naming on Layout Recommendation of 16-Pin HTSSOP Package for Double Layer Board figure .............. 61
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3
DRV8847
SLVSE65B – JULY 2018 – REVISED SEPTEMBER 2019
www.ti.com
5 Pin Configuration and Functions
DRV8847 PW Package
16-Pin TSSOP
Top View
DRV8847 PWP PowerPAD™ Package
16-Pin HTSSOP
Top View
nSLEEP
1
16
IN1
nSLEEP
1
16
IN1
OUT1
2
15
IN2
OUT1
2
15
IN2
ISEN12
3
14
MODE
ISEN12
3
14
MODE
OUT2
4
13
GND
OUT2
4
13
GND
12
VM
Thermal
OUT4
5
12
VM
ISEN34
6
11
TRQ
OUT3
7
10
nFAULT
8
9
OUT4
5
ISEN34
6
11
TRQ
IN4
OUT3
7
10
IN4
IN3
nFAULT
8
9
IN3
Not to scale
Not to scale
1
OUT2
2
IN2
DRV8847S PW Package
16-Pin TSSOP
Top View
13
IN1
14
nSLEEP
15
16
OUT1
DRV8847 RTE Package
16-Pin WQFN With Exposed Thermal Pad
Top View
ISEN12
16
IN1
OUT1
2
15
IN2
ISEN12
3
14
SDA
OUT2
4
13
GND
11
GND
OUT4
5
12
VM
10
VM
ISEN34
6
11
SCL
OUT3
7
10
IN4
nFAULT
8
9
IN3
TRQ
8
IN4
7
IN3
OUT3
4
1
MODE
9
6
4
nFAULT
ISEN34
Pad
5
3
nSLEEP
12
Thermal
OUT4
Pad
Not to scale
Not to scale
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SLVSE65B – JULY 2018 – REVISED SEPTEMBER 2019
Pin Functions
PIN
DRV8847
NAME
DRV8847S
TYPE (1)
DESCRIPTION
TSSOP
HTSSOP
WQFN
TSSOP
GND
13
11
13
PWR
IN1
16
14
16
I
Half-bridge input 1
IN2
15
13
15
I
Half-bridge input 2
IN3
9
7
9
I
Half-bridge input 3
IN4
10
8
10
I
Half-bridge input 4
ISEN12
3
1
3
O
Full-bridge-12 sense. Connect this pin to the current sense resistor for fullbridge-12. Connect this pin to the GND pin if current regulation is not
required.
ISEN34
6
4
6
O
Full-bridge-34 sense. Connect this pin to the to current sense resistor for
full-bridge-34. Connect this pin to the GND pin if current regulation is not
required.
MODE
14
12
—
I
Tri-state pin for selection of driver operating mode
nFAULT
8
6
8
OD / I
Fault indication pin. This pin is pulled logic low with a fault condition. This
open-drain output requires an external pullup resistor. This pin is also
used as an input pin for the DRV8847S device for releasing the I2C bus.
nSLEEP
1
15
1
I
Sleep mode input. Set this pin to logic high to enable the device. Set this
pin to logic low to go to low-power sleep mode
OUT1
2
16
2
O
Half-bridge output 1
OUT2
4
2
4
O
Half-bridge output 2
OUT3
7
5
7
O
Half-bridge output 3
OUT4
5
3
5
O
Half-bridge output 4
SCL
—
—
11
I
I2C clock signal.
SDA
—
—
14
OD
TRQ
11
9
—
I
VM
12
10
12
PWR
(1)
Device ground. Recommended to connect the GND pin and device
thermal pad (HTSSOP and WQFN packages) to ground
I2C data signal. The SDA pin requires a pullup resistor.
Torque current scalar
Power supply. Connect the VM pin to the motor power supply. Bypass this
pin to ground with a VM-rated 0.1-µF (ceramic) and 10-μF (minimum)
capacitor.
I = input, O = output, OD = open-drain output, PWR = power
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DRV8847
SLVSE65B – JULY 2018 – REVISED SEPTEMBER 2019
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted) (1)
Power supply pin voltage (VM)
MIN
MAX
-0.3
20
V
V/µs
Power supply voltage ramp rate (VM)
UNIT
0
2
Digital pin voltage (IN1, IN2, IN3, IN4, TRQ, nSLEEP, nFAULT, SCL, SDA)
-0.3
5.75
V
Continuous phase node pin voltage (OUT1, OUT2, OUT3, OUT4)
-0.7
VM + 0.6
V
-0.6
0.6
V
Shunt amplifier input pin voltage (ISEN12, ISEN34)
(2)
Peak drive current (OUT1, OUT2, OUT3, OUT4), VVM 16.5 V (3)
A
0
4
A
Ambient temperature, TA
-40
125
°C
Junction temperature, TJ
-40
150
°C
Storage temperature, Tstg
-65
150
°C
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Transients of ±1 V for less than 25 ns are acceptable.
Power dissipation and thermal limits must be observed.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001, all pins (1)
±4000
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over operating ambient temperature range (unless otherwise noted). Typical limits apply for TA = 25°C and VVM = 12 V.
MIN
VVM
Power supply voltage (VM)
VIN
IRMS
NOM
MAX
UNIT
2.7
18
V
Logic input voltage (IN1, IN2, IN3, IN4, TRQ, nSLEEP, SCL, SDA)
0
5
V
Motor RMS current per bridge (OUT1, OUT2, OUT3, OUT4)
0
1 (1)
A
(1)
fPWM
PWM frequency (IN1, IN2, IN3, IN4)
0
VOD
Open drain pullup voltage (nFAULT)
0
5
V
IOD
Open drain output current (nFAULT)
0
5
mA
TA
Operating Ambient Temperature
-40
85
°C
TJ
Operating Junction Temperature
-40
150
°C
(1)
250
kHz
Power dissipation and thermal limits must be observed. Dependent on the package thermal performance.
6.4 Thermal Information
THERMAL METRIC (1)
DRV8847, DRV8847S
DRV8847
DRV8847
PW (TSSOP)
PWP (HTSSOP)
RTE (QFN)
UNIT
16 PINS
16 PINS
16 PINS
RθJA
Junction-to-ambient thermal resistance
107.9
46.5
46.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
38.5
40.1
47.5
°C/W
RθJB
Junction-to-board thermal resistance
54.2
18.8
21.2
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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Thermal Information (continued)
THERMAL METRIC (1)
DRV8847, DRV8847S
DRV8847
DRV8847
PW (TSSOP)
PWP (HTSSOP)
RTE (QFN)
16 PINS
16 PINS
16 PINS
UNIT
ΨJT
Junction-to-top characterization parameter
3.1
1.3
0.9
°C/W
ΨJB
Junction-to-board characterization parameter
53.6
19.0
21.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
5.9
6.1
°C/W
6.5 Electrical Characteristics
Over recommended operating conditions unless otherwise noted. Typical limits apply for TA = 25°C and VVM = 12 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VM = 2.7 V; nSLEEP = 1; INX = 0
2
2.5
mA
VM = 5 V; nSLEEP = 1; INX = 0
3
3.5
mA
VM = 12 V; nSLEEP = 1; INX = 0
3
3.5
mA
POWER SUPPLIES (VM)
IVM
VM operating supply current
VM = 2.7 V; nSLEEP = 0; TA = 25°C
0.1
VM = 2.7 V; nSLEEP = 0; TA = 85°C
IVMQ
VM sleep mode current
µA
0.5
VM = 5 V; nSLEEP = 0; TA = 25°C
0.2
VM = 5 V; nSLEEP = 0; TA = 85°C
µA
1
VM = 12 V; nSLEEP = 0; TA = 25°C
1.7
VM = 12 V; nSLEEP = 0; TA = 85°C
µA
µA
µA
2.5
µA
nSLEEP = 1 to output transition
1.5
ms
VM > UVLO to output transition
(nSLEEP = 1)
1.5
ms
0
0.6
V
0
1.0
V
1.6
5.5
tSLEEP
Sleep time
nSLEEP = 0 to sleep mode
tWAKE
Wake-up time
tON
Turnon-time
2
µs
LOGIC-LEVEL INPUTS (IN1, IN2, IN3, IN4, NSLEEP, TRQ, SCL, SDA)
VM < 7 V
VIL
Input logic low voltage
VIH
Input logic high voltage
VHYS
Input logic hysteresis
nSLEEP pin
VHYS
Input logic hysteresis
IN1, IN2, IN3, IN4, TRQ, SCL pins
IIL
Input logic low current
VIN = 0 V
-1
1
µA
IN1, IN2, IN3, IN4, TRQ, VIN = 5 V
18
35
µA
25
µA
600
ns
IIH
Input logic high current
tPD
Propagation Delay
tDEGLITCH
Input logic deglitch
VM >= 7 V
(1)
nSLEEP, VIN = minimum (VM, 5 V)
INx edge to output
40
100
mV
10
100
V
mV
400
50
ns
TRI-LEVEL INPUTS (MODE)
VIL
Tri-level input logic low voltage
VIZ
Tri-level input hi-Z voltage
0
VIH
Tri-level input logic high voltage
IIL
Tri-level input logic low current
VIN = 0 V
IIH
Tri-level input logic high current
VIN = 5 V
0.6
1.2
1.6
V
V
5.5
V
-9
-4
µA
8
25
µA
OPEN-DRAIN OUTPUTS (nFAULT)
VOL
Output logic low voltage
IOD = 5 mA
IOH
Output logic high current
VOD = 3.3 V
-1
0.5
V
1
µA
0.5
V
1
µA
OPEN-DRAIN OUTPUTS (SDA)
VOL
Output logic low voltage
IOD = 5 mA
IOH
Output logic high current
VOD = 3.3 V
(1)
-1
Specified by design and characterization
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Electrical Characteristics (continued)
Over recommended operating conditions unless otherwise noted. Typical limits apply for TA = 25°C and VVM = 12 V.
PARAMETER
CB
TEST CONDITIONS
MIN
TYP
Capacitive load for each bus line
MAX
UNIT
400
pF
DRIVER OUTPUTS (OUT1, OUT2, OUT3, OUT4)
VVM = 2.7 V; IOUT = 0.5 A; TA = 25°C
690
VVM = 2.7 V; IOUT = 0.5 A; TA = 85°C
RDS(ON)_HS High-side MOSFET on resistance
950
VVM = 5 V; IOUT = 0.5 A; TA = 25°C
530
VVM = 5 V; IOUT = 0.5 A; TA = 85°C
520
VVM = 12 V; IOUT = 0.5 A; TA = 85°C
570
VVM = 2.7 V; IOUT = 0.5 A; TA = 85°C
460
VVM = 5 V; IOUT = 0.5 A; TA = 85°C
450
VVM = 12 V; IOUT = 0.5 A; TA = 85°C
mΩ
mΩ
690
VVM = 12 V; IOUT = 0.5 A; TA = 25°C
mΩ
mΩ
900
VVM = 5 V; IOUT = 0.5 A; TA = 25°C
mΩ
mΩ
700
VVM = 2.7 V; IOUT = 0.5 A; TA = 25°C
mΩ
mΩ
740
VVM = 12 V; IOUT = 0.5 A; TA = 25°C
RDS(ON)_LS Low-side MOSFET on resistance
mΩ
mΩ
mΩ
680
mΩ
1
µA
IOFF
Off-state leakage current
VVM = 5 V; TJ = 25 °C; VOUT = 0 V
-1
tRISE
Output rise time
VVM = 12 V; IOUT = 0.5 A
150
ns
tFALL
Output fall time
VVM = 12 V, IOUT = 0.5 A
150
ns
tDEAD
Output dead time
Internal dead time
200
ns
VSD
Body diode forward voltage
IOUT = 0.5 A
1.1
V
PWM CURRENT CONTROL (ISEN12, SEN34)
Torque at 100% (TRQ = 0)
140
150
160
mV
63.75
75
86.25
mV
VTRIP
ISENxx trip voltage
tBLANK
Current sense blanking time
1.8
µs
tOFF
Current control constant off time
20
µs
Torque at 50% (TRQ = 1)
PROTECTION CIRCUITS
VUVLO
Supply rising
Supply undervoltage lockout
2.7
Supply falling
2.4
V
V
VUVLO_HYS Supply undervoltage hysteresis
Rising to falling theshold
50
mV
tUVLO
Supply undervoltage deglitch time
VM falling; UVLO report
10
µs
IOCP
Overcurrent protection trip point
2
A
tOCP
Overcurrent protection deglitch time
VVM < 15 V
3
µs
VVM >= 15 V
1
µs
tRETRY
Overcurrent protection retry time
1
ms
IOL_PU
Open load pull-up current
< 15 nF on OUTx Pin
200
µA
IOL_PD
Open load pull-down current
< 15 nF on OUTx Pin
230
µA
VOL_HS
Open load detect threshold (high side)
2.3
V
VOL_LS
Open load detect threshold (low side)
1.2
V
TTSD
Thermal shutdown temperature
THYS
Thermal shutdown hysteresis
(2)
(2)
1.6
150
160
180
40
°C
°C
For VM > 16.5 V, the output current on OUTx must be limited to 4 A
6.6 I2C Timing Requirements
MIN
NOM
MAX
UNIT
100
kHz
STANDARD MODE
fSCL
8
SCL Clock frequency
0
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I2C Timing Requirements (continued)
MIN
NOM
MAX
UNIT
tHD,STA
Hold time (repeated) START condition. After this period, the first
clock pulse is generated
tLOW
tHIGH
tSU,STA
Setup time for a repeated START condition
tHD,DAT
Data hold time: For I2C bus devices
tSU,DAT
Data set-up time
tR
SDA and SCL rise time
1000
ns
tF
SDA and SCL fall time
300
ns
tSU,STO
Set-up time for STOP condition
tBUF
Bus free time between a STOP and START condition
4
µs
LOW period of the SCL clock
4.7
µs
HIGH period of the SCL clock
4
µs
4.7
µs
0
3.45
µs
250
ns
4
µs
4.7
µs
FAST MODE
fSCL
SCL Clock frequency
tHD,STA
Hold time (repeated) START condition. After this period, the first
clock pulse is generated
0
400
kHz
0.6
µs
tLOW
LOW period of the SCL clock
1.3
µs
tHIGH
HIGH period of the SCL clock
0.6
µs
tSU,STA
Setup time for a repeated START condition
0.6
tHD,DAT
Data hold time: For I2C bus devices
tSU,DAT
Data set-up time
tR
SDA and SCL rise time
300
ns
tF
SDA and SCL fall time
300
ns
tSU,STO
Set-up time for STOP condition
0.6
tBUF
Bus free time between a STOP and START condition
1.3
tSP
Pulse width of spikes to be supressed by input noise filter
µs
0
0.9
250
ns
µs
µs
50
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xIN1
tpd
xIN2
tpd
xOUT1
tpd
Z
Z
tpd
Z
Z
xOUT2
90%
90%
10%
10%
trise
tfall
Figure 1. Timing Diagram
STO
SDA
STA
STA
STO
tBUF
tr
SCL
tHD,STA
tf
tLOW
tHD,DAT
tHIGH
tSU,DAT
tSU,STO
tSU,STA
tHD,STA
Figure 2. I2C Timing Diagram
10
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6.7 Typical Characteristics
5
4
Supply Current (mA)
Supply Current (mA)
4
3
2
1
3
2
VVM = 2.7 V
VVM = 5 V
VVM = 12 V
VVM = 15 V
VVM = 18 V
1
TA = -40°C
TA = 25°C
TA = 85°C
0
2
4
6
8
10
12
Supply Voltage (V)
14
16
0
-40
18
-20
0
D001
Figure 3. Operating Supply Current (IVM) vs Supply Voltage
(VVM)
20
40
Temperature (°C)
60
100
D002
Figure 4. Operating Supply Current (IVM) vs Ambient
Temperature (TA)
7
5
VVM = 2.7 V
VVM = 5 V
VVM = 12 V
VVM = 15 V
VVM = 18 V
6
Sleep Current (PA)
4
Sleep Current (PA)
80
3
2
1
TA = -40°C
TA = 25°C
TA = 85°C
4
6
8
10
12
Supply Voltage (V)
14
16
4
3
2
1
0
2
5
18
0
-40
D003
Figure 5. Sleep Mode Supply Current (IVMQ) vs Supply
Voltage (VVM)
-20
0
20
40
Temperature (°C)
60
80
100
D004
Figure 6. Sleep Mode Supply Current (IVMQ) vs Ambient
Temperature (TA)
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Typical Characteristics (continued)
1
1
TA = -40°C
TA = 25°C
TA = 85°C
0.9
0.9
0.8
0.7
Resistance (:)
Resistance (:)
0.8
0.6
0.5
0.4
0.5
0.4
0.3
0.2
0.2
0.1
0.1
2
4
6
8
10
12
Supply Voltage (V)
14
16
0
-40
18
VVM = 2.7 V
VVM = 5 V
VVM = 12 V
VVM = 15 V
VVM = 18 V
-20
0
D005
20
40
Temperature (qC)
60
80
100
D006
Figure 7. High Side On-State Resistance (RDS(ON)_HS) vs
Supply Voltage (VVM)
Figure 8. High Side On-State Resistance (RDS(ON)_HS) vs
Ambient Temperature (TA)
1
1
TA = -40°C
TA = 25°C
TA = 85°C
0.9
0.8
0.9
0.8
0.7
Resistance (:)
Resistance (:)
0.6
0.3
0
0.6
0.5
0.4
0.7
0.6
0.5
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0
2
4
6
8
10
12
Supply Voltage (V)
14
16
18
0
-40
D007
Figure 9. Low Side On-State Resistance (RDS(ON)_LS) vs
Supply Voltage (VVM)
12
0.7
VVM = 2.7 V
VVM = 5 V
VVM = 12 V
VVM = 15 V
VVM = 18 V
-20
0
20
40
Temperature (qC)
60
80
100
D008
Figure 10. Low Side On-State Resistance (RDS(ON)_LS) vs
Ambient Temperature (TA)
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Typical Characteristics (continued)
250
Open Load Pull-Down Current (PA)
Open Load Pull-Up Current (PA)
225
200
175
150
125
TA = -40°C
TA = 25°C
TA = 85°C
100
200
175
150
TA = -40°C
TA = 25°C
TA = 85°C
125
100
2
4
6
8
10
12
Supply Voltage (V)
14
16
18
2
2.4
2.2
2
1.8
1.6
TA = -40°C
TA = 25°C
TA = 85°C
1.4
1.2
4
6
8
10
12
Supply Voltage (V)
6
14
16
18
14
16
18
D001
1.3
1.2
1.1
1
0.9
0.8
TA = -40°C
TA = 25°C
TA = 85°C
0.7
0.6
2
D001
Figure 13. Open Load High-Side Threshold Voltage (VOL_HS)
vs Supply Voltage (VVM)
8
10
12
Supply Voltage (V)
Figure 12. Open Load Pull-Down Current (IOL_PD) vs Supply
Voltage (VVM)
Open Load Low-Side Threshold Voltage (V)
2.6
2
4
D009
Figure 11. Open Load Pull-Up Current (IOL_PU) vs Supply
Voltage (VVM)
Open Load High-Side Threshold Voltage (V)
225
4
6
8
10
12
Supply Voltage (V)
14
16
18
D001
Figure 14. Open Load Low-Side Threshold Voltage (VOL_LS)
vs Supply Voltage (VVM)
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7 Detailed Description
7.1 Overview
The DRV8847 device is an integrated 2.7-V to 18-V dual motor driver for industrial brushed and stepper motor
applications. This driver can drive two DC motors, a bipolar stepper motor, or the solenoid loads. The device
integrates two H-bridges that use NMOS low-side and high-side drivers and current-sense regulation circuitry.
The DRV8847 device supports a high output current of 1-A RMS per H-bridge using low-RDS(ON) integrated
MOSFETs.
A simple PWM interface option allows easy interfacing to the H-bridge outputs. The interface options can be
configured using the MODE and IN3 pins in the DRV8847 device. The interface options can be configured
through a I2C interface in the I2C device variant (DRV8847S).
The current regulation uses a fixed off-time (tOFF) PWM scheme. The trip point for current regulation is controlled
by the value of the sense resistor and fixed internal VTRIP value.
A low-power sleep mode is included which lets the system save power when not driving the motor.
The DRV8847 device is available in three different packages:
• 16-pin TSSOP (no thermal pad)
• 16 pin HTSSOP (PowerPAD)
• 16 pin WQFN (thermal pad)
The I2C variant of the DRV8847 device is also available for a detailed diagnostics requirement and multi-slave
operation with multi-slave operation control over I2C bus.
The DRV8847S device variant is available in one package which is the 16-pin TSSOP (no thermal pad).
The DRV8847 device has a broad range of integrated protection features. These features include power supply
undervoltage lockout, open-load detection, overcurrent faults, and thermal shutdown.
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7.2 Functional Block Diagram
VM
VM
CVM2
0.1 µF
CVM1
bulk
Charge Pump
Power
VM
Internal
Reference
and
Regulators
OUT1
MODE
Gate
Drive
and
OCP
TRQ
VM
DC
Motor
Stepper
Motor
OUT2
nSLEEP
RSENSE12
ISENS12
(Optional)
ISEN
IN1
VM
Logic
IN2
OUT3
IN3
Gate
Drive
and
OCP
IN4
VEXT
DC
Motor
VM
RnFAULT
nFAULT
OUT4
Output
RSENSE34
ISENS34 (Optional)
ISEN
Overtemperature
GND
PPAD
Figure 15. Block Diagram for DRV8847
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Functional Block Diagram (continued)
VM
VM
CVM2
0.1 µF
CVM1
bulk
Charge Pump
Power
VM
Internal
Reference
and
Regulators
OUT1
nSLEEP
Gate
Drive
and
OCP
IN1
DC
Motor
VM
Stepper
Motor
IN2
OUT2
IN3
RSENSE12
ISENS12
(Optional)
ISEN
VM
IN4
VEXT
Logic
RnFAULT
nFAULT
OUT3
Output
Gate
Drive
and
OCP
SCL
VEXT
I 2C
Registers
RSDA
DC
Motor
VM
OUT4
SDA
RSENSE34
ISENS34 (Optional)
ISEN
Overtemperature
GND
PPAD
Figure 16. Block Diagram for DRV8847S
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7.3 Feature Description
Table 1 lists the recommended values of the external components for the gate driver.
Table 1. DRV8847 External Components
(1)
COMPONENT
PIN 1
PIN 2
CVM1
VM
GND
10-µF (minimum) VM-rated capacitor
CVM2
VM
GND
0.1-µF VM-rated ceramic capacitor
(1)
RECOMMENDED
RnFAULT
VEXT
RISEN12
ISEN12
nFAULT
GND
>1 kΩ
Sense resistor, see the Typical Application for sizing
RISEN34
ISEN34
GND
Sense resistor, see the Typical Application for sizing
VEXT is not a pin on the DRV8847 device, but a pullup resistor on the VEXT external supply voltage is required for the open-drain
output, nFAULT.
7.3.1 PWM Motor Drivers
The DRV8847 device has two identical H-bridge motor drivers with current-control PWM circuitry. Figure 17
shows a block diagram of the circuitry.
The two H-bridges can also be used as four independent half-bridges depending upon the interface option. The
ISENxx pin can be only used together with two half-bridges.
VM
IN1
OUT1
IN2
PWM
VM
Predrive
Stepper
Motor
OUT2
ISEN12
±
RSENSE12
+
REF (VTRIP)
Figure 17. PWM Motor Driver Circuitry
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7.3.2 Bridge Operation
The full-bridge can operate in four different operating modes: forward, reverse, coast (fast decay), and brake
(slow decay) operation.
7.3.2.1 Forward Operation
This operating mode refers to the forward rotation of the motor such that the current flows from terminal A (OUT1
or OUT3) to terminal B (OUT2 or OUT4) as shown in Figure 18. In this mode, terminal A is connected to VM and
terminal B is connected to ground.
VM
B
A
Figure 18. Forward Operation
7.3.2.2 Reverse Operation
This operating mode refers to the reverse rotation of the motor such that the current flows from terminal B (OUT2
or OUT4) to terminal A (OUT1 or OUT3) as shown in Figure 19. In this mode, terminal A is connected to ground
and terminal B is connected to VM.
VM
B
A
Figure 19. Reverse Operation
18
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7.3.2.3 Coast Operation (Fast Decay)
In this operating mode, all the FETs of the full-bridges are in the high impedance (Hi-Z) state. The motor also
goes to the Hi-Z state, and the motor starts coasting. This operating mode also helps to decay the motor current
faster and is therefore also referred to as a fast decay mode. If the motor was initially connected in forward
operation (current flows from terminal A to terminal B) and if the coast operation is applied, then, because of the
inductive nature of motor load, the current continues to flow in the same direction (A to B), and the anti-parallel
diodes of the alternate FETs starts conducting as shown in Figure 20. This flow of current through anti-parallel
diodes lets the current decrease rapidly because of the higher negative potential created by the supply voltage,
VM.
VM
A
B
Figure 20. Coast Operation (Fast Decay)
7.3.2.4 Brake Operation (Slow Decay)
This operating mode is realized by switching on both of the low-side FETs of the full-bridge as shown in
Figure 21. A current circulation path is provided when both low-side FETs are turned on. Due to this circulation
path, the current decays to ground using the resistance of the motor and of the low-side FET. Because this
current decay is less when compared to the coast operation because of the low potential difference, this mode is
also referred to the slow decay mode.
VM
A
B
Figure 21. Brake Operation (Slow Decay)
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7.3.3 Bridge Control
The DRV8847 device can be configured in four different operating modes depending on user requirements. The
MODE and IN3 pins are used to configure the DRV8847 in one of the four different interfaces: 4-pin interface, 2pin interface, a parallel bridge interface, and the independent bridge interface. Mode selection is done using the
I2C registers in the DRV8847S device variant (see the Programming section). Table 2 lists the configurations to
select the operating mode of the bridges.
Table 2. Bridge Mode Selection (DRV8847 Hardware Device Variant)
nSLEEP
MODE
IN3
0
X
X
Sleep mode
INTERFACE
1
0
X
4-pin interface
1
1
0
2-pin interface
1
1
1
Parallel bridge interface
1
Z
X
Independent bridge interface
NOTE
The MODE pin is not latched during driver operation. Therefore, TI does not recommend
connecting this pin to a controller to use at any time.
7.3.3.1 4-Pin Interface
In the 4-pin interface, the DRV8847 device is configured to drive a stepper motor or two BDC motors with fully
functional modes. To configure 4-pin interface operation, connect the MODE pin to ground and use the IN1, IN2,
IN3, and IN4 pins to control the drivers. In this mode, the stepper or brushed DC motor can operate with all four
modes (forward, reverse, coast, and brake mode) and the stepper motor can operate in either full-stepping mode
or the non-circulating half-stepping mode. Sense resistors can be connected to the ISEN12 and ISEN34 pins for
independent current regulation in bridge-12 and bridge-34 respectively.
Use this interface option for the following loads:
• Stepper motor in full-stepping mode (with or without current regulation)
• Stepper motor in half-stepping mode (with or without current regulation)
• Single or dual BDC motor (with or without current regulation) with full functional BDC modes (forward,
reverse, brake, and coast mode)
Table 3 lists the configurations for 4-pin interface operation and Figure 22 shows the application diagram for 4pin interface operation.
Table 3. 4-Pin Interface (MODE = 0)
nSLEEP
IN1
IN2
IN3
IN4
OUT1
OUT2
OUT3
OUT4
0
X
X
X
X
Z
Z
Z
Z
1
0
0
Z
Z
Motor coast (fast decay)
1
0
1
L
H
Reverse direction
1
1
0
H
L
Forward direction
1
1
1
L
L
Motor brake (slow decay)
20
1
0
0
1
0
1
1
1
1
FUNCTION (DC MOTOR)
Sleep mode
Z
Z
Motor coast (fast decay)
1
L
H
Reverse direction
0
H
L
Forward direction
1
L
L
Motor brake (slow decay)
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VM
OUT1
Gate
Drive
and
OCP
VM
DC
Motor
Stepper
Motor
OUT2
IN1
RSENSE
ISEN12
ISEN
IN2
IN3
(Optional)
VM
Logic
Controller
IN4
OUT3
nSLEEP
Gate
Drive
and
OCP
DC
Motor
VM
MODE
OUT4
GND
RSENSE
ISEN34
(Optional)
ISEN
Figure 22. 4-Pin Interface Operation
7.3.3.2 2-Pin Interface
In the 2-pin interface, the DRV8847 device is configured to drive a stepper motor or two BDC motors with lower
number of control inputs from microcontroller. To configure 2-pin interface operation, connect the MODE pin to
the external supply (3.3 V or 5 V), connect the IN3 pin to ground, and use the IN1 and IN2 pins to control the
driver. In this mode, the stepper or brushed DC motor operate in only two modes (forward mode and reverse
mode) i.e. only full-step operation is supported for stepper motor. This 2-pin interface is very useful for low GPIO
applications such as refrigerator dampers. Sense resistors can be connected to the ISEN12 and ISEN34 pins for
current regulation.
Use this interface option for the following loads:
• Stepper motor in full stepping mode (with or without current regulation)
• Single or dual BDC motor (with or without current regulation) with reduced functional BDC modes (forward
and reverse mode only)
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Table 4 lists the configurations for 2-pin interface operation and Figure 23 shows the application diagram for 2pin interface operation.
Table 4. 2-Pin Interface (MODE = 1, IN3 = 0)
nSLEEP
IN1
IN2
IN3
IN4
OUT1
OUT2
OUT3
OUT4
0
X
X
X
X
1
0
0
X
1
1
0
X
FUNCTION (DC MOTOR)
Z
Z
Z
Z
L
H
Reverse direction
H
L
Forward direction
Sleep mode
1
0
0
X
L
H
Reverse direction
1
1
0
X
H
L
Forward direction
VM
OUT1
VEXT
MODE
Gate
Drive
and
OCP
IN3
VM
DC
Motor
Stepper
Motor
GND
OUT2
'RQ¶W &DUH
IN4
RSENSE
ISEN12
(Optional)
ISEN
VM
Logic
OUT3
IN1
IN2
Controller
Gate
Drive
and
OCP
DC
Motor
VM
nSLEEP
OUT4
RSENSE
ISEN34
(Optional)
ISEN
Figure 23. 2-Pin Interface Operation
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NOTE
In this mode, two of the OUTx pins are always 'ON' if the device is in non-sleep state
(nSLEEP = HIGH). Therefore, to completely de-energize the motor-coils connected to
OUTx pins, the user has to pull-down nSLEEP pin.
7.3.3.3 Parallel Bridge Interface
In the parallel bridge interface, the DRV8847 device is configured to drive a higher current BDC motor by using
the driver in parallel to deliver twice the motor current. To go to parallel bridge interface operation, connect the
MODE and IN3 pins to the external supply (3.3 V or 5 V) and use the IN1 and IN2 pins to control the driver. This
mode can deliver the full functionality of the BDC motor control with all four modes (forward, reverse, coast, and
brake mode).
Use this interface option for the following loads:
• One high current BDC motor (with or without current regulation) with full functional BDC modes (forward,
reverse, brake, and coast mode)
• Two independent BDC motors operating together (with or without current regulation) with full functional BDC
modes (forward, reverse, brake, and coast mode)
Table 5 lists the configurations for parallel bridge interface operation, and Figure 24 shows the application
diagram for parallel bridge interface operation.
Table 5. Parallel Interface (MODE = 1, IN3 = 1)
nSLEEP
IN1
IN2
IN3
IN4
OUT1
OUT2
OUT3
OUT4
0
X
X
X
X
Z
Z
Z
Z
FUNCTION (DC MOTOR)
Sleep mode
1
0
0
1
X
Z
Z
Z
Z
Motor coast (fast decay)
1
0
1
1
X
L
H
L
H
Reverse direction
1
1
0
1
X
H
L
H
L
Forward direction
1
1
1
1
X
L
L
L
L
Motor brake (slow decay)
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VM
VEXT
OUT1
MODE
IN3
'RQ¶W &DUH
Gate
Drive
and
OCP
VM
IN4
OUT2
ISEN12
ISEN
VM
Logic
IN1
OUT3
IN2
Controller
Gate
Drive
and
OCP
nSLEEP
DC
Motor
VM
OUT4
RSENSE
ISEN34
ISEN
(Optional)
Figure 24. Parallel Mode Operation
7.3.3.4 Independent Bridge Interface
In the independent bridge interface, the DRV8847 device is configured for independent half-bridge operation. To
configure independent bridge interface operation, leave the MODE pin unconnected (Hi-Z state) and use the IN1,
IN2, IN3, and IN4 pins to independently control the OUT1, OUT2, OUT3, and OUT4 pins respectively. Only two
output states of the OUTx pin can be controlled (either connected to VM or connected to GND). This mode is
used to drive independent loads such as relays and solenoids.
Use this interface option for the following loads:
• Relay or solenoid coils connected between OUTx and VM/ground pin without current regulation
• Single or dual BDC motor (with or without current regulation) with three functional BDC modes (forward,
reverse, and braking mode only)
• Stepper motor in full-stepping mode (with or without current regulation)
• Stepper motor in half-stepping mode (with or without current regulation) using brake mode
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Table 6 lists the configurations for independent bridge interface operation and Figure 25 shows the application
diagram for independent bridge interface operation.
Table 6. Independent Bridge Interface (MODE = Hi-Z)
nSLEEP
IN1
IN2
IN3
IN4
OUT1
OUT2
OUT3
OUT4
0
X
X
X
X
Z
Z
Z
Z
1
0
L
OUT1 connected to GND
1
1
H
OUT1 connected to VM
1
0
L
1
1
H
FUNCTION (DC MOTOR)
Sleep mode
OUT2 connected to GND
OUT2 connected to VM
1
0
L
OUT3 connected to GND
1
1
H
OUT3 connected to VM
1
0
L
OUT4 connected to GND
1
1
H
OUT4 connected to VM
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VM
OUT1
Gate
Drive
and
OCP
VM
OUT2
IN1
IN2
ISEN12
IN3
ISEN
Controller
IN4
VM
Logic
nSLEEP
OUT3
Gate
Drive
and
OCP
Not Connected
VM
MODE
OUT4
ISEN34
ISEN
Figure 25. Independent Bridge Interface
7.3.4 Current Regulation
The current through the motor windings is regulated by a fixed off-time PWM current regulation circuit. With
brushed DC motors, current regulation can be used to limit the stall current (which is also the start-up current) of
the motor.
Current regulation works as follows: When an H-bridge is enabled, current rises through the winding at a rate
dependent on the supply voltage and inductance of the winding. If the current reaches the current trip threshold,
the bridge disables the current for a time tOFF before starting the next PWM cycle.
NOTE
Immediately after the current is enabled, the voltage on the ISENxx pin is ignored for a
period of time (tBLANK) before enabling the current sense circuitry. This blanking time also
sets the minimum on-time of the PWM cycle.
26
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The PWM trip current is set by a comparator which compares the voltage across a current sense resistor
connected to the ISENxx pin with a reference voltage. This reference voltage (VTRIP) is generated on-chip and
decides the current trip level.
The full-scale trip current in a winding is calculated as shown in Equation 1.
ITRIP
Torque
VTRIP
RSENSExx
where
•
•
•
•
ITRIP is the regulated current.
VTRIP is the internally generated trip voltage.
RSENSExx is the resistance of the sense resistor.
Torque is the torque scalar, the value of which depends on the input on TRQ pin. TRQ = 100% for TRQ pin
connected to GND (DRV8847) or TRQ bit set to 0 (DRV8847S) and TRQ = 50% connected to VEXT (DRV8847)
or TRQ bit set to 1 (DRV8847S).
(1)
For example, if the VTRIP voltage is 150 mV and the value of the sense resistor is 150 mΩ, the full-scale trip
current is 1 A (150 mV / (150 mΩ) = 1 A).
NOTE
If current control is not needed, connect the ISENxx pins directly to ground.
7.3.5 Current Recirculation and Decay Modes
During PWM current trip operation, the H-bridge is enabled to drive current through the motor winding until the
trip threshold of the current regulation is reached. After the trip current threshold is reached, the drive current is
interrupted, but, because of the inductive nature of the motor, current must continue to flow for some time. This
continuous flow of current is called recirculation current. A mixed decay allows a better current regulation by
optimizing the current ripple by using fast and slow decay.
Mixed decay is a combination of fast and slow decay modes. In fast decay mode, the anti-parallel diodes of the
opposite FETs are conducting on to let the current decay faster as shown in Figure 26 (see case 2). In slow
decay mode, winding current is recirculated by enabling both low-side FETs in the bridge (see case 3 in
Figure 26). Mixed decay starts with fast decay, then goes to slow decay. In the DRV8847 device, the mixed
decay ratio is 25% fast decay and 75% slow decay as shown in Figure 27.
VM
1
1
Drive Current
2
Fast Decay
3
Slow Decay
2
3
Figure 26. Decay Modes
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Fast Decay
ITRIP
Slow Decay
Motor
Current
25% of tOFF
Time
tON
tOFF
Mixed Decay (25% Fast Decay)
Figure 27. Mixed Decay
NOTE
The current regulation scheme uses a single sense resistor and hence always works for
two half bridges even when used in "Independent Bridge Interface". It is recommended
that current regulation not be used for loads using independent half bridges.
7.3.6 Torque Scalar
The torque scalar is used to dynamically adjust the output current through a digital input pin, TRQ. This torque
scalar decreases the trip reference value of the output current to 50% (whenever the TRQ pin is pulled-high).
Torque scalar can be used to scale the holding torque of the stepper motor. For the I2C device variant
(DRV8847S), this feature is implemented through an I2C register.
When the TRQ pin is pulled-low (or the TRQ bit is reset in the DRV8847S device variant), then trip current is
calculated using Equation 2.
ITRIP
Torque u VTRIP
RSENSExx
(2)
When the TRQ pin is pulled-high (or the TRQ bit is set in the DRV8847S device variant), then trip current is
calculated using Equation 3.
VTRIP
ITRIP 0.5
RSENSExx
(3)
28
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7.3.7 Stepping Modes
The DRV8847 device is used to drive a stepper motor in full-stepping mode or non-circulating half-stepping mode
using the following bridge configurations:
• Full-stepping mode (with or without current regulation)
– Using 4-pin interface configuration
– Using 2-pin interface configuration
• Half-stepping mode (with or without current regulation)
– Using 4-pin interface configuration
7.3.7.1 Full-Stepping Mode (4-Pin Interface)
In full-stepping mode, the full-bridge operates in either of two modes (forward or reverse mode) with a phase shift
of 90° between the two windings.
In 4-pin interface, the PWM input is applied to the IN1, IN2, IN3, and IN4 pins as shown in Figure 28 and the
driver operates only in forward (FRW) and reverse (REV) mode.
90o
Phase
IN1
IN2
IN3
IN4
OUT12 FRW
OUT12 FRW
OUT12
OUT12 REV
OUT12 REV
OUT34 FRW
OUT34 FRW
OUT34
OUT34 REV
OUT34 REV
Time
Figure 28. Full-Stepping Mode Using 4-Pin Interface
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7.3.7.2 Full-Stepping Mode (2-Pin Interface)
In full-stepping using the 2-pin interface, the PWM input is only applied to the IN1 and IN2 pins, and the IN3 is
connected to ground (see the Figure 23 section). Figure 29 shows the full-stepping mode of stepper motor using
the 2-pin interface
90o
Phase
IN1
IN2
OUT12 FRW
OUT12 FRW
OUT12
OUT12 REV
OUT12 REV
OUT34 FRW
OUT34 FRW
OUT34
OUT34 REV
OUT34 REV
Time
Figure 29. Full-Stepping Mode Using 2-Pin Interface
30
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7.3.7.3 Half-Stepping Mode (With Non-Driving Fast Decay)
In half-stepping mode, the full-bridge operates in one of the three modes (forward, reverse, or coast mode) with a
phase shift of 45° between the two windings.
In 4-pin interface, the PWM input is connected to the IN1, IN2, IN3, and IN4 pins as shown in Figure 30, and the
driver operates in forward, reverse, and coast mode.
45o
Phase
IN1
IN2
IN3
COAST
OUT12 FRW
COAST
COAST
OUT12 FRW
COAST
COAST
IN4
OUT12
OUT12 REV
OUT12 REV
OUT34 FRW
OUT34 FRW
COAST
OUT34 REV
COAST
COAST
COAST
OUT34
OUT34 REV
Time
Figure 30. Half-Stepping Mode Using 4-Pin Interface (With Non-Driving Fast Decay)
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7.3.7.4 Half-Stepping Mode (With Non-Driving Slow Decay)
In this half-stepping mode, the non-driving state is slow decay (braking mode). Therefore, the full-bridge operates
in one of the three modes (forward, reverse, or brake mode) with a phase shift of 45° between the two windings.
In 4-pin interface, the PWM input is connected to the IN1, IN2, IN3, and IN4 pins as shown in Figure 31, and the
driver operates in forward, reverse, and brake mode.
45o
Phase
IN1
IN2
IN3
BRAKE
OUT12 FRW
BRAKE
BRAKE
OUT12 FRW
BRAKE
BRAKE
IN4
OUT12
OUT12 REV
OUT12 REV
OUT34 FRW
OUT34 FRW
BRAKE
OUT34 REV
BRAKE
BRAKE
BRAKE
OUT34
OUT34 REV
Time
Figure 31. Half-Stepping Mode Using 4-Pin Interface (With Non-Driving Slow Decay)
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7.3.8 Motor Driver Protection Circuits
The DRV8847 device is protected against VM undervoltage, overcurrent, open load, and over temperature
events.
7.3.8.1
Overcurrent Protection (OCP)
The DRV8847 is protected against overcurrent by overcurrent protection trip. The OCP circuit on each FET
disables the current flow through the FET by removing the gate drive. If this overcurrent detection continues for
longer than the OCP deglitch time (tOCP), all FETs in the H-bridge (or half-bridge in the independent interface) are
disabled and the nFAULT pin is driven low. The DRV8847 device stays disabled until the retry time tRETRY occurs
whereas the DRV8847S device has a programmable option for auto-retry or the latch mode.
7.3.8.1.1 OCP Automatic Retry (Hardware Device and Software Device (OCPR = 0b))
After an OCP event in this mode, the corresponding half-bridges, full-bridge, or both bridges (depending on the
MODE bits) are disabled and the nFAULT pin is driven low (see Table 13 and Table 14). The OCP and
corresponding OCPx bits are latched high in the I2C registers (see the Register Map section). Normal operation
resumes automatically (motor driver operation and the nFAULT pin is released) after the tRETRY time elapses as
shown in Figure 32. The OCP and OCPx bits remain latched until the tRETRY period expires.
Overshoot due to OCP
deglitch time (tOCP)
IOCP
Motor
Current
tOCP
Time
tRETRY
Figure 32. OCP Operation
7.3.8.1.2 OCP Latch Mode (Software Device (OCPR = 1b))
OCP latch mode is only available in the DRV8847S device. After an OCP event, the corresponding half-bridges,
full-bridge, or both bridges (depending on the MODE bits) are disabled and the nFAULT pin is driven low. The
OCP and corresponding OCPx bits are latched high in the I2C registers (see the Register Map section). Normal
operation continues (motor driver operation and the nFAULT pin is released) when the OCP condition is removed
and a clear faults command is issued through the CLR_FLT bit.
NOTE
For supply voltage, VVM > 16.5-V, if the OUTx current (FET current) exceeds 4-A, then the
device operation is pushed beyond the safe operating area (SOA) of the device. User has
to ensure that the FET-current is below 4-A for device safe operation for supply voltage
above 16.5-V.
7.3.8.2 Thermal Shutdown (TSD)
If the die temperature exceeds thermal shutdown limits (TTSD), all FETs in the H-bridge are disabled and the
nFAULT pin is driven low. After the die temperature decreases to a value within the specified limits, normal
operation resumes automatically. The nFAULT pin is released after operation starts again.
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7.3.8.3 VM Undervoltage Lockout (VM_UVLO)
Whenever the voltage on the VM pin falls below the UVLO falling threshold voltage, VUVLO, all circuitry in the
device is disabled, and all internal logic is reset. Operation continues when the VVM voltage rises above the
UVLO rising threshold as shown in Figure 33. The nFAULT pin is driven low during an undervoltage condition
and is released after operation starts again.
VUVLO (max) rising
VUVLO (min) rising
VUVLO (max) falling
VUVLO (min) falling
VVM
DEVICE OFF
DEVICE ON
DEVICE ON
nFAULT
Time
Figure 33. VM UVLO Operation
7.3.8.4 Open Load Detection (OLD)
An open load detection feature is also implemented in this device. This diagnostic test runs at device power up or
when the DRV8847 device comes out from sleep mode (rising edge on the nSLEEP pin). The OLD diagnostic
test can run any time in the I2C variant device (DRV8847S) using the OLDOD (OLD On Demand) bit.
The OLD implementation is done on the full-bridge and the half-bridge. In the DRV8847 device, during an openload condition, the half-bridges, full-bridge, or both bridges (depending on the MODE pin) are always operating
and the nFAULT pin is pulled-low. The user must reset the power to release the nFAULT pin by doing the OLD
sequence again. Table 7 lists the different OLD scenarios for the DRV8847 device.
In the DRV8847S device, the user can program the full-bridge or half-bridge to be in the operating mode or the
Hi-Z state, whenever an open-load condition is detected by using the OLDBO (OLD Bridge Operation) bit.
Moreover, the nFAULT signaling on the OLD bit can be disabled using the OLDFD (OLD Fault Disable) bit. For
detailed I2C register settings, see the Register Map section. Table 8 lists the different OLD scenarios for the
DRV8847S device.
NOTE
For accurate OLD operation, the user must ensure that the motor is stationary (or current
in connected load becomes zero) before the open load on-demand command is executed.
34
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Table 7. Open Load Detection in DRV8847
LOAD TYPE
OLD
BRIDGE
OPERATION
nFAULT
Full-Bridge Connected
NO
YES
NO
Half-Bridge Connected
NO
YES
NO
Bridge Open
YES
YES
YES
One Half-Bridge Open
YES
YES
YES
NO
INTERFACE
4-pin
2-pin
Parallel bridge
Independent
bridge
Full-Bridge Connected
NO
YES
Half-Bridge Connected
NO
YES
NO
Bridge Open
YES
YES
YES
One Half-Bridge Open
YES
YES
YES
Full-Bridge Connected
NO
YES
NO
Half-Bridge Connected
NO
YES
NO
Bridge Open
YES
YES
YES
One Half-Bridge Open
YES
YES
YES
Table 8. Open Load Detection in DRV8847S (Full-bridge-12)
INTERFACE
4-pin
2-pin
Parallel bridge
Independent
bridge
LOAD TYPE
OLD
(2)
OLDBO = 0b
OLDBO = 1b
nFAULT
OLD BITS
OLD1
OLD2
OLD3
OLD4
Full-bridge connected
NO
YES
YES
NO
0b
0b
X
X
Half-bridge connected
NO
YES
YES
NO
0b
0b
X
X
Bridge open
YES
YES
NO
YES
1b
1b
X
X
One half-bridge open
YES
YES
NO
YES
1b or
0b (2)
0b or
1b
X
X
Full-bridge connected
NO
YES
YES
NO
0b
0b
X
X
Half-bridge connected
NO
YES
YES
NO
0b
0b
X
X
Bridge open
YES
YES
NO
YES
1b
1b
X
X
0b or
1b
X
X
One half-Bridge Open
YES
YES
NO
YES
1b or
0b
Full-Bridge Connected
NO
YES
YES
NO
0b
0b
X
X
Half-Bridge Connected
NO
YES
YES
NO
0b
0b
X
X
Bridge Open
YES
YES
NO
YES
1b
1b
X
X
YES
1b or
0b
0b or
1b
X
X
One Half-Bridge Open
(1)
BRIDGE OPERATION (1)
YES
YES
NO
The operation of the bridge is subjected to the selected mode type:
(a) In 4-pin or 2-pin interface, the corresponding bridge is in the operating or Hi-Z state.
(b) In parallel bridge (BDC) interface, both bridges are in the operating or Hi-Z state.
(c) In independent bridge interface, the corresponding half-bridge is in the operating or Hi-Z state.
Depending on which half-bridge is open, the corresponding bit in the I2C register is set.
The open-load detect sequence comprise of three detection states in which the driver ensures that any of the
load is either connected or open as follows.
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7.3.8.4.1 Full-Bridge Open Load Detection
As shown in Figure 34, during device wakeup, a constant current source pulls the OUT1 pin to the AVDD
(internal) fixed voltage which allows current flow from OUT1 to OUT2 terminal. The current drawn is completely
dependent on the motor resistance between OUT1 and OUT2. Depending on this current and the comparator
threshold voltage (VOL_HS and VOL_LS), the comparator output OL1_HS and OL2_LS are either set or reset which
determines the open load status. Table 9 shows the states of OL1_HS and OL2_LS for the open load detect.
This test executes before the tWAKE or tON time has elapsed. When an open load is detected, the nFAULT pin is
latched low until the device is power cycled or device reset with nSLEEP pin. A similar implementation is done
for the OUT3 and OUT4 pins.
Table 9. Open Load Detection for Full-Bridge Connection
OL1_HS
OL2_LS
OLD STATUS
0
0
NO OLD
0
1
1
0
1
1
AVDD
±
12 kŸ
+
OL1_HS
VM
SW1_HS
VOL_HS
OLD
IOL_PU
X
OUT1
SW1_LS
OLD1
X
IOL_PD
±
+
OL1_LS
VOL_LS
15 kŸ
DC
Motor
AVDD
±
12 kŸ
+
OL2_HS
VM
SW2_HS
VOL_HS
Stepper
Motor
IOL_PU
X
OUT2
SW2_LS
OLD2
X
IOL_PD
To OUT3 and OUT4
±
+
OL2_LS
VOL_LS
15 kŸ
Figure 34. Open Load Detect Circuit for Full-Bridge Connection
36
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NOTE
AVDD voltage is the internal regulator voltage and is determined as min (VVM, 4.2 V).
Hence, for supply voltage (VVM) higher than 4.2 V, this voltage is fixed at 4.2 V else it is
equal to supply voltage ( VVM).
7.3.8.4.2 Load Connected to VM
For detection of the VM connected load, a constant current source pull-down the OUT1 node as shown in
Figure 35. This allows the current to flow from VM to OUT1 depending upon the value of load resistor (RL)
connected between OUT1 and VM. Higher current (not open load) will allow the OL1_LS comparator to set and
higher current resets the comparator output as shown in Table 10 for open load detection.
Table 10. Open Load Detection for VM Connected Load
OL1_LS
OLD STATUS
0
NO OLD
1
OLD
VM
AVDD
±
VOL_HS
12 kŸ
+
OL1_HS
VM
SW1_HS
IOL_PU
X
RL
X
OUT1
SW1_LS
OLD1
X
IOL_PD
±
+
OL1_LS
VOL_LS
15 kŸ
Figure 35. Open Load Detect Circuit for Load Connected to VM
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7.3.8.4.3 Load Connected to GND
For detection of the GND connected load, the OUT1 node is pulled-up by the internal current source and the
internal (4.2-V) fixed voltage as shown in Figure 36. This allows the current to flow from OUT1 to GND
depending upon the value of load resistor (RL) connected between OUT1 and GND. Higher current (not open
load) will allow the OL1_HS comparator to set and higher current resets the comparator output as shown in
Table 11.
Table 11. Open Load Detection for GND Connected
Load
OL1_HS
OLD STATUS
0
NO OLD
1
OLD
AVDD
±
VOL_HS
12 kŸ
+
OL1_HS
VM
SW1_HS
IOL_PU
X
OUT1
SW1_LS
OLD1
IOL_PD
±
+
OL1_LS
X
VOL_LS
X
RL
15 kŸ
Figure 36. Open Load Detect Circuit for Load Connected to GND
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7.4 Device Functional Modes
The DRV8847 device is active until the nSLEEP pin is pulled logic low. In sleep mode, the internal circuitry
(charge pump and regulators) is disabled and all internal FETs are disabled (Hi-Z state).
The device goes to operating mode automatically if the nSLEEP pin is pulled logic high. tWAKE must elapse
before the device is ready for inputs. The nFAULT pin asserts for small duration during power-up. Various
functional modes are described in Table 12.
The DRV8847 device goes to a fault mode in the event of VM undervoltage (UVLO), overcurrent (OCP), openload detection (OLD), and thermal shutdown (TSD). The functionality of each fault depends on the type of fault
listed in Table 13 for the DRV8847 device and Table 14 for the DRV8847S device.
NOTE
The tSLEEP time must elapse before the device goes to sleep mode.
Table 12. Functional Modes
MODE
CONDITION
H-BRIDGE
INTERNAL CIRCUITS
Operating
2.7 V < VVM < 18 V
nSLEEP pin = 1
Operating
Operating
Sleep
2.7 V < VVM < 18 V
nSLEEP pin = 0
Disabled
Disabled
Fault
Any fault condition met
Depends on fault
Depends on fault
Table 13. Fault Support for DRV8847
FAULT
INTERFACE
CONDITION
REPORT
H-BRIDGE
INTERNAL
CIRCUITS
RECOVERY
VM undervoltage
(VM_UVLO)
All interfaces
VM < VUVLO
nFAULT
Both H-bridges in
Hi-Z state
Shutdown
Automatic:
VM > VUVLO
Operating
Automatic:
tRETRY
Operating
Power cycle
/RESET: OUTx
Connected
Operating
TJ < TTSD
(THYS typ 40°C)
Corresponding Hbridges in Hi-Z
state
4-pin
2-pin
Overcurrent
(OCP)
Parallel bridge
I > IOCP
nFAULT
Corresponding
half-bridges in HiZ state
Independent
bridge
Open load detect
(OLD)
Thermal shutdown
(TSD)
Both H-bridges in
Hi-Z state
4-pin
Full-bridge open
nFAULT
H-bridge in
operating mode
2-pin
Parallel bridge
Full-bridges open
nFAULT
Both H-bridges in
operating mode
Independent
bridge
Half-bridge open
nFAULT
Half-bridge in
operating mode
All interfaces
TJ > TTSD
(min 150°C)
nFAULT
Both H-bridges in
Hi-Z state
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Table 14. Fault Support for DRV8847S
FAULT
MODE
CONDITION
REPORT
H-BRIDGE
INTERNAL
CIRCUITS
RECOVERY
VM undervoltage
(VM_UVLO)
All interfaces
VM < VUVLO
nFAULT
Both H-bridges in
Hi-Z state
Shutdown
Automatic:
VM > VUVLO
Operating
Automatic:
tRETRY
Operating
Power cycle /
RESET: OUTx
Connected
Operating
TJ < TTSD
(THYS typ 40°C)
Corresponding Hbridges in Hi-Z
state
4-pin
2-pin
Overcurrent
(OCP)
Parallel bridge
I > IOCP
nFAULT
Corresponding
half-bridges in HiZ state
Independent
bridge Interface
Open load detect
(OLD)
Thermal shutdown
(TSD)
(1)
40
Both H-bridges in
Hi-Z state
4-pin
Full-bridge open
nFAULT
H-bridge in
operating or Hi-Z
state (1)
2-pin
Parallel bridge
Full-bridges open
nFAULT
Both H-bridges in
operating or Hi-Z
state
Independent
bridge
Half-bridge open
nFAULT
Half-bridge in
operating or Hi-Z
state
All interfaces
TJ > TTSD
(min 150°C)
nFAULT
Both H-bridges in
Hi-Z state
The state of the bridge in OLD is dependent on the OLDBO bit as listed in Table 19.
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7.5 Programming
This section applies only to the DRV8847S device (I2C variant).
7.5.1 I2C Communication
7.5.1.1 I2C Write
To write on the I2C bus, the master device sends a START condition on the bus with the address of the 7-bit
slave device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the slave sends the
acknowledge bit, the master device then sends the register address of the register to be written. The slave
device sends an acknowledge (ACK) signal again which notifies the master device that the slave device is ready.
After this process, the master device sends 8-bit write data and terminates the transmission with a STOP
condition.
START
7-bit Slave Address
R/W=0
ACK
8-bit Register Address
ACK
8-bit Data
ACK
STOP
Write to Memory
Figure 37. I2C Write Sequence
7.5.1.2 I2C Read
To read from a slave device, the master device must first communicate to the slave device which register will be
read from. This communication is done by the master starting the transmission similarly to the write process
which is by setting the address with the R/W bit equal to 0b (signifying a write). The master device then sends
the register address of the register to be read from. When the slave device acknowledges this register address,
the master device sends a START condition again, followed by the slave address with the R/W bit set to 1b
(signifying a read). After this process, the slave device acknowledges the read request and the master device
releases the SDA bus, but continues supplying the clock to the slave device.
During this part of the transaction, the master device becomes the master-receiver, and the slave device
becomes the slave-transmitter. The master device continues sending out the clock pulses, but releases the SDA
line so that the slave device can transmit data. At the end of the byte, the master device send a negativeacknowledge (NACK) signal, signaling to the slave device to stop communications and release the bus. The
master device then sends a STOP condition.
Repeated Start
START
7-bit Slave Address
R/W=0
ACK
8-bit Register Address
ACK
RSTRT
7-bit Slave Address
R/W=1
STOP
NACK
8-bit Data
ACK
Figure 38. I2C Read Sequence
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Programming (continued)
7.5.2 Multi-Slave Operation
Multi-slave operation is used to control multiple DRV8847S devices through one I2C line as shown in Figure 39.
The default device address of the DRV8847 device is 0x60 (7-bit address). Therefore, any DRV8847S device
can be accessed using this address. The steps for multi-slave configuration for programming device-1 out of 4
connected devices (as shown in Figure 39) are as follows:
nFAULT1
nFAULT4
Microcontroller
(Master)
nFAULT2
nFAULT3
DRV8847S (2)
(Slave 2)
DRV8847S (1)
(Slave 1)
DRV8847S (3)
(Slave 3)
nFAULT (4)
SDA
SCL
nFAULT (3)
SDA
SCL
nFAULT (2)
SDA
SCL
nFAULT (1)
SDA
SCL
SCL SDA
DRV8847S (4)
(Slave 4)
Figure 39. Multi-Slave Operation of DRV8847S
•
•
•
•
•
•
•
42
The DRV8847S device variant is configured for multi-slave operation by writing the DISFLT bit (IC2_CON
register) of all connected devices to 1b. This step will disable the nFAULT output pin of all DRV8847S, to
avoid any race condition between master and slave I2C device.
Pull the nFAULT pins (nFAULT2, nFAULT3, and nFAULT4 pins) of three devices (2, 3, and 4) to low to
release the I2C buses of the slave device (device-2, device-3 and device-4). Now only device-1 is connected
to master.
Since, only one device, DRV8847S (1), is connected to the controller, and, therefore, its slave address can be
reprogrammed from default 0x60 (7-bit address) to another unique address.
Similarly, the slave address (SLAVE_ADDR) of the other three devices (device-2, device-3 and device-4) can
be reprogrammed sequentially to unique addresses by a combination of nFAULT pins.
When all slave addresses are reprogrammed, write the DISFLT bit to 0b (IC2_CON register). This will enable
the nFAULT output pin for fault flagging.
All the nFAULT pins are released and a multi-slave setup is complete. Now all connected slave devices can
be accessed using the newly reprogrammed address.
The above steps should be repeated for any device in case of a power reset (nSLEEP). .
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7.6 Register Map
Table 15 lists the memory-mapped I2c registers for the DRV8847 device. The I2C registers are used to configure the DRV8847S device and for device
diagnostics.
NOTE
Do not modify reserved registers or addresses not listed in the register map (Table 15). Writing to these registers may have
unintended effects. For all reserved bits, the default value is 0b.
Table 15. I2C Registers
Address
Acronym
0x00
SLAVE_ADDR
Register Name
0x01
IC1_CON
IC1 Control
TRQ
IN4
IN3
IN2
IN1
I2CBC
0x02
IC2_CON
IC2 Control
CLRFLT
DISFLT
RSVD
DECAY
OCPR
OLDOD
OLDFD
OLDBO
0x03
SLR_STATUS1
Slew Rate and Fault Status-1
RSVD
SLR
RSVD
nFAULT
OCP
OLD
TSDF
0x04
STATUS2
Fault Status-2
OLD4
OLD3
OLD2
OLD1
OCP4
OCP3
OCP2
Slave Address
7
6
5
4
RSVD
3
2
1
0
Access
Section
RW
Go
RW
Go
RW
Go
UVLOF
RW
Go
OCP1
R
Go
SLAVE_ADDR
MODE
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Complex bit access types are encoded to fit into small table cells. Table 16 shows the codes that are used for
access types in this section.
Table 16. Access Type Codes
Access Type
Code
Description
R
Read
W
Write
Read Type
R
Write Type
W
Reset or Default Value
-n
Value after reset or the default
value
7.6.1 Slave Address Register (Address = 0x00) [reset = 0x60]
Slave Address is shown in Figure 40 and described in Table 17.
Figure 40. Slave Address Register
7
RSVD
R-0b
6
5
4
3
SLAVE_ADDR
R/W-1100000b
2
1
0
Table 17. Slave Address Register Field Descriptions
Bit
Field
Type
Reset
Description
7
RSVD
R
0b
Reserved
SLAVE_ADDR
R/W
1100000b
Slave address (8 bit)
The default value is 0x60
6-0
7.6.2 IC1 Control Register (Address = 0x01) [reset = 0x00]
IC1 Control is shown in Figure 41 and described in Table 18.
Figure 41. IC1 Control Register
7
TRQ
R/W-0b
6
IN4
R/W-0b
5
IN3
R/W-0b
4
IN2
R/W-0b
3
IN1
R/W-0b
2
I2CBC
R/W-0b
1
0
MODE
R/W-00b
Table 18. IC1 Control Register Field Descriptions
Bit
Field
Type
Reset
Description
7
TRQ
R/W
0b
0b = Torque scalar set to 100%
6
IN4
R/W
0b
The INx bits are used to control the bridge operation.
5
IN3
R/W
0b
The INx bits are used to control the bridge operation.
4
IN2
R/W
0b
The INx bits are used to control the bridge operation.
3
IN1
R/W
0b
The INx bits are used to control the bridge operation.
2
I2CBC
R/W
0b
0b = Bridge control configured by using the INx pins
1-0
MODE
R/W
00b
1b = Torque scalar set to 50%
1b = Bridge control configured by using the INx bits
00b = 4-pin interface
01b = 2-pin interface
10b = Parallel interface
11b = Independent mode
44
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7.6.3 IC2 Control Register (Address = 0x02) [reset = 0x00]
IC2 Control is shown in Figure 42 and described in Table 19.
Figure 42. IC2 Control Register
7
CLRFLT
R/W-0b
6
DISFLT
R/W-0b
5
RSVD
R-0b
4
DECAY
R/W-0b
3
OCPR
R/W-0b
2
OLDOD
R/W-0b
1
OLDFD
R/W-0b
0
OLDBO
R/W-0b
Table 19. IC2 Control Register Field Descriptions
Bit
7
Field
Type
Reset
Description
CLRFLT
R/W
0b
Set this bit to issue a clear FAULT command. This command
clears all FAULT bits other than the OLD and OLDx bits. This bit
reset to 0b after clearing all the faults.
0b = No clear FAULT command issued
1b = Clear FAULT command issued
6
DISFLT
R/W
0b
0b = nFAULT pin not disable
1b = nFAULT pin is disabled
5
RSVD
R
0b
Reserved
4
DECAY
R/W
0b
0b = 25% fast decay
1b = 100% slow decay
3
OCPR
R/W
0b
2
OLDOD
R/W
0b
1
OLDFD
R/W
0b
0
OLDBO
R/W
0b
0b = OCP auto retry mode
1b = OCP latch mode
0b = Idle
1b = OLD on-demand is activated
0b = Fault signaling on OLD
1b = No fault signaling on OLD
0b = Bridge operating on OLD
1b = Bridge Hi-Z on OLD
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7.6.4 Slew-Rate and Fault Status-1 Register (Address = 0x03) [reset = 0x40]
Fault Status-1 is shown in Figure 43 and described in Table 20.
Figure 43. Fault Status-1 Register
7
RSVD
R-0b
6
SLR
R/W-0b
5
RSVD
R-0b
4
nFAULT
R-0b
3
OCP
R-0b
2
OLD
R-0b
1
TSDF
R-0b
0
UVLOF
R-0b
Table 20. Fault Status-1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
RSVD
R
0b
Reserved
6
SLR
R/W
0b
0b = 150 ns
1b = 300 ns
5
RSVD
R
0b
Reserved
4
nFAULT
R
0b
0b = No FAULT detected (mirrors the nFAULT pin)
1b = FAULT detected
3
OCP
R
0b
0b = No OCP detected
1b = OCP detected
2
OLD
R
0b
1
TSDF
R
0b
0
UVLOF
R
0b
0b = No open load detected
1b = Open load detected
0b = No TSD fault detected
1b = TSD fault detected
0b = No UVLO fault detected
1b = UVLO fault detected
46
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7.6.5 Fault Status-2 Register (Address = 0x04) [reset = 0x00]
Fault Status-2 is shown in Figure 44 and described in Table 21.
Figure 44. Fault Status-2 Register
7
OLD4
R-0b
6
OLD3
R-0b
5
OLD2
R-0b
4
OLD1
R-0b
3
OCP4
R-0b
2
OCP3
R-0b
1
OCP2
R-0b
0
OCP1
R-0b
Table 21. Fault Status-2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
OLD4
R
0b
0b = No open load detected on OUT4
6
OLD3
R
0b
5
OLD2
R
0b
4
OLD1
R
0b
3
OCP4
R
0b
2
OCP3
R
0b
1
OCP2
R
0b
1b = Open load detected on OUT4
0b = No open load detected on OUT3
1b = Open load detected on OUT3
0b = No open load detected on OUT2
1b = Open load detected on OUT2
0b = No open load detected on OUT1
1b = Open load detected on OUT1
0b = No OCP detected on OUT4
1b = OCP detected on OUT4
0b = No OCP detected on OUT3
1b = OCP detected on OUT3
0b = No OCP detected on OUT2
1b = OCP detected on OUT2
0
OCP1
R
0b
0b = No OCP detected on OUT1
1b = OCP detected on OUT1
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DRV8847 device is used in applications for stepper or brushed DC motor control.
8.2 Typical Application
The user can configure the DRV8847 for stepper motor and dual BDC motor applications as described in this
section.
8.2.1 Stepper Motor Application
Figure 45 shows the typical application of the DRV8847 device to drive a stepper motor.
1
2
nSLEEP
IN1
OUT1
IN2
3
330 m
MODE
ISEN12
4
5
Stepper
Motor
330 m
6
8
15
14
13
10 µF
DRV8847
VM
OUT4
ISEN34
7
VEXT
GND
OUT2
16
TRQ
OUT3
IN4
nFAULT
IN3
0.1 µF
12
11
10
9
(Logic Supply)
To Controller
Figure 45. Typical Application Schematic of Device Driving Stepper Motor
8.2.1.1 Design Requirements
Table 22 lists design input parameters for system design.
Table 22. Design Parameters
DESIGN PARAMETER
REFERENCE
VM
12 V
Motor winding resistance
RL
34 Ω/phase
Motor winding inductance
48
EXAMPLE VALUE
Motor supply voltage
LL
33 mH/phase
Motor RMS current
IRMS
350 mA
Target trip current
ITRIP
350 mA
Trip current reference voltage (internal voltage)
VTRIP
150 mV
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8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Current Regulation
The trip current (ITRIP) is the maximum current driven through either winding. The amount of this current depends
on the sense resistor value (RSENSExx) as shown in Equation 4 (Considering torque setting (TRQ) as 100%).
ITRIP
Torque u VTRIP
RSENSExx
(4)
The ITRIP current is set by a comparator which compares the voltage across the RSENSExx resistor to a reference
voltage. To avoid saturation of the motor, the ITRIP current must be calculated as shown in Equation 5.
VVM
ITRIP
RL (:) RDS(ON) _ HS (:) RDS(ON) _ LS (:) RSENSExx (:)
where
•
•
•
VVM is the motor supply voltage.
RL is the motor winding resistance.
RDS(ON)_HS and RDS(ON)_LS are the high-side and low-side on-state resistance of the FET.
For an ITRIP value of 350 mA, the value of the sense resistor (RSENSExx) is calculated as shown in Equation 6.
VTRIP 150 mV
RSENSE12 RSENSE34
428.6 m:
ITRIP
350 mA
(5)
(6)
Select the closest available value of 440 mΩ for the sense resistors. Selecting this value will effect the current
accuracy by 2.8%.
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8.2.1.3 Application Curves
50
Figure 46. Device Power-up with Supply Voltage (VM)
Figure 47. Device Power-up with nSLEEP
Figure 48. Stepper Motor Full-Step Operation
Figure 49. Stepper Motor Half-Step Operation With OffState as Hi-Z
Figure 50. Stepper Motor Half-Step Operation With OffState as Brake
Figure 51. Brushed DC Motor Operation in Parallel Mode
Showing Current Regulation at 2-A
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Figure 52. Zoomed Waveform Showing Current Regulation
Figure 53. Torque Pin Functionality for Current Scaling
Figure 54. Undervoltage Lockout Operation
Figure 55. Open Load Detect Operation
Figure 56. Over Current Protection and Recovery
Figure 57. Zoomed Waveform of Over Current Protection
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8.2.2 Dual BDC Motor Application
Figure 58 shows the typical application of DRV8847 device to drive dual BDC motors.
1
2
IN1
OUT1
IN2
3
330 m
BDC
nSLEEP
5
330 m
BDC
6
7
8
VEXT
15
MODE
ISEN12
4
16
GND
OUT2
14
13
10 µF
DRV8847
VM
OUT4
ISEN34
TRQ
OUT3
IN4
nFAULT
IN3
0.1 µF
12
11
10
9
(Logic Supply)
To Controller
Figure 58. Typical Application Schematic of Device Driving Two BDC Motors
8.2.2.1 Design Requirements
Table 23 lists the design input parameters for system design.
Table 23. Design Parameters
DESIGN PARAMETER
REFERENCE
EXAMPLE VALUE
Motor supply voltage
VM
12 V
Motor winding resistance
RL
13.2 Ω
Motor winding inductance
Motor RMS current
Motor start-up current
LL
500 µH
IRMS
490 mA
ISTART
900 mA
Target trip current
ITRIP
1.2 A
Trip current reference voltage (internal voltage)
VTRIP
150 mV
8.2.2.2 Detailed Design Procedure
8.2.2.2.1 Motor Voltage
The motor voltage used in an application depends on the rating of the selected motor and the desired revolutions
per minute (RPM). A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to
the power FETs. A higher voltage also increases the rate of current change through the inductive motor
windings.
8.2.2.2.2 Current Regulation
The trip current (ITRIP) is the maximum current driven through either winding. Because the peak current (start
current) of the motor is 900 mA, the ITRIP current level is selected to be just greater than the peak current. The
selected ITRIP value for this example is 1.2 A. Therefore, use Equation 7 to select the value of the sense resistors
(RSENSE12 and RSENSE34) connected to the ISEN12 and ISEN34 pins.
VTRIP 150 mV
RSENSE12 RSENSE34
125 m:
ITRIP
1.2 A
(7)
52
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8.2.2.2.3 Sense Resistor
For optimal performance, the sense resistor must:
• Be a surface mount component
• Have low inductance
• Be rated for high enough power
• Be placed closely to the motor driver
The power dissipated by the sense resistor equals IRMS2 × R. In this example, the peak current is 900 mA, the
RMS motor current is 490 mA, and the sense resistor value is 125 mΩ. Therefore, the sense resistors (RSENSE12
and RSENSE34) dissipate 30 mW (490 mA2 × 125 mΩ = 30 mW). The power quickly increases with higher current
levels.
Resistors typically have a rated power within some ambient temperature range, along with a derated power curve
for high ambient temperatures. When a printed circuit board (PCB) is shared with other components generating
heat, margin should be added. For best practice, measure the actual sense resistor temperature in a final
system, along with the power MOSFETs, because those components are often the hottest.
Because power resistors are larger and more expensive than standard resistors, the common practice is to use
multiple standard resistors in parallel, between the sense node and ground. This practice distributes the current
and heat dissipation.
8.2.3 Open Load Implementation
This section presents the open load detection circuit and the operation. The open load detection diagnostic test
runs during the device power up or when the DRV8847 device comes out from sleep mode. In the I2C variant
device (DRV8847S), the OLD diagnostic test can run any instant of time using the I2C register bits.
8.2.3.1 Open Load Detection Circuit
OLD circuit consists of four main components i.e. current source (and current sink), series sequencing switches
(sequenced by the digital core), resistors and comparators. For ground (GND) connected load, the current
source (IOL_PU) pulls up the OUTx node to internal regulator voltage (AVDD) and allows the current to flow from
internal regulator voltage (AVDD) to ground via the connected load as shown in Figure 59. Moreover, for the
supply (VM) connected load, the current sink (IOL_PD) pulls down the current from supply voltage (VM) to ground
via the connected load as shown in Figure 61. The resistance of the load connected at the OUTx terminal will
change the source / sink current and indirectly the voltage drop across two resistors (12-kΩ and 15-kΩ). This
voltage drop across resistors is compared with the reference voltage (VOL_HS and VOL_LS) by the internal
comparators to give the output as OL1_HS and OL1_LS. This comparator output is fed to the open load digital
circuit to determine the open load condition.
NOTE
Following are the values of various parameter shown above: AVDD voltage = 4.2-V, IOL_PU
= 200-µA, IOL_PD = 230-µA, VOL_HS = 2.3-V, VOL_LS = 1.2-V.
Note that the values taken above are at the typical condition of supply voltage and
temperature. Refer to "Typical Characteristics" section in Specifications for detailed
specifications.
8.2.3.2 OLD for Ground Connected Load
Figure 59 shows the ground connected load with internal OLD circuit. When high-side open load sequence is
activated (i.e. SW1_HS is on and SW1_LS is off), the current source (IOL_PU) pulls up the OUT1 node to internal
regulator voltage (AVDD) and current flows from internal regulator voltage (AVDD) to ground via the connected
load (RL). Now, depending upon if the load is present or not, there can be three cases as follows:
8.2.3.2.1 Half Bridge Open
If no-load is connected at the OUT1, then no current flows from AVDD. This pulls up the positive terminal of
OL1_HS comparator to 4.2-V (AVDD). This if compared with 2.3-V (VOL_HS) sets the comparator output to "1",
which signifies an open load detect.
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AVDD
±
VOL_HS
12 kŸ
+
OL1_HS
VM
SW1_HS
IOL_PU
X
OUT1
SW1_LS
OLD1
IOL_PD
±
+
OL1_LS
X X
VOL_LS
RL
15 kŸ
Figure 59. Open Load Detect Circuit for Load Connected to Ground (GND)
8.2.3.2.2 Half Bridge Short
If OUT1 pin is shorted to ground, then pull-up current of 200-µA (IOL_PU) flows from AVDD. Due to this, there is a
voltage drop at the positive terminal of OL1_HS comparator as:
VOL1_ HS
VAVDD IOL _ PU u 12k:
(8)
Using Equation 8, the VOL1_HS(+) is calculated as shown in Equation 9,
VOL1_ HS
4.2V
200PA u 12k:
1.8V
(9)
This voltage, if compared with 2.3-V (VOL_HS) reset the OL1_HS comparator output to "0", which signifies a no
open load detect.
8.2.3.2.3 Load Connected
If a resistive load (RL) is connected between OUT1 and GND, then current flowing from AVDD depends on load
reistance (RL) as:
ILOAD =
VAVDD
RL 12k:
(10)
Now, if the voltage drop at positive terminal of OL1_HS comparator is higher than 2.3-V (VOL_HS), the comparator
sets output to "1" showing as open load. Hence, the voltage required to trip the OL1_HS comparator is
calculated as:
VOL _ HS
VAVDD ILOAD u 12k:
(11)
By putting Equation 10 to Equation 11,
VOL _ HS
VAVDD
VAVDD u 12k:
RL 12k:
(12)
By solving Equation 12, the load resistance (RL) is expressed as,
RL !
54
VAVDD u 12k:
VAVDD VOL _ HS
12k:
(13)
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By putting the values of VAVDD and VOL_HS in Equation 13, the load resistance (RL) is calculated as 14.52-kΩ.
Hence, any resisitive load connected between OUTx and GND above this value is shown as an open-load.
NOTE
The values of these parameters are taken for a typical case for understanding. These
parameters changes with supply voltage and temperature. User has to consider a design
margin based on the above calculations.
17
Resistance (k:)
16
15
14
13
12
TA = -40°C
TA = 25°C
TA = 85°C
11
2
4
6
8
10
Supply Voltage (V)
12
14
16
18
D001
Figure 60. Resistance Threshold's for Open Load Detect in Ground (GND) Connected Load
8.2.3.3 OLD for Supply (VM) Connected Load
Figure 61 shows the supply (VM) connected load with internal OLD circuit. When low-side open load sequence is
activated (i.e. SW1_HS is off and SW1_LS is on), the current sink (IOL_PD) pulls down the OUT1 node to supply
voltage (VVM) and current flows from supply (VM) to ground via the connected load (RL). Now, depending upon if
the load is present or not, there can be three cases as follows:
VM
AVDD
±
VOL_HS
12 kŸ
+
OL1_HS
VM
SW1_HS
IOL_PU
X
X
RL
OUT1
SW1_LS
OLD1
X
IOL_PD
±
+
OL1_LS
VOL_LS
15 kŸ
Figure 61. Open Load Detect Circuit for Load Connected to Supply Voltage (VM)
8.2.3.3.1 Half Bridge Open
If no-load is connected at the OUT1, then no current flows from supply (VM). This pulls down the negative
terminal of OL1_LS comparator to 0-V (GND). This if compared with 1.2-V (VOL_LS) sets the comparator output to
"1", which signifies an open load detect.
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8.2.3.3.2 Half Bridge Short
If OUT1 pin is shorted to supply (VM), then pull-down current of 230-µA (IOL_LS) flows from supply (VM). Due to
this, there is a voltage drop at the negative terminal of OL1_LS comparator as:
VOL1_ LS
IOL _ PD u 15k:
(14)
Using Equation 14, the VOL1_LS(-) is calculated as shown in Equation 15,
VOL1_ LS
230PA u 15k:
3.45V
(15)
This voltage, if compared with 1.2-V (VOL_LS) reset the OL1_LS comparator output to "0", signifying a no open
load detect.
8.2.3.3.3 Load Connected
If a resistive load (RL) is connected between OUT1 and VM, then current flowing from supply (VM) is as:
ILOAD
VVM
RL 15k:
(16)
Now, if the voltage drop at negative terminal of OL1_LS comparator is lower than 1.2-V (VOL_LS), the comparator
sets output to "1" showing open load. Hence, the voltage required to trip OL1_LS comparator is calculated as:
VOL _ LS ! ILOAD u 15k:
(17)
By putting Equation 16 to Equation 17,
VOL _ LS !
VVM u 15k:
RL 15k:
(18)
By solving Equation 18, the load resistance (RL) is expressed as,
RL !
VVM u 15k:
15k:
VOL _ LS
(19)
By putting the values of VVM and VOL_HS in Equation 19, the load resistance (RL) is calculated as 135-kΩ for
supply voltage (VVM) of 12-V. Hence, any resistive load connected between VM and OUTx above this value (at
VVM = 12-V) is shown as an open-load.
250
Y Axis Title (Unit)
200
150
100
50
TA = -40°C
TA = 25°C
TA = 85°C
0
2
4
6
8
10
Supply Voltage (V)
12
14
16
18
D002
Figure 62. Resistance Threshold's for Open Load Detect in Supply (VM) Connected Load
NOTE
In the open load detection for load connected to supply (VM) configuration, the resistive
load threshold for an open load also depends on the supply voltage (VVM).
56
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8.2.3.4 OLD for Full Bridge Connected Load
Figure 63 shows the load connected as a full bridge configuration with internal OLD circuit. Full-bridge open load
sequence consists of turning-on the high-side switch (SW1_HS) of half-bridge-1 and low-side switch (SW2_LS)
of half-bridge-2 together. In a similar manner, the full-bridge open-load sequence for the other half bridge with
turning-on the high-side switch (SW2_HS) of half-bridge-2 and low-side switch (SW1_LS) of half-bridge-1
together is executed. Now, depending on the load presence, three cases are considered:
8.2.3.4.1 Full Bridge Open
If no-load is connected between the OUT1 and OUT2 terminals, then no current flows from internal regulator
(AVDD). Now, the voltage-drop at the positive terminal of high side comparator of half-bridge-1 (OL1_HS) and
the negative terminal of low side comparator of half-bridge-2 (OL2_LS) will be as follows:
8.2.3.4.1.1 High side comparator of half-bridge-1 (OL1_HS)
Since no current is flowing from the internal regulator (AVDD), the voltage at the OUT1 node (which is also the
positive terminal of OL1_HS comparator) is clamped to 4.2-V (i.e. AVDD). This if compared with 2.3-V (VOL_HS)
sets the comparator output to "1".
8.2.3.4.1.2 Low side comparator of half-bridge-2 (OL2_LS)
For an open load condition, no current flows through the SW2_LS switch, which pulls down the negative terminal
of OL2_LS comparator to 0-V (GND). This if compared with 1.2-V (VOL_LS) sets the comparator output to "1".
Now, if both the comparator outputs (OL1_HS and OL2_LS) is high, it signifies an open load.
8.2.3.4.2
Full Bridge Short
If there is short between the OUT1 and OUT2 terminals, then a short current (ISC) will flows from internal
regulator (AVDD) depending upon the high-side (12-kΩ) and low-side (15-kΩ) resistors as,
ISC
VAVDD
15k: 12k:
VAVDD
27k:
(20)
Hence the short-current flowing using Equation 20 is calculated as,
ISC
VAVDD
27k:
4.2V
27k:
155.56PA
(21)
Now, the voltage-drop at the positive terminal of high side comparator of half-bridge-1 (OL1_HS) and the
negative terminal of low side comparator of half-bridge-2 (OL2_LS) will be as follows:
8.2.3.4.2.1 High side comparator of half-bridge-1 (OL1_HS)
Now, the pull up current of ISC (155.56-µA) is flowing from the internal regulator (AVDD), therefore the voltage at
the positive terminal of OL1_HS comparator (which is also the OUT1 node) is calculated as,
VOL1_ HS
VAVDD
ISC u 12k:
(22)
using Equation 22, the VOL1_HS(+) is calculated as,
VOL1_ HS
4.2V 155.56PA u 12k:
2.33V
(23)
This voltage, if compared with 2.3-V (VOL_HS) sets the OL1_HS comparator output to "1".
8.2.3.4.2.2 Low side comparator of half-bridge-2 (OL2_LS)
The pull down current of ISC (155.56-µA) is flowing from the internal regulator (AVDD) to the SW2_LS switch,
therefore the voltage at the negative terminal of OL2_LS comparator is calculated as,
VOL2 _ LS
ISC u 15k:
(24)
Using Equation 24, the VOL2_LS is calculated as,
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VOL2 _ LS
155.56PA u 15k:
www.ti.com
2.33V
(25)
This voltage, if compared with 1.2-V (VOL_LS) reset the OL2_LS comparator output to "0".
Since, OL1_HS comparator shows an output "1" and OL2_LS comparator shows and output "0", therefore this
case is considered as no-open load.
AVDD
VM
SW1_HS
±
OL1_HS
VOL_HS
12 kŸ
+
IOL_PU
X
OUT1
SW1_LS
OLD1
IOL_PD
±
OL1_LS
+
AVDD
±
OL2_HS
X X
VOL_LS
15 kŸ
VM
SW2_HS
VOL_HS
12 kŸ
+
IOL_PU
X
X
OUT2
SW2_LS
OLD2
IOL_PD
X
±
OL2_LS
VOL_LS
+
15 kŸ
Figure 63. Open Load Detect Circuit for Motor Connected in Full Bridge Configuration
8.2.3.4.3
Load Connected in Full Bridge
If there is a load (RL) connected between the OUT1 and OUT2 terminals, then a load current (IL) is calculated as,
ILOAD
VAVDD
12k: RL 15k:
VAVDD
RL 27k:
(26)
Now, the voltage-drop at the positive terminal of high side comparator of half-bridge-1 (OL1_HS) and the
negative terminal of low side comparator of half-bridge-2 (OL2_LS) will be as follows:
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8.2.3.4.3.1 High side comparator of half-bridge-1 (OL1_HS)
If the voltage drop at positive terminal of OL1_HS comparator is higher than 2.3-V (VOL_HS), the comparator sets
output to "1" (for open load). Hence, the voltage required to trip the OL1_HS comparator is calculated as:
VOL _ HS
VAVDD ILOAD u 12k:
(27)
By putting Equation 26 into Equation 27,
VOLHS
VAVDD
VAVDD u 12k:
RL 27k:
(28)
By solving Equation 28, the load resistance (RL) is expressed as,
RL !
VAVDD u 12k:
VAVDD VOL _ HS
27k:
(29)
By putting the values of VAVDD and VOL_HS in Equation 29, the load resistance (RL) is calculated as (-)10.2-kΩ.
Since, the value of resistance is negative, therefore, the voltage at positive terminal of OL1_HS comparator is
always higher than VOL_HS and comparator output is always high ("1").
8.2.3.4.3.2 Low side comparator of half-bridge-2 (OL2_LS)
If the voltage drop at negative terminal of OL2_LS comparator is lower than 1.2-V (VOL_LS), the comparator sets
output to "1" showing as open load. Hence, the voltage required to trip the OL2_LS comparator is calculated as:
VOL _ LS ! ILOAD u 15k:
(30)
By putting Equation 26 to Equation 30,
VOL _ LS
VAVDD u 15k:
RL 27k:
(31)
By solving Equation 31, the load resistance (RL) is expressed as,
RL !
VAVDD u 15k:
VOL _ LS
27k:
(32)
By putting the values of VAVDD and VOL_LS in Equation 32, the load resistance (RL) is calculated as 25.5-kΩ.
Therefore, the output of OL2_HS comparator sets to 1, if the load resistance is greater than 25.5-kΩ.
Since, the OL1_HS comparator always outputs "1", therefore, the open load status is solely dependent on the
output of OL2_HS comparator. If OL2_HS comparator output is "1", then an open load is detected.
37.5
TA = -40°C
TA = 25°C
TA = 85°C
Resistance (k:)
35
32.5
30
27.5
25
2
4
6
8
10
Supply Voltage (V)
12
14
16
18
D003
Figure 64. Resistance Threshold's for Open Load Detect for Load Connected in Full-Bridge
Configuration
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9 Power Supply Recommendations
The DRV8847 device is designed to operate from an input voltage supply (VVM) range from 2.7 V to 18 V. Place
a 0.1-µF ceramic capacitor rated for VM as close to the DRV8847 device as possible. In addition, a bulk
capacitor with a value of at least 10 µF must be included on the VM pin.
9.1 Bulk Capacitance Sizing
Bulk capacitance sizing is an important factor in motor drive system design. The amount of bulk capacitance
depends on a variety of factors including:
• Type of power supply
• Acceptable supply voltage ripple
• Parasitic inductance in the power supply wiring
• Type of motor (brushed DC, brushless DC, stepper)
• Motor start-up current
• Motor braking method
The inductance between the power supply and motor drive system limits the rate that current can change from
the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands
or dumps from the motor with a change in voltage. Size the bulk capacitance to meet acceptable voltage ripple
levels.
The data sheet provides a recommended minimum value, but system-level testing is required to determine the
appropriate-sized bulk capacitor.
Parasitic Wire
Inductance
Motor Drive System
Power Supply
VM
+
+
Motor Driver
±
GND
Local
Bulk Capacitor
IC Bypass
Capacitor
Figure 65. Setup of Motor Drive System With External Power Supply
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10 Layout
10.1 Layout Guidelines
Bypass the VM pin to ground using a low-ESR ceramic bypass capacitor with a recommended value of 10 μF
and rated for VM. Place this capacitor as close to the VM pin as possible with a thick trace or ground plane
connection to the device GND pin.
10.2 Layout Example
nSLEEP
16
IN1
OUT1
15
IN2
ISEN12
14
MODE/SDA
4
OUT2
13
GND
5
OUT4
VM
12
6
SEN34
TRQ/SCL
11
7
OUT3
IN4
10
8
nFAULT
IN3
Figure 66. Layout Recommendation of 16-Pin TSSOP Package for Single-Layer Board
nSLEEP
16
IN1
OUT1
IN2
15
ISEN12
14
MODE
4
OUT2
GND
13
5
OUT4
12
VM
6
SEN34
11
TRQ
7
OUT3
IN4
10
8
nFAULT
IN3
Figure 67. Layout Recommendation of 16-Pin HTSSOP Package for Double-Layer Board
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IN2
IN1
nSLEEP
OUT1
Layout Example (continued)
OUT4
VM
ISEN34
TRQ
IN4
GND
IN3
OUT2
nFAULT
MODE
OUT3
ISEN12
Figure 68. Layout Recommendation of 16-Pin QFN Package for Double-Layer Board
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10.3 Thermal Considerations
10.3.1 Maximum Output Current
In actual operation, the maximum output current that is achievable with a motor driver is a function of the die
temperature. This die temperature is greatly affected by ambient temperature and PCB design. Essentially, the
maximum motor current is the amount of current that results in a power dissipation level that, along with the
thermal resistance of the package and PCB, keeps the die at a low enough temperature to avoid thermal
shutdown.
The dissipation ratings given in the data sheet can be used as a guide to calculate the approximate maximum
power dissipation that can be expected without putting the device in thermal shutdown for several different PCB
constructions. However, for accurate data, the actual PCB design must be analyzed through measurement or
thermal simulation.
10.3.2 Thermal Protection
The DRV8847 device has thermal shutdown (TSD) as described in the Maximum Output Current section. If the
die temperature exceeds approximately 150°C, the device is disabled until the temperature decreases 40°C.
Any tendency of the device to enter TSD is an indication of either excessive power dissipation, insufficient heatsinking, or too high an ambient temperature.
10.4 Power Dissipation
Power dissipation in the DRV8847 device is dominated by the DC power dissipated in the output FET resistance
(RDS(ON)_HS and RDS(ON)_LS). Additional power is dissipated because of PWM switching losses. These losses are
dependent on the PWM frequency, rise and fall times, and VM supply voltages. These switching losses are
typically on the order of 10% to 30% of the DC power dissipation.
Use Equation 33 to estimate the DC power dissipation of one H-bridge.
RDS(ON) _ LS u IOUT(RMS)2 RDS(ON) _ HS u IOUT(rms)2
PTOT
where
•
•
•
PTOT is the total power dissipation
IOUT(RMS) is the RMS output current being applied to motor
RDS(ON)_HS and RDS(ON)_LS are the high-side and low-side on-state resistance of the FET
(33)
NOTE
The value of RDS(ON)_HS and RDS(ON)_LS increases with temperature. Therefore, as the
device heats, the power dissipation increases. This relationship must be considered when
sizing the heat-sink.
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, DRV8847EVM User's Guide
• Texas Instruments, DRV8847EVM and DRV8847SEVM Software User's Guide
• Texas Instruments, Small Motors in Large Appliances TI TechNote
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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28-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
DRV8847PWPR
ACTIVE
HTSSOP
PWP
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
8847PWP
DRV8847PWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
8847PW
DRV8847RTER
ACTIVE
WQFN
RTE
16
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
8847
DRV8847RTET
ACTIVE
WQFN
RTE
16
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
8847
DRV8847SPWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
8847SPW
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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