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DRV8873
SLVSET1 – AUGUST 2018
DRV8873 H-Bridge Motor Driver
1 Features
3 Description
•
The DRV8873 device is an integrated driver IC for
driving a brushed DC motor in industrial applications.
Two logic inputs control the H-bridge driver, which
consists of four N-channel MOSFETs that drive
motors bi-directionally with up to 10-A peak current.
The device operates from a single power supply and
supports a wide input supply range from 4.5 V to 38
V.
1
•
•
•
•
•
•
•
•
•
•
H-Bridge Motor Driver
– Drives One DC Motor, One Winding of a
Stepper Motor, or Solenoid Loads
4.5-V to 38-V Operating Voltage Range
10-A Peak Current Drive
Low HS + LS RDS(ON)
– 150 mΩ at TJ = 25°C, 13.5 V
– 250 mΩ at TJ = 150°C, 13.5 V
Current Mirror for Output Current Sensing
Configurable Control Interface
– PH/EN
– PWM (IN1/IN2)
– Independent Half-Bridge Control
Supports 1.8-V, 3.3-V, 5-V Logic Inputs
SPI or Hardware Interface Options
Low-Power Sleep Mode (10 µA)
Small Package and Footprint
– 24 HTSSOP PowerPAD™ IC Package
Protection Features
– VM Undervoltage Lockout (UVLO)
– Charge Pump Undervoltage (CPUV)
– Overcurrent Protection (OCP)
– Output short to battery and short to ground
protection
– Open Load Detection
– Thermal Shutdown (TSD)
– Fault Condition Output (nFAULT / SPI)
A PH/EN or PWM interface allows simple interfacing
to controller circuits. Alternatively, independent halfbridge control is available to drive two solenoid loads.
A current mirror allows the controller to monitor the
load current. This mirror approximates the current
through the high-side FETs, and does not require a
high-power resistor for sensing the current.
A low-power sleep mode is provided to achieve verylow quiescent current draw by shutting down much of
the internal circuitry. Internal protection functions are
provided for undervoltage lockout, charge pump
faults, overcurrent protection, short-circuit protection,
open-load detection, and overtemperature. Fault
conditions are indicated on an nFAULT pin and
through the SPI registers.
Device Information(1)
PART NUMBER
DRV8873
PACKAGE
HTSSOP (24)
BODY SIZE (NOM)
7.70 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
4.5 to 38 V
2 Applications
DRV8873
•
•
•
•
•
•
•
ePOS and Currency Counters
ATMs (Automated Teller Machines)
Multi-Function Printers
Laser Beam Printers
Factory Automation and Robotics
Motorized Window Blinds
Adjustable Desks and Beds
Controller
PWM
DISABLE
H-Bridge Driver
SPI or HW
BDC
nFAULT
Current Sense
Monitor
Current Regulation
Built-In Protection
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRV8873
SLVSET1 – AUGUST 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
5
5
5
5
8
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
SPI Timing Requirements .........................................
Typical Characteristics ..............................................
7.6 Register Maps ......................................................... 35
8
8.1 Application Information............................................ 40
8.2 Typical Application .................................................. 40
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Power Supply Recommendations...................... 46
9.1 Bulk Capacitance Sizing ......................................... 46
10 Layout................................................................... 47
10.1 Layout Guidelines ................................................. 47
10.2 Layout Example .................................................... 47
11 Device and Documentation Support ................. 48
11.1
11.2
11.3
11.4
11.5
11.6
Detailed Description ............................................ 10
7.1
7.2
7.3
7.4
7.5
Application and Implementation ........................ 40
10
11
13
29
30
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
48
48
48
48
48
48
12 Mechanical, Packaging, and Orderable
Information ........................................................... 48
12.1 Package Option Addendum .................................. 49
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
August 2018
*
Initial release.
September 2018
0.95
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5 Pin Configuration and Functions
DRV8873H PWP PowerPAD Package
24-Pin HTSSOP
Top View
DRV8873S PWP PowerPAD Package
24-Pin HTSSOP
Top View
DVDD
1
24
GND
DVDD
1
24
GND
nFAULT
2
23
CPL
nFAULT
2
23
CPL
MODE
3
22
CPH
SDO
3
22
CPH
SR
4
21
VCP
SDI
4
21
VCP
nITRIP
5
20
VM
SCLK
5
20
VM
nOL
6
19
OUT1
nSCS
6
19
OUT1
18
OUT1
Thermal
EN/IN1
7
PH/IN2
Thermal
18
OUT1
EN/IN1
7
8
17
SRC
PH/IN2
8
17
SRC
DISABLE
9
16
SRC
DISABLE
9
16
SRC
IPROPI1
10
15
OUT2
IPROPI1
10
15
OUT2
nSLEEP
11
14
OUT2
nSLEEP
11
14
OUT2
IPROPI2
12
13
VM
IPROPI2
12
13
VM
Pad
Not to scale
Pad
Not to scale
Pin Functions
PIN
NAME
NO.
TYPE (1)
DESCRIPTION
DRV8873H
DRV8873S
CPH
22
22
PWR
Charge pump switching node. Connect a X7R capacitor with a value of 47 nF
between the CPH and CPL pins.
CPL
23
23
PWR
Charge pump switching node. Connect a X7R capacitor with a value of 47 nF
between the CPH and CPL pins.
DVDD
1
1
PWR
Digital regulator. This pin is the 5-V internal digital-supply regulator. Bypass
this pin to GND with a 6.3-V, 1-µF ceramic capacitor.
EN/IN1
7
7
I
Control Inputs. For details, see the Control Modes section. This pin has an
internal pulldown resistor to GND.
DISABLE
9
9
I
Bridge disable input. A logic high on this pin disables the H-bridge Hi-Z.
Internal pullup to DVDD.
GND
24
24
PWR
IPROPI1
10
10
O
High-side FET current. The analog current proportional to the current flowing
in the half bridge.
IPROPI2
12
12
O
High-side FET current. The analog current proportional to the current flowing
in the half bridge.
nITRIP
5
—
I
Internal current-regulation control pin (ITRIP). To enable the ITRIP feature,
do not connect this pin (or tie it to GND). To disable the ITRIP feature,
connect this pin to the DVDD pin.
nOL
6
—
I
Open-load diagnostic control pin. To run the open-load diagnostic at power
up, tie it to ground. Connect it to DVDD, open-load diagnostic will be
disabled.
Ground pin
MODE
3
—
I
Input mode pin. Sets the PH/EN, PWM, or independent-PWM mode.
OUT1
18
18
O
Half-bridge output 1. Connect this pin to the motor or load.
OUT1
19
19
O
Half-bridge output 1. Connect this pin to the motor or load.
OUT2
14
14
O
Half-bridge output 2. Connect this pin to the motor or load.
OUT2
15
15
O
Half-bridge output 2. Connect this pin to the motor or load.
(1)
I = input, O = output, PWR = power, NC = no connect, OD = open-drain output, PP = push-pull output
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Pin Functions (continued)
PIN
TYPE (1)
NO.
NAME
DESCRIPTION
DRV8873H
DRV8873S
PH/IN2
8
8
I
Control inputs. For details, see the Control Modes section. This pin has an
internal pulldown resistor to GND.
SCLK
—
5
I
Serial clock input. Serial data is shifted out and captured on the
corresponding rising and falling edge on this pin.
SDI
—
4
I
Serial data input. Data is captured on the falling edge of the SCLK pin.
SDO
—
3
PP
Serial data output. Data is shifted out on the rising edge of the SCLK pin.
This is a push-pull output.
SR
4
—
I
Slew rate adjust. This pin sets the slew rate of the H-bridge outputs.
SRC
16
16
O
Power FET source. Tie this pin to GND through a low-impedance path.
SRC
17
17
O
Power FET source. Tie this pin to GND through a low-impedance path.
VCP
21
21
PWR
Charge pump output. Connect a 16-V, 1-µF ceramic capacitor from this pin to
the VM supply.
VM
13
13
PWR
Power supply. This pin is the motor supply voltage. Bypass this pin to GND
with a 0.1-µF ceramic capacitor and a bulk capacitor.
VM
20
20
PWR
Power supply. This pin is the motor supply voltage. Bypass this pin to GND
with a 0.1-µF ceramic capacitor and a bulk capacitor.
nFAULT
2
2
OD
nSCS
—
6
I
Serial chip select. An active low on this pin enables the serial interface
communications. Internal pullup to nSLEEP.
nSLEEP
11
11
I
Sleep input. To enter a low-power sleep mode, set this pin logic low.
Fault indication pin. This pin is pulled logic low with a fault condition. This
open-drain output requires an external pullup resistor.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
Power supply voltage
VM
–0.3
40
V
Charge pump voltage
VCP, CPH
–0.3
VVM + 5.7
V
Charge pump switching pin
CPL
–0.3
VVM
V
Internal logic regulator voltage
DVDD
–0.3
5.7
V
Digital pin voltage
EN/IN1, PH/IN2, nSLEEP, DISABLE, nFAULT,
MODE, SR, SCLK, SDI, SDO, nSCS
–0.3
5.7
V
VTRIP
Analog pin voltage
IPROPI1, IPROPI2
0
5.5
V
VSRC
H-Bridge source pin voltage
V
–0.3
0.3
VSRC – 1
VVM + 1
nFAULT
0
10
mA
SDO
0
10
mA
Phase node pin voltage
OUTx
Open drain output current
Push-pull output current
V
TJ
Operating junction temperature
–40
150
°C
Tstg
Storage temperature
–65
150
°C
(1)
4
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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6.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
V(ESD)
(1)
(2)
Electrostatic
discharge
Charged device model (CDM), per
JEDEC specification JESD22-C101, all pins (2)
UNIT
±2000
Corner pins (1, 12, 13,
and 24)
±750
Other pins
±500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
4.5
38
V
0
5.5
V
100
kHz
125
°C
150
°C
VVM
Power supply voltage
VI
Logic level input voltage
fPWM
Applied PWM signal (EN/IN1, PH/IN2)
TA
Operating ambient temperature
–40
TJ
Operating junction temperature
–40
UNIT
6.4 Thermal Information
DRV8873-Q1
THERMAL METRIC
(1)
PWP (HTSSOP)
UNIT
24 PINS
RθJA
Junction-to-ambient thermal resistance
27.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
18.8
°C/W
RθJB
Junction-to-board thermal resistance
5.1
°C/W
ΨJT
Junction-to-top characterization parameter
0.3
°C/W
ΨJB
Junction-to-board characterization parameter
5.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.0
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
Over recommended operating conditions unless otherwise noted. Typical limits apply for TA = 25°C and VVM = 13.5 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLIES (VM, DVDD)
VVM
VM operating voltage
4.5
IVM
VM operating supply current
VVM = 13.5 V; nSLEEP = 1; DISABLE
=0
IVM(Q)
VM sleep mode supply current
VVM = 13.5 V; nSLEEP = 0
VDVDD
Internal logic regulator voltage
2-mA load, VVM > 5.5 V
4.7
t(SLEEP)
Sleep time
nSLEEP low to start device shutdown
50
t(RESET)
nSLEEP reset pulse
nSLEEP low to only clear fault registers
t(WAKE)
38
V
10
mA
15
30
µA
5
5.3
V
5
µs
5
20
µs
Wake-up time
nSLEEP high to device ready for input
signals
1.5
ms
ton
Turn-on time
VM > V(UVLO); nSLEEP = 1, to output
transition
1.5
ms
t(DISABLE)
DISABLE deglitch time
DISABLE signal transition
2.5
µs
CHARGE PUMP (VCP, CPH, CPL)
VVCP
VCP operating voltage
with respect to VM
IVCP
VCP current
VVM = 13.5 V
f(VCP)
Charge pump switching frequency
VVM > V(UVLO); nSLEEP = 1
VVM+5
7
V
10
400
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mA
kHz
5
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SLVSET1 – AUGUST 2018
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Electrical Characteristics (continued)
Over recommended operating conditions unless otherwise noted. Typical limits apply for TA = 25°C and VVM = 13.5 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LOGIC-LEVEL INPUTS (EN/IN1, PH/IN2, nSLEEP, SCLK, SDI)
VIL
Input logic-low voltage
VIH
Input logic-high voltage
VHYS
Input logic hysteresis
IIL
Input logic-low current
VIN = 0 V
IIH
Input logic-high current
VIN = 5 V
RPD
Internal pulldown resistance
Propagation delay (EN/IN1, PH/IN2
to OUTx = 50%)
tpd
0
0.8
V
1.6
5.3
V
150
mV
–5
5
µA
50
µA
to GND
100
kΩ
SR = 000b; IO = 1 A
1.2
SR = 001b; IO = 1 A
1.6
SR = 010b; IO = 1 A
2.6
SR = 011b; IO = 1 A
3.4
SR = 100b; IO = 1 A
4.1
SR = 101b; IO = 1 A
5.2
SR = 110b; IO = 1 A
7.8
SR = 111b; IO = 1 A
13.3
DISABLE to DVDD
100
µs
LOGIC-LEVEL INPUT (DISABLE)
RPU,DIS
Internal pull-up resistance
VIL,DIS
Input logic-low voltage
VIH,DIS
Input logic-high voltage
kΩ
0
0.8
V
1.6
5.3
V
0
0.8
V
1.6
5.3
LOGIC-LEVEL INPUT (nSCS)
VIL,nSCS
Input logic-low voltage
VIH,nSCS
Input logic-high voltage
RPU,nSCS
Internal pull-up resistance
nSCS to nSLEEP
450
V
kΩ
LOGIC-LEVEL INPUT (nSLEEP)
VIL,SLEEP
Input logic-low voltage
VIH,SLEEP
Input logic-high voltage
IIH,SLEEP
Input logic-high current
0
0.8
2.7
5.3
VIN = 5 V; nSCS is High
80+ISDO
(1)
V
V
µA
THREE-LEVEL INPUT (MODE)
RIN-1
Input mode 1
Tied to GND
RIN-2
Input mode 2
Tied to GND
RIN-3
Input mode 3
Tied to DVDD
105
190
Ω
kΩ
105
Ω
30
50
Ω
120
240
Ω
PUSH-PULL OUTPUT (SDO)
RPD,SDO
Internal pull-down resistance
With respect to GND
RPU,SDO
Internal pull-up resistance
With respect to nSLEEP
OPEN DRAIN OUTPUT (nFAULT)
VOL
Output logic-low voltage
IO = 2 mA
IOZ
Output high-impedance leakage
VO = 5 V
–2
0.1
V
2
µA
MOTOR DRIVER OUTPUTS (OUT1, OUT2)
RDS(ON)
High-side FET on-resistance
RDS(ON)
Low-side FET on-resistance
t(DEAD)
VF(DIODE)
(1)
6
VVM = 13.5 V; TA = 25°C; TJ = 25°C
75
VVM = 13.5 V; TA = 25°C; TJ = 150°C
125
155
mΩ
VVM = 13.5 V; TA = 25°C; TJ = 25°C
75
VVM = 13.5 V; TA = 25°C; TJ = 150°C
125
Output dead time
SR = 100b
500
ns
Body diode forward voltage
IO = 1 A
0.8
V
155
mΩ
SDO output current external to the device
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Electrical Characteristics (continued)
Over recommended operating conditions unless otherwise noted. Typical limits apply for TA = 25°C and VVM = 13.5 V
PARAMETER
ISINK
SR
Sink current when OUTx = Hi-Z
Slew rate (H/W Device)
OUTx 10% to 90% changing
TEST CONDITIONS
MIN
nSLEEP = 0
SR
MAX
62
nSLEEP = 1, DISABLE = 1
340
IO = 1 A; Connect to GND
53.2
IO = 1 A; R(SR) = 22 kΩ ± 5% to GND
34
IO = 1 A; R(SR) = 68 kΩ ± 5% to GND
18.3
IO = 1 A; No connect (Hi-Z)
13
IO = 1 A; R(SR) = 51 kΩ ± 5% to DVDD
7.9
IO = 1 A; Connect to DVDD
Slew rate (SPI Device)
OUTx 10% to 90% changing
TYP
UNIT
µA
V/µs
2.6
IO = 1 A; SR = 000b
53.2
IO = 1 A; SR = 001b
34
IO = 1 A; SR = 010b
18.3
IO = 1 A; SR = 011b
13
IO = 1 A; SR = 100b
10.8
IO = 1 A; SR = 101b
7.9
IO = 1 A; SR = 110b
5.3
IO = 1 A; SR = 111b
2.6
V/µs
CURRENT SENSE OUTPUTS (IPROPI1, IPROPI2)
k
Current mirror scaling
kERR
Current mirror scaling
t(IPROPI)
OUTx to IPROPI
1100
A/A
IO < 1 A
–50
50
mA
IO ≥ 1 A
–5
5
%
VO = 2 V; SR = 000b
2.2
VO = 2 V; SR = 111b
10.5
µs
CURRENT REGULATION
ITRIP
Current limit threshold
tOFF
PWM off-time
tBLANK
PWM blanking time
ITRIP_LVL = 00b; VVM = 13.5 V
3.27
3.85
4.43
ITRIP_LVL = 01b; VVM = 13.5 V
4.6
5.4
6.2
ITRIP_LVL = 10b; VVM = 13.5 V
5.5
6.5
7.5
ITRIP_LVL = 11b; VVM = 13.5 V
5.95
7
8.1
TOFF = 00b
20
TOFF = 01b
40
TOFF = 10b
60
TOFF = 11b
80
A
µs
5
µs
PROTECTION CIRCUITS
4.35
4.45
VM rising; UVLO recovery
4.5
4.7
VM UVLO falling deglitch time
VM falling; UVLO report
10
VM UVLO reset
VM falling; UVLO report; device reset
VVCP(UV)
Charge pump undervoltage
VVM = 12 V; TA = 25°C; CPUV report
I(OCP)
Overcurrent protection trip level
t(OCP)
Overcurrent deglitch time
t(RETRY)
Overcurrent retry time (H/W Device)
V(UVLO)
VM undervoltage lockout
t(UVLO)
V(RST)
t(RETRY)
Overcurrent retry time (SPI Device)
VOLA
Open load active mode
VM falling; UVLO report
µs
4.1
VVM + 2.25
A
3
5
4
OCP_TRETRY = 00b
0.5
OCP_TRETRY = 01b
1
OCP_TRETRY = 10b
2
ms
ms
300
450
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4
150
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V
V
10
OCP_TRETRY = 11b
V
mV
7
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SLVSET1 – AUGUST 2018
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Electrical Characteristics (continued)
Over recommended operating conditions unless otherwise noted. Typical limits apply for TA = 25°C and VVM = 13.5 V
PARAMETER
TEST CONDITIONS
MIN
TYP
OL_DLY = 0b
0.3
OL_DLY = 1b
1.2
MAX
UNIT
td(OL)
Open load diagnostic delay time
ms
IOL
Open load current
TOTW
Thermal warning temperature
Die temperature (TJ)
140
150
160
°C
TTSD
Thermal shutdown temperature
Die Temperature (TJ)
165
175
185
°C
Thys
Thermal shutdown hysteresis
Die temperature (TJ)
3
mA
20
°C
6.6 SPI Timing Requirements
MIN
NOM
MAX
UNIT
t(READY)
SPI ready, VM > V(UVLO)
t(CLK)
SCLK minimum period
100
ns
t(CLKH)
SCLK minimum high time
50
ns
t(CLKL)
SCLK minimum low time
50
ns
tsu(SDI)
SDI input setup time
20
ns
th(SDI)
SDI input hold time
30
td(SDO)
SDO output delay time, SCLK high to SDO valid, CL = 20 pF
tsu(nSCS)
nSCS input setup time
th(nSCS)
nSCS input hold time
t(HI_nSCS)
nSCS minimum high time before active low
tdis(nSCS)
nSCS disable time, nSCS high to SDO high impedance
t(HI_nSCS)
1
ms
ns
30
ns
50
ns
50
ns
500
ns
10
ns
th(nSCS)
tsu(nSCS)
t(CLK)
t(CLKH)
X
t(CLKL)
LSB
MSB
X
tsu(SDI) th(SDI)
Z
LSB
MSB
td(SDO)
Z
tdis(nSCS)
Figure 1. SPI Slave-Mode Timing Definition
8
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6.7 Typical Characteristics
160
6
140
5
Operating Current (mA)
RDS(ON) (m:)
120
100
80
60
40
4
3
2
1
20
0
-50
0
50
100
Temperature (qC)
150
0
-50
200
0
D001
Figure 2. RDS(on) vs Temperature
50
100
Temperature (qC)
150
200
D002
Figure 3. Operating Current (IVM) vs Temperature
20
6.2
18
6
14
ITRIP Current (A)
Sleep Current (PA)
16
12
10
8
6
4
5.8
5.6
5.4
5.2
2
0
-50
0
50
100
Temperature (qC)
150
5
-50
200
0
D003
50
100
Temperature (qC)
150
200
D004
ITRIP = 01b
Figure 4. Sleep Current (IVM(Q)) vs Temperature
Figure 5. ITRIP Current vs Temperature
7.8
8
7.7
7
7.6
7.5
ITRIP Current (A)
ITRIP Current (A)
6
5
4
3
7.4
7.3
7.2
7.1
7
6.9
2
6.8
1
6.7
0
-50
0
50
100
Temperature (qC)
150
200
6.6
-50
0
D005
ITRIP = 10b
50
100
Temperature (qC)
150
200
D006
ITRIP = 11b
Figure 6. ITRIP Current vs Temperature
Figure 7. ITRIP Current vs Temperature
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7 Detailed Description
7.1 Overview
The device is an integrated, 4.5-V to 38-V motor driver for industrial brushed-motor applications. The device is
capable of high output-current drive using low-RDS(ON) integrated MOSFETs.
A standard 4-wire serial peripheral interface (SPI) decreases the device pin count by allowing the various device
settings and fault reporting to be managed through an external controller. Alternatively a hardware interface
option device is available for easy configuration with less detailed control of all device functions.
The device integrates a current mirror which provides an output current proportional to the current through the
high-side FETs. This feature allows the system to monitor the motor current without the need for a large highpower resistor for current sensing. The device has a built-in current regulation feature with a fixed off-time
current-chopping scheme. The current-chopping level is selected through SPI in the SPI version of the device
and in the hardware version of the device is it a fixed value.
In addition to the high level of driver integration, the device provides a broad range of integrated protection
features. These features include power-supply undervoltage lockout (UVLO), charge-pump undervoltage lockout,
overcurrent faults, open-load detection, output short to battery and short to ground protection, and thermal
shutdown. Device faults are indicated by the nFAULT pin with detailed information available in the device
registers.
The device integrates a spread spectrum clocking feature for both the internal digital oscillator and internal
charge pump. This feature combined with output slew rate control minimizes the radiated emissions from the
device.
The device is available in a 24-pin HTSSOP package with a thermal pad.
10
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7.2 Functional Block Diagram
1 µF
DVDD
VM
VM
VCP
Power
1 µF
VM
VM
VCP
0.1 µF
CPH
Charge
Pump
47 nF
Internal
Regulators
CPL
0.1 µF
+
bulk
OUT1
Predriver
IN1
VCP
BDC
VM
IN2
Core
Logic
nSLEEP
OUT2
Predriver
DVDD
SRC
DISABLE
nSLEEP
Control
Inputs
VTRIP
nOL
IPROPI1
Protection
SR
Undervoltage
Overcurrent
MODE
Thermal
nITRIP
RSENSE-1
Current
Sense
Output
IPROPI2
Open Load
RSENSE-2
RnFAULT
nFAULT
Output
GND
PPAD
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Figure 8. Hardware Device Block Diagram
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Functional Block Diagram (continued)
1 µF
DVDD
VM
VM
VCP
Power
1 µF
VM
VM
VCP
0.1 µF
CPH
Charge
Pump
47 nF
Internal
Regulators
CPL
0.1 µF
+
bulk
OUT1
Predriver
IN1
VCP
BDC
VM
IN2
Control
Inputs
nSLEEP
Core
Logic
OUT2
Predriver
DVDD
SRC
DISABLE
RnFAULT
VTRIP
Output
nFAULT
IPROPI1
Protection
nSLEEP
Undervoltage
nSCS
SPI
nSLEEP
SDI
Overcurrent
Thermal
RSENSE-1
Current
Sense
Output
IPROPI2
Open Load
RSENSE-2
SDO
SCLK
GND
PPAD
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Figure 9. Software Device Block Diagram
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7.3 Feature Description
Table 1 lists the recommended external components for the device.
Table 1. External Components
COMPONENT
PIN 1
PIN 2
RECOMMENDED
CVM1
VM
GND
0.1-µF ceramic capacitor rated for VM
CVM2
VM
GND
Bulk capacitor rated for VM
CVCP
VCP
VM
16-V, 1-µF ceramic capacitor
CFLY
CPH
CPL
47-nF capacitor rated for VM
CDVDD
DVDD
GND
6.3-V, 1-µF ceramic capacitor
(1)
RnFAULT
VCC
nFAULT
≥ 10-kΩ pullup resistor
RMODE
MODE
GND or DVDD
Device hardware interface
RSENSE-1
IPROPI1
GND
Resistors to convert mirrored current into a voltage
RSENSE-2
IPROPI2
GND
Resistors to convert mirrored current into a voltage
(1)
VCC is not a pin on the device, but a VCC supply-voltage pullup is required for the open-drain output nFAULT.
7.3.1 Bridge Control
The device output has four N-channel MOSFETs configured in a H-bridge. The driver can be controlled using a
PH/EN, PWM, or independent half-bridge input mode. Table 2 lists the control mode configurations.
Table 2. Control Mode Configuration
HARDWARE DEVICE
MODE PIN
SPI DEVICE
MODE REGISTER
CONTROL MODE
L
00b
PH/EN
H
01b (default)
PWM
200 kΩ ± 5% to GND
10b
Independent half bridge
Not applicable
11b
Input disabled, bridge Hi-Z
In the hardware version of the device, the MODE pin determines the control interface and latches on power-up or
when exiting sleep mode. During the device power-up sequence, the DVDD pin is enabled first, and then the
MODE pin latches. Tying the MODE pin directly to ground sets the mode to phase and enable. Tying the MODE
pin to the DVDD pin, or an external 5 V rail, sets the mode to PWM. Connecting the MODE pin to ground with a
200 kΩ ± 5% resistor sets the mode to independent half-bridge where the two half-bridges can be independently
controlled by their respective input (INx) pins. Table 3 lists the different MODE pin settings.
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Table 3. DRV8873H MODE Pin Settings
CONNECTION
MODE
CIRCUIT
Connect to GND
Phase and Enable
200 kΩ ± 5% to GND
Independent half-bridge
MODE
MODE
RMODE
DVDD
Connect to DVDD
MODE
PWM
In the SPI version of the device, the mode setting can be changed by writing to the MODE register in the IC1
control register because this device version has no dedicated MODE pin. The device mode gets latched when
the DISABLE signal transitions from high to low.
7.3.1.1 Control Modes
The device output consists of four N-channel MOSFETs that are designed to drive high current. The MOSFETs
are controlled by two logic inputs, EN/IN1 and PH/IN2, in three different input modes to support various
commutation and control methods, as shown in the logic tables (Table 4, Table 5, and Table 6). In the
Independent PWM mode, the fault handling is performed independently for each half bridge. For example, if an
overcurrent condition (OCP) is detected in half-bridge 1, only the half-bridge 1 output (OUT1) is disabled and
half-bridge 2 continues to operate based on the IN2 input.
Table 4. PH/EN Mode Truth Table
14
nSLEEP
DISABLE
EN/IN1
PH/IN2
OUT1
OUT2
0
X
X
X
Hi-Z
Hi-Z
1
1
X
X
Hi-Z
Hi-Z
1
0
0
X
H
H
1
0
1
0
L
H
1
0
1
1
H
L
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Table 5. PWM Mode Truth Table
nSLEEP
DISABLE
EN/IN1
PH/IN2
OUT1
OUT2
0
X
X
X
Hi-Z
Hi-Z
1
1
X
X
Hi-Z
Hi-Z
1
0
0
0
Hi-Z
Hi-Z
1
0
0
1
L
H
1
0
1
0
H
L
1
0
1
1
H
H
Table 6. Independent Mode Truth Table
nSLEEP
DISABLE
EN/IN1
PH/IN2
OUT1
OUT2
0
X
X
X
Hi-Z
Hi-Z
1
1
X
X
Hi-Z
Hi-Z
1
0
0
0
L
L
1
0
0
1
L
H
1
0
1
0
H
L
1
0
1
1
H
H
The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM)
for variable motor speed. When using PWM mode (MODE = 1), switching between driving and braking typically
is best. For example, to drive a motor forward with 50% of its maximum revolutions per minute (RPM), the IN1
pin is high and the IN2 pin is low during the driving period. During the other period in this example, the IN1 pin is
high and the IN2 pin is high.
VM
VM
VM
VM
2
2
1
SH1
3
SH2
SH1
SH2
SH1
SH2
SH1
SH2
1 Forward drive
2 High-side recirculation (brake)
3 Reverse drive
Figure 10. Half-Bridge Current Paths
In the Independent PWM mode, to independently put the outputs of the half bridge in the high-impedance (Hi-Z)
state, the OUT1_DIS or OUT2_DIS bit in the IC3 register must be set to 1b. Writing a logic 1 to the OUT1_DIS
bit disables the OUT1 output. Writing a logic 1 to the OUT2_DIS bit disables the OUT2 output. The default value
in these registers is 0b. The option to independently set the outputs of the half bridge in the Hi-Z state is not
available for the hardware version of the device.
7.3.1.2 Half-Bridge Operation
The device can be used to drive two solenoids or unidirectional brushed DC-motor loads instead of a brushedDC motor in full H-bridge configuration. Independent half-bridge control is preferred for operation in this mode;
however, using the PH/EN or PWM modes is not restricted if the correct driving and braking states can be
achieved.
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VCP
VM
VM
+
0.1 µF
bulk
OUT1
Predriver
BDC
VCP
VM
OUT2
Predriver
SRC
BDC
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Figure 11. Independent Half bridge Mode Driving Two Low-Side Loads
TI does not recommend tying the OUT1 and OUT2 pins together and drive a load. The half bridges may be out
of synchronization in this configuration and any mismatch in the input commands can momentarily result in shoot
through condition. This mismatch can be mitigated by adding an inductor in-line with the outputs.
If loads are connected between the OUTx and VM pins, the device can draw more current than specified in the
Electrical Characteristics table. To avoid this condition, TI recommends connecting loads in the configuration
shown in Figure 11.
Depending on how the loads are connected on the outputs pin, some of the features offered by the device could
have reduced functionality. For example, having a load between the OUTx and GND pins, as shown in
Figure 11, results in false trips of the open-load diagnosis in active-mode (OLA). Having a load tied between the
OUTx and VM pins restricts the use of internal current regulation because no means of measuring current
flowing through the load with the current mirror block is available. Table 7 lists these use cases.
Table 7. Control Mode Configuration
LOAD CONNECTIONS
16
FUNCTIONALITY
NODE 1
NODE 2
OLA
OUTx
GND
Not Available
Operational
OUTx
VM
Operational
Not Available
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CURRENT REGULATION (ITRIP)
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7.3.1.3 Internal Current Sense and Current Regulation
The IPROPI pin outputs an analog current that is proportional to the current flowing in the H-bridge. The output
current is typically 1/1100 of the current in both high-side FETs. The IPROPI pin is derived from the current
through either of the high-side FETs. Because of this, the IPROPI pin does not represent the half bridge current
when operating in a fast decay mode or low-side slow decay mode. The IPROPI pin represents the H-bridge
current under forward drive, reverse drive, and high-side slow decay. The IPROPI output is delayed by
approximately 2 µs for the fastest slew-rate setting (43.2 V/µs) after the high-side FET is switched on.
VM
HS1
SENSE_FET
1/1100 scaled
HS1
PWR_FET
OUT1
Current Sense
and
Current Regulation
IPROPI1
RSENSE-1
VM
HS2
SENSE_FET
1/1100 scaled
HS2
PWR_FET
Current Sense
and
Current Regulation
OUT2
IPROPI2
RSENSE-2
Figure 12. Current-Sense Block Diagram
The selection of the external resistor should be such that the voltage on the IPROPI pin is less than 5 V.
Therefore the resistor must be sized less than this value based on Equation 1. The range of current that can be
monitored is from 100 mA to 10 A assuming the selected external resistor meets the calculated value from
Equation 1. If the current exceeds 10 A, the device could reach overcurrent protection (OCP) or overtemperature
shutdown (TSD). If OCP occurs, the device disables the internal MOSFETs and protects itself (for the hardware
version of the device) or based on the OCP_MODE setting (for the SPI version of the device). For guidelines on
selecting a sense resistor, see the Sense Resistor section.
R(SENSE) = k × 5 V / IO
where
•
•
k is the current mirror scaling factor, which is typically 1100.
IO is the maximum drive current to be monitored.
(1)
NOTE
Texas Instruments recommends the load current not exceed 8 A during normal operation.
If slew rate setting of 2.6 V/µs (SR = 111b) is used when the load current is about 8 A,
choose TOFF to be either 40 µs or 60 µs.
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The SPI version of the device limits the output current based on the trip level set in the SPI registers. In the
hardware version of the device, the current trip limit is set to 6.5 A. The current regulation feature is enabled by
default on both the outputs (OUT1 and OUT2). To disable current regulation in the hardware version of the
device, the nITRIP pin must be connected to DVDD. To disable current regulation in the SPI version of the
device, the DIS_ITRIP bits in the IC4 Control register must be written to. The bit settings are:
• 01b to disable current regulation only on the OUT1 pin
• 10b to disable current regulation only on the OUT2 pin
• 11b to disable current regulation on both the OUT1 and OUT2 pins
Table 8. Control Regulation Threshold
PARAMETER
ITRIP
Current limit threshold
ITRIP_LVL BIT
MIN
TYP
MAX
UNIT
ITRIP_LVL = 00b
3.4
4
4.6
A
ITRIP_LVL = 01b
4.6
5.4
6.2
A
ITRIP_LVL = 10b
5.5
6.5
7.5
A
ITRIP_LVL = 11b
6
7
8
A
When the ITRIP current has been reached, the device enforces slow current decay by enabling both the high-side
FETs for a time of tOFF . In the hardware version of the device, the tOFF time is 40 µs. The tOFF time is selectable
through SPI in the SPI version of the device, as shown in Table 9. The default setting is 01b (tOFF = 40 µs).
Table 9. PWM Off Time Settings
PARAMETER
tOFF
PWM off time
TOFF BIT
tOFF DURATION
UNIT
TOFF = 00b
20
µs
TOFF = 01b
40
µs
TOFF = 10b
60
µs
TOFF = 11b
80
µs
Drive Current (A)
ITRIP
tBLANK
Drive
Brake or Slow Decay
Drive
Brake or Slow Decay
tDRIVE
tOFF
tDRIVE
tOFF
Figure 13. Current Regulation Time Periods
When the tOFF time has elapsed and the current level falls below the current regulation (ITRIP) level, the output is
re-enabled according to the inputs. If, after the tOFF time has elapsed the current is still higher than the ITRIP level,
the device enforces another tOFF time period of the same duration.
The drive time (tDRIVE) occurs until another ITRIP event is reached and depends heavily on the VM voltage, the
back-EMF of the motor, and the inductance of the motor. During the tDRIVE time, the current-sense regulator does
not enforce the ITRIP limit until the tBLANK time has elapsed. While in current regulation, the inputs can be toggled
to drive the load in the opposite direction to decay the current faster. For example, if the load was in forward
drive prior to entering current regulation it can only go into reverse drive when the driver enforces current
regulation.
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The IPROPI1 pin represents the current flowing through the HS1 MOSFET of half-bridge 1. The IPROPI2 pin
represents the current flowing through the HS2 MOSFET of half-bridge 2. To measure current with one sense
resistor, the IPROPI1 and IPROPI2 pins must be connected together with the RSENSE resistor as shown in
Figure 14. In this configuration, the current-sense output is proportional to the sum of the currents flowing
through the both high-side FETs.
IPROPI1
Current-Sense
Output
RSENSE-1
IPROPI2
GND
PPAD
Figure 14. Current Sense Output
7.3.1.4 Slew-Rate Control
The rise and fall times (tr and tf) of the outputs can be adjusted on the hardware version of the device by
changing the value of an external resistor connected from the SR pin to ground. On the SPI version of the
device, the slew rate can be adjusted through the SPI. The output slew rate is adjusted internally to the device by
controlling the ramp rate of the driven FET gate. The voltage or resistance on the SR pin sets the output rise and
fall times in the hardware version of the device.
Table 10. DRV8873H Slew Rate (SR) Pin Connections
CONNECTION
SR
Connect to GND
53.2 V/µs
22 kΩ ± 5% to GND
34 V/µs
CIRCUIT
SR
SR
RSR
68 kΩ ± 5% to GND
SR
18.3 V/µs
RSR
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Table 10. DRV8873H Slew Rate (SR) Pin Connections (continued)
CONNECTION
SR
> 2 MΩ to GND (Hi-Z)
13 V/µs
CIRCUIT
SR
DVDD
51 kΩ ± 5% to DVDD
SR
7.9 V/µs
DVDD
Connect to DVDD
SR
2.6 V/µs
Figure 15 shows the internal circuit block for the SR pin.
SLEW RATE
53.2 V/µs
+
VREF
±
34 V/µs
DVDD
+
VREF
±
SR
18.3 V/µs
+
VREF
±
13 V/µs
+
VREF
±
7.9 V/µs
+
VREF
±
2.6 V/µs
Figure 15. SR Block Diagram
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Table 11 lists the settings in the SPI register that set the output rise and fall times in the SPI version of the
device.
Table 11. DRV8873S Slew Rate Settings
SR
RISE TIME (V/µs)
FALL TIME (V/µs)
000b
53.2
53.2
001b
34
34
010b
18.3
18.3
011b
13
13
100b
10.8
10.8
101b
7.9
7.9
110b
5.3
5.3
111b
2.6
2.6
The typical voltage on the SR pin is 3 V and is driven internally. Changing the resistor value on the SR pin
changes the slew-rate setting from approximately 2.6 V/µs to 53.2 V/µs. The recommended values for the
external resistor are shown in the Slew Rate section. If the SR pin is grounded then the slew rate is 53.2 V/µs.
Leaving the SR pin as a no-connect pin sets the slew rate to 13 V/µs. Tying it to the DVDD pin sets the slew rate
to 2.6 V/µs.
7.3.1.5 Dead Time
The dead time (t(DEAD)) is measured as the time when the OUTx pin is in the Hi-Z state between turning off one
of the half bridge MOSFETs and turning on the other. For example, the output is in the Hi-Z state between
turning off the high-side MOSFET and turning on the low-side MOSFET, or turning on the high-side MOSFET
and turning off the low-side MOSFET.
IN1
IN2
OUT1
tPD
t(DEAD)
tR
tPD
t(DEAD)
tF
tPD
t(DEAD)
tF
tPD
t(DEAD)
tR
OUT2
Figure 16. Propagation Delay Time
If the output pin is measured during the tDEAD time the voltage depends on the direction of the current. If the
current is leaving the pin, the voltage is a diode drop below ground. If the current is entering the pin, the voltage
is a diode drop above VM. The diode drop is associated with the body diode of the high-side or the low-side FET.
The dead time is dependent on the slew-rate setting because a portion of the FET gate ramp includes the
observable dead time.
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7.3.1.6 Propagation Delay
The propagation delay time (tPD) is measured as the time between an input edge to an output change. This time
comprises two parts: an input deglitcher and output slewing delay. The input deglitcher prevents noise on the
input pins from affecting the output state. The adjustable slew rate also contributes to the propagation delay time.
For the fastest slew-rate setting, the tPD time is typically 1.5 µs, and for the slowest slew-rate setting, the tPD time
is typically 4.5 µs. For the output to change state during normal operation, one FET must first be turned off.
7.3.1.7 nFAULT Pin
The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. When a fault is
detected, the nFAULT line is logic low. For a 3.3-V pullup the nFAULT pin can be tied to the DVDD pin with a
resistor (see the Application and Implementation section). For a 5-V pullup, an external 5-V supply must be used.
Output
nFAULT
Figure 17. nFAULT Pin
During the device power-up sequence, or when exiting sleep mode, the nFAULT pin is held low until the digital
core is alive and functional. This low level signal on the nFAULT line does not represent a fault condition. The
signal can be used by the external MCU to determine when the digital core of the device is ready; however, this
does not mean that the device is ready to accept input commands via the INx pins.
7.3.1.8 nSLEEP as SDO Reference
The nSLEEP pin manages the state of the device. The device goes into sleep mode with a logic-low signal, and
comes out of sleep mode when the nSLEEP pin goes high. The signal level when the nSLEEP pin goes high
determines the logic level on the SDO output in the SPI version of the device. A 3.3-V signal on the nSLEEP pin
provides a 3.3-V output on the SDO output. A 5-V signal on the nSLEEP pin provides a 5-V output on the SDO
pin. If the sleep feature is not required, the nSLEEP pin can be connected to the MCU power supply. In that
case, when the MCU is powered-up, the motor driver device is also be powered-up.
DVDD
nSLEEP
Digital
Core
400 k
100 k
nSCS
Figure 18. nSCS and nSLEEP Circuit
In the SPI version of the device, if the nSLEEP reset pulse is used to clear faults, the SDO voltage reference is
not available for the duration of the nSLEEP reset pulse. No data can be transmitted on the SDO line for the
duration when the nSLEEP pin is held low. Therefore, TI recommends using the CLR_FLT bit in the IC3 control
register to clear the faults.
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7.3.2 Motor Driver Protection Circuits
The device is fully protected against VM undervoltage conditions, charge-pump undervoltage conditions,
overcurrent events, and overtemperature events.
7.3.2.1 VM Undervoltage Lockout (UVLO)
If at any time the voltage on the VM pin falls below the UVLO-threshold voltage, V(UVLO), for the voltage supply,
all the outputs (OUTx) are disabled, and the nFAULT pin is driven low. The charge pump is disabled in this
condition. The FAULT and UVLO bits are latched high in the SPI registers. Normal operation resumes (motordriver operation and nFAULT released) when the VM undervoltage condition is removed. The UVLO bit remains
set until it is cleared through the CLR_FLT bit or an nSLEEP reset pulse.
NOTE
During the power-up sequence VM must exceed V(UVLO) recovery max limit in order to
power-up and function properly. After a successful power-up sequence, the device can
operate down to the V(UVLO) report limit before going into the undervoltage lockout
condition.
7.3.2.2 VCP Undervoltage Lockout (CPUV)
If at any time the voltage on the VCP pin falls below the VVCP(UV) voltage for the charge pump, all the outputs
(OUTx) are disabled, and the nFAULT pin is driven low. The charge pump remains active during this condition.
The FAULT and CPUV bits are latched high in the SPI registers. Normal operation resumes (motor-driver
operation and nFAULT released) when the VCP undervoltage condition is removed. The CPUV bit remains set
until it is cleared through the CLR_FLT bit or an nSLEEP reset pulse. This protection feature can be disabled by
setting the DIS_CPUV bit high.
7.3.2.3 Overcurrent Protection (OCP)
If the current in any FET exceeds the I(ocp) limits for longer than the t(OCP) time, all FETs in the half bridge are
disabled and the nFAULT pin is driven low. The charge pump remains active during this condition. The
overcurrent protection can operate in four different modes: latched shutdown, automatic retry, report only, and
disabled. In the independent PWM mode (MODE = 10b or MODE pin to ground with a 200-kΩ ± 5% resistor) the
fault handling is performed independently for each half-bridge based on the OCP mode selected. This protection
scheme protects the outputs from shorts to battery and shorts to ground.
7.3.2.3.1 Latched Shutdown (OCP_MODE = 00b)
In this mode, after an OCP event, all the outputs (OUTx) are disabled and the nFAULT pin are driven low. The
FAULT, OCP, and corresponding MOSFET OCP bits are latched high in the SPI registers. Normal operation
resumes (motor-driver operation and nFAULT released) when the OCP condition is removed and a clear faults
command has been issued either through the CLR_FLT bit or an nSLEEP reset pulse. This mode is the default
mode for an OCP event for both the hardware version and SPI version of the device.
7.3.2.3.2 Automatic Retry (OCP_MODE = 01b)
In this mode, after an OCP event all the outputs (OUTx) are disabled and the nFAULT pin is driven low. The
FAULT, OCP, and corresponding MOSFET OCP bits are latched high in the SPI registers. Normal operation
resumes automatically (motor-driver operation and nFAULT released) after the t(RETRY) time has elapsed and the
fault condition is removed.
7.3.2.3.3 Report Only (OCP_MODE = 10b)
In this mode, no protective action is performed when an overcurrent event occurs. The overcurrent event is
reported by driving the nFAULT pin low and latching the FAULT, OCP, and corresponding MOSFET OCP bits
high in the SPI registers. The motor driver continues to operate. The external controller acts appropriately to
manage the overcurrent condition. The reporting is cleared (nFAULT released) when the OCP condition is
removed and a clear faults command has been issued either through the CLR_FLT bit or an nSLEEP reset
pulse.
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7.3.2.3.4 Disabled (OCP_MODE = 11b)
In this mode, no protective or reporting action is performed when an overcurrent event occurs. The device
continues to drive the load based on the input signals.
7.3.2.4 Open-Load Detection (OLD)
If the motor is disconnected from the device, an open-load condition is detected and the nFAULT pin is latched
low until a clear faults command is issued by the MCU either through the CLR_FLT bit or an nSLEEP reset
pulse. The fault also clears when the device is power cycled or comes out of sleep mode. The OLD test is
designed for applications that have capacitance less than 15 nF when the OL_DLY bit set to 0b and for less than
60 nF when the OL_DLY bit is set to 1b on the OUTx pins. This setting is equivalent to measuring the resistance
values listed in Table 12.
Table 12. Resistance for Open Load Detection
NODE 1
NODE 2
RESISTANCE
OUT1
OUT2
2 kΩ
OUTx
VM
12 kΩ
OUTx
GND
3 kΩ
COMMENTS
VVM = 13.5 V
Open load detection works in both standby mode (OLP) and active mode (OLA). OLP detects the presence of
the motor prior to commutating the motor. OLA detects the motor disconnection from the driver during
commutation.
7.3.2.4.1 Open-Load Detection in Passive Mode (OLP)
The open-load passive diagnostic (OLP) is different for the hardware and SPI version of the device. The OLP
test is available in all three modes of operation (PN/EN, PWM, and independent half-bridge). When the openload test is running, the internal power MOSFETs are disabled.
For the hardware version of the device, the OLP test is performed at power-up or after exiting sleep mode if the
nOL pin is left as a no connect pin (or tied to GND). If the nOL pin is tied to the DVDD pin (or an external 5-V
rail), the OLP test is not performed by the device.
For the SPI version of the device, the OLP test is performed when commanded. The following sequence shows
how to perform the OLP test directly after the device powers up:
1. Power up the device (DISABLE pin high).
2. Select the mode through SPI.
3. Wait for the t(DISABLE) time to expire.
4. Write 1b to the EN_OL bit in the IC1 register.
5. Perform the OLP test.
– If an open load (OL) is detected, the nFAULT pin is driven low, the FAULT and OLx bits are latched high.
When the OL condition is removed, a clear faults command must be issued by the MCU either through
the CLR_FLT bit or an nSLEEP reset pulse which resets the OLx register bit.
– If an OL condition is not detected, the EN_OL bits return to the default setting (0b) after the td(OL) time
expires.
6. Set the DISABLE pin low so that the device drives the motor or load based on the input signals.
If an open-load diagnostic is performed at any other time, the following sequence must be followed:
1. Set the pin DISABLE high (to disable the half bridge outputs).
2. Wait for the t(DISABLE) time to expire.
3. Write 1b to the EN_OL bit in the IC1 register.
4. Perform the OLP test.
– If an OL condition is detected, the nFAULT pin is driven low, and the FAULT and OLx bits are latched
high. When the OL condition is removed, a clear faults command must be issued by the MCU either
through the CLR_FLT bit or an nSLEEP reset pulse which resets the OLx register bits.
– If an OL condition is not detected, the EN_OL bits return to the default setting (0b) after the td(OL) time
expires.
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5. Set the DISABLE pin low so that the device drives the motor or load based on the input signals.
DVDD
DVDD
VM
OL1_PU
output
4V
OUT1
1V
OL1_PD
output
DVDD
VM
Digital
Core
OL2_PU
output
4V
OUT2
SRC
OL2_PD
output
1V
Figure 19. Open-Load Detection Circuit
The EN_OL register maintains the written command until the diagnostic is complete. The signal on the DISABLE
pin must remain high for the entire duration of the test. While the OLP test is running, if the DISABLE pin goes
low, the OLP test is aborted to resume normal operation and no fault is reported. The OLP test is not performed
if the motor is energized.
The OLD test checks for a high-impedance connection on the OUTx pins. The diagnostic runs in two steps. First
the pullup current source is enabled. If a load is connected, the current passes through the pullup resistor and
the OLx_PU comparator output remains low. If an OL condition exists, the current through the pullup resistor
goes to 0 A and the OLx_PU comparator trips high. Second the pulldown current source is enabled. In the same
way, the OLx_PD comparator output either remains low to indicate that a load is connected, or trips high to
indicate an OL condition.
If both the OLx_PU and OLx_PD comparators report an OL condition, the OLx bit in the SPI register latches high
and the nFAULT line goes low to indicate an OL fault. When the OL condition is removed, a clear faults
command must be issued by the MCU either through the CLR_FLT bit or an nSLEEP reset pulse which resets
the OL1 and OL2 register bits. The charge pump remains active during this fault condition.
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7.3.2.4.2 Open-Load Detection in Active Mode (OLA)
Open load in active mode is detected when the OUT1 and OUT2 voltages do not exhibit overshoot greater than
the VOLA over VM between the time the low-side FET is switched off and the high-side FET is switched on during
an output PWM cycle, as shown in Figure 20. An open load is not detected if the energy stored in the inductor is
high enough to cause an overshoot greater than the VOLA over VM caused by the flyback current flowing through
the body diode of the high-side FET. The OLA diagnostic is disabled by default and can be enabled by writing a
1b to the EN_OLA bit in IC4 control register.
SH2
SH1
VM
SH2
SH1
+
SH1
VM
Detects OLD
if the diode VF
drop < VOLA
SH2
±
VM
No OLD detected
if the diode VF
drop > VOLA
Figure 20. Open-Load Active Mode Circuit
In PH/EN and PWM mode, the motor current decays by high-side recirculation. In independent PWM mode, the
motor can enter the brake state either by high-side or low-side recirculation. If the motor enters the brake state
using low-side recirculation, the diode VF voltage of high-side FET is less than the VOLA voltage which flags an
open load fault even though the load is connected across the OUT1 and OUT2 pins. In this case, the OLA mode
should not be used. If high-side current recirculation is done with independent PWM mode, the OLA mode
functions properly.
NOTE
The OLA mode is functional only when high-side recirculation of the motor current occurs.
Depending on the operation conditions and external circuitry, such as the output
capacitors, an open load condition could be indicated even though the load is present.
This case might occur, for example, during a direction change or for small load currents
with respectively small PWM duty cycles. Therefore, TI recommends evaluating the open
load diagnosis only in known, suitable operating conditions and to ignore it otherwise.
To avoid inadvertently triggering the open load diagnosis, a failure counter is implemented. Three consecutive
occurrences of the internal open-load signal must occur, essentially three consecutive PWM pulses without
freewheeling detected, before an open load condition is reported by the nFAULT pin and in the SPI register.
In the hardware version of the device, OLA mode is active when the nOL pin if left as a no-connect pin or tied to
ground. If low-side current recirculation is done with independent PWM control, an open load condition is
detected even though the load is connected. To avoid this false trip, the OLD must be disabled by taking the nOL
pin high; however, both OLA and OLP diagnostics will be disabled.
7.3.2.5 Thermal Shutdown (TSD)
If the die temperature exceeds the thermal shutdown limit, the half bridge are disabled, and the nFAULT pin is
driven low. The charge pump remains active during this condition. In addition, the FAULT bit and TSD bit are
latched high. This protection feature cannot be disabled. The overtemperature protection can operate in two
different modes: latched shutdown and automatic recovery.
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7.3.2.5.1 Latched Shutdown (TSD_MODE = 0b)
In this mode, after a TSD event all the outputs (OUTx) are disabled and the nFAULT pin is driven low. The
FAULT and TSD bits are latched high in the SPI register. Normal operation resumes (motor-driver operation and
the nFAULT line released) when the TSD condition is removed and a clear faults command has been issued
either through the CLR_FLT bit or an nSLEEP reset pulse. This mode is the default mode for a TSD event in the
SPI version of the device.
7.3.2.5.2 Automatic Recovery (TSD_MODE = 1b)
In this mode, after a TSD event all the outputs (OUTx) are disabled and the nFAULT pin is driven low. The
FAULT and TSD bits are latched high in the SPI register. Normal operation resumes (motor-driver operation and
the nFAULT line released) when the junction temperature falls below the overtemperature threshold limit minus
the hysteresis (TTSD – THYS). The TSD bit remains latched high indicating that a thermal event occurred until a
clear faults command is issued either through the CLR_FLT bit or an nSLEEP reset pulse. This mode is the
default mode for a TSD event in the hardware version of the device.
7.3.2.6 Thermal Warning (OTW)
If the die temperature exceeds the trip point of the thermal warning (TOTW) the OTW bit is set in the registers of
SPI devices. The device performs no additional action and continues to function. When the die temperature falls
below the hysteresis point of the thermal warning, the OTW bit clears automatically. The OTW bit can also be
configured to report on the nFAULT pin, and set the FAULT bit in the SPI version of the device, by setting the
OTW_REP bit to 1b through the SPI registers. The charge pump remains active during this condition.
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Table 13. Fault Response
FAULT
CONDITION
CONFIGURATION
REPORT
HALF BRIDGE
LOGIC
RECOVERY
VM undervoltage (UVLO)
VVM < V(UVLO)
(maximum 4.45 V)
—
nFAULT
Hi-Z
Reset
Automatic: VVM > V(UVLO)
(maximum 4.55 V)
Charge pump undervoltage
(CPUV)
VVCP < VVCP(UV)
(typical VVM + 2.25 V)
DIS_CPUV = 0b
nFAULT
Hi-Z
Active
Automatic: VVCP > VVCP(UV)
(typical VVM + 2.25 V)
Overcurrent (OCP)
IO > I(OCP)
(minimum 10 A)
Open load (OLD)
No load detected
Current regulation (ITRIPx)
IO > ITRIP_LVL
28
Thermal shutdown (TSD)
TJ > TTSD
(minimum 165°C)
Thermal Warning (OTW)
TJ > TOTW
(minimum 140°C)
DIS_CPUV = 1b
none
Active
Active
No action
OCP_MODE = 00b
nFAULT
Hi-Z
Active
Latched: CLR_FLT/nSLEEP
OCP_MODE = 01b
nFAULT
Hi-Z
Active
Retry: t(RETRY)
OCP_MODE = 10b
nFAULT
Active
Active
No action
OCP_MODE = 11b
none
Active
Active
No action
EN_OLP = 1b
nFAULT
Active
Active
Latched: CLR_FLT/nSLEEP
EN_OLA = 1b
nFAULT
Active
Active
Latched: CLR_FLT/nSLEEP
ITRIP_REP = 0b
none
Active
Active
No action
ITRIP_REP = 1b
nFAULT
Active
Active
No action
TSD_MODE = 0b
nFAULT
Hi-Z
Active
Latched: CLR_FLT/nSLEEP
TSD_MODE = 1b
nFAULT
Hi-Z
Active
Automatic:
TJ > TTSD – THYS
(THYS typical 20°C)
OTW_REP = 0b
none
Active
Active
No action
OTW_REP = 1b
nFAULT
Active
Active
Automatic: TJ < TOTW – THYS
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7.3.3 Hardware Interface
The hardware-interface device option lets the device be configured without a SPI, however not all of the
functionality is configurable. The following configuration settings are fixed for the hardware interface device
option:
• CPUV is enabled
• OCP_MODE is latched shutdown
• TSD_MODE is automatic recovery
• OL_DLY is 300 µs
• ITRIP level is 6.5-A if current regulation is enabled by the nITRIP pin
• OLA is activated when the open load diagnostic is enabled by the nOL pin
• No option to independently set the outputs (OUTx) to the Hi-Z state
7.3.3.1 MODE (Tri-Level Input)
The MODE pin of the hardware version of the device determines the control interface and latches on power-up or
when exiting sleep mode. Table 14 lists the different control interfaces that can be set with the MODE pin.
Table 14. DRV8873H MODE Settings
MODE
CONTROL MODE
L
PH/EN
H
PWM
Hi-Z (200 kΩ ± 5% to GND)
Independent half bridge
When the MODE pin is latched on power-up or when exiting sleep mode; any additional changes to the signal at
the MODE pin are ignored by the device. To change the mode settings, a power cycle or sleep reset must be
performed on the device. To use the device in PWM mode, tie the MODE pin to either the DVDD pin or an
external 5-V rail. To use the device in independent half-bridge mode, the MODE pin must be connected to with a
200-kΩ ± 5% resistor (or left as a no connect). Tying the MODE pin to the GND pin puts the device in phase and
enable (PH/EN) mode.
7.3.3.2 Slew Rate
The rise and fall times of the outputs can be selected based on the configuration listed in Table 15 for the
hardware version of the device.
Table 15. Slew Rate Settings in H/W Device
SR PIN CONNECTION
RISE TIME (V/µs)
FALL TIME (V/µs)
53.2
Connect to GND
53.2
22 kΩ ± 5% to GND
34
34
68 kΩ ± 5% to GND
18.3
18.3
> 2MΩ to GND (Hi-Z)
13
13
51 kΩ ± 5% to DVDD
7.9
7.9
Connect to DVDD
2.6
2.6
7.4 Device Functional Modes
7.4.1 Motor Driver Functional Modes
7.4.1.1 Sleep Mode (nSLEEP = 0)
The nSLEEP pin sets the state of the device. When the nSLEEP pin is low, the device goes to a low-power sleep
mode. In sleep mode, all the internal MOSFETs are disabled, the charge pump is disabled, and the SPI is
disabled. The t(SLEEP) time must elapse after a falling edge on the nSLEEP pin before the device enters sleep
mode. The device goes from sleep mode automatically if the nSLEEP pin is brought high. The t(WAKE) time must
elapse before the device is ready for inputs.
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Device Functional Modes (continued)
7.4.1.2 Disable Mode (nSLEEP = 1, DISABLE = 1)
The DISABLE pin is used to enable or disable the half bridge in the device. When the DISABLE pin is high, the
output drivers are disabled in the Hi-Z state. In this mode, the open-load diagnostic can be performed for the SPI
version of the device because the SPI remains active.
7.4.1.3 Operating Mode (nSLEEP = 1, DISABLE = 0)
When the nSLEEP pin is high, the DISABLE pin is low, and VM > V(UVLO), the device enters the active mode. The
t(WAKE) time must elapse before the device is ready for inputs. In this mode, the charge pump and low-side gate
regulator are enabled.
7.4.1.4 nSLEEP Reset Pulse
In addition to the CLR_FLT bit in the SPI register, a latched fault can be cleared through a quick nSLEEP pulse.
This pulse must be greater than the nSLEEP deglitch time of 5 µs and shorter than 20 µs. If nSLEEP is low for
longer than 20 µs, the faults are cleared and the device may or may not shutdown, as shown in the timing
diagram (see Figure 21). This reset pulse resets any SPI faults and does not affect the status of the charge
pump or other functional blocks.
nSLEEP
5 µs
No Action. nSLEEP
low pulse is too short
(deglitch)
20 µs
30 µs
50 µs
60 µs
All faults cleared, device stays active
All faults cleared, device may or may not shutdown
Device shutdowns down (goes into sleep mode, faults cleared by default)
Device shutdowns down (sleep mode)
Figure 21. nSLEEP Reset Pulse
7.5 Programming
7.5.1 Serial Peripheral Interface (SPI) Communication
The SPI version of the device has full duplex, 4-wire synchronous communication. This section describes the SPI
protocol, the command structure, and the control and status registers. The device can be connected with the
MCU in the following configurations:
• One slave device
• Multiple slave devices in parallel connection
• Multiple slave devices in series (daisy chain) connection
7.5.1.1 SPI Format
The SDI input data word is 16 bits long and consists of the following format:
• 1 read or write bit, W (bit 14)
• 5 address bits, A (bits 13 through 9)
• 8 data bits, D (bits 7 through 0)
The SDO output-data word is 16 bits long and the first 8 bits make up the Status Register (S1). The Report word
(R1) is the content of the register being accessed.
For a write command (W0 = 0), the response word on the SDO pin is the data currently in the register being
written to.
For a read command (W0 = 1), the response word is the data currently in the register being read
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Programming (continued)
Table 16. SDI Input Data Word Format
R/W
ADDRESS
DATA
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
0
W0
A4
A3
A2
A1
A0
X
D7
D6
D5
D4
D3
D2
D1
D0
Table 17. SDO Output Data Word Format
STATUS
REPORT
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
1
1
OTW
UVLO
CPUV
OCP
TSD
OLD
D7
D6
D5
D4
D3
D2
D1
D0
7.5.1.2 SPI for a Single Slave Device
The SPI is used to set device configurations, operating parameters, and read out diagnostic information. The
device SPI operates in slave mode. The SPI input-data (SDI) word consists of a 16-bit word, with 8 bits
command and 8 bits of data. The SPI output data (SDO) word consists of 8 bits of status register with fault status
indication and 8 bits of register data. Figure 22 shows the data sequence between the MCU and the SPI slave
driver.
nSCS
A1
D1
S1
R1
SDI
SDO
Figure 22. SPI Transaction Between MCU and SPI version of the device
A
•
•
•
•
•
•
•
•
valid frame must meet the following conditions:
The SCLK pin must be low when the nSCS pin goes low and when the nSCS pin goes high.
The nSCS pin should be taken high for at least 500 ns between frames.
When the nSCS pin is asserted high, any signals at the SCLK and SDI pins are ignored, and the SDO pin is
in the high-impedance state (Hi-Z).
Full 16 SCLK cycles must occur.
Data is captured on the falling edge of the clock and data is driven on the rising edge of the clock.
The most-significant bit (MSB) is shifted in and out first.
If the data word sent to SDI pin is less than 16 bits or more than 16 bits, a frame error occurs and the data
word is ignored.
For a write command, the existing data in the register being written to is shifted out on the SDO pin following
the 8-bit command data.
7.5.1.3 SPI for Multiple Slave Devices in Parallel Configuration
Multiple devices can be connected in parallel as shown in Figure 23. In this configuration, all the slave devices
can share the same SDI, SDO, and CLK lines from the micro-controller, but has dedicated chip-select pin (CSx)
for each device from the micro-controller.
The micro-controller activates the SPI of a given device via that device's chip-select input, the other devices
remain inactive for SPI transactions. This configuration helps reduce micro-controller resources for SPI
transactions if multiple slave devices are connected to the same micro-controller.
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SCLK
nSCS
SDI2
DRV8873_3
SDO2
SPI
SDI3
SDO3
SPI
SCLK
SDO1
SPI
nSCS
SDI1
DRV8873_2
nSCS
DRV8873_1
SCLK
Microcontroller
M-CS1
M-CS2
M-CS3
M-CLK
M-SDO
M-SDI
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Figure 23. Three DRV8873S Devices Connected in Parallel Configuration
7.5.1.4 SPI for Multiple Slave Devices in Daisy Chain Configuration
The device can be connected in a daisy chain configuration to keep GPIO ports available when multiple devices
are communicating to the same MCU. Figure 24 shows the topology when three devices are connected in series.
Slave Device
(1)
Master
Device
M-SDO
SDI1
SDO1 / SDI2
Slave Device
(2)
Slave Device
(3)
SDO1 / SDI2
SDO3
M-nSCS
M-SCLK
M-SDI
Figure 24. Three DRV8873S Devices Connected in Daisy Chain
The first device in the chain receives data from the MCU in the following format for 3-device configuration: 2
bytes of header (HDRx) followed by 3 bytes of address (Ax) followed by 3 bytes of data (Dx).
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nSCS
HDR1
HDR2
A3
A2
A1
D3
D2
D1
S1
HDR1
HDR2
A3
A2
R1
D3
D2
S2
S1
HDR1
HDR2
A3
R2
R1
D3
S3
S2
S1
HDR1
HDR2
R3
R2
R1
SDI1
SDO1 / SDI2
SDO2 / SDI3
SDO3
All Address bytes
reach destination
Status response here
All Data bytes
reach destination
Reads executed here
Writes executed here
Figure 25. SPI Frame With Three DRV8873S Devices
After the data has been transmitted through the chain, the MCU receives the data string in the following format
for 3-device configuration: 3 bytes of status (Sx) followed by 2 bytes of header followed by 3 bytes of report (Rx).
nSCS
HDR1
HDR2
A3
A2
A1
D3
D2
D1
S3
S2
S1
HDR1
HDR2
R3
R2
R1
SDI
SDO
Figure 26. SPI Data Sequence for Three DRV8873S Devices
The header bytes contain information of the number of devices connected in the chain, and a global clear fault
command that will clear the fault registers of all the devices on the rising edge of the chip select (nSCS) signal.
Header values N5 through N0 are 6 bits dedicated to show the number of devices in the chain. Up to 63 devices
can be connected in series for each daisy chain connection.
The 5 LSBs of the HDR2 register are don’t care bits that can be used by the MCU to determine integrity of the
daisy chain connection. Header bytes must start with 1 and 0 for the two MSBs.
HDR 1
1
0
N5
N4
N3
HDR 2
N2
N1
No. of devices in the chain
(up to 26 ± 1= 63)
N0
1
0
CLR
x
x
1 = global FAULT clear
0 = GRQ¶W FDUH
x
x
x
'RQ¶W FDUH
Figure 27. Header Bytes
The status byte provides information about the fault status register for each device in the daisy chain so that the
MCU does not have to initiate a read command to read the fault status from any particular device. This keeps
additional read commands for the MCU and makes the system more efficient to determine fault conditions
flagged in a device. Status bytes must start with 1 and 1 for the two MSBs.
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1
0
N5
N4
N3
N2
N1
N0
1
0
CLR
X
X
X
X
X
Status Byte
(Sx)
1
1
OTW
UVLO
CPUV
OCP
TSD
OLD
Address Byte
(Ax)
0
R/W
A4
A3
A2
A1
A0
X
D7
D6
D5
D4
D3
D2
D1
D0
Header Bytes
(HDRx)
Data Byte
(Dx)
Figure 28. Contents of Header, Status, Address, and Data Bytes
When data passes through a device, it determines the position of itself in the chain by counting the number of
status bytes it receives followed by the first header byte. For example, in this 3-device configuration, device 2 in
the chain receives two status bytes before receiving the HDR1 byte which is then followed by the HDR2 byte.
From the two status bytes, the data can determine that its position is second in the chain. From the HDR2 byte,
the data can determine how many devices are connected in the chain. In this way, the data only loads the
relevant address and data byte in its buffer and bypasses the other bits. This protocol allows for faster
communication without adding latency to the system for up to 63 devices in the chain.
The address and data bytes remain the same with respect to a 1-device connection. The report bytes (R1
through R3), as shown in Figure 26, are the content of the register being accessed.
nSCS
SCLK
SDI
X
MSB
LSB
X
SDO
Z
MSB
LSB
Z
Capture
Point
Propagate
Point
Figure 29. SPI Transaction
34
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7.6 Register Maps
Table 18 lists the memory-mapped registers for the device. All register addresses not listed in Table 18 should
be considered as reserved locations and the register contents should not be modified.
Table 18. Memory Map
Register
Name
7
6
FAULT Status
RSVD
FAULT
OTW
UVLO
CPUV
OCP
DIAG Status
OL1
OL2
ITRIP1
ITRIP2
OCP_H1
OCP_L1
IC1 Control
5
TOFF
IC2 Control
ITRIP_REP
IC3 Control
CLR_FLT
IC4 Control
RSVD
4
SPI_IN
TSD_MODE
2
0
Access
Type
Address
TSD
OLD
R
0x00
OCP_H2
OCP_L2
R
0x01
MODE
RW
0x02
OCP_MODE
RW
0x03
RW
0x04
RW
0x05
1
SR
OTW_REP
DIS_CPUV
LOCK
EN_OLP
3
OCP_TRETRY
OUT1_DIS
OLP_DLY
EN_OLA
OUT2_DIS
EN_IN1
ITRIP_LVL
PH_IN2
DIS_ITRIP
Complex bit access types are encoded to fit into small table cells. Table 19 shows the codes that are used for
access types in this section.
Table 19. Access Type Codes
Access Type
Code
Description
R
Read
W
Write
Read Type
R
Write Type
W
Reset or Default Value
-n
Value after reset or the default
value
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7.6.1 Status Registers
The status registers are used to reporting warning and fault conditions. Status registers are read-only registers
Table 20 lists the memory-mapped registers for the status registers. All register offset addresses not listed in
Table 20 should be considered as reserved locations and the register contents should not be modified.
Table 20. Status Registers Summary Table
Address
Register Name
Section
0x00
FAULT status
Go
0x01
DIAG status
Go
7.6.1.1 FAULT Status Register Name (address = 0x00)
FAULT status is shown in Figure 30 and described in Table 21.
Read-only
Figure 30. FAULT Status Register
7
RSVD
6
FAULT
R-0b
5
OTW
R-0b
4
UVLO
R-0b
3
CPUV
R-0b
2
OCP
R-0b
1
TSD
R-0b
0
OLD
R-0b
Table 21. FAULT Status Register Field Descriptions
Bit
Field
Type
Default
Description
7
RSVD
R
0b
Reserved
6
FAULT
R
0b
Global FAULT status register. Compliments the nFAULT pin
5
OTW
R
0b
Indicates overtemperature warning
4
UVLO
R
0b
Indicates UVLO fault condition
3
CPUV
R
0b
Indicates charge-pump undervoltage fault condition
2
OCP
R
0b
Indicates an overcurrent condition
1
TSD
R
0b
Indicates an overtemperature shutdown
0
OLD
R
0b
Indicates an open-load detection
7.6.1.2 DIAG Status Register Name (address = 0x01)
DIAG status is shown in Figure 31 and described in Table 22.
Read-only
Figure 31. DIAG Status Register
7
OL1
R-0b
6
OL2
R-0b
5
ITRIP1
R-0b
4
ITRIP2
R-0b
3
OCP_H1
R-0b
2
OCP_L1
R-0b
1
OCP_H2
R-0b
0
OCP_L2
R-0b
Table 22. DIAG Status Register Field Descriptions
Bit
Field
Type
Default
Description
7
OL1
R
0b
Indicates open-load detection on half bridge 1
6
OL2
R
0b
Indicates open-load detection on half bridge 2
5
ITRIP1
R
0b
Indicates the current regulation status of half bridge 1.
0b = Indicates output 1 is not in current regulation
1b = Indicates output 1 is in current regulation
36
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Table 22. DIAG Status Register Field Descriptions (continued)
Bit
4
Field
Type
Default
Description
ITRIP2
R
0b
Indicates the current regulation status of half bridge 2.
0b = Indicates output 2 is not in current regulation
1b = Indicates output 2 is in current regulation
3
OCP_H1
R
0b
Indicates overcurrent fault on the high-side FET of half bridge 1
2
OCP_L1
R
0b
Indicates overcurrent fault on the low-side FET of half bridge 1
1
OCP_H2
R
0b
Indicates overcurrent fault on the high-side FET of half bridge 2
0
OCP_L2
R
0b
Indicates overcurrent fault on the low-side FET of half bridge 2
7.6.2 Control Registers
The IC control registers are used to configure the device. Status registers are read and write capable.
Table 23 lists the memory-mapped registers for the control registers. All register offset addresses not listed in
Table 23 should be considered as reserved locations and the register contents should not be modified.
Table 23. Control Registers Summary Table
Address
Register Name
Section
0x02
IC1 control
Go
0x03
IC2 control
Go
0x04
IC3 control
Go
0x05
IC4 control
Go
7.6.2.1 IC1 Control Register (address = 0x02)
IC1 control is shown in Figure 32 and described in Table 24.
Read/Write
Figure 32. IC1 Control Register
7
6
TOFF
R/W-01b
5
SPI_IN
R/W-0b
4
3
SR
R/W-100b
2
1
0
MODE
R/W-01b
Table 24. IC1 Control Register Field Descriptions
Bit
Field
Type
Default
Description
7-6
TOFF
R/W
01b
00b = 20 µs
01b = 40 µs
10b = 60 µs
11b = 80 µs
5
SPI_IN
R/W
0b
0b = Outputs follow input pins (INx)
1b = Outputs follow SPI registers EN_IN1 and PH_IN2
4-2
SR
R/W
100b
000b = 53.2-V/µs rise time
001b = 34-V/µs rise time
010b = 18.3-V/µs rise time
011b = 13-V/µs rise time
100b = 10.8-V/µs rise time
101b = 7.9-V/µs rise time
110b = 5.3-V/µs rise time
111b = 2.6-V/µs rise time
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Table 24. IC1 Control Register Field Descriptions (continued)
Bit
Field
Type
Default
Description
1-0
MODE
R/W
01b
00b = PH/EN
01b = PWM
10b = Independent half bridge
11b = Input disabled; bridge Hi-Z
7.6.2.2 IC2 Control Register (address = 0x03)
IC2 control is shown in Figure 33 and described in Table 25.
Read/Write
Figure 33. IC2 Control Register
7
ITRIP_REP
R/W-0b
6
TSD_MODE
R/W-0b
5
OTW_REP
R/W-0b
4
DIS_CPUV
R/W-0b
3
2
1
OCP_TRETRY
R/W-11b
0
OCP_MODE
R/W-00b
Table 25. IC2 Control Register Field Descriptions
Bit
Field
Type
Default
Description
7
ITRIP_REP
R/W
0b
0b = ITRIP is not reported on nFAULT or the FAULT bit
6
TSD_MODE
R/W
0b
1b = ITRIP is reported on nFAULT and the FAULT bit
0b = Overtemperature condition causes a latched fault
1b = Overtemperature condition causes an automatic recovery
fault
5
OTW_REP
R/W
0b
0b = OTW is not reported on nFAULT or the FAULT bit
1b = OTW is reported on nFAULT and the FAULT bit
4
DIS_CPUV
R/W
0b
0b = Charge pump undervoltage fault is enabled
1b = Charge pump undervoltage fault is disabled
3-2
OCP_TRETRY
R/W
11b
00b = Overcurrent retry time is 0.5 ms
01b = Overcurrent retry time is 1 ms
10b = Overcurrent retry time is 2 ms
11b = Overcurrent retry time is 4 ms
1-0
OCP_MODE
R/W
00b
00b = Overcurrent condition causes a latched fault
01b = Overcurrent condition causes an automatic retrying fault
10b = Overcurrent condition is report only but no action is taken
11b = Overcurrent condition is not reported and no action is
taken
7.6.2.3 IC3 Control Register (address = 0x04)
IC3 control is shown in Figure 34 and described in Table 26.
Read/Write
Figure 34. IC3 Control Register
7
CLR_FLT
R/W-0b
38
6
5
LOCK
R/W-100b
4
3
OUT1_DIS
R/W-0b
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2
OUT2_DIS
R/W-0b
1
EN_IN1
R/W-0b
0
PH_IN2
R/W-0b
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Table 26. IC3 Control Register Field Descriptions
Bit
7
6-4
3
Field
Type
Default
Description
CLR_FLT
R/W
0b
Write a 1b to this bit to clear the fault bits. This bit is
automatically reset after a write.
LOCK
R/W
100b
Write 011b to this register to lock all register settings in the IC1
control register except to these bits and address 0x04, bit 7
(CLR_FLT)
Write 100b to this register to unlock all register settings in the
IC1 control register
OUT1_DIS
R/W
0b
Enabled only in the Independent PWM mode
0b = Half bridge 1 enabled
1b = Half bridge 1 disabled (Hi-Z)
2
OUT2_DIS
R/W
0b
Enabled only in the Independent PWM mode
0b = Half bridge 2 enabled
1b = Half bridge 2 disabled (Hi-Z)
1
EN_IN1
R/W
0b
EN/IN1 bit to control the outputs through SPI (when SPI_IN =
1b)
0
PH_IN2
R/W
0b
PH/IN2 bit to control the outputs through SPI (when SPI_IN =
1b)
7.6.2.4 IC4 Control Register (address = 0x05)
IC4 control is shown in Figure 35 and described in Table 27.
Read/Write
Figure 35. IC4 Control Register
7
RSVD
R/W-0b
6
EN_OLP
R/W-0b
5
OLP_DLY
R/W-0b
4
EN_OLA
R/W-0b
3
2
1
ITRIP_LVL
R/W-10b
0
DIS_ITRIP
R/W-00b
Table 27. IC4 Control Register Field Descriptions
Bit
Field
Type
Default
Description
7
RSVD
R/W
0b
Reserved
6
EN_OLP
R/W
0b
Write 1b to run open load diagnostic in standby mode. When
open load test is complete EN_OLP returns to 0b (status check)
5
OLP_DLY
R/W
0b
0b = Open load diagnostic delay is 300 µs
1b = Open load diagnostic delay is 1.2 ms
4
EN_OLA
R/W
0b
0b = Open load diagnostic in active mode is disabled
1b = Enable open load diagnostics in active mode
3-2
ITRIP_LVL
R/W
10b
00b = 4 A
01b = 5.4 A
10b = 6.5 A
11b = 7 A
1-0
DIS_ITRIP
R/W
00b
00b = Current regulation is enabled
01b = Current regulation is disabled for OUT1
10b = Current regulation is disabled for OUT2
11b = Current regulation is disabled for both OUT1 and OUT2
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The device is used mainly to drive a brushed DC motor. The on-board current regulation allows for limiting the
motor current during start-up and stall conditions. The design procedures in the Typical Application section
highlight how to use and configure the SPI version of the device.
8.2 Typical Application
Figure 36 shows the typical application schematic for the SPI version of the device.
1 …F
VCC
1
10 NŸ
2
DVDD
GND
nFAULT
CPL
SDO
CPH
SDI
VCP
3
5
6
7
8
9
10
11
12
1.5 NŸ
1.5 NŸ
SCLK
VM
nSCS
OUT1
EN/IN1
SPI
Device
OUT1
PH/IN2
SRC
DISABLE
SRC
IPROPI1
OUT2
nSLEEP
OUT2
IPROPI2
PPAD
4
VM
24
23
22
47 nF
21
20
1 …F
0.1 …F
VVM
>10 …F
19
18
17
16
BDC
15
14
VVM
13
0.1 …F
Figure 36. Typical Application Schematic
40
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Typical Application (continued)
8.2.1 Design Requirements
Table 28 lists the example input parameters for the system design.
Table 28. Design Parameters
DESIGN PARAMETERS
REFERENCE
EXAMPLE VALUE
Supply voltage
VM
13.5 V
Motor RMS current
IRMS
2.5 A
Motor winding inductance
LM
2.9 mH
Motor current trip point
ITRIP
6.5 A
PWM frequency
fPWM
10 kHz
RSENSE
1.5 kΩ
tSR
1 µs
Sense resistor
Rise and fall times (slew rate)
8.2.1.1 Motor Voltage
The motor voltage used depends on the ratings of the motor selected and the desired RPM. A higher voltage
spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage
also increases the rate of current change through the inductive motor windings.
8.2.1.2 Drive Current and Power Dissipation
The current path is through the high-side sourcing power driver, motor winding, and low-side sinking power
driver. The amount of current the device can drive depends on the power dissipation without going into thermal
shutdown. The amount of current that can be power dissipation losses in one source and sink power driver are
calculated in Equation 2.
PD = (IRMS)2 × (RDS(on)High-side + RDS(on)Low-side)
(2)
The IOUT current is equal to the average current drawn by the DC motor. At 25°C ambient temperature, the power
dissipation becomes (2.5 A)2 × (150 mΩ) = 0.94 W.
The temperature that the device reaches depends on the thermal resistance to the air and PCB. Soldering the
device PowerPAD to the PCB ground plane, with vias to the top and bottom board layers, is important to
dissipate heat into the PCB and reduce the device temperature. In the example used here, the device had an
effective thermal resistance RθJA of 27.8°C/W. The junction temperature TJ value becomes as shown in
Equation 3.
TJ = TA + (PD × RθJA) = 25°C + (0.94 W × 27.8°C/W) = 51°C
(3)
NOTE
The values of RDS(on) increases with temperature, so as the device heats, the power
dissipation increases. This fact must be taken into consideration when sizing the heatsink.
At start-up and fault conditions, the current flowing through the motor is much higher than normal running current;
these peak currents and their duration must also be considered. High PWM frequency also results in higher
switching losses. Typically, switching the inputs at 100 kHz compared to 10 kHz causes 20% more power loss in
heat.
Power dissipation in the device is dominated by the power dissipated of the internal MOSFET resistance. The
maximum amount of power that can be dissipated in the device is dependent on ambient temperature and
heatsinking.
Total power dissipation for the device is composed of three main components. These are the quiescent supply
current dissipation, the power MOSFET switching losses, and the power MOSFET RDS(ON) (conduction) losses.
While other factors may contribute additional power losses, these other items are typically insignificant compared
to the three main items.
PTOT = PVM + PSW + PD
(4)
PVM can be calculated from the nominal supply voltage (VM) and the supply current (IVM) in active mode.
PVM = VM × IVM = 13.5 V × 5 mA = 67.5 mW
(5)
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PSW can be calculated from the nominal supply voltage (VM), average output current (IRMS), switching frequency
(fPWM) and the device output rise and fall times (tSR) time specifications.
PSW = PSW_RISE + PSW_FALL = 0.17 W + 0.17 W = 0.34 W
PSW_RISE = 0.5 × VM × IRMS × tSR × fPWM = 0.5 × 13.5 V × 2.5 A × 1 µs × 10 kHz = 0.17 W
PSW_FALL = 0.5 × VM × IRMS × tSR × fPWM = 0.5 × 13.5 V × 2.5 A × 1 µs × 10 kHz = 0.17 W
(6)
(7)
(8)
Therefore, total power dissipation (PTOT) at 25°C ambient temperature becomes = PVM + PSW + PD = 67.5 mW +
0.34 W + 0.94 W = 1.35 W
PTOT makes the junction temperature (TJ) of the device to be
TJ = TA + (PTOT × RθJA) = 25°C + (1.35 W × 27.8°C/W) = 63°C
(9)
The power dissipation from power MOSFET switching losses and quiescent supply current dissipation results is
approximately 12°C rise in the junction temperature (different between Equation 9 and Equation 3). Care must be
taken when doing the PCB layout and heatsinking the motor driver device so that the thermal characteristics are
properly managed.
Trace 0.22 × 34.5mm
at 0.65mm pitch
A
PTH via at 2.54mm pitch
Drill 300u; plate 18µ
Array to fit the copper area
PTH via at 1.2mm pitch
Drill 300µ; plate 18µ
A
3.2mm
Copper (Cu)
Area
(cm2)
Dimension A
(mm)
2
17.9
4
23.9
8
32.2
16
44.0
32
60.6
49.23
74.2
8.2mm
Figure 37. PCB Model (4-Layer PCB Shown, 2-Layer PCB Has No Vias)
42
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30
6.1
Junction-to-Ambient
Thermal Resistance (qC/W)
Junction-to-Board
Characterization Parameter (qC/W)
1oz
2oz
29
28
27
26
25
24
23
22
21
20
6
5.95
5.9
5.85
5.8
5.75
0
10
20
30
Copper Area (cm2)
40
50
0
10
D007
Figure 38. 4-Layer PCB
Junction-to-Ambient Thermal Resistance vs Copper Area
20
30
Copper Area (cm2)
40
50
D008
Figure 39. 4-Layer PCB
Junction-to-Board Characterization Parameter vs Copper
Area
80
13
1oz
2oz
70
Junction-to-Board
Characterization Parameter (qC/W)
Junction-to-Ambient
Thermal Resistance (qC/W)
1oz
2oz
6.05
60
50
40
30
20
1oz
2oz
12
11
10
9
8
7
0
10
20
30
Copper Area (cm2)
40
50
0
D009
Figure 40. 2-Layer PCB (No Vias)
Junction-to-Ambient Thermal Resistance vs Copper Area
10
20
30
Copper Area (cm2)
40
50
D010
drv8
Figure 41. 2-Layer PCB (No Vias)
Junction-to-Board Characterization Parameter vs Copper
Area
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8.2.1.3 Sense Resistor
For optimal performance, the sense resistor must have the following features:
• Surface-mount device
• Low inductance
• Placed closely to the motor driver device
Use Equation 10 to calculate the power dissipation (PD) of the sense resistor.
PD = (I(RMS) / k)2 × R(SENSE)
(10)
In this example, for the RMS motor current is 2.5 A, the sense resistor of 1.5 kΩ dissipates approximately 7.5
mW of power. The power quickly increases with higher current levels. Resistors typically have a rated power
within some ambient temperature range, along with a derated power curve for high ambient temperatures. When
a PCB is shared with other components that generate heat, the system designer should add margin. Measuring
the actual sense resistor temperature in a final system is best.
8.2.2 Detailed Design Procedure
8.2.2.1 Thermal Considerations
The device has thermal shutdown (TSD) at 165°C (mininum). If the die temperature exceeds this TSD threshold,
the device will be disabled until the temperature drops below the temperature hysteresis level.
Any tendency of the device to enter TSD is an indication of either excessive power dissipation, insufficient
heatsinking, or too high of an ambient temperature.
8.2.2.2 Heatsinking
The PowerPAD package uses an exposed pad to remove heat from the device. For proper operation, this pad
must be thermally connected to copper on the PCB to dissipate heat. On a multi-layer PCB with a ground plane,
this connection can be accomplished by adding a number of vias to connect the thermal pad to the ground plane.
On PCBs without internal planes, a copper area can be added on either side of the PCB to dissipate heat. If the
copper area is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat
between top and bottom layers.
For details about how to design the PCB, refer to the PowerPAD™ Thermally Enhanced Package application
report, and the PowerPAD™ Made Easy application report, available at www.ti.com. In general, the more copper
area that can be provided, the more power can be dissipated.
44
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8.2.3 Application Curves
Figure 42. Overcurrent (OCP) Detection
Figure 43. Current Regulation (ITRIP)
Figure 44. ITRIP Across TOFF and Load Current
Figure 45. Motor Motion at Different Speeds
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9 Power Supply Recommendations
The device is designed to operate with an input voltage supply (VM) range from 4.5 V to 40 V. A 0.1-µF ceramic
capacitor rated for VM must be placed as close to the device as possible. Also, an appropriately sized bulk
capacitor must be placed on the VM pin.
9.1 Bulk Capacitance Sizing
Bulk capacitance sizing is an important factor in motor drive system design. It is beneficial to have more bulk
capacitance, while the disadvantages are increased cost and physical size.
The amount of local capacitance needed depends on a variety of factors including:
• The highest current required by the motor system.
• The capacitance of the power supply and the ability of the power supply to source current.
• The amount of parasitic inductance between the power supply and motor system.
• The acceptable voltage ripple.
• The type of motor used (brushed DC, brushless DC, and stepper).
• The motor braking method.
The inductance between the power supply and motor drive system limits the rate that current can change from
the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands
or dumps from the motor with a change in voltage. When sufficient bulk capacitance is used, the motor voltage
remains stable, and high current can be quickly supplied.
The data sheet provides a recommended value, but system-level testing is required to determine the appropriate
sized bulk capacitor.
Parasitic Wire
Inductance
Motor Drive System
Power Supply
VM
+
+
Motor Driver
±
GND
Local
Bulk Capacitor
IC Bypass
Capacitor
Figure 46. Example Setup of Motor Drive System With External Power Supply
The voltage rating for bulk capacitors should be higher than the operating voltage to provide a margin for cases
when the motor transfers energy to the supply.
46
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10 Layout
10.1 Layout Guidelines
Each VM pin must be bypassed to ground using low-ESR ceramic bypass capacitors with recommended values
of 0.1 μF rated for VM. These capacitors should be placed as close to the VM pins as possible with a thick trace
or ground plane connection to the device GND pin.
Additional bulk capacitance is required to bypass the high current path. This bulk capacitance should be placed
such that it minimizes the length of any high current paths. The connecting metal traces should be as wide as
possible, with numerous vias connecting PCB layers. These practices minimize inductance and allow the bulk
capacitor to deliver high current.
Place a low-ESR ceramic capacitor between the CPL and CPH pins. This capacitor should be 47 nF, rated for
VM, and be of type X5R or X7R. Additionally, place a low-ESR ceramic capacitor between the VCP and VM pins.
This capacitor should be 1 µF, rated for 16 V, and be of type X5R or X7R.
The current sense resistors should be placed as close as possible to the device pins to minimize trace
inductance between the device pin and resistors.
10.2 Layout Example
+
1 µF
0.1 µF
DVDD
1
24
GND
nFAULT
2
23
CPL
SDO
3
22
CPH
SDI
4
21
VCP
SCLK
5
20
VM
nSCS
6
19
OUT1
EN/IN1
7
18
OUT1
PH/EN2
8
17
SRC
DISABLE
9
16
SRC
IPROPI1
10
15
OUT2
nSLEEP
11
14
OUT2
IPROPI2
12
13
VM
47 nF
1 µF
0.1 µF
0.1 µF
Figure 47. Layout Example
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Calculating Motor Driver Power Dissipation application report
• Texas Instruments, Daisy Chain Implementation for Serial Peripheral Interface application report
• Texas Instruments, DRV8873x EVM User’s Guide
• Texas Instruments, DRV8873x EVM GUI User's Guide
• Texas Instruments, PowerPAD™ Thermally Enhanced Package application report
• Texas Instruments, PowerPAD™ Made Easy application report
• Texas Instruments, Understanding Motor Driver Current Ratings application report
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
48
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12.1 Package Option Addendum
12.1.1 Packaging Information
Orderable Device
(1)
(2)
(3)
(4)
(5)
(6)
Status
(1)
Package
Type
Package
Drawing
Pins
Package
Qty
Eco Plan
(2)
Lead/Ball
Finish (3)
MSL Peak Temp
(4)
Op Temp (°C)
Device Marking (5) (6)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
space
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest
availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the
requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified
lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used
between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by
weight in homogeneous material)
space
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the
finish value exceeds the maximum column width.
space
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
space
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device
space
Multiple Device markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief
on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third
parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for
release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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12.1.2 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
B0 W
Reel
Diameter
Cavity
A0
B0
K0
W
P1
A0
Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1
Q2
Q1
Q2
Q3
Q4
Q3
Q4
User Direction of Feed
Pocket Quadrants
Device
50
Package
Type
Package
Drawing
Pins
SPQ
Reel
Diameter
(mm)
Reel
Width W1
(mm)
A0
(mm)
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B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
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SLVSET1 – AUGUST 2018
TAPE AND REEL BOX DIMENSIONS
Width (mm)
L
W
Device
H
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
DRV8873HPWPR
ACTIVE
HTSSOP
PWP
24
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
8873H
DRV8873HPWPT
ACTIVE
HTSSOP
PWP
24
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
8873H
DRV8873SPWPR
ACTIVE
HTSSOP
PWP
24
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
8873S
DRV8873SPWPT
ACTIVE
HTSSOP
PWP
24
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
8873S
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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