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DRV8874
SLVSF66A – AUGUST 2019 – REVISED DECEMBER 2019
DRV8874 H-Bridge Motor Driver With Integrated Current Sense and Regulation
1 Features
3 Description
•
The DRV8874 is an integrated motor driver with Nchannel H-bridge, charge pump, current sensing and
proportional output, current regulation, and protection
circuitry. The charge pump improves efficiency by
supporting N-channel MOSFET half bridges and
100% duty cycle driving. The family of devices come
in pin-to-pin RDS(on) variants to support different loads
with minimal design changes.
•
•
•
•
•
•
•
•
•
2 Applications
•
•
•
•
•
•
•
Brushed DC motors
Major and small home appliances
Vacuum, humanoid, and toy robotics
Printers and scanners
Smart meters
ATMs, currency counters, and EPOS
Servo motors and actuators
An internal current mirror architecture on the IPROPI
pin implements current sensing and regulation. This
eliminates the need for a large power shunt resistor,
saving board area and reducing system cost. The
IPROPI current-sense output allows a microcontroller
to detect motor stall or changes in load conditions.
Using the external voltage reference pin, VREF,
these devices can regulate the motor current during
start-up and high-load events without interaction from
a microcontroller.
A low-power sleep mode achieves ultra-low quiescent
current draw by shutting down most of the internal
circuitry. Internal protection features include supply
undervoltage lockout, charge pump undervoltage,
output overcurrent, and device overtemperature.
Fault conditions are indicated on nFAULT.
View our full portfolio of brushed motor drivers on
ti.com.
Device Information
PART NUMBER
DRV8874
PACKAGE
(1)
BODY SIZE (NOM)
HTSSOP (16)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
xx
xxx
xxx
xx
Simplified Schematic
4.5 to 37 V
DRV887x
nSLEEP
x
Control Inputs
nFAULT
IPROPI
RIPROPI
•
•
N-channel H-bridge motor driver
– Drives one bidirectional brushed DC motor
– Two unidirectional brushed DC motors
– Other resistive and inductive loads
4.5-V to 37-V operating supply voltage range
Pin to pin RDS(on) variants
– DRV8874: 200-mΩ (High-Side + Low-Side)
– DRV8876: 700-mΩ (High-Side + Low-Side)
High output current capability
– DRV8874: 6-A Peak
– DRV8876: 3.5-A Peak
Integrated current sensing and regulation
Proportional current output (IPROPI)
Selectable current regulation (IMODE)
– Cycle-by-cycle or fixed off time
Selectable input control modes (PMODE)
– PH/EN and PWM H-bridge control modes
– Independent half-bridge control mode
Supports 1.8-V, 3.3-V, and 5-V logic inputs
Ultra low-power sleep mode
– VUVLO, nSLEEP = 5 V to active
1
ms
tSLEEP
Turnoff time
nSLEEP = 0 V to sleep mode
1
ms
VVCP
Charge pump regulator voltage
VCP with respect to VM, VVM = 24 V
fVCP
Charge pump switching frequency
3
5
V
400
kHz
LOGIC-LEVEL INPUTS (EN/IN1, PH/IN2, nSLEEP)
VIL
Input logic low voltage
VIH
Input logic high voltage
VVM < 5 V
0
0.7
VVM ≥ 5 V
0
0.8
1.5
5.5
200
VHYS
Input hysteresis
IIL
Input logic low current
VI = 0 V
IIH
Input logic high current
VI = 5 V
50
RPD
Input pulldown resistance
To GND
100
nSLEEP
V
mV
50
–5
V
mV
5
µA
75
µA
kΩ
TRI-LEVEL INPUTS (PMODE)
VTIL
Tri-level input logic low voltage
0
VTIZ
Tri-level input Hi-Z voltage
0.9
VTIH
Tri-level input logic high voltage
1.5
ITIL
Tri-level input logic low current
VI = 0 V
–50
ITIZ
Tri-level input Hi-Z current
VI = 1.1 V
–10
ITIH
Tri-level input logic high current
VI = 5 V
113
RTPD
Tri-level pulldown resistance
To GND
44
kΩ
RTPU
Tri-level pullup resistance
To internal 5 V
156
kΩ
1.1
0.65
V
1.2
V
5.5
–32
V
µA
10
µA
150
µA
QUAD-LEVEL INPUTS (IMODE)
VQI2
Quad-level input level 1
Voltage to set quad-level 1
0.45
V
RQI2
Quad-level input level 2
Resistance to GND to set quad-level 2
18.6
20
21.4
kΩ
RQI3
Quad-level input level 3
Resistance to GND to set quad-level 3
57.6
62
66.4
kΩ
VQI4
Quad-level input level 4
Voltage to set quad-level 4
RQPD
Quad-level pulldown resistance
To GND
RQPU
Quad-level pullup resistance
To internal 5 V
Copyright © 2019, Texas Instruments Incorporated
0
2.5
5.5
V
136
kΩ
68
kΩ
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SLVSF66A – AUGUST 2019 – REVISED DECEMBER 2019
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Electrical Characteristics (continued)
4.5 V ≤ VVM ≤ 37 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPEN-DRAIN OUTPUTS (nFAULT)
VOL
Output logic low voltage
IOD = 5 mA
IOZ
Output logic high current
VOD = 5 V
–2
0.3
V
2
µA
DRIVER OUTPUTS (OUT1, OUT2)
RDS(on)_HS
High-side MOSFET on resistance
VVM = 24 V, IO = 2 A, TJ = 25°C
100
120
mΩ
RDS(on)_LS
Low-side MOSFET on resistance
VVM = 24 V, IO = –2 A, TJ = 25°C
100
120
mΩ
VSD
Body diode forward voltage
ISD = 1 A
0.9
V
tRISE
Output rise time
VVM = 24 V, OUTx rising 10% to 90%
150
ns
tFALL
Output fall time
VVM = 24 V, OUTx falling 90% to 10%
150
ns
tPD
Input to output propagation delay
EN/IN1, PH/IN2 to OUTx, 200 Ω from
OUTx to GND
400
ns
tDEAD
Output dead time
Body diode conducting
100
ns
450
µA/A
CURRENT SENSE AND REGULATION (IPROPI, VREF)
AIPROPI
AERR
Current mirror scaling factor
(1)
Current mirror scaling error
IOUT < 0.4 A
5.5 V ≤ VVM ≤ 37 V
–30
30
0.4 A ≤ IOUT < 1 A
5.5 V ≤ VVM ≤ 37 V
–7.5
7.5
1 A ≤ IOUT < 2 A
5.5 V ≤ VVM ≤ 37 V
–6
6
2 A ≤ IOUT ≤ 4 A
5.5 V ≤ VVM ≤ 37 V
–5.5
5.5
mA
%
tOFF
Current regulation off time
25
µs
tDELAY
Current sense delay time
1.6
µs
tDEG
Current regulation deglitch time
0.6
µs
tBLK
Current regulation blanking time
1.1
µs
PROTECTION CIRCUITS
VUVLO
Supply undervoltage lockout (UVLO)
VUVLO_HYS
Supply UVLO hysteresis
tUVLO
Supply undervoltage deglitch time
VCPUV
Charge pump undervoltage lockout
IOCP
Overcurrent protection trip point
tOCP
Overcurrent protection deglitch time
tRETRY
Overcurrent protection retry time
TTSD
Thermal shutdown temperature
THYS
Thermal shutdown hysteresis
(1)
6
VVM rising
4.3
4.45
4.6
VVM falling
4.2
4.35
4.5
VCP with respect to VM, VVCP falling
6
V
100
mV
10
µs
2.25
V
10
A
3
µs
2
160
V
175
ms
190
20
°C
°C
At low currents, the IPROPI output has a fixed offset error with respect to the IOUT current through the low-side power MOSFETs.
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SLVSF66A – AUGUST 2019 – REVISED DECEMBER 2019
EN/IN1 or
PH/IN2
tFALL
tRISE
ttPDt
OUTx (V)
ttBLKt
ttOFFt
ITRIP
OUTx (A)
tDEG
VREF
IPROPI (V)
ttDELAYt
Figure 1. Timing Parameter Diagram
Copyright © 2019, Texas Instruments Incorporated
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1.4
2
1.2
1.75
IVMQ Supply Current (PA)
IVMQ Supply Current (PA)
6.6 Typical Characteristics
1
0.8
0.6
0.4
TJ = -40°C
TJ = 25°C
TJ = 125°C
TJ = 150°C
0.2
5
10
15
20
25
VM Supply Voltage (V)
30
35
0
20
40
60
80 100
Junction Temperature (°C)
120
140
160
74_I
Figure 3. Sleep Current (IVMQ) vs. Junction Temperature
3
3.025
3
IVM Supply Current (mA)
IVM Supply Current (mA)
-20
3.05
TJ = -40°C
TJ = 25°C
TJ = 125°C
TJ = 150°C
3.03
2.97
2.94
2.91
2.88
2.85
2.82
2.975
2.95
2.925
2.9
2.875
2.85
VVM = 4.5 V
VVM = 13.5 V
VVM = 24 V
VVM = 37 V
2.825
2.79
2.8
2.775
-40
2.76
0
5
10
15
20
25
VM Supply Voltage (V)
30
35
40
VVM = 4.5 V
VVM = 13.5 V
VVM = 24 V
VVM = 37 V
-20
0
20
40
60
80 100
Junction Temperature (°C)
120
140
160
0.14
0.135
0.13
0.125
0.12
0.115
0.11
0.105
0.1
0.095
0.09
0.085
0.08
0.075
0.07
-40
454
456
452
AIPROPI from OUT2 (PA/A)
456
458
452
450
448
IOUT = 0.3 A
IOUT = 0.4 A
IOUT = 1 A
IOUT = 2 A
IOUT = 4 A
444
442
440
438
-40
-20
0
20
40
60
80 100
Ambient Temperature (qC)
120
140
74_A
Figure 8. OUT1 Current Sense Error vs. Junction
Temperature
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-20
0
20
40
60
80 100
Junction Temperature (°C)
140
160
74_I
120
140
160
74_H
450
448
446
444
IOUT = 0.3 A
IOUT = 0.4 A
IOUT = 1 A
IOUT = 2 A
IOUT = 4 A
442
440
438
160
120
Figure 7. High-Side RDS(on) vs. Junction Temperature
460
454
20
40
60
80 100
Junction Temperature (°C)
VVM = 4.5 V
VVM = 13.5 V
VVM = 24 V
VVM = 37 V
74_L
Figure 6. Low-Side RDS(on) vs. Junction Temperature
446
0
Figure 5. Active Current (IVM) vs. Junction Temperature
RDS(on)_HS (:)
0.14
0.135
0.13
0.125
0.12
0.115
0.11
0.105
0.1
0.095
0.09
0.085
0.08
0.075
0.07
0.065
-40
-20
74_I
Figure 4. Active Current (IVM) vs. Supply Voltage (VVM)
RDS(on)_LS (:)
0.5
74_I
3.06
AIPROPI from OUT1 (PA/A)
1
0.75
0
-40
40
Figure 2. Sleep Current (IVMQ) vs. Supply Voltage (VVM)
8
1.25
0.25
0
0
1.5
VVM = 4.5 V
VVM = 13.5 V
VVM = 24 V
VVM = 37 V
436
-40
-20
0
20
40
60
80 100
Ambient Temperature (°C)
120
140
160
74_A
Figure 9. OUT2 Current Sense Error vs. Junction
Temperature
Copyright © 2019, Texas Instruments Incorporated
DRV8874
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SLVSF66A – AUGUST 2019 – REVISED DECEMBER 2019
7 Detailed Description
7.1 Overview
The DRV887x family of devices are brushed DC motor drivers that operate from 4.5 to 37-V supporting a wide
range of output load currents for various types of motors and loads. The devices integrate an H-bridge output
power stage that can be operated in different control modes set by the PMODE pin setting. This allows for driving
a single bidirectional brushed DC motor, two unidirectional brushed DC motors, or other output load
configurations. The devices integrate a charge pump regulator to support more efficient high-side N-channel
MOSFETs and 100% duty cycle operation. The devices operate from a single power supply input (VM) which can
be directly connected to a battery or DC voltage supply. The nSLEEP pin provides an ultra-low power mode to
minimize current draw during system inactivity.
The DRV887x family of devices also integrate current sense output using current mirrors on the low-side power
MOSFETs. The IPROPI pin sources a small current that is proportional to the current in the MOSFETs. This
current can be converted to a proportional voltage using an external resistor (RIPROPI). The integrated current
sensing allows the DRV887x devices to limit the output current with a fixed off-time PWM chopping scheme and
provide load information to the external controller to detect changes in load or stall conditions. The integrated
current sensing outperforms traditional external shunt resistor sensing by providing current information even
during the off-time slow decay recirculating period and removing the need for an external power shunt resistor.
The off-time PWM current regulation level can be configured during motor operation through the VREF pin to
limit the load current accordingly to the system demands.
A variety of integrated protection features protect the device in the case of a system fault. These include
undervoltage lockout (UVLO), charge pump undervoltage (CPUV), overcurrent protection (OCP), and
overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin.
7.2 Functional Block Diagram
VM
VM
0.1 …F
VCP
VM
Gate Driver
VVCP
VVCP
0.1 …F
VCP
Charge
Pump
CPH
0.022 …F
HS
OUT1
VDD
CPL
LS
VDD
Internal
Regulator
GND
ISEN1
Power
Digital
Core
nSLEEP
VM
Gate Driver
VVCP
EN/IN1
HS
PH/IN2
PMODE
IMODE
OUT2
VDD
Control
Inputs
LS
3-Level
PGND
4-Level
VVCC
ISEN2
VVCC
VREF
IPROPI
IPROPI
Clamp
RIPROPI
Copyright © 2019, Texas Instruments Incorporated
RPU
Fault Output
+
nFAULT
±
Current
Sense
ISEN1
ISEN2
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7.3 Feature Description
7.3.1 External Components
Table 1 lists the recommended external components for the device.
Table 1. Recommended External Components
COMPONENT
PIN 1
PIN 2
RECOMMENDED
CVM1
VM
GND
0.1-µF, low ESR ceramic capacitor, VM-rated.
CVM2
VM
GND
Bulk Capacitance, VM-rated.
CVCP
VCP
VM
X5R or X7R, 100-nF, 16-V ceramic capacitor
CFLY
CPH
CPL
X5R or X7R, 22-nF, VM-rated ceramic capacitor
RIMODE
IMODE
GND
See Current Regulation.
RPMODE
PMODE
GND
See Control Modes.
RnFAULT
VCC
nFAULT
Pullup resistor, IOD ≤ 5-mA
RIPROPI
IPROPI
GND
See Current Sensing.
7.3.2 Control Modes
The DRV887x family of devices provides three modes to support different control schemes with the EN/IN1 and
PH/IN2 pins. The control mode is selected through the PMODE pin with either logic low, logic high, or setting the
pin Hi-Z as shown in Table 2. The PMODE pin state is latched when the device is enabled through the nSLEEP
pin. The PMODE state can be changed by taking the nSLEEP pin logic low, waiting the tSLEEP time, changing the
PMODE pin input, and then enabling the device by taking the nSLEEP pin back logic high.
Table 2. PMODE Functions
PMODE STATE
CONTROL MODE
PMODE = Logic Low
PH/EN
PMODE = Logic High
PWM
PMODE = Hi-Z
Independent Half-Bridge
VM
VM
1 Reverse drive
1 Forward drive
22 Slow decay (brake)
2 Slow decay (brake)
1
OUT1
1
3 High-Z (coast)
OUT2
3 High-Z (coast)
OUT1
OUT2
2
2
3
3
Forward
Reverse
Figure 10. H-Bridge States
10
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The inputs can accept static or pulse-width modulated (PWM) voltage signals for either 100% or PWM drive
modes. The device input pins can be powered before VM is applied with no issues. By default, the EN/IN1 and
PH/IN2 pins have an internal pulldown resistor to ensure the outputs are Hi-Z if no inputs are present.
The sections below show the truth table for each control mode. Note that these tables do not take into account
the internal current regulation feature. Additionally, the DRV887x family of devices automatically handles the
dead-time generation when switching between the high-side and low-side MOSFET of a half-bridge.
Figure 10 describes the naming and configuration for the various H-bridge states.
7.3.2.1 PH/EN Control Mode (PMODE = Logic Low)
When the PMODE pin is logic low on power up, the device is latched into PH/EN mode. PH/EN mode allows for
the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is
shown in Table 3.
Table 3. PH/EN Control Mode
nSLEEP
EN
PH
OUT1
OUT2
DESCRIPTION
0
X
X
Hi-Z
Hi-Z
1
0
X
L
L
Brake, (Low-Side Slow Decay)
1
1
0
L
H
Reverse (OUT2 → OUT1)
1
1
1
H
L
Forward (OUT1 → OUT2)
Sleep, (H-Bridge Hi-Z)
7.3.2.2 PWM Control Mode (PMODE = Logic High)
When the PMODE pin is logic high on power up, the device is latched into PWM mode. PWM mode allows for
the H-bridge to enter the Hi-Z state without taking the nSLEEP pin logic low. The truth table for PWM mode is
shown in Table 4.
Table 4. PWM Control Mode
nSLEEP
IN1
IN2
OUT1
OUT2
DESCRIPTION
0
X
X
Hi-Z
Hi-Z
Sleep, (H-Bridge Hi-Z)
1
0
0
Hi-Z
Hi-Z
Coast, (H-Bridge Hi-Z)
1
0
1
L
H
Reverse (OUT2 → OUT1)
1
1
0
H
L
Forward (OUT1 → OUT2)
1
1
1
L
L
Brake, (Low-Side Slow Decay)
7.3.2.3 Independent Half-Bridge Control Mode (PMODE = Hi-Z)
When the PMODE pin is Hi-Z on power up, the device is latched into independent half-bridge control mode. This
mode allows for each half-bridge to be directly controlled in order to support high-side slow decay or driving two
independent loads. The truth table for independent half-bridge mode is shown in Table 5.
In independent half-bridge control mode, current sensing and feedback are still available, but the internal current
regulation is disabled since each half-bridge is operating independently. Additionally, if both low-side MOSFETs
are conducting current at the same time, the IPROPI scaled output will be the sum of the currents. See Current
Sense and Regulation for more information.
Table 5. Independent Half-Bridge Control Mode
nSLEEP
INx
OUTx
0
X
Hi-Z
1
0
L
OUTx Low-Side On
1
1
H
OUTx High-Side On
Copyright © 2019, Texas Instruments Incorporated
DESCRIPTION
Sleep, (H-Bridge Hi-Z)
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7.3.3 Current Sense and Regulation
The DRV887x family of devices integrate current sensing, regulation, and feedback. These features allow for the
device to sense the output current without an external sense resistor or sense circuitry reducing system size,
cost, and complexity. This also allows for the devices to limit the output current in the case of motor stall or high
torque events and give detailed feedback to the controller about the load current through a current proportional
output.
7.3.3.1 Current Sensing
The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power
MOSFETs in the H-bridge scaled by AIPROPI. The IPROPI output current can be calculated by Equation 1. The
ILSx in Equation 1 is only valid when the current flows from drain to source in the low-side MOSFET. If current
flows from source to drain, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake,
slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side
MOSFETs.
IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A)
(1)
The current is measured by an internal current mirror architecture that removes the needs for an external power
sense resistor. Additionally, the current mirror architecture allows for the motor winding current to be sensed in
both the drive and brake low-side slow-decay periods allowing for continuous current monitoring in typical
bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed
because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in
either drive or slow-decay modes and measuring the current before switching back to coast mode again. In the
case of independent PWM mode and both low-side MOSFETs are carrying current, the IPROPI output will be the
sum of the two low-side MOSFET currents.
The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a
proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load
current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter
(ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full
range of the controller ADC is utilized. Additionally, the DRV887x devices implement an internal IPROPI voltage
clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of
output overcurrent or unexpected high current events.
The corresponding IPROPI voltage to the output current can be calculated by Equation 2.
VIPROPI (V) = IPROPI (A) x RIPROPI (Ω)
(2)
OUT
Control
Inputs
VREF
+
ILOAD
LS
±
GND
IPROPI
Clamp
Integrated
Current Sense
MCU
ADC
IPROPI
+
VPROPI
±
RIPROPI
IPROPI
AIPROPI
Copyright © 2017, Texas Instruments Incorporated
Figure 11. Integrated Current Sensing
12
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The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the DRV887x internal current sensing
circuit. This time is the delay from the low-side MOSFET enable command to the IPROPI output being ready. If
the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side
MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output.
7.3.3.2 Current Regulation
The DRV887x family of devices integrate current regulation using either a fixed off-time or cycle-by-cycle PWM
current chopping scheme. The current chopping scheme is selectable through the IMODE quad-level input. This
allows the devices to limit the output current in case of motor stall, high torque, or other high current load events.
The IMODE level can be set by leaving the pin floating (Hi-Z), connecting the pin to GND, or connecting a
resistor between IMODE and GND. The IMODE pin state is latched when the device is enabled through the
nSLEEP pin. The IMODE state can be changed by taking the nSLEEP pin logic low, waiting the tSLEEP time,
changing the IMODE pin input, and then enabling the device by taking the nSLEEP pin back logic high. The
IMODE input is also used to select the device response to an overcurrent event. See more details in the
Protection Circuits section.
The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater
than GND (if current feedback is not required) or if current feedback is required, setting VVREF and RIPROPI such
that VIPROPI never reaches the VVREF threshold. In independent half-bridge control mode (PMODE = Hi-Z), the
internal current regulation is automatically disabled since the outputs are operating independently and the current
sense and regulation is shared between half-bridges.
Table 6. IMODE Functions
IMODE FUNCTION
IMODE STATE
Quad-Level 1
RIMODE = GND
nFAULT
Response
Current Chopping
Mode
Overcurrent
Response
Fixed Off-Time
Automatic Retry
Overcurrent Only
Quad-Level 2
RIMODE = 20 kΩ to GND
Cycle-By-Cycle
Automatic Retry
Current Chopping and
Overcurrent
Quad-Level 3
RIMODE = 62 kΩ to GND
Cycle-By-Cycle
Outputs Latched Off
Current Chopping and
Overcurrent
Quad-Level 4
RIMODE = Hi-Z
Fixed Off-Time
Outputs Latched Off
Overcurrent Only
The current chopping threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI
output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF
with an internal comparator.
ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω)
(3)
For example, if VVREF = 2.5 V, RIPROPI = 1500 Ω, and AIPROPI = 455 μA/A, then ITRIP will be approximately 3.66 A.
When the ITRIP threshold is exceeded, the outputs will enter a current chopping mode according to the IMODE
setting. The ITRIP comparator has both a blanking time (tBLK) and a deglitch time (tDEG). The internal blanking time
helps to prevent voltage and current transients during output switching from effecting the current regulation.
These transients may be caused by a capacitor inside the motor or on the connections to the motor terminals.
The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In
certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the
IPROPI pin, close to the DRV887x, will help filter the transients on IPROPI output so current regulation does not
prematurely trigger. The capacitor value can be adjusted as needed, however large capacitor values may slow
down the response time of the current regulation circuitry.
The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It
indicates the combined effect of offset error added to the IOUT current and gain error.
7.3.3.2.1 Fixed Off-Time Current Chopping
In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON)
for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs
unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of
brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs changes during the tOFF
time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs.
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The fixed off-time mode allows for a simple current chopping scheme without involvement from the external
controller. This is shown in Figure 12. Fixed off-time mode will support 100% duty cycle current regulation since
the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the
EN/IN1 or PH/IN2 pins to reset the outputs.
ITRIP
IOUT
VOUT
Control
Input
tOFF
tOFF
tOFF
Figure 12. Off-Time Current-Regulation
7.3.3.2.2 Cycle-By-Cycle Current Chopping
In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON)
after IOUT exceeds ITRIP until the next control input edge on the EN/IN1 or PH/IN2 pins. This allows for additional
control of the current chopping scheme by the external controller. This is shown in Figure 13. Cycle-by-cycle
mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the
outputs after the brake, low-side slow decay state has been entered.
ITRIP
IOUT
VOUT
Control
Input
Re-enable
Re-enable
Figure 13. Cycle-By-Cycle Current Regulation
In cycle-by-cycle mode, the device will also indicate whenever the H-bridge enters internal current chopping by
pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control
inputs or the load has reached the ITRIP threshold. This is shown in Figure 14. nFAULT will be released whenever
the next control input edge is received by the device and the outputs are reset.
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Control
Input
ITRIP
IOUT
Drive
Decay
Drive
Chop
Decay
Drive
VOUT
VIPROPI
nFAULT
Figure 14. Cycle-By-Cycle Current Regulation Where nFAULT Acts as Current Chopping Indicator
No device functionality is affected when the nFAULT pin is pulled low for the current chopping indicator. The
nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device
fault (outlined in the Protection Circuits section) from the current chopping indicator, the nFAULT pin can be
compared with the control inputs. The current chopping indicator can only assert when the control inputs are
commanding a forward or reverse drive state (Figure 10). If the nFAULT pin behavior deviates from the operation
shown in Figure 14 then one of the following situations has occurred:
• If a device fault has occurred, then the nFAULT pin pulls low to indicate a fault condition rather than current
chopping. Depending on the device fault, nFAULT may remain low even when the control inputs are
commanding the high-Z or slow-decay states.
• When the control inputs transition from drive to slow decay, the nFAULT pin will go high for tBLK then be
pulled low again if IOUT > ITRIP. This may be caused by a PWM frequency or duty cycle on the control inputs
with a off-time that is too short for the IOUT current to decay below the ITRIP threshold. Figure 15 shows an
example of this condition. The condition IOUT > ITRIP can be viewed on an oscilloscope as VIPROPI > VREF.
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Chan. 1 = EN
Chan. 2 = nFAULT
Chan. 3 = VREF
Chan. 4 = IPROPI
Figure 15. nFAULT Pin When VIPROPI > VVREF with PH/EN Mode and PWM Signal on EN Pin
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7.3.4 Protection Circuits
The DRV887x family of devices are fully protected against supply undervoltage, charge pump undervoltage,
output overcurrent, and device overtemperature events.
7.3.4.1 VM Supply Undervoltage Lockout (UVLO)
If at any time the supply voltage on the VM pin falls below the undervoltage lockout threshold voltage (VUVLO), all
MOSFETs in the H-bridge will be disabled and the nFAULT pin driven low. The charge pump is disabled in this
condition. Normal operation will resume when the undervoltage condition is removed and VM rises above the
VUVLO threshold.
7.3.4.2 VCP Charge Pump Undervoltage Lockout (CPUV)
If at any time the charge pump voltage on the VCP pin falls below the undervoltage lockout threshold voltage
(VCPUV), all MOSFETs in the H-bridge will be disabled and the nFAULT pin driven low. Normal operation will
resume when the undervoltage condition is removed and VCP rises above the VCPUV threshold.
7.3.4.3 OUTx Overcurrent Protection (OCP)
An analog current limit circuit on each MOSFET limits the peak current out of the device even in hard short
circuit events.
If the output current exceeds the overcurrent threshold, IOCP, for longer than tOCP, all MOSFETs in the H-bridge
will be disabled and the nFAULT pin driven low. The overcurrent response can be configured through the IMODE
pin as shown in Table 6.
In automatic retry mode, the MOSFETs will be disabled and nFAULT pin driven low for a duration of tRETRY. After
tRETRY, the MOSFETs are re-enabled according to the state of the EN/IN1 and PH/IN2 pins. If the overcurrent
condition is still present, the cycle repeats; otherwise normal device operation resumes.
In latched off mode, the MOSFETs will remain disabled and nFAULT pin driven low until the device is reset
through either the nSLEEP pin or by removing the VM power supply.
In Independent Half-Bridge Control Mode (PMODE = Hi-Z), the OCP behavior is slightly modified. If an
overcurrent event is detected, only the corresponding half-bridge will be disabled and the nFAULT pin driven low.
The other half-bridge will continue normal operation. This allows for the device to manage independent fault
events when driving independent loads. If an overcurrent event is detected in both half-bridges, both half-bridges
will be disabled and the nFAULT pin driven low. In automatic retry mode, both half-bridges share the same
overcurrent retry timer. If an overcurrent event occurs first in one half-bridge and then later in the secondary halfbridge, but before tRETRY has expired, the retry timer for the first half-bridge will be reset to tRETRY and both halfbridges will enable again after the retry timer expires.
7.3.4.4 Thermal Shutdown (TSD)
If the die temperature exceeds the overtemperature limit TTSD, all MOSFET in the H-bridge will be disabled and
the nFAULT pin driven low. Normal operation will resume when the overtemperature condition is removed and
the die temperature drops below the TTSD threshold.
7.3.4.5 Fault Condition Summary
Table 7. Fault Condition Summary
FAULT
REPORT
H-BRIDGE
RECOVERY
ITRIP Indicator
CBC Mode &
IOUT > ITRIP
nFAULT
Active
Low-Side Slow Decay
Control Input Edge
VM Undervoltage Lockout (UVLO)
VM < VUVLO
nFAULT
Disabled
VM > VUVLO
VCP < VCPUV
nFAULT
Disabled
VCP > VCPUV
VCP Undervoltage Lockout (CPUV)
Overcurrent (OCP)
Thermal Shutdown (TSD)
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CONDITION
IOUT > IOCP
nFAULT
Disabled
tRETRY or Reset
(Set by IMODE)
TJ > TTSD
nFAULT
Disabled
TJ < TTSD – THYS
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7.3.5 Pin Diagrams
7.3.5.1 Logic-Level Inputs
Figure 16 shows the input structure for the logic-level input pins EN/IN1, PH/IN2, and nSLEEP.
100 k
Figure 16. Logic-Level Input
7.3.5.2 Tri-Level Inputs
Figure 17 shows the input structure for the tri-level input pin PMODE.
5V
156 k
+
±
+
44 k
±
Figure 17. PMODE Tri-Level Input
7.3.5.3 Quad-Level Inputs
Figure 18 shows the input structure for the quad-level input pin IMODE.
+
5V
68 k
±
+
±
+
136 k
±
Figure 18. Quad-Level Input
7.4 Device Functional Modes
The DRV887x family of devices have several different modes of operation depending on the system inputs.
7.4.1 Active Mode
After the supply voltage on the VM pin has crossed the undervoltage threshold VUVLO, the nSLEEP pin is logic
high, and tWAKE has elapsed, the device enters its active mode. In this mode, the H-bridge, charge pump, and
internal logic are active and the device is ready to receive inputs. The input control mode (PMODE) and current
control modes (IMODE) will be latched when the device enters active mode.
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Device Functional Modes (continued)
7.4.2 Low-Power Sleep Mode
The DRV887x family of devices support a low power mode to reduce current consumption from the VM pin when
the driver is not active. This mode is entered by setting the nSLEEP pin logic low and waiting for tSLEEP to elapse.
In sleep mode, the H-bridge, charge pump, internal 5-V regulator, and internal logic are disabled. The device
relies on a weak pulldown to ensure all of the internal MOSFETs remain disabled. The device will not respond to
any inputs besides nSLEEP while in low-power sleep mode.
7.4.3 Fault Mode
The DRV887x family of devices enter a fault mode when a fault is encountered. This is utilized to protect the
device and the output load. The device behavior in the fault mode is described in Table 7 and depends on the
fault condition. The device will leave the fault mode and re-enter the active mode when the recovery condition is
met.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DRV887x family of devices can be used in a variety of applications that require either a half-bridge or Hbridge power stage configuration. Common application examples include brushed DC motors, solenoids, and
actuators. The device can also be utilized to drive many common passive loads such as LEDs, resistive
elements, relays, etc. The application examples below will highlight how to use the device in bidirectional current
control applications requiring an H-bridge driver and dual unidirectional current control applications requiring two
half-bridge drivers.
8.2 Typical Application
8.2.1 Primary Application
In the primary application example, the device is configured to drive a bidirectional current through an external
load (such as a brushed DC motor) using an H-bridge configuration. The H-bridge polarity and duty cycle are
controlled with a PWM and IO resource from the external controller to the EN/IN1 and PH/IN2 pins. The device is
configured for the PH/EN control mode by tying the PMODE pin to GND. The current limit threshold (ITRIP) is
generated with an external resistor divider from the control logic supply voltage (VCC). The device is configured
for the fixed off-time current regulation scheme by tying the IMODE pin to GND. The load current is monitored
with an ADC from the controller to detect the voltage across RIPROPI.
VCC
Controller
1
PWM
EN/IN1
DRV887x
16
PMODE
2
I/O
VCC
15
PH/IN2
GND
nSLEEP
CPL
3
I/O
10 k
14
4
I/O
13
nFAULT
VREF
5
ADC
VREF
Thermal
Pad
CPH
12
VM
11
IPROPI
VM
IMODE
OUT2
OUT1
PGND
7
10
8
VCC
0.1 …F
VCP
6
RIPROPI
0.022 …F
0.1 …F
CBulk
9
RREF1
VREF
RREF2
BDC
Figure 19. Typical Application Schematic
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Typical Application (continued)
8.2.1.1 Design Requirements
Table 8. Design Parameters
REFERENCE
DESIGN PARAMETER
EXAMPLE VALUE
VM
Motor and driver supply voltage
24 V
3.3 V
VCC
Controller supply voltage
IRMS
Output RMS current
0.5 A
fPWM
Switching frequency
20 kHz
ITRIP
Current regulation trip point
1A
AIPROPI
Current sense scaling factor
455 µA/A
RIPROPI
IPROPI external resistor
5.5 kΩ
2.5 V
VREF
Current regulation reference voltage
VADC
Controller ADC reference voltage
2.5 V
RREF1
VREF external resistor
16 kΩ
RREF2
VREF external resistor
50 kΩ
TA
PCB ambient temperature
–20 to 85 °C
TJ
Device max junction temperature
150 °C
RθJA
Device junction to ambient thermal resistance
35 °C/W
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Current Sense and Regulation
The DRV887x family of devices provide integrated regulation and sensing out the output current.
The current sense feedback is configured by scaling the RIPROPI resistor to properly sense the scaled down
output current from IPROPI within the dynamic voltage range of the controller ADC. An example of this is shown.
RIPROPI
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