DRV8935
SLOSE62A – JANUARY 2021 – REVISED MAY 2022
DRV8935 Quad Half-Bridge Driver With Integrated Current Sense
•
•
1 Features
•
•
•
•
•
•
Quad Half-bridge driver
– Can drive up to Four Solenoid Loads, Two DC
Motors, One Stepper Motor, or Other Loads
Integrated current sensing and regulation
4.5-V to 33-V Operating supply voltage range
Low RDS(ON): 330 mΩ HS + LS at 24 V, 25°C
2.5-A Maximum Drive Current at 24 V, 25°C
Pin to pin compatible with – DRV8932: 33-V, 900 mΩ HS + LS
– DRV8955: 48-V, 330 mΩ HS + LS
•
•
•
•
•
– Small package and footprint
Configurable Off-Time PWM Chopping
– 7, 16, 24 or 32 μs
Supports 1.8-V, 3.3-V, 5.0-V logic inputs
Low-current sleep mode (2 µA)
Spread spectrum clocking for low electromagnetic
interference (EMI)
Protection features
– VM undervoltage lockout (UVLO)
– Charge pump undervoltage (CPUV)
– Overcurrent protection (OCP)
– Thermal shutdown (OTSD)
– Fault condition output (nFAULT)]
2 Applications
•
•
•
•
•
Refrigerator Damper and Ice Maker
Textile Machines
Office and Home Automation
Factory Automation and Robotics
Washers, Dryers and Dishwashers
Gaming Machines
General Purpose Solenoid Loads
3 Description
The DRV8935 provides four half-bridge drivers for
industrial applications. The device can be used for
driving up to four solenoid loads, two DC motors, one
Stepper motor, or other loads. The output stage for
each channel consists of N-channel power MOSFETs
configured in a half bridge. A simple PWM interface
allows easy interface with the controller.
The DRV8935 operates off a single power supply and
supports a wide input supply range from 4.5 V to 33 V.
The DRV8935 can supply up to 2.5-A peak or 1.75-A
RMS output current per channel (dependent on PCB
design).
A low-power sleep mode is provided to achieve a
low quiescent current draw by shutting down much
of the internal circuitry. Internal protection functions
are provided for undervoltage-lockout, overcurrent
protection on each FET, short circuit protection, and
overtemperature. Fault conditions are indicated by the
nFAULT pin.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
DRV8935PPWPR
HTSSOP (28)
9.7mm x 4.4mm
DRV8935PRGER
VQFN (24)
4.0mm x 4.0mm
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
DRV8935 Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRV8935
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Functions.................................................................... 4
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings........................................ 6
6.2 ESD Ratings............................................................... 6
6.3 Recommended Operating Conditions.........................7
6.4 Thermal Information....................................................7
6.5 Electrical Characteristics.............................................8
6.6 Typical Characteristics................................................ 9
7 Detailed Description......................................................12
7.1 Overview................................................................... 12
7.2 Functional Block Diagrams....................................... 13
7.3 Feature Description...................................................14
7.4 Device Functional Modes..........................................21
8 Application and Implementation.................................. 23
8.1 Application Information............................................. 23
8.2 Typical Application.................................................... 23
9 Power Supply Recommendations................................26
9.1 Bulk Capacitance...................................................... 26
10 Layout...........................................................................27
10.1 Layout Guidelines................................................... 27
10.2 Layout Example...................................................... 27
11 Device and Documentation Support..........................29
11.1 Documentation Support.......................................... 29
11.2 Receiving Notification of Documentation Updates.. 29
11.3 Community Resources............................................29
11.4 Trademarks............................................................. 29
12 Mechanical, Packaging, and Orderable
Information.................................................................... 30
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (January 2021) to Revision A (May 2022)
Page
• Updated HTSSOP and QFN layout example....................................................................................................27
• Updated Related Documentation section......................................................................................................... 29
2
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5 Pin Configuration and Functions
Figure 5-1. PWP PowerPAD™ Package 28-Pin HTSSOP Top View DRV8935
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Figure 5-2. RGE Package 24-Pin VQFN with Exposed Thermal PAD Top View DRV8935
Pin Functions
PIN
NAME
DESCRIPTION
RGE
IN1
25
20
I
PWM input. Logic controls the state of Half-bridge 1; internal pulldown.
IN2
24
19
I
PWM input. Logic controls the state of Half-bridge 2; internal pulldown.
IN3
23
18
I
PWM input. Logic controls the state of Half-bridge 3; internal pulldown.
IN4
22
17
I
PWM input. Logic controls the state of Half-bridge 4; internal pulldown.
OUT1
4, 5
3
O
Output of Half-bridge 1.
OUT2
6, 7
4
O
Output of Half-bridge 2.
OUT3
10, 11
6
O
Output of Half-bridge 3.
OUT4
8, 9
5
O
Output of Half-bridge 4.
VREF12
18
13
I
Reference voltage input pin. Controls the current level for Half-bridges 1
and 2.
VREF34
17
12
I
Reference voltage input pin. Controls the current level for Half-bridges 3
and 4.
-
No Connect.
NC
4
TYPE
PWP
20, 21
15, 16
CPH
28
23
CPL
27
22
GND
14
TOFF
PWR
Charge pump switching node. Connect a X7R, 0.022-μF, VM-rated ceramic
capacitor from CPH to CPL.
9
PWR
Device ground. Connect to system ground.
19
14
I
DVDD
15
10
PWR
Logic supply voltage. Connect a X7R, 0.47-μF to 1-μF, 6.3-V or 10-V rated
ceramic capacitor to GND.
VCP
1
24
O
Charge pump output. Connect a X7R, 0.22-μF, 16-V ceramic capacitor to
VM.
VM
2, 13
1, 8
PWR
Power supply. Connect to supply voltage and bypass to PGND with two
0.01-μF ceramic capacitors (one for each pin) plus a bulk capacitor rated
for VM.
Sets the off-time during current chopping; quad-level pin.
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PIN
NAME
TYPE
DESCRIPTION
PWP
RGE
3, 12
2, 7
PWR
Common power ground pin for all the half-bridges. Connect to system
ground.
nFAULT
16
11
O
Fault indication. Pulled logic low with fault condition; open-drain output
requires an external pullup resistor.
nSLEEP
26
21
I
Sleep mode input. Logic high to enable device; logic low to enter low-power
sleep mode; internal pulldown resistor.
-
-
-
Thermal pad. Connect to system ground.
PGND
PAD
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range referenced with respect to GND (unless otherwise noted)
MIN
MAX
UNIT
Power supply voltage (VM)
–0.3
35
V
Charge pump voltage (VCP, CPH)
–0.3
VVM + 7
V
Charge pump negative switching pin (CPL)
–0.3
VVM
V
nSLEEP pin voltage (nSLEEP)
–0.3
VVM
V
Internal regulator voltage (DVDD)
–0.3
5.75
V
Control pin voltage (IN1, IN2, IN3, IN4, nFAULT, TOFF)
–0.3
5.75
V
0
10
mA
Open drain output current (nFAULT)
Reference input pin voltage (VREF12, VREF34)
–0.3
5.75
V
Continuous phase node pin voltage (OUT1, OUT2, OUT3, OUT4)
–1
VVM + 1
V
Transient 100 ns phase node pin voltage (OUT1, OUT2, OUT3, OUT4)
–3
VVM + 3
V
Peak drive current (OUT1, OUT2, OUT3, OUT4)
Internally Limited
A
Operating ambient temperature, TA
–40
125
°C
Operating junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These are stress ratings only, which do not imply functional operation of the device at these or any other
conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximumrated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
6
Electrostatic
discharge
Charged-device model (CDM), per JEDEC specification JESD22C101
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UNIT
±2000
Corner pins for PWP (1,
14, 15, and 28)
±750
Other pins
±500
V
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
4.5
33
V
0
5.5
V
VVM
Supply voltage range for normal (DC) operation
VI
Logic level input voltage
VREF
Reference rms voltage range (VREF)
ƒPWM
Applied PWM signal (IN1, IN2, IN3, IN4)
IFS
Peak output current
0
2.5
A
TA
Operating ambient temperature
–40
125
°C
TJ
Operating junction temperature
–40
150
°C
0.05
3.3
V
0
100
kHz
6.4 Thermal Information
PWP (HTSSOP)
RGE (VQFN)
28 PINS
24 PINS
31.0
40.7
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
25.2
31.8
°C/W
RθJB
Junction-to-board thermal resistance
10.8
17.7
°C/W
ψJT
Junction-to-top characterization parameter
0.4
0.6
°C/W
ψJB
Junction-to-board characterization parameter
10.7
17.7
°C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance
3.3
4.7
°C/W
THERMAL METRIC
RθJA
Junction-to-ambient thermal resistance
UNIT
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6.5 Electrical Characteristics
Typical values are at TA = 25°C and VVM = 24 V. All limits are over recommended operating conditions, unless otherwise
noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLIES (VM, DVDD)
IVM
VM operating supply current
nSLEEP = 1, No load
5
6.5
mA
IVMQ
VM sleep mode supply current
nSLEEP = 0
2
4
μA
tSLEEP
Sleep time
nSLEEP = 0 to sleep-mode
120
tRESET
nSLEEP reset pulse
nSLEEP low to clear fault
20
tWAKE
Wake-up time
nSLEEP = 1 to output transition
tON
Turn-on time
VM > UVLO to output transition
VDVDD
Internal regulator voltage
μs
40
μs
0.8
1.2
ms
0.8
1.2
ms
5.25
V
No external load, 6 V < VVM < 33 V
4.75
5
No external load, VVM = 4.5 V
4.2
4.35
V
VVM + 5
V
360
kHz
CHARGE PUMP (VCP, CPH, CPL)
VVCP
VCP operating voltage
6 V < VVM < 33 V
f(VCP)
Charge pump switching
frequency
VVM > UVLO; nSLEEP = 1
LOGIC-LEVEL INPUTS (IN1, IN2, IN3, IN4, nSLEEP)
VIL
Input logic-low voltage
0
0.6
V
VIH
Input logic-high voltage
1.5
5.5
V
VHYS
Input logic hysteresis
IIL
Input logic-low current
VIN = 0 V
IIH
Input logic-high current
VIN = 5 V
150
–1
mV
1
μA
100
μA
QUAD-LEVEL INPUTS (TOFF)
VI1
Input logic-low voltage
VI2
Tied to GND
0
0.6
V
330kΩ ± 5% to GND
1
1.25
1.4
V
2
2.2
V
5.5
V
VI3
Input Hi-Z voltage
Hi-Z (>500kΩ to GND)
1.8
VI4
Input logic-high voltage
Tied to DVDD
2.7
IO
Output pull-up current
10
μA
CONTROL OUTPUTS (nFAULT)
VOL
Output logic-low voltage
IOH
Output logic-high leakage
IO = 5 mA
–1
0.5
V
1
μA
MOTOR DRIVER OUTPUTS (OUT1, OUT2, OUT3, OUT4)
RDS(ONH)
RDS(ONL)
High-side FET on resistance
Low-side FET on resistance
TJ = 25 °C, IO = -1 A
165
200
mΩ
TJ = 125 °C, IO = -1 A
250
300
mΩ
TJ = 150 °C, IO = -1 A
280
350
mΩ
TJ = 25 °C, IO = 1 A
165
200
mΩ
TJ = 125 °C, IO = 1 A
250
300
mΩ
TJ = 150 °C, IO = 1 A
280
350
mΩ
1.32
1.386
V/A
8.25
μA
CURRENT REGULATION (VREF)
KV
Transimpedance gain
VREF = 3.3V
IVREF
VREF Leakage Current
VREF = 3.3V
tOFF
8
PWM off-time
1.254
TOFF = 0
7
TOFF = 1
16
TOFF = Hi-Z
24
TOFF = 330 kΩ to GND
32
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Typical values are at TA = 25°C and VVM = 24 V. All limits are over recommended operating conditions, unless otherwise
noted.
PARAMETER
ΔITRIP
Current trip accuracy
TEST CONDITIONS
MIN
TYP
MAX
IO = 2.5 A, 10% to 20% current setting
-8
12
IO = 2.5 A, 20% to 40% current setting
-7
7
IO = 2.5 A, 40% to 100% current setting
-5
5
VM falling, UVLO falling
4.1
4.25
4.35
VM rising, UVLO rising
4.2
4.35
4.45
UNIT
%
PROTECTION CIRCUITS
VUVLO
VM UVLO lockout
VUVLO,HYS
Undervoltage hysteresis
Rising to falling threshold
VCPUV
Charge pump undervoltage
VCP falling
IOCP
Overcurrent protection
Current through any FET
tOCP
Overcurrent deglitch time
TOTSD
Thermal shutdown
Die temperature TJ
THYS_OTSD
Thermal shutdown hysteresis
Die temperature TJ
100
mV
VVM + 2
V
4
A
1.8
150
V
165
20
μs
180
°C
°C
6.6 Typical Characteristics
Figure 6-1. Sleep Current over Supply Voltage
Figure 6-2. Sleep Current over Temperature
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Figure 6-3. Operating Current over Supply Voltage
Figure 6-4. Operating Current over Temperature
Figure 6-5. Low-Side RDS(ON) over Supply Voltage
Figure 6-6. Low-Side RDS(ON) over Temperature
10
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Figure 6-7. High-Side RDS(ON) over Supply Voltage
Figure 6-8. High-Side RDS(ON) over Temperature
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7 Detailed Description
7.1 Overview
The DRV8935 integrates four 2.5-A half-H bridges for industrial applications. The device supports a wide 4.5-V
to 33-V supply voltage and can drive up to four solenoid loads.
A simple PWM interface option allows easy interfacing to the outputs. The trip point for current regulation is
controlled by the value of the VREF pin voltage. The PWM off-time, tOFF, can be adjusted to 7, 16, 24, or 32 μs.
A low-power sleep mode is included which lets the system save power when not driving the load.
A variety of integrated protection features protect the device in the case of a system fault. These
include undervoltage lockout (UVLO), charge pump undervoltage (CPUV), overcurrent protection (OCP), and
overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin.
12
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7.2 Functional Block Diagrams
Figure 7-1. DRV8935 Block Diagram
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7.3 Feature Description
The following table shows the recommended values of the external components for the driver.
Figure 7-2. Resistor divider connected to the VREF pins
Table 7-1. External Components
COMPONENT
PIN 1
PIN 2
RECOMMENDED
CVM1
VM
PGND
Two X7R, 0.01-µF, VM-rated ceramic capacitors
CVM2
VM
PGND
Bulk, VM-rated capacitor
CVCP
VCP
VM
X7R, 0.22-µF, 16-V ceramic capacitor
CSW
CPH
CPL
X7R, 0.022-µF, VM-rated ceramic capacitor
X7R, 0.47-µF to 1-µF, 6.3-V or 10-V rated ceramic capacitor
CDVDD
DVDD
GND
RnFAULT
VCC
nFAULT
RREF1
VREF12
VCC
RREF2 (Optional)
VREF12
GND
RREF3
VREF34
VCC
RREF4 (Optional)
VREF34
GND
>4.7-kΩ resistor
Resistor to limit chopping current. It is recommended that the value of parallel
combination of RREF1 and RREF2 should be less than 50-kΩ.
Resistor to limit chopping current. It is recommended that the value of parallel
combination of RREF3 and RREF4 should be less than 50-kΩ.
7.3.1 Bridge Control and Current Regulation
The INx input pins directly control the state (high or low) of the OUTx outputs. The truth table is shown below.
Table 7-2. DRV8935 Control Interface
nSLEEP
INx
OUTx
DESCRIPTION
0
X
Hi-Z
1
0
L
Sleep mode; Half-bridge disabled (Hi-Z)
OUTx Low-side ON
1
1
H
OUTx High-side ON
When an output load is connected to the VM supply, the load current can be regulated to the ITRIP level. The
ITRIP current level for OUT1 and OUT2 outputs is controlled by the VREF12 pin, and the ITRIP level for OUT3
and OUT4 outputs is controlled by the VREF34 pin. The ITRIP current (ITRIP) can be calculated as ITRIP (A) =
VREF (V) / 1.32 (V/A). The VREF voltage can be programmed by connecting resistor dividers from DVDD pin to
ground. Both VREF pins can be tied together to program the same ITRIP current for all four output channels.
The DRV8935 can simultaneously drive four resistive or inductive loads connected to VM supply. With INx = 0,
the low side FET is turned ON till the current increases and hits the ITRIP level. Once the load current equals
ITRIP, the low-side FET is turned OFF and the high-side FET is turned on for a period of off-time determined by
the TOFF pin. After the off-time expires, the low-side FET is again turned ON and the cycle repeats. The OFF
time settings can be changed on the fly. After a OFF time setting change, the new OFF time is applied after a 10
µs de-glitch time.
For resistive loads connected to VM, if the ITRIP is higher than the (VM / RLOAD), the load current is regulated
at VM / RLOAD level while INx = 0. For inductive loads connected to VM, it should be ensured that the current
decays enough every cycle to prevent runaway and triggering overcurrent protection. The different scenarios are
shown below 14
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Figure 7-3. Resistive Load Connected to VM, Cycle-by-cycle control, ITRIP is higher than VM/RLOAD.
Figure 7-4. Inductive Load Connected to VM, fixed off-time current chopping
In this scenario, with INx = 0, the high-side MOSFET is turned on for tOFF duration after IOUT exceeds ITRIP.
After tOFF, the low side MOSFET is again turned on till IOUT exceeds ITRIP again. The fixed off-time mode
allows for a simple current chopping scheme without involvement from the external controller. Fixed off-time
mode will support 100% duty cycle current regulation.
Another way of controlling the load current is the cycle-by-cycle control mode, where PWM pulse width of the
INx input pins are controlled. This allows for additional control of the current chopping scheme by the external
controller. For loads connected to VM, when INx = 0, the current through the load builds up; and when INx =
1, the current through the load decays. By properly choosing the duty cycle of the INx pulse, current can be
regulated to a target value. Various such scenarios are shown below -
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Figure 7-5. Inductive Load Connected to VM, Cycle-by-cycle control
This scenarion requires INx pin duty cycle adjustment to ensure that the current does not run away.
Figure 7-6. Inductive Load Connected to VM, Cycle-by-cycle control, T has to be less than TOFF of the
DRV8935.
Similarly, current through loads connected to ground can be controlled by controlling the INx pin pulse width INx = 1 builds up the current, and INx = 0 decays the current. Two such scenarios are shown below -
Figure 7-7. Inductive Load Connected to ground, Cycle-by-cycle control
16
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This scenario requires INx pin duty cycle adjustment to ensure that the current does not run away.
Figure 7-8. Resistive Load Connected to ground, Cycle-by-cycle control
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7.3.2 Decay Modes
7.3.2.1 Blanking time
After the current is enabled in the low-side FET, the current sense comparator is ignored for a period of time
(tBLANK) before enabling the current-sense circuitry. The blanking time also sets the minimum drive time of the
PWM. The blanking time is approximately 1 µs.
7.3.3 Charge Pump
A charge pump is integrated to supply a high-side N-channel MOSFET gate-drive voltage. The charge pump
requires a capacitor between the VM and VCP pins to act as the storage capacitor. Additionally a ceramic
capacitor is required between the CPH and CPL pins to act as the flying capacitor.
Figure 7-9. Charge Pump Block Diagram
18
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7.3.4 Linear Voltage Regulators
A linear voltage regulator is integrated in the device. The DVDD regulator can be used to provide a reference
voltage. DVDD can supply a maximum of 2 mA load. For proper operation, bypass the DVDD pin to GND using
a ceramic capacitor.
The DVDD output is nominally 5-V. When the DVDD LDO current load exceeds 2 mA, the output voltage drops
significantly.
Figure 7-10. Linear Voltage Regulator Block Diagram
If TOFF must be tied permanently high, tying it to the DVDD pin instead of an external regulator is preferred.
This method saves power when the VM pin is not applied or in sleep mode: the DVDD regulator is disabled
and current does not flow through the input pulldown resistors. For reference, logic level inputs have a typical
pulldown of 200 kΩ.
The nSLEEP pin cannot be tied to DVDD, else the device will never exit sleep mode.
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7.3.5 Logic and Quad-Level Pin Diagrams
Figure 7-11 gives the input structure for logic-level pins IN1, IN2, IN3, IN4 and nSLEEP:
Figure 7-11. Logic-level Input Pin Diagram
Quad-level logic pin TOFF has the following structure as shown in Figure 7-12.
Figure 7-12. Quad-Level Input Pin Diagram
7.3.6 nFAULT Pin
The nFAULT pin has an open-drain output and should be pulled up to a 5-V, 3.3-V or 1.8-V supply. When a
fault is detected, the nFAULT pin will be logic low. nFAULT pin will be high after power-up. For a 5-V pullup, the
nFAULT pin can be tied to the DVDD pin with a resistor. For a 3.3-V or 1.8-V pullup, an external supply must be
used.
Output
nFAULT
Figure 7-13. nFAULT Pin
7.3.7 Protection Circuits
The devices are fully protected against supply undervoltage, charge pump undervoltage, output overcurrent, and
device overtemperature events.
7.3.7.1 VM Undervoltage Lockout (UVLO)
If at any time the voltage on the VM pin falls below the UVLO-threshold voltage for the voltage supply, all
the outputs are disabled, and the nFAULT pin is driven low. The charge pump is disabled in this condition.
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Normal operation resumes (motor-driver operation and nFAULT released) when the VM undervoltage condition
is removed.
7.3.7.2 VCP Undervoltage Lockout (CPUV)
If at any time the voltage on the VCP pin falls below the CPUV voltage, all the outputs are disabled, and the
nFAULT pin is driven low. The charge pump remains active during this condition. Normal operation resumes
(motor-driver operation and nFAULT released) when the VCP undervoltage condition is removed.
7.3.7.3 Overcurrent Protection (OCP)
An analog current-limit circuit on each FET limits the current through the FET by removing the gate drive. If this
current limit persists for longer than the tOCP time, the half-bridge in which OCP is detected is disabled and the
nFAULT pin is driven low. The charge pump remains active during this condition. Once the OCP condition is
removed, normal operation resumes after applying an nSLEEP reset pulse or a power cycling.
7.3.7.4 Thermal Shutdown (OTSD)
If the die temperature exceeds the thermal shutdown limit (TOTSD) all MOSFETs in the H-bridge are disabled,
and the nFAULT pin is driven low. After the junction temperature falls below the overtemperature threshold limit
minus the hysteresis (TOTSD – THYS_OTSD), normal operation resumes after applying an nSLEEP reset pulse or a
power cycling.
7.3.7.5 Fault Condition Summary
Table 7-3. Fault Condition Summary
FAULT
CONDITION
ERROR
REPORT
HALFBRIDGE
CHARGE
PUMP
LOGIC
RECOVERY
VM undervoltage
(UVLO)
VM < VUVLO
nFAULT
All Disabled
Disabled
Reset
(VDVDD < 3.9
V)
Automatic: VM > VUVLO
VCP undervoltage
(CPUV)
VCP < VCPUV
nFAULT
All Disabled
Operating
Operating
VCP > VCPUV
Overcurrent (OCP)
IOUT > IOCP
nFAULT
Half-bridge
with OCP is
Disabled
Operating
Operating
Latched
Thermal Shutdown
(OTSD)
TJ > TTSD
nFAULT
All Disabled
Disabled
Operating
Latched
7.4 Device Functional Modes
7.4.1 Sleep Mode (nSLEEP = 0)
The state of the device is managed by the nSLEEP pin. When the nSLEEP pin is low, the device enters a
low-power sleep mode. In sleep mode, all the internal MOSFETs are disabled and the charge pump is disabled.
The tSLEEP time must elapse after a falling edge on the nSLEEP pin before the device enters sleep mode. The
device is brought out of sleep automatically if the nSLEEP pin is brought high. The tWAKE time must elapse
before the device is ready for inputs.
7.4.2 Operating Mode (nSLEEP = 1)
When the nSLEEP pin is high, and VM > UVLO, the device enters the active mode. The tWAKE time must elapse
before the device is ready for inputs.
7.4.3 nSLEEP Reset Pulse
A fault can be cleared through a quick nSLEEP pulse. This pulse width must be greater than 20 µs and shorter
than 40 µs. If nSLEEP is low for longer than 40 µs but less than 120 µs, the faults are cleared and the device
may or may not shutdown, as shown in the timing diagram. This reset pulse does not affect the status of the
charge pump or other functional blocks.
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Figure 7-14. nSLEEP Reset Pulse
7.4.4 Functional Modes Summary
The following table lists a summary of the functional modes.
Table 7-4. Functional Modes Summary
CONDITION
CONFIGURATI
ON
HALF-BRIDGE
DVDD Regulator CHARGE PUMP
Logic
Sleep mode
4.5 V < VM < 33 V
nSLEEP pin = 0
Disabled
Disbaled
Disabled
Disabled
Operating
4.5 V < VM < 33 V
nSLEEP pin = 1
Operating
Operating
Operating
Operating
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
The DRV8935 is a four channel half-bridge driver with protection features. The device can be used to drive one
stepper motor, multiple brushed DC motors, or up to four solenoid loads.
8.2 Typical Application
The following design procedure can be used to configure the DRV8935. In this application, the device will be
used to drive four solenoid loads.
Figure 8-1. Typical Application Schematic
8.2.1 Design Requirements
Table 8-1 lists the design input parameters for a typical application.
Table 8-1. Design Parameters
DESIGN PARAMETER
REFERENCE
EXAMPLE VALUE
Supply Voltage Range
VM
19 - 29V
Current per Channel
IOUT
1.5 A
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Table 8-1. Design Parameters (continued)
DESIGN PARAMETER
REFERENCE
PWM Frequency
EXAMPLE VALUE
fPWM
40 kHz
8.2.2 Detailed Design Procedure
8.2.2.1 Current Regulation
When an output load is connected to the VM supply, the load current can be regulated to the ITRIP level. The
ITRIP current level for OUT1 and OUT2 outputs is controlled by the VREF12 pin, and the ITRIP level for OUT3
and OUT4 outputs is controlled by the VREF34 pin. The ITRIP current (ITRIP) can be calculated as ITRIP (A) =
VREF (V) / 1.32 (V/A). The VREF voltage can be programmed by connecting resistor dividers from DVDD pin to
ground. Both VREF pins can be tied together to program the same ITRIP current for all four output channels.
8.2.3 Power Dissipation Calculation and Application Curves
The output current and power dissipation capabilities of the device are heavily dependent on the PCB design
and external system conditions. This section provides some guidelines for calculating these values.
Total power dissipation (PTOT) for the device is composed of three main components. These are the power
MOSFET RDS(ON) (conduction) losses, the power MOSFET switching losses and the quiescent supply current
dissipation. While other factors may contribute additional power losses, these other items are typically
insignificant compared to the three main items.
PTOT = PCOND + PSW + PQ
For loads connected to VM, assuming that all the outputs are loaded with same current, total conduction loss
can be expressed as PCOND = 4 x (IOUT)2 x RDS(ONL)
As the high-side and low-side MOSFETs of the DRV8935 have the same on-resistance, the conduction loss
will be independent of the duty cycle of the input PWM or the amount of PWM off-time. It should be noted
that RDS(ON) has a strong correlation with the device temperature. A curve showing the normalized RDS(ON) with
temperature can be found in the Typical Characteristics curves.
PCOND = 4 x (1.5-A)2 x 0.165-Ω = 1.485-W
PSW can be calculated from the nominal supply voltage (VM), regulated output current (IOUT), switching
frequency (fPWM) and the device output rise (tRISE) and fall (tFALL) time specifications.
Assuming that all the four outputs are switching simultaneously PSW = 4 x (PSW_RISE + PSW_FALL)
PSW_RISE = 0.5 x VM x IOUT x tRISE x fPWM
PSW_FALL = 0.5 x VM x IOUT x tFALL x fPWM
PSW_RISE = 0.5 x 24 V x 1.5 A x 100 ns x 40 kHz = 0.072 W
PSW_FALL = 0.5 x 24 V x 1.5 A x 100 ns x 40 kHz = 0.072 W
PSW = 4 x (0.072W + 0.072W) = 0.576 W
PQ can be calculated from the nominal supply voltage (VM) and the IVM current specification.
PQ = VM x IVM = 24 V x 5 mA = 0.12 W
The total power dissipation (PTOT) is calculated as the sum of conduction loss, switching loss and the quiescent
power loss.
PTOT = PCOND + PSW + PQ = 1.485-W + 0.576-W + 0.12-W = 2.181-W
For an ambient temperature of TA and total power dissipation (PTOT), the junction temperature (TJ) is calculated
as
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TJ = TA + (PTOT x RθJA)
Considering a JEDEC standard 4-layer PCB, the junction-to-ambient thermal resistance (RθJA) is 31 °C/W for
the HTSSOP package and 40.7 °C/W for the VQFN package.
Assuming 25°C ambient temperature, the junction temperature for the HTSSOP package is calculated as TJ = 25°C + (2.181-W x 31°C/W) = 92.6 °C
The junction temperature for the VQFN package is calculated as TJ = 25°C + (2.181-W x 40.7°C/W) = 113.8 °C
It should be ensured that the device junction temperature is within the specified operating region.
CH1 = IN1 (3V/div), CH3 = OUT1 (24V/div), CH7 = IOUT1 (1.5A/div)
Figure 8-2. Current Regulation with VM-connected Load
CH1 = IN1 (3V/div), CH3 = OUT1 (24V/div)
Figure 8-3. IN1 to OUT1 Propagation Delay
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9 Power Supply Recommendations
The device is designed to operate from an input voltage supply (VM) range from 4.5 V to 33 V. A 0.01-µF
ceramic capacitor rated for VM must be placed at each VM pin as close to the device as possible. In addition, a
bulk capacitor must be included on VM.
9.1 Bulk Capacitance
Having appropriate local bulk capacitance is an important factor in motor drive system design. It is generally
beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size.
The amount of local capacitance needed depends on a variety of factors, including:
•
•
•
•
•
•
The highest current required by the motor system
The power supply’s capacitance and ability to source current
The amount of parasitic inductance between the power supply and motor system
The acceptable voltage ripple
The type of motor used (brushed DC, brushless DC, stepper)
The motor braking method
The inductance between the power supply and motor drive system will limit the rate current can change from the
power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands
or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage
remains stable and high current can be quickly supplied.
The data sheet generally provides a recommended value, but system-level testing is required to determine the
appropriate sized bulk capacitor.
The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases
when the motor transfers energy to the supply.
Power Supply
Parasitic Wire
Inductance
Motor Drive System
VM
+
±
+
Motor
Driver
GND
Local
Bulk Capacitor
IC Bypass
Capacitor
Copyright © 2016, Texas Instruments Incorporated
Figure 9-1. Example Setup of Motor Drive System With External Power Supply
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10 Layout
10.1 Layout Guidelines
The VM pin should be bypassed to PGND using a low-ESR ceramic bypass capacitor with a recommended
value of 0.01 µF rated for VM. This capacitor should be placed as close to the VM pin as possible with a thick
trace or ground plane connection to the device PGND pin.
The VM pin must be bypassed to ground using a bulk capacitor rated for VM. This component can be an
electrolytic capacitor.
A low-ESR ceramic capacitor must be placed in between the CPL and CPH pins. A value of 0.022 µF rated for
VM is recommended. Place this component as close to the pins as possible.
A low-ESR ceramic capacitor must be placed in between the VM and VCP pins. A value of 0.22 µF rated for 16
V is recommended. Place this component as close to the pins as possible.
Bypass the DVDD pin to ground with a low-ESR ceramic capacitor. A value of 0.47 µF rated for 6.3 V is
recommended. Place this bypassing capacitor as close to the pin as possible.
The thermal PAD must be connected to system ground.
10.2 Layout Example
Figure 10-1. HTSSOP Layout Recommmendation
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Figure 10-2. QFN Layout Recommendation
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
•
•
•
•
Texas Instruments, How to Drive Unipolar Stepper Motors with DRV8xxx application report
Texas Instruments, PowerPAD™ Thermally Enhanced Package application report
Texas Instruments, PowerPAD™ Made Easy application report
Texas Instruments, Calculating Motor Driver Power Dissipation application report
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
11.4 Trademarks
All trademarks are the property of their respective owners.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
PWP0028M
TM
PowerPAD TSSOP - 1.2 mm max height
SCALE 2.000
SMALL OUTLINE PACKAGE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX
AREA
SEATING
PLANE
26X 0.65
28
1
2X
9.8
9.6
NOTE 3
8.45
14
15
0.30
0.19
0.1
C A B
28X
4.5
4.3
B
SEE DETAIL A
(0.15) TYP
2X 0.82 MAX
NOTE 5
14
15
2X 0.825 MAX
NOTE 5
0.25
GAGE PLANE
1.2 MAX
4.05
3.53
THERMAL
PAD
0 -8
0.15
0.05
0.75
0.50
DETAIL A
A 20
TYPICAL
28
1
3.10
2.58
4224480/A 08/2018
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ or may not be present.
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EXAMPLE BOARD LAYOUT
PWP0028M
TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(3.4)
NOTE 9
(3.1)
METAL COVERED
BY SOLDER MASK
SYMM
28X (1.5)
1
28X (0.45)
28
SEE DETAILS
(R0.05) TYP
26X (0.65)
(4.05)
(0.6)
SYMM
(9.7)
NOTE 9
SOLDER MASK
DEFINED PAD
(1.2) TYP
( 0.2) TYP
VIA
15
14
(1.2) TYP
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 8X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4224480/A 08/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
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EXAMPLE STENCIL DESIGN
PWP0028M
TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(3.1)
BASED ON
0.125 THICK
STENCIL
28X (1.5)
METAL COVERED
BY SOLDER MASK
1
28
28X (0.45)
(R0.05) TYP
26X (0.65)
(4.05)
BASED ON
0.125 THICK
STENCIL
SYMM
15
14
SYMM
(5.8)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 8X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
0.125
0.15
0.175
3.47 X 4.53
3.10 X 4.05 (SHOWN)
2.83 X 3.70
2.62 X 3.42
4224480/A 08/2018
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
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PACKAGE OPTION ADDENDUM
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27-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
DRV8935PPWPR
ACTIVE
HTSSOP
PWP
28
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
DRV8935P
DRV8935PRGER
ACTIVE
VQFN
RGE
24
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
DRV
8935P
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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