DS10BR254
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SNLS260D – DECEMBER 2007 – REVISED APRIL 2013
DS10BR254 1.5 Gbps 1:4 LVDS Repeater
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FEATURES
DESCRIPTION
•
The DS10BR254 is a 1.5 Gbps 1:4 LVDS repeater
optimized for high-speed signal routing and
distribution over FR-4 printed circuit board
backplanes and balanced cables. Fully differential
signal paths ensure exceptional signal integrity and
noise immunity.
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2
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DC - 1.5 Gbps Low Jitter, Low Skew, Low
Power Operation
Wide Input Common Mode Voltage Range
Allows for DC-Coupled Interface to LVDS, CML
and LVPECL Drivers
Redundant Inputs
LOS Circuitry Detects Open Inputs Fault
Condition
Integrated 100Ω Input and Output
Terminations
8 kV ESD on LVDS I/O Pins Protects Adjoining
Components
Small 6 mm x 6 mm WQFN-40 Space Saving
Package
APPLICATIONS
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Clock Distribution
Clock and Data Buffering and Muxing
OC-12 / STM-4
SD/HD SDI Routers
The device has two different LVDS input channels
and a select pin determines which input is active. A
loss-of-signal (LOS) circuit monitors both input
channels and a unique LOS pin is asserted when no
signal is detected at that input.
Wide input common mode range allows the switch to
accept signals with LVDS, CML and LVPECL levels;
the output levels are LVDS. A very small package
footprint requires a minimal space on the board while
the flow-through pinout allows easy board layout.
Each differential input and output is internally
terminated with a 100Ω resistor to lower device return
losses, reduce component count and further minimize
board space.
Typical Application
CARD A
CARD C
ASIC/FPGA 1
ASIC/FPGA
ASIC/FPGA 2
DS10BR254
1:4 LVDS
Repeater
Discrete
Serializer
CARD B
Discrete
Deserializer 1
Discrete
Deserializer 2
BACKPLANE
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2013, Texas Instruments Incorporated
DS10BR254
SNLS260D – DECEMBER 2007 – REVISED APRIL 2013
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Block Diagram
SEL_in
PWDNn
4
OUT0+
OUT0IN1+
OUT1+
IN1-
OUT1-
IN2+
OUT2+
IN2-
OUT2OUT3+
OUT3-
PWDN
Control and LOS
Circuitry
2
LOSn
NC
NC
PWDN
LOS1
LOS2
PWDN0
PWDN1
PWDN2
PWDN3
NC
40
39
38
37
36
35
34
33
32
31
Connection Diagram
NC
1
30
VDD
NC
2
29
OUT0+
VDD
3
28
OUT0-
IN1+
4
27
OUT1+
26
OUT1-
25
VDD
DAP
IN1-
5
IN2+
6
IN2-
7
24
OUT2+
VDD
8
23
OUT2-
NC
9
22
OUT3+
NC
10
21
OUT3-
11
12
13
14
15
16
17
18
19
20
NC
NC
NC
SEL_in
VDD
GND
NC
NC
NC
NC
(GND)
Figure 1. DS10BR254 Pin Diagram
See Package Number RTA0040A
2
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SNLS260D – DECEMBER 2007 – REVISED APRIL 2013
PIN DESCRIPTIONS
Pin Name
Pin
Number
IN1+, IN1-,
IN2+, IN2-,
I/O, Type
Pin Description
4, 5,
6, 7,
I, LVDS
Inverting and non-inverting high speed LVDS input pins.
OUT0+, OUT0-,
OUT1+, OUT1-,
OUT2+, OUT2-,
OUT3+, OUT3-
29,
27,
24,
22,
O, LVDS
Inverting and non-inverting high speed LVDS output pins.
SEL_in
14
I, LVCMOS
This pin selects which LVDS input is active.
LOS1,
LOS2
37,
36
O, LVCMOS
Loss Of Signal output pins, LOSn report when an open input fault condition is
detected at the input, INn. These are open drain outputs. External pull up
resistors are required.
PWDN0,
PWDN1,
PWDN2,
PWDN3
35,
34
33,
32
I, LVCMOS
Channel output power down pin. When the PWDNn is set to L, the channel
output OUTn is in the power down mode.
PWDN
38
I, LVCMOS
Device power down pin. When the PWDN is set to L, the device is in the
power down mode.
VDD
3, 8,
15,25, 30
Power
Power supply pins.
GND
16, DAP
Power
Ground pin and a pad (DAP - die attach pad).
NC
1, 2
9, 10,
11, 12,
13, 17,
18, 19,
20, 31,
39, 40
NC
NO CONNECT pins. May be left floating.
28,
26,
23,
21
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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DS10BR254
SNLS260D – DECEMBER 2007 – REVISED APRIL 2013
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Absolute Maximum Ratings (1) (2)
−0.3V to +4V
Supply Voltage
LVCMOS Input Voltage
−0.3V to (VCC + 0.3V)
LVCMOS Output Voltage
−0.3V to (VCC + 0.3V)
−0.3V to +4V
LVDS Input Voltage
Differential Input Voltage |VID|
1V
−0.3V to (VCC + 0.3V)
LVDS Output Voltage
LVDS Differential Output Voltage
0.0V to +1V
LVDS Output Short Circuit Current Duration
5 ms
Junction Temperature
+150°C
−65°C to +150°C
Storage Temperature Range
Lead Temperature Range Soldering (4 sec.)
+260°C
Maximum Package Power
Dissipation at 25°C
SQA Package
4.65W
Package Thermal
Resistance
θJA
+26.9°C/W
θJC
+3.8°C/W
ESD Susceptibility
HBM (3)
≥8 kV
MM (4)
≥250V
Derate SQA Package
37.2 mW/°C above +25°C
CDM (5)
(1)
(2)
(3)
(4)
(5)
≥1250V
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Human Body Model, applicable std. JESD22-A114C
Machine Model, applicable std. JESD22-A115-A
Field Induced Charge Device Model, applicable std. JESD22-C101-C
Recommended Operating Conditions
Supply Voltage (VCC)
Receiver Differential Input Voltage (VID)
Operating Free Air Temperature (TA)
4
Min
Typ
Max
Units
3.0
3.3
3.6
V
1
V
+85
°C
0
−40
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+25
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SNLS260D – DECEMBER 2007 – REVISED APRIL 2013
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) (3)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V
LVCMOS DC SPECIFICATIONS
VIH
High Level Input Voltage
2.0
VDD
VIL
Low Level Input Voltage
GND
0.8
V
IIH
High Level Input Current
VIN = 3.6V
VCC = 3.6V
0
±10
μA
IIL
Low Level Input Current
VIN = GND
VCC = 3.6V
0
±10
μA
VCL
Input Clamp Voltage
ICL = −18 mA, VCC = 0V
−0.9
−1.5
V
VOL
Low Level Output Voltage
IOL= 4 mA
0.26
0.4
V
1
V
+100
mV
LVDS INPUT DC SPECIFICATIONS
VID
Input Differential Voltage
0
VTH
Differential Input High Threshold
VTL
Differential Input Low Threshold
VCMR
Common Mode Voltage Range
VID = 100 mV
IIN
Input Current
VIN = +3.6V or 0V
VCC = 3.6V or 0V
±1
CIN
Input Capacitance
Any LVDS Input Pin to GND
1.7
pF
RIN
Input Termination Resistor
Between IN+ and IN-
100
Ω
VCM = +0.05V or VCC-0.05V
0
−100
0
0.05
mV
VCC 0.05
V
±10
μA
LVDS OUTPUT DC SPECIFICATIONS
VOD
Differential Output Voltage
250
ΔVOD
Change in Magnitude of VOD for Complimentary
Output States
VOS
Offset Voltage
ΔVOS
Change in Magnitude of VOS for Complimentary
Output States
IOS
Output Short Circuit Current
RL = 100Ω
-35
1.05
(4)
RL = 100Ω
350
1.2
-35
450
mV
35
mV
1.375
V
35
mV
OUT to GND
-35
-55
mA
OUT to VCC
7
55
mA
COUT
Output Capacitance
Any LVDS Output Pin to GND
1.2
pF
ROUT
Output Termination Resistor
Between OUT+ and OUT-
100
Ω
SUPPLY CURRENT
ICC
Supply Current
PWDN = H
113
135
mA
ICCZ
Power Down Supply Current
PWDN = L
50
60
mA
(1)
(2)
(3)
(4)
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
except VOD and ΔVOD.
Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions
at the time of product characterization and are not ensured.
Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
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DS10BR254
SNLS260D – DECEMBER 2007 – REVISED APRIL 2013
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AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
440
650
ps
400
650
ps
LVDS OUTPUT AC SPECIFICATIONS
tPLHD
Differential Propagation Delay Low to
High (1)
tPHLD
Differential Propagation Delay High to
Low (1)
tSKD1
Pulse Skew |tPLHD − tPHLD| (1) (2)
40
100
ps
tSKD2
Channel to Channel Skew (1) (3)
40
125
ps
tSKD3
Part to Part Skew
tLHT
Rise Time (1)
tHLT
Fall Time (1)
tON
RL = 100Ω
(1) (4)
50
200
ps
150
300
ps
150
300
ps
Any PWDN to Output Active Time
8
20
μs
tOFF
Any PWDN to Output Inactive Time
5
12
ns
tSEL
Select Time
5
12
ns
135 MHz
0.5
1
ps
311 MHz
0.5
1
ps
503 MHz
0.5
1
ps
750 MHz
0.5
1
ps
270 Mbps
6
22
ps
622 Mbps
6
21
ps
1.0625 Gbps
9
18
ps
RL = 100Ω
JITTER PERFORMANCE (1)
tRJ1
tRJ2
tRJ3
Random Jitter
(RMS Value) (5)
VID = 350 mV
VCM = 1.2V
Clock (RZ)
tRJ4
tDJ1
tDJ2
tDJ3
Deterministic Jitter
(Peak to Peak Value) (6)
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
tDJ4
tTJ1
tTJ2
tTJ3
Total Jitter (7)
tTJ4
(1)
(2)
(3)
(4)
(5)
(6)
(7)
6
VID = 350 mV
VCM = 1.2V
PRBS-23 (NRZ)
1.5 Gbps
9
17
ps
270 Mbps
0.01
0.03
UIP-P
622 Mbps
0.01
0.03
UIP-P
1.0625 Gbps
0.01
0.04
UIP-P
1.5 Gbps
0.01
0.06
UIP-P
Specification is specified by characterization and is not tested in production.
tSKD1, |tPLHD − tPHLD|, Pulse Skew, is the magnitude difference in differential propagation delay time between the positive going edge and
the negative going edge of the same channel.
tSKD2, Channel to Channel Skew, is the difference in propagation delay (tPLHD or tPHLD) among all output channels in Broadcast mode
(any one input to all outputs).
tSKD3, Part to Part Skew, is defined as the difference between the minimum and maximum differential propagation delays. This
specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range.
Measured on a clock edge with a histogram and an accumulation of 1500 histogram hits. Input stimulus jitter is subtracted geometrically.
Tested with a combination of the 1100000101 (K28.5+ character) and 0011111010 (K28.5- character) patterns. Input stimulus jitter is
subtracted algebraically.
Measured on an eye diagram with a histogram and an accumulation of 3500 histogram hits. Input stimulus jitter is subtracted.
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SNLS260D – DECEMBER 2007 – REVISED APRIL 2013
APPLICATION INFORMATION
DC TEST CIRCUITS
¼ DS10BR254
Power Supply
VOH
OUT+
IN+
R
D
RL
Power Supply
IN-
OUTVOL
AC TEST CIRCUITS AND TIMING DIAGRAMS
¼ DS10BR254
OUT+
IN+
R
Signal Generator
D
IN-
RL
OUT-
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DS10BR254
SNLS260D – DECEMBER 2007 – REVISED APRIL 2013
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FUNCTIONAL DESCRIPTION
The DS10BR254 is a 1.5 Gbps 1:4 LVDS repeater optimized for high-speed signal routing and distribution over
lossy FR-4 printed circuit board backplanes and balanced cables.
Table 1. Input Select Truth Table
CONTROL Pin (SEL_in) State
Input Selected
0
IN1
1
IN2
Input Interfacing
The DS10BR254 accepts differential signals and allows simple AC or DC coupling. With a wide common mode
range, the DS10BR254 can be DC-coupled with all common differential drivers (i.e. LVPECL, LVDS, CML). The
following three figures illustrate typical DC-coupled interface to common differential drivers. Note that the
DS10BR254 inputs are internally terminated with a 100Ω resistor.
LVDS
Driver
DS10BR254
Receiver
100: Differential T-Line
OUT+
IN+
100:
IN-
OUT-
Figure 2. Typical LVDS Driver DC-Coupled Interface to an DS10BR254 Input
CML3.3V or CML2.5V
Driver
VCC
50:
DS10BR254
Receiver
100: Differential T-Line
50:
OUT+
IN+
100:
IN-
OUT-
Figure 3. Typical CML Driver DC-Coupled Interface to an DS10BR254 Input
8
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SNLS260D – DECEMBER 2007 – REVISED APRIL 2013
LVPECL
Driver
OUT+
100: Differential T-Line
LVDS
Receiver
IN+
100:
OUT150-250:
IN150-250:
Figure 4. Typical LVPECL Driver DC-Coupled Interface to an DS10BR254 Input
Output Interfacing
The DS10BR254 outputs signals compliant to the LVDS standard. Its outputs can be DC-coupled to most
common differential receivers. The following figure illustrates typical DC-coupled interface to common differential
receivers and assumes that the receivers have high impedance inputs. While most differential receivers have a
common mode input range that can accomodate LVDS compliant signals, it is recommended to check respective
receiver's data sheet prior to implementing the suggested interface implementation.
DS10BR254
Driver
Differential
Receiver
100: Differential T-Line
OUT+
IN+
CML or
LVPECL or
LVDS
100:
100:
IN-
OUT-
Figure 5. Typical DS10BR254 Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver
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DS10BR254
SNLS260D – DECEMBER 2007 – REVISED APRIL 2013
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Typical Performance
Figure 6. A 1.5 Gbps NRZ PRBS-7 After 2"
Differential FR-4 Stripline
V:100 mV / DIV, H:100 ps / DIV
Figure 7. A 1.06 Gbps NRZ PRBS-7 After 2"
Differential FR-4 Stripline
V:100 mV / DIV, H:200 ps / DIV
Figure 8. A 622 Mbps NRZ PRBS-7 After 2"
Differential FR-4 Stripline
V:100 mV / DIV, H:200 ps / DIV
Figure 9. A 270 Mbps NRZ PRBS-7 After 2"
Differential FR-4 Stripline
V:100 mV / DIV, H:500 ps / DIV
120
VCC = 3.3V
TA = 25°C
NRZ PRBS-7
SUPPLY CURRENT (mA)
110
All Outputs ON
100
3 Outputs ON
90
2 Outputs ON
80
70
1 Output ON
60
0
0.8
1.6
2.4
3.2
4.0
DATA RATE (Gbps)
Figure 10. Supply Current as a Function of a Number of Outputs Used
10
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SNLS260D – DECEMBER 2007 – REVISED APRIL 2013
REVISION HISTORY
Changes from Revision C (April 2013) to Revision D
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 10
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
DS10BR254TSQ/NOPB
ACTIVE
WQFN
RTA
40
250
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
1BR254SQ
DS10BR254TSQX/NOPB
ACTIVE
WQFN
RTA
40
2500
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
1BR254SQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
