DS10CP154
1.5 Gbps 4x4 LVDS Crosspoint Switch
General Description
Features
The DS10CP154 is a 1.5 Gbps 4x4 LVDS crosspoint switch
optimized for high-speed signal routing and switching over
FR-4 printed circuit board backplanes and balanced cables.
Fully differential signal paths ensure exceptional signal integrity and noise immunity. The non-blocking architecture
allows connections of any input to any output or outputs. The
switch configuration can be accomplished via external pins or
the System Management Bus (SMBus) interface. In addition,
the SMBus circuitry enables the loss of signal (LOS) monitors
that can inform a system of the presence of an open inputs
condition (e.g. disconnected cable).
The DS10CP154 supports only a restricted SMBus application of a point-to-point connection between the master and a
single slave device. The DS25CP104 SMBus cannot be
shared with multiple SMBus slave devices on the same bus.
For applications that require multiple SMBus slave devices
using the same bus, the DS10CP154A is recommended.
Wide input common mode range allows the switch to accept
signals with LVDS, CML and LVPECL levels; the output levels
are LVDS. A very small package footprint requires a minimal
space on the board while the flow-through pinout allows easy
board layout. Each differential input and output is internally
terminated with a 100Ω resistor to lower device insertion and
return losses, reduce component count and further minimize
board space.
■ DC - 1.5 Gbps low jitter, low skew, low power operation
■ Pin and SMBus configurable, fully differential, non■
■
■
■
■
blocking architecture
Wide input common mode range enables DC coupled
interface to CML or LVPECL drivers
LOS circuitry detects open inputs fault condition
On-chip 100 Ω input and output termination minimizes
insertion and return losses, reduces component count and
minimizes board space
8 kV ESD on LVDS I/O pins protects adjoining
components
Small 6 mm x 6 mm LLP-40 space saving package
Applications
■ High-speed channel select applications
■ Clock and data buffering and muxing
■ SD / HD SDI Routers
Typical Application
30006603
© 2008 National Semiconductor Corporation
300066
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DS10CP154 1.5 Gbps 4x4 LVDS Crosspoint Switch
August 19, 2008
DS10CP154
Ordering Code
NSID
Function
DS10CP154TSQ
Crosspoint Switch
Block Diagram
30006601
Connection Diagram
30006602
DS10CP154 Pin Diagram
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2
DS10CP154
Pin Descriptions
Pin Name
Pin
Number
I/O, Type
Pin Description
IN0+, IN0- ,
IN1+, IN1-,
IN2+, IN2-,
IN3+, IN3-
1, 2,
4, 5,
6, 7,
9, 10
I, LVDS
Inverting and non-inverting high speed LVDS input pins.
OUT0+, OUT0-,
OUT1+, OUT1-,
OUT2+, OUT2-,
OUT3+, OUT3-
29, 28,
27, 26,
24, 23,
22, 21
O, LVDS
Inverting and non-inverting high speed LVDS output pins.
EN_smb
17
I, LVCMOS
System Management Bus (SMBus) mode enable pin. The pin has
an internal 20k pull down. When the pin is set to a [1], the device
is in the SMBus mode. All SMBus registers are reset when the pin
is toggled.
S00/SCL,
S01/SDA
37,
36
I/O, LVCMOS
For EN_smb = [1], these pins select which LVDS input is routed
to the OUT0.
In the SMBus mode, when the EN_smb = [1], these pins are the
SMBus clock input and data I/O pins respectively.
S10/ADDR0,
S11/ADDR1
35,
34
I/O, LVCMOS
For EN_smb = [0], these pins select which LVDS input is routed
to the OUT1.
In the SMBus mode, when the EN_smb = [1], these pins are the
User-Set SMBus Slave Address inputs.
S20/ADDR2,
S21/ADDR3
33,
32
I/O, LVCMOS
For EN_smb = [0], these pins select which LVDS input is routed
to the OUT2.
In the SMBus mode, when the EN_smb = [1], these pins are the
User-Set SMBus Slave Address inputs.
S30, S31
13, 14
I, LVCMOS
For EN_smb = [0], these pins select which LVDS input is routed
to the OUT3.
In the SMBus mode, when the EN_smb = [1], these pins are nonfunctional and should be tied to either logic [0] or [1].
PWDN
38
I, LVCMOS
For EN_smb = [0], this is the power down pin. When the PWDN is
set to a [0], the device is in the power down mode. The SMBus
circuitry can still be accessed provided the EN_smb pin is set to a
[1].
In the SMBus mode, the device is powered up by either setting the
PWDN pin to [1] OR by writing a [1] to the Control Register D[7]
bit ( SoftPWDN). The device will be powered down by setting the
PWDN pin to [0] AND by writing a [0] to the Control Register D[7]
bit ( SoftPWDN).
NC
11, 12,
18, 19,
20, 31,
39, 40
No connect pins. May be left floating.
VDD
3, 8,
Power
15,25, 30
Power supply pins.
GND
16, DAP
Ground pin and pad (DAP - die attach pad).
Power
3
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DS10CP154
Package Thermal Resistance
Absolute Maximum Ratings (Note 4)
θJA
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
+26.9°C/W
θJC
ESD Susceptibility
HBM (Note 1)
Supply Voltage
−0.3V to +4V
LVCMOS Input Voltage
−0.3V to (VCC + 0.3V)
LVCMOS Output Voltage
−0.3V to (VCC + 0.3V)
LVDS Input Voltage
−0.3V to +4V
LVDS Differential Input Voltage
0V to 1.0V
LVDS Output Voltage
−0.3V to (VCC + 0.3V)
LVDS Differential Output Voltage
0V to 1.0V
LVDS Output Short Circuit Current
5 ms
Duration
Junction Temperature
+150°C
Storage Temperature Range
−65°C to +150°C
Lead Temperature Range
Soldering (4 sec.)
+260°C
Maximum Package Power Dissipation at 25°C
SQA Package
4.65W
Derate SQA Package
37.2 mW/°C above +25°C
+3.8°C/W
≥8 kV
≥250V
≥1250V
MM (Note 2)
CDM (Note 3)
Note 1: Human Body Model, applicable std. JESD22-A114C
Note 2: Machine Model, applicable std. JESD22-A115-A
Note 3: Field Induced Charge Device Model, applicable std.
JESD22-C101-C
Recommended Operating
Conditions
Supply Voltage (VCC)
Receiver Differential Input
Voltage (VID)
Operating Free Air
Temperature (TA)
SMBus (SDA, SCL)
Min
3.0
0
Typ
3.3
Max
3.6
1.0
Units
V
V
−40
+25
+85
°C
3.6
V
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 5, 6, 7)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
LVCMOS DC SPECIFICATIONS
VIH
High Level Input Voltage
2.0
VDD
V
VIL
Low Level Input Voltage
GND
0.8
V
IIH
High Level Input Current
VIN = 3.6V
VCC = 3.6V
EN_smb pin
IIL
Low Level Input Current
VIN = GND
VCC = 3.6V
VCL
Input Clamp Voltage
ICL = −18 mA, VCC = 0V
VOL
Low Level Output Voltage
IOL= 4 mA
40
0
±10
μA
175
250
μA
0
±10
μA
−0.9
−1.5
V
0.4
V
SDA pin
LVDS INPUT DC SPECIFICATIONS
VID
Input Differential Voltage
VTH
Differential Input High Threshold
VTL
Differential Input Low Threshold
VCMR
Common Mode Voltage Range
VID = 100 mV
IIN
Input Current
VIN = 3.6V or 0V
VCC = 3.6V or 0V
CIN
Input Capacitance
Any LVDS Input Pin to GND
1.7
pF
Between IN+ and IN-
100
Ω
RIN
Input Termination Resistor
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0
VCM = +0.05V or VCC-0.05V
0
−100
4
1
V
+100
mV
0
0.05
±1
mV
VCC 0.05
V
±10
μA
Parameter
Conditions
Min
Typ
Max
Units
250
350
450
mV
35
mV
1.375
V
35
mV
LVDS OUTPUT DC SPECIFICATIONS
VOD
Differential Output Voltage
ΔVOD
Change in Magnitude of VOD for Complimentary
Output States
VOS
Offset Voltage
ΔVOS
Change in Magnitude of VOS for Complimentary
Output States
RL = 100Ω
IOS
Output Short Circuit Current (Note 8)
OUT to GND
-25
-55
mA
OUT to VCC
7
55
mA
RL = 100Ω
-35
1.05
1.2
-35
COUT
Output Capacitance
Any LVDS Output Pin to GND
1.2
pF
ROUT
Output Termination Resistor
Between OUT+ and OUT-
100
Ω
SUPPLY CURRENT
ICC1
Supply Current
PWDN = 0
40
50
mA
ICC2
Supply Current
PWDN = 1
Broadcast Mode (1:4)
103
125
mA
ICC3
Supply Current
PWDN = 1
Quad Buffer Mode (4:4)
115
140
mA
Note 4: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions.
Note 5: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 6: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD and
ΔVOD.
Note 7: Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not guaranteed.
Note 8: Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
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DS10CP154
Symbol
DS10CP154
AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 9, 10)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
500
675
ps
460
675
ps
LVDS OUTPUT AC SPECIFICATIONS (Note 11)
tPLHD
Differential Propagation Delay Low to
High
tPHLD
Differential Propagation Delay High to
Low
tSKD1
Pulse Skew |tPLHD − tPHLD| , (Note 12)
40
100
ps
tSKD2
Channel to Channel Skew , (Note 13)
40
125
ps
tSKD3
Part to Part Skew , (Note 14)
50
225
ps
tLHT
Rise Time
145
350
ps
tHLT
Fall Time
145
350
ps
tON
Power Up Time
Time from PWDN = LH to OUTn active
7
20
μs
tOFF
Power Down Time
Time from PWDN = HL to OUTn
inactive
6
25
ns
tSEL
Select Time
Time from Sn = LH or HL to new signal
at OUTn
8
12
ns
135 MHz
1
2.0
ps
311 MHz
0.5
1.2
ps
503 MHz
0.5
1.0
ps
750 MHz
0.5
1.0
ps
270 Mbps
7
30
ps
622 Mbps
12
26
ps
1.06 Gbps
9
24
ps
1.5 Gbps
12
28
ps
270 mbps
0.008
0.036
UIP-P
622 Mbps
0.007
0.043
UIP-P
1.06Gbps
0.008
0.064
UIP-P
1.5 Gbps
0.007
0.072
UIP-P
RL = 100Ω
RL = 100Ω
JITTER PERFORMANCE (Note 11)
tRJ1
tRJ2
tRJ3
Random Jitter
(RMS Value)
(Note 15)
VID = 350 mV
VCM = 1.2V
Clock (RZ)
tRJ4
tDJ1
tDJ2
tDJ3
Deterministic Jitter
(Peak to Peak Value)
(Note 16)
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
tDJ4
tTJ1
tTJ2
tTJ3
Total Jitter
(Peak to Peak Value)
(Note 17)
VID = 350 mV
VCM = 1.2V
PRBS-23 (NRZ)
tTJ4
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Parameter
Conditions
Min
Typ
Max
Units
100
kHz
SMBus AC SPECIFICATIONS
fSMB
SMBus Operating Frequency
10
tBUF
Bus free time between Stop and Start
Conditions
4.7
μs
tHD:SDA
Hold time after (Repeated) Start
Condition. After this period, the first clock
is generated.
4.0
μs
tSU:SDA
Repeated Start Condition setup time.
4.7
μs
tSU:SDO
Stop Condition setup time
4.0
μs
tHD:DAT
Data hold time
300
ns
tSU:DAT
Data setup time
250
ns
tTIMEOUT
Detect clock low timeout
25
tLOW
Clock low period
4.7
tHIGH
Clock high period
4.0
tPOR
Time in which a device must be
operational after power-on reset
35
ms
μs
50
μs
500
ms
Note 9: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 10: Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not guaranteed.
Note 11: Specification is guaranteed by characterization and is not tested in production.
Note 12: tSKD1, |tPLHD − tPHLD|, Pulse Skew, is the magnitude difference in differential propagation delay time between the positive going edge and the negative
going edge of the same channel.
Note 13: tSKD2, Channel to Channel Skew, is the difference in propagation delay (tPLHD or tPHLD) among all output channels in Broadcast mode (any one input to
all outputs).
Note 14: tSKD3, Part to Part Skew, is defined as the difference between the minimum and maximum differential propagation delays. This specification applies to
devices at the same VCC and within 5°C of each other within the operating temperature range.
Note 15: Measured on a clock edge with a histogram and an acummulation of 1500 histogram hits. Input stimulus jitter is subtracted geometrically.
Note 16: Tested with a combination of the 1100000101 (K28.5+ character) and 0011111010 (K28.5- character) patterns. Input stimulus jitter is subtracted
algebraically.
Note 17: Measured on an eye diagram with a histogram and an acummulation of 3500 histogram hits. Input stimulus jitter is subtracted.
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DS10CP154
Symbol
DS10CP154
DC Test Circuits
30006620
FIGURE 1. Differential Driver DC Test Circuit
AC Test Circuits and Timing Diagrams
30006621
FIGURE 2. Differential Driver AC Test Circuit
30006622
FIGURE 3. Propagation Delay Timing Diagram
30006623
FIGURE 4. LVDS Output Transition Times
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The DS10CP154 is a 1.5 Gbps 4x4 LVDS digital crosspoint
switch optimized for high-speed signal routing and switching
over lossy FR-4 printed circuit board backplanes and balanced cables. The DS10CP154 operates in two modes: Pin
Mode (EN_smb = 0) and SMBus Mode (EN_smb = 1).
When in the Pin Mode, the switch is fully configurable with
external pins. This is possible with two input select pins per
output (e.g. S00 and S01 pins for OUT0).
In the Pin Mode, feedback from the LOS (Loss Of Signal)
monitor circuitry is not available (there is not an LOS output
pin).
The DS10CP154 supports only a restricted SMBus application of a point-to-point connection between the master and a
single slave device. The DS10CP154 SMBus cannot be
shared with multiple SMBus slave devices on the same bus.
For applications that require multiple SMBus slave devices
using the same bus, the DS10CP154A is recommended. For
more information about the DS10CP154 SMBus application
restrictions read the SMBus User Information Note at http://
www.national.com/appinfo/interface/files/
SMBus_UIN_Crosspoints.pdf.
When in the SMBus Mode, the full switch configuration and
SoftPWDN can be programmed via the SMBus interface. In
addition, by using the SMBus interface, a user can obtain the
feedback from the built-in LOS circuitry which detects an open
inputs fault condition.
In the SMBus Mode, the S00 and S01 pins become SMBus
clock (SCL) input and data (SDA) input pins respectively; the
S10, S11, S21 and S21 pins become the User-Set SMBus
Slave Address input pins (ADDR0, 1, 2 and 3) while the S30
and S31 pins become non-functional (tieing these two pins to
either H or L is recommended if the device will function only
in the SMBus mode).
In the SMBus Mode, the PWDN pin remains functional. How
this pin functions in each mode is detailed in the following
sections.
DS10CP154 OPERATION IN THE PIN MODE
Power Up
In the Pin Mode, when the power is applied to the device
power suppy pins, the DS10CP154 enters the Power Up
mode when the PWDN pin is set to logic H. When in the Power
Down mode (PWDN pin is set to logic L), all circuitry is shut
down except the minimum required circuitry for the LOS and
SMBus Slave operation.
Switch Configuration
In the Pin Mode, the DS10CP154 operates as a fully pin-configurable crosspoint switch. The following truth tables illustrate how the swich can be configured with external pins.
Switch Configuration Truth Tables
TABLE 1. Input Select Pins Configuration for the Output OUT0
S01
S00
INPUT SELECTED
0
0
IN0
0
1
IN1
1
0
IN2
1
1
IN3
TABLE 2. Input Select Pins Configuration for the Output OUT1
S11
S10
INPUT SELECTED
0
0
IN0
0
1
IN1
1
0
IN2
1
1
IN3
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DS10CP154
Functional Description
DS10CP154
TABLE 3. Input Select Pins Configuration for the Output OUT2
S21
S20
INPUT SELECTED
0
0
IN0
0
1
IN1
1
0
IN2
1
1
IN3
TABLE 4. Input Select Pins Configuration for the Output OUT3
S31
S30
INPUT SELECTED
0
0
IN0
0
1
IN1
1
0
IN2
1
1
IN3
shared with multiple SMBus slave devices on the same bus.
For applications that require multiple SMBus slave devices
using the same bus, the DS10CP154A is recommended. For
more information about the DS10CP154 SMBus application
restrictions read the SMBus User Information Note at http://
www.national.com/appinfo/interface/files/
SMBus_UIN_Crosspoints.pdf.
DS10CP154 OPERATION IN THE SMBUS MODE
The DS10CP154 operates as a slave on the System Management Bus (SMBus) when the EN_smb pin is set to a high
(1). Under these conditions, the SCL pin is a clock input while
the SDA pin is a serial data input pin.
The DS10CP154 supports only a restricted SMBus application of a point-to-point connection between the master and a
single slave device. The DS10CP154 SMBus cannot be
30006670
FIGURE 5. DS10CP154 SMBus Only Supports a Point-to-Point Connection with a Master
“101”. The four least significant bits of the address are assigned to pins ADDR3-ADDR0 and are set by connecting
these pins to GND for a low (0) or to VCC for a high (1). The
complete slave address is shown in the following table:
Device Address
Based on the SMBus 2.0 specification, the DS10CP154 has
a 7-bit slave address. The three most significant bits of the
slave address are hard wired inside the DS10CP154 and are
TABLE 5. DS10CP154 Slave Address
1
0
1
ADDR3
MSB
ADDR1
ADDR0
LSB
IDLE: If SCK and SDA are both high for a time exceeding
tBUF from the last detected STOP condition or if they are high
for a total exceeding the maximum specification for tHIGH
then the bus will transfer to the IDLE state.
Transfer of Data via the SMBus
During normal operation the data on SDA must be stable during the time when SCK is high.
There are three unique states for the SMBus:
START: A HIGH to LOW transition on SDA while SCK is high
indicates a message START condition.
STOP: A LOW to HIGH transition on SDA while SCK is high
indicates a message STOP condition.
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ADDR2
SMBus Transactions
A transaction begins with the host placing the DS10CP154
SMBus into the START condition, then a byte (8 bits) is transferred, MSB first, followed by a ninth ACK bit. ACK bits are ‘0’
to signify an ACK, or ‘1’ to signify NACK, after this the host
10
1) The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
2) The Device (Slave) drives an ACK bit (“0”).
3) The Host drives the 8-bit Register Address.
4) The Device drives an ACK bit (“0”).
5) The Host drives a START condition.
6) The Host drives the 7-bit SMBus Address, and a “1” indicating a READ.
7) The Device drives an ACK bit “0”.
8) The Device drives the 8-bit data value (register contents).
9) The Host drives a NACK bit “1” indicating end of READ
transfer.
10) The Host drives a STOP condition.
The READ transaction is completed, the bus goes Idle and
communication with other SMBus devices may now occur.
Writing to a Register
To write a register, the following protocol is used (see SMBus
2.0 specification):
1) The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
2) The Device (Slave) drives an ACK bit (“0”).
3) The Host drives the 8-bit Register Address.
4) The Device drives an ACK bit (“0”).
5) The Host drives the 8-bit data byte.
6) The Device drives an ACK bit “0”.
7) The Host drives a STOP condition.
The WRITE transaction is completed, the bus goes Idle and
communication with other SMBus devices may now occur.
Reading From a Register
To read a register, the following protocol is used (see SMBus
2.0 specification):
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DS10CP154
holds the SCL line low, and waits for the receiver to raise the
SDA line as an ACKnowledge that the byte has been received.
DS10CP154
REGISTER DESCRIPTIONS
There are three data registers in the DS10CP154 accessible via the SMBus interface.
TABLE 6. DS10CP154 SMBus Data Registers
Address
(hex)
Name
Access
Description
0
Switch Configuration
R/W
Switch Configuration Register
3
Control
R/W
Powerdown, LOS Enable and Pin Control Register
4
LOS
RO
Loss Of Signal (LOS) Reporting Register
30006610
FIGURE 6. DS10CP154 Registers Block Diagram
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The Switch Configuration register is utilized to configure the switch. The following two tables show the Switch Configuration Register
mapping and associated truth table.
Bit
Default
Bit Name
Access
Description
D[1:0]
00
Input Select 0
R/W
Selects which input is routed to the OUT0.
D[3:2]
00
Input Select 1
R/W
Selects which input is routed to the OUT1.
D[5:4]
00
Input Select 2
R/W
Selects which input is routed to the OUT2.
D[7:6]
00
Input Select 3
R/W
Selects which input is routed to the OUT3.
TABLE 7. Switch Configuration Register Truth Table
D1
D0
Input Routed to the OUT0
0
0
IN0
0
1
IN1
1
0
IN2
1
1
IN3
The truth tables for the OUT1, OUT2, and OUT3 outputs are identical to this table.
The switch configuration logic has a SmartPWDN circuitry which automatically optimizes the device's power consumption based
on the switch configuration (i.e. It places unused I/O blocks and other unused circuitry in the power down state).
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DS10CP154
SWITCH CONFIGURATION REGISTER
DS10CP154
CONTROL REGISTER
The Control register enables SoftPWDN control, individual output power down (PWDNn) control and LOS Circuitry Enable control
via the SMBus. The following table shows the register mapping.
Bit
Default
Bit Name
1111
PWDNn
R/W
Writing a [0] to the bit D[n] will power down the output OUTn
when either the PWDN pin OR the Control Register bit D[7]
(SoftPWDN) is set to a high [1].
D[4]
x
n/a
R/W
Undefined.
D[5]
x
n/a
R/W
Undefined.
D[6]
0
EN_LOS
R/W
Writing a [1] to the bit D[6] will enable the LOS circuitry and
receivers on all four inputs. The SmartPWDN circuitry will not
disable any of the inputs nor any supporting LOS circuitry
depending on the switch configuration.
D[7]
0
SoftPWDN
R/W
Writing a [0] to the bit D[7] will place the device into the power
down mode. This pin is ORed together with the PWDN pin.
D[3:0]
Access
Description
TABLE 8. DS10CP154 Power Modes Truth Table
PWDN
SoftPWDN
PWDNn
0
0
x
DS25CP104 Power Mode
Power Down Mode. In this mode, all circuitry is shut down except the
minimum required circuitry for the LOS and SMBus Slave operation. The
SMBus circuitry allows enabling the LOS circuitry and receivers on all inputs
in this mode by setting the EN_LOS bit to a [1].
0
1
1
1
0
1
x
x
x
Power Up Mode. In this mode, the SmartPWDN circuitry will automatically
power down any unused I/O and logic blocks and other supporting circuitry
depending on the switch configuration.
An output will be enabled only when the SmartPWDN circuitry indicates that
that particular output is needed for the particular switch configuration and
the respective PWDNn bit has logic high [1].
An input will be enabled when the SmartPWDN circuitry indicates that that
particular input is needed for the particular switch configuration or the
EN_LOS bit is set to a [1].
LOS REGISTER
The LOS register reports an open inputs fault condition for each of the inputs. The following table shows the register mapping.
Bit
Default
Bit Name
D[0]
0
LOS0
RO
Reading a [0] from the bit D[0] indicates an open inputs fault condition on
the IN0. A [1] indicates presence of a valid signal.
D[1]
0
LOS1
RO
Reading a [0] from the bit D[1] indicates an open inputs fault condition on
the IN1. A [1] indicates presence of a valid signal.
D[2]
0
LOS2
RO
Reading a [0] from the bit D[2] indicates an open inputs fault condition on
the IN2. A [1] indicates presence of a valid signal.
D[3]
0
LOS3
RO
Reading a [0] from the bit D[3] indicates an open inputs fault condition on
the IN3. A [1] indicates presence of a valid signal.
0000
Reserved
RO
Reserved for future use. Returns undefined value when read.
D[7:4]
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Access
Description
14
30006631
Typical LVDS Driver DC-Coupled Interface to DS10CP154 Input
30006632
Typical CML Driver DC-Coupled Interface to DS10CP154 Input
30006633
Typical LVPECL Driver DC-Coupled Interface to DS10CP154 Input
15
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DS10CP154
drivers (i.e. LVPECL, LVDS, CML). The following three figures illustrate typical DC-coupled interface to common differential drivers. Note that the DS10CP154 inputs are internally
terminated with a 100Ω resistor.
INPUT INTERFACING
The DS10CP154 accepts differential signals and allows simple AC or DC coupling. With a wide common mode range, the
DS10CP154 can be DC-coupled with all common differential
DS10CP154
and assumes that the receivers have high impedance inputs.
While most differential receivers have a common mode input
range that can accomodate LVDS compliant signals, it is recommended to check respective receiver's data sheet prior to
implementing the suggested interface implementation.
OUTPUT INTERFACING
The DS10CP154 outputs signals that are compliant to the
LVDS standard. Its outputs can be DC-coupled to most common differential receivers. The following figure illustrates typical DC-coupled interface to common differential receivers
30006634
Typical DS10CP154 Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver
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16
DS10CP154
Physical Dimensions inches (millimeters) unless otherwise noted
Order Number DS10CP154TSQ
NS Package Number SQA40A
(See AN-1187 for PCB Design and Assembly Recommendations)
17
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DS10CP154 1.5 Gbps 4x4 LVDS Crosspoint Switch
Notes
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