DS125BR800A
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SNLS467 – NOVEMBER 2013
Low-Power 12.5-Gbps 8-Channel (Unidirectional) Repeater With Input Equalization
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FEATURES
DESCRIPTION
•
•
The DS125BR800A is an extremely low-power highperformance multi-protocol repeater/redriver designed
to support eight channels of PCIe, SAS, and other
high-speed interface serial protocols up to 12.5 Gbps.
The receiver's continuous time linear equalizer
(CTLE) provides a boost of up to +30 dB at 6.25 GHz
(12.5 Gbps) in each of its eight channels and is
capable of opening an input eye that is completely
closed due to inter symbol interference (ISI) induced
by interconnect medium such as 30in+ backplane
traces or 8m+ copper cables, hence enabling host
controllers to ensure an error free end-to-end link.
The strong linear equalization maximizes interconnect
channel extension when the DS125BR800A is placed
with the majority of channel loss on the devices input
side. Adjustable transmit de-emphasis and output
voltage amplitude help to compensate for the
remaining channel attenuation on the output side.
1
2
•
•
•
•
•
•
•
•
•
Proven System Interoperability
Comprehensive multi-protocol Repeater
Family
Low 65-mW/Channel (Typ) Power
Consumption, With Option to Power Down
Unused Channels
Transparent Management of Link Training
Protocol for PCIe and SAS
Advanced Signal Conditioning Features
– Rx CTLE up to 30 dB (24 dB for SAS3)
– Tx De-Emphasis up to -12 dB
– Tx Output Voltage Control: 700 - 1300 mV
Device Configuration Interface:
– Pin Selection, EEPROM, or SMBus Interface
Single Supply Voltage: 2.5 V or 3.3 V
−40°C to 85°C Operating Temperature Range
3-kV HBM ESD Rating
Flow-Thru Pinout: 54-Pin LLP (10 mm x 5.5
mm, 0.5 mm pitch)
Supported Protocols
– SAS/SATA
– PCIe
– Other Proprietary Interface up to 12.5 Gbps
When operating in SAS-3 and PCIe Gen-3 mode, the
DS125BR800A transparently allows the host
controller and the end point to optimize the full link
and negotiate transmit equalizer coefficients. This
seamless management of the link training protocol
ensures system level interoperability with minimum
latency. With a low power consumption of 65
mW/channel (typ) and option to turn-off unused
channels, the DS125BR800A enables energy efficient
system design. A single supply of 3.3 V or 2.5 V is
required to power the device.
The programmable settings can be applied easily via
pins, software (SMBus or I2C) or loaded via an
external EEPROM. When operating in the EEPROM
mode, the configuration information is automatically
loaded on power up, which eliminates the need for an
external microprocessor or software driver.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013 , Texas Instruments Incorporated
DS125BR800A
SNLS467 – NOVEMBER 2013
www.ti.com
Typical Application
8
TX
Connector
ASIC
or
PCIe EP
8
RX
DS125BR800A
8
RX
System Board
Root Complex
DS125BR800A
Connector
ard
Bo ce
Tra
8
TX
Block Diagram - Detail View Of Channel (1 Of 8)
VOD/DeEMPHASIS
CONTROL
VDD
Auto/Manual
RXDET
INx_n+
RATE
DET
DEMA/B
SMBus
EQ
OUTBUF
INx_n-
EQA/B
SMBus
2
OUTx_n+
OUTx_n-
IDLE
DET
TX Idle Enable
SMBus
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SNLS467 – NOVEMBER 2013
PWDN
VDD
DEMA1/SCL
DEMA0/SDA
ENSMB
EQB1/AD2
EQB0/AD3
51
50
49
48
47
46
DEMB0/AD1
53
52
DEMB1/AD0
54
Pin Diagram
SMBUS AND CONTROL
INB_0+
1
45
OUTB_0+
INB_0-
2
44
OUTB_0-
INB_1+
3
43
OUTB_1+
INB_1-
4
42
OUTB_1-
INB_2+
5
41
VDD
INB_2-
6
40
OUTB_2+
INB_3+
7
39
OUTB_2-
INB_3-
8
38
OUTB_3+
VDD
9
37
OUTB_3-
INA_0+
10
36
VDD
INA_0-
11
35
OUTA_0+
INA_1+
12
34
OUTA_0-
INA_1-
13
33
OUTA_1+
VDD
14
32
OUTA_1-
INA_2+
15
31
OUTA_2+
INA_2-
16
30
OUTA_2-
INA_3+
17
29
OUTA_3+
INA_3-
18
28
OUTA_3-
19
20
21
22
23
24
25
26
27
EQA1
EQA0
MODE
RXDET
RESERVED
VIN
VDD_SEL
SD_TH/READ_EN
ALL_DONE
DAP = GND
NOTE: Above 54-lead LLP graphic is a TOP VIEW, looking down through the package.
Figure 1. DS125BR800A Pin Diagram 54 lead
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Table 1. Pin Descriptions (1)
Pin Name
Pin Number
I/O, Type
Pin Description
Differential High Speed I/O's
INB_0+, INB_0-,INB_1+,
INB_1-,INB_2+, INB_2,INB_3+, INB_3-
1, 2, 3, 4,
5, 6, 7, 8,
I
Inverting and non-inverting CML differential inputs to the equalizer. Onchip 50Ω termination resistor connects INB_n+ to VDD and INB_n- to
VDD when enabled.
AC coupling required on high-speed I/O
INA_0+, INA_0-,INA_1+,
INA_1-,INA_2+, INA_2,INA_3+, INA_3-
10, 11, 12, 13,
15, 16, 17, 18
I
Inverting and non-inverting CML differential inputs to the equalizer. Onchip 50Ω termination resistor connects INA_n+ to VDD and INA_n- to
VDD when enabled.
AC coupling required on high-speed I/O
OUTB_0+,
OUTB_1+,
OUTB_2+,
OUTB_3+,
OUTB_0-,
OUTB_1-,
OUTB_2-,
OUTB_3-
45, 44, 43, 42,
40, 39, 38, 37
O
Inverting and non-inverting 50Ω driver outputs with de-emphasis.
Compatible with AC coupled CML inputs.
AC coupling required on high-speed I/O
OUTA_0+,
OUTA_1+,
OUTA_2+,
OUTA_3+,
OUTA_0-,
OUTA_1-,
OUTA_2-,
OUTA_3-
35, 34, 33, 32,
31, 30, 29, 28
O
Inverting and non-inverting 50Ω driver outputs with de-emphasis.
Compatible with AC coupled CML inputs.
AC coupling required on high-speed I/O
I, 4-LEVEL
System Management Bus (SMBus) enable pin
Tie 1kΩ to VDD = Register Access SMBus Slave Mode
FLOAT = Read External EEPROM (Master SMBUS Mode)
Tie 1kΩ to GND = Pin Mode
Control Pins — Shared (LVCMOS)
ENSMB
48
ENSMB = 1 (SMBUS MODE)
SCL
50
I, LVCMOS
O, OPEN Drain
ENSMB Master or Slave mode
SMBUS clock input is enabled (slave mode).
Clock output when loading EEPROM configuration (master mode).
SDA
49
I, LVCMOS,
O, OPEN Drain
ENSMB Master or Slave mode
The SMBus bidirectional SDA pin is enabled. Data input or open drain
(pull-down only) output.
AD0-AD3
54, 53, 47, 46
I, LVCMOS
ENSMB Master or Slave mode
SMBus Slave Address Inputs. In SMBus mode, these pins are the user
set SMBus slave address inputs.
READ_EN
26
I, LVCMOS
When using an External EEPROM, a transition from high to low starts
the load from the external EEPROM
EQA0, EQA1,
EQB0, EQB1
20, 19,
46, 47
I, 4-LEVEL
EQA[1:0] and EQB[1:0] control the level of equalization on the input pins.
The pins are active only when ENSMB is de-asserted (low). The 8
channels are organized into two banks. Bank A is controlled with the
EQA[1:0] pins and bank B is controlled with the EQB[1:0] pins. When
ENSMB goes high the SMBus registers provide independent control of
each channel. The EQB[1:0] pins are converted to SMBUS AD2/AD3
inputs. See Table 3.
DEMA0, DEMA1,
DEMB0, DEMB1
49, 50,
53, 54
I, 4-LEVEL
DEMA[1:0] and DEMB[1:0] control the level of de-emphasis of the output
driver. The pins are only active when ENSMB is de-asserted (low). The 8
channels are organized into two banks. Bank A is controlled with the
DEMA[1:0] pins and bank B is controlled with the DEMB[1:0] pins. When
ENSMB goes high the SMBus registers provide independent control of
each channel. The DEMA[1:0] pins are converted to SMBUS SCL/SDA
and DEMB[1:0] pins are converted to AD0, AD1 inputs.
See Table 4.
MODE
21
I, 4-LEVEL
MODE control pin selects operating modes.
Tie 1kΩ to GND = GEN 1,2 and SAS/SATA (up to 6 Gbps)
FLOAT = AUTO Rate Select (for PCIe)
Tie 20kΩ to GND = SAS-3 and GEN-3 without De-emphasis
Tie 1kΩ to VDD = SAS-3 and GEN-3 with De-emphasis
See Table 7
ENSMB = 0 (PIN MODE)
(1)
4
LVCMOS inputs without the "FLOAT" conditions must be driven to a logic low or high at all times or operation is not guaranteed.
Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%.
For 3.3V mode operation, VIN pin = 3.3V and the "VDD" for the 4-level input is 3.3V.
For 2.5V mode operation, VDD pin = 2.5V and the "VDD" for the 4-level input is 2.5V.
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Table 1. Pin Descriptions(1) (continued)
Pin Name
Pin Number
I/O, Type
Pin Description
SD_TH
26
I, 4-LEVEL
Controls the internal Signal Detect Threshold.
See Table 6.
Control Pins — Both Pin and SMBus Modes (LVCMOS)
RXDET
22
I, 4-LEVEL
The RXDET pin controls the receiver detect function. Depending on the
input level, a 50Ω or >50kΩ termination to the power rail is enabled.
See Table 5.
RESERVED
23
I, 4-LEVEL
Float (leave pin open) = Normal Operation
VDD_SEL
25
INPUT
Controls the internal regulator
FLOAT = 2.5V mode
Tie GND = 3.3V mode
PWDN
52
I, LVCMOS
Tie High = Low power - power down
Tie GND = Normal Operation
See Table 5.
27
O, LVCMOS
Valid Register Load Status Output
HIGH = External EEPROM load failed or incomplete
LOW = External EEPROM load passed
VIN
24
Power
In 3.3V mode, feed 3.3V to VIN
In 2.5V mode, leave floating
VDD
9, 14, 36, 41, 51
Power
Power supply pins CML/analog
2.5V mode, connect to 2.5V supply
3.3V mode, connect 0.1uF cap to each VDD pin
GND
DAP
Power
Ground pad (DAP - die attach pad)
Outputs
ALL_DONE
Power
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2)
Supply Voltage (VDD - 2.5V mode)
-0.5V to +2.75V
Supply Voltage (VIN - 3.3V mode)
-0.5V to +4.0V
LVCMOS Input/Output Voltage
-0.5V to +4.0V
CML Input Voltage
-0.5V to (VDD+0.5)
CML Input Current
-30 to +30 mA
Junction Temperature
125°C
Storage Temperature
-40°C to +125°C
Lead Temperature Range Soldering (4 sec.)
+260°C
Derate NJY Package
52.6mW/°C above +25°C
ESD Rating
HBM, STD - JESD22-A114F
3 kV
CDM, STD - JESD22-C101-D
Thermal Resistance
1000 V
θJC
11.5°C/W
θJA, No Airflow, 4 layer JEDEC
19.1°C/W
For soldering specifications: see product folder at www.ti.com
(1)
(2)
"Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Absolute
Maximum Numbers are ensured for a junction temperature range of -40°C to +125°C. Models are validated to Maximum Operating
Voltages only.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
Recommended Operating Conditions
Min
Typ
Max
Unit
Supply voltage (2.5V mode)
2.375
2.5
2.625
V
Supply voltage (3.3V mode)
3.0
3.3
3.6
V
Ambient temperature
-40
25
+85
°C
SMBus (SDA, SCL)
Supply noise up to 50 MHz
(1)
(1)
3.6
V
100
mVp-p
Allowed supply noise (mVp-p sine wave) under typical conditions.
Electrical Characteristics (1) (2) (3)
Symbol
Parameter
Test Conditions
Power Dissipation
Min
Typ
Max
Unit
VDD = 2.5 V supply,
EQ Enabled,
VOD = 1.0 Vp-p,
RXDET = 1, PWDN = 0
500
700
mW
VIN = 3.3 V supply,
EQ Enabled,
VOD = 1.0 Vp-p,
RXDET = 1, PWDN = 0
660
900
mW
3.6
V
Power
PD
LVCMOS / LVTTL DC Specifications
Vih
(1)
(2)
(3)
6
High Level Input Voltage
2.0
Typical values represent most likely parametric norms at VDD = 2.5V, TA = 25°C., and at the Recommended Operation Conditions at
the time of product characterization and are not guaranteed.
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not guaranteed.
Ensured by device characterization.
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Electrical Characteristics(1)(2)(3) (continued)
Symbol
Parameter
Vil
Low Level Input Voltage
Test Conditions
Voh
High Level Output Voltage
(ALL_DONE pin)
Ioh= −4mA
Vol
Low Level Output Voltage
(ALL_DONE pin)
Iol= 4mA
Iih
Input High Current (PWDN pin)
VIN = 3.6 V (pin 24),
Input under test = 3.6 V
Typ
0
Input High Current with internal
resistors
(4–level input pin)
Iil
Min
Input Low Current (PWDN pin)
VIN = 3.6 V (pin 24),
Input under test = 0 V
Input Low Current with internal
resistors
(4–level input pin)
Max
Unit
0.8
V
2.0
V
0.4
V
-15
+15
uA
+20
+150
uA
-15
+15
uA
-160
-40
uA
CML Receiver Inputs (IN_n+, IN_n-)
RLrx-diff
RX Differential return loss
0.05 - 7.5 GHz
-15
dB
7.5 - 15 GHz
-5
dB
-10
dB
RLrx-cm
RX Common mode return loss
0.05 - 5 GHz
Zrx-dc
RX DC common mode impedance
Tested at VDD = 2.5 V
40
50
60
Ω
Zrx-diff-dc
RX DC differntial mode impedance
Tested at VDD = 2.5 V
80
100
120
Ω
Vrx-diff-dc
Differential RX peak to peak voltage
(VID)
Tested at pins
0.6
1.0
1.2
V
Vrx-signal-det-diff-pp
Signal detect assert level for active
data signal
SD_TH = float,
0101 pattern at 12 Gbps
50
mVp-p
Vrx-idle-det-diff-pp
Signal detect de-assert level for
electrical idle
SD_TH = float,
0101 pattern at 12 Gbps
37
mVp-p
High Speed Outputs
Vtx-diff-pp
Output Voltage Differential Swing
Differential measurement with
OUT_n+ and OUT_n-,
terminated by 50Ω to GND,
AC-Coupled, VID = 1.0 Vp-p,
DEM0 = 1, DEM1 = 0 (4)
Vtx-de-ratio_3.5
TX de-emphasis ratio
VOD = 1.0 Vp-p,
DEM0 = 0, DEM1 = R,
Gen 1 and 2 modes only
-3.5
dB
Vtx-de-ratio_6
TX de-emphasis ratio
VOD = 1.0 Vp-p,
DEM0 = R, DEM1 = R
Gen1 and 2 modes only
-6
dB
TTX-HF-DJ-DD
TX Dj > 1.5 MHz
0.15
UI
TTX-LF-RMS
TX RMS jitter < 1.5 MHz
3.0
ps RMS
TTX-RISE-FALL
TX rise/fall time
20% to 80% of differential output
voltage
TRF-MISMATCH
TX rise/fall mismatch
20% to 80% of differential output
voltage
0.01
RLTX-DIFF
TX Differential return loss
0.05 - 7.5 GHz
-15
dB
7.5 - 15 GHz
-5
dB
0.05 - 5 GHz
-10
dB
RLTX-CM
TX Common mode return loss
ZTX-DIFF-DC
DC differential TX impedance
VTX-CM-AC-PP
TX AC peak-peak common mode
voltage
VOD = 1.0 Vp-p,
DEM0 = 1, DEM1 = 0
ITX-SHORT
TX short circuit current limit
Total current the transmitter can
supply when shorted to VDD or
GND
(4)
0.8
35
1.0
1.2
Vp-p
45
ps
0.1
UI
Ω
100
100
mVpp
20
mA
In SAS3 and GEN3 mode the output VOD level is not fixed. It will be adjusted automatically based on the VID input amplitude level. The
output VOD level set by DEMA/B[1:0] is dependent on the VID level and the frequency content. The DS125BR800A repeater in SAS3
and GEN3 mode is designed to be transparent, so the TX-FIR (de-emphasis) is passed to the RX to support link training.
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Electrical Characteristics(1)(2)(3) (continued)
Symbol
Parameter
Max
Unit
VTX-CM-DC-
Absolute delta of DC common mode
voltage during L0 and electrical idle
100
mV
Absolute delta of DC common mode
voltage between TX+ and TX-
25
mV
ACTIVE-IDLE-DELTA
VTX-CM-DC-LINEDELTA
Test Conditions
Min
Typ
TTX-IDLE-DATA
Max time to transition to differential
DATA signal after IDLE
VID = 1.0 Vp-p, 3 Gbps
3.5
ns
TTX-DATA-IDLE
Max time to transition to IDLE after
differential DATA signal
VID = 1.0 Vp-p, 3 Gbps
5.0
ns
TPLHD/PHLD
Differential Propagation Delay
EQ = 00 (5)
200
ps
TLSK
Lane to lane skew
T = 25C, VDD = 2.5V
25
ps
TPPSK
Part to part propagation delay skew
T = 25C, VDD = 2.5V
40
ps
DJE1
Residual deterministic jitter at 12 Gbps
30in 5mils FR4,
VID = 0.6 Vp-p,
PRBS15, EQ = 07'h,
DEM = 0 dB
0.18
UI
DJE2
Residual deterministic jitter at 8 Gbps
30in 5mils FR4,
VID = 0.6 Vp-p,
PRBS15,EQ = 07'h,
DEM = 0 dB
0.11
UI
DJE3
Residual deterministic jitter at 5 Gbps
30in 5mils FR4,
VID = 0.6 Vp-p,
PRBS15, EQ = 07'h,
DEM = 0 dB
0.07
UI
DJE4
Residual deterministic jitter at 12 Gbps
5m 30 awg cable,
VID = 0.6 Vp-p,
PRBS15, EQ = 07'h,
DEM = 0 dB
0.25
UI
DJE5
Residual deterministic jitter at 5 Gbps
8m 30 awg cable,
VID = 0.6 Vp-p,
PRBS15, EQ = 0F'h,
DEM = 0 dB
0.33
UI
Input Channel: 20in 5mils FR4,
Output Channel: 10in 5mils FR4
VID = 0.6 Vp-p,
PRBS15, EQ = 03'h,
VOD = 1.0 Vp-p,
DEM = −3.5 dB
0.1
UI
Equalization
De-emphasis (GEN 1,2 mode only)
DJD1
(5)
8
Residual deterministic jitter at 12 Gbps
Propagation Delay measurements will change slightly based on the level of EQ selected. EQ = 00 will result in the shortest propagation
delays.
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Electrical Characteristics — Serial Management Bus Interface
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
0.8
V
3.6
V
SERIAL BUS INTERFACE DC SPECIFICATIONS
VIL
Data, Clock Input Low Voltage
SDA and SCL
VIH
Data, Clock Input High Voltage
SDA and SCL
IPULLUP
Current Through Pull-Up Resistor
or Current Source
High Power Specification
VDD
Nominal Bus Voltage
ILEAK-Bus
Input Leakage Per Bus Segment
ILEAK-Pin
Input Leakage Per Device Pin
CI
Capacitance for SDA and SCL
(1) (2)
RTERM
External Termination Resistance
pull to VDD = 2.5V ± 5% OR 3.3V
± 10%
Pullup VDD = 3.3V (1)
(2) (3)
Pullup VDD = 2.5V (1)
(2) (3)
2.1
(1)
4
mA
2.375
3.6
V
-200
+200
µA
-15
µA
10
pF
2000
Ω
1000
Ω
SERIAL BUS INTERFACE TIMING SPECIFICATIONS
FSMB
Bus Operating Frequency
ENSMB = VDD (Slave Mode)
TBUF
Bus Free Time Between Stop and
Start Condition
THD:STA
Hold time after (Repeated) Start
Condition. After this period, the
first clock is generated.
ENSMB = FLOAT (Master Mode)
280
400
400
kHz
520
kHz
1.3
µs
0.6
µs
At IPULLUP, Max
TSU:STA
Repeated Start Condition Setup
Time
0.6
µs
TSU:STO
Stop Condition Setup Time
0.6
µs
THD:DAT
Data Hold Time
0
ns
TSU:DAT
Data Setup Time
100
ns
TLOW
Clock Low Period
THIGH
Clock High Period
(4)
tF
Clock/Data Fall Time
tR
Clock/Data Rise Time
tPOR
Time in which a device must be
operational after power-on reset
(1)
(2)
(3)
(4)
(5)
1.3
0.6
µs
50
µs
(4)
300
ns
(4)
300
ns
500
ms
(4) (5)
Recommended value.
Recommended maximum capacitance load per bus segment is 400pF.
Maximum termination voltage should be identical to the device supply voltage.
Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1
SMBus common AC specifications for details.
Ensured by Design. Parameter not tested in production.
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TIMING DIAGRAMS
(OUT+)
80%
80%
VOD (p-p) = (OUT+) ± (OUT-)
0V
20%
20%
(OUT-)
tRISE
tFALL
Figure 2. CML Output and Rise and FALL Transition Time
+
IN
0V
tPLHD
tPHLD
+
OUT
0V
-
Figure 3. Propagation Delay Timing Diagram
+
IN
0V
DATA
tDATA-IDLE
tIDLE-DATA
+
OUT
0V
DATA
IDLE
IDLE
Figure 4. Transmit IDLE-DATA and DATA-IDLE Response Time
tLOW
tR
tHIGH
SCL
tHD:STA
tBUF
tHD:DAT
tF
tSU:STA
tSU:DAT
tSU:STO
SDA
SP
ST
ST
SP
Figure 5. SMBus Timing Parameters
10
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FUNCTIONAL DESCRIPTION
The DS125BR800A compensates for lossy FR-4 printed circuit board backplanes and balanced cables. The
DS125BR800A operates in 3 modes: Pin Control Mode (ENSMB = 0), SMBus Slave Mode (ENSMB = 1) and
SMBus Master Mode (ENSMB = float) to load register information from external EEPROM; please refer to
SMBUS Master Mode for additional information.
Pin Control Mode:
When in pin mode (ENSMB = 0), equalization and de-emphasis can be selected via pin for each side
independently. When de-emphasis is asserted VOD is automatically adjusted per Table 4. For PCIe applications,
the RXDET pins provides automatic and manual control for input termination (50Ω or >50KΩ). MODE setting is
also pin controllable with pin selections (Gen 1/2, auto detect and SAS-3 / PCIe Gen 3). The receiver electrical
idle detect threshold is also adjustable via the SD_TH pin.
SMBUS Mode:
When in SMBus mode (ENSMB = 1), the VOD (output amplitude), equalization, de-emphasis, and termination
disable features are all programmable on a individual lane basis, instead of grouped by A or B as in the pin mode
case. Upon assertion of ENSMB, the EQx and DEMx functions revert to register control immediately. The EQx
and DEMx pins are converted to AD0-AD3 SMBus address inputs. The other external control pins (MODE,
RXDET and SD_TH) remain active unless their respective registers are written to and the appropriate override bit
is set, in which case they are ignored until ENSMB is driven low (pin mode). On power-up and when ENSMB is
driven low all registers are reset to their default state. If PWDN is asserted while ENSMB is high, the registers
retain their current state.
Equalization settings accessible via the pin controls were chosen to meet the needs of most PCIe applications. If
additional fine tuning or adjustment is needed, additional equalization settings can be accessed via the SMBus
registers. Each input has a total of 256 possible equalization settings. The tables show the 16 setting when the
device is in pin mode. When using SMBus mode, the equalization, VOD and de-Emphasis levels are set by
registers.
The 4-Level input pins utilize a resistor divider to help set the 4 valid levels and provide a wider range of control
settings when ENSMB=0. There is an internal 30K pull-up and a 60K pull-down connected to the package pin.
These resistors, together with the external resistor connection combine to achieve the desired voltage level.
Using the 1K pull-up, 1K pull-down, no connect, and 20K pull-down provide the optimal voltage levels for each of
the four input states.
Table 2. 4-Level Control Pin Settings
Level
Setting
3.3V Mode
2.5V Mode
0
Tie 1kΩ to GND
0.10 V
0.08 V
1/3 x VDD
R
Tie 20kΩ to GND
1/3 x VIN
Float
Float (leave pin open)
2/3 x VIN
2/3 x VDD
1
Tie 1kΩ to VDD
VIN - 0.05 V
VDD - 0.04 V
Typical 4-Level Input Thresholds
• Level 1 - 2 = 0.2 * VIN or VDD
• Level 2 - 3 = 0.5 * VIN or VDD
• Level 3 - 4 = 0.8 * VIN or VDD
In order to minimize the startup current associated with the integrated 2.5V regulator the 1K pull-up / pull-down
resistors are recommended. If several 4 level inputs require the same setting, it is possible to combine two or
more 1K resistors into a single lower value resistor. As an example; combining two inputs with a single 500 Ohm
resistor is a good way to save board space.
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3.3V or 2.5V Supply Mode Operation
The DS125BR800A has an optional internal voltage regulator to provide the 2.5V supply to the device. In 3.3V
mode operation, the VIN pin = 3.3V is used to supply power to the device. The internal regulator will provide the
2.5V to the VDD pins of the device and a 0.1 uF cap is needed at each of the 5 VDD pins for power supply decoupling (total capacitance should be ≤0.5 uF), and the VDD pins should be left open. The VDD_SEL pin must
be tied to GND to enable the internal regulator. In 2.5V mode operation, the VIN pin should be left open and 2.5V
supply must be applied to the 5 VDD pins to power the device. The VDD_SEL pin must be left open (no connect)
to disable the internal regulator.
3.3V mode
2.5V mode
VDD_SEL
Enable
VDD_SEL
open
VIN
open
Disable
3.3V
1 uF
VIN
10 uF
Internal
voltage
regulator
2.5V
VDD
VDD
0.1 uF
0.1 uF
VDD
VDD
0.1 uF
0.1 uF
1 uF
2.5V
Capacitors can be
either tantalum or an
ultra-low ESR seramic.
10 uF
Internal
voltage
regulator
Capacitors can be
either tantalum or an
ultra-low ESR seramic.
VDD
VDD
0.1 uF
0.1 uF
VDD
VDD
0.1 uF
0.1 uF
VDD
VDD
0.1 uF
0.1 uF
Place 0.1 uF close to VDD Pin
Total capacitance should be 7 0.5 uF
Place capcitors close to VDD Pin
Figure 6. 3.3V or 2.5V Supply Connection Diagram
PCIE SIGNAL INTEGRITY
When using the DS125BR800A in PCIe GEN-3 systems, there are specific signal integrity settings to ensure
signal integrity margin. The settings were achieved with completing extensive testing. Please contact your field
representative for more information regarding the testing completed to achieve these settings.
For tuning the in the downstream direction (from CPU to EP).
• EQ: use the guidelines outlined in Table 3.
• De-Emphasis: use the guidelines outlined in Table 4.
• VOD: use the guidelines outlined in Table 4.
For tuning in the upstream direction (from EP to CPU).
• EQ: use the guidelines outlined in Table 3.
• De-Emphasis:
– For trace lengths < 15" set to -3.5 dB
– For trace lengths > 15" set to -6 dB
• VOD: set to 900 mV
12
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Table 3. Equalizer Settings
Level
EQA1
EQB1
EQA0
EQB
EQ – 8 bits [7:0]
dB at
1.5 GHz
dB at
2.5 GHz
dB at
4 GHz
dB at
6 GHz
Suggested Use (1)
1
0
0
0000 0000 = 0x00
2.5
3.5
3.8
3.1
FR4 < 5 inch trace
2
0
R
0000 0001 = 0x01
3.8
5.4
6.7
6.7
FR4 5-10 inch trace
3
0
Float
0000 0010 = 0x02
5.0
7.0
8.4
8.4
FR4 10 inch trace
4
0
1
0000 0011 = 0x03
5.9
8.0
9.3
9.1
FR4 15-20 inch trace
5
R
0
0000 0111 = 0x07
7.4
10.3
12.8
13.7
FR4 20-30 inch trace
6
R
R
0001 0101 = 0x15
6.9
10.2
13.9
16.2
FR4 25-30 inch trace
7
R
Float
0000 1011 = 0x0B
9.0
12.4
15.3
15.9
FR4 25-30 inch trace
8
R
1
0000 1111 = 0x0F
10.2
13.8
16.7
17.0
8m, 30awg cable
9
Float
0
0101 0101 = 0x55
8.5
12.6
17.5
20.7
> 8m cable
10
Float
R
0001 1111 = 0x1F
11.7
16.2
20.3
21.8
11
Float
Float
0010 1111 = 0x2F
13.2
18.3
22.8
23.6
12
Float
1
0011 1111 = 0x3F
14.4
19.8
24.2
24.7
13
1
0
1010 1010 = 0xAA
14.4
20.5
26.4
28.0
14
1
R
0111 1111 = 0x7F
16.0
22.2
27.8
29.2
15
1
Float
1011 1111 = 0xBF
17.6
24.4
30.2
30.9
16
1
1
1111 1111 = 0xFF
18.7
25.8
31.6
31.9
(1)
Cable and FR4 lengths are for reference only. FR4 lengths based on a 100 Ohm differential stripline with 5-mil traces and 8-mil trace
separation. Optimal EQ setting should be determined via simulation and prototype verification.
Table 4. Output Voltage and De-emphasis Settings
(1)
(2)
Level
DEMA1
DEMB1
DEMA0
DEMB0
VOD Vp-p
DEM dB (1)
Inner Amplitude
Vp-p
Suggested Use (2)
1
0
0
0.8
0
0.8
FR4
