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Table of Contents
User’s Guide
DS160PR410EVM-RSC Evaluation Module (EVM)
Davor Glisic
ABSTRACT
The DS160PR410EVM-RSC and DS160PR410EVM-SMA evaluation modules provide a complete highbandwidth platform for evaluating the signal conditioning features of the Texas Instruments DS160PR410 QuadChannel PCI-Express Gen-4 Linear Redriver. These evaluation boards can be used for standard compliance
testing, performance evaluation, and initial system prototyping.
Figure 1-1. DS160PR410EVM-RSC - Top Side Photo
Table of Contents
1 Introduction.............................................................................................................................................................................3
1.1 Features............................................................................................................................................................................. 3
1.2 Applications........................................................................................................................................................................3
1.3 Description......................................................................................................................................................................... 3
1.4 Quick-Start Guide (Pin Mode)............................................................................................................................................ 8
1.5 Quick-Start Guide (SMBus Slave Mode)............................................................................................................................8
2 Test Setup and Results........................................................................................................................................................ 10
3 Board Layout......................................................................................................................................................................... 11
4 Schematics............................................................................................................................................................................12
5 Bill of Materials..................................................................................................................................................................... 20
6 References............................................................................................................................................................................ 24
7 Revision History................................................................................................................................................................... 24
List of Figures
Figure 1-1. DS160PR410EVM-RSC - Top Side Photo................................................................................................................ 1
Figure 1-1. SigCon Architect DS160PR410 High Level Page..................................................................................................... 9
Figure 2-1. Example Test Setup................................................................................................................................................ 10
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Trademarks
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Figure 2-2. Example Test Results..............................................................................................................................................10
Figure 3-1. Top Layer.................................................................................................................................................................11
Figure 3-2. Bottom Layer........................................................................................................................................................... 11
Figure 4-1. Top Level Schematic Page......................................................................................................................................12
Figure 4-2. Control and Status Schematic Page....................................................................................................................... 13
Figure 4-3. Voltage Regulator Schematic Page.........................................................................................................................14
Figure 4-4. Gold Finger Connector Schematic Page.................................................................................................................15
Figure 4-5. Downstream Devices Schematic Page................................................................................................................... 16
Figure 4-6. Upstream Devices Schematic Page........................................................................................................................17
Figure 4-7. Straddle Connector Schematic Page...................................................................................................................... 18
Figure 4-8. Hardware Page....................................................................................................................................................... 19
List of Tables
Table 1-1. 4-Level Control Pin Settings....................................................................................................................................... 3
Table 1-2. Modes of Operation.................................................................................................................................................... 3
Table 1-3. SMBus / I2C Slave Address Settings..........................................................................................................................4
Table 1-4. Equalization Control Settings......................................................................................................................................5
Table 1-5. 4-Level Control Pin Settings....................................................................................................................................... 5
Table 1-6. VOD Control................................................................................................................................................................6
Table 1-7. GAIN Control...............................................................................................................................................................6
Table 1-8. EVM Global Controls.................................................................................................................................................. 6
Table 1-9. EVM Downstream Devices Controls...........................................................................................................................7
Table 1-10. EVM Upstream Devices Controls............................................................................................................................. 7
Table 5-1. Bill of Materials..........................................................................................................................................................20
Trademarks
All trademarks are the property of their respective owners.
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Introduction
1 Introduction
The DS160PR410EVM-RSC evaluation module option features eight DS160PR410 linear redrivers that can
extend the transmission distance of a PCIe Gen-4 x16 bus. It can directly be plugged into a PCIe slot on a
Server / PC motherboard using one end of the board, and paired up with a PCIe Riser Card using the straddle
mount connector attached to the other end of the board.
The DS160PR410EVM-SMA evaluation board option features a single, standalone DS160PR410 device with
the high-speed I/Os routed to SMA connectors. The SMA connectors can interface to multiple connector types
through commercially available breakout cables, adaptors, and boards (not included).
This document describes the DS160PR410EVM-RSC evaluation module.
1.1 Features
•
•
•
•
•
•
•
PCIe x16 Riser Card option with eight 4-channel unidirectional linear redrivers operating at rates up to 25
Gbps
Linear equalization for seamless support of link training and PCIe channel extension
CTLE boosts up to 18 dB at 8 GHz
Programmable device configuration through GPIO or I2C / SMBus
Onboard 12-V to 3.3-V, 2-A step-down DC-DC converter
Industrial temperature range: –40°C to 85°C
Flow-through layout in 4 mm × 6 mm, 40-pin, leadless WQFN 0.4-mm pitch package
1.2 Applications
•
•
•
•
•
PCI Express Gen-1, 2, 3, and 4
High-speed interfaces up to 25 Gbps
Enterprise server motherboard, workstation
Enterprise storage
Enterprise add-in card, end-point
1.3 Description
1.3.1 DS160PR410 4-Level I/O Control Inputs
Each DS160PR410 has six (GAIN, VOD, EQ1_ADDR1, EQ0_ADDR0, EN_SMB, and RX_DET) 4-level input
pins that are used to control the configuration of the device. These 4-level inputs use a resistor divider to help set
the four valid levels and provide a wider range of control settings.
Table 1-1. 4-Level Control Pin Settings
PIN LEVEL
PIN SETTING
L0
1 kΩ to GND
L1
13 kΩ to GND
L2
Float
L3
59 kΩ to GND
1.3.2 DS160PR410 Modes of Operation
Each DS160PR410 can be configured to operate in either Pin Mode, SMBus / I2C Slave Mode, or SMBus / I2C
Master Mode. The mode of operation of the DS160PR410 is determined by the pin strap setting on the EN_SMB
pin as shown in Table 1-2.
Table 1-2. Modes of Operation
EN_SMB PIN LEVEL
MODE OF OPERATION
L0
Pin Mode
L1
SMBus / I2C Master Mode
L2
Reserved
L3
SMBus / I2C Slave Mode
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1.3.3 DS160PR410 SMBus / I2C Register Control Interface
Each DS160PR410 may be configured through a standard I2C or SMBus interface that may operate up to 1
MHz. The slave address of the DS160PR410 is determined by the pin strap settings on the EQ1_ADDR1 and
EQ0_ADDR0 pins. The device can be configured for best signal integrity and power settings in the system using
the I2C or SMBus interface. Certain status information is also available through this interface. The possible
SMBus/I2C slave addresses are shown in Table 1-3.
Table 1-3. SMBus / I2C Slave Address Settings
4
EQ1_ADDR1 PIN LEVEL
EQ0_ADDR0 PIN LEVEL
8-BIT WRITE ADDRESS (HEX)
7-BIT ADDRESS (HEX)
L0
L0
0x30
0x18
L0
L1
0x32
0x19
L0
L2
0x34
0x1A
L0
L3
0x36
0x1B
L1
L0
0x38
0x1C
L1
L1
0x3A
0x1D
L1
L2
0x3C
0x1E
L1
L3
0x3E
0x1F
L2
L0
0x40
0x20
L2
L1
0x42
0x21
L2
L2
0x44
0x22
L2
L3
0x46
0x23
L3
L0
0x48
0x24
L3
L1
0x4A
0x25
L3
L2
0x4C
0x26
L3
L3
0x4E
0x27
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1.3.4 DS160PR410 Equalization Control
Each channel of the DS160PR410 features a continuous-time linear equalizer (CTLE) that applies highfrequency boost and low-frequency attenuation to help equalize the frequency-dependent insertion loss effects
of the passive channel. Table 1-4 shows available equalization gain that can be set through EQ0_ADDR0 and
EQ1_ADDR1 control pins when operating in Pin Mode.
Table 1-4. Equalization Control Settings
EQ INDEX
EQ1_ADDR1 PIN LEVEL
EQ0_ADDR0 PIN LEVEL
CTLE BOOST AT 4 GHz
(dB)
CTLE BOOST AT 8 GHz
(dB)
0
L0
L0
–0.3
–0.8
1
L0
L1
0.4
1.3
2
L0
L2
3.3
5.7
3
L0
L3
3.8
7.1
4
L1
L0
4.9
8.4
5
L1
L1
5.2
9.1
6
L1
L2
5.4
9.8
7
L1
L3
6.5
10.7
8
L2
L0
6.7
11.3
9
L2
L1
7.7
12.6
10
L2
L2
8.7
13.6
11
L2
L3
9.1
14.4
12
L3
L0
9.4
15.0
13
L3
L1
10.3
15.9
14
L3
L2
10.6
16.5
15
L3
L3
11.8
17.8
The equalization gain of each channel of each device can also be set by writing to SMBus / I2C registers in
Slave or Master Modes. Refer to the DS160PR410 Programming Guide (SNLU255) for details.
1.3.5 DS160PR410 RX Detect State Machine
Each DS160PR410 deploys an RX Detect state machine that governs the RX detection cycle as defined in the
PCI Express specification. At power up or after a manually triggered event, the redriver determines whether
or not a valid PCI Express termination is present at the far end of the link. The RX_DET pin of DS160PR410
provides additional flexibility to system designers to appropriately set the device in their desired mode, according
to Table 1-5.
Table 1-5. 4-Level Control Pin Settings
PWDN PIN LEVEL
RXDET PIN LEVEL
DESCRIPTION
L
L0
Reserved
L
L1
Reserved
L
L2
PCI Express RX detection state machine is
enabled. Recommended for PCI Express use
cases. Pre Detect: Hi-Z, Post Detect: 50 Ω.
L
L3
PCI Express RX detection state machine is
disabled. Recommended for non-PCI Express use
cases. Inputs are always 50 Ω.
H
X
Manual reset, inputs are Hi-Z
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1.3.6 DS160PR410 Equalization DC Gain Control
When operating in Pin Mode, the VOD and GAIN pins can be used to set the overall datapath DC (low
frequency) gain of the DS160PR410 as shown in Table 1-6 and Table 1-7.
Table 1-6. VOD Control
VOD PIN LEVEL
VOD SETTING
L0
–6 dB
L1
–3.5 dB
L2
0 dB (Recommended for most use cases)
L3
–1.6 dB
Table 1-7. GAIN Control
GAIN PIN LEVEL
GAIN SETTING
L0
Reserved
L1
Reserved
L2
0 dB (Recommended for most use cases)
L3
3.5 dB
The DC gain of each channel of each device can also be set by writing to SMBus / I2C registers in Slave or
Master Modes. Refer to the DS160PR410 Programming Guide (SNLU255) for details.
1.3.7 DS160PR410EVM-RSC Global Controls and Access Points
Table 1-8 shows DS160PR410EVM-RSC global controls that affect all devices on the board.
Table 1-8. EVM Global Controls
COMPONENT
6
NAME
FUNCTION / DESCRIPTION
J1
3x2 Header
EN_SMB control tied to EN_SMB pins of all 8 DS160PR410 devices on the EVM
L0: All devices set to Pin Mode (Default)
L1: All devices set to SMBus / I2C Master Mode
L2: Reserved
L3: SMBus / I2C Slave Mode
J2
5x2 Header
SMBus / I2C interface. All 8 DS160PR410 devices on the EVM are on the same
bus and can be accessed through this interface.
J3
3x1 Header
PWDN control tied to PWDN1 and PWDN2 pins of all 8 DS160PR410 devices on
the EVM
PWDN tied to GND: All devices enabled (Default)
PWDN tied to 3.3V_REG: All devices disabled.
PWDN floating: Tie PCIe system PRSNT signal to PWDN using J5 for the PWDN
control (optional for PCIe use case)
J4
3x1 Header
Access point to the WP (write protect) pin of the onboard EEPROM devices
WP tied to GND: I2C Access to the EEPROM enabled
WP floating: I2C Access to the EEPROM disabled (default)
J5
2x1 Header
Alternative PWDN Control
PWDN floating: Use J3 for the PWDN control
PWDN tied to PRSNT: PRSNT signal controls PWDN (optional for PCIe use case)
J6, J7, J8, J9
3x1 Headers
PCIe PRSNT Signal Controls
Tie pins 1-2 on J6, J7, J8, and J9: Allow support any PCIe bus width (default)
Tie pins 2-3 of J6, leave J7, J8, and J9 floating: Force x1 PCIe bus width
Tie pins 2-3 of J7, leave J6, J8, and J9 floating: Force x4 PCIe bus width
Tie pins 2-3 of J8, leave J6, J7, and J9 floating: Force x8 PCIe bus width
Tie pins 2-3 of J9, leave J6, J7, and J8 floating: Force x16 PCIe bus width
J10
2x1 Header
Onboard regulator input. Apply 12 V when using the EVM as a standalone system.
DO NOT APPLY power if plugging the EVM into a system as the power is provided
through the gold finger connector (J13).
J11
2x1 Header
Onboard regulator 3.3-V output.
J12
2x1 Header
Access point to the GND reference.
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1.3.8 DS160PR410EVM-RSC Downstream Devices Control
Table 1-9 shows DS160PR410EVM-RSC downstream devices controls that affect DS1-DS4 devices on the
board.
Table 1-9. EVM Downstream Devices Controls
COMPONENT
J14
J15
J16
NAME
FUNCTION / DESCRIPTION
12x2 Header
EQ1_ADDR1 controls for each downstream device.
Use pins 1-6 for configuring EQ1_ADDR1 pin of DS1 device.
Use pins 7-12 for configuring EQ1_ADDR1 pin of DS2 device.
Use pins 13-18 for configuring EQ1_ADDR1 pin of DS3 device.
Use pins 19-24 for configuring EQ1_ADDR1 pin of DS4 device.
Install a shunt to achieve L0, L1, or L3 level on the pin. Leave floating to achieve
L2 level on the pin.
12x2 Header
EQ0_ADDR0 controls for each downstream device.
Use pins 1-6 for configuring EQ0_ADDR0 pin of DS1 device.
Use pins 7-12 for configuring EQ0_ADDR0 pin of DS2 device.
Use pins 13-18 for configuring EQ0_ADDR0 pin of DS3 device.
Use pins 19-24 for configuring EQ0_ADDR0 pin of DS4 device.
Install a shunt to achieve L0, L1, or L3 level on the pin. Leave floating to achieve
L2 level on the pin.
5x2 Header
Downstream Devices Global Controls
VOD: L0 (pins 1-2): –6 dB VOD Setting on all downstream devices
VOD: L1 (pins 3-4): –3.5 dB VOD Setting on all downstream devices
VOD: L2 (floating pins 1-6): 0 dB VOD Setting on all downstream devices (default)
VOD: L3 (pins 5-6): –1.6 dB VOD Setting on all downstream devices
GAIN: L2 (floating pins 7-8): 0 dB GAIN Setting on all downstream devices (default)
GAIN: L3 (pins 7-8): 3.5 dB GAIN Setting on all downstream devices
RX_DET: L2 (floating pins 9-10):RX Detect state machine enabled on all
downstream devices (default)
RX_DET: L3 (pins 9-10): RX Detect state machine disabled on all downstream
devices
Install a shunt to achieve L0, L1, or L3 level on the pin. Leave floating to achieve
L2 level on the pin.
1.3.9 DS160PR410EVM-RSC Upstream Devices Control
Table 1-10 shows DS160PR410EVM-RSC upstream devices controls that affect US1-US4 devices on the board.
Table 1-10. EVM Upstream Devices Controls
COMPONENT
J17
J18
NAME
FUNCTION / DESCRIPTION
12x2 Header
EQ1_ADDR1 controls for each upstream device.
Use pins 1-6 for configuring EQ1_ADDR1 pin of US1 device.
Use pins 7-12 for configuring EQ1_ADDR1 pin of US2 device.
Use pins 13-18 for configuring EQ1_ADDR1 pin of US3 device.
Use pins 19-24 for configuring EQ1_ADDR1 pin of US4 device.
Install a shunt to achieve L0, L1, or L3 level on the pin. Leave floating to achieve
L2 level on the pin.
12x2 Header
EQ0_ADDR0 controls for each upstream device.
Use pins 1-6 for configuring EQ0_ADDR0 pin of US1 device.
Use pins 7-12 for configuring EQ0_ADDR0 pin of US2 device.
Use pins 13-18 for configuring EQ0_ADDR0 pin of US3 device.
Use pins 19-24 for configuring EQ0_ADDR0 pin of US4 device.
Install a shunt to achieve L0, L1, or L3 level on the pin. Leave floating to achieve
L2 level on the pin.
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Table 1-10. EVM Upstream Devices Controls (continued)
COMPONENT
J19
NAME
FUNCTION / DESCRIPTION
Upstream Devices Global Controls
VOD: L0 (pins 1-2): –6 dB VOD Setting on all upstream devices
VOD: L1 (pins 3-4): –3.5 dB VOD Setting on all upstream devices
VOD: L2 (floating pins 1-6): 0 dB VOD Setting on all upstream devices (default)
VOD: L3 (pins 5-6): –1.6 dB VOD Setting on all upstream devices
GAIN: L2 (floating pins 7-8): 0 dB GAIN Setting on all upstream devices (default)
GAIN: L3 (pins 7-8): 3.5 dB GAIN Setting on all upstream devices
RX_DET: L2 (floating pins 9-10):RX Detect state machine enabled on all upstream
devices (default)
RX_DET: L3 (pins 9-10): RX Detect state machine disabled on all upstream
devices
Install a shunt to achieve L0, L1, or L3 level on the pin. Leave floating to achieve
L2 level on the pin.
5x2 Header
1.4 Quick-Start Guide (Pin Mode)
1. Check that the shunts are at the following positions as shown in Figure 1-1.
• The redrivers are configured to operate in Pin Mode (EN_SMB pins tied to L0 using J1 header).
• The redrivers are enabled (PWDN pins tied to GND using J3 header). Alternatively, for PCIe applications,
the PWDN pins may be driven by PCIe Present (PRSNT) signal by leaving J3 open and placing a shunt
across pins 1 and 2 of J5.
• The board is configured for any PCIe bus width (PRSNT signal controls set as shown in Figure 1-1 using
J6, J7, J8, and J9 headers).
• DC Gain of the RX CTLEs of all redrivers is set to 0 dB by leaving J16 (pins 7-8) open for the
downstream redrivers and by leaving J19 (pins 7-8) open for the upstream redrivers.
• VOD of all redrivers is set to 0 dB by leaving J16 (pins 1-2, 3-4, and 5-6) open for the downstream
redrivers and by leaving J19 (pins 1-2, 3-4, and 5-6) open for the upstream redrivers.
• RX_Detect state machine of all redrivers is enabled by leaving J16 (pins 9-10) open for the downstream
redrivers and by leaving J19 (pins 9-10) open for the upstream redrivers.
• EQ level of the RX CTLEs of all redrivers is set to 8.4 dB at 8 GHz by using J14 and J15 for the
downstream redrivers, and J17 and J18 for the upstream redrivers.
2. If necessary, adjust EQ levels of the downstream and/or upstream redrivers by arranging shunts on J14 and
J15 for the downstream redrivers, and J17 and J18 for the upstream redrivers.
3. Plug the EVM into a PCIe x16 server motherboard slot.
4. Install a compatible PCIe end point card into the EVM's straddle connector.
1.5 Quick-Start Guide (SMBus Slave Mode)
1. Configure all devices to operate in the SMBus Slave Mode by setting their EN_SMB pins to the L3 level. This
is accomplished by placing a shunt on J1 to L3 location.
2. Set a unique SMBus Slave address for each device by placing shunts in the following arrangement:
• On J14 connector, place shunts in L0 locations for all downstream devices (DS1-DS4).
• On J15 connector, place a shunt to L0 location for the device DS1, to L1 location for DS2, to L3 location
for DS4; no shunt for the DS3 sets its EQ0_ADD0 pin to the L2 level.
• On J17 connector, place shunts in L1 locations for all upstream devices (US1-US4).
• On J18 connector, place a shunt to L0 location for the device US1, to L1 location for US2, to L3 location
for US4; no shunt for the US3 sets its EQ0_ADD0 pin to the L2 level.
3. Enable all devices by pulling their PWDN pins to GND. This is accomplished by placing a shunt on J3
between PWDN and GND.
4. Connect USB2ANY Adapter to J2 (Note that the USB2ANY Adapter is not supplied with the
DS160PR410EVM-RSC).
5. Install SigCon Architect Version 3.0.0.10 application. It comes with the DS160PR410 profile.
6. Plug the EVM into a PCIe x16 server motherboard slot.
7. Install a compatible PCIe end point card into the EVM' s straddle connector.
8. Start the SigCon Architect application.
9. In the DS160PR410 Configuration Page, click on "Auto Detect" box to detect the EVM Model. If necessary,
edit devices addresses in the Edit Device Addresses box.
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Introduction
10. Select Low Level Page to initialize the register map tree in the application. Failure to perform this step may
cause the application to crash.
11. In the DS160PR410 High Level Page, select Block Diagram as shown in Figure 1-1.
12. Select desired EQ Settings and Driver VOD.
13. Select device(s) to which you want to apply the selected settings and click Apply to All Channels.
Figure 1-1. SigCon Architect DS160PR410 High Level Page
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2 Test Setup and Results
Figure 2-1 shows a typical system setup with the DS160PR410EVM-RSC placed between a CPU on a server
motherboard and an PCIe end point (Network Interface Card or NIC). Additional "Extender" cards are inserted to
increase the channel loss and demonstrate the redriver's ability to extend the reach.
NIC
6´ ([WHQGHU &DUG
10´ ([WHQGHU &DUG
DS160PR410 Riser Card
PCIe Gen - 4 CPU
Server Motherboard
8´ ([WHQGHU &DUG
Figure 2-1. Example Test Setup
Figure 2-2 is a typical test result achieved with a system shown in Figure 2-1. As the result indicates, the end
point (Mellanox NIC) with the DS160PR410EVM-RSC placed in the datapath achieves a stable Gen4, x16 PCIe
link.
Figure 2-2. Example Test Results
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Board Layout
3 Board Layout
Figure 3-1. Top Layer
Figure 3-2. Bottom Layer
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4 Schematics
CoverSheet
HSDC058A_CoverSheet.SchDoc
U_HSDC058A_GoldFinger_Conn
HSDC058A_GoldFinger_Conn.SchDoc
PERST#
REFCLK_P
REFCLK_N
SMCLK
SMDAT
PERST#
REFCLK_P
REFCLK_N
SMCLK
SMDAT
Hardware
HSDC058A_Hardware.SchDoc
WAKE
CLKREQ
JTAG1
JTAG2
JTAG3
JTAG4
JTAG5
VoltageRegulator
HSDC058A_VoltageRegulator.SchDoc
RSVD
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
PGOOD
PGOOD
WAKE
CLKREQ
JTAG1
JTAG2
JTAG3
JTAG4
JTAG5
RSVD
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
PET0_P
PET0_N
PET1_P
PET1_N
PET2_P
PET2_N
PET3_P
PET3_N
PET4_P
PET4_N
PET5_P
PET5_N
PET6_P
PET6_N
PET7_P
PET7_N
PET8_P
PET8_N
PET9_P
PET9_N
PET10_P
PET10_N
PET11_P
PET11_N
PET12_P
PET12_N
PET13_P
PET13_N
PET14_P
PET14_N
PET15_P
PET15_N
HSDC058A_4x_DS
HSDC058A_4x_DS.SchDoc
PET0_P
PET0_N
PET1_P
PET1_N
PET2_P
PET2_N
PET3_P
PET3_N
PET4_P
PET4_N
PET5_P
PET5_N
PET6_P
PET6_N
PET7_P
PET7_N
PET8_P
PET8_N
PET9_P
PET9_N
PET10_P
PET10_N
PET11_P
PET11_N
PET12_P
PET12_N
PET13_P
PET13_N
PET14_P
PET14_N
PET15_P
PET15_N
PET0_P
PET0_N
PET1_P
PET1_N
PET2_P
PET2_N
PET3_P
PET3_N
PET4_P
PET4_N
PET5_P
PET5_N
PET6_P
PET6_N
PET7_P
PET7_N
PET8_P
PET8_N
PET9_P
PET9_N
PET10_P
PET10_N
PET11_P
PET11_N
PET12_P
PET12_N
PET13_P
PET13_N
PET14_P
PET14_N
PET15_P
PET15_N
PWDN
ENSMB
SDA
SCL
READ_EN_N
PRSNT1
PRSNT2_1
PRSNT2_2
PRSNT2_3
PRSNT2_4
PRSNT2_1_C
PRSNT2_2_C
PRSNT2_3_C
PRSNT2_4_C
SMDAT
SMCLK
PGOOD
PRSNT1
PRSNT2_1
PRSNT2_2
PRSNT2_3
PRSNT2_4
PWDN
ENSMB
PRSNT2_1_C
PRSNT2_2_C
PRSNT2_3_C
PRSNT2_4_C
SDA
SCL
READ_EN_N
ALL_DONE_N
PRSNT1
PRSNT2_1
PRSNT2_2
PRSNT2_3
PRSNT2_4
PWDN
ENSMB
SDA
SCL
READ_EN_N
ALL_DONE_N
U_HSDC058A_SMA_Card
HSDC058A_SMA_Card.SchDoc
PWDN
ENSMB
SDA
SCL
PWDN
ENSMB
ALL_DONE_N_SA1
SDA
SCL
ALL_DONE_N_DS
PET0_C_P
PET0_C_N
PET1_C_P
PET1_C_N
PET2_C_P
PET2_C_N
PET3_C_P
PET3_C_N
PET4_C_P
PET4_C_N
PET5_C_P
PET5_C_N
PET6_C_P
PET6_C_N
PET7_C_P
PET7_C_N
PET8_C_P
PET8_C_N
PET9_C_P
PET9_C_N
PET10_C_P
PET10_C_N
PET11_C_P
PET11_C_N
PET12_C_P
PET12_C_N
PET13_C_P
PET13_C_N
PET14_C_P
PET14_C_N
PET15_C_P
PET15_C_N
ALL_DONE_N_DS
PERST#
REFCLK_P
REFCLK_N
SMCLK
SMDAT
WAKE
CLKREQ
JTAG1
JTAG2
JTAG3
JTAG4
JTAG5
RSVD
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
PERST#
REFCLK_P
REFCLK_N
SMCLK
SMDAT
WAKE
CLKREQ
JTAG1
JTAG2
JTAG3
JTAG4
JTAG5
RSVD
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
READ_EN_N
HSDC058A_4x_US
HSDC058A_4x_US.SchDoc
U_HSDC058A_Control_Status
HSDC058A_Control_Status.SchDoc
SMDAT
SMCLK
PWDN
ENSMB
SDA
SCL
U_HSDC058A_Straddle_Conn
HSDC058A_Straddle_Conn.SchDoc
PET0_C_P
PET0_C_N
PET1_C_P
PET1_C_N
PET2_C_P
PET2_C_N
PET3_C_P
PET3_C_N
PET4_C_P
PET4_C_N
PET5_C_P
PET5_C_N
PET6_C_P
PET6_C_N
PET7_C_P
PET7_C_N
PET8_C_P
PET8_C_N
PET9_C_P
PET9_C_N
PET10_C_P
PET10_C_N
PET11_C_P
PET11_C_N
PET12_C_P
PET12_C_N
PET13_C_P
PET13_C_N
PET14_C_P
PET14_C_N
PET15_C_P
PET15_C_N
PET0_C_P
PET0_C_N
PET1_C_P
PET1_C_N
PET2_C_P
PET2_C_N
PET3_C_P
PET3_C_N
PET4_C_P
PET4_C_N
PET5_C_P
PET5_C_N
PET6_C_P
PET6_C_N
PET7_C_P
PET7_C_N
PET8_C_P
PET8_C_N
PET9_C_P
PET9_C_N
PET10_C_P
PET10_C_N
PET11_C_P
PET11_C_N
PET12_C_P
PET12_C_N
PET13_C_P
PET13_C_N
PET14_C_P
PET14_C_N
PET15_C_P
PET15_C_N
READ_EN_N
R1
DNP
0
ALL_DONE_N
PRSNT1
PRSNT2_1
PRSNT2_2
PRSNT2_3
PRSNT2_4
PER0_C_P
PER0_C_N
PER1_C_P
PER1_C_N
PER2_C_P
PER2_C_N
PER3_C_P
PER3_C_N
PER4_C_P
PER4_C_N
PER5_C_P
PER5_C_N
PER6_C_P
PER6_C_N
PER7_C_P
PER7_C_N
PER8_C_P
PER8_C_N
PER9_C_P
PER9_C_N
PER10_C_P
PER10_C_N
PER11_C_P
PER11_C_N
PER12_C_P
PER12_C_N
PER13_C_P
PER13_C_N
PER14_C_P
PER14_C_N
PER15_C_P
PER15_C_N
PER0_C_P
PER0_C_N
PER1_C_P
PER1_C_N
PER2_C_P
PER2_C_N
PER3_C_P
PER3_C_N
PER4_C_P
PER4_C_N
PER5_C_P
PER5_C_N
PER6_C_P
PER6_C_N
PER7_C_P
PER7_C_N
PER8_C_P
PER8_C_N
PER9_C_P
PER9_C_N
PER10_C_P
PER10_C_N
PER11_C_P
PER11_C_N
PER12_C_P
PER12_C_N
PER13_C_P
PER13_C_N
PER14_C_P
PER14_C_N
PER15_C_P
PER15_C_N
PER0_C_P
PER0_C_N
PER1_C_P
PER1_C_N
PER2_C_P
PER2_C_N
PER3_C_P
PER3_C_N
PER4_C_P
PER4_C_N
PER5_C_P
PER5_C_N
PER6_C_P
PER6_C_N
PER7_C_P
PER7_C_N
PER8_C_P
PER8_C_N
PER9_C_P
PER9_C_N
PER10_C_P
PER10_C_N
PER11_C_P
PER11_C_N
PER12_C_P
PER12_C_N
PER13_C_P
PER13_C_N
PER14_C_P
PER14_C_N
PER15_C_P
PER15_C_N
PWDN
ENSMB
SDA
SCL
READ_EN_N
ALL_DONE_N_DS
PER0_P
PER0_N
PER1_P
PER1_N
PER2_P
PER2_N
PER3_P
PER3_N
PER4_P
PER4_N
PER5_P
PER5_N
PER6_P
PER6_N
PER7_P
PER7_N
PER8_P
PER8_N
PER9_P
PER9_N
PER10_P
PER10_N
PER11_P
PER11_N
PER12_P
PER12_N
PER13_P
PER13_N
PER14_P
PER14_N
PER15_P
PER15_N
PER0_P
PER0_N
PER1_P
PER1_N
PER2_P
PER2_N
PER3_P
PER3_N
PER4_P
PER4_N
PER5_P
PER5_N
PER6_P
PER6_N
PER7_P
PER7_N
PER8_P
PER8_N
PER9_P
PER9_N
PER10_P
PER10_N
PER11_P
PER11_N
PER12_P
PER12_N
PER13_P
PER13_N
PER14_P
PER14_N
PER15_P
PER15_N
PER0_P
PER0_N
PER1_P
PER1_N
PER2_P
PER2_N
PER3_P
PER3_N
PER4_P
PER4_N
PER5_P
PER5_N
PER6_P
PER6_N
PER7_P
PER7_N
PER8_P
PER8_N
PER9_P
PER9_N
PER10_P
PER10_N
PER11_P
PER11_N
PER12_P
PER12_N
PER13_P
PER13_N
PER14_P
PER14_N
PER15_P
PER15_N
PRSNT1
PRSNT2_1_C
PRSNT2_2_C
PRSNT2_3_C
PRSNT2_4_C
PRSNT1
PRSNT2_1_C
PRSNT2_2_C
PRSNT2_3_C
PRSNT2_4_C
PWDN
ENSMB
SDA
SCL
ALL_DONE_N_DS
ALL_DONE_N
ALL_DONE_N
Figure 4-1. Top Level Schematic Page
12
DS160PR410EVM-RSC Evaluation Module (EVM)
SNLU252B – JANUARY 2020 – REVISED JULY 2021
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Copyright © 2021 Texas Instruments Incorporated
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Board Layout
J1
J5
2 R6
4 R7
6 R8
1
3
5
ENSMB
124
1.62k
7.32k
PRSNT1
PWDN
PRSNT1
3_3V_REG
U1
J2
SCL
SCL
1
3
5
7
9
2
4
6
8
10
GND
SDA
SDA
GND
J6
1
A0
VCC
8
2
A1
WP
7
EEPROM_WP
C1
3
A2
SCL
6
SCL
1uF
4
VSS
SDA
5
SDA
GND
PRSNT2_1_C
PRSNT2_1
1
2
3 PRSNT1
PRSNT2_2_C
PRSNT2_2
J7
AT24C02D-SSHM-T
GND
J3
J8
1
2
3 PRSNT1
1
2
3 PRSNT1
PRSNT2_3_C
PRSNT2_3
1
2
3 PRSNT1
PRSNT2_4_C
PRSNT2_4
J9
3_3V_REG
1
2
3
PWDN
PWDN
GND
3_3V_REG
J4
R9
1
2
3
249
EEPROM_WP
3_3V_REG
GND
R115
4.70k
U2E
3_3V_REG
14
VCC
GND
7
READ_EN_N
SW1
C2
1uF
GND
1 U2A
PGOOD
3_3V_REG
SMDAT
R2
DNP
0
2
ALL_DONE_N
6
SMCLK
1
R12
GND
D2
1
2
330
10
3_3V_REG
U2C
9
R3
DNP
0
2
U2B
5
SDA
D3
8
R13
2
1
330
3_3V_REG
3_3V_REG
R11
330
4
R4
2.2k
D1
3
GND
R5
2.2k
13
SCL
12
U2D
11
R10
10.0k
GND
GND
Figure 4-2. Control and Status Schematic Page
SNLU252B – JANUARY 2020 – REVISED JULY 2021
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DS160PR410EVM-RSC Evaluation Module (EVM)
Copyright © 2021 Texas Instruments Incorporated
13
Board Layout
www.ti.com
J10
12V+/-20%
12V
U3
28
R14
165k
C4
C5
C6
C7
C8
100uF
22uF
22uF
4.7uF
1uF
21
22
23
24
25
R15
120k
4
GND
PVIN
PVIN
PVIN
PVIN
PVIN
35
PGOOD
34
MODE
C17
32
FS EL
4.7uF
33
VSEL
36
ILIM
37
RESV_TRK
R22
165k
R19
100k
R23
37.4k
R20
100k
R17
105k
R24
42.2k
R25
2.05k
PGOOD
1
NU
2
NU
3
NU
29
30
DRGND
AGND
TPS548B22RVFR
40
VSENSE trace goes to furthest DS160PR410
3_3V_REG
J11
3.3V, 2A MAX
5
C3
PGOOD
SW
SW
SW
SW
SW
8
9
10
11
12
NC
NC
NC
NC
6
7
26
27
RSP
39
RSN
38
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
13
14
15
16
17
18
19
20
PAD
41
EN_UVLO
BP
R18
100k
VOSNS
BOOT
31
J12
GND
VDD
0.1uF
PGOOD
L1
3_3V_REG
6.8uH
R16
10.0k
C9
C10
C11
C12
C13
C14
C15
C16
100uF
100uF
47uF
10uF
4.7uF
1µF
470nF
100nF
R21
5.76k
GND
Figure 4-3. Voltage Regulator Schematic Page
14
DS160PR410EVM-RSC Evaluation Module (EVM)
SNLU252B – JANUARY 2020 – REVISED JULY 2021
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Copyright © 2021 Texas Instruments Incorporated
PRSNT2_2
C50
PRSNT2_3
C53
PRSNT2_4
C56
1pF
1pF
1pF
R26
R29
R32
GND
43
43
43
RSVD5
C51
C54
C57
C59
1pF
RSVD2
1pF
RSVD3
1pF
RSVD4
1pF
R27
R30
43
R33
43
GND
43
C60
RSVD
C52
1pF
CLKREQ
C55
1pF
43
PRSNT2_1
C58
1pF
R35
RSVD1
1pF
P ET8_P
SNLU252B – JANUARY 2020 – REVISED JULY 2021
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Copyright © 2021 Texas Instruments Incorporated
DS160PR410EVM-RSC Evaluation Module (EVM)
RS VD
GND
P RS NT2_4
P ET15_N
GND
P ET15_P
P ET14_N
GND
P ET14_P
P ET13_N
GND
P ET13_P
P ET12_N
GND
P ET12_P
P ET11_N
GND
P ET11_P
P ET10_N
GND
P ET10_P
P ET9_N
GND
P ET9_P
GND
P ET8_N
B82
RS VD
B80
B79
B78
B77
B76
B75
B74
B73
B72
B71
B70
B69
B68
B67
B66
B65
B64
B63
B62
B61
B60
B59
B58
B57
B56
B55
B54
B53
B52
B51
B50
B49
B48
B47
B46
B45
B44
B43
B42
B41
B40
B39
B38
B37
B36
B35
B34
B33
B32
B31
B30
B29
B28
B27
B26
B25
B24
B23
B22
B21
B20
B19
B18
B17
B16
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B81
GND
P RS NT2_4
P RS NT2_3
GND
P RS NT2_3
P ET7_N
GND
P ET7_P
P ET6_N
GND
P ET6_P
P ET5_N
GND
P ET5_P
P ET4_N
GND
P ET4_P
P RS NT2_2
P RS NT2_2
RS VD2
GND
RS VD2
P ET3_N
GND
P ET3_P
P ET2_N
GND
P ET2_P
GND
P ET1_P
GND
P ET1_N
P RS NT2_1
GND
P RS NT2_1
P ET0_N
12V
P ET0_P
3_3VAUX
CLKREQ
3_3V
CLKREQ
GND
B3
TOP
BOT
0.22uF
C42
GND
0.22uF
C44
GND
0.22uF
C46
GND
0.22uF
C48
0.22uF
C49
GND
A82
A81
A80
A79
0.22uF
C47
GND
A78
A77
A76
A75
0.22uF
C45
GND
A74
A73
A72
A71
0.22uF
C43
GND
A70
A69
A68
GND
A67
C40
0.22uF
C41
GND
0.22uF
A66
A65
A64
GND
A63
C38
0.22uF
C39
GND
0.22uF
A62
A61
A60
GND
A59
C36
0.22uF
C37
GND
0.22uF
A58
A57
A56
GND
A55
C34
0.22uF
C35
GND
A54
A53
0.22uF
GND
A51
A52
RS VD5
A50
C32
0.22uF
C33
GND
0.22uF
A49
A48
A47
GND
A46
C30
0.22uF
C31
GND
0.22uF
A45
A44
A43
GND
A42
C28
0.22uF
C29
GND
A41
A40
0.22uF
GND
A38
A39
0.22uF
C27
GND
A37
A36
C26
GND
A34
0.22uF
RS VD4
A33
A35
RS VD3
A32
C24
0.22uF
C25
GND
0.22uF
A31
A30
A29
GND
A28
C22
0.22uF
C23
GND
0.22uF
A27
A26
A25
GND
A24
C20
GND
0.22uF
C21
GND
0.22uF
C18
C19
GND
RS VD1
0.22uF
0.22uF
GND
GND
GND
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
12V
WAKE
GND
J TAG1
S MDAT
S MCLK
B1
B2
P ER15_C_N
P ER15_C_P
P ER14_C_N
P ER14_C_P
P ER13_C_N
P ER13_C_P
P ER12_C_N
P ER12_C_P
P ER11_C_N
P ER11_C_P
P ER10_C_N
P ER10_C_P
P ER9_C_N
P ER9_C_P
P ER8_C_N
P ER8_C_P
RS VD5
P ER7_C_N
P ER7_C_P
P ER6_C_N
P ER6_C_P
P ER5_C_N
P ER5_C_P
P ER4_C_N
P ER4_C_P
RS VD4
RS VD3
P ER3_C_N
P ER3_C_P
P ER2_C_N
P ER2_C_P
P ER1_C_N
P ER1_C_P
RS VD1
P ER0_C_N
P ER0_C_P
REFCLK_N
REFCLK_P
P ERS T#
J TAG5
J TAG4
J TAG3
J TAG2
P RS NT1
www.ti.com
Board Layout
3_3V
J13
R28
43
R31
43
R34
43
R36
43
GND
Figure 4-4. Gold Finger Connector Schematic Page
15
Board Layout
www.ti.com
DS1
VREG_DS1
11
18
VREG
VREG
31
34
35
38
VDD
VDD
VDD
VDD
PET0_P
PET0_N
29
30
RX0P
RX0N
PET1_P
PET1_N
32
33
RX1P
RX1N
PET2_P
PET2_N
36
37
RX2P
RX2N
PET3_P
PET3_N
39
40
RX3P
RX3N
3_3V_REG
ENSMB
SCL
SDA
2
3
4
26
RSVD
24
SCL
SDA
5
GAIN
EQ1_AD1_DS1
EQ0_AD0_DS1
6
7
EQ1_ADDR1
EQ0_ADDR0
ALL_DONE_DS1
8
ALL_DONE_N
RXDET_DS
VREG_DS3
11
18
VREG
VREG
31
34
35
38
VDD
VDD
VDD
VDD
PET8_P
PET8_N
29
30
RX0P
RX0N
PET9_P
PET9_N
32
33
RX1P
RX1N
PET10_P
PET10_N
36
37
RX2P
RX2N
PET11_P
PET11_N
39
40
RX3P
RX3N
3_3V_REG
VOD
23
VOD_DS
READ_EN_N
22
READ_EN_N
PWDN1
PWDN2
21
25
PWDN
PWDN
TX0P
TX0N
20
19
PET0_C_P
PET0_C_N
TX1P
TX1N
17
16
PET1_C_P
PET1_C_N
TX2P
TX2N
13
12
PET2_C_P
PET2_C_N
TX3P
TX3N
10
9
PET3_C_P
PET3_C_N
NC
NC
NC
NC
NC
1
14
15
27
28
GND
41
EN_SMB
GAIN_DS
R37
4.70k
DS3
RX_DET
GND
GND
DS160PR410
3_3V_REG
ENSMB
2
SCL
SDA
3
4
DS4
26
RSVD
24
5
GAIN
6
7
EQ1_ADDR1
EQ0_ADDR0
ALL_DONE_DS3
8
ALL_DONE_N
VREG_DS4
11
18
VREG
VREG
31
34
35
38
VDD
VDD
VDD
VDD
PET12_P
PET12_N
29
30
RX0P
RX0N
PET13_P
PET13_N
32
33
RX1P
RX1N
PET14_P
PET14_N
36
37
RX2P
RX2N
PET15_P
PET15_N
39
40
RX3P
RX3N
3_3V_REG
VOD
23
VOD_DS
22
ALL_DONE_DS2
PWDN1
PWDN2
21
25
PWDN
PWDN
TX0P
TX0N
20
19
SCL
SDA
EQ1_AD1_DS3
EQ0_AD0_DS3
RXDET_DS
READ_EN_N
PET8_C_P
PET8_C_N
TX1P
TX1N
17
16
PET9_C_P
PET9_C_N
TX2P
TX2N
13
12
PET10_C_P
PET10_C_N
TX3P
TX3N
10
9
PET11_C_P
PET11_C_N
NC
NC
NC
NC
NC
1
14
15
27
28
GND
41
EN_SMB
GAIN_DS
R39
4.70k
RX_DET
ENSMB
SCL
SDA
GND
3
4
3_3V_REG
24
5
GAIN
6
7
EQ1_ADDR1
EQ0_ADDR0
RXDET_DS
VOD_DS
VOD
23
READ_EN_N
22
ALL_DONE_DS3
PWDN1
PWDN2
21
25
PWDN
PWDN
TX0P
TX0N
20
19
PET12_C_P
PET12_C_N
TX1P
TX1N
17
16
PET13_C_P
PET13_C_N
TX2P
TX2N
13
12
PET14_C_P
PET14_C_N
TX3P
TX3N
10
9
PET15_C_P
PET15_C_N
NC
NC
NC
NC
NC
1
14
15
27
28
GND
41
SCL
SDA
EQ1_AD1_DS4
EQ0_AD0_DS4
R40
4.70k
26
RSVD
EN_SMB
GAIN_DS
ALL_DONE_N_DS 8
GND
DS160PR410
2
RX_DET
ALL_DONE_N
GND
GND
DS160PR410
3_3V_REG
DS2
VREG_DS2
11
18
VREG
VREG
31
34
35
38
VDD
VDD
VDD
VDD
3_3V_REG
PET4_P
PET4_N
29
30
RX0P
RX0N
PET5_P
PET5_N
32
33
RX1P
RX1N
PET6_P
PET6_N
36
37
RX2P
RX2N
PET7_P
PET7_N
39
40
RX3P
RX3N
ENSMB
2
3
4
SCL
SDA
GAIN_DS
5
GAIN
EQ1_AD1_DS2
EQ0_AD0_DS2
6
7
EQ1_ADDR1
EQ0_ADDR0
ALL_DONE_DS2
8
ALL_DONE_N
R38
4.70k
26
RSVD
24
VOD
23
VOD_DS
READ_EN_N
22
ALL_DONE_DS1
DS160PR410
PWDN
PWDN
PWDN1
PWDN2
21
25
TX0P
TX0N
20
19
PET4_C_P
PET4_C_N
TX1P
TX1N
17
16
PET5_C_P
PET5_C_N
TX2P
TX2N
13
12
PET6_C_P
PET6_C_N
TX3P
TX3N
10
9
PET7_C_P
PET7_C_N
NC
NC
NC
NC
NC
1
14
15
27
28
GND
41
EN_SMB
SCL
SDA
RXDET_DS
RX_DET
ENSMB
ENSMB
SCL
SCL
SDA
SDA
PWDN
PWDN
GAIN_DS
RXDET_DS
READ_EN_N
READ_EN_N
ALL_DONE_N_DS
ALL_DONE_N_DS
EQ1_AD1_DS3
EQ1_AD1_DS4
1
3
5
7
9
11
13
15
17
19
21
23
2
4
6
8
10
R58
R60
R62
R64
R66
249
3.24k
14.7k
14.7k
14.7k
GND
3_3V_REG
2
4
6
8
10
12
14
16
18
20
22
24
R41
R42
R43
R44
R45
R46
R47
R48
R49
R50
R51
R52
1.00k
13.0k
59.0k
1.00k
13.0k
59.0k
1.00k
13.0k
59.0k
1.00k
13.0k
59.0k
2
4
6
8
10
12
14
16
18
20
22
24
R53
R54
R55
R56
R57
R59
R61
R63
R65
R67
R68
R69
1.00k
13.0k
59.0k
1.00k
13.0k
59.0k
1.00k
13.0k
59.0k
1.00k
13.0k
59.0k
GND
VREG_DS1
C61
0.1uF
C62
0.1uF
C67
0.1uF
C68
0.1uF
C73
0.1uF
C74
0.1uF
C79
0.1uF
C80
0.1uF
C63
0.1uF
C64
0.1uF
C65
0.1uF
C66
0.1uF
C69
0.1uF
C70
0.1uF
C71
0.1uF
C72
0.1uF
C75
0.1uF
C76
0.1uF
C77
0.1uF
C78
0.1uF
C81
0.1uF
C82
0.1uF
C83
0.1uF
C84
0.1uF
GND
GND
VREG_DS2
GND
GND
3_3V_REG
1
3
5
7
9
J14
EQ1_AD1_DS1
EQ1_AD1_DS2
GND
J16
VOD_DS
EQ0_AD0_DS2
EQ0_AD0_DS3
EQ0_AD0_DS4
1
3
5
7
9
11
13
15
17
19
21
23
GND
VREG_DS3
J15
EQ0_AD0_DS1
GND
GND
VREG_DS4
GND
GND
GND
Figure 4-5. Downstream Devices Schematic Page
16
DS160PR410EVM-RSC Evaluation Module (EVM)
SNLU252B – JANUARY 2020 – REVISED JULY 2021
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
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Board Layout
US1
VREG_US1
11
18
VREG
VREG
31
34
35
38
VDD
VDD
VDD
VDD
PER0_P
PER0_N
29
30
RX0P
RX0N
PER1_P
PER1_N
32
33
RX1P
RX1N
PER2_P
PER2_N
36
37
RX2P
RX2N
PER3_P
PER3_N
39
40
RX3P
RX3N
3_3V_REG
ENSMB
SCL
SDA
2
3
4
26
RSVD
24
SCL
SDA
5
GAIN
EQ1_AD1_US1
EQ0_AD0_US1
6
7
EQ1_ADDR1
EQ0_ADDR0
ALL_DONE_US1
8
ALL_DONE_N
RXDET_US
VREG_US3
VOD
23
VOD_US
22
ALL_DONE_N_DS
PWDN1
PWDN2
21
25
PWDN
TX0P
TX0N
20
19
PER0_C_P
PER0_C_N
TX1P
TX1N
17
16
PER1_C_P
PER1_C_N
TX2P
TX2N
13
12
PER2_C_P
PER2_C_N
TX3P
TX3N
10
9
PER3_C_P
PER3_C_N
NC
NC
NC
NC
NC
1
14
15
27
28
GND
41
GND
31
34
35
38
VDD
VDD
VDD
VDD
PER8_P
PER8_N
29
30
RX0P
RX0N
PER9_P
PER9_N
32
33
RX1P
RX1N
PER10_P
PER10_N
36
37
RX2P
RX2N
PER11_P
PER11_N
39
40
RX3P
RX3N
ENSMB
2
SCL
SDA
US4
RX_DET
26
RSVD
24
5
GAIN
EQ1_AD1_US3
EQ0_AD0_US3
6
7
EQ1_ADDR1
EQ0_ADDR0
ALL_DONE_US3
8
ALL_DONE_N
11
18
VREG
VREG
31
34
35
38
VDD
VDD
VDD
VDD
PER12_P
PER12_N
29
30
RX0P
RX0N
PER13_P
PER13_N
32
33
RX1P
RX1N
PER14_P
PER14_N
36
37
RX2P
RX2N
PER15_P
PER15_N
39
40
RX3P
RX3N
3_3V_REG
VOD
23
VOD_US
22
ALL_DONE_US2
PWDN1
PWDN2
21
25
PWDN
SCL
SDA
GAIN_US
VREG_US4
READ_EN_N
TX0P
TX0N
20
19
PER8_C_P
PER8_C_N
TX1P
TX1N
17
16
PER9_C_P
PER9_C_N
TX2P
TX2N
13
12
PER10_C_P
PER10_C_N
TX3P
TX3N
10
9
PER11_C_P
PER11_C_N
NC
NC
NC
NC
NC
1
14
15
27
28
GND
41
EN_SMB
3
4
RXDET_US
ENSMB
SCL
SDA
GND
US2
VREG
VREG
31
34
35
38
VDD
VDD
VDD
VDD
PER4_P
PER4_N
29
30
RX0P
RX0N
PER5_P
PER5_N
32
33
RX1P
RX1N
PER6_P
PER6_N
36
37
RX2P
RX2N
PER7_P
PER7_N
39
40
RX3P
RX3N
3_3V_REG
ENSMB
2
EN_SMB
SCL
SDA
3
4
SCL
SDA
GAIN_US
5
GAIN
EQ1_AD1_US2
EQ0_AD0_US2
6
7
EQ1_ADDR1
EQ0_ADDR0
ALL_DONE_US2
8
ALL_DONE_N
RX_DET
26
RXDET_US
RSVD
24
VOD
23
VOD_US
READ_EN_N
22
ALL_DONE_US1
PWDN1
PWDN2
21
25
PWDN
TX0P
TX0N
20
19
PER4_C_P
PER4_C_N
TX1P
TX1N
17
16
PER5_C_P
PER5_C_N
TX2P
TX2N
13
12
PER6_C_P
PER6_C_N
TX3P
TX3N
10
9
PER7_C_P
PER7_C_N
NC
NC
NC
NC
NC
1
14
15
27
28
GND
41
DS160PR410
3
4
RX_DET
26
RSVD
24
VOD
23
VOD_US
READ_EN_N
22
ALL_DONE_US3
PWDN1
PWDN2
21
25
PWDN
TX0P
TX0N
20
19
PER12_C_P
PER12_C_N
TX1P
TX1N
17
16
PER13_C_P
PER13_C_N
TX2P
TX2N
13
12
PER14_C_P
PER14_C_N
TX3P
TX3N
10
9
PER15_C_P
PER15_C_N
NC
NC
NC
NC
NC
1
14
15
27
28
GND
41
EN_SMB
SCL
SDA
5
GAIN
EQ1_AD1_US4
EQ0_AD0_US4
6
7
EQ1_ADDR1
EQ0_ADDR0
ALL_DONE_N
8
RXDET_US
ALL_DONE_N
GND
GND
DS160PR410
3_3V_REG
ENSMB
ENSMB
SCL
SCL
SDA
SDA
PWDN
PWDN
J19
VOD_US
GAIN_US
RXDET_US
ALL_DONE_N_DS
ALL_DONE_N_DS
ALL_DONE_N
ALL_DONE_N
1
3
5
7
9
2
4
6
8
10
R91
R93
R95
R97
R99
249
3.24k
14.7k
14.7k
14.7k
GND
3_3V_REG
J17
EQ1_AD1_US1
EQ1_AD1_US2
EQ1_AD1_US3
EQ1_AD1_US4
1
3
5
7
9
11
13
15
17
19
21
23
VREG_US1
2
4
6
8
10
12
14
16
18
20
22
24
R74
R75
R76
R77
R78
R79
R80
R81
R82
R83
R84
R85
1.00k
13.0k
59.0k
1.00k
13.0k
59.0k
1.00k
13.0k
59.0k
1.00k
13.0k
59.0k
2
4
6
8
10
12
14
16
18
20
22
24
R86
R87
R88
R89
R90
R92
R94
R96
R98
R100
R101
R102
1.00k
13.0k
59.0k
1.00k
13.0k
59.0k
1.00k
13.0k
59.0k
1.00k
13.0k
59.0k
GND
EQ0_AD0_US1
EQ0_AD0_US2
3_3V_REG
EQ0_AD0_US3
EQ0_AD0_US4
1
3
5
7
9
11
13
15
17
19
21
23
C85
0.1uF
C86
0.1uF
C91
0.1uF
C92
0.1uF
C97
0.1uF
C98
0.1uF
C103
0.1uF
C104
0.1uF
C87
0.1uF
C88
0.1uF
C89
0.1uF
C90
0.1uF
C93
0.1uF
C94
0.1uF
C95
0.1uF
C96
0.1uF
C99
0.1uF
C100
0.1uF
C101
0.1uF
C102
0.1uF
C105
0.1uF
C106
0.1uF
C107
0.1uF
C108
0.1uF
GND
GND
VREG_US2
GND
GND
VREG_US3
GND
J18
GND
2
GAIN_US
R73
4.70k
GND
DS160PR410
3_3V_REG
11
18
R71
4.70k
VREG
VREG
R72
4.70k
GND
DS160PR410
3_3V_REG
VREG_US2
11
18
3_3V_REG
READ_EN_N
EN_SMB
GAIN_US
R70
4.70k
US3
RX_DET
GND
GND
VREG_US4
GND
GND
GND
Figure 4-6. Upstream Devices Schematic Page
SNLU252B – JANUARY 2020 – REVISED JULY 2021
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DS160PR410EVM-RSC Evaluation Module (EVM)
Copyright © 2021 Texas Instruments Incorporated
17
18
P RS NT2_4_C
RS VD
GND
DS160PR410EVM-RSC Evaluation Module (EVM)
Copyright © 2021 Texas Instruments Incorporated
GND
GND
GND
P ET15_C_P
P ET15_C_N
GND
P ET14_C_P
P ET14_C_N
GND
P ET13_C_P
P ET13_C_N
GND
P ET12_C_P
P ET12_C_N
GND GND
P ET11_C_P
P ET11_C_N
GND
P ET10_C_P
P ET10_C_N
GND
P ET9_C_P
P ET9_C_N
P RS NT2_3_C
GND
P ET8_C_P
P ET8_C_N
GND
P ET7_C_P
P ET7_C_N
GND
P ET6_C_P
P ET6_C_N
GND
P ET5_C_P
P ET5_C_N
GND
P ET4_C_P
P ET4_C_N
RS VD2
P RS NT2_2_C
GND GND
P ET3_C_P
P ET3_C_N
GND
P ET2_C_P
P ET2_C_N
P RS NT2_1_C
GND
P ET1_C_P
P ET1_C_N
P ET0_C_P
P ET0_C_N
WAKE
GND
CLKREQ
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
B12
B13
C140
C124
C139
C123
C138
C122
C137
C121
C136
C120
C135
C119
C134
C118
C133
C117
C132
C116
C131
C115
C130
C114
C129
C113
C128
C112
C127
C111
C126
C110
C125
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82
C109 B14
TOP
BOT
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
12V
J TAG1
S MCLK
S MDAT
12V
GND
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
RS VD5
RS VD1
P ERS T#
J TAG2
J TAG3
J TAG4
J TAG5
P RS NT1
RS VD3
RS VD4
P ER15_P
P ER15_N
P ER14_P
P ER14_N
P ER13_P
P ER13_N
P ER12_P
P ER12_N
P ER11_P
P ER11_N
P ER10_P
P ER10_N
P ER9_P
P ER9_N
P ER8_P
P ER8_N
P ER7_P
P ER7_N
P ER6_P
P ER6_N
P ER5_P
P ER5_N
P ER4_P
P ER4_N
P ER3_P
P ER3_N
P ER2_P
P ER2_N
P ER1_P
P ER1_N
P ER0_P
P ER0_N
REFCLK_P
REFCLK_N
Board Layout
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3_3V
J20
3_3V
GND
3_3VAUX
Figure 4-7. Straddle Connector Schematic Page
SNLU252B – JANUARY 2020 – REVISED JULY 2021
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Board Layout
SH-J1
H2
H4
1
H6
1
DNP
1
DNP
NY PMS 440 0025 PH
H1
H8
1
DNP
NY PMS 440 0025 PH
H3
DNP
NY PMS 440 0025 PH
H5
NY PMS 440 0025 PH
H7
DNP
DNP
DNP
DNP
1902C
1902C
1902C
1902C
SH-J2
SH-J3
SH-J4
DNP
DNP
DNP
DNP
DNP
DNP
FID1
FID2
FID3
FID4
FID5
FID6
SH-J5
PCB Number: HSDC058
PCB Rev: A
ZZ5
Assembly Note
Place accross pins 1-2 of J1
P CB
LOGO
Texas Instruments
CE Mark
P CB
LOGO
P CB
LOGO
FCC dis claimer
WEEE logo
SH-J6
ZZ6
Assembly Note
Place accross pins 1-2 of J5
ZZ7
Assembly Note
Place accross pins 1-2 of J6
ZZ8
Assembly Note
Place accross pins 1-2 of J7
ZZ9
Assembly Note
Place accross pins 1-2 of J8
ZZ10
Assembly Note
Place accross pins 1-2 of J9
SH-J11
SH-J12
SH-J13
SH-J14
SH-J15
SH-J16
SH-J17
SH-J18
Varia nt/Label Ta ble
Variant
LBL1
P CB Label
THT-14-423-10
Size: 0.65" x 0.20 "
ZZ15
Assembly Note
Place accross pins 1-2 of J14
ZZ16
Assembly Note
Place accross pins 7-8 of J14
ZZ17
Assembly Note
Place accross pins 13-14 of J14
ZZ18
Assembly Note
Place accross pins 19-20 of J14
ZZ19
Assembly Note
Place accross pins 5-6 of J15
ZZ20
Assembly Note
Place accross pins 11-12 of J15
ZZ21
Assembly Note
Place accross pins 17-18 of J15
ZZ22
Assembly Note
Place accross pins 23-24 of J15
SH-J19
SH-J20
SH-J21
SH-J22
SH-J23
SH-J24
SH-J25
SH-J26
ZZ23
Assembly Note
Place accross pins 1-2 of J17
ZZ24
Assembly Note
Place accross pins 7-8 of J17
ZZ25
Assembly Note
Place accross pins 13-14 of J17
ZZ26
Assembly Note
Place accross pins 19-20 of J17
ZZ27
Assembly Note
Place accross pins 5-6 of J18
ZZ28
Assembly Note
Place accross pins 11-12 of J18
ZZ29
Assembly Note
Place accross pins 17-18 of J18
ZZ30
Assembly Note
Place accross pins 23-24 of J18
Label Text
001
DS160PR410EVM-RSC
002
DS160PR410EVM-SMA
ZZ1
Label Assembly Note
This Assembly Note is for PCB labels only
SH-J7
DNP
SH-J8
DNP
ZZ2
Assembly Note
These assemblie s are ESD sens itive, ESD precautions shall be observed.
ZZ3
Assembly Note
These assemblie s must be clean and free from flux and all contaminants. Use of no clean flux is not acceptable.
ZZ4
Assembly Note
These assemblie s must comply with workmanship standards IPC-A-610 Class 2, unless otherwis e specifie d.
SH-J9
DNP
SH-J10
DNP
ZZ11
DNPNote
Assembly
Place accross pins 2-3 of J3
ZZ12
DNPNote
Assembly
Place accross pins 1-2 of J29
ZZ13
DNPNote
Assembly
Place accross pins 11-12 of J29
ZZ14
DNPNote
Assembly
Place accross pins 19-20 of J29
MP1
H9
PMSSS 440 0025 PH
H10
9B90-0000A
PMSSS 440 0025 PH
Figure 4-8. Hardware Page
SNLU252B – JANUARY 2020 – REVISED JULY 2021
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Board Layout
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5 Bill of Materials
Table 5-1. Bill of Materials
VALUE
PACKAGE
REFERENCE
DESIGNATOR
QTY
DESCRIPTION
PART NUMBER
MANUFACTURER
!PCB1
1
HSDC058
Any
C1, C2, C8
3
1uF
CAP, CERM, 1 uF, 25 V, +/- 10%, X5R, 0402
C3
1
0.1uF
CAP, CERM, 0.1 uF, 25 V, +/- 10%, X5R, 0402
0402
C1005X5R1E105K050BC
TDK
0402
GRM155R61E104KA87D
MuRata
C4
1
100uF
C5, C6
2
22uF
CAP, TA, 100 uF, 25 V, +/- 10%, 0.1 ohm, SMD
7360-38
T495E107K025ATE100
Kemet
CAP, CERM, 22 uF, 25 V, +/- 20%, X5R, 1206_190
1206_190
TMK316BBJ226ML-T
Taiyo Yuden
C7, C17
2
C9, C10
2
4.7uF
CAP, CERM, 4.7 uF, 25 V, +/- 10%, X6S, 0603
0603
GRM188C81E475KE11D
MuRata
100uF
CAP, CERM, 100 uF, 6.3 V, +/- 20%, X5R, 0805
0805
GRM21BR60J107M
MuRata
C11
C12
1
47uF
CAP, CERM, 47 uF, 6.3 V, +/- 20%, X5R, 0805
0805
GRM219R60J476ME44D
MuRata
1
10uF
CAP, CERM, 10 uF, 6.3 V, +/- 10%, X5R, 0805
0805
GRM219R60J106KE19D
MuRata
C13
1
4.7uF
CAP, CERM, 4.7 uF, 6.3 V, +/- 10%, X5R, 0603
0603
GRM188R60J475KE19D
MuRata
C14
1
1uF
CAP, CERM, 1 uF, 6.3 V, +/- 10%, X7R, 0603
0603
GRM188R70J105KA01D
MuRata
C15
1
0.47uF
CAP, CERM, 0.47 uF, 6.3 V, +/- 10%, X7R, 0603
0603
GRM188R70J474KA01D
MuRata
C16
1
Printed Circuit Board
0.1uF
CAP, CERM, 0.1 uF, 6.3 V, +/- 10%, X7R, 0603
0603
GRM188R70J104KA01D
MuRata
C18, C19, C20, C21, C22, C23, C24, 64
C25, C26, C27, C28, C29, C30, C31,
C32, C33, C34, C35, C36, C37, C38,
C39, C40, C41, C42, C43, C44, C45,
C46, C47, C48, C49, C109, C110,
C111, C112, C113, C114, C115, C116,
C117, C118, C119, C120, C121,
C122, C123, C124, C125, C126,
C127, C128, C129, C130, C131,
C132, C133, C134, C135, C136,
C137, C138, C139, C140
0.22uF
CAP, CERM, 0.22 uF, 10 V, +/- 20%, X5R, 0201
0201
LMK063BJ224MP-F
Taiyo Yuden
C50, C51, C52, C53, C54, C55, C56,
C57, C58, C59, C60
11
1pF
CAP, CERM, 1 pF, 50 V, +/- 10%, C0G/NP0, 0402
0402
GJM1555C1H1R0BB01D
MuRata
C61, C62, C63, C64, C65, C66, C67,
C68, C69, C70, C71, C72, C73, C74,
C75, C76, C77, C78, C79, C80, C81,
C82, C83, C84, C85, C86, C87, C88,
C89, C90, C91, C92, C93, C94, C95,
C96, C97, C98, C99, C100, C101,
C102, C103, C104, C105, C106,
C107, C108
48
0.1uF
CAP, CERM, 0.1 uF, 6.3 V, +/- 10%, X5R, 0201
0201
C0603X5R0J104K030BC
TDK
D1, D2, D3
3
Green
LED, Green, SMD
2x1.4mm
LG M67K-G1J2-24-Z
OSRAM
DS1, DS2, DS3, DS4, US1, US2,
US3, US4
8
DS160PR410, RNQ0040A (WQFN-40)
RNQ0040A
DS160PR410
Texas Instruments
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Board Layout
Table 5-1. Bill of Materials (continued)
VALUE
PACKAGE
REFERENCE
DESIGNATOR
QTY
PART NUMBER
MANUFACTURER
H9, H10
2
MACHINE SCREW PAN PHILLIPS 4-40
Machine
Screw, 4-40,
1/4 inch
PMSSS 440 0025 PH
B and F Fastener
Supply
J1
1
Header, 100mil, 3x2, Gold, TH
3x2 Header
TSW-103-07-G-D
Samtec
J2, J16, J19
J3, J4, J6, J7, J8, J9
3
Header, 100mil, 5x2, Gold, TH
5x2 Header
TSW-105-07-G-D
Samtec
6
Header, 2.54mm, 3x1, Gold, TH
Header,
2.54mm, 3x1,
TH
961103-6804-AR
3M
J5, J10, J11, J12
4
Header, 2.54mm, 2x1, TH
Header,
2.54mm, 2x1,
TH
961102-6404-AR
3M
J14, J15, J17, J18
4
Header, 100mil, 12x2, Gold, TH
12x2 Header
TSW-112-07-G-D
Samtec
J20
1
Receptacle, 1mm, 82x2, Gold, SMT
Receptacle,
1mm, 82x2,
SMT
GWE82DHRN-T9410
Sullins Connector
Solutions
L1
1
Inductor, Drum Core, Ferrite, 6.8 uH, 3.2 A, 0.04 ohm, SMD
SDR0805
SDR0805-6R8ML
Bourns
LBL1
1
Thermal Transfer Printable Labels, 0.650" W x 0.200" H - 10,000 PCB Label
per roll
0.650 x 0.200
inch
THT-14-423-10
Brady
MP1
1
PCI bracket
PCI_BRCKT_N 9B90-0000A
PTH_2
Gompf Brackets,
Inc.
R4, R5
2
2.2k
RES, 2.2 k, 5%, 0.063 W, AEC-Q200 Grade 0, 0402
0402
CRCW04022K20JNED
Vishay-Dale
R6
1
124
RES, 124, 1%, 0.063 W, AEC-Q200 Grade 0, 0402
0402
CRCW0402124RFKED
Vishay-Dale
R7
1
1.62k
RES, 1.62 k, 1%, 0.063 W, AEC-Q200 Grade 0, 0402
0402
CRCW04021K62FKED
Vishay-Dale
R8
1
7.32k
RES, 7.32 k, 1%, 0.063 W, AEC-Q200 Grade 0, 0402
0402
CRCW04027K32FKED
Vishay-Dale
R9, R58, R91
3
249
RES, 249, 1%, 0.1 W, AEC-Q200 Grade 0, 0402
0402
ERJ-2RKF2490X
Panasonic
R10
1
10.0k
RES, 10.0 k, 1%, 0.063 W, AEC-Q200 Grade 0, 0402
0402
AC0402FR-0710KL
Yageo America
R11, R12, R13
3
330
RES, 330, 5%, 0.063 W, AEC-Q200 Grade 0, 0402
0402
CRCW0402330RJNED
Vishay-Dale
R14
1
165k
RES, 165 k, 1%, 0.1 W, 0603
0603
RC0603FR-07165KL
Yageo
R15
1
120k
RES, 120 k, 1%, 0.1 W, 0603
0603
RC0603FR-07120KL
Yageo
R16
1
10.0k
RES, 10.0 k, 1%, 0.063 W, 0402
0402
RC0402FR-0710KL
Yageo America
R17
1
105k
RES, 105 k, 1%, 0.063 W, AEC-Q200 Grade 0, 0402
0402
CRCW0402105KFKED
Vishay-Dale
R18, R19, R20
3
100k
RES, 100 k, 1%, 0.0625 W, 0402
0402
RC0402FR-07100KL
Yageo America
R21
1
5.76k
RES, 5.76 k, 1%, 0.063 W, AEC-Q200 Grade 0, 0402
0402
CRCW04025K76FKED
Vishay-Dale
R22
1
165k
RES, 165 k, 1%, 0.1 W, AEC-Q200 Grade 0, 0402
0402
ERJ-2RKF1653X
Panasonic
R23
1
37.4k
RES, 37.4 k, 1%, 0.063 W, AEC-Q200 Grade 0, 0402
0402
CRCW040237K4FKED
Vishay-Dale
R24
1
42.2k
RES, 42.2 k, 1%, 0.063 W, AEC-Q200 Grade 0, 0402
0402
CRCW040242K2FKED
Vishay-Dale
6.8uH
DESCRIPTION
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Table 5-1. Bill of Materials (continued)
DESIGNATOR
QTY
VALUE
DESCRIPTION
PACKAGE
REFERENCE
PART NUMBER
MANUFACTURER
R25
1
2.05k
RES, 2.05 k, 1%, 0.063 W, AEC-Q200 Grade 0, 0402
0402
CRCW04022K05FKED
Vishay-Dale
R26, R27, R28, R29, R30, R31, R32,
R33, R34, R35, R36
11
43
RES, 43, 5%, 0.063 W, AEC-Q200 Grade 0, 0402
0402
CRCW040243R0JNED
Vishay-Dale
R37, R38, R39, R40, R70, R71, R72,
R73
8
4.70k
RES, 4.70 k, 1%, 0.063 W, 0402
0402
CRG0402F4K7
TE Connectivity
R41, R44, R47, R50, R53, R56, R61,
R67, R74, R77, R80, R83, R86, R89,
R94, R100
16
1.00k
RES, 1.00 k, 1%, 0.063 W, 0402
0402
MCR01MZPF1001
Rohm
R42, R45, R48, R51, R54, R57, R63,
R68, R75, R78, R81, R84, R87, R90,
R96, R101
16
13.0k
RES, 13.0 k, 1%, 0.063 W, AEC-Q200 Grade 0, 0402
0402
CRCW040213K0FKED
Vishay-Dale
R43, R46, R49, R52, R55, R59, R65,
R69, R76, R79, R82, R85, R88, R92,
R98, R102
16
59.0k
RES, 59.0 k, 1%, 0.063 W, AEC-Q200 Grade 0, 0402
0402
CRCW040259K0FKED
Vishay-Dale
R60, R93
2
3.24k
RES, 3.24 k, 1%, 0.063 W, AEC-Q200 Grade 0, 0402
0402
CRCW04023K24FKED
Vishay-Dale
R62, R64, R66, R95, R97, R99
6
14.7k
RES, 14.7 k, 1%, 0.063 W, AEC-Q200 Grade 0, 0402
0402
CRCW040214K7FKED
Vishay-Dale
1x2
Shunt, 100mil, Flash Gold, Black
Closed Top
100mil Shunt
SPC02SYAN
Sullins Connector
Solutions
SH-J1, SH-J2, SH-J3, SH-J4, SH-J5, 22
SH-J6, SH-J11, SH-J12, SH-J13, SHJ14, SH-J15, SH-J16, SH-J17, SHJ18, SH-J19, SH-J20, SH-J21, SHJ22, SH-J23, SH-J24, SH-J25, SHJ26
SW1
1
Switch, Tactile, SPST-NO, 0.02A, 15V, TH
6.0x5.0x6mm
EVQ-21505R
Panasonic
U1
1
I2C-Compatible (2-wire) Serial EEPROM 2-Kbit (256 x 8),
SOIC-8
SOIC-8
AT24C02D-SSHM-T
Atmel
U2
1
Quadruple Bus Buffer Gate With 3-State Outputs, PW0014A,
LARGE T and R
PW0014A
SN74LVC125APWRG3
Texas Instruments
U3
1
1.5-V to 16-V VIN, 4.5-V to 22-V VDD, 25-A SWIFT
Synchronous Step-Down Converter with Full Differential Sense,
RVF0040A (LQFN-CLIP-40)
RVF0040A
TPS548B22RVFR
Texas Instruments
C141, C142, C143, C144, C145,
C146, C147, C148, C155, C156,
C157, C158, C159, C160, C161,
C162
0
0.22uF
CAP, CERM, 0.22 uF, 10 V, +/- 20%, X5R, 0201
0201
LMK063BJ224MP-F
Taiyo Yuden
C149, C150, C151, C152, C153,
C154
0
0.1uF
CAP, CERM, 0.1 uF, 6.3 V, +/- 10%, X5R, 0201
0201
C0603X5R0J104K030BC
TDK
FID1, FID2, FID3, FID4, FID5, FID6
0
Fiducial mark. There is nothing to buy or mount.
N/A
N/A
N/A
H1, H3, H5, H7
0
Standoff, Hex, 0.5"L #4-40 Nylon
Standoff
1902C
Keystone
H2, H4, H6, H8
0
Machine Screw, Round, #4-40 x 1/4, Nylon, Philips panhead
Screw
NY PMS 440 0025 PH
B and F Fastener
Supply
22
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Board Layout
Table 5-1. Bill of Materials (continued)
DESIGNATOR
QTY
J21, J22, J27, J28, J30, J31, J32,
J33, J38, J39, J40, J41
0
VALUE
PACKAGE
REFERENCE
DESCRIPTION
PART NUMBER
MANUFACTURER
SMA, Straight Jack, SMT
SMA
Connector,
SMT
732511352
Molex
J23, J24, J25, J26, J34, J35, J36, J37 0
SMA JACK 50 OHM, R/A, SMT
SMA JACK,
R/A, SMT
32K243-40ML5
Rosenberger
J29
0
Header, 100mil, 12x2, Gold, TH
12x2 Header
TSW-112-07-G-D
Samtec
R103
0
4.70k
RES, 4.70 k, 1%, 0.063 W, 0402
0402
CRG0402F4K7
TE Connectivity
R104, R107, R110
0
1.00k
RES, 1.00 k, 1%, 0.063 W, 0402
0402
MCR01MZPF1001
Rohm
R105, R108, R111
0
13.0k
RES, 13.0 k, 1%, 0.063 W, AEC-Q200 Grade 0, 0402
0402
CRCW040213K0FKED
Vishay-Dale
R106, R109, R112, R113, R114
0
59.0k
RES, 59.0 k, 1%, 0.063 W, AEC-Q200 Grade 0, 0402
0402
CRCW040259K0FKED
Vishay-Dale
SA1
0
DS160PR410, RNQ0040A (WQFN-40)
RNQ0040A
DS160PR410
Texas Instruments
SH-J7, SH-J8, SH-J9, SH-J10
0
Shunt, 100mil, Flash Gold, Black
Closed Top
100mil Shunt
SPC02SYAN
Sullins Connector
Solutions
1x2
SNLU252B – JANUARY 2020 – REVISED JULY 2021
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References
www.ti.com
6 References
For references, see the following:
1. Texas Instruments, DS160PR410 4-Channel PCI-Express Gen-4 Linear Redriver Datasheet (SNLS645)
2. Texas Instruments, DS160PR410 Programming Guide (SNLU255)
3. Texas Instruments, Understanding EEPROM Programming for DS160PR410 PCI-Express Gen-4 Redriver
(SNLA320)
7 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (January 2020) to Revision B (July 2021)
Page
• Updated the numbering format for tables, figures and cross-references throughout the document...................3
24
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