DS25BR101TSDE/NOPB

DS25BR100 www.ti.com SNLS217F – MARCH 2007 – REVISED APRIL 2013 DS25BR100 / DS25BR101 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization Check for Samples: DS25BR100 FEATURES DESCRIPTION • The DS25BR100 and DS25BR101 are single channel 3.125 Gbps LVDS buffers optimized for high-speed signal transmission over lossy FR-4 printed circuit board backplanes and balanced metallic cables. Fully differential signal paths ensure exceptional signal integrity and noise immunity. 1 2 • • • • • • DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation Receive Equalization Reduces ISI Jitter Due to Media Loss Transmit Pre-Emphasis Drives Lossy Backplanes and Cables On-Chip 100Ω Input and Output Termination: – Minimizes Insertion and Return Losses – Reduces Component Count – Minimizes Board Space DS25BR101 Eliminates On-Chip Input Termination for Added Design Flexibility 7 kV ESD on LVDS I/O Pins Protects Adjoining Components Small 3 mm x 3 mm WSON-8 Space Saving Package APPLICATIONS • • • Clock and Data Buffering Metallic Cable Driving and Equalization FR-4 Equalization The DS25BR100 and DS25BR101 feature transmit pre-emphasis (PE) and receive equalization (EQ), making them ideal for use as a repeater device. Other LVDS devices with similar IO characteristics include the following products. The DS25BR120 features four levels of pre-emphasis for use as an optimized driver device, while the DS25BR110 features four levels of equalization for use as an optimized receiver device. The DS25BR150 is a buffer/repeater with the lowest power consumption and does not feature transmit pre-emphasis nor receive equalization. Wide input common mode range allows the receiver to accept signals with LVDS, CML and LVPECL levels; the output levels are LVDS. A very small package footprint requires minimal space on the board while the flow-through pinout allows easy board layout. On the DS25BR100 the differential input and output is internally terminated with a 100Ω resistor to lower return losses, reduce component count and further minimize board space. For added design flexibility the 100Ω input terminations on the DS25BR101 have been eliminated. This elimination enables a designer to adjust the termination for custom interconnect topologies and layout. Typical Application PE VCC CML ASIC / FPGA LVDS BR100 EQ LVPECL EQ VCC LVDS ASIC / FPGA PE BR100 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007–2013, Texas Instruments Incorporated DS25BR100 SNLS217F – MARCH 2007 – REVISED APRIL 2013 www.ti.com Device Information Termination Option Available Signal Conditioning DS25BR100 Device Buffer / Repeater Function Internal 100Ω for LVDS inputs 2 Levels: PE and EQ DS25BR101 Buffer / Repeater External termination required 2 Levels: PE and EQ DS25BR110 Receiver Internal 100Ω for LVDS inputs 4 Levels: EQ DS25BR120 Driver Internal 100Ω for LVDS inputs 4 Levels: PE DS25BR150 Buffer / Repeater Internal 100Ω for LVDS inputs None Block Diagram EQ PE IN+ OUT+ IN- OUT- DS25BR101 eliminates 100Ω input termination. Pin Diagram EQ 1 IN+ 2 DAP IN- 3 GND PE 4 8 VCC 7 OUT+ 6 OUT- 5 NC PIN DESCRIPTIONS Pin Name Pin Name Pin Type EQ 1 Input Equalizer select pin. Pin Description IN+ 2 Input Non-inverting LVDS input pin. IN- 3 Input Inverting LVDS input pin. PE 4 Input Pre-emphasis select pin. NC 5 NA "NO CONNECT" pin. OUT- 6 Output Inverting LVDS output pin. OUT+ 7 Output Non-inverting LVDS Output pin. VCC 8 Power Power supply pin. GND DAP Power Ground pad (DAP - die attach pad). Control Pins (PE and EQ) Truth Table 2 EQ PE Equalization Level 0 0 Low (Approx. 4 dB at 1.56 GHz) Off 0 1 Low (Approx. 4 dB at 1.56 GHz) Medium (Approx. 6 dB at 1.56 GHz) 1 0 Medium (Approx. 8 dB at 1.56 GHz) Off 1 1 Medium (Approx. 8 dB at 1.56 GHz) Medium (Approx. 6 dB at 1.56 GHz) Submit Documentation Feedback Pre-emphasis Level Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: DS25BR100 DS25BR100 www.ti.com SNLS217F – MARCH 2007 – REVISED APRIL 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) −0.3V to +4V Supply Voltage (VCC) −0.3V to (VCC + 0.3V) LVCMOS Input Voltage (EQ, PE) −0.3V to +4V LVDS Input Voltage (IN+, IN−) Differential Input Voltage |VID| (DS25BR100) 1V LVDS Differential Input Voltage (DS25BR101) VCC + 0.6V −0.3V to (VCC + 0.3V) LVDS Output Voltage (OUT+, OUT−) LVDS Differential Output Voltage ((OUT+) - (OUT−)) 0V to 1V LVDS Output Short Circuit Current Duration 5 ms Junction Temperature +150°C −65°C to +150°C Storage Temperature Range Lead Temperature Range Soldering (4 sec.) +260°C NGQ0008A Package Maximum Package Power Dissipation at 25°C 2.08W Derate NGQ0008A Package Package Thermal Resistance 16.7 mW/°C above +25°C θJA +60.0°C/W θJC +12.3°C/W HBM (3) ESD Susceptibility MM ≥7 kV (4) ≥250V CDM (5) (1) (2) (3) (4) (5) ≥1250V “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications. Human Body Model, applicable std. JESD22-A114C Machine Model, applicable std. JESD22-A115-A Field Induced Charge Device Model, applicable std. JESD22-C101-C Recommended Operating Conditions Supply Voltage (VCC) Min Typ Max Units 3.0 3.3 3.6 V 1.0 V +85 °C Receiver Differential Input Voltage (VID) (DS25BR100 only) −40 Operating Free Air Temperature (TA) +25 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: DS25BR100 3 DS25BR100 SNLS217F – MARCH 2007 – REVISED APRIL 2013 www.ti.com DC Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified (1) (2) (3) Parameter Test Conditions Min Typ Max Units V LVCMOS INPUT DC SPECIFICATIONS (EQ, PE) VIH High Level Input Voltage 2.0 VCC VIL Low Level Input Voltage GND 0.8 V IIH High Level Input Current VIN = 3.6V VCC = 3.6V 0 ±10 μA IIL Low Level Input Current VIN = GND VCC = 3.6V 0 ±10 μA VCL Input Clamp Voltage ICL = −18 mA, VCC = 0V -0.9 −1.5 V 350 450 mV 35 mV 1.375 V 35 mV LVDS OUTPUT DC SPECIFICATIONS (OUT+, OUT-) VOD Differential Output Voltage ΔVOD Change in Magnitude of VOD for Complimentary Output States 250 VOS Offset Voltage ΔVOS Change in Magnitude of VOS for Complimentary Output States RL = 100Ω IOS Output Short Circuit Current (4) OUT to GND, PE = 0 -35 -55 mA OUT to VCC, PE = 0 7 55 mA RL = 100Ω -35 1.05 1.2 -35 COUT Output Capacitance Any LVDS Output Pin to GND 1.2 pF ROUT Output Termination Resistor Between OUT+ and OUT- 100 Ω LVDS INPUT DC SPECIFICATIONS (IN+, IN-) VID Input Differential Voltage (5) VTH Differential Input High Threshold VTL Differential Input Low Threshold VCMR Common Mode Voltage Range VID = 100 mV IIN Input Current VIN = GND or 3.6V VCC = 3.6V or 0.0V ±1 CIN Input Capacitance Any LVDS Input Pin to GND 1.7 pF Between IN+ and IN- 100 Ω EQ = 0, PE = 0 35 RIN Input Termination Resistor (6) 0 VCM = +0.05V or VCC-0.05V 0 −100 1 V +100 mV 0 0.05 mV VCC 0.05 V ±10 μA SUPPLY CURRENT ICC (1) (2) (3) (4) (5) (6) 4 Supply Current 43 mA The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD and ΔVOD. Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Input Differential Voltage (VID) The DS25BR100 limits input amplitude to 1 volt. The DS25BR101 supports any VID within the supply voltage to GND range. Input Termination Resistor (RIN) The DS25BR100 provides an integrated 100 ohm input termination for the high speed LVDS pair. The DS25BR101 eliminates this internal termination. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: DS25BR100 DS25BR100 www.ti.com SNLS217F – MARCH 2007 – REVISED APRIL 2013 AC Electrical Characteristics (1) Over recommended operating supply and temperature ranges unless otherwise specified (2) (3) Parameter Test Conditions Min Typ Max Units 350 465 ps 350 465 ps 45 100 ps 45 150 ps 80 150 ps 80 150 ps LVDS OUTPUT AC SPECIFICATIONS (OUT+, OUT-) tPHLD Differential Propagation Delay High to Low tPLHD Differential Propagation Delay Low to High tSKD1 Pulse Skew |tPLHD − tPHLD| (4) tSKD2 Part to Part Skew tLHT Rise Time tHLT Fall Time RL = 100Ω (5) RL = 100Ω JITTER PERFORMANCE WITH PE = OFF AND EQ = LOW tRJ1A tRJ2A VID = 350 mV VCM = 1.2V Clock (RZ) PE = 0, EQ = 0 2.5 Gbps 0.5 1 ps Random Jitter (RMS Value) Input Test Channel D (8) 3.125 Gbps 0.5 1 ps VID = 350 mV VCM = 1.2V K28.5 (NRZ) PE = 0, EQ = 0 2.5 Gbps 1 16 ps Deterministic Jitter (Peak to Peak) Input Test Channel D (9) 3.125 Gbps 11 31 ps VID = 350 mV VCM = 1.2V PRBS-23 (NRZ) PE = 0, EQ = 0 2.5 Gbps 0.03 0.09 UIP-P Total Jitter (Peak to Peak) Input Test Channel D (10) 3.125 Gbps 0.06 0.14 UIP-P tDJ1A tDJ2A tTJ1A tTJ2A (6) (7) JITTER PERFORMANCE WITH PE = OFF AND EQ = MEDIUM (6) (7) tRJ1B tRJ2B VID = 350 mV VCM = 1.2V Clock (RZ) PE = 0, EQ = 1 2.5 Gbps 0.5 1 ps Random Jitter (RMS Value) Input Test Channel E (8) 3.125 Gbps 0.5 1 ps VID = 350 mV VCM = 1.2V K28.5 (NRZ) PE = 0, EQ = 1 2.5 Gbps 10 29 ps Deterministic Jitter (Peak to Peak) Input Test Channel E (9) 3.125 Gbps 27 43 ps VID = 350 mV VCM = 1.2V PRBS-23 (NRZ) PE = 0, EQ = 1 2.5 Gbps 0.07 0.12 UIP-P Total Jitter (Peak to Peak) Input Test Channel E (10) 3.125 Gbps 0.12 0.17 UIP-P tDJ1B tDJ2B tTJ1B tTJ2B (1) (2) Specification is ensured by characterization and is not tested in production. The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. (3) Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. (4) tSKD1, |tPLHD − tPHLD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel. (5) tSKD2, Part to Part Skew, is defined as the difference between the minimum and maximum differential propagation delays. This specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range. (6) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD and ΔVOD. (7) Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. (8) Measured on a clock edge with a histogram and an acummulation of 1500 histogram hits. Input stimulus jitter is subtracted geometrically. (9) Tested with a combination of the 1100000101 (K28.5+ character) and 0011111010 (K28.5- character) patterns. Input stimulus jitter is subtracted algebraically. (10) Measured on an eye diagram with a histogram and an acummulation of 3500 histogram hits. Input stimulus jitter is subtracted. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: DS25BR100 5 DS25BR100 SNLS217F – MARCH 2007 – REVISED APRIL 2013 www.ti.com AC Electrical Characteristics(1) (continued) Over recommended operating supply and temperature ranges unless otherwise specified(2)(3) Parameter Test Conditions JITTER PERFORMANCE WITH PE = MEDIUM AND EQ = LOW tRJ1C tRJ2C tDJ1C tDJ2C tTJ1C tTJ2C Min Typ Max Units (11) (12) Random Jitter (RMS Value) Input Test Channel D Output Test Channel B (13) VID = 350 mV VCM = 1.2V Clock (RZ) PE = 1, EQ = 0 2.5 Gbps 0.5 1 ps 3.125 Gbps 0.5 1 ps Deterministic Jitter (Peak to Peak) Input Test Channel D Output Test Channel B (14) VID = 350 mV VCM = 1.2V K28.5 (NRZ) PE = 1, EQ = 0 2.5 Gbps 29 57 ps 3.125 Gbps 29 51 ps Total Jitter (Peak to Peak) Input Test Channel D Output Test Channel B (15) VID = 350 mV VCM = 1.2V PRBS-23 (NRZ) PE = 1, EQ = 0 2.5 Gbps 0.10 0.19 UIP-P 3.125 Gbps 0.13 0.22 UIP-P JITTER PERFORMANCE WITH PE = MEDIUM AND EQ = MEDIUM (11) (12) tRJ1D tRJ2D tDJ1D tDJ2D tTJ1D tTJ2D Random Jitter (RMS Value) Input Test Channel E Output Test Channel B (13) VID = 350 mV VCM = 1.2V Clock (RZ) PE = 1, EQ = 1 2.5 Gbps 0.5 1.1 ps 3.125 Gbps 0.5 1 ps Deterministic Jitter (Peak to Peak) Input Test Channel E Output Test Channel B (14) VID = 350 mV VCM = 1.2V K28.5 (NRZ) PE = 1, EQ = 1 2.5 Gbps 41 77 ps 3.125 Gbps 46 98 ps Total Jitter (Peak to Peak) Input Test Channel E Output Test Channel B (15) VID = 350 mV VCM = 1.2V PRBS-23 (NRZ) PE = 1, EQ = 1 2.5 Gbps 0.13 0.20 UIP-P 3.125 Gbps 0.19 0.30 UIP-P (11) Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. (12) Input Differential Voltage (VID) The DS25BR100 limits input amplitude to 1 volt. The DS25BR101 supports any VID within the supply voltage to GND range. (13) Measured on a clock edge with a histogram and an acummulation of 1500 histogram hits. Input stimulus jitter is subtracted geometrically. (14) Tested with a combination of the 1100000101 (K28.5+ character) and 0011111010 (K28.5- character) patterns. Input stimulus jitter is subtracted algebraically. (15) Measured on an eye diagram with a histogram and an acummulation of 3500 histogram hits. Input stimulus jitter is subtracted. 6 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: DS25BR100 DS25BR100 www.ti.com SNLS217F – MARCH 2007 – REVISED APRIL 2013 Typical Performance Characteristics 4.50 VCC = 3.3V MAXIMUM DATA RATE (Gbps) w/ PE and/or EQ TA = 25°C NRZ PRBS-7 TJ = 0.25 UI 3.75 3.00 2.25 w/o PE and EQ 1.50 0.75 0 0 6 12 18 24 30 CAT5e LENGTH (m) Figure 1. Maximum Data Rate as a Function of CAT5e (Belden 1700A) Length Figure 2. A 2.5 Gbps NRZ PRBS-7 After 60" Differential FR-4 Stripline V:125 mV / DIV, H:75 ps / DIV 4.50 MAXIMUM DATA RATE (Gbps) w/ PE and/or EQ 3.75 3.00 2.25 w/o PE and EQ 1.50 VCC = 3.3V TA = 25°C NRZ PRBS-7 TJ = 0.5 UI 0.75 0 0 6 12 18 24 30 CAT5e LENGTH (m) Figure 3. A 3.125 Gbps NRZ PRBS-7 After 60" Differential FR-4 Stripline V:125 mV / DIV, H:50 ps / DIV Figure 4. Maximum Data Rate as a Function of CAT5e (Belden 1700A) Length Figure 5. An Equalized (with PE and EQ) 2.5 Gbps NRZ PRBS-7 After The 40" Input and 20" Output Differential Stripline (Figure 16) V:125 mV / DIV, H:75 ps / DIV Figure 6. An Equalized (with PE and EQ) 3.125 Gbps NRZ PRBS-7 After The 40" Input and 20" Output Differential Stripline (Figure 16) V:125 mV / DIV, H:50 ps / DIV Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: DS25BR100 7 DS25BR100 SNLS217F – MARCH 2007 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) 150 150 VCC = 3.3V TA = 25°C NRZ PRBS-7 EQ = Low PE = Off 125 100 75 TOTAL RESIDUAL JITTER (ps) TOTAL RESIDUAL JITTER (ps) VCC = 3.3V 20" FR4 Stripline 50 10" FR4 Stripline 25 0 0 0.8 1.6 2.4 3.2 TA = 25°C NRZ PRBS-7 2.5 Gbps PE = Off 125 100 75 30" FR4, EQ = Medium 50 15" FR4, EQ = Low 25 0 0.25 4.0 DATA RATE (Gbps) Figure 7. Total Jitter as a Function of Data Rate TOTAL RESIDUAL JITTER (ps) SUPPLY CURRENT (mA) PE = Off, EQ = Any 35 30 VCC = 3.3V TA = 25°C 0 0.4 0.8 1.2 0.85 1.00 VCC = 3.3V 45 20 0.70 150 PE = Medium, EQ = Any 25 0.55 Figure 8. Total Jitter as a Function of Input Amplitude 50 40 0.40 DIFFERENTIAL INPUT VOLTAGE (V) 1.6 TA = 25°C NRZ PRBS-7 EQ = Medium PE = Off 40" FR4 Stripline 125 100 75 30" FR4 Stripline 50 20" FR4 Stripline 25 0 2.0 0 0.8 FREQUENCY (GHz) 1.6 2.4 3.2 4.0 DATA RATE (Gbps) Figure 9. Power Supply Current as a Function of Frequency Figure 10. Total Jitter as a Function of Data Rate 150 TOTAL RESIDUAL JITTER (ps) VCC = 3.3V 125 100 TA = 25°C NRZ PRBS-7 3.125 Gbps PE = Off 75 30" FR4, EQ = Medium 50 25 0 0.25 15" FR4, EQ = Low 0.40 0.55 0.70 0.85 1.00 DIFFERENTIAL INPUT VOLTAGE (V) Figure 11. Total Jitter as a Function of Input Amplitude 8 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: DS25BR100 DS25BR100 www.ti.com SNLS217F – MARCH 2007 – REVISED APRIL 2013 APPLICATION INFORMATION DC Test Circuits VOH OUT+ IN+ Power Supply R D RL Power Supply IN- OUTVOL Figure 12. Differential Driver DC Test Circuit AC Test Circuits and Timing Diagrams OUT+ IN+ R Signal Generator D IN- RL OUT- Figure 13. Differential Driver AC Test Circuit NOTE DS25BR101 requires external 100Ω input termination. Figure 14. Propagation Delay Timing Diagram Figure 15. LVDS Output Transition Times Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: DS25BR100 9 DS25BR100 SNLS217F – MARCH 2007 – REVISED APRIL 2013 www.ti.com Pre-Emphasis and Equalization Test Circuits TEST CHANNEL CHARACTERIZATION BOARD 50: Microstrip TEST CHANNEL 50: Microstrip DS25BR100 L=4" L=4" L=4" L=4" 50: Microstrip 50: Microstrip PATTERN GENERATOR OSCILLOSCOPE Figure 16. Pre-emphasis and Equalization Performance Test Circuit NOTE DS25BR101 requires external 100Ω input termination. TEST CHANNEL CHARACTERIZATION BOARD 50: Microstrip DS25BR100 L=4" 50: Microstrip L=4" PATTERN GENERATOR OSCILLOSCOPE L=4" L=4" 50: Microstrip 50: Microstrip Figure 17. Equalization Performance Test Circuit NOTE DS25BR101 requires external 100Ω input termination. 50: MS 50: MS L=1" L=1" L=1" 50: MS L=1" 100: Diff. Stripline 50: MS Figure 18. Test Channel Description 10 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: DS25BR100 DS25BR100 www.ti.com SNLS217F – MARCH 2007 – REVISED APRIL 2013 Test Channel Loss Characteristics The test channel was fabricated with Polyclad PCL-FR-370-Laminate/PCL-FRP-370 Prepreg materials (Dielectric constant of 3.7 and Loss Tangent of 0.02). The edge coupled differential striplines have the following geometries: Trace Width (W) = 5 mils, Gap (S) = 5 mils, Height (B) = 16 mils. Test Channel Length (inches) Insertion Loss (dB) 500 MHz 750 MHz 1000 MHz 1250 MHz 1500 MHz 1560 MHz A 10 -1.2 -1.7 -2.0 -2.4 -2.7 -2.8 B 20 -2.6 -3.5 -4.1 -4.8 -5.5 -5.6 C 30 -4.3 -5.7 -7.0 -8.2 -9.4 -9.7 D 15 -1.6 -2.2 -2.7 -3.2 -3.7 -3.8 E 30 -3.4 -4.5 -5.6 -6.6 -7.7 -7.9 F 60 -7.8 -10.3 -12.4 -14.5 -16.6 -17.0 Device Operation INPUT INTERFACING The DS25BR100/101 accepts differential signals and allows simple AC or DC coupling. With a wide common mode range, the DS25BR100/101 can be DC-coupled with all common differential drivers (i.e. LVPECL, LVDS, CML). The following three figures illustrate typical DC-coupled interface to common differential drivers. The DS25BR100 inputs are internally terminated with a 100Ω resistor for optimal device performance, reduced component count, and minimum board space. External input terminations on the DS25BR101 need to be placed as close as possible to the device inputs to achieve equivalent AC performance. It is recommended to use SMT resistors sized 0402 or smaller and to keep the mounting distance to the DS25BR101 pins under 200 mils. When using the DS25BR101 in a limited multi-drop topology, any transmission line stubs should be kept very short to minimize any negative effects on signal quality. A single termination resistor or resistor network that matches the differential line impedance should be used. If DS25BR101 input pairs from two separate devices are to be connected to a single differential output, it is recommended to mount the DS25BR101 devices directly opposite of each other. One on top of the PCB and the other directly under the first on the bottom of the PCB keeps the distance between inputs equal to the PCB thickness. 100: Differential T-Line OUT+ IN+ LVDS DS25BR100 IN- OUT- Figure 19. Typical LVDS Driver DC-Coupled Interface to DS25BR100 Input CML3.3V or CML2.5V VCC 50: 100: Differential T-Line 50: OUT+ IN+ DS25BR100 OUT- IN- Figure 20. Typical CML Driver DC-Coupled Interface to DS25BR100 Input Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: DS25BR100 11 DS25BR100 SNLS217F – MARCH 2007 – REVISED APRIL 2013 LVPECL Driver OUT+ www.ti.com 100: Differential T-Line LVDS Receiver IN+ 100: OUT150-250: IN150-250: Figure 21. Typical LVPECL Driver DC-Coupled Interface to DS25BR100 Input NOTE DS25BR101 requires external 100Ω input termination. OUTPUT INTERFACING The DS25BR100/101 outputs signals are compliant to the LVDS standard. It can be DC-coupled to most common differential receivers. The following figure illustrates the typical DC-coupled interface to common differential receivers and assumes that the receivers have high impedance inputs. While most differential receivers have a common mode input range that can accommodate LVDS compliant signals, it is recommended to check the respective receiver's datasheet prior to implementing the suggested interface implementation. 100: Differential T-Line OUT+ DS25BR100 IN+ CML or LVPECL or LVDS 100: IN- OUT- Figure 22. Typical Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver 12 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: DS25BR100 DS25BR100 www.ti.com SNLS217F – MARCH 2007 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision E (April 2013) to Revision F • Page Changed layout of National Data Sheet to TI format .......................................................................................................... 12 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: DS25BR100 13 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) DS25BR100TSD/NOPB ACTIVE WSON NGQ 8 1000 RoHS & Green SN Level-3-260C-168 HR -40 to 85 2R100 DS25BR101TSD/NOPB ACTIVE WSON NGQ 8 1000 RoHS & Green SN Level-3-260C-168 HR -40 to 85 2R101 DS25BR101TSDE/NOPB ACTIVE WSON NGQ 8 250 RoHS & Green SN Level-3-260C-168 HR -40 to 85 2R101 DS25BR101TSDX/NOPB ACTIVE WSON NGQ 8 4500 RoHS & Green SN Level-3-260C-168 HR -40 to 85 2R101 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of