DS25CP104A, DS25CP114
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SNLS305C – AUGUST 2008 – REVISED MARCH 2013
DS25CP104A / DS25CP114 3.125 Gbps 4x4 LVDS Crosspoint Switch with Transmit
Pre-Emphasis and Receive Equalization
Check for Samples: DS25CP104A, DS25CP114
FEATURES
DESCRIPTION
•
The DS25CP104A and DS25CP114 are 3.125 Gbps
4x4 LVDS crosspoint switches optimized for highspeed signal routing and switching over lossy FR-4
printed circuit board backplanes and balanced cables.
Fully differential signal paths ensure exceptional
signal integrity and noise immunity. The non-blocking
architecture allows connections of any input to any
output or outputs. The switch configuration can be
accomplished via external pins or the System
Management Bus (SMBus) interface.
1
2
•
•
•
•
•
•
•
DC - 3.125 Gbps Low Jitter, Low Skew, Low
Power Operation
Pin and SMBus Configurable, Fully
Differential, Non-Blocking Architecture
Pin (Two Levels) and SMBus (Four Levels)
Selectable Pre-Emphasis and Equalization
Eliminate ISI Jitter
Wide Input Common Mode Range Enables
Easy Interface to CML and LVPECL Drivers
LOS Circuitry Detects Open Inputs Fault
Condition
On-Chip 100Ω Input and Output Termination
Minimizes Insertion and Return Losses,
Reduces Component Count, Minimizes Board
Space The DS25CP114 Eliminates the On-Chip
Input Termination for Added Design Flexibility.
8 kV ESD on LVDS I/O Pins Protects Adjoining
Components
Small 6 mm x 6 mm WQFN-40 Space Saving
Package
APPLICATIONS
•
•
•
SD/HD/3G HD SDI Routers
OC-48 / STM-16
InfiniBand and FireWire
The DS25CP104A and DS25CP114 feature four
levels (Off, Low, Medium, High) of transmit preemphasis (PE) and four levels (Off, Low, Medium,
High) of receive equalization (EQ) settable via the
SMBus interface. Off and Medium PE levels and Off
and Low EQ levels are settable with the external pins.
In addition, the SMBus circuitry enables the loss of
signal (LOS) monitors that can inform a system of the
presence of an open inputs condition (e.g.
disconnected cable).
Wide input common mode range allows the switch to
accept signals with LVDS, CML and LVPECL levels;
the output levels are LVDS. A very small package
footprint requires a minimal space on the board while
the flow-through pinout allows easy board layout. On
the DS25CP104A each differential input and output is
internally terminated with a 100Ω resistor to lower
return losses, reduce component count and further
minimize board space. For added design flexibility the
100Ω input terminations on the DS25CP114 have
been eliminated. This enables a designer to build
custom crosspoint configurations and distribution
circuits that require a limited multidrop signaling
topology.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2013, Texas Instruments Incorporated
DS25CP104A, DS25CP114
SNLS305C – AUGUST 2008 – REVISED MARCH 2013
www.ti.com
Typical Application
INPUT CARD
OUTPUT CARD
SD/HD/3G HD
Adaptive Equalizer
SD/HD/3G HD
Adaptive Equalizer
SD/HD/3G HD
Reclocker +
Cable Driver
BACKPLANES
DS25CP104
4 x 4 LVDS
Crosspoint Switch
DS25CP104
4 x 4 LVDS
Crosspoint Switch
SD/HD/3G HD
Reclocker +
Cable Driver
SD/HD/3G HD
Adaptive Equalizer
SD/HD/3G HD
Reclocker +
Cable Driver
SD/HD/3G HD
Adaptive Equalizer
SD/HD/3G HD
Reclocker +
Cable Driver
DS25CP104
4 x 4 LVDS
Crosspoint Switch
CROSSPOINT CARD
Table 1. Device Information
Device
Function
DS25CP104A
4x4 Crosspoint Switch
Internal 100Ω for LVDS inputs
Termination Option
Available Signal Conditioning
4 Levels: PE and EQ
DS25CP114
4x4 Crosspoint Switch
None: Requires external
termination
4 Levels : PE and EQ
Block Diagram
S00 ± S31
8
EQ0
IN0+
IN0-
PE0
EQ
PE
EQ1
IN1+
IN1-
IN2-
EQ
PE
4X4
IN3-
OUT1+
OUT1PE2
EQ
PE
EQ
PE
EQ3
IN3+
OUT0+
PE1
EQ2
IN2+
OUT0+
OUT2+
OUT2PE3
System
Management Bus
OUT3+
OUT3-
PWDN
ADDRn
SCL
SDA
EN_smb
4
DS25CP104A
2
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S00 ± S31
8
EQ0
IN0+
IN0-
PE0
EQ
PE
EQ
PE
OUT0+
OUT0+
EQ1
PE1
IN1+
IN1-
OUT1+
OUT1-
4X4
EQ2
IN2+
PE2
EQ
IN2-
OUT2+
PE
OUT2-
EQ3
PE3
IN3+
EQ
IN3-
OUT3+
PE
OUT3-
System
Management Bus
PWDN
ADDRn
SCL
EN_smb
SDA
4
DS25CP114
EQ0
EQ1
PWDN
S00 / SCL
S01 / SDA
S10 / ADDR0
S11 / ADDR1
S20 / ADDR2
S21 / ADDR3
PE0
40
39
38
37
36
35
34
33
32
31
Connection Diagram
IN0+
1
30
VDD
IN0-
2
29
OUT0+
VDD
3
28
OUT0-
27
OUT1+
26
OUT1-
25
VDD
24
OUT2+
8
23
OUT2-
IN3+
9
22
OUT3+
IN3-
10
21
OUT3-
15
16
17
18
19
20
VDD
GND
EN_smb
PE3
PE2
PE1
14
S31
VDD
(GND)
13
7
12
6
IN2-
S30
IN2+
DAP
EQ3
5
11
4
IN1-
EQ2
IN1+
DS25CP104A / DS25CP114 Pin Diagram
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: DS25CP104A DS25CP114
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PIN DESCRIPTIONS (1)
Pin Name
Pin
Number
IN0+, IN0- ,
IN1+, IN1-,
IN2+, IN2-,
IN3+, IN3-
I/O, Type
Pin Description
1, 2,
4, 5,
6, 7,
9, 10
I, LVDS
Inverting and non-inverting high speed LVDS input pins. These 4 input pairs
have a 100 Ohm differential input termination on the CP104A device. The
CP114 eliminates the input termination for added design flexibility.
OUT0+, OUT0-,
OUT1+, OUT1-,
OUT2+, OUT2-,
OUT3+, OUT3-
29,
27,
24,
22,
O, LVDS
Inverting and non-inverting high speed LVDS output pins. Each output pair has
an internal 100 Ohm termination to improve device return loss characteristics.
EQ0, EQ1,
EQ2, EQ3
40, 39,
11, 12
I, LVCMOS
Receive equalization level select pins. These pins are functional regardless of
the EN_smb pin state.
PE0, PE1,
PE2, PE3
31, 20,
19, 18
I, LVCMOS
Transmit pre-emphasis level select pins. These pins are functional regardless
of the EN_smb pin state.
EN_smb
17
I, LVCMOS
System Management Bus (SMBus) enable pin. The pin has an internal pull
down. When the pin is set to a [1], the device is in the SMBus mode. All
SMBus registers are reset when this pin is toggled. There is a 20k pulldown
device on this pin.
S00/SCL
37
I, LVCMOS
S01/SDA
36
I/O, LVCMOS
For EN_smb = [0], these pins select which LVDS input is routed to the OUT0.
In the SMBus mode, when the EN_smb = [1], these pins are SMBus clock
input and data input pins respectively.
S10/ADDR0,
S11/ADDR1
35,
34
I, LVCMOS
For EN_smb = [0], these pins select which LVDS input is routed to the OUT1.
In the SMBus mode, when the EN_smb = [1], these pins are the User-Set
SMBus Slave Address inputs.
S20/ADDR2,
S21/ADDR3
33,
32
I, LVCMOS
For EN_smb = [0], these pins select which LVDS input is routed to the OUT2.
In the SMBus mode, when the EN_smb = H, these pins are the User-Set
SMBus Slave Address inputs.
S30, S31
13, 14
I, LVCMOS
For EN_smb = [0], these pins select which LVDS input is routed to the OUT3.
In the SMBus mode, when the EN_smb = [1], these pins are non-functional
and should be tied to either logic H or L.
PWDN
38
I, LVCMOS
For EN_smb = [0], this is the power down pin. When the PWDN is set to a [0],
the device is in the power down mode. The SMBus circuitry can still be
accessed provided the EN_smb pin is set to a [1].
In the SMBus mode, the device is powered up by either setting the PWDN pin
to [1] OR by writing a [1] to the Control Register D[7] bit ( SoftPWDN). The
device will be powered down by setting the PWDN pin to [0] AND by writing a
[0] to the Control Register D[7] bit ( SoftPWDN).
VDD
3, 8,
15,25, 30
Power
Power supply pins.
GND
16, DAP
Power
Ground pin and a pad (DAP - die attach pad).
(1)
28,
26,
23,
21
Center DAP connection must be made to GND for optimum electrical and thermal performance.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
4
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SNLS305C – AUGUST 2008 – REVISED MARCH 2013
Absolute Maximum Ratings (1) (2)
−0.3V to +4V
Supply Voltage
LVCMOS Input Voltage
−0.3V to (VCC + 0.3V)
LVCMOS Output Voltage
−0.3V to (VCC + 0.3V)
−0.3V to +4V
LVDS Input Voltage
Differential Input Voltage |VID| (DS25CP104A)
1.0V
LVDS Differential Input Voltage (DS25CP114)
VCC + 0.6V
−0.3V to (VCC + 0.3V)
LVDS Output Voltage
LVDS Differential Output Voltage
0V to 1.0V
LVDS Output Short Circuit Current Duration
5 ms
Junction Temperature
+150°C
−65°C to +150°C
Storage Temperature Range
Lead Temperature Range
Soldering (4 sec.)
+260°C
Maximum Package Power Dissipation at 25°C
RTA0040A Package
4.65W
Derate RTA0040A Package
37.2 mW/°C above +25°C
Package Thermal Resistance
θJA
+26.9°C/W
θJC
+3.8°C/W
ESD Susceptibility
HBM
MM
(3)
CDM
(1)
(2)
(3)
(4)
(5)
≥8 kV
(4)
≥250V
(5)
≥1250V
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
Human Body Model, applicable std. JESD22-A114C
Machine Model, applicable std. JESD22-A115-A
Field Induced Charge Device Model, applicable std. JESD22-C101-C
Recommended Operating Conditions
Supply Voltage (VCC)
Receiver Differential Input Voltage (VID) (DS25CP104A only)
Min
Typ
Max
Units
3.0
3.3
3.6
V
1
V
+25
+85
°C
3.6
V
0
−40
Operating Free Air Temperature (TA)
SMBus (SDA, SCL)
DC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) (3)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
LVCMOS DC SPECIFICATIONS
VIH
High Level Input Voltage
2.0
VCC
V
VIL
Low Level Input Voltage
GND
0.8
V
(1)
(2)
(3)
The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not guaranteed.
Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
except VOD and ΔVOD.
Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions
at the time of product characterization and are not guaranteed.
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DC Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3)
Symbol
IIH
Parameter
Conditions
High Level Input Current
VIN = 3.6V
VCC = 3.6V
EN_smb pin
IIL
Low Level Input Current
VIN = GND
VCC = 3.6V
VCL
Input Clamp Voltage
ICL = −18 mA, VCC = 0V
VOL
Low Level Output Voltage
IOL= 4 mA
Min
Typ
Max
Units
0
±10
μA
40
175
250
μA
0
±10
μA
−0.9
−1.5
V
0.4
V
SDA pin
LVDS INPUT DC SPECIFICATIONS
VID
Input Differential Voltage (4)
VTH
Differential Input High Threshold
VTL
Differential Input Low Threshold
0
VCM = +0.05V or VCC-0.05V
0
−100
1
V
+100
mV
0
0.05
mV
VCC 0.05
V
±10
μA
VCMR
Input Common Mode Voltage Range
VID = 100 mV
IIN
Input Current (5)
VIN = +3.6V or 0V
VCC = 3.6V or 0V
CIN
Input Capacitance
Any LVDS Input Pin to GND
1.7
pF
RIN
Input Termination Resistor (6)
Between IN+ and IN-
100
Ω
±1
LVDS OUTPUT DC SPECIFICATIONS
VOD
Differential Output Voltage
250
ΔVOD
Change in Magnitude of VOD for Complimentary
Output States
VOS
Offset Voltage
RL = 100Ω
350
-35
1.05
RL = 100Ω
1.2
450
mV
35
mV
1.375
V
35
mV
ΔVOS
Change in Magnitude of VOS for Complimentary
Output States
IOS
Output Short Circuit Current
COUT
Output Capacitance
Any LVDS Output Pin to GND
1.2
pF
ROUT
Output Termination Resistor
Between OUT+ and OUT-
100
Ω
(7)
-35
OUT to GND
-35
-55
mA
OUT to VCC
7
55
mA
SUPPLY CURRENT
ICC1
Supply Current
PWDN = 0
40
50
mA
ICC2
Supply Current
PWDN = 1
PE = Off, EQ = Off
Broadcast (1:4) Mode
145
175
mA
ICC3
Supply Current
PWDN = 1
PE = Off, EQ = Off
Quad Buffer (4:4) Mode
157
190
mA
(4)
(5)
(6)
(7)
6
Input Differential Voltage (VID) The DS25CP104A limits input amplitude to 1 volt. The DS25CP114 supports any VID within the supply
voltage to GND range.
IIN is applied to both pins of the LVDS input pair at the same time.
Input Termination Resistor (RIN) The DS25CP104A provides an integrated 100 ohm input termination for each high speed LVDS pair.
The DS25CP114 eliminates this internal termination.
Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
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SNLS305C – AUGUST 2008 – REVISED MARCH 2013
AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2)
Symbol
Parameter
LVDS OUTPUT AC SPECIFICATIONS
Conditions
Min
Typ
Max
Units
480
650
ps
460
650
ps
(3)
tPLHD
Differential Propagation Delay Low to
High
tPHLD
Differential Propagation Delay High to
Low
tSKD1
Pulse Skew |tPLHD − tPHLD| ,
(4)
20
100
ps
Channel to Channel Skew ,
(5)
40
125
ps
50
200
ps
80
150
ps
80
150
ps
tSKD2
RL = 100Ω
(6)
tSKD3
Part to Part Skew ,
tLHT
Rise Time
tHLT
Fall Time
tON
Power Up Time
Time from PWDN =LH to OUTn active
6
20
μs
tOFF
Power Down Time
Time from PWDN =HL to OUTn inactive
8
25
ns
tSEL
Select Time
Time from Sn =LH or HL to new signal
at OUTn
8
12
ns
RL = 100Ω
JITTER PERFORMANCE WITH EQ = Off, PE = Off
tRJ1
tRJ2
(3)
(Figure 5)
Random Jitter (RMS Value)
No Test Channels
VID = 350 mV
VCM = 1.2V
Clock (RZ)
1.25 GHz
0.5
1.1
ps
1.5625 GHz
0.5
1.1
ps
Deterministic Jitter (Peak to Peak)
No Test Channels
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
2.5 Gbps
10
22
ps
10
27
ps
Total Jitter (Peak to Peak)
No Test Channels
VID = 350 mV
VCM = 1.2V
PRBS-23 (NRZ)
2.5 Gbps
0.07
0.11
UIP-P
3.125 Gbps
0.13
0.16
UIP-P
(7)
tDJ1
tDJ2
(8)
tTJ1
tTJ2
(9)
JITTER PERFORMANCE WITH EQ = Off, PE = Low
tRJ1A
tRJ2A
tDJ1A
tDJ2A
(3)
(Figure 6, Figure 9)
Random Jitter (RMS Value)
Test Channels A
VID = 350 mV
VCM = 1.2V
Clock (RZ)
1.25 GHz
0.5
1.1
ps
1.5625 GHz
0.5
1.1
ps
Deterministic Jitter (Peak to Peak)
Test Channels A
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
2.5 Gbps
10
22
ps
3.125 Gbps
10
27
ps
(7)
(8)
JITTER PERFORMANCE WITH EQ = Off, PE = Medium
tRJ1B
tRJ2B
tDJ1B
tDJ2B
tTJ1B
tTJ2B
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
3.125 Gbps
(3)
(Figure 6, Figure 9)
Random Jitter (RMS Value)
Test Channels B
VID = 350 mV
VCM = 1.2V
Clock (RZ)
1.25 GHz
0.5
1.1
ps
1.5625 GHz
0.5
1.1
ps
Deterministic Jitter (Peak to Peak)
Test Channels B
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
2.5 Gbps
12
30
ps
3.125 Gbps
12
30
ps
Total Jitter (Peak to Peak)
Test Channels B
VID = 350 mV
VCM = 1.2V
PRBS-23 (NRZ)
2.5 Gbps
0.08
0.10
UIP-P
3.125 Gbps
0.10
0.15
UIP-P
(7)
(8)
(9)
The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not guaranteed.
Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operating Conditions
at the time of product characterization and are not guaranteed.
Specification is guaranteed by characterization and is not tested in production.
tSKD1, |tPLHD − tPHLD|, Pulse Skew, is the magnitude difference in differential propagation delay time between the positive going edge and
the negative going edge of the same channel.
tSKD2, Channel to Channel Skew, is the difference in propagation delay (tPLHD or tPHLD) among all output channels in Broadcast mode
(any one input to all outputs).
tSKD3, Part to Part Skew, is defined as the difference between the same signal path of any two devices running at the same VCC and
within 5°C of each other within the operating temperature range.
Measured on a clock edge with a histogram and an accumulation of 1500 histogram hits. Input stimulus jitter is subtracted geometrically.
Tested with a combination of the 1100000101 (K28.5+ character) and 0011111010 (K28.5- character) patterns. Input stimulus jitter is
subtracted algebraically.
Measured on an eye diagram with a histogram and an accumulation of 3500 histogram hits. Input stimulus jitter is subtracted.
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AC Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)
Symbol
Parameter
JITTER PERFORMANCE WITH EQ = Off, PE = High
tRJ1C
tRJ2C
tDJ1C
tDJ2C
tRJ2D
tDJ1D
tDJ2D
tTJ1D
tTJ2D
tRJ2E
tDJ1E
tDJ2E
tDJ1F
tDJ2F
0.5
1.1
ps
1.5625 GHz
0.5
1.1
ps
Deterministic Jitter (Peak to Peak)
Test Channels C
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
2.5 Gbps
30
60
ps
3.125 Gbps
30
65
ps
(7)
(8)
(3)
(Figure 7, Figure 9)
Random Jitter (RMS Value)
Test Channels D
VID = 350 mV
VCM = 1.2V
Clock (RZ)
1.25 GHz
0.5
1.1
ps
1.5625 GHz
0.5
1.1
ps
Deterministic Jitter (Peak to Peak)
Test Channels D
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
2.5 Gbps
20
40
ps
3.125 Gbps
20
40
ps
Total Jitter (Peak to Peak)
Test Channels D
VID = 350 mV
VCM = 1.2V
PRBS-23 (NRZ)
2.5 Gbps
0.08
0.15
UIP-P
3.125 Gbps
0.09
0.20
UIP-P
(7)
(8)
(9)
(3)
(Figure 7, Figure 9)
Random Jitter (RMS Value)
Test Channels E
VID = 350 mV
VCM = 1.2V
Clock (RZ)
1.25 GHz
0.5
1.1
ps
1.5625 GHz
0.5
1.1
ps
Residual Deterministic Jitter (Peak to
Peak)
Test Channels E
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
2.5 Gbps
35
60
ps
3.125 Gbps
28
55
ps
(7)
(3)
(Figure 7, Figure 9)
Random Jitter (RMS Value)
Test Channels F
VID = 350 mV
VCM = 1.2V
Clock (RZ)
1.25 GHz
1.3
1.8
ps
1.5625 GHz
1.4
2.4
ps
Residual Deterministic Jitter (Peak to
Peak)
Test Channels F
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
2.5 Gbps
30
75
ps
3.125 Gbps
35
90
ps
(7)
(10)
JITTER PERFORMANCE WITH PE = Medium, EQ = Low
tRJ1G
tRJ2G
(11)
tDJ2G
(Figure 7, Figure 9)
Random Jitter (RMS Value)
Input Test Channels D
Output Test Channels B
VID = 350 mV
VCM = 1.2V
Clock (RZ)
1.25 GHz
0.5
1.1
ps
1.5625 GHz
0.5
1.1
ps
Deterministic Jitter (Peak to Peak)
Input Test Channels D
Output Test Channels B
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
2.5 Gbps
25
ps
3.125 Gbps
20
ps
(12)
tDJ1G
Units
1.25 GHz
JITTER PERFORMANCE WITH PE = Off, EQ = High
tRJ2F
Max
VID = 350 mV
VCM = 1.2V
Clock (RZ)
(8)
tRJ1F
Typ
(Figure 6, Figure 9)
JITTER PERFORMANCE WITH PE = Off, EQ = Medium
tRJ1E
Min
Random Jitter (RMS Value)
Test Channels C
JITTER PERFORMANCE WITH PE = Off, EQ = Low
tRJ1D
Conditions
(3)
(10)
SMBus AC SPECIFICATIONS
fSMB
SMBus Operating Frequency
10
tBUF
Bus free time between Stop and Start
Conditions
100
kHz
4.7
μs
tHD:SDA
Hold time after (Repeated) Start
Condition. After this period, the first clock
is generated.
4.0
μs
tSU:SDA
Repeated Start Condition setup time.
4.7
μs
tSU:SDO
Stop Condition setup time
4.0
μs
tHD:DAT
Data hold time
300
ns
(10) Tested with a combination of the 1100000101 (K28.5+ character) and 0011111010 (K28.5- character) patterns. Input stimulus jitter is
subtracted algebraically.
(11) Specification is guaranteed by characterization and is not tested in production.
(12) Measured on a clock edge with a histogram and an accumulation of 1500 histogram hits. Input stimulus jitter is subtracted geometrically.
8
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AC Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)
Symbol
Parameter
Conditions
Min
tSU:DAT
Data setup time
250
tTIMEOUT
Detect clock low timeout
25
tLOW
Clock low period
4.7
tHIGH
Clock high period
4.0
tPOR
Time in which a device must be
operational after power-on reset
Typ
Max
Units
35
ms
ns
μs
50
μs
500
ms
DC TEST CIRCUITS
¼ DS25CP104
Power Supply
VOH
OUT+
IN+
R
D
RL
Power Supply
IN-
OUTVOL
Figure 1. Differential Driver DC Test Circuit
AC Test Circuits and Timing Diagrams
¼ DS25CP104
OUT+
IN+
R
Signal Generator
IN-
D
RL
OUT-
DS25CP114 requires external 100Ω input termination.
Figure 2. Differential Driver AC Test Circuit
Figure 3. Propagation Delay Timing Diagram
Figure 4. LVDS Output Transition Times
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Pre-Emphasis and Equalization Test Circuits
DS25CP104
CHARACTERIZATION BOARD
50:
Microstrip
50:
Microstrip
¼ DS25CP104
L=4"
L=4"
L=4"
L=4"
50:
Microstrip
50:
Microstrip
PATTERN
GENERATOR
OSCILLOSCOPE
DS25CP114 requires external 100Ω input termination.
Figure 5. Jitter Performance Test Circuit
DS25CP104
CHARACTERIZATION BOARD
TEST
CHANNEL
¼ DS25CP104
50: MS
50: MS
L=4"
L=4"
PATTERN
GENERATOR
OSCILLOSCOPE
L=4"
L=4"
50: MS
50: MS
DS25CP114 requires external 100Ω input termination.
Figure 6. Pre-Emphasis Performance Test Circuit
TEST
CHANNEL
DS25CP104
CHARACTERIZATION BOARD
50: MS
¼ DS25CP104
50: MS
L=4"
L=4"
PATTERN
GENERATOR
OSCILLOSCOPE
L=4"
L=4"
50: MS
50: MS
DS25CP114 requires external 100Ω input termination.
Figure 7. Equalization Performance Test Circuit
TEST
CHANNEL
DS25CP104
CHARACTERIZATION BOARD
50:
Microstrip
¼ DS25CP104
TEST
CHANNEL
50:
Microstrip
L=4"
L=4"
L=4"
L=4"
50:
Microstrip
50:
Microstrip
PATTERN
GENERATOR
OSCILLOSCOPE
DS25CP114 requires external 100Ω input termination.
Figure 8. Pre-Emphasis and Equalization Performance Test Circuit
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50: MS
50: MS
L = A, B or C
L=1"
L=1"
L=1"
50: MS
L=1"
100: Diff.
Stripline
50: MS
Figure 9. Test Channel Block Diagram
Test Channel Loss Characteristics
The test channel was fabricated with Polyclad PCL-FR-370-Laminate/PCL-FRP-370 Prepreg materials (Dielectric
constant of 3.7 and Loss Tangent of 0.02). The edge coupled differential striplines have the following geometries:
Trace Width (W) = 5 mils, Gap (S) = 5 mils, Height (B) = 16 mils.
Test Channel
Length
(inches)
Insertion Loss (dB)
500 MHz
750 MHz
1000 MHz
1250 MHz
1500 MHz
1560 MHz
A
10
-1.2
-1.7
-2.0
-2.4
-2.7
-2.8
B
20
-2.6
-3.5
-4.1
-4.8
-5.5
-5.6
C
30
-4.3
-5.7
-7.0
-8.2
-9.4
-9.7
D
15
-1.6
-2.2
-2.7
-3.2
-3.7
-3.8
E
30
-3.4
-4.5
-5.6
-6.6
-7.7
-7.9
F
60
-7.8
-10.3
-12.4
-14.5
-16.6
-17.0
Functional Description
The DS25CP104A and DS25CP114 are 3.125 Gbps 4x4 LVDS digital crosspoint switch optimized for high-speed
signal routing and switching over lossy FR-4 printed circuit board backplanes and balanced cables. The
DS25CP104A and DS25CP114 operate in two modes: Pin Mode (EN_smb = 0) and SMBus Mode (EN_smb = 1).
When in the Pin Mode, the switch is fully configurable with external pins. This is possible with two input select
pins per output (e.g. S00 and S01 pins for OUT0). There is also one transmit pre-emphasis (PE) level select pin
per output for switching the PE levels between Medium and Off settings and one receive equalization (EQ) level
select pin per input for switching the EQ levels between Low and Off settings.
In the Pin Mode, feedback from the LOS (Loss Of Signal) monitor circuitry is not available (there is not an LOS
output pin).
When in the SMBus Mode, the full switch configuration, four levels of transmit pre-emphasis (Off, Low, Medium
and High), four levels of receive equalization (Off, Low, Medium and High) and SoftPWDN can be programmed
via the SMBus interface. In addition, by using the SMBus interface, a user can obtain the feedback from the builtin LOS circuitry which detects an open inputs fault condition.
In the SMBus Mode, the S00 and S01 pins become SMBus clock (SCL) input and data (SDA) input pins
respectively; the S10, S11, S21 and S21 pins become the User-Set SMBus Slave Address input pins (ADDR0, 1,
2 and 3) while the S30 and S31 pins become non-functional (tieing these two pins to either H or L is
recommended if the device will function only in the SMBus mode).
In the SMBus Mode, the PE and EQ select pins as well as the PWDN pin remain functional. How these pins
function in each mode is explained in the following sections.
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OPERATION IN PIN MODE
Power Up
In the Pin Mode, when the power is applied to the device power suppy pins, the DS25CP104A/DS25CP114
enters the Power Up mode when the PWDN pin is set to logic H. When in the Power Down mode (PWDN pin is
set to logic L), all circuitry is shut down except the minimum required circuitry for the LOS and SMBus Slave
operation.
Switch Configuration
In the Pin Mode, the DS25CP104A/DS25CP114 operates as a fully pin-configurable crosspoint switch. The
following truth tables illustrate how the swich can be configured with external pins.
Switch Configuration Truth Tables
Table 2. Input Select Pins Configuration for the Output OUT0
S01
S00
INPUT SELECTED
0
0
IN0
0
1
IN1
1
0
IN2
1
1
IN3
Table 3. Input Select Pins Configuration for the Output OUT1
S11
S10
INPUT SELECTED
0
0
IN0
0
1
IN1
1
0
IN2
1
1
IN3
Table 4. Input Select Pins Configuration for the Output OUT2
12
S21
S20
INPUT SELECTED
0
0
IN0
0
1
IN1
1
0
IN2
1
1
IN3
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Table 5. Input Select Pins Configuration for the Output OUT3
S31
S30
INPUT SELECTED
0
0
IN0
0
1
IN1
1
0
IN2
1
1
IN3
Setting Pre-Emphasis Levels
The DS25CP104A/DS25CP114 has one PE level select pin per output for setting the transmit pre-emphasis to
either Medium or Off level. The following is the transmit pre-emphasis truth table.
Table 6. Transmit Pre-Emphasis Truth Table
OUTPUT OUTn, n = {0, 1, 2, 3}
Pre-Emphasis Control Pin (PEn) State
Pre-Emphasis Level
0
Off
1
Medium
Setting Equalization Levels
The DS25CP104A/DS25CP114 has one EQ level select pin per input for setting the receive equalization to either
Low or Off level. The following is the receive equalization truth table.
Table 7. Receive Equalization Truth Table
INPUT INn, n = {0, 1, 2, 3}
Equalization Control Pin (EQn) State
Equalization Level
0
Off
1
Low
OPERATION IN SMBUS MODE
The DS25CP104A/DS25CP114 operates as a slave on the System Management Bus (SMBus) when the
EN_smb pin is set to a high (1). Under these conditions, the SCL pin is a clock input while the SDA pin is a serial
data input pin.
Device Address
Based on the SMBus 2.0 specification, the DS25CP104A/DS25CP114 has a 7-bit slave address. The three most
significant bits of the slave address are hard wired inside the DS25CP104A/DS25CP114 and are “101”. The four
least significant bits of the address are assigned to pins ADDR3-ADDR0 and are set by connecting these pins to
GND for a low (0) or to VCC for a high (1). The complete slave address is shown in the following table:
Table 8. Slave Address
1
0
1
ADDR3
ADDR2
ADDR1
MSB
ADDR0
LSB
This slave address configuration allows up to sixteen DS25CP104A/DS25CP114 devices on a single SMBus
bus.
Transfer of Data via the SMBus
During normal operation the data on SDA must be stable during the time when SCK is high.
There are three unique states for the SMBus:
START: A HIGH to LOW transition on SDA while SCK is high indicates a message START condition.
STOP: A LOW to HIGH transition on SDA while SCK is high indicates a message STOP condition.
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IDLE: If SCK and SDA are both high for a time exceeding tBUF from the last detected STOP condition or if they
are high for a total exceeding the maximum specification for tHIGH then the bus will transfer to the IDLE state.
SMBus Transactions
A transaction begins with the host placing the DS25CP104A SMBus into the START condition, then a byte (8
bits) is transferred, MSB first, followed by a ninth ACK bit. ACK bits are ‘0’ to signify an ACK, or ‘1’ to signify
NACK, after this the host holds the SCL line low, and waits for the receiver to raise the SDA line as an
ACKnowledge that the byte has been received.
Writing to a Register
To write a register, the following protocol is used (see SMBus 2.0 specification):
1) The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
2) The Device (Slave) drives an ACK bit (“0”).
3) The Host drives the 8-bit Register Address.
4) The Device drives an ACK bit (“0”).
5) The Host drives the 8-bit data byte.
6) The Device drives an ACK bit “0”.
7) The Host drives a STOP condition.
The WRITE transaction is completed, the bus goes Idle and communication with other SMBus devices may now
occur.
Reading From a Register
To read a register, the following protocol is used (see SMBus 2.0 specification):
1) The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
2) The Device (Slave) drives an ACK bit (“0”).
3) The Host drives the 8-bit Register Address.
4) The Device drives an ACK bit (“0”).
5) The Host drives a START condition.
6) The Host drives the 7-bit SMBus Address, and a “1” indicating a READ.
7) The Device drives an ACK bit “0”.
8) The Device drives the 8-bit data value (register contents).
9) The Host drives a NACK bit “1” indicating end of READ transfer.
10) The Host drives a STOP condition.
The READ transaction is completed, the bus goes Idle and communication with other SMBus devices may now
occur.
Register Descriptions
There are five data registers in the DS25CP104A/DS25CP114 accessible via the SMBus interface.
Table 9. SMBus Data Registers
Address
(hex)
14
Name
Access
Description
0
Switch Configuration
R/W
Switch Configuration Register
1
PE Level Select
R/W
Transmit Pre-emphasis Level Select Register
2
EQ Level Select
R/W
Receive Equalization Level Select Register
3
Control
R/W
Powerdown, LOS Enable and Pin Control Register
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Table 9. SMBus Data Registers (continued)
Address
(hex)
Access
LOS
Description
RO
Loss Of Signal (LOS) Reporting Register
ADDRn
4
Name
4
SCL
SMBus
Interface
SDA
PE Level
Select Register
EN_smb
Switch
Configuration
Register
EQ Level
Select Register
Control
Register
LOS
Register
Figure 10. Registers Block Diagram
SWITCH CONFIGURATION REGISTER
The Switch Configuration register is utilized to configure the switch. The following two tables show the Switch
Configuration Register mapping and associated truth table.
Switch Configuration Register Mapping
Default
Bit Name
D[1:0]
Bit
00
Input Select 0
Access
R/W
Description
Selects which input is routed to the OUT0.
D[3:2]
00
Input Select 1
R/W
Selects which input is routed to the OUT1.
D[5:4]
00
Input Select 2
R/W
Selects which input is routed to the OUT2.
D[7:6]
00
Input Select 3
R/W
Selects which input is routed to the OUT3.
Switch Configuration Register Truth Table
D1
D0
Input Routed to the OUT0
0
0
IN0
0
1
IN1
1
0
IN2
1
1
IN3
The switch configuration logic has a SmartPWDN circuitry which automatically optimizes the device's power
consumption based on the switch configuration (i.e. It places unused I/O blocks and other unused circuitry in the
power down state).
PE LEVEL SELECT REGISTER
The PE Level Select register selects the pre-emphasis level for each of the outputs. The following two tables
show the register mapping and associated truth table.
PE Level Select Register Table
Bit
D[1:0]
Default
Bit Name
00
PE Level Select
0
Access
R/W
Description
Sets pre-emphasis level on the OUT0.
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PE Level Select Register Table (continued)
Default
Bit Name
D[3:2]
Bit
00
PE Level Select
1
Access
R/W
Description
Sets pre-emphasis level on the OUT1.
D[5:4]
00
PE Level Select
2
R/W
Sets pre-emphasis level on the OUT2.
D[7:6]
00
PE Level Select
3
R/W
Sets pre-emphasis level on the OUT3.
PE Level Select Register Truth Table
D1
D0
0
0
Pre-Emphasis Level for the OUT0
Off
0
1
Low
1
0
Medium
1
1
High
EQ LEVEL SELECT REGISTER
The EQ Level Select register selects the equalization level for each of the inputs. The following two tables show
the register mapping and associated truth table.
Default
Bit Name
Access
D[1:0]
Bit
00
EQ Level
Select 0
R/W
Description
Sets equalization level on the IN0.
D[3:2]
00
EQ Level
Select 1
R/W
Sets equalization level on the IN1.
D[5:4]
00
EQ Level
Select 2
R/W
Sets equalization level on the IN2.
D[7:6]
00
EQ Level
Select 3
R/W
Sets equalization level on the IN3.
Table 10. EQ Level Select Register Truth Table
D1
D0
Equalization Level for the IN0
0
0
Off
0
1
Low
1
0
Medium
1
1
High
CONTROL REGISTER
The Control register enables SoftPWDN control, individual output power down (PWDNn) control, LOS Circuitry
Enable control, PE Level Select Enable control and EQ Level Select Enable control via the SMBus. The following
table shows the register mapping.
Table 11. Register Mapping Table
Bit
Default
Bit Name
1111
PWDNn
R/W
Writing a [0] to the bit D[n] will power down the output OUTn when either the
PWDN pin OR the Control Register bit D[7] (SoftPWDN) is set to a high [1].
D[4]
0
Ignore_External_
EQ
R/W
Writing a [1] to the bit D[4] will ignore the state of the external EQ pins and
will allow setting the EQ levels via the SMBus interface.
D[5]
0
Ignore_External_
PE
R/W
Writing a [1] to the bit D[5] will ignore the state of the external PE pins and will
allow setting the PE levels via the SMBus interface.
D[6]
0
EN_LOS
R/W
Writing a [1] to the bit D[6] will enable the LOS circuitry and receivers on all
four inputs. The SmartPWDN circuitry will not disable any of the inputs nor
any supporting LOS circuitry depending on the switch configuration.
D[3:0]
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Description
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Table 11. Register Mapping Table (continued)
Bit
Default
Bit Name
Access
D[7]
0
SoftPWDN
R/W
Description
Writing a [0] to the bit D[7] will place the device into the power down mode.
This pin is ORed together with the PWDN pin.
Table 12. Power Modes Truth Table
PWDN
SoftPWDN
PWDNn
0
0
x
Power Mode
Power Down Mode. In this mode, all
circuitry is shut down except the minimum
required circuitry for the LOS and SMBus
Slave operation. The SMBus circuitry
allows enabling the LOS circuitry and
receivers on all inputs in this mode by
setting the EN_LOS bit to a [1].
0
1
1
1
0
1
x
x
x
Power Up Mode. In this mode, the
SmartPWDN circuitry will automatically
power down any unused I/O and logic
blocks and other supporting circuitry
depending on the switch configuration.
An output will be enabled only when the
SmartPWDN circuitry indicates that that
particular output is needed for the
particular switch configuration and the
respective PWDNn bit has logic high [1].
An input will be enabled when the
SmartPWDN circuitry indicates that that
particular input is needed for the
particular switch configuration or the
EN_LOS bit is set to a [1].
LOS REGISTER
The LOS register reports an open inputs fault condition for each of the inputs. The following table shows the
register mapping.
Bit
Default
Bit Name
D[0]
0
LOS0
RO
Reading a [0] from the bit D[0] indicates an open inputs fault condition on the
IN0. A [1] indicates presence of a valid signal.
D[1]
0
LOS1
RO
Reading a [0] from the bit D[1] indicates an open inputs fault condition on the
IN1. A [1] indicates presence of a valid signal.
D[2]
0
LOS2
RO
Reading a [0] from the bit D[2] indicates an open inputs fault condition on the
IN2. A [1] indicates presence of a valid signal.
D[3]
0
LOS3
RO
Reading a [0] from the bit D[3] indicates an open inputs fault condition on the
IN3. A [1] indicates presence of a valid signal.
0000
Reserved
RO
Reserved for future use. Returns undefined value when read.
D[7:4]
Access
Description
INPUT INTERFACING
The DS25CP104A/DS25CP114 accepts differential signals and allows simple AC or DC coupling. With a wide
common mode range, the DS25CP104A/DS25CP114 can be DC-coupled with all common differential drivers
(i.e. LVPECL, LVDS, CML). The following three figures illustrate typical DC-coupled interface to common
differential drivers.
The DS25CP104A inputs are internally terminated with a 100Ω resistor for optimal device performance, reduced
component count, and minimum board space. External input terminations on the DS25CP114 need to be placed
as close as possible to the device inputs to achieve equivalent AC performance. When all four inputs are utilized
it may be necessary to alternate between the top and bottom layers to achieve the minimum device input to
termination distance. It is recommended that SMT resistors sized 0402 or smaller be used and the mounting
distance to the DS25CP114 pins kept under 200 mils.
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When using the DS25CP114 in a limited multi-drop topology, any transmission line stubs should be kept very
short to minimize any negative effects on signal quality. A single termination resistor or resistor network that
matches the differential line impedance should be used. If DS25CP114 input pairs from two separate devices are
to be connected to a single differential output, it is recommended that the DS25CP114 devices are mounted
directly opposite of each other. One on top of the PCB and the other directly under the first on the bottom of the
PCB, this keeps the distance between inputs equal to the PCB thickness.
LVDS
Driver
DS25CP104
Receiver
100: Differential T-Line
OUT+
IN+
100:
IN-
OUT-
Figure 11. Typical LVDS Driver DC-Coupled Interface to DS25CP104A Input
CML3.3V or CML2.5V
Driver
VCC
50:
DS25CP104
Receiver
100: Differential T-Line
50:
OUT+
IN+
100:
IN-
OUT-
Figure 12. Typical CML Driver DC-Coupled Interface to DS25CP104A Input
LVPECL
Driver
OUT+
100: Differential T-Line
LVDS
Receiver
IN+
100:
OUT150-250:
IN150-250:
DS25CP114 requires external 100Ω input termination.
Figure 13. Typical LVPECL Driver DC-Coupled Interface to DS25CP104A Input
OUTPUT INTERFACING
The DS25CP104A/DS25CP114 outputs signals that are compliant to the LVDS standard. Its outputs can be DCcoupled to most common differential receivers. The following figure illustrates a typical DC-coupled interface to
common differential receivers and assumes that the receivers have high impedance inputs. While most
differential receivers have a common mode input range that can accommodate LVDS compliant signals, it is
recommended to check the respective receiver's data sheet prior to implementing the suggested interface
implementation.
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DS25CP104
Driver
Differential
Receiver
100: Differential T-Line
OUT+
IN+
CML or
LVPECL or
LVDS
100:
100:
IN-
OUT-
Figure 14. Typical Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver
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Typical Performance Characteristics
60
150
VCC = 3.3V
40
TA = 25°C
NRZ PRBS7
EQ = Med
125
RESIDUAL JITTER (ps)
50
TOTAL JITTER (ps)
VCC = 3.3V
TA = 25°C
NRZ PRBS-7
EQ = Off
PE = Off
30
20
100
30" FR4 Stripline
75
50
10
25
0
0
20" FR4 Stripline
0
0.8
1.6
2.4
3.2
4.0
0
0.8
DATA RATE (Gbps)
4.0
150
VCC = 3.3V
VCC = 3.3V
TA = 25°C
NRZ PRBS7
EQ = Low
TA = 25°C
NRZ PRBS7
EQ = High
125
RESIDUAL JITTER (ps)
125
RESIDUAL JITTER (ps)
3.2
Figure 16. Residual Jitter as a Function of Data Rate, FR4
Stripline Length and EQ Level
150
100
20" FR4 Stripline
75
50
25
100
75
50
50" FR4 Stripline
40" FR4 Stripline
25
10" FR4 Stripline
0
0
0.8
1.6
2.4
3.2
0
4.0
0
0.8
DATA RATE (Gbps)
1.6
2.4
3.2
4.0
DATA RATE (Gbps)
Figure 17. Residual Jitter as a Function of Data Rate, FR4
Stripline Length and EQ Level
Figure 18. Residual Jitter as a Function of Data Rate, FR4
Stripline Length and EQ Level
150
150
VCC = 3.3V
VCC = 3.3V
TA = 25°C
NRZ PRBS7
PEM = Low
TA = 25°C
NRZ PRBS7
PEM = High
125
RESIDUAL JITTER (ps)
125
RESIDUAL JITTER (ps)
2.4
DATA RATE (Gbps)
Figure 15. Total Jitter as a Function of Data Rate
100
75
30" FR4 Stripline
50
25
100
40" FR4 Stripline
75
50
25
10" FR4 Stripline
0
0
0.8
1.6
20" FR4 Stripline
2.4
3.2
4.0
30" FR4 Stripline
0
0
DATA RATE (Gbps)
Figure 19. Residual Jitter as a Function of Data Rate, FR4
Stripline Length and PE Level
20
1.6
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0.8
1.6
2.4
3.2
4.0
DATA RATE (Gbps)
Figure 20. Residual Jitter as a Function of Data Rate, FR4
Stripline Length and PE Level
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: DS25CP104A DS25CP114
DS25CP104A, DS25CP114
www.ti.com
SNLS305C – AUGUST 2008 – REVISED MARCH 2013
Typical Performance Characteristics (continued)
150
240
VCC = 3.3V
100
40" FR4 Stripline
75
30" FR4 Stripline
50
TA = 25°C
NRZ PRBS7
220
SUPPLY CURRENT (mA)
125
RESIDUAL JITTER (ps)
VCC = 3.3V
TA = 25°C
NRZ PRBS7
PEM = Med
25
200
PEM 9
180
PEM 6
PEM 3
160
PEM 0
140
20" FR4 Stripline
0
120
0
0.8
1.6
2.4
3.2
4.0
0
0.8
1.6
2.4
3.2
4.0
DATA RATE (Gbps)
DATA RATE (Gbps)
Figure 21. Residual Jitter as a Function of Data Rate, FR4
Stripline Length and PE Level
Figure 22. Supply Current as a Function of Data Rate and
PE Level
Figure 23. A 2.5 Gbps NRZ PRBS-23 without PE
After 30" Differential FR-4 Stripline
H: 75 ps / DIV, V: 100 mV / DIV
Figure 24. A 2.5 Gbps NRZ PRBS-23 with High PE
After 2" Differential FR-4 Microstrip
H: 75 ps / DIV, V: 100 mV / DIV
Figure 25. A 2.5 Gbps NRZ PRBS-23 with High PE
After 30" Differential FR-4 Stripline
H: 75 ps / DIV, V: 100 mV / DIV
Figure 26. A 3.125 Gbps NRZ PRBS-23 without PE
After 30" Differential FR-4 Stripline
H: 50 ps / DIV, V: 100 mV / DIV
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: DS25CP104A DS25CP114
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21
DS25CP104A, DS25CP114
SNLS305C – AUGUST 2008 – REVISED MARCH 2013
www.ti.com
Typical Performance Characteristics (continued)
22
Figure 27. A 3.125 Gbps NRZ PRBS-23 with High PE
After 2" Differential FR-4 Microstrip
H: 50 ps / DIV, V: 100 mV / DIV
Figure 28. A 3.125 Gbps NRZ PRBS-23 with High PE
After 30" Differential FR-4 Stripline
H: 50 ps / DIV, V: 100 mV / DIV
Figure 29. A 2.5 Gbps NRZ PRBS-23 without EQ
After 60" Differential FR-4 Stripline
H: 75 ps / DIV, V: 100 mV / DIV
Figure 30. A 2.5 Gbps NRZ PRBS-23 with High EQ
After 60" Differential FR-4 Stripline
H: 75 ps / DIV, V: 100 mV / DIV
Figure 31. A 3.125 Gbps NRZ PRBS-23 without EQ
After 60" Differential FR-4 Stripline
H: 50 ps / DIV, V: 100 mV / DIV
Figure 32. A 3.125 Gbps NRZ PRBS-23 with High EQ
After 60" Differential FR-4 Stripline
H: 50 ps / DIV, V: 100 mV / DIV
Submit Documentation Feedback
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: DS25CP104A DS25CP114
DS25CP104A, DS25CP114
www.ti.com
SNLS305C – AUGUST 2008 – REVISED MARCH 2013
REVISION HISTORY
Changes from Revision B (March 2013) to Revision C
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 22
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: DS25CP104A DS25CP114
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23
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
DS25CP104ATSQ/NOPB
ACTIVE
WQFN
RTA
40
250
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
2CP104AS
DS25CP104ATSQX/NOPB
ACTIVE
WQFN
RTA
40
2500
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
2CP104AS
DS25CP114TSQ/NOPB
ACTIVE
WQFN
RTA
40
1000
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
2CP114SQ
DS25CP114TSQE/NOPB
ACTIVE
WQFN
RTA
40
250
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
2CP114SQ
DS25CP114TSQX/NOPB
ACTIVE
WQFN
RTA
40
2500
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
2CP114SQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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