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DS25MB100TSQX/NOPB

DS25MB100TSQX/NOPB

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    WQFN-36_6X6MM-EP

  • 描述:

    IC MULTIPLEXER 1CH 36WQFN

  • 数据手册
  • 价格&库存
DS25MB100TSQX/NOPB 数据手册
Sample & Buy Product Folder Support & Community Tools & Software Technical Documents DS25MB100 SNLS243H – SEPTEMBER 2006 – REVISED MARCH 2016 DS25MB100 2.5 Gbps 2:1/1:2 CML Mux/Buffer With Transmit Pre-Emphasis and Receive Equalization 1 Features 3 Description • • The DS25MB100 device is a signal conditioning 2:1 multiplexer and 1:2 fan-out buffer designed for use in backplane-redundancy or cable driving applications. Signal conditioning features include continuous time linear equalization (CTLE) and programmable output pre-emphasis that enable data communication in FR4 backplane up to 2.5 Gbps. Each input stage has a fixed equalizer to reduce ISI distortion from board traces. 1 • • • • • • • • • • 2:1 Multiplexer and 1:2 Buffer 0.25-Gbps to 2.5-Gbps Fully Differential Data Paths Fixed Input Equalization Programmable Output Pre-Emphasis Independent Pre-Emphasis Controls Programmable Loopback Modes On-Chip Terminations ESD Rating of 6-kV HBM 3.3-V Supply Low power, 0.45 W Typical Lead-Less WQFN-36 Package −40°C to +85°C Operating Temperature Range 2 Applications • • • Backplane Drivers or Cable Driver Redundancy and Signal Conditioning Applications CPRI/OBSAI All output drivers have four selectable levels of preemphasis to compensate for transmission losses from long FR4 backplane or cable attenuation reducing deterministic jitter. The pre-emphasis levels can be independently controlled for the line-side and switchside drivers. The internal loopback paths from switchside input to switch-side output enable at-speed system testing. All receiver inputs are internally terminated with 100-Ω differential terminating resistors. All driver outputs are internally terminated with 50-Ω terminating resistors to VCC. Device Information(1) PART NUMBER DS25MB100 PACKAGE WQFN (36) BODY SIZE (NOM) 6.00 mm × 6.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Block Diagram Switch Side Line Side EQ OUT+- IN0 +EQS DE_L MUX EQ IN1 +LB0 OUT0 +- DE_S IN + - OUT1 +- EQ DE_S LB1 EQL DEL _0 DE_L DEL_1 Pre- emphasis DES_0 Control DES_1 DE _S VCC GND RSV All CML inputs and outputs must be AC coupled for optimal performance. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DS25MB100 SNLS243H – SEPTEMBER 2006 – REVISED MARCH 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4 4 5 5 5 7 8 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics .......................................... Typical Characteristics .............................................. Parameter Measurement Information .................. 8 Detailed Description .............................................. 9 8.1 Overview ................................................................... 9 8.2 Functional Block Diagram ......................................... 9 8.3 Feature Description................................................... 9 9 Application and Implementation ........................ 12 9.1 Application Information............................................ 12 9.2 Typical Application ................................................. 12 10 Power Supply Recommendations ..................... 16 11 Layout................................................................... 16 11.1 Layout Guidelines ................................................. 16 11.2 Layout Example .................................................... 16 12 Device and Documentation Support ................. 18 12.1 12.2 12.3 12.4 12.5 Documentation Support ........................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 18 18 18 18 18 13 Mechanical, Packaging, and Orderable Information ........................................................... 18 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision G (April 2013) to Revision H Page • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1 • Changed thermal information per latest modeling results ..................................................................................................... 5 • Changed board trace attenuation estimate, per recent measurement ................................................................................ 14 Changes from Revision F (April 2013) to Revision G • 2 Page Changed layout of National Data Sheet to TI format ............................................................................................................. 1 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: DS25MB100 DS25MB100 www.ti.com SNLS243H – SEPTEMBER 2006 – REVISED MARCH 2016 5 Pin Configuration and Functions GND IN− IN+ V OUT− OUT+ GND LB0 35 34 33 32 31 30 29 28 CC   EQS 36 NJK Package 36-Pin WQFN Top View DES1 1 27 DEL1 GND 2 26 LB1 OUT0+ 3 25 IN1+ OUT0− 4 24 IN1− 23 V V CC   GND 5 CC   MUX   CC V GND   CC V 18 19 DEL0 9 17 GND RSV GND 16 20 GND 8 15 GND 14 OUT1− 13 21 12 7 GND IN0− 11 OUT1+ EQL 22 10 6 DES0 IN0+ Pin Functions (1) PIN NAME NO. TYPE (2) DESCRIPTION LINE SIDE HIGH SPEED DIFFERENTIAL IO's IN+ IN− 33 34 I Inverting and noninverting differential inputs at the line side. IN+ and IN− have an internal 50 Ω connected to an internal reference voltage. See Figure 8. OUT+ OUT− 30 31 O Inverting and noninverting differential outputs at the line side. OUT+ and OUT− have an internal 50 Ω connected to VCC. See Figure 7. SWITCH SIDE HIGH SPEED DIFFERENTIAL IO's IN0+ IN0− 6 7 I Inverting and noninverting differential inputs to the mux at the switch side. IN0+ and IN0− have an internal 50 Ω connected to an internal reference voltage. See Figure 8. IN1+ IN1− 25 24 I Inverting and noninverting differential inputs to the mux at the switch side. IN1+ and IN1− have an internal 50 Ω connected to an internal reference voltage. See Figure 8. OUT0+ OUT0− 3 4 O Inverting and noninverting differential outputs at the switch side. OUT0+ and OUT0− have an internal 50 Ω connected to VCC. See Figure 7. OUT1+ OUT1− 22 21 O Inverting and noninverting differential outputs at the switch side. OUT1+ and OUT1− have an internal 50 Ω connected to VCC. See Figure 7. I DEL_0 and DEL_1 select the output pre-emphasis of the line side drivers (OUT±). DEL_0 and DEL_1 are internally pulled high. CONTROL (3.3-V LVCMOS) DEL_0 DEL_1 (1) (2) 18 27 All CML Inputs or Outputs must be AC coupled. I = Input, O = Output, P = Power Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: DS25MB100 3 DS25MB100 SNLS243H – SEPTEMBER 2006 – REVISED MARCH 2016 www.ti.com Pin Functions(1) (continued) PIN TYPE (2) DESCRIPTION NAME NO. DES_0 DES_1 10 1 I DES_0 and DES_1 select the output pre-emphasis of the switch side drivers (OUT0±, OUT1±). DES_0 and DES_1 are internally pulled high. EQL 11 I A logic low enables the input equalizer on the line side. EQL is internally pulled high. Default is with EQ disabled. EQS 36 I A logic low enables the input equalizer on the switch side. EQS is internally pulled high. Default is with EQ disabled. LB0 28 I A logic low at LB0 enables the internal loopback path from IN0± to OUT0±. LB0 is internally pulled high. LB1 26 I A logic low at LB1 enables the internal loopback path from IN1± to OUT1±. LB1 is internally pulled high. MUX 19 I A logic low at MUX selects IN1±. MUX is internally pulled high. Default state for MUX is IN0±. RSV 17 I Reserve pin to support factory testing. This pin can be left open, or tied to GND, or tied to GND through an external pulldown resistor. 2, 8, 9, 12, 14, 16, 20, 29, 35 P Ground reference. Each ground pin must be connected to the ground plane through a low inductance path, typically with a via located as close as possible to the landing pad of the GND pin. GND P DAP is the metal contact at the bottom side, located at the center of the WQFN package. It must be connected to the GND plane with at least 16 via to lower the ground impedance and improve the thermal performance of the package. P VCC = 3.3 V ± 5%. Each VCC pin must be connected to the VCC plane through a low inductance path, typically with a via located as close as possible to the landing pad of the VCC pin. It is recommended to have a 0.01-μF or 0.1-μF, X7R, size-0402 bypass capacitor from each VCC pin to ground plane. POWER GND GND_DAP 5, 13, 15, 23, 32 VCC 6 Specifications 6.1 Absolute Maximum Ratings (1) (2) MIN MAX UNIT Supply voltage (VCC) –0.3 4 V CMOS/TTL input voltage –0.3 VCC + 0.3 V –0.3 VCC + 0.3 V 260 °C 150 °C 150 °C CML input/output voltage Lead temperature Soldering, 4 seconds Junction temperature Storage temperature, Tstg (1) (2) –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications. 6.2 ESD Ratings VALUE Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 V(ESD) (1) (2) 4 Electrostatic discharge (1) UNIT ±6000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1250 Machine model (MM) ±350 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: DS25MB100 DS25MB100 www.ti.com SNLS243H – SEPTEMBER 2006 – REVISED MARCH 2016 6.3 Recommended Operating Conditions Supply voltage (VCC – GND) MIN NOM MAX 3.135 3.3 3.465 Supply noise amplitude (10 Hz to 2 GHz) Ambient temperature –40 Case temperature UNIT V 100 mVPP 85 °C 100 °C 6.4 Thermal Information DS25MB100 THERMAL METRIC (1) NJK (WQFN) UNIT 36 PINS RθJA Junction-to-ambient thermal resistance (2) 32.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 14.3 °C/W RθJB Junction-to-board thermal resistance 6.2 °C/W ψJT Junction-to-top characterization parameter 0.2 °C/W ψJB Junction-to-board characterization parameter 6.1 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 1.9 °C/W (1) (2) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Thermal resistances are based on having 16 thermal relief vias on the DAP pad under the 0 airflow condition. 6.5 Electrical Characteristics over recommended operating supply and temperature ranges unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT 2 VCC + 0.3 V LVCMOS DC SPECIFICATIONS VIH High level input voltage VIL Low level input voltage –0.3 0.8 V IIH High level input current VIN = VCC –10 10 µA IIL Low level input current VIN = GND 75 RPU Pull-high resistance 94 124 35 µA kΩ RECEIVER SPECIFICATIONS Differential input voltage range (2) AC-coupled differential signal This parameter is not tested at production VICM Common-mode voltage at receiver inputs Measured at receiver inputs reference to ground RITD Input differential termination (3) On-chip differential termination between IN+ or IN− VID (1) (2) (3) Below 1.25 Gbps Above 1.25 Gbps 100 1750 100 1560 1.3 84 100 mVP-P V 116 Ω Typical parameters measured at VCC = 3.3 V, TA = 25°C, and represent most likely parametric norms at the time of product characterization. The typical specifications are not ensured. This parameter is ensured by design and/or characterization. It is not tested in production. IN+ and IN− are generic names refer to one of the many pairs of complimentary inputs of the DS25MB100. OUT+ and OUT− are generic names refer to one of the many pairs of the complimentary outputs of the DS25MB100. Differential input voltage VID is defined as |IN+–IN−|. Differential output voltage VOD is defined as |OUT+–OUT−|. Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: DS25MB100 5 DS25MB100 SNLS243H – SEPTEMBER 2006 – REVISED MARCH 2016 www.ti.com Electrical Characteristics (continued) over recommended operating supply and temperature ranges unless otherwise specified. PARAMETER MIN TYP (1) TEST CONDITIONS MAX UNIT DRIVER SPECIFICATIONS RL = 100Ω ±1% DES_1=DES_0=0 DEL_1=DEL_0=0 Driver pre-emphasis disabled Running K28.7 pattern at 2.5 Gbps See Figure 6 for test circuit. VODB Output differential voltage swing without preemphasis (4) VPE RL = 100Ω ±1% Running K28.7 pattern at 2.5 Gbps x=S for switch side pre-emphasis Output pre-emphasis voltage control ratio x=L for line side pre20 × log(VODPE/VODB) emphasis control See Figure 9 on waveform. See Figure 6 for test circuit. TPE Pre-emphasis width ROTSE Output termination (3) ROTD Output differential termination ΔROTS Mis-match in output termination resistors E VOCM 1100 1300 DEx_[1:0]=00 0 DEx_[1:0]=01 –3 DEx_[1:0]=10 –6 1500 mVP-P dB DEx_[1:0]=11 –9 Tested at −9-dB pre-emphasis level, DEx[1:0]=11 x=S for switch side pre-emphasis control x=L for line side pre-emphasis control See Figure 3 on measurement condition. 125 188 250 ps On-chip termination from OUT+ or OUT− to VCC 42 50 58 Ω On-chip differential termination between OUT+ and OUT− Ω 100 Mis-match in output terminations at OUT+ and OUT− 5% Output common-mode voltage 2.7 V 0.45 W POWER DISSIPATION PD Power dissipation VDD = 3.3V at 25°C All outputs terminated by 100 Ω ±1%. DEL_[1:0]=0, DES_[1:0]=0 Running PRBS 27-1 pattern at 2.5 Gbps AC CHARACTERISTICS At 0.25 Gbps 2 At 1.25 Gbps 2 At 2.5 Gbps 2 Device random jitter (5) See Figure 6 for test circuit. Alternating-1-0 pattern EQ and pre-emphasis disabled. DJ Device deterministic jitter (6) See Figure 6 for test circuit. EQ and pre-emphasis disabled Between 0.25 and 2.5 Gbps with PRBS-7 pattern for DS25MB100 at –40°C to 85°C DR Data rate (2) Tested with alternating 1-0 pattern RJ (4) (5) (6) 6 0.25 psrms 35 psp-p 2.5 Gbps K28.7 pattern is a 10-bit repeating pattern of K28.7 code group {001111 1000}K28.5 pattern is a 20-bit repeating pattern of +K28.5 and −K28.5 code groups {110000 0101 001111 1010} Device output random jitter is a measurement of the random jitter contribution from the device. It is derived by the equation sqrt(RJOUT2– RJIN2), where RJOUT is the total random jitter measured at the output of the device in psrms, RJIN is the random jitter of the pattern generator driving the device. Device output deterministic jitter is a measurement of the deterministic jitter contribution from the device. It is derived by the equation (DJOUT–DJIN), where DJOUT is the total peak-to-peak deterministic jitter measured at the output of the device in psp-p, DJIN is the peakto-peak deterministic jitter of the pattern generator driving the device. Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: DS25MB100 DS25MB100 www.ti.com SNLS243H – SEPTEMBER 2006 – REVISED MARCH 2016 6.6 Switching Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN Measured with a clock-like pattern at 2.5 Gbps, between 20% and 80% of the differential output voltage. Pre-emphasis disabled. Transition time is measured with fixture as shown in Figure 6, adjusted to reflect the transition time at the output pins. tR Differential low-to-high transition time tF Differential high-to-low transition time tPLH Differential low-to-high propagation delay tPHL Differential high-to-low propagation delay tSKP Pulse skew UNIT ps 100 ps |tPHL – tPLH| (1) MAX 100 Measured at 50% differential voltage from input to output. 1 ns 1 ns 20 ps Difference in propagation delay among data paths in the same device. 100 ps 100 ps 6 ns tSKO Output skew tSKPP Part-to-part skew Difference in propagation delay between the same output from devices operating under identical condition. tSM MUX switch time Measured from VIH or VIL of the MUX-control or loopback control to 50% of the valid differential output. (1) TYP 1.8 tSKO is the magnitude difference in the propagation delays among data paths. An example is the output skew among data paths from IN0± to OUT± and IN1± to OUT±. Another example is the output skew among data paths from IN± to OUT0± and IN± to OUT1±. tSKO also refers to the delay skew of the loopback paths of the same port and between similar data paths. An example is the output skew among data paths IN0± to OUT0± and IN1± to OUT1±. 80% 80% 0V VODB 20% 20% tR tF Figure 1. Driver Output Transition Time IN 50% VID tPLH tPHL OUT 50% VOD Figure 2. Propagation Delay from Input to Output Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: DS25MB100 7 DS25MB100 SNLS243H – SEPTEMBER 2006 – REVISED MARCH 2016 www.ti.com 1- bit 1 to N bits 1- bit 1 to N bits tPE 20% -9 dB VODB 0V VODPE3 80% Figure 3. Test Condition for Output Pre-Emphasis Duration 200 mV/DIV 200 mV/DIV 6.7 Typical Characteristics 60 ps/DIV 60 ps/DIV Figure 4. PRBS-7, Pre-Emphasis = 0 dB at 2.5 Gbps Figure 5. PRBS-7, Pre-Emphasis = –9 dB at 2.5 Gbps 7 Parameter Measurement Information Pattern Generator DS25MB100 Test Fixture DC Block 50: TL VCC DS25MB100 < 2" IN+ IN- EQ R M U X D OUT+ OUT- 50 ±1% < 2" Coax 1000 mVpp differential Oscilloscope or Jitter Measurement Instrument Coax Coax D+ D- DC Block 50: TL Coax 50: TL GND 50: TL 50 ±1% Figure 6. AC Test Circuit 8 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: DS25MB100 DS25MB100 www.ti.com SNLS243H – SEPTEMBER 2006 – REVISED MARCH 2016 8 Detailed Description 8.1 Overview The DS25MB100 is a signal-conditioning 2:1 multiplexer and a 1:2 buffer designed to support port redundancy with encoded or scrambled data rates up to 2.5 Gbps. The DS25MB100 is not designed to operate with data rates below 250 Mbps or with a DC bias applied to the CML inputs or outputs. 8.2 Functional Block Diagram DS25MB100 1.5V 50 50 VCC IN0+ 50 OUT + 50 Input stage + EQ M U X CML driver IN0- IN1+ OUT Input stage + EQ IN1- DE _L 50 50 1.5V MUX VCC LB0 DE _S LB1 50 50 2 IN + 2 Input stage + EQ IN- OUT 0+ M U X CML driver OUT 0- OUT 1+ 2 50 50 1.5V 2 M U X CML driver OUT 1- EQ_L 50 50 DE _S DEL _0 DE _L DEL _1 Pre-emphasis Control DES _0 VCC DE_S DES _1 Figure 7. Simplified Block Diagram 8.3 Feature Description The DS25MB100 MUX buffer consists of several key blocks: • CML Inputs and EQ • Multiplexer and Loopback Control • CML Drivers and Pre-Emphasis Control Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: DS25MB100 9 DS25MB100 SNLS243H – SEPTEMBER 2006 – REVISED MARCH 2016 www.ti.com Feature Description (continued) 8.3.1 CML Inputs and EQ The high speed inputs are self-biased to about 1.3 V at IN+ and IN– and are designed for AC coupling, allowing the DS25MB100 to be inserted directly into the datapath without any limitation. See Figure 8 for details about the internal receiver input termination and bias circuit. VCC 5k IN + 50 1.5V EQ 50 IN 3.9k 180 pF Figure 8. Receiver Input Termination and Bias Circuit The inputs are compatible to most AC-coupling differential signals such as LVDS, LVPECL, and CML. The ideal AC-coupling capacitor value is often based on the lowest frequency component embedded within the serial link. A typical AC-coupling capacitor value ranges from 100 to 1000 nF. Some specifications with scrambled data may require a larger coupling capacitor for optimal performance. To reduce unwanted parasitics around and within the AC-coupling capacitor, TI recommends a body size of 0402. Figure 6 shows the AC-coupling capacitor placement in an AC test circuit. Each input stage has a fixed equalizer that provides equalization to compensate about 5 dB (at 1.25 GHz) of transmission loss from a short backplane trace (about 10 inches backplane). EQ can be enabled or disabled with the EQL and EQS pins. Table 1. EQ Controls for Line and Switch Inputs PIN EQL, EQS PIN VALUE EQUALIZER FUNCTION 0 Enable equalization. 1 (default) Normal mode. Equalization disabled. 8.3.2 Multiplexer and Loopback Control Table 2 and Table 3 provide details about how to configure the DS25MB100 multiplexer and loopback settings. Table 2. Logic Table for Multiplex Controls PIN MUX PIN VALUE MUX FUNCTION 0 MUX select switch input IN1±. 1 (default) MUX select switch input IN0±. Table 3. Logic Table for Loopback Controls PIN LB0 LB1 10 PIN VALUE LOOPBACK FUNCTION 0 Enable loopback from IN0± to OUT0±. 1 (default) Normal mode. Loopback disabled. 0 Enable loopback from IN1± to OUT1±. 1 (default) Normal mode. Loopback disabled. Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: DS25MB100 DS25MB100 www.ti.com SNLS243H – SEPTEMBER 2006 – REVISED MARCH 2016 8.3.3 CML Drivers and Pre-Emphasis Control The output driver has pre-emphasis (driver-side equalization) to compensate the transmission loss of the backplane that it is driving. The driver conditions the output signal such that the lower frequency and higher frequency pulses reach approximately the same amplitude at the end of the backplane and minimize the deterministic jitter caused by the amplitude disparity. The DS25MB100 provides four steps of user-selectable preemphasis ranging from 0, –3, –6 and –9 dB to handle different lengths of backplane. Figure 9 shows a driver preemphasis waveform. The pre-emphasis duration is 188 ps nominal, corresponding to 0.47 unit intervals (UI) at 2.5 Gbps. The pre-emphasis levels of switch-side and line-side can be individually programmed. 1-bit 1 to N bits 1-bit 1 to N bits 0 dB - 3 dB - 6 dB VODPE2 VODPE1 VODPE3 0V VODB - 9 dB Figure 9. Driver Pre-Emphasis Differential Waveform (Showing All 4 Pre-Emphasis Steps) Table 4. Line-Side Pre-Emphasis Controls DEL_[1:0] PRE-EMPHASIS LEVEL IN mVPP (VODB) PRE-EMPHASIS LEVEL IN mVPP (VODPE) 00 1300 01 1300 10 11 (default) DES_[1:0] PRE-EMPHASIS LEVEL IN mVPP (VODB) PRE-EMPHASIS LEVEL IN mVPP (VODPE) PRE-EMPHASIS IN dB (VODPE/VODB) TYPICAL FR4 BOARD TRACE 00 1300 1300 0 10 inches 01 1300 920 −3 20 inches 10 1300 650 −6 30 inches 11 (default) 1300 461 −9 40 inches PRE-EMPHASIS IN dB (VODPE/VODB) TYPICAL FR4 BOARD TRACE 1300 0 10 inches 920 −3 20 inches 1300 650 −6 30 inches 1300 461 −9 40 inches Table 5. Switch-Side Pre-Emphasis Controls Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: DS25MB100 11 DS25MB100 SNLS243H – SEPTEMBER 2006 – REVISED MARCH 2016 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The DS25MB100 is a 2:1 MUX and 1:2 buffer that equalizes input data up to 2.5 Gbps and provides transmit pre-emphasis controls to improve overall signal reach. As a MUX buffer, the DS25MB100 is ideal for designs where there is a need for port sharing or redundancy as well as on-the-fly reorganization of routes and data connections. 9.2 Typical Application A typical application for the DS25MB100 is shown in Figure 10 and Figure 11. Passive Backplane Line Cards DS25MB100 SerDes HT TD SOB T_ CLK ASIC PHY SOA LI SIA RD R_CLK HR LO SIB REFCLK Mux/Buf Clock Distribution ASIC or FPGA with integrated SerDes PC Switch Card 2 Switch Card 1 SerDes TD Switch ASIC HT T_ CLK RD R_CLK HR REFCLK Clock Distribution ASIC or FPGA with integrated SerDes Figure 10. Network Switch System With Redundancy 12 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: DS25MB100 DS25MB100 www.ti.com SNLS243H – SEPTEMBER 2006 – REVISED MARCH 2016 Typical Application (continued) DS25MB100 1.5V 50 50 VCC 2 x 0.01PF 0402 - size IN0+ 50 50 OUT + To Upstream receiver Input stage + EQ M U X CML driver From downstream transmitter IN0- IN1+ From downstream transmitter OUT Input stage + EQ IN1- DE _L 2 x 0.01PF 0402 - size 50 50 1.5V Control MUX VCC LB0 DE _S LB1 50 50 2 OUT0+ M U X IN + From Upstream transmitter IN- 2 x 0.01 PF 0402 - size 2 Input stage + EQ To downstream CML driver OUT0- receiver 2 OUT1+ M U X 50 50 1.5V 2 To downstream CML driver OUT1- receiver 50 50 DE _S Control DEL _0 DE _L DEL _1 VCC Pre-emphasis Control DES _0 DE _S DES _1 GND pins and DAP VCC pins RSV 3.3V 4 x 0.01PF X7R 0402 - size Figure 11. DS25MB100 Connection Block Diagram 9.2.1 Design Requirements In a typical design, the DS25MB100 equalizes a short backplane trace on its input, followed by a longer trace at the DS25MB100 output. In this application example, a 25-inch FR4 coupled micro-strip board trace is used in place of the short backplane link. See Figure 12 for a block diagram of this example. (A) (B) Pattern Generator, 2.5 Gb/s (C) (D) DS25MB100 Pre-Emph D+ D- 25-inch FR4 board trace M IN+ EQ IN- R U X OUT+ D 40-inch FR4 trace OUT- 27 -1 pattern Figure 12. Block Diagram of DS25MB100 Application Example Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: DS25MB100 13 DS25MB100 SNLS243H – SEPTEMBER 2006 – REVISED MARCH 2016 www.ti.com Typical Application (continued) The 25-inch microstrip board trace has approximately 6 dB of attenuation at 1.875 GHz, representing closely the transmission loss of the short backplane transmission line. The 25-inch microstrip is connected between the pattern generator and the differential inputs of the DS25MB100 for AC measurements. Table 6. Input Trace Parameters TRACE LENGTH FINISHED TRACE WIDTH W SEPARATION BETWEEN TRACES DIELECTRIC HEIGHT H DIELECTRIC CONSTANT εR LOSS TANGENT 25 inches 8.5 mil 11.5 mil 6 mil 3.8 0.022 The length of the output trace may vary based on system requirements. In this example, a 40-inch FR4 trace with similar trace width, separation, and dielectric characteristics, is placed at the DS25MB100 output. As with any high speed design, there are many factors which influence the overall performance. The following is a list of critical areas for consideration and study during design. • Use 100-Ω impedance traces. Generally these are very loosely coupled to ease routing length differences. • Place AC-coupling capacitors near to the receiver end of each channel segment to minimize reflections. • The maximum body size for AC-coupling capacitors is 0402. • Back-drill connector vias and signal vias to minimize stub length. • Use reference plane vias to ensure a low inductance path for the return current. 9.2.2 Detailed Design Procedure For optimal design, the DS25MB100 must be configured to route incoming data correctly as well as provide the best signal quality. The following design procedures should be observed: 1. The DS25MB100 must be configured to provide the correct MUX and buffer routes in order to satisfy system requirements. In order to set the appropriate MUX control settings, refer to Table 2. To configure the buffer control settings, refer to Table 3. For example, consider the case where the designer wishes to route the input from Switch Card 0 (IN0±) to the output for the line card (OUT±). To accomplish this, set MUX = 1 (select IN0±). For the other direction from line card output to switch card, set LB0 = 1 and LB1 = 1 so that the input from the line card is buffered to both Switch Card 0 (OUT0±) and Switch Card 1 (OUT1±). 2. The DS25MB100 is designed to be placed at an offset location with respect to the overall channel attenuation. To optimize performance, determine whether input and output equalization is required. Set EQL = 0 and EQS = 0 to enable input equalization. The MUX buffer transmit pre-emphasis can be tuned to extend the trace length reach while also recovering a solid eye opening. To tune transmit pre-emphasis on either the line card side or switch card side, refer to Table 4 and Table 5 for recommended pre-emphasis control settings according to the length of FR4 board trace connected at the DS25MB100 output. For example, if 40 inches of FR4 trace is connected to the switch card output, set DES_[1:0] = (1, 1) for VOD = 1200 mVpp and –9 dB of transmit pre-emphasis. 9.2.3 Application Curves Figure 13 through Figure 18 show how the signal integrity varies at different places in the data path. These measured locations can be referenced back to the labeled points provided in Figure 12. • Point (A): Output signal of source pattern generator • Point (B): Input to DS25MB100 after 25 inches of FR4 trace from source • Point (C): Output of DS25MB100 driver • Point (D): Signal after 40 inches of FR4 trace from DS25MB100 driver The source signal is a PRBS-7 pattern at 2.5 Gbps. For the long output traces, the eye after 40 inches of output FR4 trace is significantly improved by adding –9 dB of pre-emphasis. 14 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: DS25MB100 DS25MB100 200 mV/DIV SNLS243H – SEPTEMBER 2006 – REVISED MARCH 2016 200 mV/DIV www.ti.com 60 ps/DIV 60 ps/DIV Figure 14. Eye Measured at Point (B) 200 mV/DIV 200 mV/DIV Figure 13. Eye Measured at Point (A) 60 ps/DIV 60 ps/DIV Figure 16. Eye Measured at Point (D), Pre-Emphasis = 0 dB 200 mV/DIV 200 mV/DIV Figure 15. Eye Measured at Point (C), Pre-Emphasis = 0 dB 60 ps/DIV 60 ps/DIV Figure 17. Eye Measured at Point (C), Pre-Emphasis = –9 dB Figure 18. Eye Measured at Point (D), Pre-Emphasis = –9 dB Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: DS25MB100 15 DS25MB100 SNLS243H – SEPTEMBER 2006 – REVISED MARCH 2016 www.ti.com 10 Power Supply Recommendations The supply (VCC) and ground (GND) pins must be connected to power planes routed on adjacent layers of the printed-circuit board. The layer thickness of the dielectric must be minimized so that the VCC and GND planes create a low inductance supply with distributed capacitance. Careful attention to supply bypassing through the proper use of bypass capacitors is required. A 0.01-μF or 0.1-μF bypass capacitor must be connected to each VCC pin such that the capacitor is placed as close as possible to the VCC pins. Smaller body size capacitors, such as 0402 body size, can help facilitate proper component placement. Refer to the VCC pin connections in Figure 11 for further details. 11 Layout 11.1 Layout Guidelines Use at least a four layer board with a power and ground plane. Closely-coupled differential lines of 100 Ω are typically recommended for differential interconnect. The closely coupled lines help to ensure that coupled noise will appear as common-mode and thus will be rejected by the receivers. Information on the WQFN style package is provided in AN-1187 Leadless Leadframe Package (LLP), SNOA401. Stencil parameters such as aperture area ratio and the fabrication process have a significant impact on paste deposition. Inspection of the stencil prior to placement of the WQFN package is highly recommended to improve board assembly yields. If the via and aperture openings are not carefully monitored, the solder may flow unevenly through the DAP. Stencil parameters for aperture opening and via locations are shown in Figure 19. A layout example for the DS25MB100 is shown in Figure 20, where 16 stencil openings are used for the DAP alongside nine vias to GND. 11.2 Layout Example Figure 19. No Pullback WQFN, Single Row Reference Diagram Table 7. No Pullback WQFN Stencil Aperture Summary for DS25MB100 DEVICE PIN COUNT MKT DWG PCB I/O PAD SIZE (mm) PCB PITCH (mm) PCB DAP SIZE (mm) STENCIL I/O APERTURE (mm) STENCIL DAP APERTURE (mm) NUMBER OF DAP APERTURE OPENINGS GAP BETWEEN DAP APERTURE (Dim A mm) DS25MB100 36 SQA36A 0.25 × 0.6 0.5 4.6 × 4.6 0.25 × 0.7 1.0 × 1.0 16 0.2 16 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: DS25MB100 DS25MB100 www.ti.com SNLS243H – SEPTEMBER 2006 – REVISED MARCH 2016 Figure 20. 36-Pin WQFN Stencil Example of Via and Opening Placement Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: DS25MB100 17 DS25MB100 SNLS243H – SEPTEMBER 2006 – REVISED MARCH 2016 www.ti.com 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation, see the following: AN-1187 Leadless Leadframe Package (LLP), SNOA401 12.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.3 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 18 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: DS25MB100 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) DS25MB100TSQ/NOPB ACTIVE WQFN NJK 36 250 RoHS & Green SN Level-3-260C-168 HR -40 to 85 25MB100 DS25MB100TSQX/NOPB ACTIVE WQFN NJK 36 2500 RoHS & Green SN Level-3-260C-168 HR -40 to 85 25MB100 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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DS25MB100TSQX/NOPB
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    • 1000+36.30000

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