DS25MB200-EVK

DS25MB200-EVK Signal Conditioning Mux-Buffer Demo Board User Guide DS25MB200 Demo Board Page 1 Rev 1.0 March 16, 2005 Introduction The DS25MB200 is a signal conditioning 2:1 multiplexer and 1:2 buffer designed to support port redundancy. Advanced signal conditioning features utilizing input equalization and output driver pre-emphasis enable data communication for FR4 backplane over 0.8-2.5Gb/s. The DS25MB200 demo board is designed to assist customers to evaluate the functionality and performance. All input and output ports of the DS25MB200 are brought out to SMA connectors for accessibility to instrumentation. A 25-inch FR4 transmission line is provided along with the demo board to facilitate evaluation of the signal conditioning features. This 25-inch board trace has about 5dB loss from 375MHz to 1.9GHz. It is intended to use as the input transmission line to the DS25MB200, whose on-chip input equalizer is optimized to minimize the deterministic jitter caused by the input board trace. Customers can also connect the DS25MB200 to their backplanes for performance evaluation. Evaluation Kit Content This evaluation kit consists of the following components: (1) (2) (3) (4) DS25MB200 demo board A 25-inch FR4 differential board trace Demo Board User Guide (this document) Demo board schematic DS25MB200 Demo Board Page 2 Rev 1.0 March 16, 2005 DS25MB200 Demo Board and 25-inch Tline Board DS25MB200 Demo Board Page 3 Rev 1.0 March 16, 2005 Connection Diagram VCC=3.3V DS25MB200 Demo Board 25-inch TLINE Board Pattern Generator DC Block Oscilloscope or Jitter Measurement Instrument DS25MB200 50 D+ IN+ IN- FR4 board traces D- EQ R M U X OUT+ D OUT- 50 TRIG 1000mVpp differential GND TRIG Figure 1. Typical connection for evaluation of the DS25MB200 Power VCC GND JP2.3 JP2.1 3.3V ± 5% 0V Pre-emphasis controls PREL0 JP2.4 Set Pre-emphasis level for all outputs at the line side (LO_0± PREL1 JP2.2 and LO_1±). Open is logic 1. Strap to GND is logic 0. PRES0 JP3.4 Set the pre-emphasis level for all outputs at the switch side PRES1 JP3.2 (SOA_0±, SOB_0±, SOA_1± and SOB_1±). Open is logic 1. Strap to GND is logic 0. Mux controls MUX_S0 JP1.3 MUX_S1 JP1.1 Loopback controls LB0A JP5.2 LB0B JP5.4 LB1A JP6.1 LB1B JB6.3 RSV control RSV JP8.2 DS25MB200 Demo Board Set the multiplexer position to switch A or switch B. Open is logic 1. Strap to GND is logic 0. Enable or disable loopback. Open is logic 1. Strap to GND is logic 0. Reserved for factory testing purposes. JP8.2 is permanently tied to GND. Page 4 Rev 1.0 March 16, 2005 Logic control for data paths Following tables list the logic states of the control pins used to configure the data paths of the DS25MB200. More detailed information about pin functions and pin descriptions can be found in the DS25MB200 datasheet. Logic table for multiplex controls MUX_S0 0 Mux Function MUX_0 select switch_B input, SIB_0±. 1 (default) MUX_0 select switch_A input, SIA_0±. MUX_S1 0 Mux Function MUX_1 select switch_B input, SIB_1±. 1 (default) MUX_1 select switch_A input, SIA_0±. Logic table for loopback controls LB0A 0 1 Loopback Function Enable loopback from SIA_0± to SOA_0±. Normal mode. Loopback disabled. LB0B 0 1 Loopback Function Enable loopback from SIB_0± to SOB_0±. Normal mode. Loopback disabled. LB1A 0 1 Loopback Function Enable loopback from SIA_1± to SOA_1±. Normal mode. Loopback disabled. LB1B 0 1 Loopback Function Enable loopback from SIB_1± to SOB_1±. Normal mode. Loopback disabled. Line-side pre-emphasis controls PreL_[1:0] Pre-emphasis level in mVpp 00 1200 01 1200 10 1200 11 1200 . Switch-side pre-emphasis controls PreS_[1:0] Pre-emphasis level in mVpp 00 1200 01 1200 10 1200 11 1200 DS25MB200 Demo Board De-emphasis level in mVpp 1200 849.53 600 425.78 Pre-emphasis in dB De-emphasis level in mVpp 1200 849.53 600 425.78 Pre-emphasis in dB Page 5 0 -3 -6 -9 0 -3 -6 -9 Rev 1.0 March 16, 2005 Typical output waveforms The followings are typical eye diagrams of the DS25MB200 using the demo board connected as shown in Figure 1. Figure 2a-b. Eye diagrams at 2.5 and 1.25 Gb/s, PRBS7 pattern, Pre-emphasis=0dB Figure 3a-b. Eye diagrams at 2.5 and 1.25 Gb/s, PRBS7 pattern, Pre-emphasis=9dB Reference Material DS25MB200 datasheet National web site http://www.national.com/appinfo/lvds/ DS25MB200 Demo Board Page 6 Rev 1.0 March 16, 2005 DS25MB200 demo board schematic DS25MB200 Demo Board Page 7 Rev 1.0 March 16, 2005 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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