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DS26C32AMQML
Quad Differential Line Receiver
with 6 mA source and sink capability. This product is pin compatible with the DS26LS32A and the AM26LS32.
General Description
The DS26C32A is a quad differential line receiver designed
to meet the RS-422, RS-423, and Federal Standards 1020
and 1030 for balanced and unbalanced digital data transmission, while retaining the low power characteristics of CMOS.
The DS26C32A has an input sensitivity of 200 mV over the
common mode input voltage range of ±7V. The DS26C32A
features internal pull-up and pull-down resistors which prevent output oscillation on unused channels.
The DS26C32A provides an enable and disable function common to all four receivers, and features TRI-STATE ® outputs
Features
■
■
■
■
■
■
CMOS design for low power
±0.2V sensitivity over input common mode voltage range
Input fail-safe circuitry.
Inputs won't load line when VCC = 0V
Meets the requirements of EIA standard RS-422
TRI-STATE outputs for connection to system buses
Ordering Information
NS Part Number
SMD Part Number
DS26C32AME/883
5962–9164001M2A
NS Package Number
E20A
Package Description
20LD Leadless Chip Carrier
DS26C32AMJ/883
5962–9164001MEA
J16A
16LD Ceramic Dip
DS26C32AMW/883
5962–9164001MFA
W16A
16LD Ceramic Flatpack
DS26C32AMWG/883
5962–9164001MXA
WG16A
16LD Ceramic SOIC
Connection Diagrams
Dual-In-Line Package
20-Lead Ceramic Leadless Chip Carrier
20163102
Top View
See NS Package J16A, WG16A, or W16A
20163112
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2010 National Semiconductor Corporation
201631
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DS26C32AMQML Quad Differential Line Receiver
October 26, 2010
DS26C32AMQML
Logic Diagram
20163101
Truth Table
ENABLE
ENABLE
Input
L
H
X
Z
VID ≥ V Th (Max)
H
VID ≤ V Th (Min)
L
Open
H
All Other
Combinations of
Enable Inputs
Z = TRI-STATE
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2
Output
DS26C32AMQML
Absolute Maximum Ratings (Note 2, Note 1)
Supply Voltage (VCC)
Common Mode Range (VCM)
Differential Input Voltage (VDiff)
Enable Input Voltage (V I)
Storage Temperature Range (T Stg)
7V
±14V
±14V
7V
−65°C ≤ TA ≤ +150°C
260°C
Lead Temperature (Soldering 4 sec.)
Recommended Operating Conditions
Min
4.50
−55
Supply Voltage (VCC)
Operating Temperature Range (TA)
Max
5.50
+125
Units
V
°C
Quality Conformance Inspection
Mil-Std-883, Method 5005 - Group A
Subgroup
Description
1
Static tests at
Temp °C
+25
2
Static tests at
+125
3
Static tests at
-55
4
Dynamic tests at
+25
5
Dynamic tests at
+125
6
Dynamic tests at
-55
7
Functional tests at
+25
8A
Functional tests at
+125
8B
Functional tests at
-55
9
Switching tests at
+25
10
Switching tests at
+125
11
Switching tests at
-55
12
Settling time at
+25
13
Settling time at
+125
14
Settling time at
-55
3
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DS26C32AMQML
DS26C32AM Electrical Characteristics
DC Parameters
Symbol
Parameter
Conditions
Notes
Min
Max
Units
Subgroups
-200
+200
mV
1, 2, 3
4.5
11
KΩ
1, 2, 3
VTH
Minimum Differential Input
Voltage
VCC = 5V, VO = VOH or VOL,
-7 < VCM < +7
RI
Input Resistance
VCC = 5V, -7 < VCM < +7,
One input AC Gnd
II
Input Current
VCC = 5V, VI = +10V,
Other Input = Gnd
+1.8
mA
1, 2, 3
VCC = 5V, VI = -10V,
Other Input = Gnd
-2.7
mA
1, 2, 3
V
1, 2, 3
V
1, 2, 3
V
1, 2, 3
0.8
V
1, 2, 3
VOH
Logical "1" Output Voltage
VCC = 4.5V, VDiff = +1V,
IO = -6.0mA
3.8
VOL
Logical "0" Output Voltage
VCC = 5.5V, VCC = Max,
VDiff = -1V, IO = 6.0mA
VIH
Minimum Enable High Level
Voltage
(Note 3)
VIL
Maximum Enable Low Level
Voltage
(Note 3)
IOZ
Maximum TRI-STATE Output
Leakage Current
VO = VCC or Gnd,
Enable = VIL, Enable = VIH
±5.0
µA
1, 2, 3
II
Maximum Enable Input Current
VI = VCC or Gnd
±1.0
µA
1, 2, 3
ICC
Quiescent Power Supply Current VDiff = +1V, VCC = 5.5V
25
mA
1, 2, 3
Max
Units
Subgroups
0.3
2.0
AC Parameters - Propagation Delay Time
The following conditions apply, unless otherwise specified.
Symbol
Parameter
VCC = 5V ±10%, CCL = 50pF, VDiff = 2.5V
Conditions
Notes
Min
tPLH
Input to Output Prop Delay
VCM = 0V
35
ns
9, 10, 11
tPHL
Input to Output Prop Delay
VCM = 0V
35
ns
9, 10, 11
tRise
Output Rise Time
VCM = 0V
9
ns
9, 10, 11
tFall
Output Fall Time
VCM = 0V
9
ns
9, 10, 11
tPLZ
Output Disable Time
RL = 1000Ω
29
ns
9, 10, 11
tPZL
Output Enable Time
RL = 1000Ω
29
ns
9, 10, 11
tPHZ
Output Disable Time
RL = 1000Ω
29
ns
9, 10, 11
tPZH
Output Enable Time
RL = 1000Ω
29
ns
9, 10, 11
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: Unless otherwise specified, all voltages are referenced to ground.
Note 3: Parameter tested Go-No-Go only.
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4
DS26C32AMQML
Typical Performance Characteristics
Differential Propagation Delay
vs Temperature
Differential Propagation Delay
vs Power Supply Voltage
20163113
20163114
Differential Skew vs
Temperature
Differential Skew vs Power
Supply Voltage
20163115
20163116
Output High Voltage vs
Output High Current
Output High Voltage vs
Output High Current
20163117
20163118
5
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DS26C32AMQML
Output Low Voltage vs
Output Low Current
Output Low Voltage vs
Output Low Current
20163119
20163120
Input Current vs Power
Supply Voltage
Input Resistance vs
Input Voltage
20163121
20163122
Hysteresis & Differential
Transition Voltage vs
Temperature
Hysteresis & Differential
Transition Voltage vs
Power Supply Voltage
20163123
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20163124
6
DS26C32AMQML
Supply Current vs
Temperature
Disabled Supply Current vs
Power Supply Voltage
20163125
20163126
Supply Current vs
Data Rate
20163127
7
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DS26C32AMQML
AC Test Circuit and Switching Time Waveforms
20163106
CL includes load and test jig capacitance.
S1 = VCC for tPZL, and tPLZ measurements.
S1 = Gnd for tPZH, and tPHZ measurements.
FIGURE 1. Test Circuit for TRI-STATE Output Tests
20163107
FIGURE 2. Propagation Delay
20163108
FIGURE 3. TRI-STATE®Output Enable and Disable Waveforms
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8
DS26C32AMQML
Typical Applications
Two-Wire Balanced Systems, RS-422
20163109
9
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DS26C32AMQML
Revision History Section
Released
10/26/2010
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Revision
A
Section
Changes
New Release, Corporate format
10
MDS data sheets converted into one Corp. data
sheet format. MNDS26C32AM-X Rev 0B0 will be
archived.
DS26C32AMQML
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Ceramic Leadless Chip Carrier (E)
NS Package Number E20A
16-Lead Ceramic Dual-In-Line Package (J)
NS Package Number J16A
11
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DS26C32AMQML
16-Lead Ceramic FlatPak (W)
NS Package Number W16A
16-Lead Ceramic FlatPak (W)
NS Package Number WG16A
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12
DS26C32AMQML
Notes
13
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DS26C32AMQML Quad Differential Line Receiver
Notes
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