DS32EL0124, DS32ELX0124
www.ti.com
SNLS284K – MAY 2008 – REVISED APRIL 2013
DS32EL0124 , DS32ELX0124 125 MHz - 312.5 MHz FPGA-Link Deserializer with DDR LVDS
Parallel Interface
Check for Samples: DS32EL0124, DS32ELX0124
FEATURES
KEY SPECIFICATIONS
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1
2
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5-bit DDR LVDS Parallel Data Interface
Programmable Receive Equalization
Selectable DC-Balance Decoder
Selectable De-Scrambler
Remote Sense for Automatic Detection and
Negotiation of Link Status
No External Receiver Reference Clock
Required
LVDS Parallel Interface
Programmable LVDS Output Clock Delay
Supports Output Data-Valid Signaling
Supports Keep-Alive Clock Output
On Chip LC VCOs
Redundant Serial Input (ELX device only)
Retimed Serial Output (ELX device only)
Configurable PLL Loop Bandwidth
Configurable via SMBus
Loss of Lock and Error Reporting
48-pin WQFN Package with Exposed DAP
APPLICATIONS
•
•
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Imaging: Industrial, Medical Security, Printers
Displays: LED Walls, Commercial
Video Transport
Communication Systems
Test and Measurement
Industrial Bus
1.25 to 3.125 Gbps Serial Data Rate
125 to 312.5 MHz DDR Parallel Clock
-40° to +85°C Temperature Range
> 8 kV ESD (HBM) Protection
0.5 UI Minimum Input Jitter Tolerance (1.25
Gbps)
DESCRIPTION
The DS32EL0124/DS32ELX0124 integrates clock
and data recovery modules for high-speed serial
communication over FR-4 printed circuit board
backplanes, balanced cables, and optical fiber. This
easy-to-use chipset integrates advanced signal and
clock conditioning functions, with an FPGA friendly
interface.
The DS32EL0124/DS32ELX0124 deserializes up to
3.125 Gbps of high speed serial data to 5 LVDS
outputs without the need for an external reference
clock. With DC-balance decoding enabled, the
application payload of 2.5 Gbps is deserialized to 4
LVDS outputs.
The
DS32EL0124/DS32ELX01214
deserializers
feature a remote sense capability to automatically
signal link status conditions to its companion
DS32EL0421/ELX0421 serializers without requiring
an additional feedback path.
The parallel LVDS interface of these devices reduce
FPGA I/O pins, board trace count and alleviates EMI
issues, when compared to traditional single-ended
wide bus interfaces.
The DS32EL0124/ELX0124 is programmable through
a SMBus interface as well as through control pins.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2013, Texas Instruments Incorporated
DS32EL0124, DS32ELX0124
SNLS284K – MAY 2008 – REVISED APRIL 2013
www.ti.com
Typical Application
DS32ELX0421
D1
R1
Redundant
Driver
Redundant Link
Retimed
Output
LVDS Interface
R0
Serial to Parallel
Parallel to Serial
Encoder
D0
RT0
LVDS
System Logic
5 LVDS
3.125 Gbps Data Payload
LVDS
Interface
LVDS
Interface
LVDS
Interface
LVDS
Interface
5 LVDS
System Logic
FPGA
DS32ELX0124
LVDS Interface
FPGA
LVDS
PLL
Clock
Control
PLL
Control
Clock
Control
Control
SMBus
SMBus
VDD33
1
N/C
2
RXOUT4-
RXOUT4+
RXOUT3-
RXOUT3+
RXOUT2-
RXOUT2+
RXOUT1-
RXOUT1+
RXOUT0-
RXOUT0+
RXCLKOUT-
RXCLKOUT+
48
47
46
45
44
43
42
41
40
39
38
37
Connection Diagrams
36
VDD33
35
VDD25
49 DAP = GND
GPIO0
3
34
SMB_CS
GPIO1
4
33
SCK
DC_B
5
32
SDA
RS
6
31
LOCK
30
RESET
DS32EL0124
23
24
N/C
VDD25
N/C
25
22
12
N/C
N/C
21
LF_REF
N/C
26
20
11
N/C
GPIO2
19
LF_CP
N/C
27
18
10
VDD33
N/C
17
VDDPLL
RXIN0-
28
16
9
RXIN0+
N/C
15
N/C
VDD33
29
14
8
N/C
N/C
13
7
N/C
VDD25
Figure 1. WQFN Package
Package Number RHS0048A
2
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VDD33
1
LT_EN
2
RXOUT4-
RXOUT4+
RXOUT3-
RXOUT3+
RXOUT2-
RXOUT2+
RXOUT1-
RXOUT1+
RXOUT0-
RXOUT0+
RXCLKOUT-
RXCLKOUT+
47
46
45
44
43
42
41
40
39
38
37
SNLS284K – MAY 2008 – REVISED APRIL 2013
48
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36
VDD33
35
VDD25
49 DAP = GND
GPIO0
3
34
SMB_CS
GPIO1
4
33
SCK
DC_B
5
32
SDA
RS
6
31
LOCK
30
RESET
DS32ELX0124
24
VDD33
N/C
VDD25
23
25
N/C
12
22
RX_MUX_SEL
TXOUT-
LF_REF
21
26
TXOUT+
11
20
GPIO2
RXIN1-
LF_CP
19
27
RXIN1+
10
18
N/C
VDD33
VDDPLL
17
28
RXIN0-
9
16
N/C
RXIN0+
N/C
15
29
14
8
VOD_CTRL
N/C
13
7
N/C
VDD25
Figure 2. WQFN Package
Package Number RHS0048A
PIN DESCRIPTIONS
Pin Name
Pin Number
I/O, Type
Description
VDD33
1, 15, 18, 36
I, VDD
3.3V supply
VDD25
7, 25, 35
I, VDD
2.5V supply
VDD_PLL
28
I, VDD
3.3V supply
LF_CP
27
Analog
Loop filter capacitor connection
LF_REF
26
Analog
Loop filter ground reference
Exposed Pad
49
GND
Exposed Pad must be connected to GND by 9 vias.
RxIN0+
RxIN0-
16
17
I, CML
Non-inverting and inverting high speed CML differential inputs of the
deserializer. These inputs are internally terminated.
RxIN1+
RxIN1-
19
20
I, CML
DS32ELX0124 only. Non-inverting and inverting high speed CML
differential inputs of the deserializer. These inputs are internally terminated.
TxOUT+
TxOUT-
21
22
O, CML
DS32ELX0124 only. Retimed serialized high speed output. Non-inverting
and inverting speed CML differential outputs of the deserializer. These
outputs are internally terminated.
CML I/O
LVDS Parallel Data Bus
RxCLKOUT+
RxCLKOUT-
37
38
O, LVDS
Deserializer output clock. RxCLKOUT+/- are the non-inverting and inverting
LVDS recovered clock output pins.
RxOUT[0:4]+/-
39, 40, 41, 42, 43, 44, 45,
46, 47, 48
O, LVDS
Deserializer output data. RxOUT[0:4]+/- are the non-inverting and inverting
LVDS deserialized output data pins.
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: DS32EL0124 DS32ELX0124
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SNLS284K – MAY 2008 – REVISED APRIL 2013
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PIN DESCRIPTIONS (continued)
Pin Name
Pin Number
I/O, Type
Description
LT_EN
2
I, LVCMOS
DS32ELX0124 only. When held high, retimed serialized high speed output
is enabled.
RX_MUX_SEL
12
I, LVCMOS
DS32ELX0124 only. RX_MUX_SEL selects the input of the deserializer.
0 = RxIN0+/- selected
1 = RxIN1+/- selected
VOD_CTRL
14
I, LVCMOS
DS32ELX0124 only. VOD control. The deserializer loop through output
amplitude can be adjusted by connecting this pin to a pull-down resistor.
The value of the pull-down resistor determines the VOD. See LOOP
THROUGH DRIVER LAUNCH AMPLITUDE for more details.
DC_B
RS
5
6
I, LVCMOS
DC-balance and Remote Sense pins. See Applications Information for
device behavior.
RESET
30
I, LVCMOS
Reset pin. When held low, reset the device.
0 = Device Reset
1 = Normal operation
LOCK
31
O, LVCMOS
Lock indication output. pin goes low when the deserializer is locked to the
incoming data stream and begins to output data and clock on RxOUT and
RxCLKOUT respectively.
0 = Deserializer locked
1 = Deserializer not locked
SCK
I, SMBus
33
SMBus compatible clock.
SDA
I/O, SMBus
32
SMBus compatible data line.
SMB_CS
I, SMBus
34
SMBus chip select. When held high, SMBus management control is
enabled.
GPIO0
3
I/O, LVCMOS Software configurable IO pins.
GPIO1
4
I/O, LVCMOS Software configurable IO pins.
GPIO2
11
I/O, LVCMOS Software configurable IO pins.
NC
2 ,8, 9, 10, 12, 13, 14, 19,
20, 21, 22, 23, 24, 29
Misc.
No Connect, for DS32EL0124
8, 9, 10, 13, 23, 24, 29
Misc
No Connect, for DS32ELX0124
Control Pins
SMBus
Other
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
4
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SNLS284K – MAY 2008 – REVISED APRIL 2013
Absolute Maximum Ratings (1) (2)
Supply Voltage (VDD33)
−0.3V to +4V
Supply Voltage (VDD25)
-0.3V to +3.0V
LVCMOS Input Voltage
−0.3V to (VDD33 + 0.3V)
LVCMOS Output Voltage
-0.3V to (VDD33 + 0.3V)
CML Input/Output Voltage
-0.3V to 3.6V
LVDS Output Voltage
-0.3V to +3.6V
Junction Temperature
+125°C
−65°C to +150°C
Storage Temperature Range
Lead Temperature Range
Soldering (4 sec.)
+260°C
Package Thermal Resistance
θJA
+25.0°C/W
ESD Susceptibility
≥8 kV
HBM
(1)
(2)
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
Recommended Operating Conditions
Min
Typ
Max
Units
Supply Voltage (VDD33)
3.135
3.3
3.465
V
Supply Voltage (VDD25)
2.375
2.5
2.625
V
100
mVP-P
+85
°C
Supply Noise Amplitude from 10 Hz to 50 MHz
−40
Ambient Temperature (TA)
+25
SMBus Pull–Up Resistor to VSDD Value
Ω
1000
Table 1. Power Supply Characteristics
Symbol
IDD25
Parameter
Condition
2.5V supply current
Loop Through Driver Disabled
2.5V supply current
Loop Through Driver Enabled
IDD33
3.3V supply current
Loop Through Driver Disabled
3.3V supply current
Loop Through Driver Enabled
PD
Power Consumption
Loop Through Driver Disabled
Power Consumption
Loop Through Driver Enabled
Typ
Max
1.25 Gbps
50
59
2.5 Gbps
62
73
3.125 Gbps
69
79
1.25 Gbps
88
99
2.5 Gbps
100
112
3.125 Gbps
107
120
1.25 Gbps
105
121
2.5 Gbps
105
121
3.125 Gbps
105
121
1.25 Gbps
111
127
2.5 Gbps
111
127
3.125 Gbps
111
127
1.25 Gbps
475
560
2.5 Gbps
500
600
3.125 Gbps
520
620
1.25 Gbps
590
690
2.5 Gbps
620
730
3.125 Gbps
640
750
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: DS32EL0124 DS32ELX0124
Min
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Unit
mA
mA
mW
5
DS32EL0124, DS32ELX0124
SNLS284K – MAY 2008 – REVISED APRIL 2013
www.ti.com
LVCMOS Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. Applies to LT_EN, GPIO0, GPIO1,
GPIO2, RX_MUX_SEL, DC_B, RESET, RS, LOCK. (1) (2) (3)
Symbol
Parameter
Conditions
Min
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
VOH
High Level Output Voltage
IOH = -2mA
VOL
Low Level Output Voltage
IOL = 2mA
VCL
Input Clamp Voltage
ICL = −18 mA
IIN
Input Current
VIN = 0.4V, 2.5V, or VDD33
IOS
Output Short Circuit Current
VOUT = 0V
(1)
(2)
(3)
(4)
Typ
2.0
GND
2.7
Max
Units
VDD
V
0.8
V
3.2
-0.9
-40
V
0.3V
V
−1.5
V
40
-45
(4)
μA
mA
The Electrical and Timing Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except
as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only
and are not ensured.
Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
except VOD and ΔVOD.
Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions
at the time of product characterization and are not ensured.
Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
SMBus Electrical Specifications
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
VSIL
Data, Clock Input Low Voltage
VSIH
Data, Clock Input High Voltage
VSDD
Nominal Bus Voltage
ISLEAKB
Input Leakage Per Bus Segment
ISLEAKP
CSI
(1)
(2)
(1) (2)
Conditions
Min
Max
Units
0.8
V
2.1
VSDD
V
2.375
3.465
SCK and SDA pins
Typ
V
±200
µA
Input Leakage Per Pin
±10
µA
Capacitance for SDA and SCK
10
pF
The Electrical and Timing Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except
as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only
and are not ensured.
Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions
at the time of product characterization and are not ensured.
SMBus Timing Specifications
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
(1) (2)
Min
Typ
Max
Units
100
kHz
fSMB
Bus Operating Frequency
10
tBUF
Bus free time between top and start condition
4.7
μs
tHD:STA
Hold time after (repeated) start condition. After this
period, the first clock is generated
4.0
µs
tSU:STA
Repeated Start Condition Setup Time
tHD:DAT
Data Hold Time
(3)
(3)
4.7
µs
300
ns
250
ns
tSU:DAT
Data Setup Time
tLOW
Clock Low Time
4.7
tHIGH
Clock High Time
4.0
tSU:CS
(1)
(2)
(3)
6
SMB_CS Setup Time
(3)
30
µs
50
µs
ns
The Electrical and Timing Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except
as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only
and are not ensured.
Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions
at the time of product characterization and are not ensured.
Parameter is specified by characterization and is not tested at production.
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SNLS284K – MAY 2008 – REVISED APRIL 2013
SMBus Timing Specifications (continued)
Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2)
Symbol
Parameter
Conditions
tHS:CS
SMB_CS Hold Time
(3)
tPOR
Time in which the device must be operational after
power on
(3)
Min
Typ
Max
Units
500
ms
Max
Units
310
mV
35
mV
100
ns
LVDS Electrical Specifications
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
VOD
Differential Output Voltage
ΔVOD
Changes in VOD between complimentary output
states
VOS
Offset Voltage
ΔVOS
Change in VOS between complimentary states
IOS
Output Short Circuit Current
(1)
(2)
(3)
(1) (2)
Min
RL = 100Ω
Typ
230
1.125
VOUT = 0V, RL = 100Ω
1.25
1.375
V
35
mV
-50
(3)
mA
The Electrical and Timing Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except
as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only
and are not ensured.
Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions
at the time of product characterization and are not ensured.
Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
LVDS Timing Specifications
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
(1) (2)
Min
Typ
Max
Units
tROTR
LVDS low-to-high transition time
300
ps
tROTF
LVDS high-to-low transition time
300
ps
tROCP
LVDS output clock period
tRODC
RxCLKOUT Duty Cycle
tRBIT
LVDS output bit width
tROSC
RxOUT Setup to RxCLKOUT OUT
tROHC
RxOUT Hold to RxCLKOUT OUT
tRODJ
LVDS Output Deterministic Jitter
2T
45
LVDS Output Random Jitter
Peak-to-Peak LVDS Output Jitter
(2)
(3)
ps
800
ps
RxCLKOUT
2.5
RxOUT0–4
2.5
RxCLKOUT
51
RxOUT0–4
70
(3)
(3)
(1)
800
650
43
(3)
tROTJ
650
RxOUT0–4
(3)
%
ns
18
(3)
ns
55
T
RxCLKOUT
(3)
tRORJ
50
ps
ps
ps
The Electrical and Timing Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except
as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only
and are not ensured.
Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions
at the time of product characterization and are not ensured.
Parameter is specified by characterization and is not tested at production.
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: DS32EL0124 DS32ELX0124
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LVDS Timing Specifications (continued)
Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2)
Symbol
tRLA
Parameter
Conditions
Deserializer Lock Time
tLVSK
Min
Typ
Max
Units
(3)
LVDS Output Skew
1.25 Gbps
22
2.5 Gbps
90
3.125 Gbps
115
LVDS Differential Output Skew
between + and - pins
20
ms
ps
CML Input Timing Specifications
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
TOLJIT
(1)
(2)
Parameter
(1) (2)
Conditions
Serial Input Jitter Tolerance
Min
RJ = 0.18 UI
DJ = 0.37 UI
SJ increased until failure
1.25 Gbps
f < 10 kHz
f > 1 MHz
Typ
Max
Units
30
0.5
UI
2.5 Gbps
f < 10 kHz
f > 1 MHz
50
0.3
3.125 Gbps
f < 10 kHz
f > 1 MHz
70
0.3
The Electrical and Timing Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except
as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only
and are not ensured.
Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions
at the time of product characterization and are not ensured.
CML Input Electrical Specifications
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Max
Units
VID
Differential input voltage
(3)
230
2200
mV
VIN
Single ended input voltage
(3)
115
1100
mV
IIN
Input Current
-300
50
μA
RIT
Input Termination
116
Ω
(1)
(2)
(3)
8
Parameter
Conditions
(1) (2)
Min
84
Typ
100
The Electrical and Timing Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except
as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only
and are not ensured.
Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions
at the time of product characterization and are not ensured.
Parameter is specified by characterization and is not tested at production.
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SNLS284K – MAY 2008 – REVISED APRIL 2013
CML Retimed Loop Through Output Electrical Specifications, DS32ELX0124 Only
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
(1) (2)
Conditions
Min
Typ
Units
1.45
V
VLTOD
Output differential voltage
VOD_CTRL resistor = 9.09 kΩ
RLTOT
Output termination
50Ω
40
50
60
75Ω
60
75
90
ΔRLTOT
(1)
(2)
(3)
1.15
Max
(3)
Mismatch in output termination resistors
Ω
5
%
The Electrical and Timing Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except
as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only
and are not ensured.
Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions
at the time of product characterization and are not ensured.
Parameter is specified by characterization and is not tested at production.
CML Retimed Loop Through Output Timing Specifications, DS32ELX0124 Only
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Typ
Max
Units
tJIT
Additive Output Jitter
(3)
24
35
ps
tOS
Output Overshoot
(3)
1.5
8
%
Retimed output driver differential low to high
transition time
(3)
74
105
tLTF
Retimed output driver differential high to low
transition time
(3)
74
105
tLTRFMM
Mismatch in Rise/Fall Time
(3)
5
15
tLTDE
Retimed driver de-emphasis width
tLTR
(1)
(2)
(3)
Parameter
(1) (2)
Conditions
Min
ps
ps
%
1
UI
The Electrical and Timing Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except
as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only
and are not ensured.
Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions
at the time of product characterization and are not ensured.
Parameter is specified by characterization and is not tested at production.
Timing Diagrams
tSU:CS
SMB_CS
tLOW
tHIGH
tR
SCK
tHD:STA
tBUF
tF
tHD:DAT
tSU:STA
tSU:STO
tSU:DAT
SDA
SP
ST
SP
ST
Figure 3. SMBus Timing Parameters
RXCLK
(diff)
80%
80%
20%
20%
tROTF
tROTR
Figure 4. LVDS Output Transition Time
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tROCP/2
+100 mV
RXCLK
-100 mV
tROCH, tROCL
tROHC
tROSC
Setup
Hold
RX[4:0]
Figure 5. Deserializer (LVDS Interface) Setup/Hold and High/Low Times
3.0V
RESET
tRPLLS
RxIN
RxCLKOUT
LOCK
tRLAPL
tRLA
Figure 6. Reset to Lock Time
Symbol N-1
Symbol N+1
Symbol N
Symbol N+3
Symbol N+2
Symbol N+4
RXIN
tRD
RXCLK
RX[0..4]
Symbol N-4
Symbol N-3
Symbol N-2
Symbol N-1
Symbol N
Figure 7. Deserializer Propagation Delay
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Last Bit In
First Bit In
E3
D3
C3
B3
A3
E2
D2
B2
C2
A2
E1
D1
B1
C1
A1
E0
D0
C0
B0
A0
High Speed Serial CML Input
Previous Cycle
Current Cycle
Next Cycle
Output Receive Clock
LVDS Data-0
A0
A1
A2
A3
LVDS Data-1
B0
B1
B2
B3
LVDS Data-2
C0
C1
C2
C3
LVDS Data-3
D0
D1
D2
D3
LVDS Data-4
E0
E1
E2
E3
Figure 8. CML to LVDS Bit Map
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FUNCTIONAL DESCRIPTION
POWER SUPPLIES
The DS32EL0124 and DS32ELX0124 have several power supply pins, at 2.5V as well as 3.3V. It is important
that these pins all be connected and properly bypassed. Bypassing should consist of parallel 4.7μF and 0.1μF
capacitors as a minimum, with a 0.1μF capacitor on each power pin. A 22 μF capacitor is required on the
VDDPLL pin which is connected to the 3.3V rail.
These devices have a large contact in the center on the bottom of the package. This contact must be connected
to the system GND as it is the major ground connection for the device.
POWER UP
It is recommended, although not necessary, to bring up the 3.3V power supply before the 2.5V supply. If the 2.5V
supply is powered up first, an initial current draw of approximately 600mA from the 2.5V rail may occur before
settling to its final value. Regardless of the sequence, both power rails should monotonically ramp up to their final
values.
POWER MANAGEMENT
These devices have two methods to reduce power consumption. To enter the first power save mode, the on
board host FPGA or controlling device can cease to output the DDR transmit clock. To further reduce power, a
write to the power down register will put the device in its lowest power mode.
RESET
There are three ways to reset these devices. A reset occurs automatically during power-up. The device can also
be reset by pulling the RESET pin low, with normal operation resuming when the pin is driven high again. The
device can also be reset by writing to the reset register. This reset will put all of the register values back to their
default values, except it will not affect the address register value if the SMBus default address has been
changed.
LVDS OUTPUTS
The DS32EL0124 and DS32ELX0124 has standard LVDS outputs, compatible with ANSI/TIA/EIA-644. It is
recommended that the PCB trace between the FPGA and the deserializer output be no more than 40-inches.
Longer PCB traces may introduce signal degradation as well as channel skew which could cause serialization
errors. The connection between the host and the DS32EL0124 or DS32ELX0124 should be over a controlled
impedance transmission line with impedance that matches the termination resistor – usually 100Ω. Setup and
hold times are specified in the LVDS Switching Characteristics table, however the clock delay can be adjusted by
writing to register 30’h.
LOOP FILTER
The DS32EL0124 and DSELX0124 have an internal clock data recovery module (CDR), which is used to recover
the input serial data. The loop filter for this CDR is external, and for optimum results, a 30nF capacitor should be
connected between pins 26 and 27. See the Typical Interface Circuit (Figure 14).
LOOP THROUGH DRIVER LAUNCH AMPLITUDE
The launch amplitude of the retimed CML loop through driver is controlled by placing a single resistor from the
VOD_CTRL pin to ground. Use the following equation to obtain the desired VLTOD by selecting the corresponding
resistor value.
R = (1400 mV / VLTOD) x 9.1 kΩ
(1)
The retimed CML loop through driver launch amplitude can also be adjusted by writing to SMBus register 49'h,
bits 3:1. This register is meant to assist system designers during the initial prototype design phase. For final
production, it is recommended that the appropriate resistor value be selected for the desired VLTOD and that
register 49'h be left to its default value.
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REMOTE SENSE
The remote sense feature can be used when a DS32EL0421 or DS32ELX0421 serializer is directly connected to
a DS32EL0124 or DS32ELX0124 deserializer. Active components in the signal path between the serializer and
the deserializer may interfere with the back channel signaling of the devices.
When remote sense is enabled, the deserializer will cycle through five states to successfully establish a link and
align the data. The state diagram for the deserialiezr is shown in Figure 9. The deserialzer will remain in the low
power IDLE state until it receives an input signal. Once the CDR of the deserializer has locked to the input clock,
the device will enter the LINK DETECT state. While in this state, the deserializer will monitor the line to see if the
serializer is sending the training pattern. While in this state, the deserializer will periodically send a link detect
signal upstream to notify the serializer that it can now send the training pattern. When the deserializer detects
that data coming in on the serial line, it will proceed to the CLOCK ACQUISITION state. While in this state the
deserializer will monitor the incoming data for set periods of time in an attempt to extract the clock from the data.
Once, the deserializer has successfully extracted the clock the device will proceed to the LINK ACQUISITION
STATE. In this state the deserializer will perform lane alignment based on the expected training pattern and then
enter the NORMAL state. If the deserializer is unable to successfully lock or maintain lock, it will break the link
sending the serializer back to the IDLE or LINK DETECT states.
DC-BALANCE DECODER
The DS32EL0124 and DS32ELX0124 have a built-in DC-balance decoder to support AC-coupled applications.
When enabled, the output signal RxOUT4+/-, is treated as a data valid bit. If RxOUT4+/- is low, then the data
output from RxOUT0 - RxOUT3 has been successfully decoded using the 8b/10b coding scheme. If RxOUT4+/is high and the outputs RxOUT0 - RxOUT3 are high then an invalid 8b/10b code was received, signifying a bit
error. If RxOUT4+/- is high and the outputs RxOUT0 - RxOUT3 are low then an idle character has been
received. The default idle character is a K28.5 code. In order to properly receive other K codes, they must first be
programmed into the deserializer via the SMBus. The SMBus registers allow for only a single programmable
character.
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Power-On/Reset
RxIN does not Exist
or
CDR Not Locked
or
Link Not Acquired
Or
Excessive Bit Errors
IDLE
RxIN
detected
RxIN detected
and
(RS:1, DC_B:0
or
RS:1, DC_B:1)
LINK DETECT
CLOCK
ACQUISITION
Clock
Recovered
CDR Locked
and
(RS:1, DC_B:0
or
RS:1, DC_B:1)
LINK
ACQUISITION
Link
Acquired
NORMAL
Figure 9. Deserializer State Diagram
DESCRAMBLER AND NRZI DECODER
The CDR of the deserializer expects a transition density of 20% for a period of 200 μs. To improve the transition
density of the data, the scrambler and NRZI encoder, which are integrated features in the DS32EL0421 and
DS32ELX0421, serializers can be enabled. If the descrambler is enabled, the serialized data is descrambled
after being recovered by the CDR to according to the polynomial specified in the DS32EL0421 datasheet. Using
the scrambler/descrambler helps to lower EMI emissions by spreading the spectrum of the data. Scrambling also
creates transitions for a deserializer’s CDR to properly lock onto.
The scrambler is enabled or disabled by default depending on how the DC_B and RS pins are configured. To
override the default scrambler setting two register writes must be performed. First, write to register 22’h and set
bit 5 to unlock the descrambler register. Next write to register 21’h and change bit 5 to the desired value. Please
note that NRZI decoder has its own control bits in registers 22'h and 21'h.
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CML INPUT INTERFACING
The DS32ELX0124 has two inputs to support redundancy and failover applications. Either input can be selected
by using the RX_MUX_SEL pin or internal control registers. Whichever input is selected will be routed to the
CDR of the deserializer. Only one input may be selected at a time. Within the CDR, the data is strobed at the
center of the eye diagram(i.e. 0.5UI).
The input stage is self-biased and does not need any external bias circuitry. The DS32EL0124 and
DS32ELX0124 include integrated input termination resistors. These deserializers also support a wide common
mode input from 50mV to Vcc - 50mV and can be DC-coupled where there is no significant Ground potential
difference between the interfacing systems. The serial inputs also provides input equalization control in order to
compensate for loss from the media. The level of equalization is controlled by the SMBus interface. For the
DS32ELX0124, each input can have its own independent equalizer settings.
It is recommended to use RxIN0+/- as the primary input. Due to its close proximity to the loop through driver,
RxIN1 has a typical performance less than RxIN0, with regards to cable length performance. When interfacing to
RxIN1+/- and transmitting with the loop through driver on TxOUT+/-, it is important to follow good layout practices
as described in the LAYOUT GUIDELINES section and in the LVDS Owner’s Manual. Poor layout techniques
can result in excessive cross talk coupled into RxIN1.
CML OUTPUT INTERFACING (DS32ELX0124 ONLY)
The retimed loop through serial outputs of the DS32ELX0124 provide low-skew differential signals. Internal
resistors connected from TxOUT+ and TxOUT- to VDD25 terminate the outputs. The output level can be set by
adjusting the pull-down resistor to the VOD_CTRL pin. The output terminations can also be programmed to be
either 50 or 75 ohms.
The output buffer consists of a current mode logic(CML) driver with user configurable de-emphasis control, which
can be used to optimize performance over a wide range of transmission line lengths and attenuation distortions
resulting from low cost CAT(-5, -6, -7) cable or FR4 backplane. Output de-emphasis is user programmable
through SMBus interface. Users can control the strength of the de-emphasis to optimize for a specific system
environment. Please see the Register Map, register 67'h bits 6:5, for details.
DEVICE CONFIGURATION
There are four ways to configure the DS32EL0124 and DS32ELX0124 devices, these combinations are shown in
Table 2. Refer to Figure 9 to see how the combinations of the RS and DC_B pins change the link startup
behavior of the deserializers. When connecting to a serializer other than the DS32EL0421 or DS32ELX0421,
Remote Sense should be disabled. The descrambler and NRZI decoder shown in Table 2 can be enabled or
disabled through register programming.
When Remote Sense is enabled, with RS pin tied low, the deserializer must be connected directly to a
DS32EL0421/DS32ELX0421 serializer without any active components between them. The Remote Sense
module features both an upstream and downstream communication method for the serializer to detect a
deserializer and vice versa. This feature is used to pass link status information between the 2 devices.
If DC-Balance is enabled, the maximum number of parallel LVDS lanes is four. The fifth lane becomes a Data
Valid signal (TXIN4±). If the Data Valid input to the serializer is logic high, then SYNC characters are transmitted.
If the deserializer receives a SYNC character, then the LVDS data outputs will all be logic low and the Data Valid
outputs will be logic high. If the deserializer detects a DC-Balance code error, the output data pins will be set to
logic high with the Data Valid output also set to logic high.
In the case where DC-Balance is enabled and Remote Sense is disabled, with RS set to high and DC_B set to
low, an external device should toggle the Data Valid input to the serializer periodically to ensure constant lock.
With these pin settings the devices can interface with other active component in the high speed signal path, such
as fiber modules. Every time a DS32EL0421/DS32ELX0421 serializer establishes a link to a
DS32EL0124/DS32ELX0124 deserializer with DC-Balance enabled and Remote Sense disabled, the Data Valid
input to the serializer must be held high for 110 LVDS clock periods. This allows the deserializer to extract the
clock and perform lane alignment while skipping the LINK ACQUISITION state.
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When both Remote Sense and DC-Balance are disabled, RS and DC_B pins set to high, the LVDS lane
alignment is not maintained. In this configuration, data formatting is handled by an FPGA or external source. In
this mode the deserializer locks to incoming random data. To achieve lock during the clock acquisition phase, the
incoming data should have a transition density of approximately 20% for a period of 200 µs. Scrambling and
NRZI encoding can be implemented to help improve the transition density of the data. This pin setting also allows
for the devices to interface with other active components in the high speed signal path.
Table 2. Device Configuration Table
Remote Sense Pin (RS)
DC-Balance Pin (DC_B)
Configuration
0
0
Remote Sense enabled
DC-Balance enabled
Data Alignment
De-Scrambler and NRZI decoder disabled by default
0
1
Remote Sense enabled
DC-Balance disabled
Data Alignment
De-Scrambler and NRZI decoder enabled by default
1
0
Remote Sense disabled
DC-Balance enabled
Data Alignment
De-Scrambler and NRZI decoder enabled by default
1
1
Remote Sense disabled
DC-Balance disabled
No Data Alignment
De-Scrambler and NRZI decoder disabled by default
SMBus INTERFACE
The System Management Bus interface is compatible to SMBus 2.0 physical layer specification. The use of the
Chip Select signal is required. Holding the SMB_CS pin HIGH enables the SMBus port, allowing access to the
configuration registers. Holding the SMB_CS pin LOW disables the device's SMBus, allowing communication
from the host to other slave devices on the bus. In the STANDBY state, the System Management Bus remains
active. When communication to other devices on the SMBus is active, the SMB_CS signal for the deserializer
must be driven LOW.
The address byte for all DS32EL0124 and DS32ELX0124 devices is B0'h. Based on the SMBus 2.0
specification, these devices have a 7-bit slave address of 1011000'b. The LSB is set to 0'b (for a WRITE), thus
the 8-bit value is 1011 0000'b or B0'h.
The SCK and SDA pins are 3.3V LVCMOS signaling and include high-Z internal pull up resistors. External low
impedance pull up resistors maybe required depending upon SMBus loading and speed. Note, these pins are not
5V tolerant.
Transfer of Data via the SMBus
During normal operation the data on SDA must be stable during the time when SCK is HIGH.
There are three unique states for the SMBus:
START
A HIGH to LOW transition on SDA while SCK is HIGH indicates a message START condition.
STOP
A LOW to HIGH transition on SDA while SCK is HIGH indicates a message STOP condition.
IDLE
If SCK and SDA are both HIGH for a time exceeding tBUF from the last detected STOP condition or if they are HIGH for a total
exceeding the maximum specification for tHIGH then the bus will transfer to the IDLE state.
SMBus Transactions
The devices support WRITE and READ transactions. See Register Map for register address, type (Read/ Write,
Read Only), default value and function information.
Writing to a Register
The devices support WRITE and READ transactions. See Register Map for register address, type (Read/ Write,
Read Only), default value and function information.
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1.
2.
3.
4.
5.
6.
7.
8.
9.
The
The
The
The
The
The
The
The
The
SNLS284K – MAY 2008 – REVISED APRIL 2013
Host (Master) selects the device by driving its SMBus Chip Select (SMB_CS) signal HIGH.
Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
Device (Slave) drives the ACK bit (“0”).
Host drives the 8-bit Register Address.
Device drives an ACK bit (“0”).
Host drive the 8-bit data byte.
Device drives an ACK bit (“0”).
Host drives a STOP condition.
Host de-selects the device by driving its SMBus CS signal Low.
The WRITE transaction is completed, the bus goes IDLE and communication with other SMBus devices may
now occur.
Reading a Register
To read a register, the following protocol is used (see SMBus 2.0 specification).
1. The Host (Master) selects the device by driving its SMBus Chip Select (SMB_CS) signal HIGH.
2. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
3. The Device (Slave) drives the ACK bit (“0”).
4. The Host drives the 8-bit Register Address.
5. The Device drives an ACK bit (“0”).
6. The Host drives a START condition.
7. The Host drives the 7-bit SMBus Address, and a “1” indicating a READ.
8. The Device drives an ACK bit “0”.
9. The Device drives the 8-bit data value (register contents).
10. The Host drives a NACK bit “1”indicating end of the READ transfer.
11. The Host drives a STOP condition.
12. The Host de-selects the device by driving its SMBus CS signal Low.
The READ transaction is completed, the bus goes IDLE and communication with other SMBus devices may now
occur.
SMBus Configurations
Many different configurations of the SMBus are possible and depend upon the specific requirements of the
applications. Several possible applications are described.
Configuration 1
The deserializer SMB_CS may be tied High (always enabled) since it is the only device on the SMBus. See
Figure 10.
Configuration2
Since the multiple SER devices have the same address, the use of the individual SMB_CS signals is required.
To communicate with a specific device, its SMB_CS is driven High to select the device. After the transaction is
complete, its SMB_CS is driven Low to disable its SMB interface. Other devices on the bus may now be selected
with their respective chip select signals and communicated with. See Figure 11.
Configuration 3
The addressing field is limited to 7-bits by the SMBus protocol. Thus it is possible that multiple devices may
share the same 7-bit address. An optional feature in the SMBus 2.0 specification supports an Address Resolution
Protocol (ARP). This optional feature is not supported by the DS32EL0124/DS32ELX0124 devices. Solutions for
this include: the use of the independent SMB_CS signals, independent SMBus segments, or other means.
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SMBus
Device
FPGA
Host
3V3
SMB_CS
SDA
LVCMOS GPIO
SMBus Interface
SCK
3V3
Figure 10. SMBus Configuration 1
SMBus
Device
FPGA
Host
SMBus
Device
SMBus
Device
SMB_CS
SDA
SCK
SMB_CS
SDA
SCK
SMB_CS
SDA
LVCMOS GPIO
SMBus Interface
SCK
3V3
Figure 11. SMBus Configuration 2
SMBus
Device
SMBus
Device
3V3
SMB_CS
SDA
SCK
SMB_CS
3V3
SDA
SMB_CS
SDA
SCK
LVCMOS GPIO
SMBus Interface
SMBus
Device
3V3
3V3
SCK
FPGA
Host
Figure 12. SMBus Configuration 3
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PROPAGATION DELAY
Once the deserializer is locked, the amount of time it takes for a signal to travel from the high speed CML serial
input through the device and out via the DDR LVDS interface is defined to be the propagation delay. The
propagation delay through the DS32EL0124/DS32ELX0124 due to the analog circuitry is considered negligible
compared to the time delay caused by the digital components. The information presented in this section allows
system designers to predict the propagation delay through the device in terms of clock cycles which are
proportional to the high speed serial line rate.
Each clock cycle shown inFigure 13 is defined to be 1/20th of the high speed serial bit rate. For example, at a
serial line rate of 3.125 Gbps the clock frequency of each delay cycle would be 156.25 MHz. Note, this is not the
same frequency as the LVDS outputs, which would be 312.5 MHz for a serial line rate of 3.125 Gbps. Dashed
lines in Figure 13 indicate that the feature is disabled by default in that mode and therefore add no more time to
the total propagation delay. In the last row, bypassed indicates that the data is sampled even though the feature
is disabled by default. The sampling of the data results in an added amount of propagation delay as specified in
the box.
Config Pins
(RS, DC_B)
CML Interface
NRZ Decoder
Descrambler
Lane
Alignment
Logic
DC Balance
Decoder
LVDS
Interface
Total
Propagation
Delay
3 clocks
1 clock
3-4 clocks
9-10 clocks
1 clock
3-4 clocks
11-12 clocks
Data Flow
0, 0
2 clocks
0, 1
2 clocks
1 clock
1 clock
3 clocks
1, 0
2 clocks
1 clock
1 clock
3 clocks
3-4 clocks
10-11 clocks
1, 1
2 clocks
1 clock
(bypassed)
1 clock
(bypassed)
3 clocks
3-4 clocks
10-11 clocks
Figure 13. Deserializer Propagation Delay
PROPAGATION DELAY FOR RETIMED LOOP THROUGH DRIVER — DS32ELX0124 ONLY
If the loop through driver is enabled in the DS32ELX0124, the propagation delay can also be defined as the
amount of time it takes a signal to pass from the high speed CML serial input to the retimed loop through driver
output. This time delay is measured in CDR clock cycles. The CDR clock frequency is equal to high speed serial
line rate or one high speed serial bit width. For example, if the high speed serial line rate is 3.125 Gbps, then the
CDR clock frequency is 3.125 GHz. The propagation delay from the high speed input to the loop through driver
output is 1 CDR clock.
Applications Information
GPIO PINS
The GPIO pins can be useful tools when debugging or evaluating the system. For specific GPIO configurations
and functions refer to registers 2, 3, 4, 5 and 6 in the device register map.
GPIO pins are commonly used when there are multiple deserializers on the same SMBus. In order to program
individual settings into each serializer, they will each need to have a unique SMBus address. To reprogram
multiple deserializers on a single SMBus, configure the first deserializer such that the SMBus lines are connected
to the FPGA or host controller. The CS pin of the second serializer should be tied to GPIO0 of the first
deserializer, with the CS pin of the next deseriazlier tied to GPIO0 of its preceding deserializer. By holding all of
the GPIO0 pins low, the first deserializer’s address may now be reprogrammed by writing to register 0. The first
deserializer’s GPIO pin can now be asserted and the second deserializer’s address may now be reprogrammed.
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HIGH SPEED COMMUNICATION MEDIA
Using the deserializer’s integrated equalizer blocks in combination with the DS32EL0421 or DS32ELX0421’s
integrated de-emphasis block allows data to be transmitted across a variety of media at high speeds. Factors
that can limit device performance include excessive input clock jitter, noisy power rails, EMI from nearby noisy
components and poor layout techniques. Although many cables contain wires of similar gauge and shielding,
performance can vary greatly depending on the quality of the connector.
The DS32ELX0124 also has a programmable de-emphasis block on its retimed loop through output TxOUT+/-.
The de-emphasis setting for the loop through driver is programmed through the SMBus.
REDUNDANCY APPLICATIONS
The DS32ELX0124 has two high speed CML serial inputs. SMBus register control allows the host device to
monitor for errors or link loss on the active input channel. This enables the host device, usually an FPGA, to
switch to the secondary input if problems occur with the primary input.
LINK AGGREGATION
Multiple DS32EL0421/DS32ELX0421 serializers and D32EL0124/DS32ELX0124 deserializers can be
aggregated together if an application requires a data throughput of more than 3.125 Gbps. By utilizing the data
valid signal of each device, the system can be properly deskewed to allow for a single cable, such as CAT-6,
DVI-D, or HDMI, to carry data payloads beyond 3.125 Gbps.
Link aggregation configurations can also be implemented in applications which require longer cable lengths. In
these type of applications the data rate of each serializer and deserializer chipset can be reduced, such that the
applications' net data throughput is still the same. Since each high speed channel is now operating at a fraction
of the original data rate, the loss over the cable is reduced, allowing for greater lengths of cable to be used in the
system.
For more information regarding link aggregation please see Application Note 1887, Expanding the Payload with
TI's FPGA-Link DS32ELX0421 and DS32ELX0124 Serializer and Deserializer.
REACH EXTENSION
The DS32ELX0124 deserializer contains a retimed loop through CML serial output. The loop through driver also
has programmable de-emphasis making this device capable of reach extension applications.
DAISY CHAINING
The loop through driver of the DS32ELX0124 deserializer can be used to string together deserializers in a daisy
chain configuration. This allows a single data source such as a DS32EL0421 serializer to communicate to
multiple receiving systems.
LAYOUT GUIDELINES
It is important to follow good layout practices for high speed devices. The length of LVDS input traces should not
exceed 40 inches. In noisy environments the LVDS traces may need to be shorter to prevent data corruption due
to EMI. Noisy components should not be placed next to the LVDS or CML traces. The LVDS and CML traces
must have a controlled differential impedance of 100Ω. Do not place termination resistors at the CML inputs or
output, the DS32EL0124 and DS32ELX0124 have internal termination resistors. It is recommended to avoid
using vias. Each pair of vias creates an impedance mismatch in the transmission line and result in reflections,
which can greatly lower the maximum distance of the high speed data link. If vias are required, they should be
placed symmetrically on each side of the differential pair. For more tips and detailed suggestions regarding high
speed board layout principles, please consult the LVDS Owner’s Manual.
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2.5V
3.3V
0.1 PF
0.1 PF
RXOUT4
-
19
RXOUT3
+
RXIN1
20 -
RXOUT2
RXOUT1
RXOUT0
+
-
VOD_CTRL
RXCLKOUT
27
+
-
DS32ELX0124
14
+
-
VDDPLL
22 PF
9.1 k:
+
-
3.3V
28
+
+
-
LF_CP
30 nF
26
RESET
LF_REF
LOCK
6
21
TXOUT-
DC_B
5
3.3V
RS
GPIO0
4
GPIO1
11
GPIO2
TXOUT+
3
47
48
45
46
43
44
41
42
39
40
37
FPGA Host
VCC25
GND
16 +
RXIN0
17 -
1, 15, 18,
28, 36
VCC33
7, 25,
35
49
38
30
31
SDA 32
SCK 33
SMB_CS 34
22
3.3V
0.1 PF
0.1 PF
Figure 14. Typical Interface Circuit
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DS32EL0124, DS32ELX0124
SNLS284K – MAY 2008 – REVISED APRIL 2013
www.ti.com
Typical Performance Characteristics
The eye diagrams shown below illustrate the typical performance of the DS32ELX0124/DS32EL0124 configured with RS = 0,
DC_B = 0, for the conditions listed below each figure. The PRBS-15 data was generated by a low cost FPGA, which used an
LMK03000C to generate the various clock frequencies. The data was then sent to a DS32ELX0421 configured with RS = 0,
DC_B = 0, which transmitted the data across the specified cable type and length at the specified data rate. The signal
conditioning settings used for each measurement are also listed below the figures.
22
Figure 15. LVDS RxCLKOUT Output
(1.25 Gbps, 40m CAT-5e, 0x000 DS32ELX0124 EQ setting,
0x10 DS32EL0421 De-Emphasis setting)
Figure 16. LVDS RxOUT0 Output
(1.25 Gbps, 40m CAT-5e, 0x000 DS32ELX0124 EQ setting,
0x10 DS32EL0421 De-Emphasis setting)
Figure 17. LVDS RxCLKOUT Output
(3.125 Gbps, 20m CAT-6 SCTP, 0x001 DS32ELX0124 EQ
setting, 0x10 DS32EL0421 De-Emphasis setting)
Figure 18. LVDS RxOUT0 Output
(3.125 Gbps, 20m CAT-6 SCTP, 0x001 DS32ELX0124 EQ
setting, 0x10 DS32EL0421 De-Emphasis setting)
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SNLS284K – MAY 2008 – REVISED APRIL 2013
Typical Performance Characteristics (continued)
The eye diagrams shown below illustrate the typical performance of the DS32ELX0124/DS32EL0124 configured with RS = 0,
DC_B = 0, for the conditions listed below each figure. The PRBS-15 data was generated by a low cost FPGA, which used an
LMK03000C to generate the various clock frequencies. The data was then sent to a DS32ELX0421 configured with RS = 0,
DC_B = 0, which transmitted the data across the specified cable type and length at the specified data rate. The signal
conditioning settings used for each measurement are also listed below the figures.
Figure 19. Retimed Loop Through Output
(1.25 Gbps, 40m CAT-5e, 0x000 DS32ELX0124 EQ setting,
0x10 DS32EL0421 De-Emphasis setting)
Figure 20. Retimed Loop Through Output
(3.125 Gbps, 20m CAT-6 SCTP, 0x001 DS32ELX0124 EQ
setting, 0x10 DS32EL0421 De-Emphasis setting)
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DS32EL0124, DS32ELX0124
SNLS284K – MAY 2008 – REVISED APRIL 2013
www.ti.com
Register Map
The register information for the deserializer is shown in the table below. Some registers have been omitted or
marked as reserved; these are for internal testing and should not be written to. Some register bits require an
override bit to be set before they can be written to.
Addr (Hex)
Name
00
Device ID
01
Reset
02
03
04
05
06
GPIO0 Config
GPIO1 Config
GPIO2 Config
GP In
GP Out
Bits
Field
R/W
R/W
Default
58'h
Description
7:1
SMBus Address
Some systems will use all 8 bits as the device
ID. This will shift the value from 58’h to B0’h
0
Reserved
7:1
Reserved
0
Software Reset
R/W
0
Reset the device. Does not affect device ID.
7:4
GPIO0 Mode
R/W
0
0000: GP Out
0001: Signal Detect RxIN0
0010: BIST Status
All Others: Reserved
3:2
GPIO0 R Enable
R/W
01'b
00:
01:
10:
11:
1
Input Enable
R/W
0
0: Input buffer disabled
1: Input buffer enabled
0
Output Enable
R/W
1'b
0: Output Tri-State™
1: Output enabled
7:4
GPIO1 Mode
R/W
0
0000: Power On Reset
0001: GP Out
0010: Signal Detect RxIN1
0011:CDR Lock
All Others: Reserved
3:2
GPIO1 R Enable
R/W
01'b
00:
01:
10:
11:
1
Input Enable
R/W
0
0: Input buffer disabled
1: Input buffer enabled
0
Output Enable
R/W
1
0: Output Tri-State™
1: Output enabled
7:4
GPIO2 Mode
R/W
0
0000: GP Out
0001: Always on Clock Out
0010: LVDS Tx CLK
0011: CDR CLK
All Others: Reserved
3:2
GPIO2 R Enable
R/W
01'b
00:
01:
10:
11:
1
Input Enable
R/W
0
0: Input buffer disabled
1: Input buffer enabled
0
Output Enable
R/W
1'b
0: Output Tri-State™
1: Output enabled
7:3
Reserved
2
GP In 2
R
0
Input value on GPIO2
1
GP In 1
R
0
Input value on GPIO1
0
GP In 0
R
0
Input value on GPIO0
7:3
Reserved
2
GP Out 2
R/W
0
Output value on GPIO2
1
GP Out 1
R/W
0
Output value on GPIO1
0
GP Out 0
R/W
0
Output value on GPIO0
0
0
Pullup/Pulldown disabled
Pulldown Enabled
Pullup Enabled
Reserved
Pullup/Pulldown disabled
Pulldown Enabled
Pullup Enabled
Reserved
Pullup/Pulldown disabled
Pulldown Enabled
Pullup Enabled
Reserved
0
07 — 1F Reserved
24
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SNLS284K – MAY 2008 – REVISED APRIL 2013
Addr (Hex)
20
21
22
Name
Device Config
0
Device Config
1
Device Config
Override
Bits
Field
R/W
R/W
Default
0
Description
7
LVDS Always On Clock
1: Disable
0: When not locked switch to Always On
Clock
6:3
Reserved
2
Reverse Data Order
R/W
0
0: Normal
1: Reverse output data order
1
Reset Channel
R/W
0
Reset input high speed channel
0
Digital Power Down
R/W
0
Power down parallel, seria-to-parallell, and
always on clock
7
Reserved
6
NRZI Decode Enable
R/W
0
Enable NRZI decoding of incoming data;
requires an override bit
5
Descramble Enable
R/W
0
Enabled the descrambler, requires an
override bit
4
Rx Mux
R/W
0
RX_MUX_SEL control register. requires an
override bit
3
Decode Bypass
R/W
0
Bypass DC Balance decoder. requires an
override bit
2
Training Sequence
Enable
R/W
0
Enable training sequence. requires an
override bit
1:0
Device Configuartion
R/W
0
MSB: Remote Sense enable, active low
LSB: DC balance encoder enable, active low
requires an override bit
7
Reserved
6
NRZ Override
R/W
0
Unlock bit 6 of register 21'h
5
Descramble Override
R/W
0
Unlock bit 5 of register 21'h
4
Rx Mux Override
R/W
0
Unlock bit 4 of register 21'h
3
Reserved
2
Decode Bypass Override R/W
0
Unlock bit 3 of register 21'h
1
Traning Override
R/W
0
Unlock bit 2 of register 21'h
0
Device Config Override
R/W
0
Unlock bits 1 and 0 of register 21'h
7
LVDS VOD High
R/W
0
0: LVDS VOD normal operation. Setting used
in Electrical Characteristics Table
1: Increases VOD. Allows for longer traces to
be driven, but consume more power
6
LVDS Control
R/W
0
1: Allow SMBus to control LVDS per channel
enable
5
RxCLKOUT Enable
R/W
0
Enables RxCLKOUT output driver
4
RxOUT4 Enable
R/W
0
Enables RxOUT4 output driver
3
RxOUT3 Enable
R/W
0
Enables RxOUT3 output driver
2
RxOUT2 Enable
R/W
0
Enables RxOUT2 output driver
1
RxOUT1 Enable
R/W
0
Enables RxOUT1 output driver
0
RxOUT0 Enable
R/W
0
Enables RxOUT0 output driver
7
Reserved
6
LVDS Reset
R/W
0
Resets LVDS block
5
LVDS Clock Rate
R/W
1
0:RxCLKOUT is DDR/2
1: RxCLKOUT is DDR
4
LVDS Clock Invert
R/W
0
Inverts the polarity of the RxCLKOUT signal
3:2
LVDS Clock Delay
R/W
10'b
00: 160 ps
11: -80 ps
80 ps step size
1:0
Reserved
0
0
0
0
23 — 26 Reserved
27
28
LVDS Per
Channel
Enable
LVDS Config
0
0
29 — 2A Reserved
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DS32EL0124, DS32ELX0124
SNLS284K – MAY 2008 – REVISED APRIL 2013
Addr (Hex)
2B
Name
Event Config
2C
Reserved
2D
Error Monitor
www.ti.com
Bits
Field
R/W
Default
Description
7:4
Reserved
0
3
Event Count Select
R/W
0
0: Select CDR Event Counter for reading.
Events include loss of signal detect or loss of
CDR lock.
1: Select Data Event Counter for reading
2
Reset CDR Error Count
R/W
0
Resets CDR event count
1
Reset Link Error Count
R/W
0
Reset data event count
0
Enable Count
R/W
0
Enable event coutners
7:5
Reserved
4
Accumulate Error Enable R/W
0
1: Enable counting accumulation of errors
3
8b/10b Error disable
R/W
0
1: Disables 8b/10b decode errors from being
counted or flagged on LOCK pin
2
Clear Event Counter
R/W
0
1: clears errors in both the current and
previous state of teh errors count
1
Select Error Count
R/W
0
0: Number of errors in current run
1: Number of errors within the selected timing
window
0
Normal Error Disable
R/W
0
1: Disable exiting NORMAL state when the
number of errors exceeds the error threshold
0
2E
Error
Threshold
LSBs
7:0
Error Threshold
R/W
10'h
Error threshold above which part stops
transmittion of data — LSB
2F
Error
Threshold
MSBs
7:0
Error Threshold
R/W
0
Error threshold above which part stops
transmittion of data — MSB
7
Reserved
6:4
Frequency Range
R
111'b
001:
010:
011:
100:
101:
110:
111:
3:2
BIST Status
R
0
00:
01:
10:
11:
1
BIST Done
R
0
BIST pattern done. Set when not using
repeat.
0
BIST Allign Done
R
0
Alignment of incoming data done
30 — 3A Reserved
3B
Data Rate
0
Reserved
1 — 1.3 Gbps
1.2 — 1.8 Gbps
1.5 — 2.1 Gbps
1.9 — 2.7 Gbps
2.4 — 3.2 Gbps
No Lock
BIST passed
BIST failed to capture PREAMBLE
BIST pattern mode failed
BIST data sequence failed
3C
Reserved
3D
Event Status
7:0
Event Count
R
0
Count of errors that caused a loss of link
3E
Error Status
LSBs
7:0
Data Error Count
R
0
Number of errors in data — LSB
3F
Errors Status
MSBs
7:0
Data Error Count
R
0
Number of errors in data — MSB
40 — 49 Reserved
26
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SNLS284K – MAY 2008 – REVISED APRIL 2013
Addr (Hex)
49
60
61
Name
Loop Through
Driver Config
EQ Attenuator
EQ Boost
Control
62
Reserved
63
EQ Override
Control
Bits
Field
R/W
Default
Description
7:5
Reserved
0
4
Termination Select
R/W
1
0: 75Ω
1: 50 Ω
3:1
Output Amplitude Adjust
R/W
011'b
000:
001:
010:
011:
100:
101:
110:
111:
0
Reserved
0
7:4
Reserved
0
3
Attenuator 0 Override
R/W
0
Overrides attenuation control in EQ 0
2
Attenuator 1 Override
R/W
0
Overrides attenuation control in EQ 1
1
Attenuator 0 Enable
R/W
0
1: enables attenuatorfor for EQ 0. Requires bit
3 to be set
0
Attenuator 1 Enable
R/W
0
Enables attenuato for EQ 1. Requires bit 2 to
be set.r
7:5
EQ 0 Boost Control
0
Sets EQ level for RxIN0. Requires override bit
000: Off
x10: Low (or 110)
x01: Mid (or 101)
x11: High (or 111)
4:2
EQ 1 Boost Control
0
Sets EQ level for RxIN1. Requires override bit
000: Off
x10: Low (or 110)
x01: Mid (or 101)
x11: High (or 111)
1:0
Reserved
0
7
Reserved
1
6
Reserved
5
EQ 0 Enable
R/W
1
1: Enables EQ for RxIN0
4
EQ 1 Enable
R/W
0
1: Enables EQ for RxIN1
3:0
Reserved
0
7
Reserved
0
6:5
De-Emphasis Setting
0
4:0
Reserved
0
Level
Level
Level
Level
Level
Level
Level
Level
7
8 (Highest output)
5
6 (Normal output)
4
3
2
1 (Lowest output)
1
64 — 66 Reserved
67
LT DeEmphasis
Control
00:
01:
10:
11:
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: DS32EL0124 DS32ELX0124
Off
Low
Med
Max
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DS32EL0124, DS32ELX0124
SNLS284K – MAY 2008 – REVISED APRIL 2013
www.ti.com
REVISION HISTORY
Changes from Revision J (April 2013) to Revision K
•
28
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 24
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
DS32EL0124SQ/NOPB
ACTIVE
WQFN
RHS
48
1000
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
32EL0124
DS32EL0124SQE/NOPB
ACTIVE
WQFN
RHS
48
250
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
32EL0124
DS32EL0124SQX/NOPB
ACTIVE
WQFN
RHS
48
2500
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
32EL0124
DS32ELX0124SQE/NOPB
ACTIVE
WQFN
RHS
48
250
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
32ELX0124
DS32ELX0124SQX/NOPB
ACTIVE
WQFN
RHS
48
2500
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
32ELX0124
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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