DS32EV100-EVK User Guide
DS32EV100 Programmable Equalizer
Overview
The DS32EV100-EVK evaluation board provides a typical application for the evaluation of the DS32EV100
programmable equalizer.
Specifications
DC Input Power (JP1): 3.3V ± 10%, or 2.5V ± 5%
Serial Data Inputs (IN_+/- ): High-speed CML inputs. Acceptable data input speed DC – 3.2 Gbps. For more
details, please refer to the datasheet.
Serial Data Outputs (OUT_+/- ): High-speed CML outputs. For more details, please refer to the datasheet.
CML Input Voltage: -0.5V to 4.0V
CMOS Input Voltage: -0.5V to 4.0V
Jumper Settings
E101 ( EQ_SEL[0:2] ): These jumpers are control equalization boost levels. The boost setting on the evaluation
board is set to 111 with on board pull up resistors R101, R102, R103 connected to VCC.
IMPORTANT ERRATA:
EQUALIZATION SETTINGS E101( EQ_SEL[2:0]/BST[2:0]) These pins control the boost level and currently
only have the option to be connected to ground using jumpers. In order to select maximum equalization
the EQ_SEL[0:2]/BST[0:2] must be hardwired to Vdd. When selecting these EQ settings please use
external hardware to force Vdd on these pins.
Please see Table 1 for equalizer boost control settings.
Table 1. Equalization Boost Controls
6 mil microstrip FR4
trace length (in)
0
5
10
15
20
25
30
40
24 AWG Twin-AX cable
length (m)
0
2
3
4
5
6
7
10
DS32EV100-EVK User Guide
November 2007
© National Semiconductor Corporation
Channel loss at 1.6 GHz
[BST_2, BST_1, BST_0]
0 dB
3 dB
6 dB
7 dB
8 dB
10 dB
12 dB
14 dB
000
001
010
011
1 0 0 (Default)
101
110
111
Bill of Materials
DESIGNATION
C105
C101, C102, C103, C104, C106,
C108
C107
C109
R101, R102, R103
JP101
E101
J101, J102, J103, J104
U1
Schematics
DS32EV100-EVK User Guide
November 2007
© National Semiconductor Corporation
QTY
1
DESCRIPTION
0.01uF +10% Ceramic Capacitor 0402
6
1
1
3
1
1
4
1
0.1uF +10% Ceramic Capacitor 0402
4.7uF +10% Ceramic Capacitor 1206
22uF +10% Tan Capacitor 6032
4 Pin Header
3X2 Pin Header
SMA Edge Tab Receptacle
National DS32EV100
Top View Layout
DS32EV100-EVK User Guide
November 2007
© National Semiconductor Corporation
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