DS36277TMX/NOPB

DS36277 www.ti.com SNLS086E – JULY 1998 – REVISED APRIL 2013 Dominant Mode Multipoint Transceiver Check for Samples: DS36277 FEATURES DESCRIPTION • The DS36277 Dominant Mode Multipoint Transceiver is designed for use on bi-directional differential busses. It is optimal for use on Interfaces that utilize Society of Automotive Engineers (SAE) J1708 Electrical Standard. 1 2 • • • • • FAILSAFE Receiver, RO = HIGH for: – OPEN Inputs – Terminated Inputs – SHORTED Inputs Optimal for Use in SAE J1708 Interfaces Compatible with Popular Interface Standards: – TIA/EIA-485 and TIA/EIA-422-A – CCITT Recommendation V.11 Bi-Directional Transceiver – Designed for Multipoint Transmission Wide Bus Common Mode Range – (−7V to +12V) Available in PDIP and SOIC Packages The device is similar to standard TIA/EIA-485 transceivers, but differs in enabling scheme. The Driver's Input is normally externally tied LOW, thus providing only two states: Active (LOW), or Disabled (OFF). When the driver is active, the dominant mode is LOW, conversely, when the driver is disabled, the bus is pulled HIGH by external bias resistors. The receiver provides a FAILSAFE feature that ensures a known output state when the Interface is in the following conditions: Floating Line, Idle Line (no active drivers), and Line Fault Conditions (open or short). The receiver output is HIGH for the following conditions: Open Inputs, Terminated Inputs (50Ω), or Shorted Inputs. FAILSAFE is a highly desirable feature when the transceivers are used with Asynchronous Controllers such as UARTs. Connection and Logic Diagram See Package Number D (R-PDSO-G8) or P (R-PDIP-T8) 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1998–2013, Texas Instruments Incorporated DS36277 SNLS086E – JULY 1998 – REVISED APRIL 2013 www.ti.com Truth Table Driver Inputs Outputs DE DI DO/RI DO /RI L L L H L H H L H X Z Z Receiver Inputs Output RE DO/RI–DO /RI RO L ≥ 0 mV H L ≤ −500 mV L L SHORTED H L OPEN H H X Z These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) Supply Voltage (VCC) Input Voltage (DE , RE , and DI) Unit 7 V 5.5 V −10V to +15 V 5.5 V P Package (derate 9.3 mW/°C above +25°C) 1168 mW D Package (derate 5.8 mW/°C above +25°C) 726 mW −65°C to +150 °C Driver Output Voltage/Receiver Input Voltage Receiver Output Voltage (RO) Maximum Package Power Dissipation @ +25°C Value Storage Temperature Range Lead Temperature (Soldering 4 sec.) 260 °C ESD Rating (HBM, 1.5 kΩ, 100 pF) 7.0 kV (1) (2) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be specified. They are not meant to imply that the devices should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Recommended Operating Conditions Supply Voltage, VCC Bus Voltage Operating Temperature (TA) DS36277T 2 Submit Documentation Feedback Min Max Units 4.75 5.25 V −7 +12 V −40 +85 °C Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: DS36277 DS36277 www.ti.com SNLS086E – JULY 1998 – REVISED APRIL 2013 Electrical Characteristics (1) (2) Over recommended Supply Voltage and Operating Temperature ranges, unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units 1.5 3.6 DRIVER CHARACTERISTICS VOD Differential Output Voltage IO = 0 mA (No Load) VoDO Output Voltage IO = 0 mA (Output to GND) VoDO Output Voltage VT1 Differential Output Voltage (Termination Load) RL = 54Ω (485) ΔVT1 Balance of VT1 |VT1 − VT1 | RL = 54Ω VOS Driver Common Mode Output Voltage RL = 54Ω ΔVOS (Figure 1) RL = 100Ω (422) See (3) VOH Output Voltage High IOH = −22 mA VOL Output Voltage Low IOL = +22 mA IOSD Driver Short-Circuit Output Current VO = +12V V 0 6 V 1.3 2.2 5.0 V 1.7 2.6 5.0 V 0.2 V −0.2 (Figure 1) RL = 100Ω RL = 54Ω V 6 −0.2 RL = 100Ω Balance of VOS |VOS − VOS | 6 0 See (3) RL = 100Ω (Figure 2) 0.2 V 0 2.5 3.0 V 0 2.5 3.0 V −0.2 0.2 V −0.2 0.2 V 2.7 3.7 1.3 (Figure 3) VO = −7V V 2 V 92 290 mA −187 −290 mA −0.150 0 V RECEIVER CHARACTERISTICS Differential Input High Threshold Voltage (4) VO = VOH, IO = −0.4 mA VTL Differential Input Low Threshold Voltage (4) VO = VOL, IO = 8.0 mA VHST Hysteresis (5) VCM = 0V IIN Line Input Current (VCC = 4.75V, 5.25V, 0V) Other Input = 0V DE = VIH (6) IOSR Short Circuit Current VO = 0V IOZ TRI-STATE Leakage Current VO = 0.4 to 2.4V VOH Output High Voltage (Figure 12) VOL Output Low Voltage (Figure 12) VID = −0.5V, IOL = +8 mA 0.3 0.7 V VID = −0.5V, IOL = +16 mA 0.3 0.8 V VTH RIN −7V ≤ VCM ≤ +12V −0.5 −0.230 V −7V ≤ VCM ≤ +12V 80 mV VI = +12V 0.5 1.5 mA VI = −7V −0.5 −1.5 mA −15 −32 −85 mA −20 1.4 +20 μA VID = 0V, IOH = −0.4 mA 2.3 3.7 VID = OPEN, IOH = −0.4 mA 2.3 3.7 RO Input Resistance 10 V V 20 kΩ DEVICE CHARACTERISTICS VIH High Level Input Voltage VIL Low Level Input Voltage IIH High Level Input Current VIH = 2.4V IIL Low Level Input Current VIL = 0.4V VCL Input Clamp Voltage ICL = −18 mA ICC Output Low Voltage Supply Current (No Load) DE , RE , or DI 2.0 VCC V GND 0.8 V 20 μA −100 μA −0.7 −1.5 V DE = 0V, RE = 0V, DI = 0V 39 60 mA DE = 3V, RE = 0V, DI = 0V 24 50 mA ICCD DE = 0V, RE = 3V, DI = 0V 40 75 mA ICCX DE = 3V, RE = 3V, DI = 0V 27 45 mA ICCR (1) (2) (3) (4) (5) (6) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground unless otherwise specified. All typicals are given for VCC = 5.0V and TA = +25°C. Δ |VT1| and Δ |VOS| are changes in magnitude of VT1 and VOS, respectively, that occur when the input changes state. Threshold parameter limits specified as an algebraic value rather than by magnitude. Hysteresis defined as VHST = VTH − VTL. IIN includes the receiver input current and driver TRI-STATE leakage current. Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: DS36277 3 DS36277 SNLS086E – JULY 1998 – REVISED APRIL 2013 www.ti.com Switching Characteristics (1) Over recommended Supply Voltage and Operating Temperature ranges, unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units DRIVER CHARACTERISTICS tPLHD Diff. Prop. Delay Low to High RL = 54Ω 8 17 60 ns tPHLD Diff. Prop. Delay High to Low CL = 50 pF 8 19 60 ns tSKD Diff. Skew (|tPLHD–tPHLD|) CD = 50 pF 2 10 ns tr Diff. Rise Time (Figure 4 and Figure 5) 11 60 ns tf Diff. Fall Time 11 60 ns tPLH Prop. Delay Low to High 22 85 ns tPHL Prop. Delay High to Low RL = 27Ω, CL = 15 pF (Figure 6 and Figure 7) 25 85 ns tPZH Enable Time Z to High 25 60 ns tPZL Enable Time Z to Low RL = 110Ω CL = 50 pF (Figure 8 – Figure 11 ) 30 60 ns tPHZ Disable Time High to Z 16 60 ns tPLZ Disable Time Low to Z 11 60 ns 15 37 90 ns 15 43 90 ns 6 15 ns 12 60 ns RECEIVER CHARACTERISTICS VID = −1.5V to +1.5V CL = 15 pF (Figure 13 and Figure 14) tPLH Prop. Delay Low to High tPHL Prop. Delay High to Low tSK Skew (|tPLH–tPHL|) tPZH Enable Time Z to High tPZL Enable Time Z to Low 28 60 ns tPHZ Disable Time High to Z 20 60 ns tPLZ Disable Time Low to Z 10 60 ns (1) 4 CL = 15 pF (Figure 15 and Figure 16) All typicals are given for VCC = 5.0V and TA = +25°C. Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: DS36277 DS36277 www.ti.com SNLS086E – JULY 1998 – REVISED APRIL 2013 PARAMETER MEASUREMENT INFORMATION Figure 1. Driver VT1 and VOS Test Circuit Figure 2. Driver VOH and VOL Test Circuit Figure 3. Driver Short Circuit Test Circuit CL includes probe and stray capacitance The input pulse is supplied by a generator having the following characteristics: f=1.0 MHz, 50% duty cycle, Tr and tf