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DS40MB200
SNLS144J – JUNE 2005 – REVISED JANUARY 2016
DS40MB200 Dual 4-Gbps 2:1/1:2 CML MUX/Buffer With Transmit Pre-Emphasis and
Receive Equalization
1 Features
3 Description
•
•
•
•
The DS40MB200 device is a dual signal conditioning
2:1 multiplexer (MUX) and 1:2 fan-out buffer designed
for use in backplane-redundancy applications. Signal
conditioning features include continuous time linear
equalization (CTLE) and programmable output preemphasis, extending data communication in FR4
backplanes at rates up to 4 Gbps. Each input stage
has a fixed equalizer to reduce intersymbol
interference distortion from board traces.
1
•
•
•
•
•
•
1-Gbps to 4-Gbps Low Jitter Operation
Fixed Input Equalization
Programmable Output Pre-Emphasis
Independent Switch and Line Side Pre-Emphasis
Controls
Programmable Switch-Side Loopback Mode
On-Chip Terminations
3.3-V Supply
ESD Rating of 6-kV HBM
48-leadless WQFN Package (7 mm × 7 mm)
0°C to +85°C Operating Temperature Range
2 Applications
•
•
•
Backplane or Cable Driver
Redundancy and Signal Conditioning Applications
XAUI
All output drivers have four selectable steps of preemphasis to compensate for transmission losses from
long FR4 backplanes and reduce deterministic jitter.
The pre-emphasis levels can be independently
controlled for the line-side and switch-side drivers.
The internal loopback paths from switch-side input to
switch-side output enable at-speed system testing. All
receiver inputs are internally terminated with 100-Ω
differential terminating resistors. All drivers are
internally terminated with 50 Ω to VCC.
Device Information(1)
PART NUMBER
DS40MB200
PACKAGE
WQFN (48)
BODY SIZE (NOM)
7.00 mm × 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Block Diagram
LO_0 ±
EQ
SIA_0 ±
EQ
SIB_0 ±
PRE_L
MUX_S0
LB0A
Port 0
SOA_0 ±
PRE_S
LI_0 ±
SOB_0 ±
EQ
PRE_S
LO_1 ±
LB0B
EQ
SIA_1 ±
EQ
SIB_1 ±
PRE_L
MUX_S1
LB1A
Port 1
SOA_1 ±
PRE_S
LI_1 ±
SOB_1 ±
EQ
PRE_S
PreL_0
PreL_1
PreS_0
PreS_1
Pre-emphasis
Control
PRE_L
PRE_S
LB1B
VCC
GND
RSV
All CML inputs and outputs must be AC coupled for optimal performance.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS40MB200
SNLS144J – JUNE 2005 – REVISED JANUARY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
5
5
5
5
6
7
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Ratings............................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 9
Detailed Description ............................................ 10
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 11
9
Application and Implementation ........................ 13
9.1 Application Information............................................ 13
9.2 Typical Application .................................................. 13
10 Power Supply Recommendations ..................... 18
11 Layout................................................................... 18
11.1 Layout Guidelines ................................................. 18
11.2 Layout Examples................................................... 18
12 Device and Documentation Support ................. 20
12.1
12.2
12.3
12.4
12.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
20
20
20
20
20
13 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision I (March 2013) to Revision J
Page
•
Added Pin Configuration and Functions section, Storage Conditions table, ESD Ratings table, Thermal Information
table, Parameter Measurement Information section, Feature Description section, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Changed thermal information per latest modeling results ...................................................................................................... 5
•
Changed board trace attenuation estimate, per recent measurement ................................................................................ 15
2
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5 Pin Configuration and Functions
PreL1
1
42
41
MUX_S0
43
VCC
44
SIA_0+
VCC
45
SIA_0-
SOA_0-
46
GND
SOA_0+
47
SIB_0+
LB0A
48
SIB_0-
LB0B
NJU Package
48-Pin WQFN
Top View
40
39
38
37
36
PreS0
VCC
2
35
VCC
SOB_0-
3
34
LO_0-
SOB_0+
4
33
LO_0+
GND
5
32
GND
LI_0+
6
31
LI_1-
LI_0-
7
30
LI_1+
VCC
8
29
VCC
LO_1+
9
28
SOB_1+
LO_1-
10
27
SOB_1-
GND
11
26
RSV
PreL0
12
25
PreS1
DAP = GND
SIA_1+
GND
20
21
22
23
24
LB1B
SIA_1-
19
LB1A
VCC
18
SOA_1-
17
SOA_1+
16
VCC
15
SIB_1-
14
SIB_1+
13
MUX_S1
WQFN-48
Pin Functions
PIN
NAME
NO.
I/O (1)
DESCRIPTION (2)
LINE-SIDE HIGH-SPEED DIFFERENTIAL I/Os
LI_0+
LI_0−
6
7
I
Inverting and noninverting differential inputs of port_0 at the line side. LI_0+ and LI_0− have an
internal 50 Ω connected to an internal reference voltage. See Figure 7.
LI_1+
LI_1−
30
31
I
Inverting and noninverting differential inputs of port_1 at the line side. LI_1+ and LI_1− have an
internal 50 Ω connected to an internal reference voltage. See Figure 7.
LO_0+
LO_0−
33
34
O
Inverting and noninverting differential outputs of port_0 at the line side. LO_0+ and LO_0− have
an internal 50 Ω connected to VCC.
LO_1+
LO_1−
9
10
O
Inverting and noninverting differential outputs of port_1 at the line side. LO_1+ and LO_1− have
an internal 50 Ω connected to VCC.
SWITCH-SIDE HIGH SPEED-DIFFERENTIAL I/Os
SIA_0+
SIA_0−
40
39
I
Inverting and noninverting differential inputs to the mux_0 at the switch_A side. SIA_0+ and
SIA_0− have an internal 50 Ω connected to an internal reference voltage. See Figure 7.
SIA_1+
SIA_1−
16
15
I
Inverting and noninverting differential inputs to the mux_1 at the switch_A side. SIA_1+ and
SIA_1− have an internal 50 Ω connected to an internal reference voltage. See Figure 7.
SIB_0+
SIB_0−
43
42
I
Inverting and noninverting differential inputs to the mux_0 at the switch_B side. SIB_0+ and
SIB_0− have an internal 50 Ω connected to an internal reference voltage. See Figure 7.
SIB_1+
SIB_1−
19
18
I
Inverting and noninverting differential inputs to the mux_1 at the switch_B side. SIB_1+ and
SIB_1− have an internal 50 Ω connected to an internal reference voltage. See Figure 7.
SOA_0+
SOA_0−
46
45
O
Inverting and noninverting differential outputs of mux_0 at the switch_A side. SOA_0+ and
SOA_0− have an internal 50 Ω connected to VCC.
SOA_1+
SOA_1−
22
21
O
Inverting and noninverting differential outputs of mux_1 at the switch_A side. SOA_1+ and
SOA_1− have an internal 50 Ω connected to VCC.
(1)
(2)
I = Input, O = Output, P = Power
All CML Inputs or Outputs must be AC coupled.
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Pin Functions (continued)
PIN
NAME
NO.
I/O (1)
DESCRIPTION (2)
SOB_0+
SOB_0−
4
3
O
Inverting and noninverting differential outputs of mux_0 at the switch_B side. SOB_0+ and
SOB_0− have an internal 50 Ω connected to VCC.
SOB_1+
SOB_1−
28
27
O
Inverting and noninverting differential outputs of mux_1 at the switch_B side. SOB_1+ and
SOB_1− have an internal 50 Ω connected to VCC.
CONTROL (3.3-V LVCMOS)
LB0A
47
I
A logic low at LB0A enables the internal loopback path from SIA_0± to SOA_0±. LB0A is
internally pulled high.
LB0B
48
I
A logic low at LB0B enables the internal loopback path from SIB_0± to SOB_0±. LB0B is
internally pulled high.
LB1A
23
I
A logic low at LB1A enables the internal loopback path from SIA_1± to SOA_1±. LB1A is
internally pulled high.
LB1B
24
I
A logic low at LB1B enables the internal loopback path from SIB_1± to SOB_1±. LB1B is
internally pulled high.
MUX_S0
37
I
A logic low at MUX_S0 selects mux_0 to switch B. MUX_S0 is internally pulled high. Default
state for mux_0 is switch A.
MUX_S1
13
I
A logic low at MUX_S1 selects mux_1 to switch B. MUX_S1 is internally pulled high. Default
state for mux_1 is switch A.
PREL_0
PREL_1
12
1
I
PREL_0 and PREL_1 select the output pre-emphasis of the line side drivers (LO_0± and
LO_1±). PREL_0 and PREL_1 are internally pulled high. See Table 3 for line side pre-emphasis
levels.
PRES_0
PRES_1
36
25
I
PRES_0 and PRES_1 select the output pre-emphasis of the switch side drivers (SOA_0±,
SOB_0±, SOA_1± and SOB_1±). PRES_0 and PRES_1 are internally pulled high. See Table 4
for switch side pre-emphasis levels.
RSV
26
I
Reserve pin to support factory testing. This pin can be left open, or tied to GND, or tied to GND
through an external pull-down resistor.
GND
5, 11, 17, 32,
41
P
Ground reference. Each ground pin must be connected to the ground plane through a low
inductance path, typically with a via located as close as possible to the landing pad of the GND
pin.
GND
DAP
P
Die Attach Pad (DAP) is the metal contact at the bottom side, located at the center of the
WQFN-48 package. It must be connected to the GND plane with at least 4 via to lower the
ground impedance and improve the thermal performance of the package.
VCC
2, 8, 14, 20,
29, 35, 38,
44
P
VCC = 3.3 V ± 5%.
Each VCC pin must be connected to the VCC plane through a low inductance path, typically with
a via located as close as possible to the landing pad of the VCC pin.
TI recommends to have a 0.01 μF or 0.1 μF, X7R, size-0402 bypass capacitor from each VCC
pin to ground plane.
POWER
4
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6 Specifications
6.1 Absolute Maximum Ratings
see (1) (2)
MIN
MAX
UNIT
Supply voltage (VCC)
−0.3
4
V
CMOS/TTL input voltage
−0.3
VCC + 0.3
V
CML input/output voltage
−0.3
VCC + 0.3
V
125
°C
260
°C
150
°C
Junction temperature
Lead temperature (soldering, 4 sec)
−65
Storage temperature, Tstg
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, contact the TI Sales Office/Distributors for availability and specifications.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic
discharge
Human body model (HBM), 1.5 kΩ, 100 pF, per ANSI/ESDA/JEDEC JS-001 (1)
±6000
Machine model (MM), per JEDEC specification JESD22-A115-A
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Ratings
Supply voltage (VCC – GND)
Supply noise amplitude
MIN
NOM
MAX
3.135
3.3
3.465
(10 Hz to 2 GHz)
Ambient temperature
0
Case temperature
UNIT
V
20
mVPP
85
°C
100
°C
6.4 Thermal Information
DS40MB200
THERMAL METRIC (1)
NJU (WQFN)
UNIT
48 PINS
RθJA
Junction-to-ambient thermal resistance
32.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
15.2
°C/W
RθJB
Junction-to-board thermal resistance
9
°C/W
ψJT
Junction-to-top characterization parameter
0.2
°C/W
ψJB
Junction-to-board characterization parameter
9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.5
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
over recommended operating supply and temperature ranges (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
LVCMOS DC SPECIFICATIONS
VIH
High level input voltage
2
VCC + 0.3
VIL
Low level input voltage
−0.3
0.8
V
IIH
High level input current
VIN = VCC
−10
10
µA
IIL
Low level input current
VIN = GND
75
RPU
Pull-high resistance
94
124
35
V
µA
kΩ
RECEIVER SPECIFICATIONS
Differential input
voltage range
VID
AC-coupled differential signal.
This parameter is not production
tested.
Below 1.25 Gbps
100
1750
At 1.25 Gbps–3.125 Gbps
100
1560 mVP-P
Above 3.125 Gbps
100
1200
VICM
Common mode voltage
at receiver inputs
Measured at receiver inputs reference to ground.
RITD
Input differential
termination
On-chip differential termination between IN+ or IN−.
1.3
84
100
1000
1200
V
116
Ω
DRIVER SPECIFICATIONS
Output differential
VODB voltage swing without
pre-emphasis
RL = 100 Ω ±1%
PRES_1 = PRES_0 = 0
PREL_1 = PREL_0 = 0
Driver pre-emphasis disabled.
Running K28.7 pattern at 4 Gbps.
See Figure 6 for test circuit.
Output pre-emphasis
voltage ratio
20 × log (VODPE /
VODB)
RL = 100 Ω ±1%
Running K28.7 pattern at
4 Gbps (2)
x = S for switch side preemphasis control
x = L for line side pre-emphasis
control
See Figure 8 on waveform.
See Figure 6 for test circuit.
tPE
Pre-emphasis width (3)
Tested at −9-dB pre-emphasis level, PREx[1:0] = 11
x = S for switch side pre-emphasis control
x = L for line side pre-emphasis control
See Figure 3 on measurement condition.
ROTSE
Output termination
On-chip termination from OUT+ or OUT− to VCC (4)
ROTD
Output differential
termination
VPE
ΔROTS Mismatch in output
termination resistors
E
VOCM
PREx_[1:0] = 00
0
PREx_[1:0] = 01
−3
PREx_[1:0] = 10
−6
1400 mVP-P
dB
−9
PREx_[1:0] = 11
On-chip differential termination between OUT+ and OUT−
(4)
125
200
250
ps
42
50
58
Ω
Mismatch in output terminations at OUT+ and OUT− (4)
Output common mode
voltage
Ω
100
5%
2.7
V
POWER DISSIPATION
PD
(1)
(2)
(3)
(4)
6
Power dissipation
VDD = 3.465 V
All outputs terminated by 100 Ω ±1%.
PREL_[1:0] = 0, PRES_[1:0] = 0
Running PRBS 27–1 pattern at 4 Gbps
1
W
Typical parameters measured at VCC = 3.3 V, TA = 25°C. They are for reference purposes and are not production-tested.
K28.7 pattern is a 10-bit repeating pattern of K28.7 code group {001111 1000} K28.5 pattern is a 20-bit repeating pattern of +K28.5 and
–K28.5 code groups {110000 0101 001111 1010}
Specified by design and characterization using statistical analysis.
IN+ and IN− are generic names refer to one of the many pairs of complementary inputs of the DS40MB200. OUT+ and OUT− are
generic names refer to one of the many pairs of the complimentary outputs of the DS40MB200. Differential input voltage VID is defined
as |IN+–IN−|. Differential output voltage VOD is defined as |OUT+–OUT−|.
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Electrical Characteristics (continued)
over recommended operating supply and temperature ranges (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
AC CHARACTERISTICS
Device random
jitter (5) (6)
See Figure 6 for test circuit.
Alternating-1-0 pattern.
Pre-emphasis disabled.
At 1.25 Gbps
2
RJ
At 4 Gbps
2
DJ
Device deterministic
jitter (7) (6)
See Figure 6 for test circuit.
Pre-emphasis disabled.
At 4 Gbps,
PRBS7 pattern
DRMA
Maximum data rate (6)
Tested with alternating-1-0 pattern
30
4
psrms
psp-p
Gbps
X
(5)
(6)
(7)
Device output random jitter is a measurement of the random jitter contribution from the device. It is derived by the equation sqrt
(RJOUT2 – RJIN2), where RJOUT is the random jitter measured at the output of the device in psrms, RJIN is the random jitter of the pattern
generator driving the device.
Specified by design and characterization using statistical analysis.
Device output deterministic jitter is a measurement of the deterministic jitter contribution from the device. It is derived by the equation
(DJOUT – DJIN), where DJOUT is the peak-to-peak deterministic jitter measured at the output of the device in psp-p, DJIN is the peak-topeak deterministic jitter of the pattern generator driving the device.
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
tR
Differential low-to-high transition
time
tF
Differential high-to-low transition
time
tPLH
Differential low-to-high propagation
delay
tPHL
Differential high-to-low propagation
delay
tSKP
Pulse skew (2)
(3) (2)
TEST CONDITIONS
Measured with a clock-like pattern at 100 MHz,
between 20% and 80% of the differential output
voltage. Pre-emphasis disabled.
Transition time is measured with fixture as
shown in Figure 6, adjusted to reflect the
transition time at the output pins.
Measured at 50% differential voltage from input
to output.
TYP (1)
MAX
UNIT
80
ps
80
ps
0.5
2
ns
0.5
2
ns
|tPHL–tPLH|
20
ps
Difference in propagation delay among data
paths in the same device.
200
ps
500
ps
6
ns
tSKO
Output skew
tSKPP
Part-to-part skew (2)
Difference in propagation delay between the
same output from devices operating under
identical condition.
tSM
MUX switch time
Measured from VIH or VIL of the mux-control or
loopback control to 50% of the valid differential
output.
(1)
(2)
(3)
MIN
1.8
Typical parameters measured at VCC = 3.3 V, TA = 25°C. They are for reference purposes and are not production-tested.
Specified by design and characterization using statistical analysis.
tSKO is the magnitude difference in the propagation delays among data paths between switch A and switch B of the same port and
similar data paths between port 0 and port 1. An example is the output skew among data paths from SIA_0± to LO_0±, SIB_0± to
LO_0±, SIA_1± to LO_1± and SIB_1± to LO_1±. Another example is the output skew among data paths from LI_0± to SOA_0±, LI_0± to
SOB_0±, LI_1± to SOA_1± and LI_1± to SOB_1±. tSKO also refers to the delay skew of the loopback paths of the same port and
between similar data paths between port 0 and port 1. An example is the output skew among data paths SIA_0± to SOA_0±, SIB_0± to
SOB_0±, SIA_1± to SOA_1± and SIB_1± to SOB_1±.
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80%
80%
VODB
0V
20%
20%
tR
tF
Figure 1. Driver Output Transition Time
50% VID
IN
tPLH
tPHL
50% VOD
OUT
Figure 2. Propagation Delay From Input to Output
1-bit
1 to N bits
1-bit
1 to N bits
tPE
20%
-9 dB
80%
0V
VODPE3
Figure 3. Test Condition for Output Pre-Emphasis Duration
8
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100 mV/div
100 mV/div
6.7 Typical Characteristics
42 ps/div
50 ps/div
Figure 4. PRBS-7, Pre-Emphasis = 0 dB at 4 Gbps
Figure 5. PRBS-7, Pre-Emphasis = –9 dB at 4 Gbps
7 Parameter Measurement Information
DS40MB200 Test Fixture
Pattern
Generator
DC
Block
VCC
D+
INPUT
25-inch
TLine
D-
50: TL
DS40MB200
Coax
IN+
IN-
EQ
R
Oscilloscope or
Jitter Measurement
Instrument
Coax
M
U
X
50+-1%
OUT+
< 2"
D
OUT-
Coax
1000 mVpp
Differential
DC
Block
Coax
GND
50: TL
50 +-1%
Figure 6. AC Test Circuit
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8 Detailed Description
8.1 Overview
The DS40MB200 is a signal conditioning 2:1 multiplexer and 1:2 buffer designed to support port redundancy with
encoded or scrambled data rates between 1 and 4 Gbps. The DS40MB200 provides fixed equalization at the
receive input and pre-emphasis control on the output in order to support signal reach extension.
8.2 Functional Block Diagram
DS40MB200
VCC
1.5V
50
50
SIA_0+
50
50
LO_0+
LO_0-
Input stage
+EQ
M
U
X
CML
driver
SIA_0-
SIB_0+
Input stage
+EQ
SIB_0-
PRE_L
1.5V
MUX_S0
50
50
VCC
PORT 0
LB0A
PRE_S
LB0B
50
50
SOA_0+
2
M
U
X
LI_0+
2
Input stage
+EQ
LI_0-
CML
driver
SOA_0-
SOB_0+
2
50
50
1.5V
2
PreL_0
PreL_1
PreS_0
PreS_1
M
U
X
SOB_0-
50
PRE_S
PRE_L
Pre-emphasis
Control
CML
driver
50
VCC
PRE_S
VCC
1.5V
50
50
SIA_1+
50
50
LO_1+
LO_1-
Input stage
+EQ
M
U
X
CML
driver
SIA_1-
SIB_1+
Input stage
+EQ
SIB_1-
PRE_L
1.5V
MUX_S1
50
50
VCC
PORT 1
LB1A
PRE_S
LB1B
50
50
SOA_1+
2
LI_1+
2
Input stage
+EQ
LI_1-
M
U
X
CML
driver
M
U
X
CML
driver
SOA_1-
SOB_1+
2
50
50
1.5V
2
SOB_150
50
PRE_S
VCC pins
10
GND pins
& DAP
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8.3 Feature Description
The DS40MB200 MUX buffer consists of several key blocks:
• CML Inputs and EQ
• Multiplexer and Loopback Control
• CML Drivers and Pre-Emphasis Control
8.3.1 CML Inputs and EQ
The high-speed inputs are self-biased to about 1.3 V at IN+ and IN- and are designed for AC coupling. See
Figure 7 for details about the internal receiver input termination and bias circuit.
VCC
5k
IN +
50
1.5V
EQ
50
IN 3.9k
180 pF
Figure 7. Receiver Input Termination and Bias Circuit
The inputs are compatible to most AC coupling differential signals such as LVDS, LVPECL, and CML. The
DS40MB200 is not designed to operate with data rates below 1000 Mbps or with a DC bias applied to the CML
inputs or outputs. Most high-speed links are encoded for DC balance and have been defined to include AC
coupling capacitors, allowing the DS40MB200 to be inserted directly into the datapath without any limitation. The
ideal AC-coupling capacitor value is often based on the lowest frequency component embedded within the serial
link. A typical AC-coupling capacitor value ranges between 100 and 1000 nF. Some specifications with
scrambled data may require a larger capacitor for optimal performance. To reduce unwanted parasitic effects
around and within the AC-coupling capacitor, a body size of 0402 is recommended. Figure 6 shows the ACcoupling capacitor placement in an AC test circuit.
Each input stage has a fixed equalizer that provides equalization to compensate about 5 dB (at 2 GHz) of
transmission loss from a short backplane trace (about 10 inches backplane).
8.3.2 Multiplexer and Loopback Control
Table 1 and Table 2 provide details about how to configure the DS40MB200 multiplexer and loopback settings.
Table 1. Logic Table for Multiplex Controls
PIN
MUX_S0
MUX_S1
PIN VALUE
MUX FUNCTION
0
MUX_0 select switch_B input, SIB_0±.
1 (default)
MUX_0 select switch_A input, SIA_0±.
0
MUX_1 select switch_B input, SIB_1±.
1 (default)
MUX_1 select switch_A input, SIA_0±.
Table 2. Logic Table for Loopback Controls
PIN
LB0A
PIN VALUE
LOOPBACK FUNCTION
0
Enable loopback from SIA_0± to SOA_0±.
1 (default)
Normal mode. Loopback disabled.
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Table 2. Logic Table for Loopback Controls (continued)
PIN
PIN VALUE
LB0B
LB1A
LB1B
LOOPBACK FUNCTION
0
Enable loopback from SIB_0± to SOB_0±.
1 (default)
Normal mode. Loopback disabled.
0
Enable loopback from SIA_1± to SOA_1±.
1 (default)
Normal mode. Loopback disabled.
0
Enable loopback from SIB_1± to SOB_1±.
1 (default)
Normal mode. Loopback disabled.
8.3.3 CML Drivers and Pre-Emphasis Control
The output driver has pre-emphasis (driver-side equalization) to compensate the transmission loss of the
backplane that it is driving. The driver conditions the output signal such that the lower frequency and higher
frequency pulses reach approximately the same amplitude at the end of the backplane and minimize the
deterministic jitter caused by the amplitude disparity. The DS40MB200 provides four steps of user-selectable preemphasis ranging from 0, –3, –6 and –9 dB to handle different lengths of backplane. Figure 8 shows a driver preemphasis waveform. The pre-emphasis duration is 200 ps nominal, corresponding to 0.8 unit intervals (UI) at
4Gbps. The pre-emphasis levels of switch-side and line-side can be individually programmed.
1-bit
1 to N bits
1-bit
1 to N bits
0 dB
-3 dB
-6 dB
VODB
-9 dB
VODPE3
0V
VODPE2
VODPE1
Figure 8. Driver Pre-Emphasis Differential Waveform (Showing All 4 Pre-Emphasis Steps)
Table 3. Line-Side Pre-Emphasis Controls
PreL_[1:0]
PRE-EMPHASIS LEVEL IN mVPP
(VODB)
DE-EMPHASIS LEVEL IN mVPP
(VODPE)
PRE-EMPHASIS IN dB
(VODPE/VODB)
TYPICAL FR4
BOARD TRACE
00
1200
1200
0
10 inches
01
1200
850
−3
20 inches
10
1200
600
−6
30 inches
11
(default)
1200
426
−9
40 inches
Table 4. Switch-Side Pre-Emphasis Controls
PreS_[1:0]
PRE-EMPHASIS LEVEL IN
mVPP
(VODB)
DE-EMPHASIS LEVEL IN mVPP
(VODPE)
00
1200
01
1200
10
11
(default)
12
PRE-EMPHASIS IN dB
(VODPE/VODB)
TYPICAL FR4
BOARD TRACE
1200
0
10 inches
850
−3
20 inches
1200
600
−6
30 inches
1200
426
−9
40 inches
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The DS40MB200 is a 2:1 MUX and 1:2 buffer that equalizes input data up to 4 Gbps and provides transmit preemphasis controls to improve overall signal reach. As a MUX buffer, the DS40MB200 is ideal for designs where
there is a need for port sharing or redundancy as well as on-the-fly reorganization of routes and data
connections.
9.2 Typical Application
A typical application for the DS40MB200 is shown in Figure 9 and Figure 10.
Passive Backplane
Line Cards
DS40MB200
SerDes
HT
TD
ASIC
PHY
SOA
LI
SOB
T_ CLK
SIA
RD
R_CLK
HR
LO
SIB
REFCLK
Mux/Buf
Clock
Distribution
ASIC or FPGA with integrated SerDes
PC
Switch Card 2
Switch Card 1
SerDes
TD
Switch
ASIC
HT
T_ CLK
RD
R_CLK
HR
REFCLK
Clock
Distribution
ASIC or FPGA with integrated SerDes
Figure 9. System Diagram (Showing Data Paths of Port 0)
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Typical Application (continued)
DS40MB200
(Showing Port0)
1.5V
50
VCC
50
2x0.1 PF
0402-size
SIA_0+
50
To Upstream
receiver
50
LO_0+
Input stage
+EQ
M
U
X
CML
driver
From
downstream
transmitter
SIA_0-
SIB_0+
LO_0-
Input stage
+EQ
From
downstream
transmitter
SIB_0-
PRE_L
50
Control
1.5V
MUX_S0
VCC
LB0A
PRE_S
LB0B
50
2
LI_0+
From
Upstream
transmitter
2
Input stage
+EQ
LI_0-
2x0.1 PF
0402-size
2
50
50
1.5V
2
M
U
X
50
SOA_0+
CML
driver
SOA_0-
To
downstream
receiver
SOB_0+
M
U
X
CML
driver
SOB_0-
50
Control
2x0.1 PF
0402-size
50
To
downstream
receiver
50
PRE_S
PreL_0
PRE_L
PreL_1
Pre-emphasis
Control
PreS_0
VCC
PRE_S
PreS_1
GND pins
& DAP
VCC pins
RSV
3.3V
4x0.01 PF
X7R
0402-size
4x0.1 PF
X7R
0402-size
Figure 10. DS40MB200 Connection Block Diagram (Showing Data Paths of Port 0)
9.2.1 Design Requirements
In a typical design, the DS40MB200 equalizes a short backplane trace on its input, followed by a longer trace at
the DS40MB200 output. In this application example, a 25-inch FR4 coupled micro-strip board trace is used in
place of the short backplane link. A block diagram of this example is shown in Figure 11.
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Typical Application (continued)
(A)
(B)
Pattern
Generator, 4 Gb/s
(C)
(D)
DS40MB200
Pre-Emph
D+
D-
25-inch FR4
board trace
M
IN+
EQ
IN-
R
U
OUT+
D
X
40-inch
FR4 trace
OUT-
27 -1 pattern
Figure 11. Block Diagram of DS40MB200 Application Example
The 25-inch microstrip board trace has approximately 6 dB of attenuation between 375 MHz and 1.875 GHz,
representing closely the transmission loss of the short backplane transmission line. The 25-inch microstrip is
connected between the pattern generator and the differential inputs of the DS40MB200 for AC measurements.
Table 5. Input Trace Parameters
TRACE LENGTH
FINISHED TRACE
WIDTH W
SEPARATION
BETWEEN TRACES
DIELECTRIC
HEIGHT H
DIELECTRIC
CONSTANT εR
LOSS TANGENT
25 inches
8.5 mil
11.5 mil
6 mil
3.8
0.022
The length of the output trace may vary based on system requirements. In this example, a 40-inch FR4 trace
with similar trace width, separation, and dielectric characteristics is placed at the DS40MB200 output.
As with any high-speed design, there are many factors which influence the overall performance. Following is a
list of critical areas for consideration and study during design.
• Use 100-Ω impedance traces. Generally, these are very loosely coupled to ease routing length differences.
• Place AC-coupling capacitors near to the receiver end of each channel segment to minimize reflections.
• The maximum body size for AC-coupling capacitors is 0402.
• Back-drill connector vias and signal vias to minimize stub length.
• Use reference plane vias to ensure a low inductance path for the return current.
9.2.2 Detailed Design Procedure
For optimal design, the DS40MB200 must be configured to route incoming data correctly as well as to provide
the best signal quality. The following design procedures must be observed:
1. The DS40MB200 must be configured to provide the correct multiplexer and buffer routes in order to satisfy
system requirements. In order to set the appropriate multiplexer control settings, refer to Table 1. To
configure the buffer control settings, refer to Table 2. For example, consider the case where the designer
wishes to route the input from Switch Card A (SIA0_0±) to the output for the line card (LO_0±). To
accomplish this, set MUX_S0 = 1 (select SIA0_0±). For the other direction from line card output to switch
card, set LB0A = 1 and LB0B = 1 so that the input from the line-card is buffered to both Switch Card A
(SOA_0±) and Switch Card B (SOB_0±).
2. The DS40MB200 is designed to be placed at an offset location with respect to the overall channel
attenuation. To optimize performance, the multiplexer buffer transmit pre-emphasis can be tuned to extend
the trace length reach while also recovering a solid eye opening. To tune transmit pre-emphasis on either the
line card side or switch card side, refer to Table 3 and Table 4 for recommended pre-emphasis control
settings according to the length of FR4 board trace connected at the DS40MB200 output. For example, if 40
inches of FR4 trace is connected to the switch card output, set PreS_[1:0] = (1, 1) for VOD = 1200 mVpp and
–9 dB of transmit pre-emphasis.
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9.2.3 Application Curves
Figure 12 through Figure 17 show how the signal integrity varies at different places in the data path. These
measured locations can be referenced back to the labeled points provided in Figure 11.
• Point (A): Output signal of source pattern generator
• Point (B): Input to DS40MB200 after 25 inches of FR4 trace from source
• Point (C): Output of DS40MB200 driver
• Point (D): Signal after 40 inches of FR4 trace from DS40MB200 driver
200 mV/DIV
200 mV/DIV
The source signal is a PRBS-7 pattern at 4 Gbps. For the long output traces, the eye after 40 inches of output
FR4 trace is significantly improved by adding –9 dB of pre-emphasis.
50 ps/DIV
Figure 13. Eye Measured at Point (B)
200 mV/DIV
200 mV/DIV
50 ps/DIV
Figure 12. Eye Measured at Point (A)
50 ps/DIV
Figure 14. Eye Measured at Point (C), Pre-Emph = 0 dB
16
50 ps/DIV
Figure 15. Eye Measured at Point (D), Pre-Emph = 0 dB
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200 mV/DIV
200 mV/DIV
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50 ps/DIV
Figure 16. Eye Measured at Point (C), Pre-Emph = –9 dB
50 ps/DIV
Figure 17. Eye Measured at Point (D), Pre-Emph = –9 dB
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10 Power Supply Recommendations
The supply (VCC) and ground (GND) pins must be connected to power planes routed on adjacent layers of the
printed circuit board. The layer thickness of the dielectric must be minimized so that the VCC and GND planes
create a low inductance supply with distributed capacitance. Careful attention to supply bypassing through the
proper use of bypass capacitors is required. A 0.01-μF or 0.1-μF bypass capacitor must be connected to each
VCC pin such that the capacitor is placed as close to the VCC pins as possible. Smaller body-size capacitors, such
as 0402 body size, can help facilitate proper component placement. Refer to the VCC pin connections in
Figure 10 for further details.
11 Layout
11.1 Layout Guidelines
Use at least a four-layer board with a power and ground plane. Closely coupled differential lines of 100 Ω are
typically recommended for differential interconnect. The closely coupled lines help to ensure that coupled noise
will appear as common-mode and thus will be rejected by the receivers. Information on the WQFN style package
is provided in AN-1187 Leadless Leadframe Package (LLP) (SNOA401).
11.2 Layout Examples
Stencil parameters such as aperture area ratio and the fabrication process have a significant impact on paste
deposition. Inspection of the stencil prior to placement of the WQFN package is highly recommended to improve
board assembly yields. If the via and aperture openings are not carefully monitored, the solder may flow
unevenly through the DAP. Stencil parameters for aperture opening and via locations are shown in Figure 18. A
layout example for the DS40MB200 DAP is shown in Figure 19, where 16 stencil openings are used for the DAP
alongside nine vias to GND.
Figure 18. No Pullback WQFN, Single Row Reference Diagram
Table 6. No Pullback WQFN Stencil Aperture Summary for DS40MB200
DEVICE
PIN
COUNT
MKT DWG
PCB I/O
PAD SIZE
(mm)
PCB
PITCH
(mm)
PCB DAP
SIZE (mm)
STENCIL I/O
APERTURE
(mm)
STENCIL DAP
APERTURE
(mm)
NUMBER
OF DAP
APERTURE
OPENINGS
GAP BETWEEN
DAP APERTURE
(Dim A mm)
DS40MB200
48
SQA48A
0.25 × 0.6
0.5
5.1 × 5.1
0.25 × 0.7
1.1 × 1.1
16
0.2
18
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Figure 19. 48-Pin WQFN Stencil Example of Via and Opening Placement
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
AN-1187 Leadless Leadframe Package (LLP), SNOA401
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
20
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
DS40MB200SQ/NOPB
ACTIVE
WQFN
NJU
48
250
RoHS & Green
SN
Level-3-260C-168 HR
0 to 85
40MB200
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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