DS50PCI402SQ/NOPB

DS50PCI402 www.ti.com SNLS320H – APRIL 2010 – REVISED MARCH 2013 DS50PCI402 2.5 Gbps / 5.0 Gbps 4 Lane PCI Express Repeater with Equalization and De-Emphasis Check for Samples: DS50PCI402 FEATURES DESCRIPTION • The DS50PCI402 is a low power, 4 lane bidirectional buffer/equalizer designed specifically for PCI Express Gen1 and Gen2 applications. The device performs both receive equalization and transmit de-emphasis, allowing maximum flexibility of physical placement within a system. The receiver is capable of opening an input eye that is completely closed due to intersymbol interference (ISI) induced by the interconnect medium. 1 2 • • • • • • • • • • • • • • Input and Output signal conditioning increases PCIe reach in backplanes and cables 0.09 UI of residual deterministic jitter at 5Gbps after 42” of FR4 (with Input EQ) 0.11 UI of residual deterministic jitter at 5Gbps after 7m of PCIe Cable (with Input EQ) 0.09 UI of residual deterministic jitter at 5Gbps with 28” of FR4 (with Output DE) 0.13 UI of residual deterministic jitter at 5Gbps with 7m of PCIe Cable (with Output DE) Adjustable Transmit VOD 800 to 1200mVp-p Automatic and manual Receiver Detection and input termination control circuitry Automatic power management on an individual lane basis via SMBus Adjustable electrical idle detect threshold. Data rate optimized 3-stage equalization to 27 dB gain Data rate optimized 6-level 0 to 12 dB transmit de-emphasis Flow-thru pinout in 10mmx5.5mm 54-pin leadless WQFN package Single supply operation at 2.5V >6kV HBM ESD rating -10 to 85°C operating temperature range The transmitter de-emphasis level can be set by the user depending on the distance from the DS50PCI402 to the PCI Express endpoint. The DS50PCI402 contains PCI Express specific functions such as Transmit Idle, RX Detection, and Beacon signal pass through. The device provides automatic receive detection circuitry which controls the input termination impedance. By automatically reflecting the current load impedance seen on the outputs back to the corresponding inputs the DS50PCI402 becomes completely transparent to both the PCIe root complex and endpoint. An internal rate detection circuit is included to detect if an incoming data stream is at Gen2 data rates, and adjusts the de-emphasis on it's output accordingly. The signal conditioning provided by the device allows systems to upgrade from Gen1 data rates to Gen2 without reducing their physical reach. This is true for FR4 applications such as backplanes, as well as cable interconnect. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010–2013, Texas Instruments Incorporated DS50PCI402 SNLS320H – APRIL 2010 – REVISED MARCH 2013 www.ti.com Typical Application PCI402 Slice 1 of 4 PCI Express Interconnect Cable or Backplane PCI Express Root Complex or Bridge PCI402 Slice 1 of 4 PCI Express Endpoint Block Diagram - Detail View Of Channel (1 of 8) VOD/ DeEMPHASIS CONTROL VDD Auto / Manual RXDETECT Ix_n+ RATE DET EQ DEMA/B SMBus LIMITER Ix_n- EQA/B SMBus 2 OUTBUF Ox_n+ Ox_n- IDLE DET TX Idle Enable TXIDLEx SMBus Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: DS50PCI402 DS50PCI402 www.ti.com SNLS320H – APRIL 2010 – REVISED MARCH 2013 DEMA1/SCL DEMA0/SDA ENSMB EQB1/AD2 EQB0/AD3 49 48 47 46 VDD 50 PRSNT 51 DEMB0/AD1 53 52 DEMB1/AD0 54 Pin Diagram SMBUS AND CONTROL OB_0+ 1 45 IB_0+ OB_0- 2 44 IB_0- OB_1+ 3 43 IB_1+ OB_1- 4 42 IB_1- OB_2+ 5 41 VDD OB_2- 6 40 IB_2+ OB_3+ 7 39 IB_2- OB_3- 8 38 IB_3+ 37 IB_3- DAP = GND VDD 9 IA_0+ 10 36 VDD IA_0- 11 35 OA_0+ IA_1+ 12 34 OA_0- IA_1- 13 33 OA_1+ VDD 14 32 OA_1- IA_2+ 15 31 OA_2+ IA_2- 16 30 OA_2- 21 22 23 24 25 26 27 RATE RXDETA RXDETB TXIDLEA TXIDLEB ENRXDET SD_TH OA_3- 20 OA_3+ 28 19 29 18 EQA1 17 IA_3- EQA0 IA_3+ The center DAP on the package bottom is the device GND connection. This pad must be connected to GND through multiple (minimum of 8) vias to ensure optimal electrical and thermal performance. DS50PCI402 Pin Diagram 54 lead Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: DS50PCI402 3 DS50PCI402 SNLS320H – APRIL 2010 – REVISED MARCH 2013 www.ti.com Table 1. Pin Descriptions Pin Name Pin Number I/O, Type (1) (2) (3) (4) Pin Description Differential High Speed I/O's IA_0+, IA_0- , IA_1+, IA_1-, IA_2+, IA_2-, IA_3+, IA_3- 10, 12, 15, 17, 11 13 16 18 I, CML Inverting and non-inverting CML differential inputs to the equalizer. A gated on-chip 50Ω termination resistor connects INA_0+ to VDD and INA_0- to VDD when enabled. OA_0+, OA_0-, OA_1+, OA_1-, OA_2+, OA_2-, OA_3+, OA_3- 35, 33, 31, 29, 34 32 30 28 O,LPDS Inverting and non-inverting low power differential signal (LPDS) 50Ω driver outputs with de-emphasis. Compatible with AC coupled CML inputs. IB_0+, IB_0- , IB_1+, IB_1-, IB_2+, IB_2-, IB_3+, IB_3- 45, 43, 40, 38, 44 42 39 37 I, CML Inverting and non-inverting CML differential inputs to the equalizer. A gated on-chip 50Ω termination resistor connects INB_0+ to VDD and INB_0- to VDD when enabled. OB_0+, OB_0-, OB_1+, OB_1-, OB_2+, OB_2-, OB_3+, OB_3- 1, 2 3, 4 5, 6 7, 8 O,LPDS Inverting and non-inverting low power differential signal (LPDS) 50Ω driver outputs with de-emphasis. Compatible with AC coupled CML inputs. I, LVCMOS w/internal pulldown System Management Bus (SMBus) enable pin. When pulled high provide access internal digital registers that are a means of auxiliary control for such functions as equalization, deemphasis, VOD, rate, and idle detection threshold. When pulled low, access to the SMBus registers are disabled and SMBus function pins are used to control the Equalizer and De-Emphasis. Please refer to SYSTEM MANAGEMENT BUS (SMBUS) AND CONFIGURATION REGISTERS and Electrical Characteristics — Serial Management Bus Interface for detail information. Control Pins — Shared (LVCMOS) ENSMB 48 ENSMB = 1 (SMBUS MODE) SCL 50 I, LVCMOS ENSMB = 1 SMBUS clock input pin is enabled. External pull-up resistor maybe needed. Refer to RTERM in the SMBus specification. SDA 49 I, LVCMOS, O, Open Drain ENSMB = 1 The SMBus bi-directional SDA pin is enabled. Data input or open drain output. External pull-up resistor is required. Refer to RTERM in the SMBus specification. AD0-AD3 54, 53, 47, 46 I, LVCMOS w/internal pulldown ENSMB = 1 SMBus Slave Address Inputs. In SMBus mode, these pins are the user set SMBus slave address inputs. See section — SYSTEM MANAGEMENT BUS (SMBUS) AND CONFIGURATION REGISTERS for additional information. ENSMB = 0 (NORMAL PIN MODE) EQA0, EQA1 EQB0, EQB1 20, 19 46, 47 I,FLOAT, LVCMOS EQA/B ,0/1 controls the level of equalization of the A/B sides as shown in Table 2. The EQA/B pins are active only when ENSMB is de-asserted (Low). Each of the 4 A/B channels have the same level unless controlled by the SMBus control registers. When ENSMB goes high the SMBus registers provide independent control of each lane, and the EQB0/B1 pins are converted to SMBUS AD2/AD3 inputs. DEMA0, DEMA1 DEMB0, DEMB1 49, 50 53, 54 I,FLOAT, LVCMOS DEMA/B ,0/1 controls the level of de-emphasis of the A/B sides as shown in Table 5. The DEMA/B pins are only active when ENSMB is deasserted (Low). Each of the 4 A/B channels have the same level unless controlled by the SMBus control registers. When ENSMB goes High the SMBus registers provide independent control of each lane and the DEM pins are converted to SMBUS AD0/AD1 and SCL/SDA inputs. (1) (2) (3) (4) 4 FLOAT = 3rd input state, don't drive pin. Pin is internally biased to mid level with 50 kΩ pull-up/pull-down. If high Z output not available, drive input to VDD/2 to assert mid level state. Internal pulldown = Internal 30 kΩ pull-down resistor to GND is present on the input. LVCMOS inputs without the “Float” conditions must be driven to a logic Low or High at all times or operation is not ensured. Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%. Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: DS50PCI402 DS50PCI402 www.ti.com SNLS320H – APRIL 2010 – REVISED MARCH 2013 Table 1. Pin Descriptions (continued) Pin Name Pin Number I/O, Type (1) (2) (3) (4) Pin Description RATE 21 I,FLOAT, LVCMOS RATE control pin controls the pulse width of de-emphasis of the output. A Low forces Gen1 (2.5Gbps), High forces Gen 2 (5Gbps), Open/Floating the rate is internally detected after each exit from idle and the pulse width is set appropriately. When ENSMBUS= 1 this pin is disabled and the RATE function is controlled internally by the SMBUS registers. Refer to Table 5. Control Pins — Both Modes (LVCMOS) RXDETA,RXDETB 22,23 I, LVCMOS w/internal pulldown The RXDET pins in combination with the ENRXDET pin controls the receiver detect function. Depending on the input level, a 50Ω or >50KΩ termination to the power rail is enabled. Refer to Table 7. PRSNT 52 I, LVCMOS Cable Present Detect input. High when a cable is not present per PCIe Cabling Spec. 1.0. Puts part into low power mode. When low (normal operation) part is enabled. ENRXDET 26 I, LVCMOS w/internal pulldown Enables pin control of receiver detect function. The default is automatic RXDET using the internal pulldown. Pin must be pulled high for manual RXDETA/B operation. Controls individual A and B sides. Refer to Table 7. TXIDLEA,TXIDLEB 24,25 I, FLOAT, LVCMOS Controls the electrical idle function on corresponding outputs when enabled. H= electrical Idle, Float=autodetect (Idle on input passed to output), L=Idle squelch disabled as shown in Table 6. 27 I, ANALOG Threshold select pin for electrical idle detect threshold. Float pin for default 130mV DIFF p-p, otherwise connect resistor from SD_TH to GND to set threshold voltage as shown in Table 7. VDD 9, 14,36, 41, 51 Power Power supply pins CML/analog. GND DAP Power Ground pad (DAP - die attach pad). Analog SD_TH Power Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: DS50PCI402 5 DS50PCI402 SNLS320H – APRIL 2010 – REVISED MARCH 2013 www.ti.com FUNCTIONAL DESCRIPTION The DS50PCI402 is a low power media compensation 4 lane repeater optimized for PCI Express Gen 1 and Gen 2 media including lossy FR-4 printed circuit board backplanes and balanced cables. The DS50PCI402 operates in two modes: Pin Control Mode (ENSMB = 0) and SMBus Mode (ENSMB = 1). Pin Control Mode: When in pin mode (ENSMB = 0) , the repeater is configurable with external pins. Equalization and de-emphasis can be selected via pin for each side independently. When de-emphasis is asserted VOD is automatically increased per the De-Emphasis table below for improved performance over lossy media. The receiver detect pins RXDETA/B provide manual control for input termination (50Ω or >50KΩ). Rate optimization is also pin controllable, with pin selections for 2.5Gbps, 5Gbps, and auto detect. The receiver electrical idle detect threshold is also programmable via an optional external resistor on the SD_TH pin. SMBUS Mode: When in SMBus mode the equalization, de-emphasis, and termination disable features are all programmable on a individual lane basis, instead of grouped by sides as in the pin mode case. Upon assertion of ENSMB the RATE, EQx and DEMx functions revert to register control immediately. The EQx and DEMx pins are converted to AD0-AD3 SMBus address inputs. The other external control pins remain active unless their respective registers are written to and the appropriate override bit is set, in which case they are ignored until ENSMB is driven low. On powerup and when ENSMB is driven low all registers are reset to their default state. If PRSNT is asserted while ENSMB is high, the registers retain their current state. Equalization settings accessible via the pin controls were chosen to meet the needs of most PCIe applications. If additional fine tuning or adjustment is needed, additional equalization settings can be accessed via the SMBus registers. Each input has a total of 24 possible equalization settings. The tables show a typical gain for each gain stage (GST[1:0]) and boost level (BST[2:0]) combination. When using SMBus mode, the Equalization and DeEmphasis levels are set using registers. Table 2. Equalization Settings with GST=1 for Pins or SMBus Registers EQ1 ( EQ0 ( EQ Setting EQ Gain (dB) 2.5 GHz Suggested Use 0 0 Bypass - Default Setting 1.6 3.2 1) 1) GST[1 :0] BST[2: 0] F F 00 000 01 000 01 001 2.1 4.2 01 010 2.6 5.0 01 011 3.2 5.9 01 100 4.0 7.3 01 101 4.9 7.9 01 110 5.4 8.5 01 111 5.6 9.0 1 (1) 1 1.25 GHz 8" FR4 (6-mil trace) or < 1m (28 AWG) PCIe cable F=Float (don't drive pin, each float pin has an internal 50K Ohm resistor to VDD and GND), 1=High, 0=Low Table 3. Equalization Settings with GST=2 for Pins or SMBus Registers EQ1 ( EQ0 ( GST[1 :0] BST[2: 0] 1.25 GHz 2.5 GHz Suggested Use 0 0 10 000 3.8 7.6 14" FR4 (6-mil trace) or 1m (28 AWG) PCIe cable 10 001 5.1 9.9 10 010 6.4 11.6 10 011 7.6 13.5 10 100 9.5 16.1 10 101 11.3 17.5 F 6 EQ Gain (dB) 1) F (1) EQ Setting 1) 0 1 20" FR4 (6-mil trace) or 5m (26 AWG) PCIe cable 40" FR4 (6-mil trace) or 9m (24 AWG) PCIe cable F=Float (don't drive pin, each float pin has an internal 50K Ohm resistor to VDD and GND), 1=High, 0=Low Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: DS50PCI402 DS50PCI402 www.ti.com SNLS320H – APRIL 2010 – REVISED MARCH 2013 Table 3. Equalization Settings with GST=2 for Pins or SMBus Registers (continued) EQ1 ( EQ0 ( 1) 1) 0 1 EQ Setting EQ Gain (dB) GST[1 :0] BST[2: 0] 1.25 GHz 2.5 GHz 10 110 12.3 18.6 10 111 12.8 19.8 Suggested Use 50" FR4 (6-mil trace) or 10m (24 AWG) PCIe cable Table 4. Equalization Settings with GST=3 for Pins or SMBus Registers EQ1 ( EQ0 ( 1) 1) 1 (1) 0 0 F 1 F EQ Setting EQ Gain (dB) GST[1 :0] BST[2: 0] 1.25 GHz 2.5 GHz 11 000 6.4 12.2 11 001 8.5 15.6 11 010 10.4 18.3 11 011 12.4 21.3 11 100 15.2 25.0 11 101 18.1 27.2 11 110 19.6 28.8 11 111 20.2 30.7 Suggested Use 30" FR4 (6-mil trace) or 7m (24 AWG) PCIe cable 15m (24 AWG) PCIe cable > 15m (24 AWG) PCIe cable F=Float (don't drive pin, each float pin has an internal 50K Ohm resistor to VDD and GND), 1=High, 0=Low The De-Emphasis level must be set when in SMBus mode. See SMBus TRANSACTIONS section and Table 10 for specific De-Emphasis values. Table 5. De-Emphasis Input Select Pins for A and B ports (3–Level Input) RATE (1) DEM1 DEM0 (1 Typical DE Pulse Width Typical VOD 0dB 0ps 1000mV -3.5dB 400ps 1000mV -6dB 400ps 1000mV -6dB 400ps enhanced 1000mV F -9dB 400ps enhanced 1000mV 1 F -12dB 400ps enhanced 1000mV 0/F F 0 -9dB 400ps enhanced 1200mV 30 inches FR4 (6-mil trace) 0/F F 1 -12dB 400ps enhanced 1400mV 40 inches FR4 (6-mil trace) 0/F F F Reserved, don't use 1/F 0 0 0dB 0ps 1000mV 1/F 0 1 -3.5dB 200ps 1000mV 1/F 1 0 -6dB 200ps 1000mV 1/F 1 1 -6dB 200ps enhanced 1000mV 1/F 0 F -9dB 200ps enhanced 1000mV 1/F 1 F -12dB 200ps enhanced 1000mV 1/F F 0 -9dB 200ps enhanced 1200mV 20 inches FR4 (6-mil trace) 1/F F 1 -12dB 200ps enhanced 1400mV 30 inches FR4 (6-mil trace) 1/F F F Reserved, don't use (1) ) 0/F 0 0 0/F 0 1 0/F 1 0 0/F 1 1 0/F 0 0/F Typical DeEmphasis Level Suggested Use 8 inches FR4 (6-mil trace) or less than 1 meter (28 AWG) PCIe cable 15 inches FR4 (6-mil trace) 10 inches FR4 (6-mil trace) F=Float (don't drive pin - (each float pin has an internal 50K Ohm resistor to VDD and GND). Enhanced DE Pulse width provides additional de-emphasis on second bit. VOD = Voltage Output Differential amplitude. When RATE is floated (F=Auto Rate Detection Active) DE Level and Pulse Width settings follow detected RATE. RATE=0 is 2.5GBps, RATE=1 is 5 GBps Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: DS50PCI402 7 DS50PCI402 SNLS320H – APRIL 2010 – REVISED MARCH 2013 www.ti.com Table 6. Idle Control (3–Level Input) TXIDLEA/B Function 0 This state is for lossy media, dedicated Idle threshold detect circuit disabled, output follows input based on EQ settings. Idle state not ensured. Float Float enables automatic idle detection. Idle on the input is passed to the output. This is the recommended default state. Output driven to Idle if diff input signal less than value set by SD_TH pin. 1 Manual override, output forced to Idle. Diff inputs are ignored. Table 7. Receiver Electrical Idle Detect Threshold Adjust (Analog input - Connect Resistor to GND or Float) Typical Receiver Electrical Idle Detect Threshold (DIFF p-p) Float (no resistor required) 130mV (default condition) 0 225mV 80K 20mV SD_TH resistor value can be set from 0 through 80K Ohms to achieve desired idle detect threshold, see Figure 1. 8K Ohm is approx 130mV. ELECTRICAL IDLE DETECT THRESHOLD (DIFF mVp-p) (1) SD_TH resistor value (Ω) (connect from pin to GND) (1) 250 VDD = 2.5V TA = 25°C 200 150 100 50 0 0 10k 20k 30k 40k 50k 60k 70k 80k SD_TH RESISTOR VALUE (:) Figure 1. Typical Idle threshold vs SD_TH resistor value Receiver Detection The Rx detection process is a feature that can set the number of active channels on the DS50PCI402. By sensing the presence of a valid PCIe load on the output, the channel can be automatically enabled for operation. This allows the DS50PCI402 to configure inself to the proper lane width, whether it is a 4-lane, 2-lane, or 1-lane PCIe link. Automatic Rx Detection is enabled by a combination of PRSNT# and ENRXDET inputs. When these inputs are set low, Automatic Rx Detection is enabled, cycling of the PRSNT# pin will reset the Rx detection circuitry, initiating a new receiver detection sequence. Pulling the ENRXDET input to logic 1, allows for manual control of the input termination. The table below summarizes control pin and receiver detect operation for the DS50PCI402. 8 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: DS50PCI402 DS50PCI402 www.ti.com SNLS320H – APRIL 2010 – REVISED MARCH 2013 Table 8. Receiver Detect Pins for A and B ports (LVCMOS inputs) PRSNT# ENRXDET RXDETA/B Input Termination Termination sensed on Output 0 0 0 >50KΩ to VDD Hi - Z 50Ω PCIe Input 0 0 1 >50KΩ to VDD Hi - Z 50Ω PCIe Input Function Automatic RXDET: Rx detection state machine enabled. Outputs will test for the presence of a receiver input every 12 msec until detection occurs. Input termination remains >50KΩ to VDD until receiver is detected. Once receiver is detected, input impedance to VDD is 50Ω. Automatic RXDET: Rx detection state machine enabled. Outputs will test for the presence of a receiver input every 12 msec for 600 msec and then stop. Input termination remains >50KΩ to VDD until receiver is detected. Once receiver is detected, input impedance to VDD is 50Ω. Restart detection if RXDETA/B is pulsed lowhigh. 0 1 0 >50KΩ to VDD X Manual RXDET: Rx detection state machine disabled. Input termination >50KΩ. Associated output channels in low power idle mode. 0 1 1 50Ω X Manual RXDET: Rx detection state machine disabled. Input termination 50Ω. Associated output channels set to active. 1 X X >50KΩ to VDD X Power down mode: Input termination >50KΩ. Associated output channels off. Part in power saving mode. PRSNT# should be held high for a minimum of 5 us to ensure complete analog power down. The Automatic RXDET functionality will be re-initialized on the falling edge of PRSNT#. RX Detect: Range of Operation The Rx detection process used in the DS50PCI402 is designed to be fully compliant with the PCIe 2.0 base specification. The receiver detection circuitry will accurately detect a receiver when both conditions listed below are true: • DS50PCI402 within Recommended Operating Range for Temperature and Supply Voltage • For receiver ZRX-DC = 40 (min) to 60 (max) Ohms Note: To ensure robust system operation, the DS50PCI402 will only signal a valid receiver detection if both halves of the differential output pair detect a proper 40 - 60 Ohm receiver impedance. If the receiver detection circuitry senses a load impedance greater than ZRX-DC on either trace of a differential pair, it will be interpreted as no termination load present (i.e. the corresponding DS50PCI402 input termination will remain High-Z). Manual Control Of RXDETA/B In A PCIe Environment In some cases manual control of RXDETA/B may be desirable. In order for upstream and downstream PCIe subsystems to communicate in a cabling environment, the PCIe specification includes several auxiliary or sideband signals to manage system-level functionality or implementation. Similar methods are used in backplane applications, but the exact implementation falls outside the PCIe standard. Initial communication from the downstream subsystem to the upstream subsystem is done with the CPRSNT# auxiliary signal. The CPRSNT# signal is asserted Low by the downstream componentry after the "Power Good" condition has been established. This mechanism allows for the upstream subsystem to determine whether the power is good within the downstream subsystem, enable the reference clock, and initiate the Link Training Sequence. Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: DS50PCI402 9 DS50PCI402 SNLS320H – APRIL 2010 – REVISED MARCH 2013 www.ti.com CPWRON 0V CPRSNT# to RESET Removal 5 ms (min) CPERST# 0V DS50PCI402 PRSNT# Min pulse width HIGH 5 Ps (min) RESET Removed and REFCLK Stable CPRSNT# 0V CREFCLK Figure 2. Typical PCIe System Timing The signals shown in the graphic could be easily replicated within the downstream subsystem and used to externally control the common mode input termination impedance on the DS50PCI402. Often an onboard microcontroller will be used to handle events like power-up, power-down, power saving modes, and hot insertion. The microcontroller would use the same information to determine when to enable and disable the DS50PCI402 input termination. In applications that require SMBus control, the microcontroller could also delay any response to the upstream subsystem to allow sufficient time to correctly program the DS50PCI402 and other devices on the board. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 10 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: DS50PCI402 DS50PCI402 www.ti.com SNLS320H – APRIL 2010 – REVISED MARCH 2013 Absolute Maximum Ratings (1) (2) Supply Voltage (VDD) -0.5V to +3.0V LVCMOS Input/Output Voltage -0.5V to +4.0V CML Input Voltage -0.5V to (VDD+0.5V) CML Input Current -30 to +30 mA LPDS Output Voltage -0.5V to (VDD+0.5V) Analog (SD_TH) (3) -0.5V to (VDD+0.5V) Junction Temperature +125°C Storage Temperature -40°C to +125°C Lead Temperature Range Maximum Package Power Dissipation at 25°C NJY Package 4.21 W Derate NJY Package 52.6mW/°C above +25°C ESD Rating ≥6 kV HBM, STD - JESD22-A114C ≥250 V MM, STD - JESD22-A115-A ≥1250 V CDM, STD - JESD22-C101-C Thermal Resistance θJC 11.5°C/W θJA, No Airflow, 4 layer JEDEC 19.1°C/W For soldering specifications: see product folder at www.ti.com http://www.ti.com/lit/SNOA549 (1) (2) (3) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Absolute Maximum Numbers are specified for a junction temperature range of -40°C to +125°C. Models are validated to Maximum Operating Voltages only. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office / Distributors for availability and specifications. Measured at default SD_TH settings Recommended Operating Conditions Min Typ Max Units 2.375 2.5 2.625 V -10 25 +85 °C Supply Voltage VDD to GND Ambient Temperature SMBus (SDA, SCL) Supply Noise Tolerance up to 50Mhz (1) (1) 3.6 V 100 mV pp Allowed supply noise (mVP-P sine wave) under typical conditions. Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: DS50PCI402 11 DS50PCI402 SNLS320H – APRIL 2010 – REVISED MARCH 2013 www.ti.com Electrical Characteristics Over recommended operating supply and temperature ranges with default register settings unless other specified. (1) (2) Symbol POWER Parameter Conditions Min Typ Max Units 800 1000 mW 4 8 mW (3) PD Power Dissipation EQX=Float, DEX=0, VOD=1Vpp ,PRSNT=0 PRSNT=1, ENSMB=0 LVCMOS / LVTTL DC SPECIFICATIONS High Level Input Voltage (4) VIL Low Level Input Voltage (4) VOH High Level Output Voltage SMBUS open drain VOH set by pullup Resistor VOL Low Level Output Voltage IOL = 4mA IIH Input High Current VIN = 3.6V , LVCMOS -15 +15 VIN = 3.6V , w/ FLOAT,PULLDOWN input -15 +120 VIN = 0V -15 +15 VIN = 0V, w/FLOAT input -80 +15 VIH IIL Input Low Current 2 3.6 0 0.8 V V V 0.4 V μA μA CML RECEIVER INPUTS (IN_n+, IN_n-) RLRX-DIFF (5) Rx package plus Si differential return loss 0.05GHz – 1.25GHz 1.25GHz – 2.5GHz (5) RLRX-CM Common mode Rx return loss 0.05GHz - 2.5GHz (5) ZRX-DC Rx DC common mode impedance Tested at VDD=0 ZRX-DIFF-DC Rx DC differential impedance Tested at VDD=0 VRX-DIFF-DC Differential Rx peak to peak voltage Tested at DC, TXIDLEx=0 ZRX-HIGH-IMP-DC -POS DC Input CM impedance for V>0 Vin = 0 to 200 mV, RXDETA/B = 0, ENSMB = 0, VDD=2.625 Electrical Idle detect threshold SD_TH = float, see Table 5, VRX-IDLE-DET-DIFF-PP (6) -21 dB -20 -11.5 dB 40 50 60 Ω 85 100 115 Ω 1.2 V 0.10 50 KΩ 40 175 mVP-P 1200 mVP-P LPDS OUTPUTS (OUT_n+, OUT_n-) VTX-DIFF-PP VOCM (1) (2) (3) (4) (5) (6) 12 Output Voltage Swing Output Common-Mode Voltage Differential measurement with OUT_n+ and OUT_n- terminated by 50Ω to GND AC-Coupled, Figure 4, (3) Single-ended measurement DCCoupled with 50Ω termination, (1) 800 1000 VDD - 1.4 V Typical values represent most likely parametric norms at VDD = 2.5V, TA = 25°C., and at the Recommended Operation Conditions at the time of product characterization and are not ensured. The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. Measured with DEM Select pins configured for 1000mV VOD, see De-emphasis table. Input edge rate for LVCMOS/FLOAT inputs must be 50ns minimum from 10-90%. Input Return Loss also uses the setup shown in Figure 6. The blocking / biasing circuit is replaced with a simple AC coupling capacitor for each input to emulate a typical PCIe application. Measured at package pins of receiver. Less than 40mV is IDLE, greater than 175mV is ACTIVE. SD_TH pin connected with resistor to GND overrides this default setting. Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: DS50PCI402 DS50PCI402 www.ti.com SNLS320H – APRIL 2010 – REVISED MARCH 2013 Electrical Characteristics (continued) Over recommended operating supply and temperature ranges with default register settings unless other specified. (1) (2) Symbol VTX-DE-RATIO-3.5 VTX-DE-RATIO-6 Parameter Conditions Min Typ Max Units Tx de-emphasis level ratio VOD = 1000 mV, DEM1 = GND, DEM0 = VDD, (1), 3.5 dB Tx de-emphasis level ratio VOD = 1000 mV, DEM1 = VDD, DEM0 = GND, (1), 6 dB (7) (7) TTX-HF-DJ-DD Tx Dj > 1.5 Mhz (8) 0.15 UI TTX-LF-RMS Tx RMS jitter < 1.5Mhz (8) 3.0 ps RMS TTX-RISE-FALL Transmitter Rise/ Fall Time 20% to 80% of differential output voltage, Figure 3 TRF-MISMATCH Tx rise/fall mismatch 20% to 80% of differential output voltage (1) (9) 0.01 RLTX-DIFF Differential Output Return Loss 0.05- 1.25 Ghz, See Figure 6 -23 dB 1.25- 2.5 Ghz, See Figure 6 -20 dB RLTX-CM Common Mode Return Loss 0.05- 2.5 Ghz, See Figure 6 -11 dB ZTX-DIFF-DC DC differential Tx impedance 100 Ω VTX-CM-AC-PP Tx AC common mode voltage ITX-SHORT transmitter short circuit current limit VTX-CM-DC- ACTIVE-IDLEDELTA VTX-CM-DC- LINE-DELTA TTX-IDLE-SET-TO -IDLE TTX-IDLE-TO -DIFF-DATA TPDEQ (1) (9) ps 0.1 UI mVpp 90 mA Absolute Delta of DC Common Mode Voltage during L0 and electrical Idle 40 mV Absolute Delta of DC Common Mode Voltage between Tx+ and Tx- 25 mV 6.5 9.5 nS 5.5 8 nS Total current transmitter can supply when shorted to VDD or GND Max time to transition to valid diff signaling after leaving Electrical Idle VIN = 800 mVp-p, 5 Gbps, Figure 5 Max time to transition to valid diff signaling after leaving Electrical Idle VIN = 800 mVp-p, 5 Gbps, Figure 5 Differential Propagation EQ = 11, Delay +4.0 dB @ 2.5 GHz , Figure 4 150 200 250 ps Differential Propagation EQ = FF, Delay Equalizer Bypass, Figure 4 120 170 220 ps 27 ps (10) (11) TLSK 67 100 (10) TPD 50 Lane to Lane Skew in a TA = 25C,VDD = 2.5V (12) (11) Single Part (7) (8) Measured with a repeating K28.5 pattern at a data rate of 2.5 Gbps and 5.0 Gbps. PCIe 2.0 transmit jitter specifications - actual device jitter is much less. Actual device Rj and Dj has been characterized and specified with test loads outlined in the EQUALIZATION and DE-EMPHASIS sections of the Electrical Characteristics table. (9) Specified by device characterization (10) Propagation Delay measurements will change slightly based on the level of EQ selected. EQ Bypass will result in the shortest propagation delays. (11) Propagation Delay measurements for Part to Part skew are all based on devices operating under indentical temperature and supply voltage conditions. (12) Specified by device characterization Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: DS50PCI402 13 DS50PCI402 SNLS320H – APRIL 2010 – REVISED MARCH 2013 www.ti.com Electrical Characteristics (continued) Over recommended operating supply and temperature ranges with default register settings unless other specified. (1) (2) Symbol TPPSK Parameter Conditions Min Max Units 35 ps 0.02 0.09 UIP-P 42” of 5 mil stripline FR4, EQ1,0=F,1; K28.5 pattern, DEMx=0, Tx Launch Amplitude 1.0 Vp-p, SD_TH=F. (13) (14) 0.02 0.04 UIP-P Residual Deterministic Jitter at 5 Gbps 7 meters of 24 AWG PCIe cable, EQ1,0=1,0; K28.5 pattern, DEMx=0, Tx Launch Amplitude 1.0 Vp-p, SD_TH=F. (13) (14) 0.02 0.11 UIP-P Residual Deterministic Jitter at 2.5 Gbps 7 meters of 24 AWG PCIe cable, EQ1,0=1,0; K28.5 pattern, DEMx=0, Tx Launch Amplitude 1.0 Vp-p, SD_TH=F. (13) (14) 0.03 0.07 UIP-P Random Jitter Tx Launch Amplitude 1.0 Vp-p, SD_TH=F, Repeating 1100b (D24.3) pattern. (13)