DS64EV400
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SNLS281H – AUGUST 2007 – REVISED APRIL 2013
DS64EV400 Programmable Quad Equalizer
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FEATURES
DESCRIPTION
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The DS64EV400 programmable quad equalizer
provides compensation for transmission medium
losses and reduces the medium-induced deterministic
jitter for four NRZ data channels. The DS64EV400 is
optimized for operation up to 10 Gbps for both cables
and FR4 traces. Each equalizer channel has eight
levels of input equalization that can be programmed
by three control pins, or individually through a Serial
Management Bus (SMBus) interface.
1
2
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Equalizes up to 24 dB Loss at 10 Gbps
Equalizes up to 22 dB Loss at 6.4 Gbps
8 Levels of Programmable Equalization
Settable through Control Pins or SMBus
Tnterface
Operates up to 10 Gbps with 30” FR4 Traces
Operates up to 6.4 Gbps with 40” FR4 Traces
0.175 UI Residual Deterministic Jitter at 6.4
Gbps with 40” FR4 Traces
Single 2.5V or 3.3V Power Supply
Signal Detect for Individual Channels
Standby Mode for Individual Channels
Supports AC or DC-Coupling with Wide Input
Common-Mode
Low Power Consumption: 375 mW Typ at 2.5V
Small 7 mm x 7 mm 48-Pin WQFN Package
9 kV HBM ESD Rating
-40 to 85°C Operating Temperature Range
The equalizer supports both AC and DC-coupled data
paths for long run length data patterns such as
PRBS-31, and balanced codes such as 8b/10b. The
device uses differential current-mode logic (CML)
inputs and outputs. The DS64EV400 is available in a
7 mm x 7 mm 48-pin leadless WQFN package.
Power is supplied from either a 2.5V or 3.3V supply.
Simplified Application Diagram
4
Tx
ASIC/FPGA
High Speed I/O
Rx
OUT
4
IN
DS64EV400
Switch Fabric Card
Backplane/Cable
Sub-system
Line Card
4
Tx
ASIC/FPGA
High Speed I/O
Rx
OUT
IN
4
DS64EV400
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2013, Texas Instruments Incorporated
DS64EV400
SNLS281H – AUGUST 2007 – REVISED APRIL 2013
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Pin Descriptions
Pin Name
I/O, Type (1)
Pin No.
Description
HIGH SPEED DIFFERENTIAL I/O
IN_0+
IN_0–
1
2
I, CML
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω
terminating resistor is connected between IN_0+ and IN_0-. Refer to Figure 7.
IN_1+
IN_1–
4
5
I, CML
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω
terminating resistor is connected between IN_1+ and IN_1-. Refer to Figure 7.
IN_2+
IN_2–
8
9
I, CML
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω
terminating resistor is connected between IN_2+ and IN_2-. Refer to Figure 7.
IN_3+
IN_3–
11
12
I, CML
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω
terminating resistor is connected between IN_3+ and IN_3-. Refer to Figure 7.
OUT_0+
OUT_0–
36
35
O, CML
Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω
terminating resistor connects OUT_0+ to VDD and OUT_0- to VDD.
OUT_1+
OUT_1–
33
32
O, CML
Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω
terminating resistor connects OUT_1+ to VDD and OUT_1- to VDD.
OUT_2+
OUT_2–
29
28
O, CML
Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω
terminating resistor connects OUT_2+ to VDD and OUT_2- to VDD.
OUT_3+
OUT_3–
26
25
O, CML
Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω
terminating resistor connects OUT_3+ to VDD and OUT_3- to VDD.
I, LVCMOS
BST_2, BST_1, and BST_0 select the equalizer strength for all EQ channels. BST_2 is
internally pulled high. BST_1 and BST_0 are internally pulled low.
EQUALIZATION CONTROL
BST_2
BST_1
BST_0
37
14
23
DEVICE CONTROL
EN0
44
I, LVCMOS
Enable Equalizer Channel 0 input. When held High, normal operation is selected. When held
Low, standby mode is selected. EN is internally pulled High.
EN1
42
I, LVCMOS
Enable Equalizer Channel 1 input. When held High, normal operation is selected. When held
Low, standby mode is selected. EN is internally pulled High.
EN2
40
I, LVCMOS
Enable Equalizer Channel 2 input. When held High, normal operation is selected. When held
Low, standby mode is selected. EN is internally pulled High.
EN3
38
I, LVCMOS
Enable Equalizer Channel 3 input. When held High, normal operation is selected. When held
Low, standby mode is selected. EN is internally pulled High.
FEB
21
I, LVCMOS
Force External Boost. When held high, the equalizer boost setting is controlled by BST_[2:0]
pins. When held low, the equalizer boost setting is controlled by SMBus (Table 1) register bits.
FEB is internally pulled High.
SD0
45
O, LVCMOS
Equalizer Ch0 Signal Detect Output. Produces a High when signal is detected.
SD1
43
O, LVCMOS
Equalizer Ch1 Signal Detect Output. Produces a High when signal is detected.
SD2
41
O, LVCMOS
Equalizer Ch2 Signal Detect Output. Produces a High when signal is detected.
SD3
39
O, LVCMOS
Equalizer Ch3 Signal Detect Output. Produces a High when signal is detected.
VDD
3, 6, 7,
10, 13,
15, 46
Power
VDD = 2.5V ± 5% or 3.3V ± 10%. VDD pins should be tied to VDD plane through low inductance
path. A 0.01μF bypass capacitor should be connected between each VDD pin to GND planes.
GND
22, 24,
27, 30,
31, 34
Power
Ground reference. GND should be tied to a solid ground plane through a low impedance path.
DAP
PAD
Power
Ground reference. The exposed pad at the center of the package must be connected to ground
plane of the board.
POWER
SERIAL MANAGEMENT BUS (SMBus) INTERFACE CONTROL PINS
SDA
SDC
CS
18
17
16
I/O, LVCMOS
I, LVCMOS
I, LVCMOS
Data input/output (bi-directional). Internally pulled high.
Clock input. Internally pulled high.
Chip select. When pulled high, access to the equalizer SMBus registers are enabled. When
pulled low, access to the equalizer SMBus registers are disabled. Please refer to “ SMBus
configuration Registers” section for detail information.
Other
Reserv
(1)
2
19, 20
47,48
Reserved. Do not connect.
Note: I = Input O = Output
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VDD
SD0
EN0
SD1
EN1
SD2
EN2
SD3
EN3
BST_2
45
44
43
42
41
40
39
38
37
Reserv
47
46
Reserv
48
Connection Diagram
OUT_0+
IN_0+
1
36
IN_0-
2
35
OUT_0-
VDD
3
34
GND
IN_1+
4
33
OUT_1+
IN_1-
5
32
OUT_1-
VDD
6
31
GND
VDD
7
30
GND
IN_2+
8
29
OUT_2+
DS64EV400
TOP VIEW
DAP = GND
18
19
20
21
22
23
24
SDA
Reserv
Reserv
FEB
GND
BST_0
GND
17
OUT_3-
SDC
OUT_3+
25
16
26
12
CS
11
15
IN_3+
IN_3-
VDD
GND
14
OUT_2-
27
13
28
10
BST_1
9
VDD
VDD
IN_2-
Figure 1. WQFN Package
See Package Number NJU0048D
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
(1) (2)
−0.5V to +4.0V
Supply Voltage (VDD)
CMOS Input Voltage
−0.5V + 4.0V
CMOS Output Voltage
−0.5V to 4.0V
CML Input/Output Voltage
−0.5V to 4.0V
Junction Temperature
+150°C
Storage Temperature
−65°C to +150°C
Lead Temperature (Soldering, 4 Seconds)
+260°C
ESD Rating
HBM, 1.5 kΩ, 100 pF
> 9 kV
EIAJ, 0Ω, 200 pF
> 250V
Thermal Resistance
θJA, No Airflow
30°C/W
(1)
(2)
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Absolute
Maximum Numbers are ensured for a junction temperature range of -40°C to +125°C. Models are validated to Maximum Operating
Voltages only.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
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Recommended Operating Conditions
Supply Voltage
Min
Typ
Max
Units
VDD2.5 to GND
2.375
2.5
2.625
V
VDD3.3 to GND
3.0
3.3
3.6
V
−40
25
+85
°C
Ambient Temperature
Electrical Characteristics
Over recommended operating supply and temperature ranges with default register settings unless other specified.
Parameter
Test Conditions
Min
Typ
(1)
Max
Units
700
mW
100
mW
490
mW
POWER
P
Power Supply Consumption
Device Output Enabled
(EN [0–3] = High), VDD3.3 (2)
490
Device Output Disable
(EN [0–3] = Low), VDD3.3
P
Power Supply Consumption
Supply Noise Tolerance (3)
N
Device Output Enabled
(EN [0–3] = High), VDD2.5 (2)
360
Device Output Disable
(EN [0–3] = Low), VDD2.5 (2)
30
50 Hz — 100 Hz
100 Hz — 10 MHz
10 MHz — 1.6 GHz
100
40
10
mVP-P
mVP-P
mVP-P
LVCMOS DC SPECIFICATIONS
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
VOH
High Level Output Voltage
VDD3.3
2.0
VDD3.3
V
VDD2.5
1.6
VDD2.5
V
-0.3
0.8
V
IOH = -3mA, VDD3.3
2.4
IOH = -3mA, VDD2.5
2.0
VOL
Low Level Output Voltage
IOL = 3mA
IIN
Input Leakage Current
VIN = VDD
VIN = GND
IIN-P
Input Leakage Current with Internal
Pull-Down/Up Resistors
V
0.4
V
+15
μA
μA
-15
VIN = VDD, with internal pull-down resistors
VIN = GND, with internal pull-up resistors
+120
μA
μA
-20
SIGNAL DETECT
SDH
Signal Detect ON Threshold Level
Default input signal level to assert SD pin, 6.4
Gbps
70
mVp-p
SDI
Signal Detect OFF Threshold Level
Default input signal level to de-assert SD, 6.4
Gbps
40
mVp-p
CML RECEIVER INPUTS (IN_n+, IN_n-)
VTX
Source Transmit Launch Signal Level AC-Coupled or DC-Coupled Requirement,
(IN diff)
Differential measurement at point A.
Figure 2
VINTRE
Input Threshold Voltage
Differential measurement at
point B. Figure 2
Supply Voltage of Transmitter to EQ
DC-Coupled Requirement
VICMDC
Input Common Mode Voltage
DC-Coupled Requirement, Differential
measurement at point A. Figure 2, (5)
RLI
Differential Input Return Loss
100 MHz – 3.2 GHz, with fixture’s effect deembedded
(2)
(3)
(4)
(5)
4
1600
120
(4)
VDDTX
(1)
400
mVP-P
mVP-P
1.6
VDD
V
VDDTX –
0.8
VDDTX
– 0.2
V
10
dB
Typical values represent most likely parametric norms at VDD = 3.3V or 2.5V, TA = 25°C, and at the Recommended Operation
Conditions at the time of product characterization and are not ensured.
The VDD2.5 is VDD = 2.5V ± 5% and VDD3.3 is VDD = 3.3V ± 10%.
Allowed supply noise (mVP-P sine wave) under typical conditions.
Recommended value. Parameter not tested in production.
Measured with clock-like {11111 00000} pattern.
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Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges with default register settings unless other specified.
Parameter
Test Conditions
Min
Typ
(1)
Max
Units
Differential across IN+ and IN-, Figure 7
85
100
115
Ω
Output Differential Voltage Level
(OUT diff)
Differential measurement with OUT+ and OUTterminated by 50Ω to GND, AC-Coupled
Figure 3
500
620
725
mVP-P
VOCM
Output Common Mode Voltage
Single-ended measurement DC-Coupled with
50Ω terminations (5)
VDD–
0.2
VDD–
0.1
V
tR, tF
Transition Time
20% to 80% of differential output voltage,
measured within 1” from output pins.
Figure 3, (5)
20
60
ps
42
58
Ω
RIN
Input Resistance
CML OUTPUTS (OUT_n+, OUT_n-)
VOD
RO
Output Resistance
Single ended to VDD
50
RLO
Differential Output Return Loss
100 MHz – 1.6 GHz, with fixture’s effect deembedded. IN+ = static high.
10
dB
tPLHD
Differential Low to High Propagation
Delay
Propagation delay measurement at 50% VO
between input to output, 100 Mbps. Figure 4,
240
ps
240
ps
(5)
tPHLD
Differential High to Low Propagation
Delay
tCCSK
Inter Pair Channel to Channel Skew
Difference in 50% crossing between channels
7
ps
tPPSK
Part to Part Output Skew
Difference in 50% crossing between outputs
20
ps
UIP-P
EQUALIZATION
DJ1
Residual Deterministic Jitter
at 10 Gbps
30” of 6 mil microstrip FR4,
EQ Setting 0x06, PRBS-7 (27-1) pattern. (6)
0.20
DJ2
Residual Deterministic Jitter
at 6.4 Gbps
40” of 6 mil microstrip FR4,
EQ Setting 0x06, PRBS-7 (27-1) pattern. (7) (6)
0.17
0.26
UIP-P
DJ3
Residual Deterministic Jitter
at 5 Gbps
40” of 6 mil microstrip FR4,
EQ Setting 0x07, PRBS-7 (27-1) pattern. (7)
0.12
0.20
UIP-P
DJ4
Residual Deterministic Jitter
at 2.5 Gbps
40” of 6 mil microstrip FR4,
EQ Setting 0x07, PRBS-7 (27-1) pattern. (7) (6)
0.1
0.16
UIP-P
RJ
Random Jitter
See
(6)
(8) (9)
0.5
psrms
35
ns
400
ns
150
ns
5
ns
SIGNAL DETECT and ENABLE TIMING
tZISD
tIZSD
Input OFF to ON detect — SD Output Response time measurement at VIN to SD
High Response Time
output, VIN = 800 mVP-P, 100 Mbps, 40” of 6 mil
microstrip FR4
Input ON to OFF detect — SD Output
Figure 2 and Figure 5, (8)
Low Response Time
tOZOED
EN High to Output ON Response
Time
tZOED
EN Low to Output OFF Response
Time
(6)
(7)
(8)
(9)
Response time measurement at EN input to
VO, VIN = 800 mVP-P, 100 Mbps, 40” of 6 mil
microstrip FR4
Figure 2 and Figure 7, (8)
Deterministic jitter is measured at the differential outputs (point C of Figure 2), minus the deterministic jitter before the test channel (point
A of Figure 2). Random jitter is removed through the use of averaging or similar means.
Specification is ensured by characterization at optimal boost setting and is not tested in production.
Measured with clock-like {11111 00000} pattern.
Random jitter contributed by the equalizer is defined as sqrt (JOUT2 – JIN2). JOUT is the random jitter at equalizer outputs in ps-rms, see
point C of Figure 2; JIN is the random jitter at the input of the equalizer in ps-rms, see point B of Figure 2.
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Electrical Characteristics — Serial Management Bus Interface
Over recommended operating supply and temperature ranges unless other specified.
Parameter
Test Conditions
Min
Typ
Max
Units
0.8
V
VDD
V
SERIAL BUS INTERFACE DC SPECIFICATIONS
VIL
Data, Clock Input Low Voltage
VIH
Data, Clock Input High Voltage
IPULLUP
Current Through Pull-Up Resistor or
Current Source
VDD
Nominal Bus Voltage
ILEAK-Bus
Input Leakage Per Bus Segment
ILEAK-Pin
Input Leakage Per Device Pin
CI
RTERM
2.1
High Power Specification
4
mA
2.375
3.6
V
-200
+200
µA
See
(1)
Capacitance for SDA and SDC
See
(1) (2)
External Termination Resistance pull
to VDD = 2.5V ± 5% OR
3.3V ± 10%
VDD3.3, (1) (2) (3)
2000
Ω
VDD2.5, (1) (2) (3)
1000
Ω
-15
µA
10
pF
SERIAL BUS INTERFACE TIMING SPECIFICATIONS (Figure 8)
FSMB
Bus Operating Frequency
TBUF
Bus Free Time Between Stop and
Start Condition
THD:STA
Hold time after (Repeated) Start
Condition. After this period, the first
clock is generated.
See
(4)
10
100
kHz
4.7
µs
4.0
µs
4.7
µs
At IPULLUP, Max
TSU:STA
Repeated Start Condition Setup Time
TSU:STO
Stop Condition Setup Time
4.0
µs
THD:DAT
Data Hold Time
300
ns
TSU:DAT
Data Setup Time
250
TTIMEOUT
Detect Clock Low Timeout
TLOW
Clock Low Period
THIGH
See
(4)
Clock High Period
See
(4)
TLOW:SEXT
Cumulative Clock Low Extend Time
(Slave Device)
See
(4)
tF
Clock/Data Fall Time
See
tR
Clock/Data Rise Time
tPOR
Time in which a device must be
operational after power-on reset
(1)
(2)
(3)
(4)
6
25
ns
35
4.7
4.0
ms
µs
50
µs
2
ms
(4)
300
ns
See
(4)
1000
ns
See
(4)
500
ms
Recommended value. Parameter not tested in production.
Recommended maximum capacitance load per bus segment is 400pF.
Maximum termination voltage should be identical to the device supply voltage.
Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1
SMBus common AC specifications for details.
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System Management Bus (SMBus) and Configuration Registers
The System Management Bus interface is compatible to SMBus 2.0 physical layer specification. The use of the
Chip Select signal is required. Holding the CS pin High enables the SMBus port allowing access to the
configuration registers. Holding the CS pin Low disables the device's SMBus allowing communication from the
host to other slave devices on the bus. In the STANDBY state, the System Management Bus remains active.
When communication to other devices on the SMBus is active, the CS signal for the DS32EV400s must be
driven Low.
The address byte for all DS64EV400s is AC'h. Based on the SMBus 2.0 specification, the DS64EV400 has a 7bit slave address of 1010110'b. The LSB is set to 0'b (for a WRITE), thus the 8-bit value is 1010 1100'b or AC'h.
The SDC and SDA pins are 3.3V LVCMOS signaling and include high-Z internal pull up resistors. External low
impedance pull up resistors maybe required depending upon SMBus loading and speed. Note, these pins are not
5V tolerant.
Transfer of Data via the SMBus
During normal operation the data on SDA must be stable during the time when SDC is High.
There are three unique states for the SMBus:
START A High-to-Low transition on SDA while SDC is High indicates a message START condition.
STOP A Low-to-High transition on SDA while SDC is High indicates a message STOP condition.
IDLE If SDC and SDA are both High for a time exceeding tBUF from the last detected STOP condition or if they
are High for a total exceeding the maximum specification for tHIGH then the bus will transfer to the IDLE
state.
SMBus Transactions
The device supports WRITE and READ transactions. See Register Description table for register address, type
(Read/Write, Read Only), default value and function information.
Writing a Register
To
1.
2.
3.
4.
5.
6.
7.
8.
9.
write a register, the following protocol is used (see SMBus 2.0 specification).
The Host (Master) selects the device by driving its SMBus Chip Select (CS) signal High.
The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
The Device (Slave) drives the ACK bit (“0”).
The Host drives the 8-bit Register Address.
The Device drives an ACK bit (“0”).
The Host drive the 8-bit data byte.
The Device drives an ACK bit (“0”).
The Host drives a STOP condition.
The Host de-selects the device by driving its SMBus CS signal Low.
The WRITE transaction is completed, the bus goes IDLE and communication with other SMBus devices may
now occur.
Reading a Register
To
1.
2.
3.
4.
5.
6.
7.
8.
read a register, the following protocol is used (see SMBus 2.0 specification).
The Host (Master) selects the device by driving its SMBus Chip Select (CS) signal High.
The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
The Device (Slave) drives the ACK bit (“0”).
The Host drives the 8-bit Register Address.
The Device drives an ACK bit (“0”).
The Host drives a START condition.
The Host drives the 7-bit SMBus Address, and a “1” indicating a READ.
The Device drives an ACK bit “0”.
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9. The Device drives the 8-bit data value (register contents).
10. The Host drives a NACK bit “1”indicating end of the READ transfer.
11. The Host drives a STOP condition.
12. The Host de-selects the device by driving its SMBus CS signal Low.
The READ transaction is completed, the bus goes IDLE and communication with other SMBus devices may now
occur.
See Table 1 for more information.
Table 1. SMBus Register Address
Name
Type
Address
Default
Status
0x00
0x00
RO
ID Revision
SD3
SD2
Status
0x01
0x00
RO
EN1
Boost 1
EN0
Boost 0
Status
0x02
0x00
RO
EN3
Boost 3
EN2
Boost 2
Enable/Boost
(CH 0, 1)
0x03
0x44
RW
EN1 Output
0:Enable
1:Disable
Boost Control for CH1
000 (Min Boost)
001
010
011
100 (Default)
101
110
111 (Max Boost)
EN0
Output
0:Enable
1:Disable
Boost Control for CH0
000 (Min Boost)
001
010
011
100 (Default)
101
110
111 (Max Boost)
Enable/Boost
(CH 2, 3)
0x04
0x44
RW
EN3 Output
0:Enable
1:Disable
Boost Control for CH3
000 (Min Boost)
001
010
011
100 (Default)
101
110
111 (Max Boost)
EN2
Output
0:Enable
1:Disable
Boost Control for CH2
000 (Min Boost)
001
010
011
100 (Default)
101
110
111 (Max Boost)
Signal Detect
0x05
0x00
RW
SD3 ON Threshold
Select
00: 70 mV (Default)
01: 55 mV
10: 90 mV
11: 75 mV
SD2 ON Threshold
Select
00: 70 mV (Default)
01: 55 mV
10: 90 mV
11: 75 mV
SD1 ON Threshold
Select
00: 70 mV (Default)
01: 55 mV
10: 90 mV
11: 75 mV
SD0 ON Threshold
Select
00: 70 mV (Default)
01: 55 mV
10: 90 mV
11: 75 mV
Signal Detect
0x06
0x00
RW
SD3 OFF Threshold
Select
00: 40 mV (Default)
01: 30 mV
10: 55 mV
11: 45 mV
SD2 OFF Threshold
Select
00: 40 mV (Default)
01: 30 mV
10: 55 mV
11: 45 mV
SD1 OFF Threshold
Select
00: 40 mV (Default)
01: 30 mV
10: 55 mV
11: 45 mV
SD0 OFF Threshold
Select
00: 40 mV (Default)
01: 30 mV
10: 55 mV
11: 45 mV
SMBus
Control
0x07
0x00
RW
Reserved
Output Level
0x08
0x78
RW
Reserved
(1)
8
Bit 7
(1)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
SD1
Bit 0
SD0
SMBus
Enable
Control
0: Disable
1: Enable
Output Level:
00: 400 mVP-P
01: 540 mVP-P
10: 620 mVPP(Default)
11: 760 mVP-P
Reserved
Note: RO = Read Only, RW = Read/Write
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B
A
C
6 mils Trace Width,
FR4 Microstrip Test Channel
DS64EV400
Signal Source
INPUT
SMA
Connector
OUTPUT
SMA
Connector
Figure 2. Test Setup Diagram
80%
80%
0V
OUT diff = (OUT+) ± (OUT-)
20%
20%
tR
tF
Figure 3. CML Output Transition Times
IN diff
0V
tPLHD
OUT diff
tPHLD
0V
Figure 4. Propagation Delay Timing Diagram
IN diff
0V
tIZSD
tZISD
VDD
SD
1.5V
1.5V
0V
Figure 5. Signal Detect (SD) Delay Timing Diagram
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VDD
EN
1.5V
1.5V
0V
tOZED
tZOED
0V
OUT diff
Figure 6. Enable (EN) Delay Timing Diagram
VDD
10k
IN +
50
VDD
6k
EQ
10k
50
IN 6k
Figure 7. Simplified Receiver Input Termination Circuit
tSU:CS
CS
tLOW
tR
tHIGH
SDC
tHD:STA
tBUF
tHD:DAT
tF
tSU:STA
tSU:DAT
tSU:STO
SDA
SP
ST
SP
ST
Figure 8. SMBus Timing Parameters
DS64EV400 FUNCTIONAL DESCRIPTIONS
The DS64EV400 is a programmable quad equalizer optimized for operation up to 10 Gbps for backplane and
cable applications.
DATA CHANNELS
The DS64EV400 provides four data channels. Each data channel consists of an equalizer stage, a limiting
amplifier, a DC offset correction block, and a CML driver as shown in Figure 9.
10
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DC Offset Correction
Data Channel (0-3)
Input
Termination
IN_n +
IN_n SDn
Limiting
Amplifier
Equalizer
BST
CNTL
EN
EN
EN
OUT_n +
OUT_n -
VDD
SD
BST_0:BST_2
ENn
VDD
3
Reg 03,04
bit 7, 3
3
3
Reg 07 SMBus
bit 0 Register
Boost Setting
SMBus Register
FEB
Figure 9. Simplified Block Diagram
EQUALIZER BOOST CONTROL
Each data channel support eight programmable levels of equalization boost. The state of the FEB pin determines
how the boost settings are controlled. If the FEB pin is held High, then the equalizer boost setting is controlled by
the Boost Set pins (BST_[2:0]) in accordance with Table 2. If this programming method is chosen, then the boost
setting selected on the Boost Set pins is applied to all channels. When the FEB pin is held Low, the equalizer
boost level is controlled through the SMBus. This programming method is accessed via the appropriate SMBus
registers (see Table 1). Using this approach, equalizer boost settings can be programmed for each channel
individually. FEB is internally pulled High (default setting); therefore if left unconnected, the boost settings are
controlled by the Boost Set pins (BST_[0:2]). The eight levels of boost settings enables the DS64EV400 to
address a wide range of media loss and data rates.
Table 2. EQ Boost Control Table
6 mil Microstrip FR4
Trace Length (m)
24 AWG Twin-AX cable
length (m)
Channel Loss at 3.2 GHz
(dB)
Channel Loss at 5 GHz
(dB)
BST_N
[2, 1, 0]
0
0
0
0
000
5
2
5
6
001
10
3
7.5
10
010
15
4
10
14
011
20
5
12.5
18
1 0 0 (Default)
25
6
15
21
101
30
7
17
24
110
40
10
22
30
111
DEVICE STATE AND ENABLE CONTROL
The DS64EV400 has an enable feature on each data channel which provides the ability to control device power
consumption. This feature can be controlled either an Enable Pin (EN_n) with Reg 07 = 00'h (default value), or
by the Enable Control Bit register which can be configured through the SMBus port (see Table 1 and Table 3 for
detail register information), which require setting Reg 07 = 01'h and changing register value of Reg 03, 04. If the
Enable is activated using either the external EN_n pin or SMBUS register, the corresponding data channel is
placed in the ACTIVE state and all device blocks function as described. The DS64EV400 can also be placed in
STANDBY mode to save power. In the STANDBY mode only the control interface including the SMBus port, as
well as the signal detection circuit remain active.
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Table 3. Controlling Device State
Register 07[0] (SMBus)
ENn Pin (CMOS)
CH 0:
Reg. 03 bit 3
CH 1:
Reg. 03 bit 7
CH 2:
Reg. 04 bit 3
CH 3:
Reg. 04 bit 7
(EN Control)
0 : Disable
1
X
ACTIVE
0 : Disable
0
X
STANDBY
1 : Enable
X
0
ACTIVE
1 : Enable
X
1
STANDBY
Device State
SIGNAL DETECT
The DS64EV400 features a signal detect circuit on each data channel. The status of the signal of each channel
can be determined by either reading the Signal Detect bit (SDn) in the SMBus registers (see Table 1) or by the
state of each SDn pin. An output logic high indicates the presence of a signal that has exceeded the ON
threshold value (called SD_ON). An output logic Low means that the input signal has fallen below the OFF
threshold value (called SD_OFF). These values are programmed via the SMBus (Table 1). If not programmed via
the SMBus, the thresholds take on the default values as shown in Table 4. The Signal Detect threshold values
can be changed through the SMBus. All threshold values specified are DC peak-to-peak differential signals
(positive signal minus negative signal) at the input of the device.
Table 4. Signal Detect Threshold Values
Channel 0: Bit 1
Channel 1: Bit 3
Channel 2: Bit 5
Channel 3: Bit 7
Channel 0: Bit 0
Channel 1: Bit 2
Channel 2: Bit 4
Channel 3: Bit 6
SD_OFF Threshold
Register 06 (mV)
SD_ON Threshold
Register 05 (mV)
0
0
40 (Default)
70 (Default)
0
1
30
55
1
0
55
90
1
1
45
75
OUTPUT LEVEL CONTROL
The output amplitude of the CML drivers for each channel can be controlled via the SMBus (see Table 1). The
default output level is 620 mVp-p. The following Table presents the output level values supported:
Table 5. Output Level Control Settings
All Channels : Bit 3
All Channels : Bit 2
Output Level Register 08 (mVP-P)
0
0
400
0
1
540
1
0
620 (Default)
1
1
760
AUTOMATIC ENABLE FEATURE
It may be desirable to place unused channels in power-saving Standby mode. This can be accomplished by
connecting the Signal detect (SDn) pin to the Enable (ENn) pin for each channel (See Figure 10). In order for this
option to function properly, the register value for Reg. 07 should be 00'h (default value). If an input signal swing
applied to a data channel is above the voltage level threshold as shown in Table 4, then the SDn output pin is
asserted High. If the SDn pin is connected to the ENn pin, this will enable the equalizer, limiting amplifier, and
output buffer on the data channels; thus the DS64EV400 will automatically enter the ACTIVE state. If the input
signal swing falls below the SD_OFF threshold level, then the SDn output will be asserted Low, causing the
channel to be placed in the STANDBY state.
12
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DS64EV400 Applications Information
IN_n r
Limiting
Amplifier
Equalizer
CML
Driver
OUT_n r
ENn
Reg 07 = K¶00
(Default)
Signal Detect
SDn
Figure 10. Automatic Enable Configuration
UNUSED EQUALIZER CHANNELS
It is recommended to put all unused channels into standby mode.
GENERAL RECOMMENDATIONS
The DS64EV400 is a high performance circuit capable of delivering excellent performance. Careful attention
must be paid to the details associated with high-speed design as well as providing a clean power supply. Refer
to the LVDS Owner's Manual for more detailed information on high speed design tips to address signal integrity
design issues.
PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL PAIRS
The CML inputs and outputs must have a controlled differential impedance of 100Ω. It is preferable to route CML
lines exclusively on one layer of the board, particularly for the input traces. The use of vias should be avoided if
possible. If vias must be used, they should be used sparingly and must be placed symmetrically for each side of
a given differential pair. Route the CML signals away from other signals and noise sources on the printed circuit
board. See AN-1187(SNOA401) for additional information on WQFN packages.
POWER SUPPLY BYPASSING
Two approaches are recommended to ensure that the DS64EV400 is provided with an adequate power supply.
First, the supply (VDD) and ground (GND) pins should be connected to power planes routed on adjacent layers of
the printed circuit board. The layer thickness of the dielectric should be minimized so that the VDD and GND
planes create a low inductance supply with distributed capacitance. Second, careful attention to supply
bypassing through the proper use of bypass capacitors is required. A 0.01μF bypass capacitor should be
connected to each VDD pin such that the capacitor is placed as close as possible to the DS64EV400. Smaller
body size capacitors can help facilitate proper component placement. Additionally, three capacitors with
capacitance in the range of 2.2 μF to 10 μF should be incorporated in the power supply bypassing design as
well. These capacitors can be either tantalum or an ultra-low ESR ceramic and should be placed as close as
possible to the DS64EV400.
DC COUPLING
The DS64EV400 supports both AC coupling with external ac coupling capacitor, and DC coupling to its upstream
driver, or downstream receiver. With DC coupling, users must ensure the input signal common mode is within the
range of the electrical specification VICMDC and the device output is terminated with 50 Ω to VDD. When power-up
and power-down the device, both the DS64EV400 and the downstream receiver should be power-up and powerdown together. This is to avoid the internal ESD structures at the output of the DS64EV400 at power-down from
being turned on by the downstream receiver.
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Typical Performance Eye Diagrams and Curves
14
Figure 11. Equalized Signal
(40 In FR4, 2.5Gbps, PRBS7, 0x07 Setting)
Figure 12. Equalized Signal
(40 In FR4, 5Gbps, PRBS7, 0x07 Setting)
Figure 13. Equalized Signal
(40 In FR4, 6.4 Gbps, PRBS7, 0x06 Setting)
Figure 14. Equalized Signal
(40 In FR4, 6.4 Gbps, PRBS31, 0x06 Setting)
Figure 15. Equalized Signal
(30 In FR4, 10 Gbps, PRBS7, 0x06 Setting)
Figure 16. Equalized Signal
(10m 24 AWG Twin-Ax Cable, 6.4 Gbps, PRBS7, 0x07
Setting)
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Typical Performance Eye Diagrams and Curves (continued)
Figure 17. Equalized Signal
(32 In Tyco XAUI Backplane, 6.25 Gbps, PRBS7, 0x06
Setting)
Figure 18. DJ vs. EQ Setting (10 Gbps)
Figure 19. DJ vs EQ Setting (6.4 Gbps)
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REVISION HISTORY
Changes from Revision G (April 2013) to Revision H
•
16
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 15
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PACKAGE OPTION ADDENDUM
www.ti.com
30-May-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
DS64EV400SQ/NOPB
LIFEBUY
Package Type Package Pins Package
Drawing
Qty
WQFN
NJU
48
250
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
Op Temp (°C)
Device Marking
(4/5)
-40 to 85
DS64EV400
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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