DS80PCI102EVK/NOPB

User’s Guide September 2012 DS80PCI102EVK User’s Guide CONTENTS 1. 1 INTRODUCTION ....................................................................................................... 1 2 SETUP....................................................................................................................... 3 3 BOARD LAYOUT ..................................................................................................... 8 4 SCHEMATIC ........................................................................................................... 10 1 2 3 4 5 6 LIST OF FIGURES DS80PCI102EVK Top view photo ............................................................................. 3 4-Level IO Control on EVK ........................................................................................ 4 Top Assembly Layer .................................................................................................. 8 Bottom Assembly Layer ............................................................................................. 9 DS80PCI102EVK Schematic (Page 1) .................................................................... 10 DS80PCI102EVK Schematic (Page 2) .................................................................... 11 1 2 3 4 5 LIST OF TABLES Device and Package Configurations.......................................................................... 1 EQA/B[1:0] Pin Setting Information ........................................................................... 5 VOD_SEL and DEMA/B Pin Setting Information ....................................................... 6 PRSNT# and RXDET Pin Setting Information ........................................................... 6 DS80PCI102 Bill of Materials .................................................................................. 12 Introduction The DS80PCI102EVK – SMA evaluation kit provides a complete high band-width platform to evaluate the signal integrity and signal conditioning features of the Texas Instruments signal conditioning products – with Equalization and De-emphasis. SMA edge launch connectors are used as the input and the output connections for this evaluation board. Commercially available adaptor boards can be purchased to facilitate connection to cables or backplane interconnects. Table 1: Device and Package Configurations September 2012 DEVICE IC PACKAGE U1 DS80PCI102SQE QFN-24 DS80PCI102EVK User’s Guide 1 Features: ■ 1 lane PCIe repeater up to 8 Gbps (GEN 3) ■ Low power consumption, with option to power down unused channels ■ Adjustable receive equalization ■ Adjustable transmit VOD and De-emphasis ■ IDLE detection — squelch function auto mutes the output ■ Programmable via pin selection or SMBus interface ■ Single supply operation: VIN = 3.3V±10% or VDD = 2.5V ±5% ■ -40°C to +85°C Operation ■ >5 kV HBM ESD Rating ■ High speed signal flow–thru pin-out package – SQA24A: 24-pin LLP (10 mm x 5.5 mm, 0.5 mm pitch) Applications: ■ FR-4 Backplane Traces and High Speed Cable for PCIe GEN 3 Demo Kit Contents: ■ End User License Agreement ■ DS80PCI102EVK User Guide ■ DS80PCI102EVK PCB Ordering Information: DEVICE: DS80PCI102SQ – QTY = 2000, DS80PIC102SQE – QTY = 250 SMA Evaluation Kit: DS80PCI102EVK 2 DS80PCI102EVK User’s Guide September 2012 2. Setup This section describes the jumpers and connectors on the EVM as well and how to properly connect, set up and use the DS80PCI102EVK. Figure 1: DS80PCI102EVK Evaluation Board September 2012 Literature #: SNLU111 3 2.1. Mode The DS80PCI102EVK – SMA evaluation kit can be used in three different modes. 1. Pin Control Mode (provides access to selected signal integrity settings) 2. SMBUS Mode (full access to signal integrity and control settings) 3. EEPROM Mode (full access to signal integrity and control settings) The EEPROM mode is a convenient method of programming one or more DS80PCI102 devices on system power-up when a SMBus master (microcontroller or similar) is unavailable in the design. Pin Control with Jumpers: Uses the external control pins on the DS80PCI102 to configure the signal integrity and control settings of the device. In this mode only a subset of the equalization and de-emphasis levels are available. Due to the limited number of control pins, a limited bandwidth 4-level input scheme has been implemented across the control pin interface. This allows for improved EQ, DE, and VOD control with fewer physical pins. The 4 levels are defined as: 1. 2. 3. 4. Low - 0 Resistor - R Float - F High - 1 1K to GND 20K to GND Open 1K to VDD The EVK interfaces to this 4-level IO using the setup below. Only one shunt connection is required to access any of the 4 levels. This methodology minimizes the risk of improper connections that could damage the board or board power supply. 4-LEVEL CONTROL HIGH RESISTOR FLOAT LOW HIGH SIGNAL RESISTOR SIGNAL LOW PIN HEADER CONNECTION Figure 2: 4-Level IO Control on EVK 4 DS80PCI102EVK User’s Guide September 2012 PIN CONTROL: The DS80PCI102EVK are shipped ready to use in pin control configuration. As delivered, the EVK will have the following installed jumpers. 1. J4 – VIN to VIH = 3.3V supply operation: Use the J1 and J3 connectors to supply VIN = 3.3V and GND. 2. J22 – VDD_SEL = GND: Use internal regulator to convert 3.3V supply to proper internal supply level of 2.5V. Note: The 2.5V level may be observed on J2 (VDD) or the device VDD pins. 3. J19 – ENSMB = 0: PIN CONTROL configuration mode. 4. J18 – PRSNT# = 0: Device is enabled. 5. J20 – RATE = Float: AUTO RATE detection. The auto RATE detect circuit requires the IDLE and ACTIVE signal which occurs during the link training negotiation. If the Beacon signal is not available then the RATE pin needs to be forced. RATE = 0 (GEN 1/2), RATE = R (GEN 3) 6. J24 – RXDET = Float: AUTO continuous RX detection. 7. J23 – VOD_SEL = Float : VOD = 1.0 Vp-p output amplitude. 8. J1, J2, J5, J6 – EQA/B[1:0] = R, R: EQ = 14.6 dB at 4 GHz. 9. J3, J4 – DEMA/B = 0: De-emphasis = 0 dB. 10. J21 – SD_TH = Float: Default signal detect threshold levels. Level 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 EQA1 EQB1 0 0 0 0 R R R R Float Float Float Float 1 1 1 1 EQA0 EQB0 0 R Float 1 0 R Float 1 0 R Float 1 0 R Float 1 EQ – 8 bits [7:0] 0000 0000 = 0x00 0000 0001 = 0x01 0000 0010 = 0x02 0000 0011 = 0x03 0000 0111 = 0x07 0001 0101 = 0x15 0000 1011 = 0x0B 0000 1111 = 0x0F 0101 0101 = 0x55 0001 1111 = 0x1F 0010 1111 = 0x2F 0011 1111 = 0x3F 1010 1010 = 0xAA 0111 1111 = 0x7F 1011 1111 = 0xBF 1111 1111 = 0xFF dB at 1.25 GHz 2.1 3.4 4.8 5.9 7.2 6.1 8.8 10.2 7.5 11.4 13 14.2 13.8 15.6 17.2 18.4 dB at 2.5 GHz 3.7 5.8 7.7 8.9 11.2 11.4 13.5 15 12.8 17.4 19.7 21.1 21.7 23.5 25.8 27.3 dB at 4 GHz 4.9 7.9 9.9 11 14.3 14.6 17 18.5 18 22 24.4 25.8 27.4 29 31.4 32.7 Suggested Use FR4 < 5 inch trace FR4 5 inch 5–mil trace FR4 5 inch 4–mil trace FR4 10 inch 5–mil trace FR4 10 inch 4–mil trace FR4 15 inch 4–mil trace FR4 20 inch 4–mil trace FR4 25 - 30 inch 4–mil trace FR4 30 inch 4–mil trace FR4 35 inch 4–mil trace 10m, 30awg cable 10m – 12m cable Table 2: EQA/B[1:0] Pin Setting Information September 2012 Literature #: SNLU111 5 Level 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VOD_SEL 0 0 0 0 R R R R Float Float Float Float 1 1 1 1 DEMA/DEMB 0 R Float 1 0 R Float 1 0 R Float 1 0 R Float 1 VOD (Vp-p) 0.7 0.7 0.7 0.7 1.2 1.2 1.2 1.2 1 1 1 1 1.1 1.1 1.3 1.3 DEM (dB) 0 -6 -3.5 -9 0 -6 -3.5 -9 0 -6 -3.5 -9 0 -1.5 -1.5 -3.5 Suggested Use FR4