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DS80PCI810
SNLS493A – OCTOBER 2014 – REVISED JANUARY 2015
DS80PCI810 Low-Power 8 Gbps 8-Channel Linear Repeater
1 Features
3 Description
•
The DS80PCI810 is an extremely low-power highperformance repeater/redriver designed to support
eight channels carrying high speed interface up to 8
Gbps, such as PCIe Gen-1, 2, and 3. The receiver's
continuous time linear equalizer (CTLE) provides high
frequency boost that is programmable from 2.7 to 9.5
dB at 4 GHz (8 Gbps) followed by a linear output
driver. The CTLE receiver is capable of opening an
input eye that is completely closed due to inter
symbol interference (ISI) induced by interconnect
medium such as board traces or twin axial-copper
cables. The programmable equalization maximizes
the flexibility of physical placement within the
interconnect channel and improves overall channel
performance.
1
•
•
•
•
•
•
•
•
•
•
Low 70 mW/Channel (Typ) Power Consumption,
With Option to Power Down Unused Channels
Seamless Link Training Support
Advanced Configurable Signal Conditioning I/O
– Receive CTLE up to ~10 dB at 4 GHz
– Linear Output Driver
– Variable Output Voltage Range up to 1200
mVp-p
Automatic Receiver Detect (Hot-Plug)
Ultra-Low Input-to-Output Latency: 80 ps (Typ)
Programmable via Pin Selection, EEPROM, or
SMBus Interface
Single Supply Voltage: 2.5 V or 3.3 V
4 kV HBM ESD Rating
−40°C to 85°C Operating Temperature Range
Flow-Thru Layout in 10 mm x 5.5 mm 54-Pin
Leadless WQFN Package
Pin Compatible with DS80PCI800
2 Applications
•
•
PCI Express Gen-1, 2, and 3
Other Proprietary High Speed Interfaces Up to 8
Gbps
When operating in PCIe applications, the
DS80PCI810
preserves
transmit
signal
characteristics, thereby allowing the host controller
and the end point to negotiate transmit equalizer
coefficients. This transparency in the link training
protocol facilitates system level interoperability and
minimizes latency.
The programmable settings can be applied easily via
pin control, software (SMBus or I2C), or direct loading
from an external EEPROM. In EEPROM mode, the
configuration information is automatically loaded on
power up, thereby eliminating the need for an
external microprocessor or software driver.
Simplified Functional Block Diagram
.
.
.
INB_0+
INB_0-
.
.
.
OUTB_0+
OUTB_0-
.
.
.
INB_3+
INB_3-
OUTB_3+
OUTB_3-
INA_0+
INA_0-
OUTA_0+
OUTA_0-
.
.
.
.
.
.
.
.
.
INA_3+
INA_3-
.
.
.
.
.
.
Device Information(1)
PART NUMBER
.
.
.
DS80PCI810
PACKAGE
WQFN (54)
10 mm x 5.5 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
.
.
.
Typical Application Block Diagram
OUTA_3+
OUTA_38
AD0
Address
straps
(pull-up or
pull-down)
BODY SIZE (NOM)
TX
AD1
AD2
Connector
AD3
SMBus
Slave Mode(1)
READ_EN
2.5 V
Mode(3)
ENSMB
SMBus
Slave Mode(1)
VDD_SEL
SDA(2)
SCL(2)
To system
SMBus
ALL_DONE
8
10 F
1 F
0.1 F
(5x)
8
RX
DS80PCI810
VIN
2.5V
ASIC
or
PCIe EP
VDD
VDD
GND
System Board
Root Complex
RX
DS80PCI810
Connector
8
(1) Schematic requires different connections for SMBus Master Mode and Pin Mode
(2) SMBus signals need to be pulled up elsewhere in the system.
(3) Schematic requires different connections for 3.3 V mode
TX
ard
Bo ce
Tra
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS80PCI810
SNLS493A – OCTOBER 2014 – REVISED JANUARY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
7
6.1
6.2
6.3
6.4
6.5
6.6
6.7
Absolute Maximum Ratings ...................................... 7
ESD Ratings.............................................................. 7
Handling Ratings ...................................................... 7
Recommended Operating Conditions....................... 7
Thermal Information ................................................. 8
Electrical Characteristics........................................... 8
Electrical Characteristics — Serial Management Bus
Interface .................................................................. 11
6.8 Timing Requirements Serial Bus Interface ............. 11
6.9 Typical Characteristics ............................................ 13
7
7.3
7.4
7.5
7.6
7.7
7.8
8
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Writing a Register ...................................................
Reading a Register .................................................
Register Maps .........................................................
15
15
18
26
27
28
Applications and Implementation ...................... 41
8.1 Application Information............................................ 41
8.2 Typical Applications ................................................ 42
9 Power Supply Recommendations...................... 50
10 Layout................................................................... 51
10.1 Layout Guidelines ................................................. 51
10.2 Layout Example .................................................... 51
11 Device and Documentation Support ................. 52
Detailed Description ............................................ 14
11.1 Trademarks ........................................................... 52
11.2 Electrostatic Discharge Caution ............................ 52
11.3 Glossary ................................................................ 52
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
12 Mechanical, Packaging, and Orderable
Information ........................................................... 52
4 Revision History
Changes from Original (September 2014) to Revision A
Page
•
Changed pin assignment numbers for OUTB_2+/- and OUTB_3+/- to correct typo ............................................................. 4
•
Changed ENSMB pin type to 4-level LVCMOS per input pin behavior.................................................................................. 4
•
Changed Handling Ratings table to ESD Ratings table. Moved Tstg and Tsolder parameters into Absolute Maximum
Ratings table........................................................................................................................................................................... 7
•
Changed register map rows to combine multiple consecutive registers with a value of all zeros and no EEPROMrelevant bits ......................................................................................................................................................................... 29
2
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DS80PCI810
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SNLS493A – OCTOBER 2014 – REVISED JANUARY 2015
5 Pin Configuration and Functions
PWDN
VDD
VODA1/SCL
VODA0/SDA
ENSMB
AD2
EQB/AD3
51
50
49
48
47
46
VODB0/AD1
53
52
VODB1/AD0
54
54-Pin WQFN
Package NJY
Top View
SMBUS AND CONTROL
INB_0+
1
45
OUTB_0+
INB_0-
2
44
OUTB_0-
INB_1+
3
43
OUTB_1+
INB_1-
4
42
OUTB_1-
INB_2+
5
41
VDD
INB_2-
6
40
OUTB_2+
INB_3+
7
39
OUTB_2-
INB_3-
8
38
OUTB_3+
VDD
9
37
OUTB_3-
INA_0+
10
36
VDD
INA_0-
11
35
OUTA_0+
INA_1+
12
34
OUTA_0-
INA_1-
13
33
OUTA_1+
VDD
14
32
OUTA_1-
INA_2+
15
31
OUTA_2+
INA_2-
16
30
OUTA_2-
INA_3+
17
29
OUTA_3+
INA_3-
18
28
OUTA_3-
19
20
21
22
23
24
25
26
27
RESERVED3
EQA
RESERVED2
RXDET
RESERVED1
VIN
VDD_SEL
SD_TH/READ_EN
ALL_DONE
DAP = GND
NOTE: Above 54-lead WQFN graphic is a TOP VIEW, looking down through the package.
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SNLS493A – OCTOBER 2014 – REVISED JANUARY 2015
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Pin Functions (1)
PIN NAME
PIN NUMBER
I/O, TYPE
DESCRIPTION
DIFFERENTIAL HIGH SPEED I/O
INB_0+,
INB_1+,
INB_2+,
INB_3+,
INB_0- ,
INB_1-,
INB_2-,
INB_3-
OUTB_0+,
OUTB_1+,
OUTB_2+,
OUTB_3+,
INA_0+,
INA_1+,
INA_2+,
INA_3+,
OUTB_0-,
OUTB_1-,
OUTB_2-,
OUTB_3-
INA_0- ,
INA_1-,
INA_2-,
INA_3-
OUTA_0+,
OUTA_1+,
OUTA_2+,
OUTA_3+,
OUTA_0-,
OUTA_1-,
OUTA_2-,
OUTA_3-
1, 2
3, 4
5, 6
7, 8
I, CML
Inverting and non-inverting CML differential inputs to the equalizer.
On-chip 50 Ω termination resistor connects INB_n+ to VDD and INB_nto VDD depending on the state of RXDET. See Table 2.
AC coupling required on high-speed I/O
45, 44
43, 42
40, 39
38, 37
O, CML
Inverting and non-inverting 50 Ω driver outputs. Compatible with AC
coupled CML inputs.
AC coupling required on high-speed I/O
10, 11
12, 13
15, 16
17, 18
I, CML
Inverting and non-inverting CML differential inputs to the equalizer.
On-chip 50 Ω termination resistor connects INA_n+ to VDD and INA_nto VDD depending on the state of RXDET. See Table 2.
AC coupling required on high-speed I/O
35, 34
33, 32
31, 30
29, 28
O, CML
Inverting and non-inverting 50 Ω driver outputs. Compatible with AC
coupled CML inputs.
AC coupling required on high-speed I/O
I, 4-LEVEL,
LVCMOS
System Management Bus (SMBus) Enable Pin
Tie 1 kΩ to VDD (2.5 V mode) or VIN (3.3 V mode) = Register Access
SMBus Slave Mode
FLOAT = Read External EEPROM (SMBus Master Mode)
Tie 1 kΩ to GND = Pin Mode
CONTROL PINS — SHARED (LVCMOS)
ENSMB
48
ENSMB = 1 (SMBus SLAVE MODE)
SCL
50
I, LVCMOS,
O, OPEN Drain
In SMBus Slave Mode, this pin is the SMBus clock I/O. Clock input or
open drain output.
External 2 kΩ to 5 kΩ pull-up resistor required as per SMBus interface
standards (2)
SDA
49
I, LVCMOS,
O, OPEN Drain
In both SMBus Modes, this pin is the SMBus data I/O. Data input or
open drain output.
External 2 kΩ to 5 kΩ pull-up resistor required as per SMBus interface
standards (2)
AD0-AD3
54, 53, 47, 46
I, LVCMOS
SMBus Slave Address Inputs. In both SMBus Modes, these pins are the
user set SMBus slave address inputs.
External 1 kΩ pull-up or pull-down recommended.
Note: In Pin Mode, AD2 must be tied via external 1 kΩ to GND.
RESERVED2
21
I, 4-LEVEL,
LVCMOS
Reserved
For applications requiring Signal Detect status register read-back:
● Leave Pin 21 floating.
● Write Reg 0x08[2] = 1 if Pin 21 is floating.
Otherwise, tie Pin 21 via external 1 kΩ to GND (External 1 kΩ to VDD
(2.5 V mode) or VIN (3.3 V mode) is also acceptable).
RESERVED3
19
I, 4-LEVEL,
LVCMOS
Reserved
This input may be left floating, tied via 1 kΩ to VDD (2.5 V mode) or VIN
(3.3 V mode), or tied via 1 kΩ to GND.
(1)
(2)
4
LVCMOS inputs without the “Float” conditions must be driven to a logic low or high at all times or operation is not ensured.
Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%.
For 3.3 V mode operation, VIN pin input = 3.3 V and the logic "1" or "high" reference for the 4-level input is 3.3 V.
For 2.5 V mode operation, VDD pin output= 2.5 V and the logic "1" or "high" reference for the 4-level input is 2.5 V.
SCL and SDA pins can be tied either to 3.3 V or 2.5 V, regardless of whether the device is operating in 2.5 V mode or 3.3 V mode.
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Pin Functions(1) (continued)
PIN NAME
PIN NUMBER
I/O, TYPE
DESCRIPTION
ENSMB = Float (SMBus MASTER MODE)
SCL
50
I, LVCMOS,
O, OPEN Drain
Clock output when loading EEPROM configuration, reverting to SMBus
clock input when EEPROM load is complete (ALL_DONE = 0).
External 2 kΩ to 5 kΩ pull-up resistor required as per SMBus interface
standards (2)
SDA
49
I, LVCMOS,
O, OPEN Drain
In both SMBus Modes, this pin is the SMBus data I/O. Data input or
open drain output.
External 2 kΩ to 5 kΩ pull-up resistor required as per SMBus interface
standards (2)
AD0-AD3
54, 53, 47, 46
I, LVCMOS
SMBus Slave Address Inputs. In both SMBus Modes, these pins are the
user set SMBus slave address inputs.
External 1 kΩ pull-up or pull-down recommended.
Note: In Pin Mode, AD2 must be tied via external 1 kΩ to GND.
READ_EN
26
I, LVCMOS
A logic low on this pin starts the load from the external EEPROM (3).
Once EEPROM load is complete (ALL_DONE = 0), this pin functionality
remains as READ_EN. It does not revert to an SD_TH input.
RESERVED2
21
I, 4-LEVEL,
LVCMOS
Reserved
For applications requiring Signal Detect status register read-back:
● Leave Pin 21 floating.
● Write Reg 0x08[2] = 1 if Pin 21 is floating.
Otherwise, tie Pin 21 via external 1 kΩ to GND (External 1 kΩ to VDD
(2.5 V mode) or VIN (3.3 V mode) is also acceptable).
RESERVED3
19
I, 4-LEVEL,
LVCMOS
Reserved
This input may be left floating, tied via 1 kΩ to VDD (2.5 V mode) or VIN
(3.3 V mode), or tied via 1 kΩ to GND.
I, 4-LEVEL,
LVCMOS
EQA and EQB pins control the level of equalization for the A-channels
and B-channels, respectively. The pins are defined as EQA and EQB
only when ENSMB is de-asserted (low). Each of the four A-channels
have the same level unless controlled by the SMBus control registers.
Likewise, each of the four B-channels have the same level unless
controlled by the SMBus control registers.
When the device operates in Slave or Master Mode, the SMBus registers
independently control each lane, and the EQB pin is converted to an
AD3 input. See Table 4.
I, 4-LEVEL,
LVCMOS
VODB[1:0] controls the output amplitude of the B-channels. The pins are
defined as VODB[1:0] only when ENSMB is de-asserted (low). Each of
the four B-channels have the same level unless controlled by the SMBus
control registers. When the device operates in Slave or Master Mode, the
SMBus registers provide independent control of each lane, and
VODB[1:0] pins are converted to AD0, AD1 inputs. See Table 5.
ENSMB = 0 (PIN MODE)
EQA
EQB
VODB0
VODB1
20
46
53
54
VODA0
VODA1
49
50
I, 4-LEVEL,
LVCMOS
VODA[1:0] controls the output amplitude of the A-channels. The pins are
defined as VODA[1:0] only when ENSMB is de-asserted (low). Each of
the four A-channels have the same level unless controlled by the SMBus
control registers. When the device operates in Slave or Master Mode, the
SMBus registers provide independent control of each lane and the
VODA[1:0] pins are converted to SCL and SDA. See Table 5.
AD2
47
I, LVCMOS
Reserved in Pin Mode (ENSMB = 0)
This input must be tied via external 1 kΩ to GND.
SD_TH
26
I, 4-LEVEL,
LVCMOS
Controls the internal Signal Detect Status Threshold value when in Pin
Mode and SMBus Slave Mode. This pin is to be used for system
debugging only, as the signal detect threshold has no impact on the data
path. See Table 3 for more information.
For final designs, input can be left floating, tied via 1 kΩ to VDD (2.5 V
mode) or VIN (3.3 V mode), or tied via 1 kΩ to GND.
RESERVED2
21
I, 4-LEVEL,
LVCMOS
Reserved
Tie via external 1 kΩ to GND (External 1 kΩ to VDD (2.5 V mode) or VIN
(3.3 V mode) is also acceptable).
(3)
When READ_EN is asserted low, the device attempts to load EEPROM. If EEPROM cannot be loaded successfully, for example due to
an invalid or blank hex file, the DS80PCI810 waits indefinitely in an unknown state where SMBus access is not possible. ALL_DONE pin
remains high in this situation.
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SNLS493A – OCTOBER 2014 – REVISED JANUARY 2015
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Pin Functions(1) (continued)
PIN NAME
RESERVED3
PIN NUMBER
19
I/O, TYPE
I, 4-LEVEL,
LVCMOS
DESCRIPTION
Reserved
This input must be tied via external 1 kΩ to GND.
CONTROL PINS — BOTH PIN AND SMBUS MODES (LVCMOS)
The RXDET pin controls the RX detection function. Depending on the
input level, a 50 Ω or >50 kΩ termination to the power rail is enabled.
Keep this input floating for normal PCIe operation.
See Table 2.
RXDET
22
I, 4-LEVEL,
LVCMOS
RESERVED1
23
I, 4-LEVEL,
LVCMOS
Reserved
This input must be left floating.
VDD_SEL
25
I, FLOAT
Controls the internal regulator
Float = 2.5 V mode
Tie to GND = 3.3 V mode
See Figure 31.
PWDN
52
I, LVCMOS
Tie High = Low power - Power Down
Tie to GND = Normal Operation
See Table 2.
ALL_DONE
27
O, LVCMOS
Valid Register Load Status Output
HIGH = External EEPROM load failed or incomplete
LOW = External EEPROM load passed
24
Power
In 3.3 V mode, feed 3.3 V to VIN
In 2.5 V mode, leave floating.
POWER
VIN
VDD
9, 14, 36, 41, 51
Power
Power Supply for CML and Analog Pins
In 2.5 V mode, connect to 2.5 V
In 3.3 V mode, connect 0.1 µF cap to each VDD Pin and GND
See Figure 31 for proper power supply decoupling .
GND
DAP
Power
Ground pad (DAP - die attach pad).
6
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SNLS493A – OCTOBER 2014 – REVISED JANUARY 2015
6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
Supply Voltage (VDD to GND, 2.5 V Mode)
-0.5
+2.75
V
Supply Voltage (VIN to GND, 3.3 V Mode)
-0.5
+4.0
V
LVCMOS Input/Output Voltage
-0.5
+4.0
V
CML Input Voltage
-0.5
VDD + 0.5
V
CML Input Current
-30
+30
mA
Storage temperature, Tstg
-40
125
°C
260
°C
Lead Temperature Range Soldering (4 sec.) (2)
Tsolder
(1)
(2)
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other
conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions
indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Absolute Maximum
Numbers are ensured for a junction temperature range of -40°C to +125°C. Models are validated to Maximum Operating Voltages only.
For soldering specifications: See application note SNOA549.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions. Pins listed as ±4000 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions. Pins listed as ±1000 V may actually have higher performance.
6.3 Handling Ratings
V(ESD)
(1)
(2)
Electrostatic discharge
MIN
MAX
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
-4000
4000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
-1000
1000
UNIT
V
JEDEC document JEP155 states that 4000-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 1000-V CDM allows safe manufacturing with a standard ESD control process.
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
Supply Voltage (2.5 V mode) (1)
2.375
2.5
2.625
V
Supply Voltage (3.3 V mode) (1)
3.0
3.3
3.6
V
Ambient Temperature
-40
+85
°C
SMBus (SDA, SCL)
Supply Noise up to 50 MHz (2)
(1)
(2)
3.6
100
V
mVp-p
DC plus AC power should not exceed these limits.
Allowed supply noise (mVp-p sine wave) under typical conditions.
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6.5 Thermal Information
NJY
THERMAL METRIC (1)
RθJA
Junction-to-ambient thermal resistance
26.6
RθJCtop
Junction-to-case (top) thermal resistance
10.8
RθJB
Junction-to-board thermal resistance
4.4
ψJT
Junction-to-top characterization parameter
0.2
ψJB
Junction-to-board characterization parameter
4.3
RθJCbot
Junction-to-case (bottom) thermal resistance
1.5
(1)
UNIT
54 PINS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.6 Electrical Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER
IDD
VDD
Current Consumption, 2.5 V Mode
EQ = Level 4, VOD = Level 6
RXDET = 1, PWDN = 0
220
280
mA
Current Consumption, 3.3 V Mode
EQ = Level 4, VOD = Level 6
RXDET = 1, PWDN = 0
220
280
mA
Power Down Current Consumption
PWDN = 1
14
27
mA
Integrated LDO Regulator
VIN = 3.0 - 3.6 V
2.5
2.625
V
2.375
LVCMOS / LVTTL DC SPECIFICATIONS
VIH25
High Level Input Voltage
2.5 V Supply Mode
1.7
VDD
V
VIH33
High Level Input Voltage
3.3 V Supply Mode
1.7
VIN
V
VIL
Low Level Input Voltage
0
0.7
V
VOH
High Level Output Voltage
(ALL_DONE pin)
IOH = −4mA
VOL
Low Level Output Voltage
(ALL_DONE pin)
IOL = 4mA
IIH
Input High Current (PWDN pin)
VIN = 3.6 V,
LVCMOS = 3.6 V
IIL
Input Low Current (PWDN pin)
2.0
V
0.4
V
-15
+15
µA
VIN = 3.6 V,
LVCMOS = 0 V
-15
+15
µA
+20
+150
µA
-160
-40
µA
4-LEVEL INPUT DC SPECIFICATIONS
IIH
Input High Current with internal
resistors
(4–level input pin)
VIN = 3.6 V,
LVCMOS = 3.6 V
IIL
Input Low Current with internal
resistors
(4–level input pin)
VIN = 3.6 V,
LVCMOS = 0 V
Voltage Threshold from Pin Mode
Level 0 to R
Voltage Threshold from Pin Mode
Level R to F
VTH
Voltage Threshold from Pin Mode
Level F to 1
Voltage Threshold from Pin Mode
Level F to 1
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1.25
V
2.00
Voltage Threshold from Pin Mode
Level 0 to R
Voltage Threshold from Pin Mode
Level R to F
8
0.50
VDD = 2.5 V (2.5 V supply mode)
Internal LDO Disabled
See Table 1 for details
0.66
VIN = 3.3 V (3.3 V supply mode)
Internal LDO Enabled
See Table 1 for details.
1.65
V
2.64
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SNLS493A – OCTOBER 2014 – REVISED JANUARY 2015
Electrical Characteristics (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
100
120
Ω
50
60
Ω
CML RECEIVER INPUTS (IN_n+, IN_n-)
ZRx-DIFF-DC
Rx DC differential mode impedance
Tested at VDD = 2.5 V
80
ZRx-DC
Rx DC single ended impedance
Tested at VDD = 2.5 V
40
RLRx-DIFF
Rx Differential Input return loss
SDD11 10 MHz
-19
SDD11 2 GHz
-14
SDD11 6-11.1 GHz
-8
dB
RLRx-CM
Rx Common mode return loss
SCC11 0.05 - 5 GHz
-10
dB
VRx-ASSERT-DIFF-PP
Signal detect assert level for active
data signal
SD_TH = F (float),
1010 pattern at 12 Gbps
57
mVp-p
VRx-DEASSERT-DIFF- Signal detect de-assert for inactive
signal level
PP
SD_TH = F (float),
1010 pattern at 12 Gbps
44
mVp-p
SDD22 10 MHz - 2 GHz
-15
SDD22 5.5 GHz
-12
SDD22 11.1 GHz
-10
dB
-8
dB
100
Ω
20
mA
HIGH SPEED OUTPUTS
RLTx-DIFF
Tx Differential return loss
RLTx-CM
Tx Common mode return loss
ZTx-DIFF-DC
DC differential Tx impedance
ITx-SHORT
Transmitter short circuit current limit
VTx-CM-DC-LINE-
Absolute delta of DC common mode
voltage between Tx+ and Tx-
DELTA
VTx-DIFF1-PP
VTx-DIFF2-PP
VTx-DIFF3-PP
(1)
(2)
(3)
SCC22 50 MHz- 2.5 GHz
Total current when output is
shorted to VDD or GND
dB
25
mV
Output Voltage Differential Swing
Differential measurement with
OUT_n+ and OUT_n-,
AC-Coupled and terminated by
50 Ω to GND,
Inputs AC-Coupled,
Measured with 8T Pattern at 12
Gbps (1)
VID = 600 mVp-p
VOD = Level 6 (2) (3)
615
mVp-p
Output Voltage Differential Swing
Differential measurement with
OUT_n+ and OUT_n-,
AC-Coupled and terminated by
50 Ω to GND,
Inputs AC-Coupled,
Measured with 8T Pattern at 12
Gbps (1)
VID = 1000 mVp-p
VOD = Level 6 (2) (3)
950
mVp-p
Output Voltage Differential Swing
Differential measurement with
OUT_n+ and OUT_n-,
AC-Coupled and terminated by
50 Ω to GND,
Inputs AC-Coupled,
Measured with 8T Pattern at 12
Gbps (1)
VID = 1200 mVp-p
VOD = Level 6 (2) (3)
1100
mVp-p
8T pattern is defined as a 1111111100000000'b pattern bit sequence.
ATE measurements for production are tested at DC.
In PCIe applications, the output VOD level is not fixed. It adjusts automatically based on the VID input amplitude level. The output VOD
level set by VODA/B[1:0] depends on the VID level and the frequency content. The DS80PCI810 repeater is designed to be transparent
in this mode, so the Tx-FIR (de-emphasis) is passed to the Rx to support the handshake negotiation link training.
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Electrical Characteristics (continued)
PARAMETER
TPDEQ
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Differential propagation delay
EQ = Level 1 to Level 4
80
ps
VTx-CM-AC-PP
AC common mode voltage
EQ = Level 4, VOD = Level 6,
PRBS-7, 8 Gbps
Measured over >106 bits using a
low pass filter with a -3 dB corner
frequency at 4 GHz (4)
20
mVp-p
VDISABLE-OUT
Tx disable output voltage
Driver disabled via PWDN
1
mVp-p
VTx-IDLE-DIFF-AC-p
Driver enabled, EQ = Level 4,
Tx idle differential peak output voltage
VOD = Level 7 (Max) (5)
8
mV
TTx-IDLE-SET-TO-
Time to transition to idle after
differential signal
VID = 1.0 Vp-p, 1.5 Gbps
0.70
ns
Time to transition to valid differential
signal after idle
VID = 1.0 Vp-p, 1.5 Gbps
0.04
ns
Additive Random Jitter
Evaluation Module (EVM) Only,
FR4,
VID = 800 mVp-p, EQ = Level 1
PRBS15, 12 Gbps
VOD = Level 6
All other channels active (6)
0.36
ps rms
DJE1
Residual deterministic jitter at 6 Gbps
5” Differential Stripline, 5mil trace
width, FR4,
VID = 800 mVp-p,
PRBS15, EQ = Level 2,
VOD = Level 6
0.06
UIp-p
DJE2
Residual deterministic jitter at 12
Gbps
5” Differential Stripline, 5mil trace
width, FR4,
VID = 800 mVp-p,
PRBS15, EQ = Level 2,
VOD = Level 6
0.12
UIp-p
IDLE
TTx-IDLE-TO-DIFFDATA
RJADD
EQUALIZATION
(4)
(5)
(6)
10
Tx Common Mode AC noise decreases at lower levels of EQ gain.
Tested with a valid idle signal on the input with peak differential voltage of 6 mV.
Additive random jitter is given in RMS value by the following equation: RJADD = √[(Output Jitter)2 - (Input Jitter)2]. Typical input jitter for
these measurements is 150 fs rms.
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6.7 Electrical Characteristics — Serial Management Bus Interface
Over recommended operating supply and temperature ranges unless other specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SERIAL BUS INTERFACE DC SPECIFICATIONS
VIL
Data, Clock Input Low Voltage
VIH
Data, Clock Input High Voltage
VOL
Output Low Voltage
VDD
Nominal Bus Voltage
IIH-Pin
Input Leakage Per Device Pin
IIL-Pin
Input Leakage Per Device Pin
SDA or SCL, IOL = 1.25 mA
0.8
V
2.1
3.6
V
0
0.36
V
2.375
3.6
V
+20
+150
µA
-160
-40
µA
(1) (2)
CI
Capacitance for SDA and SCL
See
35 dB at 4
GHz) are expected in the signal path. In contrast to open PCIe systems, a closed system is defined as a PCIe
environment with a limited number of possible Host-to-Endpoint combinations. Due to larger CTLE gain, the
DS80PCI800 is able to compensate insertion loss over longer transmission lines before the repeater. In addition,
the DS80PCI800 is able to produce de-emphasis levels up to -12 dB to support significant trace losses after the
repeater (-15 dB at 4 GHz).
8.1.2 Signal Integrity in PCIe Applications
In PCIe Gen-3 applications, specifications require Rx-Tx link training to establish and optimize signal conditioning
settings at 8 Gbps. In link training, the Rx partner requests a series of FIR coefficients from the Tx partner at
speed. This training sequence is designed to pre-condition the signal path with an optimized link between the
endpoints. Note that there is no link training with Tx FIR coefficients for PCIe Gen-1 (2.5 Gbps) or PCIe Gen-2
(5.0 Gbps) applications.
The DS80PCI810 works to extend the reach possible by using active linear equalization on the channel, boosting
attenuated signals so that they can be more easily recovered at the Rx. The repeater outputs are specially
designed to be transparent to Tx FIR signaling in order to pass information critical for optimal link training to the
Rx. Suggested settings for the A-channels and B-channels are given in Table 10 and Table 11. Further
adjustments to EQx and VODx settings may optimize signal margin on the link for different system applications:
Table 10. Suggested Device Settings in Pin Mode
CHANNEL SETTINGS
PIN MODE
EQx
Level 4
VODx[1:0]
Level 6 (1, 0)
Table 11. Suggested Device Settings in SMBus Modes
CHANNEL SETTINGS
SMBus MODES
EQx
0x03
VODx
110'b
VOD_DB
000'b
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The SMBus Slave Mode code example in Table 12 may be used to program the DS80PCI810 with the
recommended device settings.
Table 12. SMBus Example Sequence
REGISTER
WRITE VALUE
COMMENTS
0x06
0x18
Set SMBus Slave Mode Register Enable.
0x0F
0x03
Set CHB_0 EQ to 0x03.
0x10
0xAE
Set CHB_0 VOD to 110'b.
0x11
0x00
Set CHB_0 VOD_DB to 000'b.
0x16
0x03
Set CHB_1 EQ to 0x03.
0x17
0xAE
Set CHB_1 VOD to 110'b.
0x18
0x00
Set CHB_1 VOD_DB to 000'b.
0x1D
0x03
Set CHB_2 EQ to 0x03.
0x1E
0xAE
Set CHB_2 VOD to 110'b.
0x1F
0x00
Set CHB_2 VOD_DB to 000'b.
0x24
0x03
Set CHB_3 EQ to 0x03.
0x25
0xAE
Set CHB_3 VOD to 110'b.
0x26
0x00
Set CHB_3 VOD_DB to 000'b.
0x2C
0x03
Set CHA_0 EQ to 0x03.
0x2D
0xAE
Set CHA_0 VOD to 110'b.
0x2E
0x00
Set CHA_0 VOD_DB to 000'b.
0x33
0x03
Set CHA_1 EQ to 0x03.
0x34
0xAE
Set CHA_1 VOD to 110'b.
0x35
0x00
Set CHA_1 VOD_DB to 000'b.
0x3A
0x03
Set CHA_2 EQ to 0x03.
0x3B
0xAE
Set CHA_2 VOD to 110'b.
0x3C
0x00
Set CHA_2 VOD_DB to 000'b.
0x41
0x03
Set CHA_3 EQ to 0x03.
0x42
0xAE
Set CHA_3 VOD to 110'b.
0x43
0x00
Set CHA_3 VOD_DB to 000'b.
8.1.3 Rx Detect Functionality in PCIe Applications
In PCIe systems, specifications require the Tx to implement Rx detection in order to determine whether an Rx
endpoint is present. Since the DS80PCI810 is designed for placement between an ASIC Tx and endpoint Rx, the
DS80PCI810 implements automatic polling for valid Rx detection when the RXDET pin is left floating or tied low
via 20 kΩ to GND. If 50 Ω impedances are seen on both positive and negative outputs of a DS80PCI810
channel, the Rx detect state machine asserts Rx detection, and a 50 Ω termination to VDD is provided at the
respective channel's positive and negative input. For open PCIe systems where users may swap multiple cards
in and out of a given PCIe slot, it is recommended to keep the RXDET pin floating. For closed systems where an
endpoint Rx is present in a PCIe slot at all times, the RXDET pin may be left floating or tied high via 1 kΩ to VDD
(2.5 V mode) or VIN (3.3 V mode).
For more details about DS80PCI810 Rx detection, refer to Table 2.
8.2 Typical Applications
8.2.1 Generic High Speed Repeater
The DS80PCI810 extends PCB and cable reach in multiple applications by using active linear equalization. The
high linearity of this device aids specifically in protocols requiring link training and can be used in line cards,
backplanes, and motherboards, thereby improving margin and overall eye performance. The capability of the
repeater can be explored across a range of data rates and ASIC-to-link-partner signaling, as shown in the
following two test setup connections.
42
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Typical Applications (continued)
Pattern
Generator
TL
Lossy Channel
VOD = 1.0 Vp-p,
DE = 0 dB
PRBS15
IN
DS80PCI810
Scope
BW = 60 GHz
OUT
Figure 9. Test Setup Connections Diagram
Pattern
Generator
VOD = 1.0 Vp-p,
DE = -6 dB
PRBS15
TL1
Lossy Channel
IN
DS80PCI810
OUT
TL2
Lossy Channel
Scope
BW = 60 GHz
Figure 10. Test Setup Connections Diagram
8.2.1.1 Design Requirements
As with any high speed design, there are many factors that influence the overall performance. Below are a list of
critical areas for consideration and study during design.
• Use 100 Ω impedance traces. Generally these are very loosely coupled to ease routing length differences.
• Place AC-coupling capacitors near to the receiver end of each channel segment to minimize reflections.
• The maximum body size for AC-coupling capacitors is 0402.
• Back-drill connector vias and signal vias to minimize stub length.
• Use reference plane vias to ensure a low inductance path for the return current.
8.2.1.2 Detailed Design Procedure
The DS80PCI810 is designed to be placed at an offset location with respect to the overall channel attenuation. In
order to optimize performance, the repeater requires tuning to extend the reach of the cable or trace length while
also recovering a solid eye opening. To tune the repeater, the settings mentioned in Table 10 (for Pin Mode) and
Table 11 (for SMBus Modes) are recommended as a default starting point for most applications. Once these
settings are configured, additional tuning of the EQ and, to a lesser extent, VOD may be required to optimize the
repeater performance for each specific application environment.
Examples of the repeater performance as a generic high speed datapath repeater are illustrated in the
performance curves in the next section.
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Typical Applications (continued)
8.2.1.3 Application Performance Plots
CML Serializer Data Throughput
(106.3 mV/DIV)
CML Serializer Data Throughput
(93.7 mV/DIV)
8.2.1.3.1 Pre-Channel Only Setup
Time (20.83 ps/DIV)
DS80PCI810 Settings: EQA = Level 2, VODA = Level 6
TJ (1.0E-12) = 13.6 ps
Figure 12. TL = 5 Inch 5–Mil FR4 Trace,
DS80PCI810 CHA_0, 8 Gbps
CML Serializer Data Throughput
(109.75 mV/DIV)
CML Serializer Data Throughput
(91.9 mV/DIV)
No Repeater Used
TJ (1.0E-12) = 21.6 ps
Figure 11. TL = 5 Inch 5–Mil FR4 Trace,
No Repeater, 8 Gbps
Time (20.83 ps/DIV)
Time (20.83 ps/DIV)
Time (20.83 ps/DIV)
No Repeater Used
TJ (1.0E-12) = Not Available Due to Closed Eye
Figure 15. TL = 20 Inch 5–Mil FR4 Trace,
No Repeater, 8 Gbps
44
DS80PCI810 Settings: EQA = Level 3, VODA = Level 6
TJ (1.0E-12) = 18.1 ps
Figure 14. TL= 10 Inch 5–Mil FR4 Trace,
DS80PCI810 CHA_0, 8 Gbps
CML Serializer Data Throughput
(106.35 mV/DIV)
CML Serializer Data Throughput
(89.35 mV/DIV)
No Repeater Used
TJ (1.0E-12) = 43.7 ps
Figure 13. TL = 10 Inch 5–Mil FR4 Trace,
No Repeater, 8 Gbps
Time (20.83 ps/DIV)
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Time (20.83 ps/DIV)
DS80PCI810 Settings: EQA = Level 4, VODA = Level 6
TJ (1.0E-12) = 35.5 ps
Figure 16. TL = 20 Inch 5–Mil FR4 Trace,
DS80PCI810 CHA_0, 8 Gbps
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CML Serializer Data Throughput
(89.95 mV/DIV)
CML Serializer Data Throughput
(73.25 mV/DIV)
Typical Applications (continued)
Time (20.83 ps/DIV)
No Repeater
TJ (1.0E-12) = Not Available Due to Closed Eye
Figure 17. TL = 5-Meter 30-AWG 100 Ω Twin-Axial Cable,
No Repeater, 8 Gbps
Time (20.83 ps/DIV)
DS80PCI810 Settings: EQA = Level 4, VODA = Level 6
TJ (1.0E-12) = 41.4 ps
Figure 18. TL = 5-Meter 30-AWG 100 Ω Twin-Axial Cable,
DS80PCI810 CHA_0, 8 Gbps
CML Serializer Data Throughput
(63.7 mV/DIV)
CML Serializer Data Throughput
(46.05 mV/DIV)
8.2.1.3.2 Pre-Channel and Post-Channel Setup
Time (20.83 ps/DIV)
No Repeater Used
TJ (1.0E-12) = Not Available Due to Closed Eye
Figure 19. TL1 = 15 Inch 5–Mil FR4 Trace,
TL2 = 10 Inch 5–Mil FR4 Trace,
No Repeater, 8 Gbps
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Time (20.83 ps/DIV)
DS80PCI810 Settings: EQA = Level 4, VODA = Level 6
TJ (1.0E-12) = 33.0 ps
Figure 20. TL1 = 15 Inch 5–Mil FR4 Trace,
TL2 = 10 Inch 5–Mil FR4 Trace,
DS80PCI810 CHA_0, 8 Gbps
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Typical Applications (continued)
8.2.2 PCIe Board Applications (PCIe Gen-3)
The DS80PCI810 can be used to extend trace length on motherboards and line cards in PCIe Gen-3
applications. The high linearity of the DS80PCI810 aids in the link training protocol required by PCIe Gen-3 at 8
Gbps in accordance with PCI-SIG standards. For PCIe Gen-3, preservation of the pre-cursor and post-cursor Tx
FIR presets (P0-P10) is crucial to successful signal transmission from motherboard system root complex to line
card ASIC or Embedded Processor. Below is a typical example of the DS80PCI810 used in a PCIe application:
8
TX
ASIC
or
PCIe EP
Connector
8
RX
DS80PCI810
8
System Board
Root Complex
RX
DS80PCI810
Connector
8
TX
ard
Bo ce
Tra
Figure 21. Typical PCIe Gen-3 Configuration Diagram
8.2.2.1 Design Requirements
As with any high speed design, there are many factors that influence the overall performance. Please reference
Design Requirements in the Generic High Speed Repeater application section for a list of critical areas for
consideration and study during design.
8.2.2.2 Design Procedure
In PCIe Gen-3 applications, there is a large range of flexibility regarding the placement of the DS80PCI810 in the
signal path due to the high linearity of the device. If the PCIe slot must also support lower speeds like PCIe Gen1 (2.5 Gbps) and Gen-2 (5.0 Gbps), it is recommended to place the DS80PCI810 closer to the endpoint Rx.
Once the DS80PCI810 is placed on the signal path, the repeater must be tuned. To tune the repeater, the
settings mentioned in Table 10 (for Pin Mode) and Table 11 (for SMBus Modes) are recommended as a default
starting point for most applications. Once these settings are configured, additional tuning of the EQ and, to a
lesser extent, VOD may be required to optimize the repeater performance to pass link training preset
requirements for PCIe Gen-3.
An example of a test configuration used to evaluate the DS80PCI810 in this application can be seen in
Figure 22. For more information about DS80PCI810 PCIe applications, please refer to application note SNLA227.
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Typical Applications (continued)
PCIe Gen-3
Compliance
Base Board Riser
Scope
Tektronix
DSA71604
Preset Configuration Control
PC Testing
Signal Test 3.2.0
Software
FR4 Trace
TL2
FR4 Trace
TL1
PCIe Gen 3.0 (x16 Lane)
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