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DS8921, DS8921A, DS8921AT
SNLS374D – MAY 1998 – REVISED JANUARY 2015
DS8921x Differential Line Driver and Receiver Pair
1 Features
3 Description
•
•
•
•
•
The DS8921, DS8921A, and DS8921AT devices are
differential line driver and receiver pairs designed
specifically for applications meeting the ST506,
ST412, and ESDI disk drive standards. In addition,
these devices meet the requirements of the EIA
standard RS-422.
1
•
•
•
12-ns Typical Propagation Delay
Output Skew: 0.5 ns Typical
Meets the Requirements of EIA Standard RS-422
Complementary Driver Outputs
High Differential or Common-Mode Input Voltage
Ranges of ±7 V
±0.2 V Receiver Sensitivity Over the Input Voltage
Range
Receiver Input Hysteresis: 70 mV Typical
DS8921AT Industrial Temperature Operation:
(−40°C to +85°C)
2 Applications
•
Differential Line Driver and Receiver for:
– ST506 Disk Drive Standard
– ST412 Disk Drive Standard
– ESDI Disk Drive Standard
– RS-422 Interface
The DS8921x receivers offer an input sensitivity of
200 mV over a ±7 V common mode operating range.
Hysteresis is incorporated (typically 70 mV) to
improve noise margin for slowly changing input
waveforms.
The DS8921x drivers are designed to provide
unipolar differential drive to twisted-pair or parallel
wire transmission lines. Complementary outputs are
logically ANDed and provide an output skew of 0.5 ns
(typical) with propagation delays of 12 ns.
The DS8921x devices are designed to be compatible
with TTL and CMOS.
Device Information(1)
PART NUMBER
DS8921
DS8921A
DS8921AT
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm x 3.91 mm
PDIP (8)
9.81 mm x 6.35 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
SPACE
Typical Application Block Diagram
Simplified Functional Block Diagram
RI+
RO
RI-
DO+
DI
DO5.0 V
VCC
GND
0.1 µF
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS8921, DS8921A, DS8921AT
SNLS374D – MAY 1998 – REVISED JANUARY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
3
4
4
4
5
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Electrical Characteristics...........................................
Receiver Switching Characteristics ..........................
Driver Switching Characteristics: Single-Ended
Characteristics ...........................................................
6.7 Driver Switching Characteristics: Differential
Characteristics ...........................................................
6.8 Typical Characteristics ..............................................
7
9
Overview ...................................................................
Functional Block Diagram .........................................
Feature Description...................................................
Device Functional Modes..........................................
8
8
8
8
Application and Implementation .......................... 9
9.1 Application Information.............................................. 9
9.2 Typical Application .................................................... 9
10 Power Supply Recommendations ..................... 12
11 Layout................................................................... 12
11.1 Layout Guidelines ................................................. 12
11.2 Layout Example .................................................... 12
12 Device and Documentation Support ................. 13
5
5
6
Parameter Measurement Information .................. 6
7.1 AC Test Circuits and Switching Diagrams ................ 6
8
8.1
8.2
8.3
8.4
12.1
12.2
12.3
12.4
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
13
13
13
13
13 Mechanical, Packaging, and Orderable
Information ........................................................... 13
Detailed Description .............................................. 8
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (April 2013) to Revision D
•
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
Changes from Revision B (November 2004) to Revision C
•
2
Page
Changed layout of National Data Sheet to TI format. ........................................................................................................... 1
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SNLS374D – MAY 1998 – REVISED JANUARY 2015
5 Pin Configuration and Functions
D, P Package
8 Pins
Top View
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
DIFFERENTIAL SIGNALING I/O
DI
3
I
TTL/CMOS Compatible Driver Input
DO+, DO–
6, 5
O
Inverting and non-inverting differential driver outputs
RI+, RI–
8, 7
I
Inverting and non-inverting differential receiver inputs
2
O
Receiver Output Pin
GND
4
Power
Ground Pin
VCC
1
Power
Supply pin, provide 5-V supply
RO
POWER
6 Specifications
6.1 Absolute Maximum Ratings (1) (2)
MIN
Supply Voltage
−0.5
Driver Input Voltage
Output Voltage
Receiver Output Sink Current
MAX
UNIT
7
V
7
V
5.5
V
50
mA
Receiver Input Voltage
–10
10
V
Differential Input Voltage
–12
12
V
730
mW
Maximum Package Power Dissipation at 25°C: D Package
Maximum Package Power Dissipation at 25°C: P Package
1160
mW
9.3
mW/°C
Derate P Package, above 25°C
5.8
mW/°C
Lead Temperature
260
°C
260
°C
150
°C
165
°C
Derate D Package, above 25°C
(Soldering, 4 sec.)
Maximum Junction Temperature
−65
Storage Temperature, Tstg
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, please contact the Texas Instrument Sales Office/ Distributors for availability and
specifications.
Copyright © 1998–2015, Texas Instruments Incorporated
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SNLS374D – MAY 1998 – REVISED JANUARY 2015
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6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
MAX
4.5
5.5
V
0
70
°C
−40
85
°C
MIN
TYP
MAX
UNIT
+200
mV
Supply Voltage
Temperature (TA): DS8921/DS8921A
Temperature (TA): DS8921AT
UNIT
6.4 Electrical Characteristics
Over operating free-air temperature range unless otherwise noted. (1) (2) (3)
TEST CONDITIONS
RECEIVER
VTH
−7 V ≤ VCM ≤ +7 V
−200
±35
VHYST
−7 V ≤ VCM ≤ +7 V
15
70
RIN
VIN = −7 V, +7 V, (Other Input = GND)
4.0
6.0
VIN = 10 V
IIN
VIN = −10 V
VOH
IOH = −400 μA
VOL
IOL = 8 mA
ISC
VCC = MAX, VOUT = 0 V
mV
kΩ
3.25
mA
−3.25
mA
2.5
V
0.5
−15
−100
V
mA
DRIVER
VIH
2.0
V
VIL
−40
0.8
V
−200
μA
IIL
VCC = MAX, VIN = 0.4 V
IIH
VCC = MAX, VIN = 2.7 V
20
μA
II
VCC = MAX, VIN = 7.0 V
100
μA
VCL
VCC = MIN, IIN = −18 mA
−1.5
V
VOH
VCC = MIN, IOH = −20 mA
VOL
VCC = MIN, IOL = +20 mA
0.5
V
IOFF
VCC = 0V, V OUT = 5.5 V
100
μA
0.4
V
2.5
|VT| – |VT|
VT
2.0
|VOS – VOS|
ISC
V
V
0.4
VCC = MAX, VOUT = 0 V
−30
V
−150
mA
35
mA
DRIVER AND RECEIVER
ICC
(1)
(2)
(3)
4
VCC = MAX, VOUT = Logic 0
All currents into device pins are shown as positive values; all currents out of the device are shown as negative; all voltages are
referenced to ground unless otherwise specified. All values shown as max or min are classified on absolute value basis.
All typical values are VCC = 5 V, TA = 25°C.
Only one output at a time should be shorted.
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SNLS374D – MAY 1998 – REVISED JANUARY 2015
6.5 Receiver Switching Characteristics
TEST CONDITIONS
tpLH
MIN
CL = 30 pF
TYP
MAX
8921
MAX
8921A
MAX
8921AT
14
22.5
20
20
ns
14
22.5
20
20
ns
0.5
5
3.5
5
ns
TYP
MAX
8921
MAX
8921A
MAX
8921AT
10
15
15
15
ns
10
15
15
15
ns
5
8
8
9.5
ns
5
8
8
9.5
ns
1
5
3.5
3.5
ns
TYP
MAX
8921
MAX
8921A
MAX
8921AT
10
15
15
15
ns
10
15
15
15
ns
0.5
6
2.75
2.75
ns
UNIT
(Figure 3 and Figure 4)
tpHL
CL = 30 pF
(Figure 3 and Figure 4)
|tpLH–t pHL|
CL = 30 pF
(Figure 3 and Figure 4)
6.6 Driver Switching Characteristics: Single-Ended Characteristics
TEST CONDITIONS
tpLH
MIN
CL = 30 pF
UNIT
(Figure 5 and Figure 6)
tpHL
CL = 30 pF
(Figure 5 and Figure 6)
tTLH
CL = 30 pF
(Figure 9 and Figure 10)
tTHL
CL = 30 pF
(Figure 9 and Figure 10)
Skew
CL = 30 pF (1)
(Figure 5 and Figure 6)
(1)
Difference between complementary outputs at the 50% point.
6.7 Driver Switching Characteristics: Differential Characteristics (1)
TEST CONDITIONS
tpLH
MIN
CL = 30 pF
UNIT
(Figure 5, Figure 7, and Figure 8)
tpHL
CL = 30 pF
(Figure 5, Figure 7, and Figure 8)
|tpLH–t pHL|
CL = 30 pF
(Figure 5, Figure 7, and Figure 8)
(1)
Differential Delays are defined as calculated results from single ended rise and fall time measurements. This approach in establishing
AC performance specifications has been taken due to limitations of available Automatic Test Equipment (ATE). The calculated ATE
results assume a linear transition between measurement points and are a result of the following equations:
Tcr = Crossing Point Tra, Trb, Tfa and T fb are time measurements with respect to the input. See Figure 8.
Copyright © 1998–2015, Texas Instruments Incorporated
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Where:
5
DS8921, DS8921A, DS8921AT
SNLS374D – MAY 1998 – REVISED JANUARY 2015
www.ti.com
6.8 Typical Characteristics
Test Setup: Figure 5. Data Rate, Test Pattern: 2 Mbps, 1010 Pattern. T: 25°C
5.2
5.8
T(THL)
High to Low Transition Time (ns)
Low to High Transition Time (ns)
T(TLH)
5.0
4.8
4.6
5.6
5.4
5.2
4.4
4.5
4.6
4.7
4.8
4.9
5.0
5.1
5.2
5.3
5.4
Supply Voltage (V)
5.5
4.5
4.6
4.7
Figure 1. Typical Driver Output Low to High Transition Time
vs Supply Voltage
4.8
4.9
5.0
5.1
Supply Voltage (V)
C004
5.2
5.3
5.4
5.5
C005
Figure 2. Typical Driver Output High to Low Transition Time
vs Supply Voltage
7 Parameter Measurement Information
7.1 AC Test Circuits and Switching Diagrams
Figure 3. Test Circuit for Receiver Output
Figure 4. Receiver Propagation Delay
C2
D
C1
R1
C3
NOTE:R1= 100 Ohms, C1 = C2 = C3 = 30 pF
Figure 5. Driver Test Circuit
6
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SNLS374D – MAY 1998 – REVISED JANUARY 2015
AC Test Circuits and Switching Diagrams (continued)
Figure 6. Driver Single-Ended Propagation Delay
Figure 7. Driver Differential Propagation Delay
Figure 8. Driver Delay ATE Testing
Figure 9. Driver Output Transition Time
Figure 10. Driver Output Transition Time
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DS8921, DS8921A, DS8921AT
SNLS374D – MAY 1998 – REVISED JANUARY 2015
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8 Detailed Description
8.1 Overview
The DS8921x devices are each a differential line driver and receiver pair in a single package. The devices are
designed specifically for ST506, ST412, and ESDI disk drive standards, as well as RS-422 interface applications.
The DS8921 and DS8921A are rated at a commercial temperature range of 0°C to 70°C, whereas the
DS8921AT is rated at an extended temperature range of -40°C to +85°C.
8.2 Functional Block Diagram
RI+
RO
RI-
DO+
DI
DO5.0 V
VCC
GND
0.1 µF
8.3 Feature Description
The DS8921x devices each contain a differential driver and receiver.
The driver converts a TTL or CMOS input to complementary outputs that provide differential drive to a twistedpair or parallel wire transmission line. The receiver converts the differential signals at its input pins to a TTL
output. The receiver offers an input sensitivity of ±200 mV and supports a common-mode input voltage of ±7 V.
8.4 Device Functional Modes
Table 1. Function Table
RECEIVER
INPUT
OUTPUT
INPUT
RI+, RI-
RO
DI
DO+
DO-
1
1
1
0
0
0
0
1
VID (1) ≥ VTH (MAX)
VID
(1)
≤ VTH (MIN)
Open
(1)
8
DRIVER
OUTPUT
1
VID is the input differential voltage between RI+ and RI–.
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SNLS374D – MAY 1998 – REVISED JANUARY 2015
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The DS8921 is a differential line driver and receiver pair in a single package, designed for applications for the
ST506, ST412, and ESDI Disk Drive Standards. The DS8921 is compatible to EIA RS-422 signaling standards,
supporting 200-mV input sensitivity across a ±7-V common mode operating range. This transceiver is intended
for driving differential signal across long transmission lines and translating received differential signals into their
CMOS/TTL single-ended equivalence. The DS8921 transmits and reproduces received data in communications
links where ground reference difference, or noisy environment are common.
9.2 Typical Application
Figure 11 shows a typical implementation of the DS8921x device in a ST506 and ST412 disk drive application.
The differential outputs of the driver are connected to a twisted-pair transmission line, carrying data from the
driver to the differential receiver at the other end of the cable. A differential termination resistor should be
connected across the input pins of the receiver.
Figure 11. ST506 and ST412 Application
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SNLS374D – MAY 1998 – REVISED JANUARY 2015
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Typical Application (continued)
9.2.1 Design Requirements
• Apply TTL or LVCMOS signal to driver input at DI
• Transmit complementary outputs at DO+ and DO• Receive complimentary input signals at RI+ and RI• Receive TTL output signal at RO
• Use controlled-impedance transmission lines such as printed circuit board traces, twisted-pair wires or parallel
wire cable
• Place terminating resistor at the far end of the differential pair
9.2.2 Detailed Design Procedure
• Connect VCC and GND pins to the power and ground planes of the printed circuit board, with 0.1-uF bypass
capacitor
• Use TTL/LVCMOS logic levels at DI and RO
• Use controlled-impedance transmission media for the differential signals DI+- and RO+• Place a terminating resistor at the far-end of the differential pair to avoid reflection
• Ensure the received complimentary signals at RO+ and RO- are within the signal threshold of ±200 mV
Data Signal (2 V/DIV)
Data Signal (2 V/DIV)
9.2.3 Application Curves
0V
0V
Time (400 ns/DIV)
10
Time (400 ns/DIV)
2.0 Mbps Single-Ended 1010 Data Pattern
2.0 Mbps Differential Data Pattern
Note: The input for the driver is Figure 12
Figure 12. Driver Single-Ended Input Signal
Figure 13. Driver Differential Output Signal
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Data Signal (2 V/DIV)
Data Signal (2 V/DIV)
Typical Application (continued)
0V
0V
Time (400 ns/DIV)
2.0 Mbps Differential Data Pattern
Figure 14. Receiver Differential Input Signal
Time (400 ns/DIV)
2.0 Mbps Single-Ended 1010 Data Pattern
Note: The input for the receiver is Figure 14
Figure 15. Receiver Single-Ended Output Signal
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DS8921, DS8921A, DS8921AT
SNLS374D – MAY 1998 – REVISED JANUARY 2015
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10 Power Supply Recommendations
TI recommends connecting the supply (VCC) and ground (GND) pins to power planes that are routed on
adjacent layers of the PCB. Additionally, careful attention should be paid to bypassing the supply using a
capacitor. A 0.1-µF bypass capacitor should be connected to the VCC pin such that the capacitor is as close as
possible to the device.
11 Layout
11.1 Layout Guidelines
High-speed interconnects should be treated as transmission lines with a controlled impedance. The differential
interconnect can be a pair of printed-circuit board (PCB) traces, twisted-pair wires, or a parallel wire cable. A
termination resistor should be placed at the differential input, and the resistor value should be approximately the
same as the differential impedance of the transmission line to minimize reflections.
It is preferable to connect the VCC and GND pins to the power and ground planes using plated-through-holes.
Additionally, a 0.1-µF bypass capacitor should be placed close to the VCC pin across VCC and GND.
Place a terminating resistor at the receiving end of the interconnect transmission line, as close as possible to the
input pins of the receiver. The terminating resistor value should be approximately the same as the differential pair
impedance to minimize reflection, and the transmission line should have a controlled impedance with minimum
impedance discontinuities.
The input and output differential signals of the device should have traces that are routed exclusively on one layer
of the board, and the differential pairs should also be routed away from other differential pairs in order to
minimize crosstalk between transmission lines. Additionally, the differential pairs should have a controlled
impedance with minimum impedance discontinuities and be terminated with a resistor that is closely matched to
the differential pair impedance in order to minimize transmission line reflections. The differential pairs should be
routed with uniform trace width and spacing to minimize impedance mismatch.
11.2 Layout Example
Via to GND
Plane
Via to VCC
Plane
1
5
RX Differential Pair
Bypass Capacitor
Termination
Resistor
6
2
DS8921/DS8921A/DS8921AT
3
7
TX Differential Pair
Via to GND
Plane
4
8
Figure 16. DS8921 Example Layout
12
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SNLS374D – MAY 1998 – REVISED JANUARY 2015
12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
DS8921
Click here
Click here
Click here
Click here
Click here
DS8921A
Click here
Click here
Click here
Click here
Click here
DS8921AT
Click here
Click here
Click here
Click here
Click here
12.2 Trademarks
All trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
DS8921AM/NOPB
ACTIVE
SOIC
D
8
95
RoHS & Green
SN
Level-1-260C-UNLIM
0 to 70
DS89
21AM
DS8921AMX/NOPB
ACTIVE
SOIC
D
8
2500
RoHS & Green
SN
Level-1-260C-UNLIM
0 to 70
DS89
21AM
DS8921ATM/NOPB
ACTIVE
SOIC
D
8
95
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
DS892
1ATM
DS8921ATMX/NOPB
ACTIVE
SOIC
D
8
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
DS892
1ATM
DS8921M/NOPB
ACTIVE
SOIC
D
8
95
RoHS & Green
SN
Level-1-260C-UNLIM
0 to 70
DS892
1M
DS8921MX/NOPB
ACTIVE
SOIC
D
8
2500
RoHS & Green
SN
Level-1-260C-UNLIM
0 to 70
DS892
1M
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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