DS90C185SQE/NOPB

DS90C185 www.ti.com SNLS402D – FEBRUARY 2012 – REVISED FEBRUARY 2013 DS90C185 Low Power 1.8V FPD-Link (LVDS) Serializer Check for Samples: DS90C185 FEATURES DESCRIPTION • • The DS90C185 is a low-power serializer for portable battery-powered applications that reduces the size of the RGB interface between the host GPU and the display. 1 2 • • • • • • • Typical power 50 mW at 75-MHz pclk Drives up to 1400x1050 at 60-Hz (SXGA+) Displays 2.94 Gbps of throughput Two operating modes: 24-bit and 18-bit RGB 25- to 105-MHz Pixel Clock support Single 1.8-V Supply Sleep Mode Spread Spectrum Clock compatibility Small 6mm x 6mm x 0.8mm WQFN package 24-bit RGB plus three video control signals are serialized and translated to LVDS-compatible levels and sent as a 4 data + clock (4D+C) reduced-width LVDS compatible interface. The LVDS Interface is compatible with FPD-Link (1) deserializers and many LVDS based displays. These interfaces are commonly supported in LCD modules with “LVDS” or FPD-Link / FlatLink single-pixel input interfaces. Displays up to 1400x1050 at 60 fps are supported with 24-bpp color depth. 18 bpp may also be supported by a dedicated mode with a 3D+C output. Power dissipation is minimized by the full LVCMOS design and 1.8-V powered core and VDDIO rails. APPLICATIONS • • • • eBooks Media Tablet Devices Netbooks Portable Display Monitors The DS90C185 is offered in the small 48-pin WQFN package and features single 1.8-V supply operation for minimum power dissipation (50 mW typ). System Diagram 24-bit RGB 4 Control Clock 1.8V LVCMOS GPU R7-R0 G7-G0 1.8V DS90C185 FPD-Link SERIALIZER LVDS0+/- FPD-Link 4D+C LVDS DISPLAY MODULE LVDS1+/LVDS2+/- SXGA+ Resolution LVDSC+/B7-B0 LVDS3+/- TCON w/ LVDS Interface HSync VSync DE GPO/CNTL(L/R) CLK PDB 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012–2013, Texas Instruments Incorporated DS90C185 SNLS402D – FEBRUARY 2012 – REVISED FEBRUARY 2013 www.ti.com Functional Block Diagram LVCMOS PARALLEL TO LVDS LVCMOS INPUTS RED GREEN BLUE D0 ± D27 HS VS DE CNTRL (L/R) DATA (LVDS) PLL CLK CLOCK (LVDS) PDB 18B_Mode VOD_SEL RFB DS90C185 - SERIALIZER 2 VDD D8 D7 D6 D5 D4 D3 D2 D1 VOD_SEL D0 PDB 48 47 46 45 44 43 42 41 40 39 38 37 Connection Diagram D9 1 36 TxOUT0- D10 2 35 TxOUT0+ D11 3 34 TxOUT1- D12 4 33 TxOUT1+ D13 5 32 TxOUT2- CLK 6 31 TxOUT2+ D14 7 30 TxCLKOUT- D15 8 29 TxCLKOUT+ D16 9 28 TxOUT3- D17 10 27 TxOUT3+ D18 11 26 18B_MODE D19 12 25 VDDTX DS90C185SQ TOP VIEW DAP = GND 15 16 17 18 19 20 21 22 23 GND D21 D22 D23 D24 D25 D26 D27 RFB 24 14 D20 Submit Documentation Feedback GND 13 VDDPLL (Not to scale) Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: DS90C185 DS90C185 www.ti.com SNLS402D – FEBRUARY 2012 – REVISED FEBRUARY 2013 Table 1. DS90C185 Pin Descriptions Pin Name I/O No. Description 1.8 V LVCMOS VIDEO INPUTS D27-D21, D20, D19-D14, D13-D9, D8-D1, D0 I 22-16, 14, 12-7, 5-1, 47-40, 38 CLK I 6 TxOUT0 –/+, TxOUT1 –/+, TxOUT2 –/+, TxOUT3 –/+, O 36, 34, 32, 28, TxCLK OUT -/+ O 30, 29 Data input pins. This includes: 8 Red, 8 Green, 8 Blue, and 3 video control lines and a general purpose or L/R control bit. Includes pull down. Clock input. Includes pull down. LVDS VIDEO OUTPUTS 35 33 31 27 LVDS Output Data — Expects 100 Ω DC load. LVDS Output Clock — Expects 100 Ω DC load. 1.8 V LVCMOS CONTROL INPUTS R_FB I 23 LVCMOS Ievel programmable strobe select 1 = Rising Edge Clock 0 = Falling Edge Clock — default Includes pull down. 18B_Mode I 26 Mode Configuration Input 1 = 3D+C (18 bit RGB mode) 0 = 4D+C (24 bit RGB mode) — default Includes pull down. VOD_SEL I 39 VOD Select Input 0 = Reduced VOD (lower power) 1 = Normal VOD — default Includes pull down. PDB I 37 Power Down Bar(Sleep) Input 1 = ACTIVE 0 = Sleep State (low power idle) — default Includes pull down. VDD P 48 Digital power input VDDTX P 25 LVDS driver power input PLL power input POWER and GROUND VDDPLL P 13 GND G 15, 24 DAP G Ground pins Connect DAP to ground plane These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: DS90C185 3 DS90C185 SNLS402D – FEBRUARY 2012 – REVISED FEBRUARY 2013 Absolute Maximum Ratings www.ti.com (1) −0.3V to +2.5V Supply Voltage (VDD) LVCMOS Input Voltage −0.5V to (VDD + 0.3V) LVDS Driver Output Voltage −0.3V to (VDD + 0.3V) LVDS Output Short Circuit Duration Continuous Junction Temperature +150°C Storage Temperature −65°C to +150°C Lead Temperature (Soldering, 4 sec) +260°C Package Derating: θJA 26.6 °C/W above +22°C ESD Ratings HBM >4kV CDM >1.25kV MM (1) >250V “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation. Recommended OperatingConditions Supply Voltage (VDD) Operating Free Air Temperature (TA) Min Nom Max 1.71 1.8 1.89 V −10 +22 +70 °C