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DS90C187
SNLS401C – FEBRUARY 2012 – REVISED SEPTEMBER 2018
DS90C187 Low Power, 1.8-V Dual Pixel FPD-Link (LVDS) Serializer
1 Features
3 Description
•
The DS90C187 is a low power Serializer for portable
battery powered that reduces the size of the RGB
interface between the host GPU and the Display.
1
•
•
•
•
•
•
•
•
•
•
•
100 mW Typical Power Consumption at 185 MHz
(SIDO Mode)
Drives QXGA and WQXGA Class Displays
Three Operating Modes:
– Single Pixel In, Single Pixel Out (SISO): 105
MHz Maximum
– Single Pixel In, Dual Pixel Out (SIDO): 185
MHz Maximum
– Dual Pixel In, Dual Pixel Out (DIDO): 105MHz
Supports 24-Bit RGB, 48-Bit RGB
Optional low Power Mode Supports 18-Bit RGB,
36-Bit RGB
Supports 3D+C, 4D+C, 6D+C, 6D+2C, 8D+C, and
8D+2C LVDS Configurations
Compatible With FPD-Link Deserializers
Operates Off a Single 1.8-V Supply
Interfaces Directly With 1.8-V LVCMOS
Less Than 1 mW Power Consumption in Sleep
Mode
Spread Spectrum Clock Compatible
Small 7-mm × 7-mm × 0.9-mm 92-Pin Dual Row
VQFN Package
2 Applications
•
•
•
•
Camera Monitor Systems (CMS)
Automotive Head Units
Smart Mirrors
Cluster
The DS90C187 Serializer is designed to support dual
pixel data transmission between a Host and a Flat
Panel Display at resolutions of up to QXGA
(2048x1536) at 60 Hz. The transmitter converts up to
48 bits (Dual Pixel 24-bit color) of 1.8-V LVCMOS
data into two channels of 4 data + clock (4D+C)
reduced width interface LVDS compatible data
streams.
DS90C187 supports 3 modes of operation.
• In single pixel mode in/out mode, the device can
drive up to SXGA+ (1400x1050) at 60 Hz. In this
mode, the device converts one bank of 24-bit
RGB data to a one channel 4D+C LVDS data
stream.
• In single pixel in / dual pixel out mode, the device
can drive up to WUXGA+ (1920x1440) at 60 Hz.
In this configuration, the device provides single-todual pixel conversion and converts one bank of
24-bit RGB data into two channels of 4D+C LVDS
streams at half the pixel clock rate.
In dual pixel in / dual pixel out mode, the device can
drive up to QXGA 2048x1536 at 60Hz or up to
QSXGA 2560x2048 at 30Hz. In this mode, the device
converts 2 channels of 24 bit RGB data into 2
channels of 4D+C LVDS streams. For all the modes,
the device supports 18bpp and 24bpp color.
Device Information(1)
PART NUMBER
PACKAGE
DS90C187
BODY SIZE (NOM)
VQFN-MR (92)
7.00 mm × 7.00 mm
(1) For all available packages, see the order addendum at the
end of the data sheet.
Typical Application
1.8 V LVCMOS
(24 bit RGB + HS/VS/DE)
Typical Application
1.8 V LVCMOS
(24 bit RGB + HS/VS/DE)
2 Channels FPD-Link (LVDS)
(4 Data + Clock)
1.8 V
GPU
DS90C187
Single Pixel
R[7:0] G[7:0]
B[7:0]
GPU ± Jacinto 6
Single Pixel
R[7:0] G[7:0]
B[7:0]
DS90C187
L
A
T
C
H
&
LVDS
4D+C
(even pixel)
&
P
2
S
HS
VS
DE
GPO/CNTL (L/R)
PCLK
Display (TCON)
LVDS
4D+C
(odd pixel)
L
A
T
C
H
2 Channels OLDI (LVDS)
(4 Data + Clock)
2 Lanes FPD-Link III
1.8 V
DS90UB947
-Q1 SER
Display (TCON)
DOUT0+
DOUT0-
RIN0+
RIN0-
DOUT1+
DOUT1-
RIN1+
RIN1-
FPD-Link III
Interface
P
2
S
HS
VS
DE
GPO/CNTL (L/R)
PCLK
PLL
PDB
PLL
PDB
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS90C187
SNLS401C – FEBRUARY 2012 – REVISED SEPTEMBER 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
8
1
1
1
2
3
3
5
Absolute Maximum Ratings ..................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Electrical Characteristics........................................... 5
Recommended Input Characteristics........................ 7
Switching Characteristics .......................................... 7
AC Timing Diagrams................................................. 8
Typical Characteristics ............................................ 11
Detailed Description ............................................ 12
8.1 Overview ................................................................. 12
8.2 Functional Block Diagrams ..................................... 12
8.3 Device Functional Modes........................................ 15
8.4 Programming........................................................... 17
9
Application and Implementation ........................ 24
9.1 Application Information............................................ 24
9.2 Typical Application ................................................. 24
10 Power Supply Recommendations ..................... 26
10.1 Power Up Sequence ............................................. 26
10.2 Power Supply Filtering .......................................... 26
11 Layout................................................................... 27
11.1 Layout Guidelines ................................................. 27
11.2 Layout Example .................................................... 28
12 Device and Documentation Support ................. 29
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
29
29
29
29
29
29
13 Mechanical, Packaging, and Orderable
Information ........................................................... 29
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (April 2013) to Revision C
Page
•
Added Device Information table, Device Comparison table, ESD Ratings table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ..... 1
•
Added Start Up / Phase Lock Loop Set Time timing diagram ............................................................................................... 9
•
Added content to the Power Up Sequence section ............................................................................................................. 26
Changes from Revision A (April 2013) to Revision B
•
2
Page
Changed layout of National Data Sheet to TI format ............................................................................................................ 1
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SNLS401C – FEBRUARY 2012 – REVISED SEPTEMBER 2018
5 Description (continued)
The DS90C187 is offered in a small 92 pin dual row VQFN package and features single 1.8 V supply for minimal
power dissipation.
6 Pin Configuration and Functions
A39
OA_0 INA_0
INA_1
INA_2
INA_3
INA_4
INA_5
INA_6
INA_9
INA_7
INA_8
INB_9
A1
INB_10
OA_1 -
OA_2 -
INB_11
OA_2 +
INA_11
INB_12
OA_C INA_12
OA_C +
INA_13
OA_3 +
INB_13
OA_3 -
DS90C187
TOP VIEW
(not to scale)
IN_CLK
INA_14
INB_14
OB_0 OB_0 +
OB_1 OB_1 +
INA_15
DAP = GND
INB_15
OB_2 OB_2 +
INA_16
OB_C -
INB_16
OB_C +
INA_17
INB_17
18B
VDDTX
HS
OB_3 -
RSVD
OB_3 +
B20
B21
GND
MODE0
VDD
MODE1
A27
RFB
INA_27
INB_27
INB_26
INA_26
INA_25
INB_25
INB_24
INA_24
INA_23
INB_23
INB_22
INB_21
GND
B12
VDD
VDDP
A12
RSVD
DE
INA_21
RSVD
INA_22
VS
A13
B31
OA_1 +
INA_10
B11
A38
OA_0 +
A26
B1
N/C
PDB
VODSEL
B32
INB_0
INB_1
INB_2
INB_3
INB_4
INB_5
INB_6
INB_7
B40
INB_8
VDD
GND
A52
NLA Package
92-Pin VQFN-MR
Top View
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DS90C187
SNLS401C – FEBRUARY 2012 – REVISED SEPTEMBER 2018
www.ti.com
DS90C187 Pin Descriptions — Serializer
NAME
PIN NO.
I/O
DESCRIPTION
1.8-V LVCMOS VIDEO INPUTS
INA_[27:21]
INA_[17:9]
NA_[8:0]
B19-B13,
B9-B1,
B40-B32
I
Channel A Data Inputs
Typically consists of 8 Red, 8 Green, 8 Blue and a general purpose or L/R control
bit.
Includes pull down.
INB_[27:21]
INB_[17:14],
INB_[13:9]
INB_[8:0
A23-A17,
A10-A7,
A5-A1,
A50-A42
I
Channel B Data Inputs
Typically consists of 8 Red, 8 Green, 8 Blue and a general purpose or L/R control
bit.
Includes pull down.
HS (INA_18),
VS (INA_19),
DE (INA_20)
B10,
B11
B12
I
Video Control Signal Inputs HS = Horizontal Sync, VS = Vertical SYNC, and DE = Data Enable
A6
I
Pixel Input Clock
Includes pull down.
IN_CLK
1.8-V LVCMOS CONTROL INPUTS
MODE0,
MODE1
B20,
A25
I
Mode Control Input (MODE0)
00 = Single In / Single Out
01 = Single In / Dual Out
10 = Dual In / Dual Out
11 = Reserved
Includes pull down.
RFB
A24
I
Rising / Falling Clock Edge Select Input 0 = Falling Edge, 1 = Rising Edge
Includes pull down.
PDB
A40
I
Power Down (Sleep) Control Input 0 = Sleep (Power Down mode), 1 = device active (enabled)
Includes pull down.
18B
A29
I
18 bit / 24 bit Control Input 0 = 24 bit mode,
1 = 18 bit mode
Includes pull down.
VODSEL
A41
I
VOD Level Select Input 0 = Low swing, 1 = Normal swing
Includes pull down.
N/C
RSVD
A39
I
no connect pin — leave open
A11, A12, A16
I
Reserved - Tie to Ground.
B28,
A35
O
Channel A LVDS Output Clock —
Expects 100 Ω DC load.
B27, B29-B31
A34, A36-A38
O
Channel A LVDS Output Data —
Expects 100 Ω DC load.
B23,
A30
O
Channel B LVDS Output Clock —
Expects 100 Ω DC load.
B21, B24-B26
A28, A16-A33
O
Channel B LVDS Output Data —
Expects 100 Ω DC load.
B22
P
Power supply for LVDS Drivers, 1.8V.
A14, A26, A51
P
Power supply pin for core, 1.8V.
LVDS OUTPUTS
OA_C+
OA_COA_[3:0]+,
OA_[3:0]OB_C+,
OB_COB_[3:0]+,
OB_[3:0]-
POWER AND GROUND
VDDTX
VDD
VDDP
A13
P
Power supply pin for PLL, 1.8V.
GND
A15, A27, A52
G
Ground pins.
DAP
DAP
G
Connect DAP to Ground plane.
4
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SNLS401C – FEBRUARY 2012 – REVISED SEPTEMBER 2018
7 Specifications
7.1 Absolute Maximum Ratings
(1)
See
MIN
MAX
UNIT
Supply Voltage (VCC)
−0.3
2.5
V
LVCMOS Input Voltage
−0.3
VDD + 0.3
V
LVDS Driver Output Voltage
−0.3
3.6
V
150
°C
150
°C
LVDS Output Short-Circuit
Duration
Continuous
Junction Temperature
−65
Storage Temperature (Tstg)
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±8000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1250
Machine model
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. [Following
sentence optional; see the wiki.] Manufacturing with less than 500-V HBM is possible with the necessary precautions. [Following
sentence optional; see the wiki.] Pins listed as ±XXX V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. [Following
sentence optional; see the wiki.] Manufacturing with less than 250-V CDM is possible with the necessary precautions. [Following
sentence optional; see the wiki.] Pins listed as ±YYY V may actually have higher performance.
7.3 Recommended Operating Conditions
Supply Voltage
Operating Free Air
Temperature (TA)
MIN
NOM
MAX
1.71
1.80
1.89
V
−10
+25
+70
°C
80
100
Differential Load Impedance
Supply Noise Voltage
UNIT
120
Ω
1ms of black video data; this allows the DS90C187 to be phase locked, and the display to show black
data first.
6. Start sending true image data.
7. Enable backlight.
Power Down sequence (DS90C187 PDB input initially HIGH):
1. Disable LCD backlight; wait for the minimum time specified in the LCD data sheet for the backlight to go low.
2. Video source output data switch from active video data to black image data (all visible pixel turn black); drive
this for >2 frame times.
3. Set DS90C187 power down pin to PDB = GND.
4. Disable the video output of the video source.
5. Remove power from the LCD panel for lowest system power.
The DS90C187 is highly sensitive to the VDD input. Even small levels on the VDD pin prior to full power up
should be avoided. The user should additionally take care to not drive or pull up the CMOS inputs to the device
prior to device power up so as to ensure proper power on behavior.
10.2 Power Supply Filtering
The DS90C187 has several power supply pins at 1.8 V. It is important that these pins all be connected and
properly bypassed. Bypassing should consist of at least one 0.1μF capacitor placed on each pin, with an
additional 4.7 μF - 22 μF capacitor placed on the PLL supply pin (VDDP). 0.01 μF capacitors are typically
recommended for each pin. Additional filtering including ferrite beads may be necessary for noisy systems. It is
recommended to place a 0 ohm resistor at the bypass capacitors that connect to each power pin to allow for
additional filtering if needed. A large bulk capacitor is recommended at the point of power entry. This is typically
in the 50 μF — 100 μF range.
26
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SNLS401C – FEBRUARY 2012 – REVISED SEPTEMBER 2018
11 Layout
11.1 Layout Guidelines
Circuit board layout and stack-up for the LVDS devices should be designed to provide low-noise power feed to
the device. Good layout practice will also separate high frequency or high-level inputs and outputs to minimize
unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by
using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane capacitance
for the PCB power system with low-inductance parasitics, which has proven especially effective at high
frequencies, and makes the value and placement of external bypass capacitors less critical. This practice is
easier to implement in dense pcbs with many layers and may not be practical in simpler boards. External bypass
capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the
range of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF to 10 uF range. Voltage rating of the
tantalum capacitors should be at least 5X the power supply voltage being used.
Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per
supply pin, locate the smaller value closer to the pin. It is recommended to connect power and ground pins
directly to the power and ground planes with bypass capacitors connected to the plane with vias on both ends of
the capacitor.
A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size
reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of
these external bypass capacitors, usually in the range of 20-30 MHz. To provide effective bypassing, multiple
capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At
high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing
the impedance at high frequency. Some devices provide separate power and ground pins for different portions of
the circuit. This is done to isolate switching noise effects between different sections of the circuit. Separate
planes on the PCB are typically not required. Pin Description tables typically provide guidance on which circuit
blocks are connected to which power pin pairs. In some cases, an external filter many be used to provide clean
power to sensitive circuits such as PLLs.
Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the LVDS
lines to prevent coupling from the LVCMOS lines to the LVDS lines. Closely coupled differential lines of 100
Ohms are typically recommended for LVDS interconnect. The closely coupled lines help to ensure that coupled
noise will appear as common mode and thus is rejected by the receivers. The tightly coupled lines will also
radiate less.
For more information on the VQFN package, refer to the AN-1187 Leadless Leadframe Package (LLP)
application note (SNOA401).
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DS90C187
SNLS401C – FEBRUARY 2012 – REVISED SEPTEMBER 2018
www.ti.com
11.2 Layout Example
Figure 21. Layout Example
28
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SNLS401C – FEBRUARY 2012 – REVISED SEPTEMBER 2018
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see:
• LVDS Owner's Manual (SNLA187)
• AN-1108 Channel-Link PCB and Interconnect Design-In Guidelines (SNLA008)
• Transmission Line RAPIDESIGNER Operation and Applications Guide (SNLA035)
• AN-1187 Leadless Leadframe Package (LLP) (SNOA401)
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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29
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
DS90C187LF/NOPB
ACTIVE
VQFN-MR
NLA
92
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-10 to 70
90C187LF
DS90C187LFE/NOPB
ACTIVE
VQFN-MR
NLA
92
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-10 to 70
90C187LF
DS90C187LFX/NOPB
ACTIVE
VQFN-MR
NLA
92
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-10 to 70
90C187LF
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
